From gerrit at coreboot.org  Tue Sep  1 02:59:34 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Tue, 1 Sep 2015 02:59:34 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: buildgcc: Check
	free disk and warn if its size is too small
References: <Iae988300937018f166ff626b75c3a16bfa757ad9+0@gerrit.coreboot.org>
Message-ID: <Iae988300937018f166ff626b75c3a16bfa757ad9+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11474

-gerrit

commit ce9446d6e0f7377833d769e6cc16f7088749c7a6
Author: zbao <fishbaozi at gmail.com>
Date:   Mon Aug 31 22:58:42 2015 -0400

    buildgcc: Check free disk and warn if its size is too small
    
    We can only warn and can not stop building, because if the user
    saves the temp file the last time, the space might be enough.
    
    3G is a estimated size, which is required when I build i386-elf.
    
    Change-Id: Iae988300937018f166ff626b75c3a16bfa757ad9
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 49e41e5..d25febf 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -338,6 +338,11 @@ GNU General Public License for more details.
 EOF
 }
 
+freedisk() {
+	avail=$(LC_ALL=C eval df -k ./ | sed 1d | awk '{print $4}')
+	test $avail -lt 3145728 && printf "${red}WARNING: There is not enough space.${NC}\n"
+}
+
 build_GMP() {
 	CC="$CC" CFLAGS="-Os" ../${GMP_DIR}/configure --disable-shared --enable-fat --prefix=$TARGETDIR $OPTIONS \
 		|| touch .failed
@@ -583,6 +588,8 @@ case "$PACKAGE" in
 		;;
 esac
 
+freedisk
+
 # Find all the required tools:
 
 TAR=$(searchtool tar) || exit $?


From gerrit at coreboot.org  Tue Sep  1 10:07:36 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 1 Sep 2015 10:07:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: support
	compressed files in cbfstool print
References: <I13c2332702c4a5bec379e1ebda72753e06f8e135+0@gerrit.coreboot.org>
Message-ID: <I13c2332702c4a5bec379e1ebda72753e06f8e135+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11359

-gerrit

commit 272fd40c09ff242ccfed3c8b767d351e18b43c31
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Aug 26 12:13:03 2015 +0200

    cbfstool: support compressed files in cbfstool print
    
    Display compressed and decompressed sizes, as well as the compression
    algorithm used, when a compressed file is encountered.
    
    Change-Id: I13c2332702c4a5bec379e1ebda72753e06f8e135
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/cbfstool/cbfs_image.c | 35 ++++++++++++++++++++++++++++++-----
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index d295058..5e914a4 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -777,11 +777,36 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry,
 	if (!fp)
 		fp = stdout;
 
-	fprintf(fp, "%-30s 0x%-8x %-12s %d\n",
-		*name ? name : "(empty)",
-		cbfs_get_entry_addr(image, entry),
-		get_cbfs_entry_type_name(ntohl(entry->type)),
-		ntohl(entry->len));
+	unsigned int compression = CBFS_COMPRESS_NONE;
+	unsigned int decompressed_size = 0;
+	for (struct cbfs_file_attribute *attr = cbfs_file_first_attr(entry);
+	     attr != NULL;
+	     attr = cbfs_file_next_attr(entry, attr)) {
+		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION) {
+			struct cbfs_file_attr_compression *ac =
+				(struct cbfs_file_attr_compression *)attr;
+			compression = ntohl(ac->compression);
+			decompressed_size = ntohl(ac->decompressed_size);
+		}
+	}
+
+	if (compression == CBFS_COMPRESS_NONE) {
+		fprintf(fp, "%-30s 0x%-8x %-12s %d\n",
+			*name ? name : "(empty)",
+			cbfs_get_entry_addr(image, entry),
+			get_cbfs_entry_type_name(ntohl(entry->type)),
+			ntohl(entry->len));
+	} else {
+		fprintf(fp, "%-30s 0x%-8x %-12s %d (%d after %s decompression)\n",
+			*name ? name : "(empty)",
+			cbfs_get_entry_addr(image, entry),
+			get_cbfs_entry_type_name(ntohl(entry->type)),
+			ntohl(entry->len),
+			decompressed_size,
+			lookup_name_by_type(types_cbfs_compression,
+				compression, "(unknown)")
+			);
+	}
 
 	if (!verbose)
 		return 0;


From gerrit at coreboot.org  Tue Sep  1 10:07:41 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 1 Sep 2015 10:07:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: add
	extended file attributes for cbfs_file
References: <I325965286c44f31abd95df684d340cebb0e68b75+0@gerrit.coreboot.org>
Message-ID: <I325965286c44f31abd95df684d340cebb0e68b75+6@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10934

-gerrit

commit 7280070865781cacce70eaff1f02c7d00e234f2f
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Jul 15 20:49:00 2015 +0200

    cbfstool: add extended file attributes for cbfs_file
    
    cbfs_file_first_attr(struct cbfs_file *) and
    cbfs_file_next_attr(struct cbfs_file *, struct cbfs_file_attribute *)
    help navigate through extended attributes.
    
    cbfs_add_file_attr(header, tag, size) adds a new file attribute to
    header.
    
    Change-Id: I325965286c44f31abd95df684d340cebb0e68b75
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfs.h       | 11 ++++++
 util/cbfstool/cbfs_image.c | 87 +++++++++++++++++++++++++++++++++++++++++++---
 util/cbfstool/cbfs_image.h | 14 ++++++++
 3 files changed, 107 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index 3f80a04..185bdde 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -21,6 +21,10 @@
 
 #include <stdint.h>
 
+/* cbfstool will fail when trying to build a cbfs_file header that's larger
+ * than MAX_CBFS_FILE_HEADER_BUFFER. 1K should give plenty of room. */
+#define MAX_CBFS_FILE_HEADER_BUFFER 1024
+
 /* create a magic number in host-byte order.
  * b3 is the high order byte.
  * in the coreboot tools, we go with the 32-bit
@@ -77,6 +81,7 @@ struct cbfs_file {
 	/* length of file data */
 	uint32_t len;
 	uint32_t type;
+	/* offset to struct cbfs_file_attribute or 0 */
 	uint32_t attributes_offset;
 	/* length of header incl. variable data */
 	uint32_t offset;
@@ -95,6 +100,11 @@ struct cbfs_file_attribute {
 	uint8_t data[0];
 } __PACKED;
 
+/* Depending on how the header was initialized, it may be backed with 0x00 or
+ * 0xff. Support both. */
+#define CBFS_FILE_ATTR_TAG_UNUSED 0
+#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+
 struct cbfs_stage {
 	uint32_t compression;
 	uint64_t entry;
@@ -155,6 +165,7 @@ struct cbfs_payload {
 #define CBFS_COMPONENT_NULL 0xFFFFFFFF
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
+
 /* cbfs_image.c */
 uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value);
 uint32_t get_cbfs_compression(const char *name, uint32_t unknown);
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index e71d598..d295058 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -997,11 +997,8 @@ int cbfs_is_valid_entry(struct cbfs_image *image, struct cbfs_file *entry)
 struct cbfs_file *cbfs_create_file_header(int type,
 			    size_t len, const char *name)
 {
-	// assume that there won't be file names of ~1000 bytes
-	const int bufsize = 1024;
-
-	struct cbfs_file *entry = malloc(bufsize);
-	memset(entry, CBFS_CONTENT_DEFAULT_VALUE, bufsize);
+	struct cbfs_file *entry = malloc(MAX_CBFS_FILE_HEADER_BUFFER);
+	memset(entry, CBFS_CONTENT_DEFAULT_VALUE, MAX_CBFS_FILE_HEADER_BUFFER);
 	memcpy(entry->magic, CBFS_FILE_MAGIC, sizeof(entry->magic));
 	entry->type = htonl(type);
 	entry->len = htonl(len);
@@ -1022,6 +1019,86 @@ int cbfs_create_empty_entry(struct cbfs_file *entry, int type,
 	return 0;
 }
 
+struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file)
+{
+	/* attributes_offset should be 0 when there is no attribute, but all
+	 * values that point into the cbfs_file header are invalid, too. */
+	if (ntohl(file->attributes_offset) <= sizeof(*file))
+		return NULL;
+
+	/* There needs to be enough space for the file header and one
+	 * attribute header for this to make sense. */
+	if (ntohl(file->offset) <=
+		sizeof(*file) + sizeof(struct cbfs_file_attribute))
+		return NULL;
+
+	return (struct cbfs_file_attribute *)
+		(((uint8_t *)file) + ntohl(file->attributes_offset));
+}
+
+struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file,
+	struct cbfs_file_attribute *attr)
+{
+	/* ex falso sequitur quodlibet */
+	if (attr == NULL)
+		return NULL;
+
+	/* Is there enough space for another attribute? */
+	if ((uint8_t *)attr + ntohl(attr->len) +
+		sizeof(struct cbfs_file_attribute) >=
+		(uint8_t *)file + ntohl(file->offset))
+		return NULL;
+
+	struct cbfs_file_attribute *next = (struct cbfs_file_attribute *)
+		(((uint8_t *)attr) + ntohl(attr->len));
+	/* If any, "unused" attributes must come last. */
+	if (ntohl(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED)
+		return NULL;
+	if (ntohl(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED2)
+		return NULL;
+
+	return next;
+}
+
+struct cbfs_file_attribute *cbfs_add_file_attr(struct cbfs_file *header,
+					       uint32_t tag,
+					       uint32_t size)
+{
+	struct cbfs_file_attribute *attr, *next;
+	next = cbfs_file_first_attr(header);
+	do {
+		attr = next;
+		next = cbfs_file_next_attr(header, attr);
+	} while (next != NULL);
+	uint32_t header_size = ntohl(header->offset) + size;
+	if (header_size > MAX_CBFS_FILE_HEADER_BUFFER) {
+		DEBUG("exceeding allocated space for cbfs_file headers");
+		return NULL;
+	}
+	/* attr points to the last valid attribute now.
+	 * If NULL, we have to create the first one. */
+	if (attr == NULL) {
+		/* New attributes start where the header ends.
+		 * header->offset is later set to accomodate the
+		 * additional structure.
+		 * No endianess translation necessary here, because both
+		 * fields are encoded the same way. */
+		header->attributes_offset = header->offset;
+		attr = (struct cbfs_file_attribute *)
+			(((uint8_t *)header) +
+			ntohl(header->attributes_offset));
+	} else {
+		attr = (struct cbfs_file_attribute *)
+			(((uint8_t *)attr) +
+			ntohl(attr->len));
+	}
+	header->offset = htonl(header_size);
+	memset(attr, CBFS_CONTENT_DEFAULT_VALUE, size);
+	attr->tag = htonl(tag);
+	attr->len = htonl(size);
+	return attr;
+}
+
 /* Finds a place to hold whole data in same memory page. */
 static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page)
 {
diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h
index 7a9b484..aea8260 100644
--- a/util/cbfstool/cbfs_image.h
+++ b/util/cbfstool/cbfs_image.h
@@ -170,4 +170,18 @@ int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry,
 
 /* Returns the size of a cbfs file header with no extensions */
 size_t cbfs_calculate_file_header_size(const char *name);
+
+/* Given a cbfs_file, return the first file attribute, or NULL. */
+struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
+
+/* Given a cbfs_file and a cbfs_file_attribute, return the attribute that
+ * follows it, or NULL. */
+struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file,
+	struct cbfs_file_attribute *attr);
+
+/* Adds to header a new extended attribute tagged 'tag', sized 'size'.
+ * Returns pointer to the new attribute, or NULL on error. */
+struct cbfs_file_attribute *cbfs_add_file_attr(struct cbfs_file *header,
+					       uint32_t tag,
+					       uint32_t size);
 #endif


From gerrit at coreboot.org  Tue Sep  1 10:07:48 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 1 Sep 2015 10:07:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: allow
	compression at file header level
References: <I9a00ec99dfc68ffb2771bb4a3cc5ba6ba8a326f4+0@gerrit.coreboot.org>
Message-ID: <I9a00ec99dfc68ffb2771bb4a3cc5ba6ba8a326f4+6@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10935

-gerrit

commit 2161b9e793109bb3879bfe675e536773e3949c6d
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    cbfstool: allow compression at file header level
    
    Currently, compression is only allowed at subheader level (e.g. cbfs_stage,
    cbfs_payload_segment). This change adds compression field to each file's
    header so that any cbfs file can be compressed.
    
    With the necessary additions in coreboot and libpayload, the following sample
    code can load a compressed file:
    
    	const char *name = "foo.bmp";
    	struct cbfs_file *file = cbfs_get_file(media, name);
    	void *dst = malloc(ntohl(file->uncompressed_size));
    	dst = cbfs_get_file_content(media, name, type, file, dst);
    
    cbfs_stage and cbfs_payload_segment continue to support compression at
    subheader level because stages and payloads have to be decompressed to the load
    address, which is stored in the subheader. For these, file level compression
    should be turned off.
    
    Change-Id: I9a00ec99dfc68ffb2771bb4a3cc5ba6ba8a326f4
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfs.h     |  9 +++++++++
 util/cbfstool/cbfstool.c | 40 +++++++++++++++++++++++++++++++++++++---
 2 files changed, 46 insertions(+), 3 deletions(-)

diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index 185bdde..44e3dcd 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -104,6 +104,15 @@ struct cbfs_file_attribute {
  * 0xff. Support both. */
 #define CBFS_FILE_ATTR_TAG_UNUSED 0
 #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
+
+struct cbfs_file_attr_compression {
+	uint32_t tag;
+	uint32_t len;
+	/* whole file compression format. 0 if no compression. */
+	uint32_t compression;
+	uint32_t decompressed_size;
+} __PACKED;
 
 struct cbfs_stage {
 	uint32_t compression;
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 059acbf..a91b600 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -230,6 +230,40 @@ static int cbfs_add_component(const char *filename,
 	return 0;
 }
 
+static int cbfstool_convert_raw(struct buffer *buffer,
+	unused uint32_t *offset, struct cbfs_file *header)
+{
+	char *compressed;
+	int compressed_size;
+
+	comp_func_ptr compress = compression_function(param.compression);
+	if (!compress)
+		return -1;
+	compressed = calloc(buffer->size, 1);
+
+	if (compress(buffer->data, buffer->size,
+		     compressed, &compressed_size)) {
+		WARN("Compression failed - disabled\n");
+	} else {
+		struct cbfs_file_attr_compression *attrs =
+			(struct cbfs_file_attr_compression *)
+			cbfs_add_file_attr(header,
+				CBFS_FILE_ATTR_TAG_COMPRESSION,
+				sizeof(struct cbfs_file_attr_compression));
+		if (attrs == NULL)
+			return -1;
+		attrs->compression = htonl(param.compression);
+		attrs->decompressed_size = htonl(buffer->size);
+
+		free(buffer->data);
+		buffer->data = compressed;
+		buffer->size = compressed_size;
+
+		header->len = htonl(buffer->size);
+	}
+	return 0;
+}
+
 static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset,
 	struct cbfs_file *header)
 {
@@ -301,7 +335,7 @@ static int cbfs_add(void)
 				  param.type,
 				  param.baseaddress,
 				  param.headeroffset,
-				  NULL);
+				  cbfstool_convert_raw);
 }
 
 static int cbfs_add_stage(void)
@@ -747,7 +781,7 @@ static bool cbfs_is_legacy_format(struct buffer *buffer)
 }
 
 static const struct command commands[] = {
-	{"add", "H:r:f:n:t:b:vh?", cbfs_add, true, true},
+	{"add", "H:r:f:n:t:c:b:vh?", cbfs_add, true, true},
 	{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
 									true},
 	{"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true},
@@ -862,7 +896,7 @@ static void usage(char *name)
 	     "  -h               Display this help message\n\n"
 	     "COMMANDs:\n"
 	     " add [-r image,regions] -f FILE -n NAME -t TYPE \\\n"
-	     "        [-b base-address]                                    "
+	     "        [-c compression] [-b base-address]                   "
 			"Add a component\n"
 	     " add-payload [-r image,regions] -f FILE -n NAME \\\n"
 	     "        [-c compression] [-b base-address]                   "


From gerrit at coreboot.org  Tue Sep  1 10:07:54 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 1 Sep 2015 10:07:54 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: factor
	out parsing compression file attributes
References: <I8302bb18c5f797eb0a43ec4e4269790f3d49a896+0@gerrit.coreboot.org>
Message-ID: <I8302bb18c5f797eb0a43ec4e4269790f3d49a896+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11361

-gerrit

commit d4a40cb92ad3b3b60e35a0080019b9cebd92da0b
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Aug 26 12:23:26 2015 +0200

    cbfstool: factor out parsing compression file attributes
    
    cbfstool extract also needs it.
    
    Change-Id: I8302bb18c5f797eb0a43ec4e4269790f3d49a896
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/cbfstool/cbfs_image.c | 33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 5e914a4..619bf0b 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -178,6 +178,26 @@ static void cbfs_decode_payload_segment(struct cbfs_payload_segment *output,
 	assert(seg.size == 0);
 }
 
+static int cbfs_file_get_compression_info(struct cbfs_file *entry,
+	uint32_t *decompressed_size)
+{
+	unsigned int compression = CBFS_COMPRESS_NONE;
+	*decompressed_size = ntohl(entry->len);
+	for (struct cbfs_file_attribute *attr = cbfs_file_first_attr(entry);
+	     attr != NULL;
+	     attr = cbfs_file_next_attr(entry, attr)) {
+		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION) {
+			struct cbfs_file_attr_compression *ac =
+				(struct cbfs_file_attr_compression *)attr;
+			compression = ntohl(ac->compression);
+			if (decompressed_size)
+				*decompressed_size =
+					ntohl(ac->decompressed_size);
+		}
+	}
+	return compression;
+}
+
 void cbfs_get_header(struct cbfs_header *header, void *src)
 {
 	struct buffer outheader;
@@ -777,18 +797,9 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry,
 	if (!fp)
 		fp = stdout;
 
-	unsigned int compression = CBFS_COMPRESS_NONE;
 	unsigned int decompressed_size = 0;
-	for (struct cbfs_file_attribute *attr = cbfs_file_first_attr(entry);
-	     attr != NULL;
-	     attr = cbfs_file_next_attr(entry, attr)) {
-		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION) {
-			struct cbfs_file_attr_compression *ac =
-				(struct cbfs_file_attr_compression *)attr;
-			compression = ntohl(ac->compression);
-			decompressed_size = ntohl(ac->decompressed_size);
-		}
-	}
+	unsigned int compression = cbfs_file_get_compression_info(entry,
+		&decompressed_size);
 
 	if (compression == CBFS_COMPRESS_NONE) {
 		fprintf(fp, "%-30s 0x%-8x %-12s %d\n",


From gerrit at coreboot.org  Tue Sep  1 10:07:58 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 1 Sep 2015 10:07:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: add
	decompression wrappers
References: <I86a071a61fd6c1ef842f8ffe51f12f0cefdaf2fe+0@gerrit.coreboot.org>
Message-ID: <I86a071a61fd6c1ef842f8ffe51f12f0cefdaf2fe+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11362

-gerrit

commit 26fa9cf8684c541fc22f85f3ef1e0f87a07a5342
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Aug 26 12:53:41 2015 +0200

    cbfstool: add decompression wrappers
    
    ... and document the interface.
    
    Change-Id: I86a071a61fd6c1ef842f8ffe51f12f0cefdaf2fe
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/cbfstool/common.h   | 16 +++++++++++++++-
 util/cbfstool/compress.c | 27 +++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h
index 5fb1906..4a97fed 100644
--- a/util/cbfstool/common.h
+++ b/util/cbfstool/common.h
@@ -146,10 +146,24 @@ void buffer_delete(struct buffer *buffer);
 const char *arch_to_string(uint32_t a);
 uint32_t string_to_arch(const char *arch_string);
 
-typedef int (*comp_func_ptr) (char *, int, char *, int *);
+/* Compress in_len bytes from in, storing the result at out, returning the
+ * resulting length in out_len.
+ * Returns 0 on error,
+ *         != 0 otherwise, depending on the compressing function.
+ */
+typedef int (*comp_func_ptr) (char *in, int in_len, char *out, int *out_len);
+
+/* Decompress in_len bytes from in, storing the result at out, up to out_len
+ * bytes.
+ * Returns 0 on error,
+ *         != 0 otherwise, depending on the decompressing function.
+ */
+typedef int (*decomp_func_ptr) (char *in, int in_len, char *out, int out_len);
+
 enum comp_algo { CBFS_COMPRESS_NONE = 0, CBFS_COMPRESS_LZMA = 1 };
 
 comp_func_ptr compression_function(enum comp_algo algo);
+decomp_func_ptr decompression_function(enum comp_algo algo);
 
 uint64_t intfiletype(const char *name);
 
diff --git a/util/cbfstool/compress.c b/util/cbfstool/compress.c
index ab94b35..2bde7df 100644
--- a/util/cbfstool/compress.c
+++ b/util/cbfstool/compress.c
@@ -31,6 +31,10 @@ static int lzma_compress(char *in, int in_len, char *out, int *out_len)
 	return do_lzma_compress(in, in_len, out, out_len);
 }
 
+static int lzma_decompress(char *in, int in_len, char *out, unused int out_len)
+{
+	return do_lzma_uncompress(out, out_len, in, in_len);
+}
 static int none_compress(char *in, int in_len, char *out, int *out_len)
 {
 	memcpy(out, in, in_len);
@@ -38,6 +42,12 @@ static int none_compress(char *in, int in_len, char *out, int *out_len)
 	return 0;
 }
 
+static int none_decompress(char *in, int in_len, char *out, unused int out_len)
+{
+	memcpy(out, in, in_len);
+	return 0;
+}
+
 comp_func_ptr compression_function(enum comp_algo algo)
 {
 	comp_func_ptr compress;
@@ -54,3 +64,20 @@ comp_func_ptr compression_function(enum comp_algo algo)
 	}
 	return compress;
 }
+
+decomp_func_ptr decompression_function(enum comp_algo algo)
+{
+	decomp_func_ptr decompress;
+	switch (algo) {
+	case CBFS_COMPRESS_NONE:
+		decompress = none_decompress;
+		break;
+	case CBFS_COMPRESS_LZMA:
+		decompress = lzma_decompress;
+		break;
+	default:
+		ERROR("Unknown compression algorithm %d!\n", algo);
+		return NULL;
+	}
+	return decompress;
+}


From gerrit at coreboot.org  Tue Sep  1 10:08:04 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 1 Sep 2015 10:08:04 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool:
	implement decompression support for cbfstool extract
References: <I5142b03d3c3e028eeb179f225848f762186f94a8+0@gerrit.coreboot.org>
Message-ID: <I5142b03d3c3e028eeb179f225848f762186f94a8+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11363

-gerrit

commit 570e88adf51cba30d594897495db4e3b3d6657b0
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Aug 26 13:01:10 2015 +0200

    cbfstool: implement decompression support for cbfstool extract
    
    Change-Id: I5142b03d3c3e028eeb179f225848f762186f94a8
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/cbfstool/cbfs_image.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 619bf0b..c40bd66 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -661,9 +661,20 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name,
 		ERROR("File not found: %s\n", entry_name);
 		return -1;
 	}
+
+	unsigned int decompressed_size = 0;
+	unsigned int compression = cbfs_file_get_compression_info(entry,
+		&decompressed_size);
+
+	decomp_func_ptr decompress = decompression_function(compression);
+	if (!decompress) {
+		ERROR("looking up decompression routine failed\n");
+		return -1;
+	}
+
 	LOG("Found file %.30s at 0x%x, type %.12s, size %d\n",
 	    entry_name, cbfs_get_entry_addr(image, entry),
-	    get_cbfs_entry_type_name(ntohl(entry->type)), ntohl(entry->len));
+	    get_cbfs_entry_type_name(ntohl(entry->type)), decompressed_size);
 
 	if (ntohl(entry->type) == CBFS_COMPONENT_STAGE) {
 		WARN("Stages are extracted in SELF format.\n");
@@ -673,8 +684,13 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name,
 		WARN("Payloads are extracted in SELF format.\n");
 	}
 
-	buffer.data = CBFS_SUBHEADER(entry);
-	buffer.size = ntohl(entry->len);
+	buffer.data = malloc(decompressed_size);
+	buffer.size = decompressed_size;
+	if (decompress(CBFS_SUBHEADER(entry), ntohl(entry->len),
+		buffer.data, buffer.size)) {
+		ERROR("decompression failed for %s\n", entry_name);
+		return -1;
+	}
 	buffer.name = strdup("(cbfs_export_entry)");
 	if (buffer_write_file(&buffer, filename) != 0) {
 		ERROR("Failed to write %s into %s.\n",
@@ -682,6 +698,7 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name,
 		free(buffer.name);
 		return -1;
 	}
+	free(buffer.data);
 	free(buffer.name);
 	INFO("Successfully dumped the file to: %s\n", filename);
 	return 0;


From gerrit at coreboot.org  Tue Sep  1 10:39:28 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 1 Sep 2015 10:39:28 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: guard
	_Static_assert
References: <I4141f4aa23b140d2d1017ca7b4dace5aa7db0c04+0@gerrit.coreboot.org>
Message-ID: <I4141f4aa23b140d2d1017ca7b4dace5aa7db0c04+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11475

-gerrit

commit ee495d9976d8f2dc811e79222cd20851ec34d5bf
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Tue Sep 1 12:37:41 2015 +0200

    cbfstool: guard _Static_assert
    
    This isn't required for correct execution, and doesn't need to be tested
    on every single compiler out there.
    
    Since GCC < 4.5 has no idea about _Static_assert, hide it there. Our
    build tests will make sure that the test is run before changes are
    submitted to master.
    
    Change-Id: I4141f4aa23b140d2d1017ca7b4dace5aa7db0c04
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/cbfstool/cbfs.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index 44e3dcd..d1b97c5 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -88,7 +88,9 @@ struct cbfs_file {
 	char filename[];
 } __PACKED;
 
+#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 405
 _Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch");
+#endif
 
 /* The common fields of extended cbfs file attributes.
    Attributes are expected to start with tag/len, then append their


From gerrit at coreboot.org  Tue Sep  1 11:46:45 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Tue, 1 Sep 2015 11:46:45 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Check
	free disk and warn if its size is too small
References: <Iae988300937018f166ff626b75c3a16bfa757ad9+0@gerrit.coreboot.org>
Message-ID: <Iae988300937018f166ff626b75c3a16bfa757ad9+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11474

-gerrit

commit 2c8f7b9aa6446093b9395dcc763c01a2a3643195
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 1 07:45:41 2015 -0400

    buildgcc: Check free disk and warn if its size is too small
    
    We can only warn but can not stop building, because if the user
    saves the temp file the last time, the space might be enough.
    
    3G is an estimated size, which is required when I build i386-elf.
    
    Change-Id: Iae988300937018f166ff626b75c3a16bfa757ad9
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 49e41e5..ec633ac 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -288,6 +288,11 @@ cleanup()
 	printf "${green}ok${NC}\n"
 }
 
+freedisk() {
+	avail=$(LC_ALL=C eval df -k ./ | sed 1d | awk '{print $4}')
+	test $avail -lt 3145728 && printf "${red}WARNING: There might be not enough space.${NC}\n"
+}
+
 myhelp()
 {
 	printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n"
@@ -583,6 +588,8 @@ case "$PACKAGE" in
 		;;
 esac
 
+freedisk
+
 # Find all the required tools:
 
 TAR=$(searchtool tar) || exit $?


From gerrit at coreboot.org  Tue Sep  1 14:51:12 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 14:51:12 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool: add
	extended file attributes for cbfs_file
References: <I325965286c44f31abd95df684d340cebb0e68b75+0@gerrit.coreboot.org>
Message-ID: <E1ZWmu0-0000TV-7Q@mail.coreboot.org>

the following patch was just integrated into master:
commit 2c61506630b8e76bed93b3a5ac0ab2089376f548
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Jul 15 20:49:00 2015 +0200

    cbfstool: add extended file attributes for cbfs_file
    
    cbfs_file_first_attr(struct cbfs_file *) and
    cbfs_file_next_attr(struct cbfs_file *, struct cbfs_file_attribute *)
    help navigate through extended attributes.
    
    cbfs_add_file_attr(header, tag, size) adds a new file attribute to
    header.
    
    Change-Id: I325965286c44f31abd95df684d340cebb0e68b75
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/10934
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/10934 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 14:51:24 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 14:51:24 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	allow compression at file header level
References: <I9a00ec99dfc68ffb2771bb4a3cc5ba6ba8a326f4+0@gerrit.coreboot.org>
Message-ID: <E1ZWmuC-0000V8-Qh@mail.coreboot.org>

the following patch was just integrated into master:
commit 8984a637c121d06a408a5f2b3b9d5233a7aa0e6e
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    cbfstool: allow compression at file header level
    
    Currently, compression is only allowed at subheader level (e.g. cbfs_stage,
    cbfs_payload_segment). This change adds compression field to each file's
    header so that any cbfs file can be compressed.
    
    With the necessary additions in coreboot and libpayload, the following sample
    code can load a compressed file:
    
    	const char *name = "foo.bmp";
    	struct cbfs_file *file = cbfs_get_file(media, name);
    	void *dst = malloc(ntohl(file->uncompressed_size));
    	dst = cbfs_get_file_content(media, name, type, file, dst);
    
    cbfs_stage and cbfs_payload_segment continue to support compression at
    subheader level because stages and payloads have to be decompressed to the load
    address, which is stored in the subheader. For these, file level compression
    should be turned off.
    
    Change-Id: I9a00ec99dfc68ffb2771bb4a3cc5ba6ba8a326f4
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/10935
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/10935 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 14:51:36 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 14:51:36 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	support compressed files in cbfstool print
References: <I13c2332702c4a5bec379e1ebda72753e06f8e135+0@gerrit.coreboot.org>
Message-ID: <E1ZWmuO-0000Xu-5p@mail.coreboot.org>

the following patch was just integrated into master:
commit c82725c5b912a695b4582b34253029552932de69
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Aug 26 12:13:03 2015 +0200

    cbfstool: support compressed files in cbfstool print
    
    Display compressed and decompressed sizes, as well as the compression
    algorithm used, when a compressed file is encountered.
    
    Change-Id: I13c2332702c4a5bec379e1ebda72753e06f8e135
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/11359
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11359 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 14:51:48 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 14:51:48 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	factor out parsing compression file attributes
References: <I8302bb18c5f797eb0a43ec4e4269790f3d49a896+0@gerrit.coreboot.org>
Message-ID: <E1ZWmub-0000ao-2W@mail.coreboot.org>

the following patch was just integrated into master:
commit a71c83fa5c3904b562bad939a3103387cd561c80
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Aug 26 12:23:26 2015 +0200

    cbfstool: factor out parsing compression file attributes
    
    cbfstool extract also needs it.
    
    Change-Id: I8302bb18c5f797eb0a43ec4e4269790f3d49a896
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/11361
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11361 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 14:51:57 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 14:51:57 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool: add
	decompression wrappers
References: <I86a071a61fd6c1ef842f8ffe51f12f0cefdaf2fe+0@gerrit.coreboot.org>
Message-ID: <E1ZWmuj-0000e4-0e@mail.coreboot.org>

the following patch was just integrated into master:
commit 61c822900e8907e28ef6dca326835692ae6d18ca
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Aug 26 12:53:41 2015 +0200

    cbfstool: add decompression wrappers
    
    ... and document the interface.
    
    Change-Id: I86a071a61fd6c1ef842f8ffe51f12f0cefdaf2fe
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/11362
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11362 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 14:52:07 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 14:52:07 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	implement decompression support for cbfstool extract
References: <I5142b03d3c3e028eeb179f225848f762186f94a8+0@gerrit.coreboot.org>
Message-ID: <E1ZWmut-0000gs-V2@mail.coreboot.org>

the following patch was just integrated into master:
commit 23aeaff41b94af818191a8668a517abb04a7d516
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Aug 26 13:01:10 2015 +0200

    cbfstool: implement decompression support for cbfstool extract
    
    Change-Id: I5142b03d3c3e028eeb179f225848f762186f94a8
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/11363
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11363 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 14:52:25 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 14:52:25 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	guard _Static_assert
References: <I4141f4aa23b140d2d1017ca7b4dace5aa7db0c04+0@gerrit.coreboot.org>
Message-ID: <E1ZWmvB-0000jM-LK@mail.coreboot.org>

the following patch was just integrated into master:
commit 57c67e5aa52426ee8665bc6e0706ac2abf625a13
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Tue Sep 1 12:37:41 2015 +0200

    cbfstool: guard _Static_assert
    
    This isn't required for correct execution, and doesn't need to be tested
    on every single compiler out there.
    
    Since GCC < 4.5 has no idea about _Static_assert, hide it there. Our
    build tests will make sure that the test is run before changes are
    submitted to master.
    
    Change-Id: I4141f4aa23b140d2d1017ca7b4dace5aa7db0c04
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/11475
    Tested-by: build bot (Jenkins)
    Reviewed-by: Werner Zeh <werner.zeh at siemens.com>
    Reviewed-by: Jonathan A. Kollasch <jakllsch at kollasch.net>


See http://review.coreboot.org/11475 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 16:20:58 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 1 Sep 2015 16:20:58 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	off-by-one on the gcc version that provides _Static_assert
References: <I8212e7921bd9d1436a0ba491cbe6c4d473228956+0@gerrit.coreboot.org>
Message-ID: <I8212e7921bd9d1436a0ba491cbe6c4d473228956+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11476

-gerrit

commit c8aa3222082cf4dc09fe2da6625ede0ca250ad7c
Author: Patrick Georgi <pgeorgi at google.com>
Date:   Tue Sep 1 18:20:20 2015 +0200

    cbfstool: off-by-one on the gcc version that provides _Static_assert
    
    According to https://gcc.gnu.org/gcc-4.6/changes.html it's only in gcc 4.6,
    not 4.5, which I mistakenly believed.
    
    Change-Id: I8212e7921bd9d1436a0ba491cbe6c4d473228956
    Signed-off-by: Patrick Georgi <pgeorgi at google.com>
---
 util/cbfstool/cbfs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index d1b97c5..f738c60 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -88,7 +88,7 @@ struct cbfs_file {
 	char filename[];
 } __PACKED;
 
-#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 405
+#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 406
 _Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch");
 #endif
 


From gerrit at coreboot.org  Tue Sep  1 16:30:28 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 16:30:28 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	off-by-one on the gcc version that provides _Static_assert
References: <I8212e7921bd9d1436a0ba491cbe6c4d473228956+0@gerrit.coreboot.org>
Message-ID: <E1ZWoS4-0004k0-7B@mail.coreboot.org>

the following patch was just integrated into master:
commit ab5754da6639f51ee2aec796f832ce4e3b164f82
Author: Patrick Georgi <pgeorgi at google.com>
Date:   Tue Sep 1 18:20:20 2015 +0200

    cbfstool: off-by-one on the gcc version that provides _Static_assert
    
    According to https://gcc.gnu.org/gcc-4.6/changes.html it's only in gcc 4.6,
    not 4.5, which I mistakenly believed.
    
    Change-Id: I8212e7921bd9d1436a0ba491cbe6c4d473228956
    Signed-off-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-on: http://review.coreboot.org/11476
    Reviewed-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11476 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 17:05:18 2015
From: gerrit at coreboot.org (Duncan Laurie (dlaurie@google.com))
Date: Tue, 1 Sep 2015 17:05:18 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: chromeec: Move
	keyboard backlight code into Chrome EC directory
References: <I3f307bbce1a96cdd1c8224b1e89a63d6fedef738+0@gerrit.coreboot.org>
Message-ID: <I3f307bbce1a96cdd1c8224b1e89a63d6fedef738+1@gerrit.coreboot.org>

Duncan Laurie (dlaurie at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11478

-gerrit

commit 05ff05fecdb4c74e59b4f673a164f75fc03e1cc1
Author: Duncan Laurie <dlaurie at google.com>
Date:   Tue Sep 1 09:47:55 2015 -0700

    chromeec: Move keyboard backlight code into Chrome EC directory
    
    Since more boards are starting to use the EC provided keyboard
    backlight interface move the code to a common place and allow
    it to get included in mainboards.
    
    Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/ec/google/chromeec/acpi/ec.asl                 |  4 +++
 src/ec/google/chromeec/acpi/keyboard_backlight.asl | 42 ++++++++++++++++++++++
 src/mainboard/google/glados/acpi/ec.asl            |  3 ++
 src/mainboard/google/glados/acpi/mainboard.asl     | 18 ----------
 src/mainboard/google/link/acpi/ec.asl              |  5 ++-
 src/mainboard/google/link/acpi/mainboard.asl       | 19 ----------
 src/mainboard/google/samus/acpi/ec.asl             |  3 ++
 src/mainboard/google/samus/acpi/mainboard.asl      | 18 ----------
 8 files changed, 56 insertions(+), 56 deletions(-)

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 746060e..8b4f91d 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -420,6 +420,10 @@ Device (EC0)
 	#include "als.asl"
 #endif
 
+#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
+       #include "keyboard_backlight.asl"
+#endif
+
 #ifdef EC_ENABLE_PD_MCU_DEVICE
 	#include "pd.asl"
 #endif
diff --git a/src/ec/google/chromeec/acpi/keyboard_backlight.asl b/src/ec/google/chromeec/acpi/keyboard_backlight.asl
new file mode 100644
index 0000000..608994e
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/keyboard_backlight.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Scope (\_SB)
+{
+	/*
+	 * Chrome EC Keyboard Backlight interface
+	 */
+	Device (KBLT)
+	{
+		Name (_HID, "GOOG0002")
+		Name (_UID, 1)
+
+		/* Read current backlight value */
+		Method (KBQC, 0, NotSerialized)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.KBLV)
+		}
+
+		/* Write new backlight value */
+		Method (KBCM, 1, NotSerialized)
+		{
+			Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
+		}
+	}
+}
diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl
index 321b2ce..33a7471 100644
--- a/src/mainboard/google/glados/acpi/ec.asl
+++ b/src/mainboard/google/glados/acpi/ec.asl
@@ -21,6 +21,9 @@
 #include <mainboard/google/glados/ec.h>
 #include <mainboard/google/glados/gpio.h>
 
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
index 8e51259..efa7ddd 100644
--- a/src/mainboard/google/glados/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -47,24 +47,6 @@ Scope (\_SB)
 	{
 		Name (_HID, EisaId ("PNP0C0C"))
 	}
-
-	/* Keyboard Backlight interface via EC */
-	Device (KBLT) {
-		Name (_HID, "GOOG0002")
-		Name (_UID, 1)
-
-		/* Read current backlight value */
-		Method (KBQC, 0)
-		{
-			Return (\_SB.PCI0.LPCB.EC0.KBLV)
-		}
-
-		/* Write new backlight value */
-		Method (KBCM, 1)
-		{
-			Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
-		}
-	}
 }
 
 /*
diff --git a/src/mainboard/google/link/acpi/ec.asl b/src/mainboard/google/link/acpi/ec.asl
index d52e0e9..97bec3e 100644
--- a/src/mainboard/google/link/acpi/ec.asl
+++ b/src/mainboard/google/link/acpi/ec.asl
@@ -20,5 +20,8 @@
 /* mainboard configuration */
 #include "../ec.h"
 
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
 /* ACPI code for EC functions */
-#include "../../../../ec/google/chromeec/acpi/ec.asl"
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl
index 3470ff0..63169e5 100644
--- a/src/mainboard/google/link/acpi/mainboard.asl
+++ b/src/mainboard/google/link/acpi/mainboard.asl
@@ -85,23 +85,4 @@ Scope (\_SB) {
 			VendorShort (ADDR) {0x4a}
 		})
 	}
-
-	// Keyboard Backlight interface via EC
-	Device (KBLT) {
-		Name (_HID, EisaId("GGL0002"))
-		Name (_UID, 1)
-		Name (_ADR, 0)
-
-		// Read current backlight value
-		Method (KBQC, 0)
-		{
-			Return (\_SB.PCI0.LPCB.EC0.KBLV)
-		}
-
-		// Write new backlight value
-		Method (KBCM, 1)
-		{
-			Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
-		}
-	}
 }
diff --git a/src/mainboard/google/samus/acpi/ec.asl b/src/mainboard/google/samus/acpi/ec.asl
index 41951d1..1147fcf 100644
--- a/src/mainboard/google/samus/acpi/ec.asl
+++ b/src/mainboard/google/samus/acpi/ec.asl
@@ -23,6 +23,9 @@
 /* Enable EC backed ALS device in ACPI */
 #define EC_ENABLE_ALS_DEVICE
 
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 04f98a9..5a1ac57 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -37,24 +37,6 @@ Scope (\_SB)
 	{
 		Name(_HID, EisaId("PNP0C0C"))
 	}
-
-	// Keyboard Backlight interface via EC
-	Device (KBLT) {
-		Name (_HID, "GOOG0002")
-		Name (_UID, 1)
-
-		// Read current backlight value
-		Method (KBQC, 0)
-		{
-			Return (\_SB.PCI0.LPCB.EC0.KBLV)
-		}
-
-		// Write new backlight value
-		Method (KBCM, 1)
-		{
-			Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
-		}
-	}
 }
 
 /*


From gerrit at coreboot.org  Tue Sep  1 19:59:25 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 1 Sep 2015 19:59:25 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: chromeec: Move
	keyboard backlight code into Chrome EC directory
References: <I3f307bbce1a96cdd1c8224b1e89a63d6fedef738+0@gerrit.coreboot.org>
Message-ID: <E1ZWriH-0008Ly-SR@mail.coreboot.org>

the following patch was just integrated into master:
commit ef549a04c50aaef425b6f21324aa275d2e1318f4
Author: Duncan Laurie <dlaurie at google.com>
Date:   Tue Sep 1 09:47:55 2015 -0700

    chromeec: Move keyboard backlight code into Chrome EC directory
    
    Since more boards are starting to use the EC provided keyboard
    backlight interface move the code to a common place and allow
    it to get included in mainboards.
    
    Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
    Reviewed-on: http://review.coreboot.org/11478
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11478 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  1 22:07:08 2015
From: gerrit at coreboot.org (Alexander Couzens (lynxis@fe80.eu))
Date: Tue, 1 Sep 2015 22:07:08 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: SeaBios: update
	stable release to 1.8.2
References: <Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101+0@gerrit.coreboot.org>
Message-ID: <Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101+1@gerrit.coreboot.org>

Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11479

-gerrit

commit fccfc585276e7f559e78f2abb2461debdcf5e45f
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Wed Sep 2 00:02:56 2015 +0200

    SeaBios: update stable release to 1.8.2
    
    Several USB timing fixes for USB controllers on real hardware
    Initial support for USB3 hubs
    Initial support for SD cards (on QEMU only)
    Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG only)
    SeaVGABIOS improvements:
     Added cursor emulation to coreboot native init vgabios (cbvga)
     Added support for read character calls when in graphics mode
    Several bug fixes and code cleanups
    
    Change-Id: Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 payloads/external/SeaBIOS/Kconfig      | 2 +-
 payloads/external/SeaBIOS/Makefile.inc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
index 699b986..6224697 100644
--- a/payloads/external/SeaBIOS/Kconfig
+++ b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.7.5"
+	bool "1.8.2"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER
diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index 7fb63d4..ec877a9 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2
+TAG-$(CONFIG_SEABIOS_STABLE)=33fbe13a3e2a01e0ba1087a8feed801a0451db21
 
 unexport KCONFIG_AUTOHEADER
 unexport KCONFIG_AUTOCONFIG


From gerrit at coreboot.org  Wed Sep  2 00:09:14 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 2 Sep 2015 00:09:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	southbridge/bd82x6x: use new ssdt sata port generator
References: <I2be76097ebd27f2529e3fbbecefd314a0eea3cb0+0@gerrit.coreboot.org>
Message-ID: <I2be76097ebd27f2529e3fbbecefd314a0eea3cb0+17@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709

-gerrit

commit fa435f182f15a13441ac805e71127b8647a093a0
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Thu Apr 16 02:00:21 2015 +0200

    southbridge/bd82x6x: use new ssdt sata port generator
    
    Drop old incomplete, broken and hardcoded sata.asl properties.
    The new sata acpi generator only needs a proper defined device.
    
    Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 src/southbridge/intel/bd82x6x/Kconfig       |  1 +
 src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 -----------------------------
 src/southbridge/intel/bd82x6x/sata.c        |  8 +++++
 3 files changed, 9 insertions(+), 52 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 6190879..3a68fec 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
 	select COMMON_FADT
+	select ACPI_SATA_GENERATOR
 
 config EHCI_BAR
 	hex
diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl
index fb685a3..00d3010 100644
--- a/src/southbridge/intel/bd82x6x/acpi/sata.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl
@@ -26,56 +26,4 @@
 Device (SATA)
 {
 	Name (_ADR, 0x001f0002)
-
-	Device (PRID)
-	{
-		Name (_ADR, 0)
-
-		// Get Timing Mode
-		Method (_GTM)
-		{
-			Name(PBUF, Buffer(20) {
-				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-				0x00,0x00,0x00,0x00 })
-
-			CreateDwordField (PBUF,  0, PIO0)
-			CreateDwordField (PBUF,  4, DMA0)
-			CreateDwordField (PBUF,  8, PIO1)
-			CreateDwordField (PBUF, 12, DMA1)
-			CreateDwordField (PBUF, 16, FLAG)
-
-			// TODO fill return structure
-
-			Return (PBUF)
-		}
-
-		// Set Timing Mode
-		Method (_STM, 3)
-		{
-			CreateDwordField (Arg0,  0, PIO0)
-			CreateDwordField (Arg0,  4, DMA0)
-			CreateDwordField (Arg0,  8, PIO1)
-			CreateDwordField (Arg0, 12, DMA1)
-			CreateDwordField (Arg0, 16, FLAG)
-
-			// TODO: Do the deed
-		}
-
-		Device (DSK0)
-		{
-			Name (_ADR, 0)
-			// TODO: _RMV ?
-			// TODO: _GTF ?
-		}
-
-		Device (DSK1)
-		{
-			Name (_ADR, 1)
-
-			// TODO: _RMV ?
-			// TODO: _GTF ?
-		}
-
-	}
 }
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 1cdc5e2..18e5a08 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -25,6 +25,7 @@
 #include <device/pci_ids.h>
 #include "pch.h"
 #include <pc80/mc146818rtc.h>
+#include <acpi/sata.h>
 
 typedef struct southbridge_intel_bd82x6x_config config_t;
 
@@ -247,6 +248,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
+static void sata_fill_ssdt(device_t dev) {
+	config_t *config = dev->chip_info;
+	generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
+}
+
 static struct pci_operations sata_pci_ops = {
 	.set_subsystem    = sata_set_subsystem,
 };
@@ -255,6 +261,8 @@ static struct device_operations sata_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
+	.acpi_fill_ssdt_generator
+				= sata_fill_ssdt,
 	.init			= sata_init,
 	.enable			= sata_enable,
 	.scan_bus		= 0,


From gerrit at coreboot.org  Wed Sep  2 00:09:55 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 2 Sep 2015 00:09:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	southbridge/ibexpeak: use new ssdt sata port generator
References: <Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7+0@gerrit.coreboot.org>
Message-ID: <Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7+17@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9710

-gerrit

commit 5da2a5df8f010401e92210afc92e2de6caf596c0
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Thu Apr 16 02:23:00 2015 +0200

    southbridge/ibexpeak: use new ssdt sata port generator
    
    Drop old incomplete, broken and hardcoded sata.asl properties.
    The new sata acpi generator only needs a proper defined device.
    
    Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 src/southbridge/intel/ibexpeak/Kconfig | 1 +
 src/southbridge/intel/ibexpeak/sata.c  | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index ccd16bf..f31f83c 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_COMMON
 	select HAVE_USBDEBUG_OPTIONS
 	select COMMON_FADT
+	select ACPI_SATA_GENERATOR
 
 config EHCI_BAR
 	hex
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 29d9240..be2b961 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -26,6 +26,7 @@
 #include <device/pci_ids.h>
 #include "pch.h"
 #include <pc80/mc146818rtc.h>
+#include <acpi/sata.h>
 
 typedef struct southbridge_intel_ibexpeak_config config_t;
 
@@ -249,6 +250,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
+static void sata_fill_ssdt(device_t dev) {
+	config_t *config = dev->chip_info;
+	generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
+}
+
 static struct pci_operations sata_pci_ops = {
 	.set_subsystem = sata_set_subsystem,
 };
@@ -259,6 +265,7 @@ static struct device_operations sata_ops = {
 	.enable_resources = pci_dev_enable_resources,
 	.init = sata_init,
 	.enable = sata_enable,
+	.acpi_fill_ssdt_generator = sata_fill_ssdt,
 	.scan_bus = 0,
 	.ops_pci = &sata_pci_ops,
 };


From gerrit at coreboot.org  Wed Sep  2 00:20:36 2015
From: gerrit at coreboot.org (Alexander Couzens (lynxis@fe80.eu))
Date: Wed, 2 Sep 2015 00:20:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	southbridge/ibexpeak: use new ssdt sata port generator
References: <Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7+0@gerrit.coreboot.org>
Message-ID: <Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7+18@gerrit.coreboot.org>

Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9710

-gerrit

commit 71e293a145af95b6ee1f0120f55e98803c49dfc7
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Thu Apr 16 02:23:00 2015 +0200

    southbridge/ibexpeak: use new ssdt sata port generator
    
    Drop old incomplete, broken and hardcoded sata.asl properties.
    The new sata acpi generator only needs a proper defined device.
    
    Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 src/southbridge/intel/ibexpeak/Kconfig | 1 +
 src/southbridge/intel/ibexpeak/sata.c  | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index ccd16bf..f31f83c 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_COMMON
 	select HAVE_USBDEBUG_OPTIONS
 	select COMMON_FADT
+	select ACPI_SATA_GENERATOR
 
 config EHCI_BAR
 	hex
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 29d9240..6700820 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -26,6 +26,7 @@
 #include <device/pci_ids.h>
 #include "pch.h"
 #include <pc80/mc146818rtc.h>
+#include <acpi/sata.h>
 
 typedef struct southbridge_intel_ibexpeak_config config_t;
 
@@ -249,6 +250,12 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
+static void sata_fill_ssdt(device_t dev)
+{
+	config_t *config = dev->chip_info;
+	generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
+}
+
 static struct pci_operations sata_pci_ops = {
 	.set_subsystem = sata_set_subsystem,
 };
@@ -259,6 +266,7 @@ static struct device_operations sata_ops = {
 	.enable_resources = pci_dev_enable_resources,
 	.init = sata_init,
 	.enable = sata_enable,
+	.acpi_fill_ssdt_generator = sata_fill_ssdt,
 	.scan_bus = 0,
 	.ops_pci = &sata_pci_ops,
 };


From gerrit at coreboot.org  Wed Sep  2 00:20:43 2015
From: gerrit at coreboot.org (Alexander Couzens (lynxis@fe80.eu))
Date: Wed, 2 Sep 2015 00:20:43 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	southbridge/bd82x6x: use new ssdt sata port generator
References: <I2be76097ebd27f2529e3fbbecefd314a0eea3cb0+0@gerrit.coreboot.org>
Message-ID: <I2be76097ebd27f2529e3fbbecefd314a0eea3cb0+18@gerrit.coreboot.org>

Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709

-gerrit

commit ce52b9d8b23229f3df3259b0c3df591f49c9e202
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Thu Apr 16 02:00:21 2015 +0200

    southbridge/bd82x6x: use new ssdt sata port generator
    
    Drop old incomplete, broken and hardcoded sata.asl properties.
    The new sata acpi generator only needs a proper defined device.
    
    Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 src/southbridge/intel/bd82x6x/Kconfig       |  1 +
 src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 -----------------------------
 src/southbridge/intel/bd82x6x/sata.c        |  9 +++++
 3 files changed, 10 insertions(+), 52 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 6190879..3a68fec 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
 	select COMMON_FADT
+	select ACPI_SATA_GENERATOR
 
 config EHCI_BAR
 	hex
diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl
index fb685a3..00d3010 100644
--- a/src/southbridge/intel/bd82x6x/acpi/sata.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl
@@ -26,56 +26,4 @@
 Device (SATA)
 {
 	Name (_ADR, 0x001f0002)
-
-	Device (PRID)
-	{
-		Name (_ADR, 0)
-
-		// Get Timing Mode
-		Method (_GTM)
-		{
-			Name(PBUF, Buffer(20) {
-				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-				0x00,0x00,0x00,0x00 })
-
-			CreateDwordField (PBUF,  0, PIO0)
-			CreateDwordField (PBUF,  4, DMA0)
-			CreateDwordField (PBUF,  8, PIO1)
-			CreateDwordField (PBUF, 12, DMA1)
-			CreateDwordField (PBUF, 16, FLAG)
-
-			// TODO fill return structure
-
-			Return (PBUF)
-		}
-
-		// Set Timing Mode
-		Method (_STM, 3)
-		{
-			CreateDwordField (Arg0,  0, PIO0)
-			CreateDwordField (Arg0,  4, DMA0)
-			CreateDwordField (Arg0,  8, PIO1)
-			CreateDwordField (Arg0, 12, DMA1)
-			CreateDwordField (Arg0, 16, FLAG)
-
-			// TODO: Do the deed
-		}
-
-		Device (DSK0)
-		{
-			Name (_ADR, 0)
-			// TODO: _RMV ?
-			// TODO: _GTF ?
-		}
-
-		Device (DSK1)
-		{
-			Name (_ADR, 1)
-
-			// TODO: _RMV ?
-			// TODO: _GTF ?
-		}
-
-	}
 }
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 1cdc5e2..66a4c56 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -25,6 +25,7 @@
 #include <device/pci_ids.h>
 #include "pch.h"
 #include <pc80/mc146818rtc.h>
+#include <acpi/sata.h>
 
 typedef struct southbridge_intel_bd82x6x_config config_t;
 
@@ -247,6 +248,12 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
+static void sata_fill_ssdt(device_t dev)
+{
+	config_t *config = dev->chip_info;
+	generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
+}
+
 static struct pci_operations sata_pci_ops = {
 	.set_subsystem    = sata_set_subsystem,
 };
@@ -255,6 +262,8 @@ static struct device_operations sata_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
+	.acpi_fill_ssdt_generator
+				= sata_fill_ssdt,
 	.init			= sata_init,
 	.enable			= sata_enable,
 	.scan_bus		= 0,


From gerrit at coreboot.org  Wed Sep  2 06:47:24 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 2 Sep 2015 06:47:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Check
	free disk and warn if its size is too small
References: <Iae988300937018f166ff626b75c3a16bfa757ad9+0@gerrit.coreboot.org>
Message-ID: <Iae988300937018f166ff626b75c3a16bfa757ad9+3@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11474

-gerrit

commit a13a77e0c957a53f6b2012b8cb95e6a4dcedc927
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 1 22:31:08 2015 -0400

    buildgcc: Check free disk and warn if its size is too small
    
    We can only warn and can not stop building, because if the user
    saves the temp file the last time, the space might be enough.
    
    3G is an estimated size, which is required when I build i386-elf.
    
    Change-Id: Iae988300937018f166ff626b75c3a16bfa757ad9
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index bbf01b9..0ed9a39 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -290,6 +290,11 @@ cleanup()
 	printf "${green}ok${NC}\n"
 }
 
+freedisk() {
+	avail=$(LC_ALL=C eval df -k ./ | sed 1d | awk '{print $4}')
+	test $avail -lt 3145728 && printf "${red}WARNING: There might be not enough space.${NC}\n"
+}
+
 myhelp()
 {
 	printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n"
@@ -585,6 +590,7 @@ case "$PACKAGE" in
 		;;
 esac
 
+freedisk
 # Find all the required tools:
 
 TAR=$(searchtool tar) || exit $?


From gerrit at coreboot.org  Wed Sep  2 06:47:25 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 2 Sep 2015 06:47:25 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: buildgcc:
	Search the cksum command without checking OS type
References: <Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa+0@gerrit.coreboot.org>
Message-ID: <Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11483

-gerrit

commit 86fa6bafe6691f080f67655f82a2dc0941a1b31d
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 1 22:28:57 2015 -0400

    buildgcc: Search the cksum command without checking OS type
    
    Change-Id: Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 39 +++++++++++++++++++++------------------
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 49e41e5..bbf01b9 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -149,24 +149,26 @@ searchtool()
 			fi
 		fi
 	fi
-	if [ "$(echo $1 | cut -b -3)" = "sha" ]; then
-		if [ $UNAME = "FreeBSD" ]; then
-			if [ -x "$(which sha1 2>/dev/null)" ]; then
-				echo sha1
-				return
-			fi
-		fi
-		if [ $UNAME = "NetBSD" ]; then
-			if [ -x "$(which cksum 2>/dev/null)" ]; then
-				echo cksum -a $(echo $1 | sed -e 's,sum,,')
-				return
-			fi
-		fi
-		if [ $UNAME = "Darwin" ]; then
-			if [ -x "$(which openssl 2>/dev/null)" ]; then
-				echo openssl $(echo $1 | sed -e 's,sum,,')
-				return
-			fi
+	if echo $1 | grep -q "sum" ; then
+		algor=$(echo $1 | sed -e 's,sum,,')
+		if [ -x "$(which $1 2>/dev/null)" ]; then
+			#xxxsum [file]
+			echo $1
+			return
+		elif [ -x "$(which $algor 2>/dev/null)" ]; then
+			#xxx [file]
+			echo $algor
+			return
+		elif [ -x "$(which openssl 2>/dev/null)" ]; then
+			#openssl xxx [file]
+			echo openssl $algor
+			return
+		elif [ -x "$(which cksum 2>/dev/null)" ]; then
+			#cksum -a xxx [file]
+			#cksum has special options in NetBSD. Actually, NetBSD will use the second case above.
+			echo "buildgcc" | cksum -a $algor > /dev/null 2>/dev/null && \
+			echo cksum -a $algor
+			return
 		fi
 	fi
 	please_install $1
@@ -590,6 +592,7 @@ PATCH=$(searchtool patch) || exit $?
 MAKE=$(searchtool make) || exit $?
 SHA1SUM=$(searchtool sha1sum)
 SHA512SUM=$(searchtool sha512sum)
+MD5SUM=$(searchtool md5sum)
 CHECKSUM=$SHA1SUM
 
 searchtool m4 > /dev/null


From gerrit at coreboot.org  Wed Sep  2 09:09:09 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Wed, 2 Sep 2015 09:09:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: mc_tcu3: Extend
	hwinfo.hex and remove version.hex.
References: <I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7+0@gerrit.coreboot.org>
Message-ID: <I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7+1@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11484

-gerrit

commit 6c3e908adeed0e36601ccb0a2657c8d37ec983bb
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Wed Sep 2 11:00:34 2015 +0200

    mc_tcu3: Extend hwinfo.hex and remove version.hex.
    
    1. Update hwinfo.hex.
    2. Delete version.hex from mainboard directory. It can be added
       in site-local if needed.
    3. Adjust gpio settings.
    
    Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/mainboard/siemens/mc_tcu3/Makefile.inc |   4 ----
 src/mainboard/siemens/mc_tcu3/gpio.c       |   4 ++--
 src/mainboard/siemens/mc_tcu3/hwinfo.hex   | Bin 997 -> 7424 bytes
 src/mainboard/siemens/mc_tcu3/version.hex  |   3 ---
 4 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc
index 48216f6..cdf76cb 100644
--- a/src/mainboard/siemens/mc_tcu3/Makefile.inc
+++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc
@@ -30,10 +30,6 @@ hwinfo.hex-file := hwinfo.hex
 hwinfo.hex-type := raw
 hwinfo.hex-align := 0x1000
 
-cbfs-files-y += version.hex
-version.hex-file := version.hex
-version.hex-type := raw
-
 cbfs-files-y += hwinfo10.hex
 hwinfo10.hex-file := hwinfo10.hex
 hwinfo10.hex-type := raw
diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c
index 33adc00..e3d2669 100644
--- a/src/mainboard/siemens/mc_tcu3/gpio.c
+++ b/src/mainboard/siemens/mc_tcu3/gpio.c
@@ -173,7 +173,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[07]		PMC_SUSCLK[3]		RESERVED	RESERVED	RESERVED		 */
 	GPIO_INPUT_PU_10K,	/* GPIO_S5[08]		RESERVED		RESERVED	RESERVED	RESERVED 		 */
 	GPIO_INPUT_PU_10K,	/* GPIO_S5[09]		RESERVED		RESERVED	ESERVED		RESERVED		 */
-	GPIO_INPUT_PU_10K,	/* GPIO_S5[10]		RESERVED		RESERVED	RESERVED				 */
+	GPIO_OUT_HIGH,  	/* GPIO_S5[10]		RESERVED		RESERVED	RESERVED				 */
 	GPIO_DEFAULT,		/* PMC_SUSPWRDNACK	GPIO_S5[11]			-				-		 */
 	GPIO_DEFAULT,		/* PMC_SUSCLK[0]	GPIO_S5[12]			-				-		 */
 	GPIO_DEFAULT,		/* RESERVED		GPIO_S5[13]			-				-		 */
@@ -194,7 +194,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 	GPIO_DEFAULT,		/* GPIO_S5[28]		RESERVED		RESERVED	RESERVED	RESERVED		 */
 	GPIO_DEFAULT,		/* GPIO_S5[29]		RESERVED		RESERVED	RESERVED	RESERVED		 */
 	GPIO_DEFAULT,		/* GPIO_S5[30]		RESERVED		RESERVED	RESERVED	RESERVED		 */
-	GPIO_INPUT_PD_10K,	/* GPIO_S5[31]		USB_ULPI_CLK		RESERVED	RESERVED				 */
+	GPIO_OUT_LOW,   	/* GPIO_S5[31]		USB_ULPI_CLK		RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[32]		USB_ULPI_DATA[0]	RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[33]		USB_ULPI_DATA[1]	RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[34]		USB_ULPI_DATA[2]	RESERVED	RESERVED				 */
diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo.hex b/src/mainboard/siemens/mc_tcu3/hwinfo.hex
index ce7fc07..e123554 100644
Binary files a/src/mainboard/siemens/mc_tcu3/hwinfo.hex and b/src/mainboard/siemens/mc_tcu3/hwinfo.hex differ
diff --git a/src/mainboard/siemens/mc_tcu3/version.hex b/src/mainboard/siemens/mc_tcu3/version.hex
deleted file mode 100644
index 10b9c23..0000000
--- a/src/mainboard/siemens/mc_tcu3/version.hex
+++ /dev/null
@@ -1,3 +0,0 @@
-$USRV01.00.00.00
-$PLTTCU30.3
-$EXVV01.00.00.00


From gerrit at coreboot.org  Wed Sep  2 11:14:07 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Wed, 2 Sep 2015 11:14:07 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: mc_tcu3: Extend
	hwinfo.hex and remove version.hex.
References: <I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7+0@gerrit.coreboot.org>
Message-ID: <I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7+2@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11484

-gerrit

commit f561ddeca276e5d379c000953cbe9bdd3100c9ec
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Wed Sep 2 11:00:34 2015 +0200

    mc_tcu3: Extend hwinfo.hex and remove version.hex.
    
    1. Update hwinfo.hex (add dummy data and update checksums).
    2. Delete version.hex from mainboard directory. It can be added
       in site-local if needed.
    
    Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/mainboard/siemens/mc_tcu3/Makefile.inc |   4 ----
 src/mainboard/siemens/mc_tcu3/hwinfo.hex   | Bin 997 -> 7424 bytes
 src/mainboard/siemens/mc_tcu3/version.hex  |   3 ---
 3 files changed, 7 deletions(-)

diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc
index 48216f6..cdf76cb 100644
--- a/src/mainboard/siemens/mc_tcu3/Makefile.inc
+++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc
@@ -30,10 +30,6 @@ hwinfo.hex-file := hwinfo.hex
 hwinfo.hex-type := raw
 hwinfo.hex-align := 0x1000
 
-cbfs-files-y += version.hex
-version.hex-file := version.hex
-version.hex-type := raw
-
 cbfs-files-y += hwinfo10.hex
 hwinfo10.hex-file := hwinfo10.hex
 hwinfo10.hex-type := raw
diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo.hex b/src/mainboard/siemens/mc_tcu3/hwinfo.hex
index ce7fc07..e123554 100644
Binary files a/src/mainboard/siemens/mc_tcu3/hwinfo.hex and b/src/mainboard/siemens/mc_tcu3/hwinfo.hex differ
diff --git a/src/mainboard/siemens/mc_tcu3/version.hex b/src/mainboard/siemens/mc_tcu3/version.hex
deleted file mode 100644
index 10b9c23..0000000
--- a/src/mainboard/siemens/mc_tcu3/version.hex
+++ /dev/null
@@ -1,3 +0,0 @@
-$USRV01.00.00.00
-$PLTTCU30.3
-$EXVV01.00.00.00


From gerrit at coreboot.org  Wed Sep  2 13:51:09 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Wed, 2 Sep 2015 13:51:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: mc_tcu3: Adjust
	gpio settings.
References: <I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a+0@gerrit.coreboot.org>
Message-ID: <I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a+1@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11489

-gerrit

commit 57417e81b07911068ea60ace207ac2311502833f
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Wed Sep 2 15:13:04 2015 +0200

    mc_tcu3: Adjust gpio settings.
    
    Adjust gpio settings due to hardware chenge.
    
    Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/mainboard/siemens/mc_tcu3/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c
index 33adc00..ab1c59c 100644
--- a/src/mainboard/siemens/mc_tcu3/gpio.c
+++ b/src/mainboard/siemens/mc_tcu3/gpio.c
@@ -173,7 +173,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[07]		PMC_SUSCLK[3]		RESERVED	RESERVED	RESERVED		 */
 	GPIO_INPUT_PU_10K,	/* GPIO_S5[08]		RESERVED		RESERVED	RESERVED	RESERVED 		 */
 	GPIO_INPUT_PU_10K,	/* GPIO_S5[09]		RESERVED		RESERVED	ESERVED		RESERVED		 */
-	GPIO_INPUT_PU_10K,	/* GPIO_S5[10]		RESERVED		RESERVED	RESERVED				 */
+	GPIO_OUT_HIGH,		/* GPIO_S5[10]		RESERVED		RESERVED	RESERVED				 */
 	GPIO_DEFAULT,		/* PMC_SUSPWRDNACK	GPIO_S5[11]			-				-		 */
 	GPIO_DEFAULT,		/* PMC_SUSCLK[0]	GPIO_S5[12]			-				-		 */
 	GPIO_DEFAULT,		/* RESERVED		GPIO_S5[13]			-				-		 */
@@ -194,7 +194,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 	GPIO_DEFAULT,		/* GPIO_S5[28]		RESERVED		RESERVED	RESERVED	RESERVED		 */
 	GPIO_DEFAULT,		/* GPIO_S5[29]		RESERVED		RESERVED	RESERVED	RESERVED		 */
 	GPIO_DEFAULT,		/* GPIO_S5[30]		RESERVED		RESERVED	RESERVED	RESERVED		 */
-	GPIO_INPUT_PD_10K,	/* GPIO_S5[31]		USB_ULPI_CLK		RESERVED	RESERVED				 */
+	GPIO_OUT_LOW,		/* GPIO_S5[31]		USB_ULPI_CLK		RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[32]		USB_ULPI_DATA[0]	RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[33]		USB_ULPI_DATA[1]	RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[34]		USB_ULPI_DATA[2]	RESERVED	RESERVED				 */


From gerrit at coreboot.org  Wed Sep  2 14:25:52 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 2 Sep 2015 14:25:52 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: bootmode: add
	display_init_required()
References: <I403213e22c0e621e148773597a550addfbaf3f7e+0@gerrit.coreboot.org>
Message-ID: <I403213e22c0e621e148773597a550addfbaf3f7e+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490

-gerrit

commit 8749bba961f5857126c33ff03cb9c69f14aedf53
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 09:21:36 2015 -0500

    bootmode: add display_init_required()
    
    Some of the Chrome OS boards were directly calling vboot
    called in some form after contorting around #ifdef preprocessor
    macros. The reasoning is that Chrome OS doesn't always do display
    initialization during startup. It's runtime dependent. While
    this is a requirement that doesn't mean vboot functions should be
    sprinkled around in the mainboard and chipset code. Instead provide
    one function, display_init_required(), that provides the policy
    for determining display initialization action. For Chrome OS
    devices this function honors vboot_skip_display_init() and all
    other configurations default to initializing display.
    
    Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bootmode.h                    |  2 ++
 src/lib/bootmode.c                        | 11 +++++++++++
 src/mainboard/google/rush/mainboard.c     |  7 +++----
 src/mainboard/google/rush_ryu/mainboard.c |  3 ++-
 src/mainboard/google/smaug/mainboard.c    | 12 +++---------
 src/soc/nvidia/tegra124/soc.c             |  8 ++++----
 src/soc/nvidia/tegra132/soc.c             | 13 +++++++------
 src/soc/nvidia/tegra210/soc.c             | 13 +++++++------
 src/soc/rockchip/rk3288/soc.c             |  8 ++++----
 src/vendorcode/google/chromeos/chromeos.h |  1 +
 10 files changed, 44 insertions(+), 34 deletions(-)

diff --git a/src/include/bootmode.h b/src/include/bootmode.h
index ff562d5..96c789b 100644
--- a/src/include/bootmode.h
+++ b/src/include/bootmode.h
@@ -30,6 +30,8 @@ int get_wipeout_mode_switch(void);
 int get_lid_switch(void);
 
 
+/* Return 1 if display initialization is required. 0 if not. */
+int display_init_required(void);
 int gfx_get_init_done(void);
 void gfx_set_init_done(int done);
 
diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index c7e4927..7db7385 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -78,3 +78,14 @@ void gfx_set_init_done(int done)
 	gfx_init_done = done;
 }
 #endif
+
+
+int display_init_required(void)
+{
+	/* For Chrome OS always honor vboot_skip_display_init(). */
+	if (IS_ENABLED(CONFIG_CHROMEOS))
+		return !vboot_skip_display_init();
+
+	/* By default always initialize display. */
+	return 1;
+}
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index cffb7ac..aa67ec2 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -18,7 +18,9 @@
  */
 
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <memrange.h>
 #include <soc/addressmap.h>
@@ -32,9 +34,6 @@
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <delay.h>
-
 static const struct pad_config sdmmc3_pad[] = {
 	/* MMC3(SDCARD) */
 	PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
@@ -184,7 +183,7 @@ static void mainboard_init(device_t dev)
 	i2c_init(I2C1_BUS);		/* for max98090 codec */
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 863ab52..1af7395 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -19,6 +19,7 @@
 
 #include <arch/mmu.h>
 #include <boardid.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <cbmem.h>
 #include <delay.h>
@@ -281,7 +282,7 @@ static void mainboard_init(device_t dev)
 	soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c
index 1cf4d32..6e3393d 100644
--- a/src/mainboard/google/smaug/mainboard.c
+++ b/src/mainboard/google/smaug/mainboard.c
@@ -20,7 +20,9 @@
 
 #include <arch/io.h>
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/i2c.h>
 #include <soc/addressmap.h>
@@ -36,12 +38,6 @@
 #include <soc/pmc.h>
 #include <soc/power.h>
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
-#include <vendorcode/google/chromeos/vboot_handoff.h>
-#include <vendorcode/google/chromeos/vboot2/misc.h>
-#endif
-#include <delay.h>
-
 #include "gpio.h"
 #include "pmic.h"
 
@@ -202,9 +198,7 @@ static void mainboard_init(device_t dev)
 	setup_audio();
 
 	/* if panel needs to bringup */
-#if IS_ENABLED(CONFIG_CHROMEOS)
-	if (!vboot_skip_display_init())
-#endif
+	if (display_init_required())
 		configure_display_blocks();
 
 	powergate_unused_partitions();
diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c
index 406457b..c38232d 100644
--- a/src/soc/nvidia/tegra124/soc.c
+++ b/src/soc/nvidia/tegra124/soc.c
@@ -20,13 +20,13 @@
  */
 
 #include <arch/io.h>
+#include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 #include <soc/sdram.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -53,10 +53,10 @@ static void soc_enable(device_t dev)
 
 static void soc_init(device_t dev)
 {
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		display_startup(dev);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 	printk(BIOS_INFO, "CPU: Tegra124\n");
 }
 
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 4ca866c..a65f36d 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -34,7 +35,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -101,12 +101,13 @@ static void soc_init(device_t dev)
 	/* Lock down VPR */
 	lock_down_vpr();
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index 9e67531..981b09c 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -35,7 +36,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/sdram.h>
 #include <soc/sdram_configs.h>
 
@@ -92,12 +92,13 @@ static void soc_init(device_t dev)
 	spintable_init((void *)cfg->spintable_addr);
 	arch_initialize_cpus(dev, &cntrl_ops);
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static void soc_noop(device_t dev)
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index a13086a..a9484b4 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/cache.h>
+#include <bootmode.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>
@@ -30,18 +31,17 @@
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
 static void soc_init(device_t dev)
 {
 	ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		rk_display_init(dev, (uintptr_t)_framebuffer,
 				_framebuffer_size);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index c7048dd..90675b2 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -24,6 +24,7 @@
 #include <stdint.h>
 #include <bootmode.h>
 #include <rules.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "vboot_common.h"
 #include "vboot2/misc.h"
 


From gerrit at coreboot.org  Wed Sep  2 14:27:43 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 2 Sep 2015 14:27:43 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: bootmode: add
	display_init_required()
References: <I403213e22c0e621e148773597a550addfbaf3f7e+0@gerrit.coreboot.org>
Message-ID: <I403213e22c0e621e148773597a550addfbaf3f7e+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490

-gerrit

commit 10339fd30326bcd9ce2488084094d68fc0a6a0c2
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 09:21:36 2015 -0500

    bootmode: add display_init_required()
    
    Some of the Chrome OS boards were directly calling vboot
    called in some form after contorting around #ifdef preprocessor
    macros. The reasoning is that Chrome OS doesn't always do display
    initialization during startup. It's runtime dependent. While
    this is a requirement that doesn't mean vboot functions should be
    sprinkled around in the mainboard and chipset code. Instead provide
    one function, display_init_required(), that provides the policy
    for determining display initialization action. For Chrome OS
    devices this function honors vboot_skip_display_init() and all
    other configurations default to initializing display.
    
    Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bootmode.h                    |  2 ++
 src/lib/bootmode.c                        | 10 ++++++++++
 src/mainboard/google/rush/mainboard.c     |  7 +++----
 src/mainboard/google/rush_ryu/mainboard.c |  3 ++-
 src/mainboard/google/smaug/mainboard.c    | 12 +++---------
 src/soc/nvidia/tegra124/soc.c             |  8 ++++----
 src/soc/nvidia/tegra132/soc.c             | 13 +++++++------
 src/soc/nvidia/tegra210/soc.c             | 13 +++++++------
 src/soc/rockchip/rk3288/soc.c             |  8 ++++----
 9 files changed, 42 insertions(+), 34 deletions(-)

diff --git a/src/include/bootmode.h b/src/include/bootmode.h
index ff562d5..96c789b 100644
--- a/src/include/bootmode.h
+++ b/src/include/bootmode.h
@@ -30,6 +30,8 @@ int get_wipeout_mode_switch(void);
 int get_lid_switch(void);
 
 
+/* Return 1 if display initialization is required. 0 if not. */
+int display_init_required(void);
 int gfx_get_init_done(void);
 void gfx_set_init_done(int done);
 
diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index c7e4927..615b7b3 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -78,3 +78,13 @@ void gfx_set_init_done(int done)
 	gfx_init_done = done;
 }
 #endif
+
+int display_init_required(void)
+{
+	/* For Chrome OS always honor vboot_skip_display_init(). */
+	if (IS_ENABLED(CONFIG_CHROMEOS))
+		return !vboot_skip_display_init();
+
+	/* By default always initialize display. */
+	return 1;
+}
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index cffb7ac..aa67ec2 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -18,7 +18,9 @@
  */
 
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <memrange.h>
 #include <soc/addressmap.h>
@@ -32,9 +34,6 @@
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <delay.h>
-
 static const struct pad_config sdmmc3_pad[] = {
 	/* MMC3(SDCARD) */
 	PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
@@ -184,7 +183,7 @@ static void mainboard_init(device_t dev)
 	i2c_init(I2C1_BUS);		/* for max98090 codec */
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 863ab52..1af7395 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -19,6 +19,7 @@
 
 #include <arch/mmu.h>
 #include <boardid.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <cbmem.h>
 #include <delay.h>
@@ -281,7 +282,7 @@ static void mainboard_init(device_t dev)
 	soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c
index 1cf4d32..6e3393d 100644
--- a/src/mainboard/google/smaug/mainboard.c
+++ b/src/mainboard/google/smaug/mainboard.c
@@ -20,7 +20,9 @@
 
 #include <arch/io.h>
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/i2c.h>
 #include <soc/addressmap.h>
@@ -36,12 +38,6 @@
 #include <soc/pmc.h>
 #include <soc/power.h>
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
-#include <vendorcode/google/chromeos/vboot_handoff.h>
-#include <vendorcode/google/chromeos/vboot2/misc.h>
-#endif
-#include <delay.h>
-
 #include "gpio.h"
 #include "pmic.h"
 
@@ -202,9 +198,7 @@ static void mainboard_init(device_t dev)
 	setup_audio();
 
 	/* if panel needs to bringup */
-#if IS_ENABLED(CONFIG_CHROMEOS)
-	if (!vboot_skip_display_init())
-#endif
+	if (display_init_required())
 		configure_display_blocks();
 
 	powergate_unused_partitions();
diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c
index 406457b..c38232d 100644
--- a/src/soc/nvidia/tegra124/soc.c
+++ b/src/soc/nvidia/tegra124/soc.c
@@ -20,13 +20,13 @@
  */
 
 #include <arch/io.h>
+#include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 #include <soc/sdram.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -53,10 +53,10 @@ static void soc_enable(device_t dev)
 
 static void soc_init(device_t dev)
 {
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		display_startup(dev);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 	printk(BIOS_INFO, "CPU: Tegra124\n");
 }
 
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 4ca866c..a65f36d 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -34,7 +35,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -101,12 +101,13 @@ static void soc_init(device_t dev)
 	/* Lock down VPR */
 	lock_down_vpr();
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index 9e67531..981b09c 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -35,7 +36,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/sdram.h>
 #include <soc/sdram_configs.h>
 
@@ -92,12 +92,13 @@ static void soc_init(device_t dev)
 	spintable_init((void *)cfg->spintable_addr);
 	arch_initialize_cpus(dev, &cntrl_ops);
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static void soc_noop(device_t dev)
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index a13086a..a9484b4 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/cache.h>
+#include <bootmode.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>
@@ -30,18 +31,17 @@
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
 static void soc_init(device_t dev)
 {
 	ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		rk_display_init(dev, (uintptr_t)_framebuffer,
 				_framebuffer_size);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {


From gerrit at coreboot.org  Wed Sep  2 14:36:39 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 2 Sep 2015 14:36:39 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: bootmode: add
	display_init_required()
References: <I403213e22c0e621e148773597a550addfbaf3f7e+0@gerrit.coreboot.org>
Message-ID: <I403213e22c0e621e148773597a550addfbaf3f7e+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490

-gerrit

commit fba913f1a4aceea19bb00fe3c02fe316bd6aa056
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 09:21:36 2015 -0500

    bootmode: add display_init_required()
    
    Some of the Chrome OS boards were directly calling vboot
    called in some form after contorting around #ifdef preprocessor
    macros. The reasoning is that Chrome OS doesn't always do display
    initialization during startup. It's runtime dependent. While
    this is a requirement that doesn't mean vboot functions should be
    sprinkled around in the mainboard and chipset code. Instead provide
    one function, display_init_required(), that provides the policy
    for determining display initialization action. For Chrome OS
    devices this function honors vboot_skip_display_init() and all
    other configurations default to initializing display.
    
    Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bootmode.h                    |  4 ++++
 src/lib/bootmode.c                        | 10 ++++++++++
 src/mainboard/google/rush/mainboard.c     |  7 +++----
 src/mainboard/google/rush_ryu/mainboard.c |  3 ++-
 src/mainboard/google/smaug/mainboard.c    | 12 +++---------
 src/soc/nvidia/tegra124/soc.c             |  8 ++++----
 src/soc/nvidia/tegra132/soc.c             | 13 +++++++------
 src/soc/nvidia/tegra210/soc.c             | 13 +++++++------
 src/soc/rockchip/rk3288/soc.c             |  8 ++++----
 9 files changed, 44 insertions(+), 34 deletions(-)

diff --git a/src/include/bootmode.h b/src/include/bootmode.h
index ff562d5..39755d4 100644
--- a/src/include/bootmode.h
+++ b/src/include/bootmode.h
@@ -20,6 +20,8 @@
 #ifndef __BOOTMODE_H__
 #define __BOOTMODE_H__
 
+#include <vendorcode/google/chromeos/chromeos.h>
+
 /* functions implemented per mainboard: */
 void init_bootmode_straps(void);
 int get_write_protect_state(void);
@@ -30,6 +32,8 @@ int get_wipeout_mode_switch(void);
 int get_lid_switch(void);
 
 
+/* Return 1 if display initialization is required. 0 if not. */
+int display_init_required(void);
 int gfx_get_init_done(void);
 void gfx_set_init_done(int done);
 
diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index c7e4927..615b7b3 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -78,3 +78,13 @@ void gfx_set_init_done(int done)
 	gfx_init_done = done;
 }
 #endif
+
+int display_init_required(void)
+{
+	/* For Chrome OS always honor vboot_skip_display_init(). */
+	if (IS_ENABLED(CONFIG_CHROMEOS))
+		return !vboot_skip_display_init();
+
+	/* By default always initialize display. */
+	return 1;
+}
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index cffb7ac..aa67ec2 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -18,7 +18,9 @@
  */
 
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <memrange.h>
 #include <soc/addressmap.h>
@@ -32,9 +34,6 @@
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <delay.h>
-
 static const struct pad_config sdmmc3_pad[] = {
 	/* MMC3(SDCARD) */
 	PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
@@ -184,7 +183,7 @@ static void mainboard_init(device_t dev)
 	i2c_init(I2C1_BUS);		/* for max98090 codec */
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 863ab52..1af7395 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -19,6 +19,7 @@
 
 #include <arch/mmu.h>
 #include <boardid.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <cbmem.h>
 #include <delay.h>
@@ -281,7 +282,7 @@ static void mainboard_init(device_t dev)
 	soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c
index 1cf4d32..6e3393d 100644
--- a/src/mainboard/google/smaug/mainboard.c
+++ b/src/mainboard/google/smaug/mainboard.c
@@ -20,7 +20,9 @@
 
 #include <arch/io.h>
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/i2c.h>
 #include <soc/addressmap.h>
@@ -36,12 +38,6 @@
 #include <soc/pmc.h>
 #include <soc/power.h>
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
-#include <vendorcode/google/chromeos/vboot_handoff.h>
-#include <vendorcode/google/chromeos/vboot2/misc.h>
-#endif
-#include <delay.h>
-
 #include "gpio.h"
 #include "pmic.h"
 
@@ -202,9 +198,7 @@ static void mainboard_init(device_t dev)
 	setup_audio();
 
 	/* if panel needs to bringup */
-#if IS_ENABLED(CONFIG_CHROMEOS)
-	if (!vboot_skip_display_init())
-#endif
+	if (display_init_required())
 		configure_display_blocks();
 
 	powergate_unused_partitions();
diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c
index 406457b..c38232d 100644
--- a/src/soc/nvidia/tegra124/soc.c
+++ b/src/soc/nvidia/tegra124/soc.c
@@ -20,13 +20,13 @@
  */
 
 #include <arch/io.h>
+#include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 #include <soc/sdram.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -53,10 +53,10 @@ static void soc_enable(device_t dev)
 
 static void soc_init(device_t dev)
 {
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		display_startup(dev);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 	printk(BIOS_INFO, "CPU: Tegra124\n");
 }
 
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 4ca866c..a65f36d 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -34,7 +35,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -101,12 +101,13 @@ static void soc_init(device_t dev)
 	/* Lock down VPR */
 	lock_down_vpr();
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index 9e67531..981b09c 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -35,7 +36,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/sdram.h>
 #include <soc/sdram_configs.h>
 
@@ -92,12 +92,13 @@ static void soc_init(device_t dev)
 	spintable_init((void *)cfg->spintable_addr);
 	arch_initialize_cpus(dev, &cntrl_ops);
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static void soc_noop(device_t dev)
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index a13086a..a9484b4 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/cache.h>
+#include <bootmode.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>
@@ -30,18 +31,17 @@
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
 static void soc_init(device_t dev)
 {
 	ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		rk_display_init(dev, (uintptr_t)_framebuffer,
 				_framebuffer_size);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {


From gerrit at coreboot.org  Wed Sep  2 16:04:26 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Wed, 2 Sep 2015 16:04:26 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	north/intel/sandybridge: Fix native VGA initialization
References: <I51a4f4874ce77178cab96651eb7caf2edd862aa2+0@gerrit.coreboot.org>
Message-ID: <I51a4f4874ce77178cab96651eb7caf2edd862aa2+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11491

-gerrit

commit b152067b9a3722ad0ce7340e45f61618773c310f
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 2 09:00:45 2015 -0700

    north/intel/sandybridge: Fix native VGA initialization
    
    Native VGA init no longer compiles  from commit:
    * 7dbf9c6 edid: Use edid_mode struct to reduce redundancy
    
    Change-Id: I51a4f4874ce77178cab96651eb7caf2edd862aa2
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 .../intel/sandybridge/gma_sandybridge_lvds.c       | 35 +++++++++++-----------
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index bbc9882..266883e 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -128,6 +128,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	int i;
 	u8 edid_data[128];
 	struct edid edid;
+	struct edid_mode *mode;
 	u32 hactive, vactive, right_border, bottom_border;
 	int hpolarity, vpolarity;
 	u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
@@ -184,27 +185,27 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	power_port(mmio);
 
 	intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
-	decode_edid(edid_data,
-		    sizeof(edid_data), &edid);
+	decode_edid(edid_data, sizeof(edid_data), &edid);
+	mode = &edid.mode;
 
 	/* Disable screen memory to prevent garbage from appearing.  */
 	vga_sr_write(1, vga_sr_read(1) | 0x20);
 
 	hactive = edid.x_resolution;
 	vactive = edid.y_resolution;
-	right_border = edid.hborder;
-	bottom_border = edid.vborder;
-	hpolarity = (edid.phsync == '-');
-	vpolarity = (edid.pvsync == '-');
-	vsync = edid.vspw;
-	hsync = edid.hspw;
-	vblank = edid.vbl;
-	hblank = edid.hbl;
-	hfront_porch = edid.hso;
-	vfront_porch = edid.vso;
-
-	target_frequency = info->lvds_dual_channel ? edid.pixel_clock
-		: (2 * edid.pixel_clock);
+	right_border = mode->hborder;
+	bottom_border = mode->vborder;
+	hpolarity = (mode->phsync == '-');
+	vpolarity = (mode->pvsync == '-');
+	vsync = mode->vspw;
+	hsync = mode->hspw;
+	vblank = mode->vbl;
+	hblank = mode->hbl;
+	hfront_porch = mode->hso;
+	vfront_porch = mode->vso;
+
+	target_frequency = info->lvds_dual_channel ? mode->pixel_clock
+		: (2 * mode->pixel_clock);
 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_textmode_init();
 #else
@@ -272,8 +273,8 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 		return 0;
 	}
 
-	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
-	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
+	link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
+	data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
 		/ (link_frequency * 8 * (info->lvds_num_lanes ? : 4));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",


From gerrit at coreboot.org  Wed Sep  2 21:11:13 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 2 Sep 2015 21:11:13 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	southbridge/bd82x6x: use new ssdt sata port generator
References: <I2be76097ebd27f2529e3fbbecefd314a0eea3cb0+0@gerrit.coreboot.org>
Message-ID: <E1ZXFJJ-0002rH-SA@mail.coreboot.org>

the following patch was just integrated into master:
commit 7bf47eecd60415c5151cd9906947b5ef375f29de
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Thu Apr 16 02:00:21 2015 +0200

    southbridge/bd82x6x: use new ssdt sata port generator
    
    Drop old incomplete, broken and hardcoded sata.asl properties.
    The new sata acpi generator only needs a proper defined device.
    
    Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
    Reviewed-on: http://review.coreboot.org/9709
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter at stuge.se>


See http://review.coreboot.org/9709 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  2 21:11:40 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 2 Sep 2015 21:11:40 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	southbridge/ibexpeak: use new ssdt sata port generator
References: <Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7+0@gerrit.coreboot.org>
Message-ID: <E1ZXFJk-0002wH-Mk@mail.coreboot.org>

the following patch was just integrated into master:
commit beb31d0cdc4f935b4f66cb8ef84b7683e1923ed7
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Thu Apr 16 02:23:00 2015 +0200

    southbridge/ibexpeak: use new ssdt sata port generator
    
    Drop old incomplete, broken and hardcoded sata.asl properties.
    The new sata acpi generator only needs a proper defined device.
    
    Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
    Reviewed-on: http://review.coreboot.org/9710
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter at stuge.se>


See http://review.coreboot.org/9710 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  2 21:51:33 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 2 Sep 2015 21:51:33 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: bootmode: add
	display_init_required()
References: <I403213e22c0e621e148773597a550addfbaf3f7e+0@gerrit.coreboot.org>
Message-ID: <I403213e22c0e621e148773597a550addfbaf3f7e+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490

-gerrit

commit 5527c4efc7bd33e3711b13179b64952779ebcb40
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 09:21:36 2015 -0500

    bootmode: add display_init_required()
    
    Some of the Chrome OS boards were directly calling vboot
    called in some form after contorting around #ifdef preprocessor
    macros. The reasoning is that Chrome OS doesn't always do display
    initialization during startup. It's runtime dependent. While
    this is a requirement that doesn't mean vboot functions should be
    sprinkled around in the mainboard and chipset code. Instead provide
    one function, display_init_required(), that provides the policy
    for determining display initialization action. For Chrome OS
    devices this function honors vboot_skip_display_init() and all
    other configurations default to initializing display.
    
    Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bootmode.h                    |  2 ++
 src/lib/bootmode.c                        | 12 ++++++++++--
 src/mainboard/google/rush/mainboard.c     |  7 +++----
 src/mainboard/google/rush_ryu/mainboard.c |  3 ++-
 src/mainboard/google/smaug/mainboard.c    | 12 +++---------
 src/soc/nvidia/tegra124/soc.c             |  8 ++++----
 src/soc/nvidia/tegra132/soc.c             | 13 +++++++------
 src/soc/nvidia/tegra210/soc.c             | 13 +++++++------
 src/soc/rockchip/rk3288/soc.c             |  8 ++++----
 9 files changed, 42 insertions(+), 36 deletions(-)

diff --git a/src/include/bootmode.h b/src/include/bootmode.h
index ff562d5..96c789b 100644
--- a/src/include/bootmode.h
+++ b/src/include/bootmode.h
@@ -30,6 +30,8 @@ int get_wipeout_mode_switch(void);
 int get_lid_switch(void);
 
 
+/* Return 1 if display initialization is required. 0 if not. */
+int display_init_required(void);
 int gfx_get_init_done(void);
 void gfx_set_init_done(int done);
 
diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index c7e4927..f2ff72a 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -19,9 +19,7 @@
 
 #include <rules.h>
 #include <bootmode.h>
-#if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE
 #include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 #if CONFIG_BOOTMODE_STRAPS
 int developer_mode_enabled(void)
@@ -78,3 +76,13 @@ void gfx_set_init_done(int done)
 	gfx_init_done = done;
 }
 #endif
+
+int display_init_required(void)
+{
+	/* For Chrome OS always honor vboot_skip_display_init(). */
+	if (IS_ENABLED(CONFIG_CHROMEOS))
+		return !vboot_skip_display_init();
+
+	/* By default always initialize display. */
+	return 1;
+}
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index cffb7ac..aa67ec2 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -18,7 +18,9 @@
  */
 
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <memrange.h>
 #include <soc/addressmap.h>
@@ -32,9 +34,6 @@
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <delay.h>
-
 static const struct pad_config sdmmc3_pad[] = {
 	/* MMC3(SDCARD) */
 	PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
@@ -184,7 +183,7 @@ static void mainboard_init(device_t dev)
 	i2c_init(I2C1_BUS);		/* for max98090 codec */
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 863ab52..1af7395 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -19,6 +19,7 @@
 
 #include <arch/mmu.h>
 #include <boardid.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <cbmem.h>
 #include <delay.h>
@@ -281,7 +282,7 @@ static void mainboard_init(device_t dev)
 	soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c
index 1cf4d32..6e3393d 100644
--- a/src/mainboard/google/smaug/mainboard.c
+++ b/src/mainboard/google/smaug/mainboard.c
@@ -20,7 +20,9 @@
 
 #include <arch/io.h>
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/i2c.h>
 #include <soc/addressmap.h>
@@ -36,12 +38,6 @@
 #include <soc/pmc.h>
 #include <soc/power.h>
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
-#include <vendorcode/google/chromeos/vboot_handoff.h>
-#include <vendorcode/google/chromeos/vboot2/misc.h>
-#endif
-#include <delay.h>
-
 #include "gpio.h"
 #include "pmic.h"
 
@@ -202,9 +198,7 @@ static void mainboard_init(device_t dev)
 	setup_audio();
 
 	/* if panel needs to bringup */
-#if IS_ENABLED(CONFIG_CHROMEOS)
-	if (!vboot_skip_display_init())
-#endif
+	if (display_init_required())
 		configure_display_blocks();
 
 	powergate_unused_partitions();
diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c
index 406457b..c38232d 100644
--- a/src/soc/nvidia/tegra124/soc.c
+++ b/src/soc/nvidia/tegra124/soc.c
@@ -20,13 +20,13 @@
  */
 
 #include <arch/io.h>
+#include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 #include <soc/sdram.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -53,10 +53,10 @@ static void soc_enable(device_t dev)
 
 static void soc_init(device_t dev)
 {
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		display_startup(dev);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 	printk(BIOS_INFO, "CPU: Tegra124\n");
 }
 
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 4ca866c..a65f36d 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -34,7 +35,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -101,12 +101,13 @@ static void soc_init(device_t dev)
 	/* Lock down VPR */
 	lock_down_vpr();
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index 9e67531..981b09c 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -35,7 +36,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/sdram.h>
 #include <soc/sdram_configs.h>
 
@@ -92,12 +92,13 @@ static void soc_init(device_t dev)
 	spintable_init((void *)cfg->spintable_addr);
 	arch_initialize_cpus(dev, &cntrl_ops);
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static void soc_noop(device_t dev)
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index a13086a..a9484b4 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/cache.h>
+#include <bootmode.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>
@@ -30,18 +31,17 @@
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
 static void soc_init(device_t dev)
 {
 	ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		rk_display_init(dev, (uintptr_t)_framebuffer,
 				_framebuffer_size);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {


From gerrit at coreboot.org  Wed Sep  2 21:55:42 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 2 Sep 2015 21:55:42 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: google:
	veryron_*: CBFS_SIZE to match the available size for coreboot
References: <I168386a5011222866654a496d8d054faff7a9406+0@gerrit.coreboot.org>
Message-ID: <I168386a5011222866654a496d8d054faff7a9406+2@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11117

-gerrit

commit 69a2d313abdf898f5b701d5b787e9912132d8142
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Mon Aug 3 14:24:09 2015 +0200

    google: veryron_*: CBFS_SIZE to match the available size for coreboot
    
    Veyron boards come with a 4 MiB SPI flash chip. However, only 1 MiB of those is
    available for coreboot and the rest shouldn't be overriden by it.
    
    Change-Id: I168386a5011222866654a496d8d054faff7a9406
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/mainboard/google/veyron_brain/Kconfig  | 5 +++++
 src/mainboard/google/veyron_danger/Kconfig | 5 +++++
 src/mainboard/google/veyron_jerry/Kconfig  | 5 +++++
 src/mainboard/google/veyron_mickey/Kconfig | 5 +++++
 src/mainboard/google/veyron_mighty/Kconfig | 5 +++++
 src/mainboard/google/veyron_minnie/Kconfig | 5 +++++
 src/mainboard/google/veyron_pinky/Kconfig  | 5 +++++
 src/mainboard/google/veyron_rialto/Kconfig | 5 +++++
 src/mainboard/google/veyron_romy/Kconfig   | 5 +++++
 src/mainboard/google/veyron_shark/Kconfig  | 5 +++++
 src/mainboard/google/veyron_speedy/Kconfig | 5 +++++
 11 files changed, 55 insertions(+)

diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig
index f96e92c..3297d29 100644
--- a/src/mainboard/google/veyron_brain/Kconfig
+++ b/src/mainboard/google/veyron_brain/Kconfig
@@ -72,4 +72,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_BRAIN
diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig
index 4c213f2..f8f31ab 100644
--- a/src/mainboard/google/veyron_danger/Kconfig
+++ b/src/mainboard/google/veyron_danger/Kconfig
@@ -71,4 +71,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_DANGER
diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig
index 1bbcf94..1e36e22 100644
--- a/src/mainboard/google/veyron_jerry/Kconfig
+++ b/src/mainboard/google/veyron_jerry/Kconfig
@@ -82,4 +82,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_JERRY
diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig
index bbe5f7d..efec03a 100644
--- a/src/mainboard/google/veyron_mickey/Kconfig
+++ b/src/mainboard/google/veyron_mickey/Kconfig
@@ -72,4 +72,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_MICKEY
diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig
index 4dad49c..40162b3 100644
--- a/src/mainboard/google/veyron_mighty/Kconfig
+++ b/src/mainboard/google/veyron_mighty/Kconfig
@@ -82,4 +82,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_MIGHTY
diff --git a/src/mainboard/google/veyron_minnie/Kconfig b/src/mainboard/google/veyron_minnie/Kconfig
index f2cd87b..6735ca1 100644
--- a/src/mainboard/google/veyron_minnie/Kconfig
+++ b/src/mainboard/google/veyron_minnie/Kconfig
@@ -82,4 +82,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_MINNIE
diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig
index 5c6e7cd..68ad87c 100644
--- a/src/mainboard/google/veyron_pinky/Kconfig
+++ b/src/mainboard/google/veyron_pinky/Kconfig
@@ -82,4 +82,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_PINKY
diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig
index 0c72667..8feb331 100644
--- a/src/mainboard/google/veyron_rialto/Kconfig
+++ b/src/mainboard/google/veyron_rialto/Kconfig
@@ -72,4 +72,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_RIALTO
diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig
index 9cb6d89..85adb78 100644
--- a/src/mainboard/google/veyron_romy/Kconfig
+++ b/src/mainboard/google/veyron_romy/Kconfig
@@ -72,4 +72,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_ROMY
diff --git a/src/mainboard/google/veyron_shark/Kconfig b/src/mainboard/google/veyron_shark/Kconfig
index 829fb85..4e4f167 100644
--- a/src/mainboard/google/veyron_shark/Kconfig
+++ b/src/mainboard/google/veyron_shark/Kconfig
@@ -82,4 +82,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_SHARK
diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig
index 411ea42..5fab628 100644
--- a/src/mainboard/google/veyron_speedy/Kconfig
+++ b/src/mainboard/google/veyron_speedy/Kconfig
@@ -82,4 +82,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON_SPEEDY


From gerrit at coreboot.org  Wed Sep  2 22:37:45 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 2 Sep 2015 22:37:45 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: bootstate:
	remove need for #ifdef ENV_RAMSTAGE
References: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+0@gerrit.coreboot.org>
Message-ID: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492

-gerrit

commit 4195c04a02d1811294256acdabc74b55b15bf2f3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 17:34:04 2015 -0500

    bootstate: remove need for #ifdef ENV_RAMSTAGE
    
    The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
    the current state of the header meant bad build errors in non-ramstage.
    Therefore, people had to #ifdef in the source. Remove that requirement.
    
    Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp1_0/fsp_util.c          |  3 ---
 src/drivers/intel/fsp1_1/fsp_util.c          |  4 ----
 src/include/bootstate.h                      |  8 +++++---
 src/lib/cbmem_common.c                       |  5 ++++-
 src/northbridge/intel/haswell/mrccache.c     |  3 +--
 src/northbridge/intel/sandybridge/mrccache.c |  3 +--
 src/soc/intel/baytrail/spi.c                 |  2 --
 src/soc/intel/braswell/spi.c                 |  4 ----
 src/soc/intel/broadwell/spi.c                |  2 --
 src/soc/intel/common/mrc_cache.c             | 19 ++-----------------
 src/southbridge/intel/common/spi.c           |  3 +--
 11 files changed, 14 insertions(+), 42 deletions(-)

diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c
index 9dbd502..f1e0d11 100644
--- a/src/drivers/intel/fsp1_0/fsp_util.c
+++ b/src/drivers/intel/fsp1_0/fsp_util.c
@@ -215,8 +215,6 @@ void * find_fsp_reserved_mem(void *hob_list_ptr)
 }
 #endif /* FSP_RESERVE_MEMORY_SIZE */
 
-#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */
-
 void print_fsp_info(void) {
 
 	if (fsp_header_ptr == NULL)
@@ -349,4 +347,3 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
 /* Update the MRC/fast boot cache as part of the late table writing stage */
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
 			find_fsp_hob_update_mrc, NULL);
-#endif	/* #ifndef __PRE_RAM__ */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 18e8648..bce4337 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header)
 #endif
 }
 
-#if ENV_RAMSTAGE
-
 void fsp_notify(u32 phase)
 {
 	FSP_NOTIFY_PHASE notify_phase_proc;
@@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
 	fsp_notify_boot_state_callback,
 	(void *)EnumInitPhaseReadyToBoot);
 
-#endif	/* ENV_RAMSTAGE */
-
 struct fsp_runtime {
 	uint32_t fih;
 	uint32_t hob_list;
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 4952780..1bbe458 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -19,8 +19,7 @@
 #ifndef BOOTSTATE_H
 #define BOOTSTATE_H
 
-#if !defined(__SMM__) && !defined(__PRE_RAM__)
-
+#include <rules.h>
 #include <string.h>
 #include <stdlib.h>
 #include <stddef.h>
@@ -185,7 +184,11 @@ struct boot_state_init_entry {
 	struct boot_state_callback bscb;
 };
 
+#if ENV_RAMSTAGE
 #define BOOT_STATE_INIT_ATTR  __attribute__ ((used,section (".bs_init")))
+#else
+#define BOOT_STATE_INIT_ATTR  __attribute__ ((unused))
+#endif
 
 #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_)		\
 	static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \
@@ -198,5 +201,4 @@ struct boot_state_init_entry {
 		bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \
 		& func_ ##_## state_ ##_## when_;
 
-#endif
 #endif /* BOOTSTATE_H */
diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c
index d3019c5..143935e 100644
--- a/src/lib/cbmem_common.c
+++ b/src/lib/cbmem_common.c
@@ -43,9 +43,12 @@ void __attribute__((weak)) cbmem_fail_resume(void)
 {
 }
 
-#if ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
+#if !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
 static void init_cbmem_post_device(void *unused)
 {
+	if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
+		return;
+
 	if (acpi_is_wakeup())
 		cbmem_initialize();
 	else
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index eb603f6..bbc5e51 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
 /* SPI code needs malloc/free.
  * Also unknown if writing flash from XIP-flash code is a good idea
  */
-#if !defined(__PRE_RAM__)
+
 /* find the first empty block in the MRC cache area.
  * If there's none, return NULL.
  *
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
 {
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index f89fc0f..2086427 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
 /* SPI code needs malloc/free.
  * Also unknown if writing flash from XIP-flash code is a good idea
  */
-#if !defined(__PRE_RAM__)
+
 /* find the first empty block in the MRC cache area.
  * If there's none, return NULL.
  *
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
 {
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index b1fc692..380b23f 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -316,14 +316,12 @@ void spi_init(void)
 	ich_set_bbar(0);
 }
 
-#ifndef __SMM__
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index afc288a..453a719 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -295,8 +295,6 @@ void spi_init(void)
 	cntlr.preop = &ich9_spi->preop;
 }
 
-#if ENV_RAMSTAGE
-
 static void spi_init_cb(void *unused)
 {
 	spi_init();
@@ -304,8 +302,6 @@ static void spi_init_cb(void *unused)
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
 
-#endif /* ENV_RAMSTAGE */
-
 int spi_claim_bus(struct spi_slave *slave)
 {
 	/* Handled by ICH automatically. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index a75ee83..c159e20 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -312,14 +312,12 @@ void spi_init(void)
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
 
-#if ENV_RAMSTAGE
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index 9a066d5..e5e6b6a 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -18,11 +18,13 @@
  */
 
 #include <string.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <fmap.h>
 #include <ip_checksum.h>
 #include "mrc_cache.h"
+#include "nvm.h"
 
 #define MRC_DATA_ALIGN           0x1000
 #define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache)
 	return __mrc_cache_get_current(&region, cache);
 }
 
-#if ENV_ROMSTAGE
-
-/*
- * romstage code
- */
-
 /* Fill in mrc_saved_data structure with payload. */
 static void mrc_cache_fill(struct mrc_saved_data *cache, void *data,
                            size_t size)
@@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size)
 	return 0;
 }
 
-#else
-
-/*
- * ramstage code
- */
-
-#include <bootstate.h>
-#include "nvm.h"
-
 static int mrc_slot_valid(const struct mrc_data_region *region,
                           const struct mrc_saved_data *slot,
                           const struct mrc_saved_data *to_save)
@@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-
-#endif /* ENV_ROMSTAGE */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 1d3ebf6..5d18012 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -359,14 +359,13 @@ void spi_init(void)
 	bios_cntl &= ~(1 << 5);
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
-#ifndef __SMM__
+
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {


From gerrit at coreboot.org  Wed Sep  2 22:56:20 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 2 Sep 2015 22:56:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: bootstate: remove
	need for #ifdef ENV_RAMSTAGE
References: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+0@gerrit.coreboot.org>
Message-ID: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492

-gerrit

commit 2b3fd6157f1bb07aa97aab7aa625b2aac591d599
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 17:34:04 2015 -0500

    bootstate: remove need for #ifdef ENV_RAMSTAGE
    
    The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
    the current state of the header meant bad build errors in non-ramstage.
    Therefore, people had to #ifdef in the source. Remove that requirement.
    
    Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp1_0/fsp_util.c          |  3 ---
 src/drivers/intel/fsp1_1/fsp_util.c          |  4 ----
 src/include/bootstate.h                      |  8 +++++---
 src/northbridge/intel/haswell/mrccache.c     |  3 +--
 src/northbridge/intel/sandybridge/mrccache.c |  3 +--
 src/soc/intel/baytrail/spi.c                 |  2 --
 src/soc/intel/braswell/spi.c                 |  4 ----
 src/soc/intel/broadwell/spi.c                |  2 --
 src/soc/intel/common/mrc_cache.c             | 19 ++-----------------
 src/southbridge/intel/common/spi.c           |  3 +--
 10 files changed, 10 insertions(+), 41 deletions(-)

diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c
index 9dbd502..f1e0d11 100644
--- a/src/drivers/intel/fsp1_0/fsp_util.c
+++ b/src/drivers/intel/fsp1_0/fsp_util.c
@@ -215,8 +215,6 @@ void * find_fsp_reserved_mem(void *hob_list_ptr)
 }
 #endif /* FSP_RESERVE_MEMORY_SIZE */
 
-#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */
-
 void print_fsp_info(void) {
 
 	if (fsp_header_ptr == NULL)
@@ -349,4 +347,3 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
 /* Update the MRC/fast boot cache as part of the late table writing stage */
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
 			find_fsp_hob_update_mrc, NULL);
-#endif	/* #ifndef __PRE_RAM__ */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 18e8648..bce4337 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header)
 #endif
 }
 
-#if ENV_RAMSTAGE
-
 void fsp_notify(u32 phase)
 {
 	FSP_NOTIFY_PHASE notify_phase_proc;
@@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
 	fsp_notify_boot_state_callback,
 	(void *)EnumInitPhaseReadyToBoot);
 
-#endif	/* ENV_RAMSTAGE */
-
 struct fsp_runtime {
 	uint32_t fih;
 	uint32_t hob_list;
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 4952780..1bbe458 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -19,8 +19,7 @@
 #ifndef BOOTSTATE_H
 #define BOOTSTATE_H
 
-#if !defined(__SMM__) && !defined(__PRE_RAM__)
-
+#include <rules.h>
 #include <string.h>
 #include <stdlib.h>
 #include <stddef.h>
@@ -185,7 +184,11 @@ struct boot_state_init_entry {
 	struct boot_state_callback bscb;
 };
 
+#if ENV_RAMSTAGE
 #define BOOT_STATE_INIT_ATTR  __attribute__ ((used,section (".bs_init")))
+#else
+#define BOOT_STATE_INIT_ATTR  __attribute__ ((unused))
+#endif
 
 #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_)		\
 	static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \
@@ -198,5 +201,4 @@ struct boot_state_init_entry {
 		bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \
 		& func_ ##_## state_ ##_## when_;
 
-#endif
 #endif /* BOOTSTATE_H */
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index eb603f6..bbc5e51 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
 /* SPI code needs malloc/free.
  * Also unknown if writing flash from XIP-flash code is a good idea
  */
-#if !defined(__PRE_RAM__)
+
 /* find the first empty block in the MRC cache area.
  * If there's none, return NULL.
  *
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
 {
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index f89fc0f..2086427 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
 /* SPI code needs malloc/free.
  * Also unknown if writing flash from XIP-flash code is a good idea
  */
-#if !defined(__PRE_RAM__)
+
 /* find the first empty block in the MRC cache area.
  * If there's none, return NULL.
  *
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
 {
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index b1fc692..380b23f 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -316,14 +316,12 @@ void spi_init(void)
 	ich_set_bbar(0);
 }
 
-#ifndef __SMM__
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index afc288a..453a719 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -295,8 +295,6 @@ void spi_init(void)
 	cntlr.preop = &ich9_spi->preop;
 }
 
-#if ENV_RAMSTAGE
-
 static void spi_init_cb(void *unused)
 {
 	spi_init();
@@ -304,8 +302,6 @@ static void spi_init_cb(void *unused)
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
 
-#endif /* ENV_RAMSTAGE */
-
 int spi_claim_bus(struct spi_slave *slave)
 {
 	/* Handled by ICH automatically. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index a75ee83..c159e20 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -312,14 +312,12 @@ void spi_init(void)
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
 
-#if ENV_RAMSTAGE
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index 9a066d5..e5e6b6a 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -18,11 +18,13 @@
  */
 
 #include <string.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <fmap.h>
 #include <ip_checksum.h>
 #include "mrc_cache.h"
+#include "nvm.h"
 
 #define MRC_DATA_ALIGN           0x1000
 #define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache)
 	return __mrc_cache_get_current(&region, cache);
 }
 
-#if ENV_ROMSTAGE
-
-/*
- * romstage code
- */
-
 /* Fill in mrc_saved_data structure with payload. */
 static void mrc_cache_fill(struct mrc_saved_data *cache, void *data,
                            size_t size)
@@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size)
 	return 0;
 }
 
-#else
-
-/*
- * ramstage code
- */
-
-#include <bootstate.h>
-#include "nvm.h"
-
 static int mrc_slot_valid(const struct mrc_data_region *region,
                           const struct mrc_saved_data *slot,
                           const struct mrc_saved_data *to_save)
@@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-
-#endif /* ENV_ROMSTAGE */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 1d3ebf6..5d18012 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -359,14 +359,13 @@ void spi_init(void)
 	bios_cntl &= ~(1 << 5);
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
-#ifndef __SMM__
+
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {


From gerrit at coreboot.org  Thu Sep  3 01:25:04 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 3 Sep 2015 01:25:04 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: bootstate: remove
	need for #ifdef ENV_RAMSTAGE
References: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+0@gerrit.coreboot.org>
Message-ID: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492

-gerrit

commit 3de385ec9641160fa43eaf20f2402e549fb7c070
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 17:34:04 2015 -0500

    bootstate: remove need for #ifdef ENV_RAMSTAGE
    
    The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
    the current state of the header meant bad build errors in non-ramstage.
    Therefore, people had to #ifdef in the source. Remove that requirement.
    
    Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp1_1/fsp_util.c          |  4 ----
 src/include/bootstate.h                      | 10 +++++++---
 src/northbridge/intel/haswell/mrccache.c     |  3 +--
 src/northbridge/intel/sandybridge/mrccache.c |  3 +--
 src/soc/intel/baytrail/spi.c                 |  2 --
 src/soc/intel/braswell/spi.c                 |  4 ----
 src/soc/intel/broadwell/spi.c                |  2 --
 src/soc/intel/common/mrc_cache.c             | 19 ++-----------------
 src/southbridge/intel/common/spi.c           |  3 +--
 9 files changed, 12 insertions(+), 38 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 18e8648..bce4337 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header)
 #endif
 }
 
-#if ENV_RAMSTAGE
-
 void fsp_notify(u32 phase)
 {
 	FSP_NOTIFY_PHASE notify_phase_proc;
@@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
 	fsp_notify_boot_state_callback,
 	(void *)EnumInitPhaseReadyToBoot);
 
-#endif	/* ENV_RAMSTAGE */
-
 struct fsp_runtime {
 	uint32_t fih;
 	uint32_t hob_list;
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 4952780..8dafa04 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -19,8 +19,7 @@
 #ifndef BOOTSTATE_H
 #define BOOTSTATE_H
 
-#if !defined(__SMM__) && !defined(__PRE_RAM__)
-
+#include <rules.h>
 #include <string.h>
 #include <stdlib.h>
 #include <stddef.h>
@@ -173,8 +172,10 @@ int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq);
 void boot_state_current_block(void);
 void boot_state_current_unblock(void);
 
+#if ENV_RAMSTAGE
 /* Entry into the boot state machine. */
 void main(void);
+#endif
 
 /* In order to schedule boot state callbacks at compile-time specify the
  * entries in an array using the BOOT_STATE_INIT_ENTRIES and
@@ -185,7 +186,11 @@ struct boot_state_init_entry {
 	struct boot_state_callback bscb;
 };
 
+#if ENV_RAMSTAGE
 #define BOOT_STATE_INIT_ATTR  __attribute__ ((used,section (".bs_init")))
+#else
+#define BOOT_STATE_INIT_ATTR  __attribute__ ((unused))
+#endif
 
 #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_)		\
 	static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \
@@ -198,5 +203,4 @@ struct boot_state_init_entry {
 		bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \
 		& func_ ##_## state_ ##_## when_;
 
-#endif
 #endif /* BOOTSTATE_H */
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index eb603f6..bbc5e51 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
 /* SPI code needs malloc/free.
  * Also unknown if writing flash from XIP-flash code is a good idea
  */
-#if !defined(__PRE_RAM__)
+
 /* find the first empty block in the MRC cache area.
  * If there's none, return NULL.
  *
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
 {
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index f89fc0f..2086427 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
 /* SPI code needs malloc/free.
  * Also unknown if writing flash from XIP-flash code is a good idea
  */
-#if !defined(__PRE_RAM__)
+
 /* find the first empty block in the MRC cache area.
  * If there's none, return NULL.
  *
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
 {
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index b1fc692..380b23f 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -316,14 +316,12 @@ void spi_init(void)
 	ich_set_bbar(0);
 }
 
-#ifndef __SMM__
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index afc288a..453a719 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -295,8 +295,6 @@ void spi_init(void)
 	cntlr.preop = &ich9_spi->preop;
 }
 
-#if ENV_RAMSTAGE
-
 static void spi_init_cb(void *unused)
 {
 	spi_init();
@@ -304,8 +302,6 @@ static void spi_init_cb(void *unused)
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
 
-#endif /* ENV_RAMSTAGE */
-
 int spi_claim_bus(struct spi_slave *slave)
 {
 	/* Handled by ICH automatically. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index a75ee83..c159e20 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -312,14 +312,12 @@ void spi_init(void)
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
 
-#if ENV_RAMSTAGE
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index 9a066d5..e5e6b6a 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -18,11 +18,13 @@
  */
 
 #include <string.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <fmap.h>
 #include <ip_checksum.h>
 #include "mrc_cache.h"
+#include "nvm.h"
 
 #define MRC_DATA_ALIGN           0x1000
 #define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache)
 	return __mrc_cache_get_current(&region, cache);
 }
 
-#if ENV_ROMSTAGE
-
-/*
- * romstage code
- */
-
 /* Fill in mrc_saved_data structure with payload. */
 static void mrc_cache_fill(struct mrc_saved_data *cache, void *data,
                            size_t size)
@@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size)
 	return 0;
 }
 
-#else
-
-/*
- * ramstage code
- */
-
-#include <bootstate.h>
-#include "nvm.h"
-
 static int mrc_slot_valid(const struct mrc_data_region *region,
                           const struct mrc_saved_data *slot,
                           const struct mrc_saved_data *to_save)
@@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-
-#endif /* ENV_ROMSTAGE */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 1d3ebf6..5d18012 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -359,14 +359,13 @@ void spi_init(void)
 	bios_cntl &= ~(1 << 5);
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
-#ifndef __SMM__
+
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {


From gerrit at coreboot.org  Thu Sep  3 05:28:29 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Thu, 3 Sep 2015 05:28:29 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: mc_tcu3: Adjust
	gpio settings
References: <I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a+0@gerrit.coreboot.org>
Message-ID: <I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a+2@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11489

-gerrit

commit ff8f829035a5722a77b32c4d35f68aa4a0b86af1
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Wed Sep 2 15:13:04 2015 +0200

    mc_tcu3: Adjust gpio settings
    
    Adjust gpio settings due to hardware change.
    
    Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/mainboard/siemens/mc_tcu3/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c
index 33adc00..ab1c59c 100644
--- a/src/mainboard/siemens/mc_tcu3/gpio.c
+++ b/src/mainboard/siemens/mc_tcu3/gpio.c
@@ -173,7 +173,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[07]		PMC_SUSCLK[3]		RESERVED	RESERVED	RESERVED		 */
 	GPIO_INPUT_PU_10K,	/* GPIO_S5[08]		RESERVED		RESERVED	RESERVED	RESERVED 		 */
 	GPIO_INPUT_PU_10K,	/* GPIO_S5[09]		RESERVED		RESERVED	ESERVED		RESERVED		 */
-	GPIO_INPUT_PU_10K,	/* GPIO_S5[10]		RESERVED		RESERVED	RESERVED				 */
+	GPIO_OUT_HIGH,		/* GPIO_S5[10]		RESERVED		RESERVED	RESERVED				 */
 	GPIO_DEFAULT,		/* PMC_SUSPWRDNACK	GPIO_S5[11]			-				-		 */
 	GPIO_DEFAULT,		/* PMC_SUSCLK[0]	GPIO_S5[12]			-				-		 */
 	GPIO_DEFAULT,		/* RESERVED		GPIO_S5[13]			-				-		 */
@@ -194,7 +194,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 	GPIO_DEFAULT,		/* GPIO_S5[28]		RESERVED		RESERVED	RESERVED	RESERVED		 */
 	GPIO_DEFAULT,		/* GPIO_S5[29]		RESERVED		RESERVED	RESERVED	RESERVED		 */
 	GPIO_DEFAULT,		/* GPIO_S5[30]		RESERVED		RESERVED	RESERVED	RESERVED		 */
-	GPIO_INPUT_PD_10K,	/* GPIO_S5[31]		USB_ULPI_CLK		RESERVED	RESERVED				 */
+	GPIO_OUT_LOW,		/* GPIO_S5[31]		USB_ULPI_CLK		RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[32]		USB_ULPI_DATA[0]	RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[33]		USB_ULPI_DATA[1]	RESERVED	RESERVED				 */
 	GPIO_INPUT_PD_10K,	/* GPIO_S5[34]		USB_ULPI_DATA[2]	RESERVED	RESERVED				 */


From gerrit at coreboot.org  Thu Sep  3 06:58:57 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 3 Sep 2015 06:58:57 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: remove
	cpu_incs as romstage Make variable
References: <I8dc0631f8253c21c670f2f02928225ed5b869ce6+0@gerrit.coreboot.org>
Message-ID: <I8dc0631f8253c21c670f2f02928225ed5b869ce6+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11494

-gerrit

commit 1b41b6ae1d6557ff64e7376b1e702f60582e668b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 22:23:11 2015 -0500

    x86: remove cpu_incs as romstage Make variable
    
    When building up which files to include in romstage there
    were both 'cpu_incs' and 'cpu_incs-y' which were used to
    generate crt0.S. Remove the former to settle on cpu_incs-y
    as the way to be included.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. No include file changes.
    
    Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                        | 1 -
 src/cpu/amd/agesa/Makefile.inc                   | 2 +-
 src/cpu/amd/geode_gx2/Makefile.inc               | 2 +-
 src/cpu/amd/geode_lx/Makefile.inc                | 2 +-
 src/cpu/amd/pi/Makefile.inc                      | 2 +-
 src/cpu/amd/socket_754/Makefile.inc              | 2 +-
 src/cpu/amd/socket_939/Makefile.inc              | 2 +-
 src/cpu/amd/socket_940/Makefile.inc              | 2 +-
 src/cpu/amd/socket_AM2/Makefile.inc              | 2 +-
 src/cpu/amd/socket_AM2r2/Makefile.inc            | 2 +-
 src/cpu/amd/socket_AM3/Makefile.inc              | 2 +-
 src/cpu/amd/socket_ASB2/Makefile.inc             | 2 +-
 src/cpu/amd/socket_C32/Makefile.inc              | 2 +-
 src/cpu/amd/socket_F/Makefile.inc                | 2 +-
 src/cpu/amd/socket_F_1207/Makefile.inc           | 2 +-
 src/cpu/amd/socket_S1G1/Makefile.inc             | 2 +-
 src/cpu/intel/haswell/Makefile.inc               | 2 +-
 src/cpu/intel/model_106cx/Makefile.inc           | 2 +-
 src/cpu/intel/model_2065x/Makefile.inc           | 2 +-
 src/cpu/intel/model_206ax/Makefile.inc           | 2 +-
 src/cpu/intel/slot_1/Makefile.inc                | 2 +-
 src/cpu/intel/socket_BGA956/Makefile.inc         | 2 +-
 src/cpu/intel/socket_FC_PGA370/Makefile.inc      | 2 +-
 src/cpu/intel/socket_LGA771/Makefile.inc         | 2 +-
 src/cpu/intel/socket_PGA370/Makefile.inc         | 2 +-
 src/cpu/intel/socket_mFCBGA479/Makefile.inc      | 2 +-
 src/cpu/intel/socket_mFCPGA478/Makefile.inc      | 2 +-
 src/cpu/intel/socket_mPGA479M/Makefile.inc       | 2 +-
 src/cpu/via/c7/Makefile.inc                      | 2 +-
 src/cpu/via/nano/Makefile.inc                    | 2 +-
 src/drivers/intel/fsp1_0/Makefile.inc            | 4 +---
 src/mainboard/emulation/qemu-i440fx/Makefile.inc | 2 +-
 src/mainboard/emulation/qemu-q35/Makefile.inc    | 2 +-
 src/northbridge/intel/i5000/Makefile.inc         | 2 +-
 src/soc/intel/baytrail/romstage/Makefile.inc     | 4 ++--
 src/soc/intel/broadwell/romstage/Makefile.inc    | 2 +-
 36 files changed, 36 insertions(+), 39 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3a8d8d5..a9d708d 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -147,7 +147,6 @@ ifeq ($(CONFIG_SSE),y)
 crt0s += $(src)/cpu/x86/sse_enable.inc
 endif
 
-crt0s += $(cpu_incs)
 crt0s += $(cpu_incs-y)
 
 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 153b2db..89af28c 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -27,7 +27,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
 romstage-y += s3_resume.c
 ramstage-y += s3_mtrr.c
 
-cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
 
 romstage-y += heapmanager.c
 ramstage-y += heapmanager.c
diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc
index be9e1be..1580f74 100644
--- a/src/cpu/amd/geode_gx2/Makefile.inc
+++ b/src/cpu/amd/geode_gx2/Makefile.inc
@@ -6,7 +6,7 @@ subdirs-y += ../../x86/smm
 ramstage-y += geode_gx2_init.c
 ramstage-y += cpubug.c
 
-cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
 
 cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
 vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc
index 9edb332..22a3fda 100644
--- a/src/cpu/amd/geode_lx/Makefile.inc
+++ b/src/cpu/amd/geode_lx/Makefile.inc
@@ -6,7 +6,7 @@ subdirs-y += ../../x86/smm
 ramstage-y += geode_lx_init.c
 ramstage-y += cpubug.c
 
-cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
 
 cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
 vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index 5a407b2..2b9c3ff 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -25,7 +25,7 @@ romstage-y += s3_resume.c
 ramstage-y += s3_resume.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 
-cpu_incs += $(src)/cpu/amd/pi/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc
 
 romstage-y += heapmanager.c
 ramstage-y += heapmanager.c
diff --git a/src/cpu/amd/socket_754/Makefile.inc b/src/cpu/amd/socket_754/Makefile.inc
index 264fd6c..38421d7 100644
--- a/src/cpu/amd/socket_754/Makefile.inc
+++ b/src/cpu/amd/socket_754/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_939/Makefile.inc b/src/cpu/amd/socket_939/Makefile.inc
index 264fd6c..38421d7 100644
--- a/src/cpu/amd/socket_939/Makefile.inc
+++ b/src/cpu/amd/socket_939/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_940/Makefile.inc b/src/cpu/amd/socket_940/Makefile.inc
index 264fd6c..38421d7 100644
--- a/src/cpu/amd/socket_940/Makefile.inc
+++ b/src/cpu/amd/socket_940/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_AM2/Makefile.inc b/src/cpu/amd/socket_AM2/Makefile.inc
index 264fd6c..38421d7 100644
--- a/src/cpu/amd/socket_AM2/Makefile.inc
+++ b/src/cpu/amd/socket_AM2/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_AM2r2/Makefile.inc b/src/cpu/amd/socket_AM2r2/Makefile.inc
index 327e4a1..3675af4 100644
--- a/src/cpu/amd/socket_AM2r2/Makefile.inc
+++ b/src/cpu/amd/socket_AM2r2/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_AM3/Makefile.inc b/src/cpu/amd/socket_AM3/Makefile.inc
index 327e4a1..3675af4 100644
--- a/src/cpu/amd/socket_AM3/Makefile.inc
+++ b/src/cpu/amd/socket_AM3/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_ASB2/Makefile.inc b/src/cpu/amd/socket_ASB2/Makefile.inc
index 327e4a1..3675af4 100644
--- a/src/cpu/amd/socket_ASB2/Makefile.inc
+++ b/src/cpu/amd/socket_ASB2/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_C32/Makefile.inc b/src/cpu/amd/socket_C32/Makefile.inc
index 327e4a1..3675af4 100644
--- a/src/cpu/amd/socket_C32/Makefile.inc
+++ b/src/cpu/amd/socket_C32/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_F/Makefile.inc b/src/cpu/amd/socket_F/Makefile.inc
index 264fd6c..38421d7 100644
--- a/src/cpu/amd/socket_F/Makefile.inc
+++ b/src/cpu/amd/socket_F/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_F_1207/Makefile.inc b/src/cpu/amd/socket_F_1207/Makefile.inc
index 8c5ff3d..b74862e 100644
--- a/src/cpu/amd/socket_F_1207/Makefile.inc
+++ b/src/cpu/amd/socket_F_1207/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_S1G1/Makefile.inc b/src/cpu/amd/socket_S1G1/Makefile.inc
index 5ad59cd..0babff0 100644
--- a/src/cpu/amd/socket_S1G1/Makefile.inc
+++ b/src/cpu/amd/socket_S1G1/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm
 
-cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index 4297122..a4a9c34 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -16,7 +16,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
 
-cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc
 
 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index dbc093d..8aa5a5e 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -1,5 +1,5 @@
 ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
-cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 3da26dd..1b5d2ba 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -19,4 +19,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 
-cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6e0dcf6..6f12756 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -8,4 +8,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 
-cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
index d480f78..1487f5e 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -32,4 +32,4 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
-cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 6019972..2325bb9 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -9,4 +9,4 @@ subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
 # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
-cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_FC_PGA370/Makefile.inc b/src/cpu/intel/socket_FC_PGA370/Makefile.inc
index 85454ac..d9bb227 100644
--- a/src/cpu/intel/socket_FC_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_FC_PGA370/Makefile.inc
@@ -26,4 +26,4 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
-cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc
index 101fd04..8235fc5 100644
--- a/src/cpu/intel/socket_LGA771/Makefile.inc
+++ b/src/cpu/intel/socket_LGA771/Makefile.inc
@@ -8,4 +8,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
-cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc
index 3f5dfd0..98b4394 100644
--- a/src/cpu/intel/socket_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_PGA370/Makefile.inc
@@ -26,4 +26,4 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
-cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
index 9e1444d..e247c09 100644
--- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc
+++ b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
@@ -6,4 +6,4 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
-cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
index fa03f93..749f6ab 100644
--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -11,4 +11,4 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc
index 7160894..abade4e 100644
--- a/src/cpu/intel/socket_mPGA479M/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc
@@ -9,4 +9,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
-cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
diff --git a/src/cpu/via/c7/Makefile.inc b/src/cpu/via/c7/Makefile.inc
index 417d762..8c13d91 100644
--- a/src/cpu/via/c7/Makefile.inc
+++ b/src/cpu/via/c7/Makefile.inc
@@ -7,4 +7,4 @@ subdirs-y += ../../intel/microcode
 
 ramstage-y += c7_init.c
 
-cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index b5d00ec..d3df3fb 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -30,4 +30,4 @@ ramstage-y += update_ucode.c
 # the rest of coreboot.
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
 
-cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index a29bf32..ddc6bef 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -25,9 +25,7 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
 CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
 
-ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y)
-cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
-endif
+cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)
 cbfs-files-y += fsp.bin
diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
index 7423b2b..f9cf252 100644
--- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc
+++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
@@ -1,3 +1,3 @@
-cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
+cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
 ramstage-y += northbridge.c
 ramstage-y += fw_cfg.c
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc
index 0a0f869..fc4374c 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.inc
+++ b/src/mainboard/emulation/qemu-q35/Makefile.inc
@@ -1,3 +1,3 @@
-cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
+cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
 ramstage-y += ../qemu-i440fx/northbridge.c
 ramstage-y += ../qemu-i440fx/fw_cfg.c
diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc
index 53602ec..7265917 100644
--- a/src/northbridge/intel/i5000/Makefile.inc
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -21,6 +21,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y)
 
 ramstage-y += northbridge.c
 romstage-y += raminit.c
-cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S
+cpu_incs-y += src/northbridge/intel/i5000/halt_second_bsp.S
 
 endif
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc
index 345037d..5086a4e 100644
--- a/src/soc/intel/baytrail/romstage/Makefile.inc
+++ b/src/soc/intel/baytrail/romstage/Makefile.inc
@@ -1,7 +1,7 @@
-cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc
+cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc
 romstage-y += romstage.c
 romstage-y += raminit.c
 romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
 romstage-y += gfx.c
 romstage-y += pmc.c
-romstage-y += early_spi.c
\ No newline at end of file
+romstage-y += early_spi.c
diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc
index ae0f980..1617812 100644
--- a/src/soc/intel/broadwell/romstage/Makefile.inc
+++ b/src/soc/intel/broadwell/romstage/Makefile.inc
@@ -1,4 +1,4 @@
-cpu_incs += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
+cpu_incs-y += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
 
 romstage-y += cpu.c
 romstage-y += pch.c


From gerrit at coreboot.org  Thu Sep  3 06:58:59 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 3 Sep 2015 06:58:59 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: add
	bootblock.S to bind program flow and ordering
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit 308ddf511ad634cf6fe9e4f267ecc42e95c27d1e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: add bootblock.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the bootblock code by the order of files added to
    the bootblock_inc variable. Those files were then
    concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S is added that can be built using
    the default file rules. CHIPSET_BOOTBLOCK_INCLUDE
    is introduced in order to allow the chipset code
    to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 35 +++---------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 31 files changed, 117 insertions(+), 48 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..20e1596 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -75,22 +75,11 @@ ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
 bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
 endif
 
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
-
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency as well as ensuring it can be located with #include.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
@@ -102,25 +91,13 @@ $(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(objgenerated)/bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
 	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..f90adfa
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generaed by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions the begining of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Thu Sep  3 08:20:38 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 3 Sep 2015 08:20:38 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: mc_tcu3:
	Extend hwinfo.hex and remove version.hex.
References: <I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7+0@gerrit.coreboot.org>
Message-ID: <E1ZXPl8-0002Hm-So@mail.coreboot.org>

the following patch was just integrated into master:
commit 69ddcf1b6eafd7d12f52d64249a38fb9ed7abfd6
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Wed Sep 2 11:00:34 2015 +0200

    mc_tcu3: Extend hwinfo.hex and remove version.hex.
    
    1. Update hwinfo.hex (add dummy data and update checksums).
    2. Delete version.hex from mainboard directory. It can be added
       in site-local if needed.
    
    Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
    Reviewed-on: http://review.coreboot.org/11484
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Mario Scheithauer <mario.scheithauer at siemens.com>


See http://review.coreboot.org/11484 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep  3 09:10:45 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 3 Sep 2015 09:10:45 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: bootmode: add
	display_init_required()
References: <I403213e22c0e621e148773597a550addfbaf3f7e+0@gerrit.coreboot.org>
Message-ID: <I403213e22c0e621e148773597a550addfbaf3f7e+5@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490

-gerrit

commit eb1eefb334905f6f28ac3bc4e2be21a32a64182d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 09:21:36 2015 -0500

    bootmode: add display_init_required()
    
    Some of the Chrome OS boards were directly calling vboot
    called in some form after contorting around #ifdef preprocessor
    macros. The reasoning is that Chrome OS doesn't always do display
    initialization during startup. It's runtime dependent. While
    this is a requirement that doesn't mean vboot functions should be
    sprinkled around in the mainboard and chipset code. Instead provide
    one function, display_init_required(), that provides the policy
    for determining display initialization action. For Chrome OS
    devices this function honors vboot_skip_display_init() and all
    other configurations default to initializing display.
    
    Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bootmode.h                    |  2 ++
 src/lib/bootmode.c                        | 12 ++++++++++--
 src/mainboard/google/rush/mainboard.c     |  7 +++----
 src/mainboard/google/rush_ryu/mainboard.c |  3 ++-
 src/mainboard/google/smaug/mainboard.c    | 12 +++---------
 src/soc/nvidia/tegra124/soc.c             |  8 ++++----
 src/soc/nvidia/tegra132/soc.c             | 13 +++++++------
 src/soc/nvidia/tegra210/soc.c             | 13 +++++++------
 src/soc/rockchip/rk3288/soc.c             |  8 ++++----
 9 files changed, 42 insertions(+), 36 deletions(-)

diff --git a/src/include/bootmode.h b/src/include/bootmode.h
index ff562d5..96c789b 100644
--- a/src/include/bootmode.h
+++ b/src/include/bootmode.h
@@ -30,6 +30,8 @@ int get_wipeout_mode_switch(void);
 int get_lid_switch(void);
 
 
+/* Return 1 if display initialization is required. 0 if not. */
+int display_init_required(void);
 int gfx_get_init_done(void);
 void gfx_set_init_done(int done);
 
diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index c7e4927..f2ff72a 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -19,9 +19,7 @@
 
 #include <rules.h>
 #include <bootmode.h>
-#if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE
 #include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 #if CONFIG_BOOTMODE_STRAPS
 int developer_mode_enabled(void)
@@ -78,3 +76,13 @@ void gfx_set_init_done(int done)
 	gfx_init_done = done;
 }
 #endif
+
+int display_init_required(void)
+{
+	/* For Chrome OS always honor vboot_skip_display_init(). */
+	if (IS_ENABLED(CONFIG_CHROMEOS))
+		return !vboot_skip_display_init();
+
+	/* By default always initialize display. */
+	return 1;
+}
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index cffb7ac..aa67ec2 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -18,7 +18,9 @@
  */
 
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <memrange.h>
 #include <soc/addressmap.h>
@@ -32,9 +34,6 @@
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <delay.h>
-
 static const struct pad_config sdmmc3_pad[] = {
 	/* MMC3(SDCARD) */
 	PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
@@ -184,7 +183,7 @@ static void mainboard_init(device_t dev)
 	i2c_init(I2C1_BUS);		/* for max98090 codec */
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 863ab52..1af7395 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -19,6 +19,7 @@
 
 #include <arch/mmu.h>
 #include <boardid.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <cbmem.h>
 #include <delay.h>
@@ -281,7 +282,7 @@ static void mainboard_init(device_t dev)
 	soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
 
 	/* if panel needs to bringup */
-	if (!vboot_skip_display_init())
+	if (display_init_required())
 		configure_display_blocks();
 }
 
diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c
index 1cf4d32..6e3393d 100644
--- a/src/mainboard/google/smaug/mainboard.c
+++ b/src/mainboard/google/smaug/mainboard.c
@@ -20,7 +20,9 @@
 
 #include <arch/io.h>
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/i2c.h>
 #include <soc/addressmap.h>
@@ -36,12 +38,6 @@
 #include <soc/pmc.h>
 #include <soc/power.h>
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
-#include <vendorcode/google/chromeos/vboot_handoff.h>
-#include <vendorcode/google/chromeos/vboot2/misc.h>
-#endif
-#include <delay.h>
-
 #include "gpio.h"
 #include "pmic.h"
 
@@ -202,9 +198,7 @@ static void mainboard_init(device_t dev)
 	setup_audio();
 
 	/* if panel needs to bringup */
-#if IS_ENABLED(CONFIG_CHROMEOS)
-	if (!vboot_skip_display_init())
-#endif
+	if (display_init_required())
 		configure_display_blocks();
 
 	powergate_unused_partitions();
diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c
index 406457b..c38232d 100644
--- a/src/soc/nvidia/tegra124/soc.c
+++ b/src/soc/nvidia/tegra124/soc.c
@@ -20,13 +20,13 @@
  */
 
 #include <arch/io.h>
+#include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 #include <soc/sdram.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -53,10 +53,10 @@ static void soc_enable(device_t dev)
 
 static void soc_init(device_t dev)
 {
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		display_startup(dev);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 	printk(BIOS_INFO, "CPU: Tegra124\n");
 }
 
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 4ca866c..a65f36d 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -34,7 +35,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
@@ -101,12 +101,13 @@ static void soc_init(device_t dev)
 	/* Lock down VPR */
 	lock_down_vpr();
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index 9e67531..981b09c 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -22,6 +22,7 @@
 #include <arch/cache.h>
 #include <arch/spintable.h>
 #include <cpu/cpu.h>
+#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -35,7 +36,6 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/sdram.h>
 #include <soc/sdram_configs.h>
 
@@ -92,12 +92,13 @@ static void soc_init(device_t dev)
 	spintable_init((void *)cfg->spintable_addr);
 	arch_initialize_cpus(dev, &cntrl_ops);
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return;
+
+	if (display_init_required())
 		display_startup(dev);
-#endif
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static void soc_noop(device_t dev)
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index a13086a..a9484b4 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/cache.h>
+#include <bootmode.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>
@@ -30,18 +31,17 @@
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "chip.h"
 
 static void soc_init(device_t dev)
 {
 	ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
-	if (vboot_skip_display_init())
-		printk(BIOS_INFO, "Skipping display init.\n");
-	else
+	if (display_init_required())
 		rk_display_init(dev, (uintptr_t)_framebuffer,
 				_framebuffer_size);
+	else
+		printk(BIOS_INFO, "Skipping display init.\n");
 }
 
 static struct device_operations soc_ops = {


From gerrit at coreboot.org  Thu Sep  3 09:10:46 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 3 Sep 2015 09:10:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos: Allow
	disabling vboot firmware verification when ChromeOS is enabled
References: <Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb+0@gerrit.coreboot.org>
Message-ID: <Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb+2@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11143

-gerrit

commit cad659a2f605df651841d052e2d7d2984be6553a
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Sun Aug 9 10:23:38 2015 +0200

    chromeos: Allow disabling vboot firmware verification when ChromeOS is enabled
    
    Some ChromeOS bindings might be wanted without using vboot verification, for
    instance to boot up depthcharge from the version of Coreboot installed in the
    write-protected part of the SPI flash (without jumping to a RW firmware).
    
    Vboot firmware verification is still selected by default when ChromeOS is
    enabled, but this allows more flexibility since vboot firmware verification is
    no longer a hard requirement for ChromeOS (that this particular use case still
    allows booting ChromeOS).
    
    In the future, it would make sense to have all the separate components that
    CONFIG_CHROMEOS enables have their own config options, so that they can be
    enabled separately.
    
    Change-Id: Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/vendorcode/google/chromeos/Kconfig        | 2 +-
 src/vendorcode/google/chromeos/vboot2/Kconfig | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 8309d19..694e0d7 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -31,7 +31,6 @@ config CHROMEOS
 	select BOOTMODE_STRAPS
 	select ELOG
 	select COLLECT_TIMESTAMPS
-	select VBOOT_VERIFY_FIRMWARE
 	help
 	  Enable ChromeOS specific features like the GPIO sub table in
 	  the coreboot table. NOTE: Enabling this option on an unsupported
@@ -129,6 +128,7 @@ config VIRTUAL_DEV_SWITCH
 
 config VBOOT_VERIFY_FIRMWARE
 	bool "Verify firmware with vboot."
+	default y if CHROMEOS
 	default n
 	depends on HAVE_HARD_RESET
 	help
diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig
index c5c46e5..736dee6 100644
--- a/src/vendorcode/google/chromeos/vboot2/Kconfig
+++ b/src/vendorcode/google/chromeos/vboot2/Kconfig
@@ -16,6 +16,8 @@
 ## Foundation, Inc.
 ##
 
+if VBOOT_VERIFY_FIRMWARE
+
 config VBOOT_STARTS_IN_BOOTBLOCK
 	bool "Vboot starts verifying in bootblock"
 	default n
@@ -126,3 +128,5 @@ config VBOOT_DYNAMIC_WORK_BUFFER
 	  ram to allocate the vboot work buffer. That means vboot verification
 	  is after memory init and requires main memory to back the work
 	  buffer.
+
+endif # VBOOT_VERIFY_FIRMWARE


From gerrit at coreboot.org  Thu Sep  3 09:33:25 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 3 Sep 2015 09:33:25 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: chromeos: vboot
	prefix removal on sw write protect state function
References: <I47ce31530a03f6749e0f370e5d868466318b3bb6+0@gerrit.coreboot.org>
Message-ID: <I47ce31530a03f6749e0f370e5d868466318b3bb6+1@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11496

-gerrit

commit 42f19c8cbefcb350e446a983a7d5a58446fccede
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:27:27 2015 +0200

    chromeos: vboot prefix removal on sw write protect state function
    
    This removes the vboot prefix to the vboot_get_sw_write_protect function, since
    it is called from soc code and doesn't really have to be tied to vboot.
    
    Its name is also refactored to be consistent with the previous definition of
    get_write_protect_state.
    
    Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/soc/intel/baytrail/romstage/romstage.c            | 2 +-
 src/soc/intel/broadwell/romstage/romstage.c           | 2 +-
 src/soc/intel/skylake/romstage/romstage.c             | 2 +-
 src/vendorcode/google/chromeos/chromeos.c             | 2 +-
 src/vendorcode/google/chromeos/chromeos.h             | 2 +-
 src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 1b93eb6..dbd69be 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -363,7 +363,7 @@ void ramstage_cache_invalid(void)
 }
 
 #if CONFIG_CHROMEOS
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 	/* Return unprotected status if status read fails. */
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 27fb0f2..bc8cb3f 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -148,7 +148,7 @@ void ramstage_cache_invalid(void)
 }
 
 #if CONFIG_CHROMEOS
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 	/* Return unprotected status if status read fails. */
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 91a496e..e9b7243 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -67,7 +67,7 @@ void soc_romstage_init(struct romstage_params *params)
 }
 
 #if IS_ENABLED(CONFIG_CHROMEOS)
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index 0737267..c2190b7 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -65,7 +65,7 @@ void __attribute__((weak)) save_chromeos_gpios(void)
 	// Can be implemented by a mainboard
 }
 
-int __attribute__((weak)) vboot_get_sw_write_protect(void)
+int __attribute__((weak)) get_sw_write_protect_state(void)
 {
 	// Can be implemented by a platform / mainboard
 	return 0;
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index c7048dd..d3fb8e9 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -68,7 +68,7 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
 }
 #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
 
-int vboot_get_sw_write_protect(void);
+int get_sw_write_protect_state(void);
 
 #include "gnvs.h"
 struct device;
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index c8ba114..8e12fdc 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -61,7 +61,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff,
 
 	if (get_write_protect_state())
 		vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED;
-	if (vboot_get_sw_write_protect())
+	if (get_sw_write_protect_state())
 		vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED;
 
 	if (vb2_sd->recovery_reason) {


From gerrit at coreboot.org  Thu Sep  3 09:55:33 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 3 Sep 2015 09:55:33 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos: vboot
	prefix removal on sw write protect state function
References: <I47ce31530a03f6749e0f370e5d868466318b3bb6+0@gerrit.coreboot.org>
Message-ID: <I47ce31530a03f6749e0f370e5d868466318b3bb6+2@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11496

-gerrit

commit af123cd6799f109afcb8758be348e84cb51bc907
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:27:27 2015 +0200

    chromeos: vboot prefix removal on sw write protect state function
    
    This removes the vboot prefix to the vboot_get_sw_write_protect function, since
    it is called from soc code and doesn't really have to be tied to vboot.
    
    Its name is also refactored to be consistent with the previous definition of
    get_write_protect_state.
    
    Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/soc/intel/baytrail/romstage/romstage.c            | 2 +-
 src/soc/intel/broadwell/romstage/romstage.c           | 2 +-
 src/soc/intel/skylake/romstage/romstage.c             | 2 +-
 src/vendorcode/google/chromeos/chromeos.c             | 2 +-
 src/vendorcode/google/chromeos/chromeos.h             | 2 +-
 src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 1b93eb6..dbd69be 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -363,7 +363,7 @@ void ramstage_cache_invalid(void)
 }
 
 #if CONFIG_CHROMEOS
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 	/* Return unprotected status if status read fails. */
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 27fb0f2..bc8cb3f 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -148,7 +148,7 @@ void ramstage_cache_invalid(void)
 }
 
 #if CONFIG_CHROMEOS
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 	/* Return unprotected status if status read fails. */
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 91a496e..e9b7243 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -67,7 +67,7 @@ void soc_romstage_init(struct romstage_params *params)
 }
 
 #if IS_ENABLED(CONFIG_CHROMEOS)
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index 0737267..c2190b7 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -65,7 +65,7 @@ void __attribute__((weak)) save_chromeos_gpios(void)
 	// Can be implemented by a mainboard
 }
 
-int __attribute__((weak)) vboot_get_sw_write_protect(void)
+int __attribute__((weak)) get_sw_write_protect_state(void)
 {
 	// Can be implemented by a platform / mainboard
 	return 0;
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index c7048dd..d3fb8e9 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -68,7 +68,7 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
 }
 #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
 
-int vboot_get_sw_write_protect(void);
+int get_sw_write_protect_state(void);
 
 #include "gnvs.h"
 struct device;
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index c8ba114..8e12fdc 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -61,7 +61,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff,
 
 	if (get_write_protect_state())
 		vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED;
-	if (vboot_get_sw_write_protect())
+	if (get_sw_write_protect_state())
 		vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED;
 
 	if (vb2_sd->recovery_reason) {


From gerrit at coreboot.org  Thu Sep  3 09:55:34 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 3 Sep 2015 09:55:34 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: chromeos:
	vboot-related functions move to common vboot code
References: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+0@gerrit.coreboot.org>
Message-ID: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+1@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11497

-gerrit

commit 1573fcd63a77bf1bc11c9154a84e3b0f182836b1
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:41:14 2015 +0200

    chromeos: vboot-related functions move to common vboot code
    
    This moves a few vboot-prefixed functions that were defined in chromeos.c to
    vboot_common.c, since those are only relevant to vboot and depend on the vboot
    handoff data.
    
    Thus, the actual definitions of these functions will only be declared when
    CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling
    vboot_skip_display_init in bootmode was also adapted.
    
    Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/lib/bootmode.c                            |  2 +-
 src/vendorcode/google/chromeos/chromeos.c     | 32 ---------------------------
 src/vendorcode/google/chromeos/chromeos.h     | 10 ++++-----
 src/vendorcode/google/chromeos/vboot_common.c | 27 ++++++++++++++++++++++
 4 files changed, 33 insertions(+), 38 deletions(-)

diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index f2ff72a..d0aa40e 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -80,7 +80,7 @@ void gfx_set_init_done(int done)
 int display_init_required(void)
 {
 	/* For Chrome OS always honor vboot_skip_display_init(). */
-	if (IS_ENABLED(CONFIG_CHROMEOS))
+	if (IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE))
 		return !vboot_skip_display_init();
 
 	/* By default always initialize display. */
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index c2190b7..4864b8c 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -20,38 +20,6 @@
 #include <stddef.h>
 #include <string.h>
 #include "chromeos.h"
-#include <boot/coreboot_tables.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include "vboot_handoff.h"
-
-static int vboot_handoff_flag(uint32_t flag)
-{
-	struct vboot_handoff *vbho;
-
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
-
-	if (vbho == NULL)
-		return 0;
-
-	return !!(vbho->init_params.out_flags & flag);
-}
-
-int vboot_skip_display_init(void)
-{
-	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
-}
-
-int vboot_enable_developer(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
-}
-
-int vboot_enable_recovery(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
-}
 
 int __attribute__((weak)) clear_recovery_mode_switch(void)
 {
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index d3fb8e9..b0356ac 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -45,15 +45,10 @@ void elog_add_boot_reason(void);
 /* functions implemented in watchdog.c */
 void elog_add_watchdog_reset(void);
 void reboot_from_watchdog(void);
-
-int vboot_enable_developer(void);
-int vboot_enable_recovery(void);
-int vboot_skip_display_init(void);
 #else
 static inline void elog_add_boot_reason(void) { return; }
 static inline void elog_add_watchdog_reset(void) { return; }
 static inline void reboot_from_watchdog(void) { return; }
-static inline int vboot_skip_display_init(void) { return 0; }
 #endif /* CONFIG_CHROMEOS */
 
 struct romstage_handoff;
@@ -61,11 +56,16 @@ struct romstage_handoff;
 #if CONFIG_VBOOT_VERIFY_FIRMWARE
 /* Returns 0 on success < 0 on error. */
 int vboot_get_handoff_info(void **addr, uint32_t *size);
+
+int vboot_enable_developer(void);
+int vboot_enable_recovery(void);
+int vboot_skip_display_init(void);
 #else /* CONFIG_VBOOT_VERIFY_FIRMWARE */
 static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
 {
 	return -1;
 }
+static inline int vboot_skip_display_init(void) { return 0; }
 #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
 
 int get_sw_write_protect_state(void);
diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 2fd29b6..1c216d0 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -55,6 +55,33 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 	return 0;
 }
 
+static int vboot_handoff_flag(uint32_t flag)
+{
+	struct vboot_handoff *vbho;
+
+	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
+
+	if (vbho == NULL)
+		return 0;
+
+	return !!(vbho->init_params.out_flags & flag);
+}
+
+int vboot_skip_display_init(void)
+{
+	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
+}
+
+int vboot_enable_developer(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
+}
+
+int vboot_enable_recovery(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
+}
+
 void vboot_reboot(void)
 {
 	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))


From gerrit at coreboot.org  Thu Sep  3 09:55:35 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 3 Sep 2015 09:55:35 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: chromeos:
	vboot_common: Avoid code duplication when grabbing the handoff info
References: <I28f1decce98f988f90c446a3a0dbe7409d714527+0@gerrit.coreboot.org>
Message-ID: <I28f1decce98f988f90c446a3a0dbe7409d714527+1@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11498

-gerrit

commit dac52e6563de6926c32854c9a1de6daea7676849
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:44:56 2015 +0200

    chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
    
    vboot_handoff_flag was duplicating the logic to grab the handoff info, that is
    already made available with vboot_get_handoff_info.
    This uses vboot_get_handoff_info in vboot_handoff_flag instead.
    
    Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/vendorcode/google/chromeos/vboot_common.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 1c216d0..74b95cd 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -57,11 +57,13 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 
 static int vboot_handoff_flag(uint32_t flag)
 {
-	struct vboot_handoff *vbho;
+	struct vboot_handoff *vbho = NULL;
+	uint32_t size = 0;
+	int ret;
 
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
+	ret = vboot_get_handoff_info((void **)&vbho, &size);
 
-	if (vbho == NULL)
+	if (ret || vbho == NULL)
 		return 0;
 
 	return !!(vbho->init_params.out_flags & flag);


From gerrit at coreboot.org  Thu Sep  3 23:05:09 2015
From: gerrit at coreboot.org (Alexander Couzens (lynxis@fe80.eu))
Date: Thu, 3 Sep 2015 23:05:09 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: SeaBIOS: update
	stable release from 1.7.5 to 1.8.2
References: <Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101+0@gerrit.coreboot.org>
Message-ID: <Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101+2@gerrit.coreboot.org>

Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11479

-gerrit

commit 9baf57ec1fb6ddee9bbb45a5a02143b0d7ff57d0
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Wed Sep 2 00:02:56 2015 +0200

    SeaBIOS: update stable release from 1.7.5 to 1.8.2
    
    Several USB timing fixes for USB controllers on real hardware
    Initial support for USB3 hubs
    Initial support for SD cards (on QEMU only)
    Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG only)
    SeaVGABIOS improvements:
     Added cursor emulation to coreboot native init vgabios (cbvga)
     Added support for read character calls when in graphics mode
    
    Change-Id: Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 payloads/external/SeaBIOS/Kconfig      | 2 +-
 payloads/external/SeaBIOS/Makefile.inc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
index 699b986..6224697 100644
--- a/payloads/external/SeaBIOS/Kconfig
+++ b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.7.5"
+	bool "1.8.2"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER
diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index 7fb63d4..ec877a9 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2
+TAG-$(CONFIG_SEABIOS_STABLE)=33fbe13a3e2a01e0ba1087a8feed801a0451db21
 
 unexport KCONFIG_AUTOHEADER
 unexport KCONFIG_AUTOCONFIG


From gerrit at coreboot.org  Fri Sep  4 08:05:49 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 4 Sep 2015 08:05:49 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: mc_tcu3:
	Adjust gpio settings
References: <I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a+0@gerrit.coreboot.org>
Message-ID: <E1ZXm0L-0000Bn-NK@mail.coreboot.org>

the following patch was just integrated into master:
commit 5fc6f90ef7d3a69e87a004b07b99ef337c6d3380
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Wed Sep 2 15:13:04 2015 +0200

    mc_tcu3: Adjust gpio settings
    
    Adjust gpio settings due to hardware change.
    
    Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
    Reviewed-on: http://review.coreboot.org/11489
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mario Scheithauer <mario.scheithauer at siemens.com>


See http://review.coreboot.org/11489 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep  4 10:59:27 2015
From: gerrit at coreboot.org (Gerd Hoffmann (kraxel@redhat.com))
Date: Fri, 4 Sep 2015 10:59:27 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: qemu: fix vga
	driver build
References: <I9ec82a403d0264955d4b72496219036c7775c758+0@gerrit.coreboot.org>
Message-ID: <I9ec82a403d0264955d4b72496219036c7775c758+1@gerrit.coreboot.org>

Gerd Hoffmann (kraxel at redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11502

-gerrit

commit 13ea015c5de23ac511c75855c145b1b043c1628c
Author: Gerd Hoffmann <kraxel at redhat.com>
Date:   Fri Sep 4 12:58:00 2015 +0200

    qemu: fix vga driver build
    
    Commit "7dbf9c6 edid: Use edid_mode struct to reduce redundancy" moved
    some fields from "struct edid" to "struct edid_mode".  Adapt the bochs
    and cirrus drivers to that change.
    
    Change-Id: I9ec82a403d0264955d4b72496219036c7775c758
    Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
 src/drivers/emulation/qemu/bochs.c  | 4 ++--
 src/drivers/emulation/qemu/cirrus.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c
index cb0075a..ae2975d 100644
--- a/src/drivers/emulation/qemu/bochs.c
+++ b/src/drivers/emulation/qemu/bochs.c
@@ -109,8 +109,8 @@ static void bochs_init(struct device *dev)
 	outb(0x20, 0x3c0); /* disable blanking */
 
 	/* setup coreboot framebuffer */
-	edid.ha = width;
-	edid.va = height;
+	edid.mode.ha = width;
+	edid.mode.va = height;
 	edid.x_resolution = width;
 	edid.y_resolution = height;
 	edid.bytes_per_line = width * 4;
diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c
index ffc9772..be8afdf 100644
--- a/src/drivers/emulation/qemu/cirrus.c
+++ b/src/drivers/emulation/qemu/cirrus.c
@@ -332,8 +332,8 @@ static void cirrus_init(struct device *dev)
 
 
 	struct edid edid;
-	edid.ha = width;
-	edid.va = height;
+	edid.mode.ha = width;
+	edid.mode.va = height;
 	edid.x_resolution = width;
 	edid.y_resolution = height;
 	edid.bytes_per_line = width * 4;


From gerrit at coreboot.org  Fri Sep  4 15:09:04 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 4 Sep 2015 15:09:04 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: bootmode: add
	display_init_required()
References: <I403213e22c0e621e148773597a550addfbaf3f7e+0@gerrit.coreboot.org>
Message-ID: <E1ZXsbw-0003dB-Jg@mail.coreboot.org>

the following patch was just integrated into master:
commit bc98cc66b2fe787173ec04b84ea11bc3e57fe373
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 09:21:36 2015 -0500

    bootmode: add display_init_required()
    
    Some of the Chrome OS boards were directly calling vboot
    called in some form after contorting around #ifdef preprocessor
    macros. The reasoning is that Chrome OS doesn't always do display
    initialization during startup. It's runtime dependent. While
    this is a requirement that doesn't mean vboot functions should be
    sprinkled around in the mainboard and chipset code. Instead provide
    one function, display_init_required(), that provides the policy
    for determining display initialization action. For Chrome OS
    devices this function honors vboot_skip_display_init() and all
    other configurations default to initializing display.
    
    Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11490
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11490 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep  4 15:09:39 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 4 Sep 2015 15:09:39 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: remove
	cpu_incs as romstage Make variable
References: <I8dc0631f8253c21c670f2f02928225ed5b869ce6+0@gerrit.coreboot.org>
Message-ID: <E1ZXscV-0003gl-S6@mail.coreboot.org>

the following patch was just integrated into master:
commit 439356fabcacbbc3a3231f6e27b5298f8f5ad41f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 22:23:11 2015 -0500

    x86: remove cpu_incs as romstage Make variable
    
    When building up which files to include in romstage there
    were both 'cpu_incs' and 'cpu_incs-y' which were used to
    generate crt0.S. Remove the former to settle on cpu_incs-y
    as the way to be included.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. No include file changes.
    
    Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11494
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11494 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep  4 17:40:43 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:40:43 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: bootstate: remove
	need for #ifdef ENV_RAMSTAGE
References: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+0@gerrit.coreboot.org>
Message-ID: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492

-gerrit

commit 7567599ea7b64a4fcdf0771d242739a90ace7e16
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 17:34:04 2015 -0500

    bootstate: remove need for #ifdef ENV_RAMSTAGE
    
    The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
    the current state of the header meant bad build errors in non-ramstage.
    Therefore, people had to #ifdef in the source. Remove that requirement.
    
    Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp1_1/fsp_util.c          |  4 ----
 src/include/bootstate.h                      | 10 +++++++---
 src/northbridge/intel/haswell/mrccache.c     |  3 +--
 src/northbridge/intel/sandybridge/mrccache.c |  3 +--
 src/soc/intel/baytrail/spi.c                 |  2 --
 src/soc/intel/braswell/spi.c                 |  4 ----
 src/soc/intel/broadwell/spi.c                |  2 --
 src/soc/intel/common/mrc_cache.c             | 19 ++-----------------
 src/southbridge/intel/common/spi.c           |  3 +--
 9 files changed, 12 insertions(+), 38 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 18e8648..bce4337 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header)
 #endif
 }
 
-#if ENV_RAMSTAGE
-
 void fsp_notify(u32 phase)
 {
 	FSP_NOTIFY_PHASE notify_phase_proc;
@@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
 	fsp_notify_boot_state_callback,
 	(void *)EnumInitPhaseReadyToBoot);
 
-#endif	/* ENV_RAMSTAGE */
-
 struct fsp_runtime {
 	uint32_t fih;
 	uint32_t hob_list;
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 4952780..8dafa04 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -19,8 +19,7 @@
 #ifndef BOOTSTATE_H
 #define BOOTSTATE_H
 
-#if !defined(__SMM__) && !defined(__PRE_RAM__)
-
+#include <rules.h>
 #include <string.h>
 #include <stdlib.h>
 #include <stddef.h>
@@ -173,8 +172,10 @@ int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq);
 void boot_state_current_block(void);
 void boot_state_current_unblock(void);
 
+#if ENV_RAMSTAGE
 /* Entry into the boot state machine. */
 void main(void);
+#endif
 
 /* In order to schedule boot state callbacks at compile-time specify the
  * entries in an array using the BOOT_STATE_INIT_ENTRIES and
@@ -185,7 +186,11 @@ struct boot_state_init_entry {
 	struct boot_state_callback bscb;
 };
 
+#if ENV_RAMSTAGE
 #define BOOT_STATE_INIT_ATTR  __attribute__ ((used,section (".bs_init")))
+#else
+#define BOOT_STATE_INIT_ATTR  __attribute__ ((unused))
+#endif
 
 #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_)		\
 	static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \
@@ -198,5 +203,4 @@ struct boot_state_init_entry {
 		bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \
 		& func_ ##_## state_ ##_## when_;
 
-#endif
 #endif /* BOOTSTATE_H */
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index eb603f6..bbc5e51 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
 /* SPI code needs malloc/free.
  * Also unknown if writing flash from XIP-flash code is a good idea
  */
-#if !defined(__PRE_RAM__)
+
 /* find the first empty block in the MRC cache area.
  * If there's none, return NULL.
  *
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
 {
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index f89fc0f..2086427 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
 /* SPI code needs malloc/free.
  * Also unknown if writing flash from XIP-flash code is a good idea
  */
-#if !defined(__PRE_RAM__)
+
 /* find the first empty block in the MRC cache area.
  * If there's none, return NULL.
  *
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
 
 struct mrc_data_container *find_current_mrc_cache(void)
 {
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index b1fc692..380b23f 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -316,14 +316,12 @@ void spi_init(void)
 	ich_set_bbar(0);
 }
 
-#ifndef __SMM__
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index afc288a..453a719 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -295,8 +295,6 @@ void spi_init(void)
 	cntlr.preop = &ich9_spi->preop;
 }
 
-#if ENV_RAMSTAGE
-
 static void spi_init_cb(void *unused)
 {
 	spi_init();
@@ -304,8 +302,6 @@ static void spi_init_cb(void *unused)
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
 
-#endif /* ENV_RAMSTAGE */
-
 int spi_claim_bus(struct spi_slave *slave)
 {
 	/* Handled by ICH automatically. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index a75ee83..c159e20 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -312,14 +312,12 @@ void spi_init(void)
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
 
-#if ENV_RAMSTAGE
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index 9a066d5..e5e6b6a 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -18,11 +18,13 @@
  */
 
 #include <string.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <fmap.h>
 #include <ip_checksum.h>
 #include "mrc_cache.h"
+#include "nvm.h"
 
 #define MRC_DATA_ALIGN           0x1000
 #define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache)
 	return __mrc_cache_get_current(&region, cache);
 }
 
-#if ENV_ROMSTAGE
-
-/*
- * romstage code
- */
-
 /* Fill in mrc_saved_data structure with payload. */
 static void mrc_cache_fill(struct mrc_saved_data *cache, void *data,
                            size_t size)
@@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size)
 	return 0;
 }
 
-#else
-
-/*
- * ramstage code
- */
-
-#include <bootstate.h>
-#include "nvm.h"
-
 static int mrc_slot_valid(const struct mrc_data_region *region,
                           const struct mrc_saved_data *slot,
                           const struct mrc_saved_data *to_save)
@@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused)
 }
 
 BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-
-#endif /* ENV_ROMSTAGE */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 1d3ebf6..5d18012 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -359,14 +359,13 @@ void spi_init(void)
 	bios_cntl &= ~(1 << 5);
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
-#ifndef __SMM__
+
 static void spi_init_cb(void *unused)
 {
 	spi_init();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
 
 int spi_claim_bus(struct spi_slave *slave)
 {


From gerrit at coreboot.org  Fri Sep  4 17:40:45 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:40:45 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit 49f140f0d3acd6c310f28722680c46e5b0bc6f60
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 48 +++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 31 files changed, 121 insertions(+), 57 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..94d104d 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,30 +67,14 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
@@ -102,30 +86,18 @@ $(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..f90adfa
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generaed by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions the begining of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Fri Sep  4 17:40:46 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:40:46 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: don't
	create MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit d9cc948e59f2f2aa55b8e0c2e4d0646da37335b3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 94d104d..7f2a3a2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -121,13 +121,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -152,17 +158,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Fri Sep  4 17:40:48 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:40:48 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: add
	rosmtage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit a44a19dbafe7b591cb8207e018a3e39526af9b39
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add rosmtage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7f2a3a2..74d17f0 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -109,17 +109,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -161,8 +167,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -205,10 +209,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..eb07675
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ *attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Fri Sep  4 17:40:49 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:40:49 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit 4517f7e1dbb24ce08a7da07b365983e9cdd8ab0c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Fri Sep  4 17:40:51 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:40:51 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: symbols: add
	'_' to pci_drivers and cpu_drivers symbols
References: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+0@gerrit.coreboot.org>
Message-ID: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11506

-gerrit

commit b5007784d4a52c469e52118d4375f8ec55c76908
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 17:23:08 2015 -0500

    symbols: add '_' to pci_drivers and cpu_drivers symbols
    
    In order to prepare for more unification of the linker
    scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
    ecpu_drivers with an underscore.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built different boards includes ones w/ and w/o relocatable
         ramstage.
    
    Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm64/cpu_ramstage.c | 2 +-
 src/arch/x86/cpu.c            | 2 +-
 src/device/pci_device.c       | 2 +-
 src/include/cpu/cpu.h         | 4 ++--
 src/include/device/pci.h      | 4 ++--
 src/lib/rmodule.ld            | 8 ++++----
 6 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 7b4b26a..a49bf48 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -42,7 +42,7 @@ static struct cpu_driver *locate_cpu_driver(uint32_t midr)
 {
 	struct cpu_driver *cur;
 
-	for (cur = cpu_drivers; cur != ecpu_drivers; cur++) {
+	for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) {
 		const struct cpu_device_id *id_table = cur->id_table;
 
 		for (; id_table->midr != CPU_ID_END; id_table++) {
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 3eb7b94..ceed077 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -192,7 +192,7 @@ static void identify_cpu(struct device *cpu)
 struct cpu_driver *find_cpu_driver(struct device *cpu)
 {
 	struct cpu_driver *driver;
-	for (driver = cpu_drivers; driver < ecpu_drivers; driver++) {
+	for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) {
 		struct cpu_device_id *id;
 		for (id = driver->id_table;
 		     id->vendor != X86_VENDOR_INVALID; id++) {
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 6332209..f2e4d5d 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -850,7 +850,7 @@ static void set_pci_ops(struct device *dev)
 	 * Look through the list of setup drivers and find one for
 	 * this PCI device.
 	 */
-	for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
+	for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) {
 		if ((driver->vendor == dev->vendor) &&
 		    device_id_match(driver, dev->device)) {
 			dev->ops = (struct device_operations *)driver->ops;
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index 47521d4..28431c0 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -18,9 +18,9 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
 #ifndef __SIMPLE_DEVICE__
 /** start of compile time generated pci driver array */
-extern struct cpu_driver cpu_drivers[];
+extern struct cpu_driver _cpu_drivers[];
 /** end of compile time generated pci driver array */
-extern struct cpu_driver ecpu_drivers[];
+extern struct cpu_driver _ecpu_drivers[];
 #endif
 #endif /* !__PRE_RAM__ && !__SMM__ */
 
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 2a76ba9..fe31b54 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -55,9 +55,9 @@ struct pci_driver {
 
 #define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver")))
 /** start of compile time generated pci driver array */
-extern struct pci_driver pci_drivers[];
+extern struct pci_driver _pci_drivers[];
 /** end of compile time generated pci driver array */
-extern struct pci_driver epci_drivers[];
+extern struct pci_driver _epci_drivers[];
 
 
 extern struct device_operations default_pci_ops_dev;
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index e6b4da7..f5d5f06 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -42,13 +42,13 @@ SECTIONS
 		 * ramstage with the rmodule linker. Any changes made in
 		 * ramstage.ld should be made here as well. */
 		. = ALIGN(8);
-		pci_drivers = . ;
+		_pci_drivers = . ;
 		KEEP(*(.rodata.pci_driver));
-		epci_drivers = . ;
+		_epci_drivers = . ;
 		. = ALIGN(8);
-		cpu_drivers = . ;
+		_cpu_drivers = . ;
 		KEEP(*(.rodata.cpu_driver));
-		ecpu_drivers = . ;
+		_ecpu_drivers = . ;
 		. = ALIGN(8);
 		_bs_init_begin = .;
 		KEEP(*(.bs_init));


From gerrit at coreboot.org  Fri Sep  4 17:40:55 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:40:55 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: linking: lay
	the groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 4f567c317aad04dfd4bb99b1f74d191d53f2dd3e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  67 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 218 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 74d17f0..e0037ac 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -285,7 +285,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..4900d3e
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+	SYMBOL_CURRENT_LOC(etext)
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index 432df40..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	epci_drivers = . ;
-	cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Fri Sep  4 17:40:58 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:40:58 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit e200decbd4e1ccd362eb318e5c47a66c543829a6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Fri Sep  4 17:41:00 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:41:00 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 2111ec932b3cab3a0d9f9eb410a95476e8a25f36
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Fri Sep  4 17:41:02 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 17:41:02 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 913897d7bb31677e8b4ef0f1ac3848d0fdbec498
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 +++++++++-
 src/arch/x86/romstage.ld              | 49 ++++++++---------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 34 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index e0037ac..7423ffe 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -109,8 +109,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -189,11 +188,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..00aef68 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,24 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	ROMSTAGE(ROMSTAGE_BASE, CONFIG_XIP_ROM_SIZE)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Fri Sep  4 18:03:09 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:09 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 07d5730349903b0290d95f83cddaca225b941833
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Fri Sep  4 18:03:13 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:13 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 57aaab0dc67069951a3e25bc840c23f89bbd35ad
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Fri Sep  4 18:03:17 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:17 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 7b7fe62416d93f0c0da862ea74c142363ca771c0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 +++++++++-
 src/arch/x86/romstage.ld              | 49 ++++++++---------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 34 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 23a24f2..8868a3f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..00aef68 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,24 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	ROMSTAGE(ROMSTAGE_BASE, CONFIG_XIP_ROM_SIZE)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Fri Sep  4 18:03:22 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:22 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit 7598c0e26376e9284ab89fca78d0d15c01fb31f1
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 54 +++++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 31 files changed, 126 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..cf69868 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
 bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+	touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) $(objgenerated)/empty
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..f90adfa
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generaed by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions the begining of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Fri Sep  4 18:03:28 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:28 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	rosmtage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit c778a07434232c8e4378b2086da3d1da842287c5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add rosmtage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8d07603..8311b11 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..eb07675
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ *attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Fri Sep  4 18:03:32 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit 38791d6ca8c932448e47767f2a2fa457dd5f7d33
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Fri Sep  4 18:03:36 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: symbols: add '_'
	to pci_drivers and cpu_drivers symbols
References: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+0@gerrit.coreboot.org>
Message-ID: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11506

-gerrit

commit ed45bd66cd60c8287cbeae7392b9d0704e89ecb7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 17:23:08 2015 -0500

    symbols: add '_' to pci_drivers and cpu_drivers symbols
    
    In order to prepare for more unification of the linker
    scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
    ecpu_drivers with an underscore.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built different boards includes ones w/ and w/o relocatable
         ramstage.
    
    Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm64/cpu_ramstage.c | 2 +-
 src/arch/x86/cpu.c            | 2 +-
 src/device/pci_device.c       | 2 +-
 src/include/cpu/cpu.h         | 4 ++--
 src/include/device/pci.h      | 4 ++--
 src/lib/rmodule.ld            | 8 ++++----
 6 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 7b4b26a..a49bf48 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -42,7 +42,7 @@ static struct cpu_driver *locate_cpu_driver(uint32_t midr)
 {
 	struct cpu_driver *cur;
 
-	for (cur = cpu_drivers; cur != ecpu_drivers; cur++) {
+	for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) {
 		const struct cpu_device_id *id_table = cur->id_table;
 
 		for (; id_table->midr != CPU_ID_END; id_table++) {
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 3eb7b94..ceed077 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -192,7 +192,7 @@ static void identify_cpu(struct device *cpu)
 struct cpu_driver *find_cpu_driver(struct device *cpu)
 {
 	struct cpu_driver *driver;
-	for (driver = cpu_drivers; driver < ecpu_drivers; driver++) {
+	for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) {
 		struct cpu_device_id *id;
 		for (id = driver->id_table;
 		     id->vendor != X86_VENDOR_INVALID; id++) {
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 6332209..f2e4d5d 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -850,7 +850,7 @@ static void set_pci_ops(struct device *dev)
 	 * Look through the list of setup drivers and find one for
 	 * this PCI device.
 	 */
-	for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
+	for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) {
 		if ((driver->vendor == dev->vendor) &&
 		    device_id_match(driver, dev->device)) {
 			dev->ops = (struct device_operations *)driver->ops;
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index 47521d4..28431c0 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -18,9 +18,9 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
 #ifndef __SIMPLE_DEVICE__
 /** start of compile time generated pci driver array */
-extern struct cpu_driver cpu_drivers[];
+extern struct cpu_driver _cpu_drivers[];
 /** end of compile time generated pci driver array */
-extern struct cpu_driver ecpu_drivers[];
+extern struct cpu_driver _ecpu_drivers[];
 #endif
 #endif /* !__PRE_RAM__ && !__SMM__ */
 
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 2a76ba9..fe31b54 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -55,9 +55,9 @@ struct pci_driver {
 
 #define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver")))
 /** start of compile time generated pci driver array */
-extern struct pci_driver pci_drivers[];
+extern struct pci_driver _pci_drivers[];
 /** end of compile time generated pci driver array */
-extern struct pci_driver epci_drivers[];
+extern struct pci_driver _epci_drivers[];
 
 
 extern struct device_operations default_pci_ops_dev;
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index e6b4da7..f5d5f06 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -42,13 +42,13 @@ SECTIONS
 		 * ramstage with the rmodule linker. Any changes made in
 		 * ramstage.ld should be made here as well. */
 		. = ALIGN(8);
-		pci_drivers = . ;
+		_pci_drivers = . ;
 		KEEP(*(.rodata.pci_driver));
-		epci_drivers = . ;
+		_epci_drivers = . ;
 		. = ALIGN(8);
-		cpu_drivers = . ;
+		_cpu_drivers = . ;
 		KEEP(*(.rodata.cpu_driver));
-		ecpu_drivers = . ;
+		_ecpu_drivers = . ;
 		. = ALIGN(8);
 		_bs_init_begin = .;
 		KEEP(*(.bs_init));


From gerrit at coreboot.org  Fri Sep  4 18:03:40 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:40 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 2537ea75b8151e6fc52f2b49019a234957ae90e3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  67 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 218 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8311b11..23a24f2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..4900d3e
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+	SYMBOL_CURRENT_LOC(etext)
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index 432df40..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	epci_drivers = . ;
-	cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Fri Sep  4 18:03:44 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:03:44 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: don't create
	MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit e19178e89eacaf7562f893e3d182beadcbbc30fc
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index cf69868..8d07603 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -125,13 +125,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Fri Sep  4 18:08:18 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 4 Sep 2015 18:08:18 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	intel/common/firmware: Add common GBE rom support
References: <Id5fab3061874dad759750b67d3339eb8c99a62d6+0@gerrit.coreboot.org>
Message-ID: <E1ZXvPO-0002ui-6m@mail.coreboot.org>

the following patch was just integrated into master:
commit c6a177d50064a22215c8f682e1d16043d5470fa8
Author: Martin Roth <gaumless at gmail.com>
Date:   Thu Jul 9 20:50:51 2015 -0600

    intel/common/firmware: Add common GBE rom support
    
    Add support to the Intel common firmware Kconfig and Makefile.inc to
    allow the Gigabit Ethernet (GBE) blob to be added to the final
    binary.
    
    Change-Id: Id5fab3061874dad759750b67d3339eb8c99a62d6
    Signed-off-by: Martin Roth <gaumless at gmail.com>
    Reviewed-on: http://review.coreboot.org/10875
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexander Couzens <lynxis at fe80.eu>


See http://review.coreboot.org/10875 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep  4 18:50:10 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:10 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 492531fdfed5395d5af0df34d3e7c0bcba5f5b52
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Fri Sep  4 18:50:14 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 7630ceee02e431151c5543f4c92902270d451052
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Fri Sep  4 18:50:19 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:19 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit a50734326354963c79d985f4e54ec45fb1ad27a3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 +++++++++-
 src/arch/x86/romstage.ld              | 49 ++++++++---------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 34 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 23a24f2..8868a3f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..00aef68 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,24 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	ROMSTAGE(ROMSTAGE_BASE, CONFIG_XIP_ROM_SIZE)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Fri Sep  4 18:50:26 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:26 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit 5b61c180ff85f7259b0a4d517afd34804df0dc49
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 54 +++++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++
 src/arch/x86/bootblock.ld                      | 29 ++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 32 files changed, 155 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..cf69868 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
 bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+	touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) $(objgenerated)/empty
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..f90adfa
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generaed by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions the begining of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
new file mode 100644
index 0000000..6835430
--- /dev/null
+++ b/src/arch/x86/bootblock.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/x86/failover.ld>
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
+
+/* Include generated .ld files. */
+#include <generated/bootblock.ld>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Fri Sep  4 18:50:32 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	rosmtage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit 87ce5eecaf674240778aba12142ae2b306d2c45f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add rosmtage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8d07603..8311b11 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..eb07675
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ *attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Fri Sep  4 18:50:38 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:38 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit 0801d5b5e983aecfe3e754bc8164d1bd24e2dbbe
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Fri Sep  4 18:50:44 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:44 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: symbols: add '_'
	to pci_drivers and cpu_drivers symbols
References: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+0@gerrit.coreboot.org>
Message-ID: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11506

-gerrit

commit c20485d643901f07174d8c92f988f73a123981da
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 17:23:08 2015 -0500

    symbols: add '_' to pci_drivers and cpu_drivers symbols
    
    In order to prepare for more unification of the linker
    scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
    ecpu_drivers with an underscore.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built different boards includes ones w/ and w/o relocatable
         ramstage.
    
    Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm64/cpu_ramstage.c | 2 +-
 src/arch/x86/cpu.c            | 2 +-
 src/device/pci_device.c       | 2 +-
 src/include/cpu/cpu.h         | 4 ++--
 src/include/device/pci.h      | 4 ++--
 src/lib/rmodule.ld            | 8 ++++----
 6 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 7b4b26a..a49bf48 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -42,7 +42,7 @@ static struct cpu_driver *locate_cpu_driver(uint32_t midr)
 {
 	struct cpu_driver *cur;
 
-	for (cur = cpu_drivers; cur != ecpu_drivers; cur++) {
+	for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) {
 		const struct cpu_device_id *id_table = cur->id_table;
 
 		for (; id_table->midr != CPU_ID_END; id_table++) {
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 3eb7b94..ceed077 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -192,7 +192,7 @@ static void identify_cpu(struct device *cpu)
 struct cpu_driver *find_cpu_driver(struct device *cpu)
 {
 	struct cpu_driver *driver;
-	for (driver = cpu_drivers; driver < ecpu_drivers; driver++) {
+	for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) {
 		struct cpu_device_id *id;
 		for (id = driver->id_table;
 		     id->vendor != X86_VENDOR_INVALID; id++) {
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 6332209..f2e4d5d 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -850,7 +850,7 @@ static void set_pci_ops(struct device *dev)
 	 * Look through the list of setup drivers and find one for
 	 * this PCI device.
 	 */
-	for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
+	for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) {
 		if ((driver->vendor == dev->vendor) &&
 		    device_id_match(driver, dev->device)) {
 			dev->ops = (struct device_operations *)driver->ops;
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index 47521d4..28431c0 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -18,9 +18,9 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
 #ifndef __SIMPLE_DEVICE__
 /** start of compile time generated pci driver array */
-extern struct cpu_driver cpu_drivers[];
+extern struct cpu_driver _cpu_drivers[];
 /** end of compile time generated pci driver array */
-extern struct cpu_driver ecpu_drivers[];
+extern struct cpu_driver _ecpu_drivers[];
 #endif
 #endif /* !__PRE_RAM__ && !__SMM__ */
 
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 2a76ba9..fe31b54 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -55,9 +55,9 @@ struct pci_driver {
 
 #define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver")))
 /** start of compile time generated pci driver array */
-extern struct pci_driver pci_drivers[];
+extern struct pci_driver _pci_drivers[];
 /** end of compile time generated pci driver array */
-extern struct pci_driver epci_drivers[];
+extern struct pci_driver _epci_drivers[];
 
 
 extern struct device_operations default_pci_ops_dev;
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index e6b4da7..f5d5f06 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -42,13 +42,13 @@ SECTIONS
 		 * ramstage with the rmodule linker. Any changes made in
 		 * ramstage.ld should be made here as well. */
 		. = ALIGN(8);
-		pci_drivers = . ;
+		_pci_drivers = . ;
 		KEEP(*(.rodata.pci_driver));
-		epci_drivers = . ;
+		_epci_drivers = . ;
 		. = ALIGN(8);
-		cpu_drivers = . ;
+		_cpu_drivers = . ;
 		KEEP(*(.rodata.cpu_driver));
-		ecpu_drivers = . ;
+		_ecpu_drivers = . ;
 		. = ALIGN(8);
 		_bs_init_begin = .;
 		KEEP(*(.bs_init));


From gerrit at coreboot.org  Fri Sep  4 18:50:50 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:50 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit ead7ba5d3c170d0d54f939cb2a5bc2ad9d3f06b0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  67 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 218 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8311b11..23a24f2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..4900d3e
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+	SYMBOL_CURRENT_LOC(etext)
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index 432df40..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	epci_drivers = . ;
-	cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Fri Sep  4 18:50:54 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 18:50:54 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: don't create
	MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit 92d035f90c90ac6948705143513bdae076c22e75
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index cf69868..8d07603 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -125,13 +125,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Fri Sep  4 21:02:01 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 4 Sep 2015 21:02:01 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: bootstate:
	remove need for #ifdef ENV_RAMSTAGE
References: <I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd+0@gerrit.coreboot.org>
Message-ID: <E1ZXy7W-00036P-2f@mail.coreboot.org>

the following patch was just integrated into master:
commit 4d3de7e328fd92498fd7cf149a0aa887e33f8dfd
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 2 17:34:04 2015 -0500

    bootstate: remove need for #ifdef ENV_RAMSTAGE
    
    The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
    the current state of the header meant bad build errors in non-ramstage.
    Therefore, people had to #ifdef in the source. Remove that requirement.
    
    Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11492
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11492 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep  4 21:07:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:07:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit afa48b6d72ecce7e4d1123fc116329327c54cb05
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Fri Sep  4 21:07:48 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:07:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit c45c3e98d4c0f134d4d59494fca65be336c43330
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Fri Sep  4 21:07:55 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:07:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit a65c29dc2cf314c1d506779e63d5288298e4ae6e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 23a24f2..8868a3f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Fri Sep  4 21:08:03 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:08:03 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit 3dfecaa4c119c35a799de2f9991a13ee26bc6eaf
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 54 +++++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++
 src/arch/x86/bootblock.ld                      | 29 ++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 32 files changed, 155 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..cf69868 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
 bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+	touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) $(objgenerated)/empty
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..f90adfa
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generaed by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions the begining of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
new file mode 100644
index 0000000..6835430
--- /dev/null
+++ b/src/arch/x86/bootblock.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/x86/failover.ld>
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
+
+/* Include generated .ld files. */
+#include <generated/bootblock.ld>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Fri Sep  4 21:08:11 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:08:11 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	rosmtage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit 6c3be82ac102642e47f7d0254e21b1c30f14a85e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add rosmtage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8d07603..8311b11 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..eb07675
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ *attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Fri Sep  4 21:08:17 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:08:17 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit 4529e04be1337149179e0096b1453df711217305
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Fri Sep  4 21:08:24 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:08:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: symbols: add '_'
	to pci_drivers and cpu_drivers symbols
References: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+0@gerrit.coreboot.org>
Message-ID: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11506

-gerrit

commit 2c1e4dd5d327a3f3dfc9b1a0d5fa4c29aaa60aec
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 17:23:08 2015 -0500

    symbols: add '_' to pci_drivers and cpu_drivers symbols
    
    In order to prepare for more unification of the linker
    scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
    ecpu_drivers with an underscore.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built different boards includes ones w/ and w/o relocatable
         ramstage.
    
    Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm64/cpu_ramstage.c | 2 +-
 src/arch/x86/cpu.c            | 2 +-
 src/device/pci_device.c       | 2 +-
 src/include/cpu/cpu.h         | 4 ++--
 src/include/device/pci.h      | 4 ++--
 src/lib/rmodule.ld            | 8 ++++----
 6 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 7b4b26a..a49bf48 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -42,7 +42,7 @@ static struct cpu_driver *locate_cpu_driver(uint32_t midr)
 {
 	struct cpu_driver *cur;
 
-	for (cur = cpu_drivers; cur != ecpu_drivers; cur++) {
+	for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) {
 		const struct cpu_device_id *id_table = cur->id_table;
 
 		for (; id_table->midr != CPU_ID_END; id_table++) {
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 3eb7b94..ceed077 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -192,7 +192,7 @@ static void identify_cpu(struct device *cpu)
 struct cpu_driver *find_cpu_driver(struct device *cpu)
 {
 	struct cpu_driver *driver;
-	for (driver = cpu_drivers; driver < ecpu_drivers; driver++) {
+	for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) {
 		struct cpu_device_id *id;
 		for (id = driver->id_table;
 		     id->vendor != X86_VENDOR_INVALID; id++) {
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 6332209..f2e4d5d 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -850,7 +850,7 @@ static void set_pci_ops(struct device *dev)
 	 * Look through the list of setup drivers and find one for
 	 * this PCI device.
 	 */
-	for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
+	for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) {
 		if ((driver->vendor == dev->vendor) &&
 		    device_id_match(driver, dev->device)) {
 			dev->ops = (struct device_operations *)driver->ops;
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index 47521d4..28431c0 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -18,9 +18,9 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
 #ifndef __SIMPLE_DEVICE__
 /** start of compile time generated pci driver array */
-extern struct cpu_driver cpu_drivers[];
+extern struct cpu_driver _cpu_drivers[];
 /** end of compile time generated pci driver array */
-extern struct cpu_driver ecpu_drivers[];
+extern struct cpu_driver _ecpu_drivers[];
 #endif
 #endif /* !__PRE_RAM__ && !__SMM__ */
 
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 2a76ba9..fe31b54 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -55,9 +55,9 @@ struct pci_driver {
 
 #define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver")))
 /** start of compile time generated pci driver array */
-extern struct pci_driver pci_drivers[];
+extern struct pci_driver _pci_drivers[];
 /** end of compile time generated pci driver array */
-extern struct pci_driver epci_drivers[];
+extern struct pci_driver _epci_drivers[];
 
 
 extern struct device_operations default_pci_ops_dev;
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index e6b4da7..f5d5f06 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -42,13 +42,13 @@ SECTIONS
 		 * ramstage with the rmodule linker. Any changes made in
 		 * ramstage.ld should be made here as well. */
 		. = ALIGN(8);
-		pci_drivers = . ;
+		_pci_drivers = . ;
 		KEEP(*(.rodata.pci_driver));
-		epci_drivers = . ;
+		_epci_drivers = . ;
 		. = ALIGN(8);
-		cpu_drivers = . ;
+		_cpu_drivers = . ;
 		KEEP(*(.rodata.cpu_driver));
-		ecpu_drivers = . ;
+		_ecpu_drivers = . ;
 		. = ALIGN(8);
 		_bs_init_begin = .;
 		KEEP(*(.bs_init));


From gerrit at coreboot.org  Fri Sep  4 21:08:32 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:08:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 848c158e3fbdb2a081671c0215f52fe71a48e721
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  67 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 218 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8311b11..23a24f2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..4900d3e
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+	SYMBOL_CURRENT_LOC(etext)
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index 432df40..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	epci_drivers = . ;
-	cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Fri Sep  4 21:08:38 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:08:38 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: don't create
	MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit 0144d3692b17e62935a45ed8a6a5af0356744208
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index cf69868..8d07603 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -125,13 +125,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Fri Sep  4 21:08:40 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:08:40 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: amd/geode_lx:
	make done_cache_as_ram_main global
References: <I84c3af0026f3f98bc64af007aa7cc196429f4e5f+0@gerrit.coreboot.org>
Message-ID: <I84c3af0026f3f98bc64af007aa7cc196429f4e5f+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11511

-gerrit

commit b45ca02849a8ffd15b9a4db490961577526598ee
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 15:55:27 2015 -0500

    amd/geode_lx: make done_cache_as_ram_main global
    
    Current code written in C is calling a function implemented
    in assembly. However, the symbol's visibility is not set
    for such usage. Of course this works because MAINBOARDDIR/romstage.c
    is being processed into an assembly file currently.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built digitallogic/msm800sev while not changing romstage.c
         into an assembly file.
    
    Change-Id: I84c3af0026f3f98bc64af007aa7cc196429f4e5f
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/cpu/amd/geode_lx/cache_as_ram.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index bcb0d4b..11eda54 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -186,6 +186,7 @@ DCacheSetupGood:
 
 	/* Call romstage.c main function */
 	call	main
+.global done_cache_as_ram_main
 done_cache_as_ram_main:
 
 	/* We now run over the stack-in-cache,


From gerrit at coreboot.org  Fri Sep  4 21:08:42 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:08:42 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: amd/thatcher:
	include .c files with the right path
References: <If4fb1064a246b4fc11a958b07a0b76d9f9673898+0@gerrit.coreboot.org>
Message-ID: <If4fb1064a246b4fc11a958b07a0b76d9f9673898+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11512

-gerrit

commit 5684d010a125e9bc560e6967e5847a85cfdb7094
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:03:07 2015 -0500

    amd/thatcher: include .c files with the right path
    
    The #include path during compilation already has '-I src'.
    Don't encode the src part of a path.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built amd/thatcher while compiling romstage.c with C compiler..
    
    Change-Id: If4fb1064a246b4fc11a958b07a0b76d9f9673898
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/amd/thatcher/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 69614e1..6ab4e4f 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -34,7 +34,7 @@
 #include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
-#include "src/superio/smsc/lpc47n217/early_serial.c"
+#include <superio/smsc/lpc47n217/early_serial.c>
 #include <cpu/amd/agesa/s3_resume.h>
 #include "cbmem.h"
 


From gerrit at coreboot.org  Fri Sep  4 21:15:39 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:15:39 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit caf835059902bd79f9b80fc7f71c9b72f79ac88c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Fri Sep  4 21:15:45 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:15:45 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit f49e79760dcab4ea3bf4bf09aad9b8be67c73e0f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Fri Sep  4 21:15:50 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:15:50 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 5088b0ad4ec6373b5d16b75c95a53ced3f2fecd6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 23a24f2..8868a3f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Fri Sep  4 21:15:56 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:15:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: symbols: add '_'
	to pci_drivers and cpu_drivers symbols
References: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+0@gerrit.coreboot.org>
Message-ID: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11506

-gerrit

commit c25ca7be840d35ad5f7669e37abb064ac4871363
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 17:23:08 2015 -0500

    symbols: add '_' to pci_drivers and cpu_drivers symbols
    
    In order to prepare for more unification of the linker
    scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
    ecpu_drivers with an underscore.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built different boards includes ones w/ and w/o relocatable
         ramstage.
    
    Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm64/cpu_ramstage.c | 2 +-
 src/arch/x86/cpu.c            | 2 +-
 src/device/pci_device.c       | 2 +-
 src/include/cpu/cpu.h         | 4 ++--
 src/include/device/pci.h      | 4 ++--
 src/lib/ramstage.ld           | 8 ++++----
 src/lib/rmodule.ld            | 8 ++++----
 7 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 7b4b26a..a49bf48 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -42,7 +42,7 @@ static struct cpu_driver *locate_cpu_driver(uint32_t midr)
 {
 	struct cpu_driver *cur;
 
-	for (cur = cpu_drivers; cur != ecpu_drivers; cur++) {
+	for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) {
 		const struct cpu_device_id *id_table = cur->id_table;
 
 		for (; id_table->midr != CPU_ID_END; id_table++) {
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 3eb7b94..ceed077 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -192,7 +192,7 @@ static void identify_cpu(struct device *cpu)
 struct cpu_driver *find_cpu_driver(struct device *cpu)
 {
 	struct cpu_driver *driver;
-	for (driver = cpu_drivers; driver < ecpu_drivers; driver++) {
+	for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) {
 		struct cpu_device_id *id;
 		for (id = driver->id_table;
 		     id->vendor != X86_VENDOR_INVALID; id++) {
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 6332209..f2e4d5d 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -850,7 +850,7 @@ static void set_pci_ops(struct device *dev)
 	 * Look through the list of setup drivers and find one for
 	 * this PCI device.
 	 */
-	for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
+	for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) {
 		if ((driver->vendor == dev->vendor) &&
 		    device_id_match(driver, dev->device)) {
 			dev->ops = (struct device_operations *)driver->ops;
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index 47521d4..28431c0 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -18,9 +18,9 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
 #ifndef __SIMPLE_DEVICE__
 /** start of compile time generated pci driver array */
-extern struct cpu_driver cpu_drivers[];
+extern struct cpu_driver _cpu_drivers[];
 /** end of compile time generated pci driver array */
-extern struct cpu_driver ecpu_drivers[];
+extern struct cpu_driver _ecpu_drivers[];
 #endif
 #endif /* !__PRE_RAM__ && !__SMM__ */
 
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 2a76ba9..fe31b54 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -55,9 +55,9 @@ struct pci_driver {
 
 #define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver")))
 /** start of compile time generated pci driver array */
-extern struct pci_driver pci_drivers[];
+extern struct pci_driver _pci_drivers[];
 /** end of compile time generated pci driver array */
-extern struct pci_driver epci_drivers[];
+extern struct pci_driver _epci_drivers[];
 
 
 extern struct device_operations default_pci_ops_dev;
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
index 432df40..b224827 100644
--- a/src/lib/ramstage.ld
+++ b/src/lib/ramstage.ld
@@ -53,12 +53,12 @@
 	/* If any changes are made to the driver start/symbols or the
 	 * section names the equivalent changes need to made to
 	 * rmodule.ld. */
-	pci_drivers = . ;
+	_pci_drivers = . ;
 	KEEP(*(.rodata.pci_driver));
-	epci_drivers = . ;
-	cpu_drivers = . ;
+	_epci_drivers = . ;
+	_cpu_drivers = . ;
 	KEEP(*(.rodata.cpu_driver));
-	ecpu_drivers = . ;
+	_ecpu_drivers = . ;
 	_bs_init_begin = .;
 	KEEP(*(.bs_init));
 	LONG(0);
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index e6b4da7..f5d5f06 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -42,13 +42,13 @@ SECTIONS
 		 * ramstage with the rmodule linker. Any changes made in
 		 * ramstage.ld should be made here as well. */
 		. = ALIGN(8);
-		pci_drivers = . ;
+		_pci_drivers = . ;
 		KEEP(*(.rodata.pci_driver));
-		epci_drivers = . ;
+		_epci_drivers = . ;
 		. = ALIGN(8);
-		cpu_drivers = . ;
+		_cpu_drivers = . ;
 		KEEP(*(.rodata.cpu_driver));
-		ecpu_drivers = . ;
+		_ecpu_drivers = . ;
 		. = ALIGN(8);
 		_bs_init_begin = .;
 		KEEP(*(.bs_init));


From gerrit at coreboot.org  Fri Sep  4 21:16:01 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:16:01 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit b5678b17b447ba7154060328e0f07002446db30f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  67 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 218 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8311b11..23a24f2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..4900d3e
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+	SYMBOL_CURRENT_LOC(etext)
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Fri Sep  4 21:32:17 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:32:17 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit cb4e405c79aad27a1a36d54eb92dcc75cbeb6eed
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Fri Sep  4 21:32:24 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:32:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit df4ddbd502b33e39ec82fa4f63be110bbdf3d33f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 23a24f2..8868a3f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Fri Sep  4 21:32:25 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:32:25 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: rules.h: add
	fall through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit e8f331dfb57c362ed6230e3dafa0bdb176c75d83
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..2e7f88f 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,23 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/* Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Fri Sep  4 21:36:28 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:36:28 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 693dc60b11bb82a616ee2e8191716e40947001d3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Fri Sep  4 21:36:37 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:36:37 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 9cf9c327e633f29b8526d1c1b8b1dbef779ca6d6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Fri Sep  4 21:36:45 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:36:45 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 8ec989dc6b9bfb4b4335865c98fe6195009f9359
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 23a24f2..8868a3f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Fri Sep  4 21:36:53 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:36:53 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 1b3c261f4610fa2fac10c427566512af4ddd90d8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  67 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 218 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8311b11..23a24f2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..4900d3e
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+	SYMBOL_CURRENT_LOC(etext)
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Fri Sep  4 21:36:56 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 4 Sep 2015 21:36:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit e7e42da91e32560822196826e8ac675453d9ecbf
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..2e7f88f 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,23 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/* Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Sat Sep  5 14:52:25 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 5 Sep 2015 14:52:25 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Drop "See file
	CREDITS..." comment
References: <Iaa4686979ba1385b00ad1dbb6ea91e58f5014384+0@gerrit.coreboot.org>
Message-ID: <Iaa4686979ba1385b00ad1dbb6ea91e58f5014384+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11514

-gerrit

commit 5f4da52bd3efe3def8303b8775ebfe7eb2036826
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Sat Sep 5 07:51:32 2015 -0700

    Drop "See file CREDITS..." comment
    
    coreboot has no CREDITS file.
    
    Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 payloads/libpayload/arch/x86/string.c             | 3 ---
 src/arch/arm/div0.c                               | 3 ---
 src/arch/arm/include/armv7.h                      | 3 ---
 src/arch/arm/include/clocks.h                     | 2 --
 src/arch/arm64/div0.c                             | 3 ---
 src/arch/arm64/include/clocks.h                   | 2 --
 src/arch/x86/memset.c                             | 3 ---
 src/drivers/i2c/tpm/tis.c                         | 3 ---
 src/drivers/i2c/tpm/tpm.c                         | 3 ---
 src/drivers/i2c/tpm/tpm.h                         | 4 ----
 src/drivers/maxim/max77686/max77686.c             | 3 ---
 src/drivers/maxim/max77686/max77686.h             | 3 ---
 src/drivers/maxim/max77802/max77802.h             | 3 ---
 src/drivers/spi/gigadevice.c                      | 3 ---
 src/drivers/spi/macronix.c                        | 3 ---
 src/drivers/spi/spansion.c                        | 3 ---
 src/drivers/spi/stmicro.c                         | 3 ---
 src/ec/google/chromeec/ec_message.h               | 2 --
 src/include/spi-generic.h                         | 3 ---
 src/include/spi_flash.h                           | 3 ---
 src/lib/hexdump.c                                 | 3 ---
 src/soc/intel/baytrail/spi.c                      | 3 ---
 src/soc/intel/braswell/spi.c                      | 3 ---
 src/soc/intel/broadwell/spi.c                     | 3 ---
 src/soc/intel/skylake/flash_controller.c          | 3 ---
 src/soc/nvidia/tegra/dc.h                         | 3 ---
 src/soc/nvidia/tegra/pwm.h                        | 3 ---
 src/soc/nvidia/tegra124/include/soc/sdram_param.h | 3 ---
 src/soc/nvidia/tegra132/include/soc/sdram_param.h | 3 ---
 src/soc/nvidia/tegra210/include/soc/sdram_param.h | 3 ---
 src/soc/samsung/exynos5420/dmc_init_ddr3.c        | 3 ---
 src/southbridge/intel/common/spi.c                | 3 ---
 src/southbridge/intel/fsp_rangeley/spi.c          | 3 ---
 33 files changed, 97 deletions(-)

diff --git a/payloads/libpayload/arch/x86/string.c b/payloads/libpayload/arch/x86/string.c
index 60de812..a646db4 100644
--- a/payloads/libpayload/arch/x86/string.c
+++ b/payloads/libpayload/arch/x86/string.c
@@ -3,9 +3,6 @@
  * This file is part of the GNU C Library.
  * Copyright (c) 2011 The Chromium OS Authors.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/arch/arm/div0.c b/src/arch/arm/div0.c
index 786a117..6550142 100644
--- a/src/arch/arm/div0.c
+++ b/src/arch/arm/div0.c
@@ -2,9 +2,6 @@
  * (C) Copyright 2002
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/arch/arm/include/armv7.h b/src/arch/arm/include/armv7.h
index 7cbd33f..47faaa1 100644
--- a/src/arch/arm/include/armv7.h
+++ b/src/arch/arm/include/armv7.h
@@ -3,9 +3,6 @@
  * Texas Instruments, <www.ti.com>
  * Aneesh V <aneesh at ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/arch/arm/include/clocks.h b/src/arch/arm/include/clocks.h
index 96cdd06..eadd58a 100644
--- a/src/arch/arm/include/clocks.h
+++ b/src/arch/arm/include/clocks.h
@@ -1,7 +1,5 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
diff --git a/src/arch/arm64/div0.c b/src/arch/arm64/div0.c
index 786a117..6550142 100644
--- a/src/arch/arm64/div0.c
+++ b/src/arch/arm64/div0.c
@@ -2,9 +2,6 @@
  * (C) Copyright 2002
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/arch/arm64/include/clocks.h b/src/arch/arm64/include/clocks.h
index 96cdd06..eadd58a 100644
--- a/src/arch/arm64/include/clocks.h
+++ b/src/arch/arm64/include/clocks.h
@@ -1,7 +1,5 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c
index d534556..6ae6c6b 100644
--- a/src/arch/x86/memset.c
+++ b/src/arch/x86/memset.c
@@ -2,9 +2,6 @@
  * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
  * This file is part of the GNU C Library.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c
index fca4316..1e17275 100644
--- a/src/drivers/i2c/tpm/tis.c
+++ b/src/drivers/i2c/tpm/tis.c
@@ -2,9 +2,6 @@
  * Copyright (C) 2011 Infineon Technologies
  * Copyright 2013 Google Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
index 160b391..d02604b 100644
--- a/src/drivers/i2c/tpm/tpm.c
+++ b/src/drivers/i2c/tpm/tpm.c
@@ -17,9 +17,6 @@
  *
  * Version: 2.1.1
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation, version 2 of the
diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h
index 35285c0..6650996 100644
--- a/src/drivers/i2c/tpm/tpm.h
+++ b/src/drivers/i2c/tpm/tpm.h
@@ -13,10 +13,6 @@
  * It is based on the Linux kernel driver tpm.c from Leendert van
  * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall.
  *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation, version 2 of the
diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c
index 0a4abe3..8638bf6 100644
--- a/src/drivers/maxim/max77686/max77686.c
+++ b/src/drivers/maxim/max77686/max77686.c
@@ -2,9 +2,6 @@
  * Copyright (C) 2012 Samsung Electronics
  * Alim Akhtar <alim.akhtar at samsung.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h
index f20a7f4..a35b9cc 100644
--- a/src/drivers/maxim/max77686/max77686.h
+++ b/src/drivers/maxim/max77686/max77686.h
@@ -2,9 +2,6 @@
  *  Copyright (C) 2012 Samsung Electronics
  *  Alim Akhtar <alim.akhtar at samsung.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/drivers/maxim/max77802/max77802.h b/src/drivers/maxim/max77802/max77802.h
index 0ec06fd..8bd35f3 100644
--- a/src/drivers/maxim/max77802/max77802.h
+++ b/src/drivers/maxim/max77802/max77802.h
@@ -2,9 +2,6 @@
  *  Copyright (C) 2012 Samsung Electronics
  *  Rajeshwari Shinde <rajeshwari.s at samsung.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c
index 2616e8d..cd5d35d 100644
--- a/src/drivers/spi/gigadevice.c
+++ b/src/drivers/spi/gigadevice.c
@@ -6,9 +6,6 @@
  * Copyright 2008, Network Appliance Inc.
  * Jason McMullan <mcmullan at netapp.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
index 053744e..256b24e 100644
--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
@@ -10,9 +10,6 @@
  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c
index 2595214..0d4a7fa 100644
--- a/src/drivers/spi/spansion.c
+++ b/src/drivers/spi/spansion.c
@@ -6,9 +6,6 @@
  * TsiChung Liew (Tsi-Chung.Liew at freescale.com),
  * and  Jason McMullan (mcmullan at netapp.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c
index 9866e80..0779517 100644
--- a/src/drivers/spi/stmicro.c
+++ b/src/drivers/spi/stmicro.c
@@ -8,9 +8,6 @@
  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/ec/google/chromeec/ec_message.h b/src/ec/google/chromeec/ec_message.h
index a9d5a3c..ee15749 100644
--- a/src/ec/google/chromeec/ec_message.h
+++ b/src/ec/google/chromeec/ec_message.h
@@ -2,8 +2,6 @@
  * Chromium OS Matrix Keyboard Message Protocol definitions
  *
  * Copyright (c) 2012 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h
index 36bbb22..7d8f971 100644
--- a/src/include/spi-generic.h
+++ b/src/include/spi-generic.h
@@ -2,9 +2,6 @@
  * (C) Copyright 2001
  * Gerald Van Baren, Custom IDEAS, vanbaren at cideas.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index 24a5ab2..8b29df8 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -3,9 +3,6 @@
  *
  * Copyright (C) 2008 Atmel Corporation
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * version 2 as published by the Free Software Foundation.
diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c
index 1329f22..9807def 100644
--- a/src/lib/hexdump.c
+++ b/src/lib/hexdump.c
@@ -1,9 +1,6 @@
 /*
  * Copyright 2013 Google Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 380b23f..a630a91 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -1,9 +1,6 @@
 /*
  * Copyright (c) 2013 Google Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 453a719..6e85d56 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -2,9 +2,6 @@
  * Copyright (c) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index c159e20..64d58a3 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -1,9 +1,6 @@
 /*
  * Copyright (C) 2014 Google Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index 549e883..48be9bb 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -2,9 +2,6 @@
  * Copyright (C) 2014 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h
index b4470dc..9b30841 100644
--- a/src/soc/nvidia/tegra/dc.h
+++ b/src/soc/nvidia/tegra/dc.h
@@ -3,9 +3,6 @@
  *  (C) Copyright 2010
  *  NVIDIA Corporation <www.nvidia.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/soc/nvidia/tegra/pwm.h b/src/soc/nvidia/tegra/pwm.h
index 096686e..bb26689 100644
--- a/src/soc/nvidia/tegra/pwm.h
+++ b/src/soc/nvidia/tegra/pwm.h
@@ -3,9 +3,6 @@
  *  (C) Copyright 2010
  *  NVIDIA Corporation <www.nvidia.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h
index c845611..6c7dabc 100644
--- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h
+++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h
@@ -13,9 +13,6 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
  */
 
 /**
diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_param.h b/src/soc/nvidia/tegra132/include/soc/sdram_param.h
index 7688930..eafa6a5 100644
--- a/src/soc/nvidia/tegra132/include/soc/sdram_param.h
+++ b/src/soc/nvidia/tegra132/include/soc/sdram_param.h
@@ -13,9 +13,6 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
  */
 
 /**
diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h
index 018101e..529380d 100644
--- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h
+++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h
@@ -13,9 +13,6 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
  */
 
 /**
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
index 7030f1c..7f3d55f 100644
--- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
@@ -5,9 +5,6 @@
  *
  * Copyright (C) 2012 Samsung Electronics
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 5d18012..b664a63 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -3,9 +3,6 @@
  * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
  * Copyright (C) 2011 Stefan Tauner
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index e6d5fc2..8a4eabc 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -2,9 +2,6 @@
  * Copyright (c) 2011 The Chromium OS Authors.
  * Copyright (C) 2013, Intel Corporation.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of


From gerrit at coreboot.org  Sat Sep  5 15:26:28 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 5 Sep 2015 15:26:28 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: amd/geode_lx:
	make done_cache_as_ram_main global
References: <I84c3af0026f3f98bc64af007aa7cc196429f4e5f+0@gerrit.coreboot.org>
Message-ID: <E1ZYFMK-0004ee-QT@mail.coreboot.org>

the following patch was just integrated into master:
commit 649901e8e882d5aa14e94e4de611867ca678866b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 15:55:27 2015 -0500

    amd/geode_lx: make done_cache_as_ram_main global
    
    Current code written in C is calling a function implemented
    in assembly. However, the symbol's visibility is not set
    for such usage. Of course this works because MAINBOARDDIR/romstage.c
    is being processed into an assembly file currently.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built digitallogic/msm800sev while not changing romstage.c
         into an assembly file.
    
    Change-Id: I84c3af0026f3f98bc64af007aa7cc196429f4e5f
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11511
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11511 for details.

-gerrit


From gerrit at coreboot.org  Sat Sep  5 15:26:43 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 5 Sep 2015 15:26:43 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: amd/thatcher:
	include .c files with the right path
References: <If4fb1064a246b4fc11a958b07a0b76d9f9673898+0@gerrit.coreboot.org>
Message-ID: <E1ZYFMY-0004ha-Q5@mail.coreboot.org>

the following patch was just integrated into master:
commit 541b567167620c96de29c3bd1aec14c6742ae2b6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:03:07 2015 -0500

    amd/thatcher: include .c files with the right path
    
    The #include path during compilation already has '-I src'.
    Don't encode the src part of a path.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built amd/thatcher while compiling romstage.c with C compiler..
    
    Change-Id: If4fb1064a246b4fc11a958b07a0b76d9f9673898
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11512
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11512 for details.

-gerrit


From gerrit at coreboot.org  Sat Sep  5 15:36:26 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 5 Sep 2015 15:36:26 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: symbols: add
	'_' to pci_drivers and cpu_drivers symbols
References: <I8918b38db3b754332e8d8506b424f3c6b3e06af8+0@gerrit.coreboot.org>
Message-ID: <E1ZYFVy-00063u-67@mail.coreboot.org>

the following patch was just integrated into master:
commit 037581542b8e4571437ea34fb0244ad2ef43b6a3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 17:23:08 2015 -0500

    symbols: add '_' to pci_drivers and cpu_drivers symbols
    
    In order to prepare for more unification of the linker
    scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
    ecpu_drivers with an underscore.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built different boards includes ones w/ and w/o relocatable
         ramstage.
    
    Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11506
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11506 for details.

-gerrit


From gerrit at coreboot.org  Sat Sep  5 15:48:06 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 5 Sep 2015 15:48:06 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: qemu: fix vga
	driver build
References: <I9ec82a403d0264955d4b72496219036c7775c758+0@gerrit.coreboot.org>
Message-ID: <E1ZYFhF-0007Xt-VP@mail.coreboot.org>

the following patch was just integrated into master:
commit 0bc3e325c922a1528e75f668ff211f7310a4262b
Author: Gerd Hoffmann <kraxel at redhat.com>
Date:   Fri Sep 4 12:58:00 2015 +0200

    qemu: fix vga driver build
    
    Commit "7dbf9c6 edid: Use edid_mode struct to reduce redundancy" moved
    some fields from "struct edid" to "struct edid_mode".  Adapt the bochs
    and cirrus drivers to that change.
    
    Change-Id: I9ec82a403d0264955d4b72496219036c7775c758
    Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
    Reviewed-on: http://review.coreboot.org/11502
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/11502 for details.

-gerrit


From gerrit at coreboot.org  Sat Sep  5 15:49:06 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 5 Sep 2015 15:49:06 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: SeaBIOS:
	update stable release from 1.7.5 to 1.8.2
References: <Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101+0@gerrit.coreboot.org>
Message-ID: <E1ZYFiE-0007ey-Lz@mail.coreboot.org>

the following patch was just integrated into master:
commit 3ed0d85d527e929d862b4846625261e4189a9dce
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Wed Sep 2 00:02:56 2015 +0200

    SeaBIOS: update stable release from 1.7.5 to 1.8.2
    
    Several USB timing fixes for USB controllers on real hardware
    Initial support for USB3 hubs
    Initial support for SD cards (on QEMU only)
    Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG only)
    SeaVGABIOS improvements:
     Added cursor emulation to coreboot native init vgabios (cbvga)
     Added support for read character calls when in graphics mode
    
    Change-Id: Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
    Reviewed-on: http://review.coreboot.org/11479
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11479 for details.

-gerrit


From gerrit at coreboot.org  Sat Sep  5 16:11:49 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:11:49 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit e899d2ec6c553b820d871a62821bf8f0f753b2f4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Sat Sep  5 16:12:02 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:12:02 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit a6523c62394ec82d116e77cfed4cc338e5bc63d3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sat Sep  5 16:12:13 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:12:13 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 7205a8ec5688cc58710763704198b235aba58dd7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 23a24f2..8868a3f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Sat Sep  5 16:12:24 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:12:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit 9f5ea87a535b6962a74f776d25fc89b8445c8bf5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 54 +++++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++
 src/arch/x86/bootblock.ld                      | 29 ++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 32 files changed, 155 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..cf69868 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
 bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+	touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) $(objgenerated)/empty
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..7276c7a
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generated by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions at the beginning of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
new file mode 100644
index 0000000..6835430
--- /dev/null
+++ b/src/arch/x86/bootblock.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/x86/failover.ld>
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
+
+/* Include generated .ld files. */
+#include <generated/bootblock.ld>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Sat Sep  5 16:12:33 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:12:33 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	rosmtage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit e0ea8950fcea9297e3a57e9bfb2c488d768a879c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add rosmtage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8d07603..8311b11 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..b19b954
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Sat Sep  5 16:12:40 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:12:40 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit e31e50d19293590b6f82f9bbb24af6c1ef373c90
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Sat Sep  5 16:12:48 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:12:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit ff0bc7882fb8b354e72e194a63eb2a8d634b6926
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  67 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 218 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8311b11..23a24f2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..4900d3e
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+	SYMBOL_CURRENT_LOC(etext)
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Sat Sep  5 16:12:55 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:12:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: don't create
	MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit f4592227f29a2ef48f049c40725650ce90b4a2c3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index cf69868..8d07603 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -125,13 +125,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Sat Sep  5 16:12:58 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:12:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit 86d35596353ff2330aa36e3dbac653273a51186e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..2e7f88f 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,23 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/* Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Sat Sep  5 16:13:00 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:13:00 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: stash
References: <I17e5e8e4d8a541bb665b8b6d08ae43ed24e9d4fe+0@gerrit.coreboot.org>
Message-ID: <I17e5e8e4d8a541bb665b8b6d08ae43ed24e9d4fe+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11515

-gerrit

commit 3db4663b1607b434292e752eba33230a7d8487b4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    stash
    
    Change-Id: I17e5e8e4d8a541bb665b8b6d08ae43ed24e9d4fe
---
 src/vendorcode/google/chromeos/memlayout.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
index 29434bd..e86246f 100644
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ b/src/vendorcode/google/chromeos/memlayout.h
@@ -31,13 +31,13 @@
 
 #ifdef __VERSTAGE__
 	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Verstage exceeded its allotted size! (sz))); \
 		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
 #else
 	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
+		SET_COUNTER(verstage, addr) \
 		. += sz;
 #endif
 


From gerrit at coreboot.org  Sat Sep  5 16:13:02 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 16:13:02 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit a7a39e52530ea4f465a0bdd76fff655f54e56774
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 11:08:02 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 1a38256..02f67db 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,6 +139,33 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #if ENV_RAMSTAGE || ENV_ROMSTAGE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index e86246f..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(verstage, addr) \
-		_ = ASSERT(_eprogram - _program <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(verstage, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sat Sep  5 18:07:53 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 18:07:53 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit e87704b1108d0154fe76e5f6b45615ed83594af1
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Sat Sep  5 18:08:06 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 18:08:06 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 67f9dfe44f7b57365c53aec337f42c5a6d411848
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sat Sep  5 18:08:20 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 18:08:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 9889ad18a5bd1e62529b04b52fbe1006d5722416
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 23a24f2..8868a3f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Sat Sep  5 18:08:32 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 18:08:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit e304dbdd9d13b6f1f919af8ebba25d84fcc6303e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  66 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 217 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8311b11..23a24f2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..f4850d3
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Sat Sep  5 18:08:36 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 18:08:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit 4dc3c98750f690e86bc5ec3e9adc4c92cadd2de5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 11:08:02 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 1a38256..02f67db 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,6 +139,33 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #if ENV_RAMSTAGE || ENV_ROMSTAGE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index e86246f..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(verstage, addr) \
-		_ = ASSERT(_eprogram - _program <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(verstage, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sat Sep  5 18:08:39 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 18:08:39 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: stash
References: <I17e5e8e4d8a541bb665b8b6d08ae43ed24e9d4fe+0@gerrit.coreboot.org>
Message-ID: <I17e5e8e4d8a541bb665b8b6d08ae43ed24e9d4fe+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11515

-gerrit

commit b3468f79d27ff9eee5723f28200b87a757918f57
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    stash
    
    Change-Id: I17e5e8e4d8a541bb665b8b6d08ae43ed24e9d4fe
---
 src/vendorcode/google/chromeos/memlayout.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
index 29434bd..e86246f 100644
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ b/src/vendorcode/google/chromeos/memlayout.h
@@ -31,13 +31,13 @@
 
 #ifdef __VERSTAGE__
 	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Verstage exceeded its allotted size! (sz))); \
 		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
 #else
 	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
+		SET_COUNTER(verstage, addr) \
 		. += sz;
 #endif
 


From gerrit at coreboot.org  Sat Sep  5 18:08:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 18:08:41 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit d98f88c1e63d6892a2cf04197fc73732e0b12161
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    For starters, assume '_start' is the entry point for
    rmodules instead of __rmodule_entry. That's the
    majority of this patch's work diff. Second, add
    support for ENV_RMODULE so that one can distinguish the
    environment when generating linker scripts. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |  22 ++++++--
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   6 +-
 13 files changed, 66 insertions(+), 124 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..b5d8309 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..b3112e3 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBTLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 02f67db..ef47f6b 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
@@ -166,7 +166,7 @@
 	REGION(watchdog_tombstone, addr, size, 4) \
 	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
@@ -176,7 +176,7 @@
 #define CBMEM_INIT_HOOKS
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 #define DRIVERS_RODATA \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(pci_drivers) \
@@ -206,7 +206,7 @@
 #define  DATA_EXTRA \
 	PROVIDE(_preram_cbmem_console = .); \
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 #define DATA_EXTRA \
 	SYMBOL_CURRENT_LOC(bs_init_begin) \
 	KEEP(*(.bs_init)); \
@@ -217,8 +217,18 @@
 #define DATA_EXTRA
 #endif
 
+#if ENV_RMODULE
+#define RMODULE_PARAMS \
+	SYMBOL_CURRENT_LOC(rmodule_params) \
+	KEEP(*(.module_parameters)); \
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#else
+#define RMODULE_PARAMS
+#endif
+
 #define DATA_SECTION \
 	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	RMODULE_PARAMS \
 	*(.data); \
 	*(.data.*); \
 	DATA_EXTRA \
@@ -242,7 +252,7 @@
 #if ARCH_STAGE_HAS_HEAP_SECTION
 #define HEAP_SECTION \
 	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
-	. += CONFIG_HEAP_SIZE ; \
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE); \
 	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
 #else
 #define HEAP_SECTION
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index 2e7f88f..c9d3f59 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /* Default case of nothing set for random blob generation using
@@ -80,6 +95,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..3b127b2 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,7 +416,7 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
+	if (populate_sym(ctx, "_start", &ctx->entry, nsyms, strtab))
 		return -1;
 
 	/* Link address is the virtual address of the program segment. */


From gerrit at coreboot.org  Sat Sep  5 18:18:44 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sat, 5 Sep 2015 18:18:44 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: rmodtool: honor
	ELF entry point
References: <I53e9c6eaa1ce761ab8519677fe2f4d0d2b82bb40+0@gerrit.coreboot.org>
Message-ID: <I53e9c6eaa1ce761ab8519677fe2f4d0d2b82bb40+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11518

-gerrit

commit e8e0e7d0433385f43118c3d277083a5618dfc928
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:17:25 2015 -0500

    rmodtool: honor ELF entry point
    
    Instead of using a pre-determined symbol, _start, use
    the entry point within the ELF header.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: I53e9c6eaa1ce761ab8519677fe2f4d0d2b82bb40
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 3b127b2..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_start", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Sat Sep  5 18:25:28 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sat, 5 Sep 2015 18:25:28 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: smmhandler: on
	i945..nehalem, crash if LAPIC overlaps with ASEG
References: <I508c0b10ab88779da81d18a94b08dcfeca6f5a6f+0@gerrit.coreboot.org>
Message-ID: <I508c0b10ab88779da81d18a94b08dcfeca6f5a6f+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11519

-gerrit

commit 21716a5d3464e183c6fa08a215591a2aff5bc617
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Sep 5 20:21:24 2015 +0200

    smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG
    
    This mitigates the Memory Sinkhole issue (described on
    https://github.com/xoreaxeaxeax/sinkhole) by checking for the issue and
    crashing the system explicitly if LAPIC overlaps ASEG.
    This needs to happen without a data access (only code fetches) because
    data accesses could be tampered with.
    
    Don't try to recover because, if somebody tried to do shenanigans like
    these, we have to expect more.
    Sandybridge is safe because it does the same test in hardware, and
    crashes. Newer chipsets presumably do the same.
    
    This needs to be extended to deal with overlapping TSEG as well.
    
    Change-Id: I508c0b10ab88779da81d18a94b08dcfeca6f5a6f
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/cpu/x86/smm/smmhandler.S | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 7b70ce9..f2094ef 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -25,6 +25,10 @@
  * to 64k if we can though.
  */
 
+#include <kconfig.h>
+#include <config.h>
+#define LAPIC_BASE_MSR 0x1b
+
 /*
  * +--------------------------------+ 0xaffff
  * |  Save State Map Node 0         |
@@ -74,8 +78,39 @@
  *
  * All the bad magic is not all that bad after all.
  */
+#define SMM_START 0xa0000
+#define SMM_END   0xb0000
+#if SMM_END <= SMM_START
+#error invalid SMM configuration
+#endif
 .global smm_handler_start
 smm_handler_start:
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) || \
+    IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_GM45) || \
+    IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_I945)
+	mov	$LAPIC_BASE_MSR, %ecx
+	rdmsr
+	and	$(~0xfff), %eax
+	sub	$(SMM_START), %eax
+	cmp	$(SMM_END - SMM_START), %eax
+	ja	untampered_lapic
+1:
+	// "Crash"
+	mov	$(CONFIG_TTYS0_BASE), %dx
+	mov	$'C', %al
+	out	%al, (%dx)
+	mov	$'r', %al
+	out	%al, (%dx)
+	mov	$'a', %al
+	out	%al, (%dx)
+	mov	$'s', %al
+	out	%al, (%dx)
+	mov	$'h', %al
+	out	%al, (%dx)
+	// now crash for real
+	ud2
+untampered_lapic:
+#endif
 	movw    $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx
 	data32  lgdt %cs:(%bx)
 


From gerrit at coreboot.org  Sun Sep  6 06:11:09 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Sun, 6 Sep 2015 06:11:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: buildgcc: Show
	the progress when downloading *still working*.
References: <I4559e88d541738a594dce92e23589992f234cb9b+0@gerrit.coreboot.org>
Message-ID: <I4559e88d541738a594dce92e23589992f234cb9b+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11520

-gerrit

commit 1f6246dd823c1d3cb39603a177d1aa5ee2c345c6
Author: zbao <fishbaozi at gmail.com>
Date:   Sun Sep 6 02:10:42 2015 -0400

    buildgcc: Show the progress when downloading *still working*.
    
    For some systems, the commands are buffered by default. On these
    systems, the progress can not been seen, except the final "ok".
    
    Change-Id: I4559e88d541738a594dce92e23589992f234cb9b
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 0ed9a39..a8612ca 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -188,6 +188,13 @@ compute_sum() {
 	printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}"
 }
 
+download_one() {
+	url=$1
+	printf " ..    "
+	wget --no-check-certificate $url 2>&1 | grep --line-buffered -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}'
+	printf "\b\b\b\b${green} ok${NC}"
+}
+
 download() {
 	package=$1
 	archive="$(eval echo \$$package"_ARCHIVE")"
@@ -201,14 +208,13 @@ download() {
 		printf "(downloading from $archive)"
 		rm -f tarballs/$FILE
 		cd tarballs
-		wget --no-check-certificate -q $archive
-		wgetret=$?
+		download_one $archive
 		cd ..
 		compute_sum $FILE
 	fi
 
 	if [ ! -f tarballs/$FILE ]; then
-		printf "\n${RED}Failed to download $FILE. Wget returns $wgetret. See 'man wget'.${NC}\n"
+		printf "\n${RED}Failed to download $FILE.${NC}\n"
 		exit 1
 	fi
 	printf "\n"


From gerrit at coreboot.org  Sun Sep  6 08:45:13 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Sun, 6 Sep 2015 08:45:13 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Show
	the progress when downloading
References: <I4559e88d541738a594dce92e23589992f234cb9b+0@gerrit.coreboot.org>
Message-ID: <I4559e88d541738a594dce92e23589992f234cb9b+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11520

-gerrit

commit f89f6137312ce006b50364c75e69e66d5b0e15d9
Author: zbao <fishbaozi at gmail.com>
Date:   Sun Sep 6 04:44:38 2015 -0400

    buildgcc: Show the progress when downloading
    
    Change-Id: I4559e88d541738a594dce92e23589992f234cb9b
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 0ed9a39..a2c4b81 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -188,6 +188,14 @@ compute_sum() {
 	printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}"
 }
 
+download_one() {
+	url=$1
+	printf " ..  0%%"
+	wget --no-check-certificate $url 2>&1 | while read line; do
+		echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}'
+	done
+}
+
 download() {
 	package=$1
 	archive="$(eval echo \$$package"_ARCHIVE")"
@@ -201,14 +209,13 @@ download() {
 		printf "(downloading from $archive)"
 		rm -f tarballs/$FILE
 		cd tarballs
-		wget --no-check-certificate -q $archive
-		wgetret=$?
+		download_one $archive
 		cd ..
 		compute_sum $FILE
 	fi
 
 	if [ ! -f tarballs/$FILE ]; then
-		printf "\n${RED}Failed to download $FILE. Wget returns $wgetret. See 'man wget'.${NC}\n"
+		printf "\n${RED}Failed to download $FILE.${NC}\n"
 		exit 1
 	fi
 	printf "\n"


From gerrit at coreboot.org  Sun Sep  6 09:00:41 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Sun, 6 Sep 2015 09:00:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Show
	the progress when downloading
References: <I4559e88d541738a594dce92e23589992f234cb9b+0@gerrit.coreboot.org>
Message-ID: <I4559e88d541738a594dce92e23589992f234cb9b+3@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11520

-gerrit

commit eba84def407643d05044bedaf1f45032f17d2efc
Author: zbao <fishbaozi at gmail.com>
Date:   Sun Sep 6 05:00:04 2015 -0400

    buildgcc: Show the progress when downloading
    
    Leave the final "100%" unerased.
    Checking return code of wget is removed.
    
    Change-Id: I4559e88d541738a594dce92e23589992f234cb9b
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 0ed9a39..ed233d8 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -188,6 +188,14 @@ compute_sum() {
 	printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}"
 }
 
+download_showing_percentage() {
+	url=$1
+	printf " ..  0%%"
+	wget --no-check-certificate $url 2>&1 | while read line; do
+		echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}'
+	done
+}
+
 download() {
 	package=$1
 	archive="$(eval echo \$$package"_ARCHIVE")"
@@ -201,14 +209,13 @@ download() {
 		printf "(downloading from $archive)"
 		rm -f tarballs/$FILE
 		cd tarballs
-		wget --no-check-certificate -q $archive
-		wgetret=$?
+		download_showing_percentage $archive
 		cd ..
 		compute_sum $FILE
 	fi
 
 	if [ ! -f tarballs/$FILE ]; then
-		printf "\n${RED}Failed to download $FILE. Wget returns $wgetret. See 'man wget'.${NC}\n"
+		printf "\n${RED}Failed to download $FILE.${NC}\n"
 		exit 1
 	fi
 	printf "\n"


From gerrit at coreboot.org  Sun Sep  6 17:08:35 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:08:35 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 7c5f9f6c4481d315eb3e66ebd3fbc2f783d4581f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Sun Sep  6 17:08:49 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:08:49 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 56b8087db90e87d2f82aee25ed1fd04034d674a6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 17:09:03 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:09:03 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit a36bc5f21b9c6c7b30530ccdacfe61a525096883
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7337f1e..4c88a27 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Sun Sep  6 17:09:13 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:09:13 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit bd7a4bb41586c7305b4713189c0e437dd518f563
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 54 +++++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++
 src/arch/x86/bootblock.ld                      | 29 ++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 32 files changed, 155 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..f58c142 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
 bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+	touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter-out, $(obj)/arch/x86/bootblock.bootblock.ld, $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..7276c7a
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generated by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions at the beginning of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
new file mode 100644
index 0000000..6835430
--- /dev/null
+++ b/src/arch/x86/bootblock.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/x86/failover.ld>
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
+
+/* Include generated .ld files. */
+#include <generated/bootblock.ld>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Sun Sep  6 17:09:21 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:09:21 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	rosmtage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit 14e0cc726df3643d978b028b0a2f0a457898605f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add rosmtage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8f8e4bc..f6379ab 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..b19b954
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Sun Sep  6 17:09:31 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:09:31 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit a0475c1bf2fb71fce888ab1f5a0898fce2090e99
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Sun Sep  6 17:09:43 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:09:43 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 37674403b3946fd49c68ef5871a6d74ef6678b0f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  66 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 217 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f6379ab..7337f1e 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..f4850d3
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Sun Sep  6 17:09:46 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:09:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit b36f52dea5df396d125afaacde183955a76faa5c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 1a38256..02f67db 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,6 +139,33 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #if ENV_RAMSTAGE || ENV_ROMSTAGE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 17:09:47 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:09:47 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit e06a906165adfe88a99d14529e6b4733bd821963
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |  22 ++++++--
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 13 files changed, 67 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..b5d8309 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..b3112e3 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBTLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 02f67db..ef47f6b 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
@@ -166,7 +166,7 @@
 	REGION(watchdog_tombstone, addr, size, 4) \
 	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
@@ -176,7 +176,7 @@
 #define CBMEM_INIT_HOOKS
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 #define DRIVERS_RODATA \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(pci_drivers) \
@@ -206,7 +206,7 @@
 #define  DATA_EXTRA \
 	PROVIDE(_preram_cbmem_console = .); \
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 #define DATA_EXTRA \
 	SYMBOL_CURRENT_LOC(bs_init_begin) \
 	KEEP(*(.bs_init)); \
@@ -217,8 +217,18 @@
 #define DATA_EXTRA
 #endif
 
+#if ENV_RMODULE
+#define RMODULE_PARAMS \
+	SYMBOL_CURRENT_LOC(rmodule_params) \
+	KEEP(*(.module_parameters)); \
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#else
+#define RMODULE_PARAMS
+#endif
+
 #define DATA_SECTION \
 	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	RMODULE_PARAMS \
 	*(.data); \
 	*(.data.*); \
 	DATA_EXTRA \
@@ -242,7 +252,7 @@
 #if ARCH_STAGE_HAS_HEAP_SECTION
 #define HEAP_SECTION \
 	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
-	. += CONFIG_HEAP_SIZE ; \
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE); \
 	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
 #else
 #define HEAP_SECTION
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index 2e7f88f..c9d3f59 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /* Default case of nothing set for random blob generation using
@@ -80,6 +95,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Sun Sep  6 17:09:56 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:09:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: don't create
	MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit 557de991414d1340fabbd4619ed3a2adaffb85ad
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f58c142..8f8e4bc 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -125,13 +125,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Sun Sep  6 17:10:04 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:10:04 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit 91a1abe3ad8df72dfa5b68a276053784a718d19f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..2e7f88f 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,23 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/* Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Sun Sep  6 17:10:06 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:10:06 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit bdaffefe0ddf3a7bae7cb7fd4ebadac03c53a8f3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 4c88a27..bbbe273 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..1724a73
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 9c44b13..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		POINTER_ALIGN
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Sun Sep  6 17:10:07 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:10:07 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: linking: add
	and use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit 718bf308e2181e74917391650c94b097831aec60
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..5294b69 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index bbbe273..fc1a7c8 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -292,7 +292,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Sun Sep  6 17:10:08 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:10:08 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit 6a7b810eb774ecc72ad7ff341106f443f88707e8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Sun Sep  6 17:10:10 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:10:10 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit 4e9869685f2cb10e9fa6d4740f0bdb49d55ebcea
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/include/memlayout.h   |  6 +++---
 src/lib/Makefile.inc      |  9 ++++++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index fc1a7c8..e6b7484 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -276,17 +276,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index ef47f6b..82fa73e 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -166,7 +166,7 @@
 	REGION(watchdog_tombstone, addr, size, 4) \
 	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
@@ -176,7 +176,7 @@
 #define CBMEM_INIT_HOOKS
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 #define DRIVERS_RODATA \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(pci_drivers) \
@@ -206,7 +206,7 @@
 #define  DATA_EXTRA \
 	PROVIDE(_preram_cbmem_console = .); \
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 #define DATA_EXTRA \
 	SYMBOL_CURRENT_LOC(bs_init_begin) \
 	KEEP(*(.bs_init)); \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@


From gerrit at coreboot.org  Sun Sep  6 17:39:58 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:39:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 0aeeab0a18974a10ef2bb8fe6a950fc6a9fc4dac
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Sun Sep  6 17:40:17 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:40:17 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 70f201fa83e6ca04ae550dea52ef2dc884a67fbc
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 17:40:35 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:40:35 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 5a5e43a3b269a54732b51e30720e043d0cae949c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9d3f07f..0b8058f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Sun Sep  6 17:40:46 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:40:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	rosmtage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit 0a91aeec5940b719a559ef17b347c86144185573
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add rosmtage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 00d8d27..fe974ef 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..b19b954
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Sun Sep  6 17:41:00 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:00 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit c4552e5be1e76e36abf5e26d5464b668a795cc29
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Sun Sep  6 17:41:15 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:15 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit d478c79c2f34c6b0efe68f8231b04f6ee45fef44
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               | 126 ++++++++++++++++++++++++++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    |  66 ++++++++++++++++++
 src/lib/ramstage.ld                   | 115 -------------------------------
 7 files changed, 217 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index fe974ef..9d3f07f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
 		. += sz;
 #endif
 
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+	KEEP(*(.rodata.cbmem_init_hooks)); \
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(pci_drivers) \
+	KEEP(*(.rodata.pci_driver)); \
+	SYMBOL_CURRENT_LOC(epci_drivers) \
+	POINTER_ALIGN \
+	SYMBOL_CURRENT_LOC(cpu_drivers) \
+	KEEP(*(.rodata.cpu_driver)); \
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+	.##name : { \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+	ALIGN_COUNTER(align) \
+	SYMBOL_CURRENT_LOC(e##name) \
+	}
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define  DATA_EXTRA \
+	PROVIDE(_preram_cbmem_console = .); \
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+	SYMBOL_CURRENT_LOC(bs_init_begin) \
+	KEEP(*(.bs_init)); \
+	LONG(0); \
+	LONG(0); \
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	*(.data); \
+	*(.data.*); \
+	DATA_EXTRA \
+	END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+	BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+	*(.bss) \
+	*(.bss.*) \
+	*(.sbss) \
+	*(.sbss.*) \
+	END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+	. += CONFIG_HEAP_SIZE ; \
+	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..f4850d3
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+	SYMBOL_CURRENT_LOC(program)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	POINTER_ALIGN
+	CBMEM_INIT_HOOKS
+	DRIVERS_RODATA
+	*(.rodata);
+	*(.rodata.*);
+	POINTER_ALIGN
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Sun Sep  6 17:41:20 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit d54cd08002f2d831e29519b3c827aa17ae3976d5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 1a38256..02f67db 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,6 +139,33 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #if ENV_RAMSTAGE || ENV_ROMSTAGE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 17:41:22 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:22 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit 6ee4e8627cac4c433acb0095490f012905454c9e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0b8058f..9e5110f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..1724a73
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 9c44b13..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		POINTER_ALIGN
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Sun Sep  6 17:41:25 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:25 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit 75034faafe688b667bd99c9394070405ec377aed
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |  22 ++++++--
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 13 files changed, 67 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..b5d8309 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..b3112e3 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBTLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 02f67db..ef47f6b 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
@@ -166,7 +166,7 @@
 	REGION(watchdog_tombstone, addr, size, 4) \
 	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
@@ -176,7 +176,7 @@
 #define CBMEM_INIT_HOOKS
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 #define DRIVERS_RODATA \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(pci_drivers) \
@@ -206,7 +206,7 @@
 #define  DATA_EXTRA \
 	PROVIDE(_preram_cbmem_console = .); \
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 #define DATA_EXTRA \
 	SYMBOL_CURRENT_LOC(bs_init_begin) \
 	KEEP(*(.bs_init)); \
@@ -217,8 +217,18 @@
 #define DATA_EXTRA
 #endif
 
+#if ENV_RMODULE
+#define RMODULE_PARAMS \
+	SYMBOL_CURRENT_LOC(rmodule_params) \
+	KEEP(*(.module_parameters)); \
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#else
+#define RMODULE_PARAMS
+#endif
+
 #define DATA_SECTION \
 	BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+	RMODULE_PARAMS \
 	*(.data); \
 	*(.data.*); \
 	DATA_EXTRA \
@@ -242,7 +252,7 @@
 #if ARCH_STAGE_HAS_HEAP_SECTION
 #define HEAP_SECTION \
 	BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
-	. += CONFIG_HEAP_SIZE ; \
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE); \
 	END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
 #else
 #define HEAP_SECTION
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index 2e7f88f..c9d3f59 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /* Default case of nothing set for random blob generation using
@@ -80,6 +95,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Sun Sep  6 17:41:27 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:27 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit 75d89572255b43559c584b38446cefaffac01522
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..5294b69 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9e5110f..b018f7c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -292,7 +292,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Sun Sep  6 17:41:31 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:31 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit c71a7cb5d29267a784b9ce9242c07200eb960491
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Sun Sep  6 17:41:35 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:35 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit 8caecddd634b185ac2aa83f1eb0f5cc9d2287a71
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/include/memlayout.h   |  6 +++---
 src/lib/Makefile.inc      |  9 ++++++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b018f7c..885bb7f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -276,17 +276,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index ef47f6b..82fa73e 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -166,7 +166,7 @@
 	REGION(watchdog_tombstone, addr, size, 4) \
 	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
@@ -176,7 +176,7 @@
 #define CBMEM_INIT_HOOKS
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 #define DRIVERS_RODATA \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(pci_drivers) \
@@ -206,7 +206,7 @@
 #define  DATA_EXTRA \
 	PROVIDE(_preram_cbmem_console = .); \
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 #define DATA_EXTRA \
 	SYMBOL_CURRENT_LOC(bs_init_begin) \
 	KEEP(*(.bs_init)); \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@


From gerrit at coreboot.org  Sun Sep  6 17:41:43 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:43 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit 4229ee11cb98568ef3bc683b8a9ae4c0b778ab69
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..2e7f88f 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,23 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/* Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Sun Sep  6 17:41:55 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:41:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit cac9e96d48182e2362910ef7ed2fd4c8484bb6ea
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 54 +++++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++
 src/arch/x86/bootblock.ld                      | 29 ++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 32 files changed, 155 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..b0546f5 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
 bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+	touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock.ld, $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..7276c7a
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generated by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions at the beginning of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
new file mode 100644
index 0000000..6835430
--- /dev/null
+++ b/src/arch/x86/bootblock.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/x86/failover.ld>
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
+
+/* Include generated .ld files. */
+#include <generated/bootblock.ld>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Sun Sep  6 17:42:06 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 17:42:06 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: don't create
	MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit e7c0dcf2e104c47af8fe19d9d7e5f984a1012fae
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b0546f5..00d8d27 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -125,13 +125,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Sun Sep  6 18:15:24 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 18:15:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit 0356d2f9bf545ba896b69b2f1ce928a3e5c8d116
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9e5110f..b018f7c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -292,7 +292,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Sun Sep  6 18:15:28 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 18:15:28 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit 2e2e6689a7e6b82a0c01d01b51e94a00f748872d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Sun Sep  6 18:15:32 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 18:15:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit 83aa23ce623ddae141b4dab070e4e945e392eae6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/include/memlayout.h   |  6 +++---
 src/lib/Makefile.inc      |  9 ++++++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b018f7c..885bb7f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -276,17 +276,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index ef47f6b..82fa73e 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -166,7 +166,7 @@
 	REGION(watchdog_tombstone, addr, size, 4) \
 	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 #define CBMEM_INIT_HOOKS \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
@@ -176,7 +176,7 @@
 #define CBMEM_INIT_HOOKS
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 #define DRIVERS_RODATA \
 	POINTER_ALIGN \
 	SYMBOL_CURRENT_LOC(pci_drivers) \
@@ -206,7 +206,7 @@
 #define  DATA_EXTRA \
 	PROVIDE(_preram_cbmem_console = .); \
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 #define DATA_EXTRA \
 	SYMBOL_CURRENT_LOC(bs_init_begin) \
 	KEEP(*(.bs_init)); \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@


From gerrit at coreboot.org  Sun Sep  6 19:26:39 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:26:39 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 78f9a89214fe738b16c3ec00302d6adc617bfbe3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Sun Sep  6 19:26:58 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:26:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+12@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 1d3e9ba7dbd1a538b181e09939b6fd4615515ad1
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3963339..5f9c3c1 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 19:27:18 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:27:18 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+12@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 5a1ff771504c78d5d2173ee8f3980b9ea3aad291
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9d3f07f..0b8058f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..9c44b13 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		POINTER_ALIGN
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Sun Sep  6 19:27:34 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:27:34 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 9fca8f2d0be467d5a8c917614505918338d2cf84
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               |  42 +++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    | 129 ++++++++++++++++++++++++++++++++++
 src/lib/ramstage.ld                   | 115 ------------------------------
 7 files changed, 196 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index fe974ef..9d3f07f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3963339 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,12 +127,12 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..9fb179c
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+.text : {
+	SYMBOL_CURRENT_LOC(program)
+	SYMBOL_CURRENT_LOC(text)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
+	KEEP(*(.rodata.cbmem_init_hooks));
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#endif
+
+#if ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(pci_drivers)
+	KEEP(*(.rodata.pci_driver));
+	SYMBOL_CURRENT_LOC(epci_drivers)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cpu_drivers)
+	KEEP(*(.rodata.cpu_driver));
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	*(.rodata);
+	*(.rodata.*);
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(etext)
+} : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+.ctors : {
+	ALIGN_COUNTER(0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+}
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+#if ARCH_STAGE_HAS_DATA_SECTION
+.data : {
+	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(data)
+	*(.data);
+	*(.data.*);
+
+#ifdef __PRE_RAM__
+	PROVIDE(_preram_cbmem_console = .);
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+	SYMBOL_CURRENT_LOC(bs_init_begin)
+	KEEP(*(.bs_init));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(edata)
+}
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+.bss : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bss)
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(ebss)
+}
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+.heap : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(heap)
+	. += CONFIG_HEAP_SIZE;
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(eheap)
+}
+#endif
+
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Sun Sep  6 19:27:42 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:27:42 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit 45d15c45e4aa90df99a38e7fddc4cade3541a5ac
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 5f9c3c1..d4be3f8 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,4 +139,31 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 19:27:46 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:27:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit 6fa0ea6534558724a88fb233b0f616d74946d893
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |   4 +-
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/program.ld                    |  15 +++--
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 14 files changed, 64 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..b5d8309 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..b3112e3 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBTLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index d4be3f8..a25e018 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index 56cad3a..b460840 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /* Default case of nothing set for random blob generation using
@@ -81,6 +96,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 9fb179c..e30a945 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -74,13 +74,20 @@
 .data : {
 	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(data)
+
+#if ENV_RMODULE
+	SYMBOL_CURRENT_LOC(rmodule_params)
+	KEEP(*(.module_parameters));
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#endif
+
 	*(.data);
 	*(.data.*);
 
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
 	LONG(0);
@@ -110,7 +117,7 @@
 .heap : {
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(heap)
-	. += CONFIG_HEAP_SIZE;
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(eheap)
 }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Sun Sep  6 19:27:52 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:27:52 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit e5b450aad6509e6587e75b9744ee47a036515e40
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0b8058f..9e5110f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..6793ca1
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 9c44b13..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		POINTER_ALIGN
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Sun Sep  6 19:27:58 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:27:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit 80e5df5e9f5d9103fd7ff5d26cd2f2daf2888789
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9e5110f..b018f7c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -292,7 +292,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Sun Sep  6 19:28:04 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:28:04 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit 352cc3a119a86d12de1e6e221bd0e27118f73e5a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Sun Sep  6 19:28:10 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:28:10 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit 3b473d038d4e5dc1f92b725d712e717ce5f08136
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/lib/Makefile.inc      |  9 ++++++---
 src/lib/program.ld        |  6 +++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b018f7c..885bb7f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -276,17 +276,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
diff --git a/src/lib/program.ld b/src/lib/program.ld
index e30a945..f776541 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -87,7 +87,7 @@
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
 	LONG(0);


From gerrit at coreboot.org  Sun Sep  6 19:28:19 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:28:19 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit 7c53b85aa0c14e719b5dbbda97b005d7c748c456
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..56cad3a 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,24 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/* Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. */
+#warning Unknown environment used for compiling/linking.
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Sun Sep  6 19:34:14 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:34:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+13@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 07cf8ef3412b37d801b95870da9bc529ff9bd726
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9d3f07f..0b8058f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..4bb7250 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Sun Sep  6 19:34:21 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:34:21 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit b7393513a5a06cf757235749041921345fb5940f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 5f9c3c1..d4be3f8 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,4 +139,31 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 19:34:25 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:34:25 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit da985e263f763e3f1267e232da639d239b5cab99
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |   4 +-
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/program.ld                    |  15 +++--
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 14 files changed, 64 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..b5d8309 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..b3112e3 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBTLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index d4be3f8..a25e018 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index 56cad3a..b460840 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /* Default case of nothing set for random blob generation using
@@ -81,6 +96,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 9fb179c..e30a945 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -74,13 +74,20 @@
 .data : {
 	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(data)
+
+#if ENV_RMODULE
+	SYMBOL_CURRENT_LOC(rmodule_params)
+	KEEP(*(.module_parameters));
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#endif
+
 	*(.data);
 	*(.data.*);
 
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
 	LONG(0);
@@ -110,7 +117,7 @@
 .heap : {
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(heap)
-	. += CONFIG_HEAP_SIZE;
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(eheap)
 }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Sun Sep  6 19:34:28 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:34:28 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit 4aaa96a41e6d1a21be8503f5cb1c0509f7faa5a2
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0b8058f..9e5110f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..6793ca1
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 4bb7250..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Sun Sep  6 19:34:35 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:34:35 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit bfef79725dc8aef0011188635b08c1315b92fca7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9e5110f..b018f7c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -292,7 +292,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Sun Sep  6 19:34:43 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:34:43 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit 8a00d63a1146a7b78679e2e7b66263612ae6e957
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Sun Sep  6 19:34:49 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 19:34:49 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit a7c0417c1366e8a3b5bfbe1c2e3d2715844b86bd
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/lib/Makefile.inc      |  9 ++++++---
 src/lib/program.ld        |  6 +++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b018f7c..885bb7f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -276,17 +276,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
diff --git a/src/lib/program.ld b/src/lib/program.ld
index e30a945..f776541 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -87,7 +87,7 @@
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
 	LONG(0);


From gerrit at coreboot.org  Sun Sep  6 21:28:14 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:28:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+12@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 4053f51ef9d07ca95906daed9b763c5a9c1d6428
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Sun Sep  6 21:28:36 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:28:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+13@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit f473580c7d2e56a47f69614e1f5823332d2d49ff
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3963339..5f9c3c1 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 21:29:00 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:29:00 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+14@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit cef193cac4dc662ad13e40072a657a1601697c48
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9d3f07f..0b8058f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..4bb7250 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Sun Sep  6 21:29:18 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:29:18 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+12@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 62315abd4958889b33ee05e72a3327cf5a667ab6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               |  42 +++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    | 129 ++++++++++++++++++++++++++++++++++
 src/lib/ramstage.ld                   | 115 ------------------------------
 7 files changed, 196 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index fe974ef..9d3f07f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3963339 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,12 +127,12 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..9fb179c
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+.text : {
+	SYMBOL_CURRENT_LOC(program)
+	SYMBOL_CURRENT_LOC(text)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
+	KEEP(*(.rodata.cbmem_init_hooks));
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#endif
+
+#if ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(pci_drivers)
+	KEEP(*(.rodata.pci_driver));
+	SYMBOL_CURRENT_LOC(epci_drivers)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cpu_drivers)
+	KEEP(*(.rodata.cpu_driver));
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	*(.rodata);
+	*(.rodata.*);
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(etext)
+} : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+.ctors : {
+	ALIGN_COUNTER(0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+}
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+#if ARCH_STAGE_HAS_DATA_SECTION
+.data : {
+	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(data)
+	*(.data);
+	*(.data.*);
+
+#ifdef __PRE_RAM__
+	PROVIDE(_preram_cbmem_console = .);
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+	SYMBOL_CURRENT_LOC(bs_init_begin)
+	KEEP(*(.bs_init));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(edata)
+}
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+.bss : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bss)
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(ebss)
+}
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+.heap : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(heap)
+	. += CONFIG_HEAP_SIZE;
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(eheap)
+}
+#endif
+
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Sun Sep  6 21:29:27 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:29:27 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit d46bd0c22d612054f84ce6bcbc7ad2ddd54367a9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 5f9c3c1..d4be3f8 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,4 +139,31 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Sun Sep  6 21:29:36 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:29:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit 32fb04f99a98ed54335d9d0da0fdb6417ae88a2b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |   4 +-
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/program.ld                    |  15 +++--
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 14 files changed, 64 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..b5d8309 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..b3112e3 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBTLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index d4be3f8..a25e018 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index d147d3c..1563f2d 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /*
@@ -84,6 +99,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 9fb179c..e30a945 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -74,13 +74,20 @@
 .data : {
 	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(data)
+
+#if ENV_RMODULE
+	SYMBOL_CURRENT_LOC(rmodule_params)
+	KEEP(*(.module_parameters));
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#endif
+
 	*(.data);
 	*(.data.*);
 
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
 	LONG(0);
@@ -110,7 +117,7 @@
 .heap : {
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(heap)
-	. += CONFIG_HEAP_SIZE;
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(eheap)
 }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Sun Sep  6 21:29:43 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:29:43 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit cd152e95db7d51639b67de7a7b0b31026e587528
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0b8058f..9e5110f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..6793ca1
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 4bb7250..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Sun Sep  6 21:29:55 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:29:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit eae0c477c7a507ff50950b9193321c2bec058558
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9e5110f..b018f7c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -292,7 +292,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Sun Sep  6 21:30:05 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:30:05 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit da726e933829941e23b87610fe7bfff72b190e03
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Sun Sep  6 21:30:14 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:30:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit d12ef8dfad8b39733bab9a0bba4b91ab1a1a24fa
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/lib/Makefile.inc      |  9 ++++++---
 src/lib/program.ld        |  6 +++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b018f7c..885bb7f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -276,17 +276,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
diff --git a/src/lib/program.ld b/src/lib/program.ld
index e30a945..f776541 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -87,7 +87,7 @@
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
 	LONG(0);


From gerrit at coreboot.org  Sun Sep  6 21:30:27 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Sun, 6 Sep 2015 21:30:27 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit 4f633859fd732f82ada8dbc823055e90d7318eae
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..d147d3c 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,27 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/*
+ * Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. Also AGES
+ * apparently builds compeletely separate from our build infrastructure
+ * hardcoding its own rules.
+ */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Mon Sep  7 01:52:35 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:52:35 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+13@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 2d690cac9075ef091e07c9058cc7765f53ca7625
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Mon Sep  7 01:52:59 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:52:59 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+14@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit bacf9bc031ed25f4c947fddb31d2c0adbdaba879
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3963339..5f9c3c1 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Mon Sep  7 01:53:21 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:53:21 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+15@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 03a7b6ddd969085c34b7b03a55ac8e353ed6cc37
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9d3f07f..0b8058f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..4bb7250 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Mon Sep  7 01:53:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:53:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+13@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 6a2304404ac9d2b948d6a24ee23327de7ba6f989
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               |  42 +++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    | 130 ++++++++++++++++++++++++++++++++++
 src/lib/ramstage.ld                   | 115 ------------------------------
 7 files changed, 197 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index fe974ef..9d3f07f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3963339 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,12 +127,12 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..02d017a
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+.text : {
+	SYMBOL_CURRENT_LOC(program)
+	SYMBOL_CURRENT_LOC(text)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
+	KEEP(*(.rodata.cbmem_init_hooks));
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#endif
+
+#if ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(pci_drivers)
+	KEEP(*(.rodata.pci_driver));
+	SYMBOL_CURRENT_LOC(epci_drivers)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cpu_drivers)
+	KEEP(*(.rodata.cpu_driver));
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	*(.rodata);
+	*(.rodata.*);
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(etext)
+} : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+.ctors : {
+	ALIGN_COUNTER(0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+}
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+#if ARCH_STAGE_HAS_DATA_SECTION
+.data : {
+	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(data)
+	*(.data);
+	*(.data.*);
+
+#ifdef __PRE_RAM__
+	PROVIDE(_preram_cbmem_console = .);
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bs_init_begin)
+	KEEP(*(.bs_init));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(edata)
+}
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+.bss : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bss)
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(ebss)
+}
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+.heap : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(heap)
+	. += CONFIG_HEAP_SIZE;
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(eheap)
+}
+#endif
+
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Mon Sep  7 01:53:52 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:53:52 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit 95548a50de28612c651adf2bba9aeb9ab3d656d5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 5f9c3c1..d4be3f8 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,4 +139,31 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Mon Sep  7 01:54:01 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:54:01 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit 6708549d6f5f9a1a3aee6b5bd26fa1299d7ae272
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |   4 +-
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/program.ld                    |  15 +++--
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 14 files changed, 64 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..b5d8309 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..b3112e3 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBTLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index d4be3f8..a25e018 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index d147d3c..1563f2d 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /*
@@ -84,6 +99,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 02d017a..43b1fea 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -74,13 +74,20 @@
 .data : {
 	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(data)
+
+#if ENV_RMODULE
+	SYMBOL_CURRENT_LOC(rmodule_params)
+	KEEP(*(.module_parameters));
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#endif
+
 	*(.data);
 	*(.data.*);
 
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
@@ -111,7 +118,7 @@
 .heap : {
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(heap)
-	. += CONFIG_HEAP_SIZE;
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(eheap)
 }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Mon Sep  7 01:54:10 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:54:10 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit 961deb18c506a4952ce64ddbe17fd7fd48f41168
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0b8058f..9e5110f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..6793ca1
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 4bb7250..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Mon Sep  7 01:54:20 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:54:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit b25427ae023acf0e6a332347dffdabcec07099b3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9e5110f..b018f7c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -292,7 +292,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Mon Sep  7 01:54:30 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:54:30 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit eaf1bd0aa281c4972feb842eb9206678d907f8cf
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Mon Sep  7 01:54:38 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 7 Sep 2015 01:54:38 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit f55d0f69940b5dfde3496e8a56e2d4067aaad549
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/lib/Makefile.inc      |  9 ++++++---
 src/lib/program.ld        |  6 +++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b018f7c..885bb7f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -276,17 +276,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 43b1fea..794dcf8 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -87,7 +87,7 @@
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));


From gerrit at coreboot.org  Mon Sep  7 07:50:03 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 07:50:03 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: Allow
	adding file with specific alignemt requirement
References: <I526483296b494363f15dc169f163d93a6fc71bb0+0@gerrit.coreboot.org>
Message-ID: <I526483296b494363f15dc169f163d93a6fc71bb0+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11525

-gerrit

commit 6f54edb63128ccfe66f498a115149c0b04d7703a
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:05:44 2015 -0700

    cbfstool: Allow adding file with specific alignemt requirement
    
    Whenever we want to add a file to CBFS with a specific alignment, we
    have to do two cbfstool invocations: one to find a place for the file,
    and another to actually add the file to CBFS. Get rid of this nonsense
    and allow this to be done in one step.
    
    Change-Id: I526483296b494363f15dc169f163d93a6fc71bb0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/cbfstool/cbfstool.c | 98 ++++++++++++++++++++++++++++++------------------
 1 file changed, 61 insertions(+), 37 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index a91b600..d6c116a 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -328,8 +328,65 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer,
 	return 0;
 }
 
+static int do_cbfs_locate(int32_t *cbfs_addr)
+{
+	if (!param.filename) {
+		ERROR("You need to specify -f/--filename.\n");
+		return 1;
+	}
+
+	if (!param.name) {
+		ERROR("You need to specify -n/--name.\n");
+		return 1;
+	}
+
+	struct cbfs_image image;
+	if (cbfs_image_from_buffer(&image, param.image_region,
+							param.headeroffset))
+		return 1;
+
+	if (cbfs_get_entry(&image, param.name))
+		WARN("'%s' already in CBFS.\n", param.name);
+
+	struct buffer buffer;
+	if (buffer_from_file(&buffer, param.filename) != 0) {
+		ERROR("Cannot load %s.\n", param.filename);
+		return 1;
+	}
+
+	int32_t address = cbfs_locate_entry(&image, param.name, buffer.size,
+				    param.pagesize, param.alignment);
+	buffer_delete(&buffer);
+
+	if (address == -1) {
+		ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n",
+		      param.name, param.pagesize, param.alignment);
+		return 1;
+	}
+
+	if (param.top_aligned)
+		address = -convert_to_from_top_aligned(param.image_region,
+								address);
+
+	*cbfs_addr = address;
+	return 0;
+}
+
 static int cbfs_add(void)
 {
+	int32_t address;
+
+	if (param.alignment && param.baseaddress) {
+		ERROR("Cannot specify both alignment and base address\n");
+		return 1;
+	}
+
+	if (param.alignment) {
+		if (do_cbfs_locate(&address))
+			return 1;
+		param.baseaddress = address;
+	}
+
 	return cbfs_add_component(param.filename,
 				  param.name,
 				  param.type,
@@ -494,43 +551,10 @@ static int cbfs_create(void)
 
 static int cbfs_locate(void)
 {
-	if (!param.filename) {
-		ERROR("You need to specify -f/--filename.\n");
-		return 1;
-	}
-
-	if (!param.name) {
-		ERROR("You need to specify -n/--name.\n");
-		return 1;
-	}
-
-	struct cbfs_image image;
-	if (cbfs_image_from_buffer(&image, param.image_region,
-							param.headeroffset))
-		return 1;
-
-	if (cbfs_get_entry(&image, param.name))
-		WARN("'%s' already in CBFS.\n", param.name);
+	int32_t address;
 
-	struct buffer buffer;
-	if (buffer_from_file(&buffer, param.filename) != 0) {
-		ERROR("Cannot load %s.\n", param.filename);
+	if (do_cbfs_locate(&address) != 0)
 		return 1;
-	}
-
-	int32_t address = cbfs_locate_entry(&image, param.name, buffer.size,
-				    param.pagesize, param.alignment);
-	buffer_delete(&buffer);
-
-	if (address == -1) {
-		ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n",
-		      param.name, param.pagesize, param.alignment);
-		return 1;
-	}
-
-	if (param.top_aligned)
-		address = -convert_to_from_top_aligned(param.image_region,
-								address);
 
 	printf("0x%x\n", address);
 	return 0;
@@ -781,7 +805,7 @@ static bool cbfs_is_legacy_format(struct buffer *buffer)
 }
 
 static const struct command commands[] = {
-	{"add", "H:r:f:n:t:c:b:vh?", cbfs_add, true, true},
+	{"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true},
 	{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
 									true},
 	{"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true},
@@ -896,7 +920,7 @@ static void usage(char *name)
 	     "  -h               Display this help message\n\n"
 	     "COMMANDs:\n"
 	     " add [-r image,regions] -f FILE -n NAME -t TYPE \\\n"
-	     "        [-c compression] [-b base-address]                   "
+	     "        [-c compression] [-b base-address | -a alignment]    "
 			"Add a component\n"
 	     " add-payload [-r image,regions] -f FILE -n NAME \\\n"
 	     "        [-c compression] [-b base-address]                   "


From gerrit at coreboot.org  Mon Sep  7 07:50:05 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 07:50:05 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: microcode:
	Unify rules to add microcode to CBFS once again
References: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+0@gerrit.coreboot.org>
Message-ID: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526

-gerrit

commit a5c0e0339f4cc82308cd19a1f25ef8631e7d4196
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:35:55 2015 -0700

    microcode: Unify rules to add microcode to CBFS once again
    
    Now that cbfstool supports file alignment, we can use the conveniently
    available <filename>-align handler, and remove the need to have a
    separate rule in src/Makefile.inc just for adding the microcode.
    
    We can also get rid of the layering violation of having the
    CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
    Note that we still have a layering violation by the use of the
    CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
    for the time being.
    
    Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 Makefile.inc                                  |  1 -
 src/cpu/Makefile.inc                          | 20 +++++++-------------
 src/soc/intel/braswell/microcode/Makefile.inc | 11 -----------
 src/soc/intel/skylake/microcode/Makefile.inc  | 11 -----------
 4 files changed, 7 insertions(+), 36 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..be6021b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(
 	-B $(objcbfs)/bootblock.bin \
 	$(CBFSTOOL_PRE1_OPTS)
 	$(prebuild-files) true
-	$(call add-cpu-microcode-to-cbfs,$@.tmp)
 	mv $@.tmp $@
 else
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index cdd353f..cb49b27 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64))
 ## Rules for building the microcode blob in CBFS
 ################################################################################
 
-cpu_ucode_cbfs_name = cpu_microcode_blob.bin
-
 # External microcode file, or are we generating one ?
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
 cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
@@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y)
-cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)"
-else
-cpu_ucode_cbfs_offset = "-b"
-endif
-
 # In case we have more than one "source" (cough) files containing microcode, we
 # link them together in one large blob, so that we get all the microcode updates
 # in one file. This makes it easier for objcopy in the final step.
@@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
 	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
 
-ifeq ($(cbfs_include_ucode),y)
-# Add CPU microcode to specified rom image $(1)
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset)
+cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
+cpu_microcode_blob.bin-file = $(cpu_ucode_cbfs_file)
+cpu_microcode_blob.bin-type = 0x53
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
+cpu_microcode_blob.bin-position = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
 else
-add-cpu-microcode-to-cbfs = true
+cpu_microcode_blob.bin-align = 0x10000
 endif
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
index da25b8b..3497328 100644
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ b/src/soc/intel/braswell/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-y += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
index a5e8981..ba308f6 100644
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ b/src/soc/intel/skylake/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-


From gerrit at coreboot.org  Mon Sep  7 07:53:10 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 07:53:10 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: microcode: Unify
	rules to add microcode to CBFS once again
References: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+0@gerrit.coreboot.org>
Message-ID: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+2@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526

-gerrit

commit 5081046c0561712badd8cd54e0a0972a855aa300
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:35:55 2015 -0700

    microcode: Unify rules to add microcode to CBFS once again
    
    Now that cbfstool supports file alignment, we can use the conveniently
    available <filename>-align handler, and remove the need to have a
    separate rule in src/Makefile.inc just for adding the microcode.
    
    We can also get rid of the layering violation of having the
    CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
    Note that we still have a layering violation by the use of the
    CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
    for the time being.
    
    Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 Makefile.inc                                  |  1 -
 src/cpu/Makefile.inc                          | 20 +++++++-------------
 src/soc/intel/braswell/microcode/Makefile.inc | 11 -----------
 src/soc/intel/skylake/microcode/Makefile.inc  | 11 -----------
 4 files changed, 7 insertions(+), 36 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..be6021b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(
 	-B $(objcbfs)/bootblock.bin \
 	$(CBFSTOOL_PRE1_OPTS)
 	$(prebuild-files) true
-	$(call add-cpu-microcode-to-cbfs,$@.tmp)
 	mv $@.tmp $@
 else
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index cdd353f..9f28b36 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64))
 ## Rules for building the microcode blob in CBFS
 ################################################################################
 
-cpu_ucode_cbfs_name = cpu_microcode_blob.bin
-
 # External microcode file, or are we generating one ?
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
 cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
@@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y)
-cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)"
-else
-cpu_ucode_cbfs_offset = "-b"
-endif
-
 # In case we have more than one "source" (cough) files containing microcode, we
 # link them together in one large blob, so that we get all the microcode updates
 # in one file. This makes it easier for objcopy in the final step.
@@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
 	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
 
-ifeq ($(cbfs_include_ucode),y)
-# Add CPU microcode to specified rom image $(1)
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset)
+cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
+cpu_microcode_blob.bin-file = $(cpu_ucode_cbfs_file)
+cpu_microcode_blob.bin-type = 0x53
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
+cpu_microcode_blob.bin-position = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
 else
-add-cpu-microcode-to-cbfs = true
+cpu_microcode_blob.bin-align = 16
 endif
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
index da25b8b..3497328 100644
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ b/src/soc/intel/braswell/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-y += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
index a5e8981..ba308f6 100644
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ b/src/soc/intel/skylake/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-


From gerrit at coreboot.org  Mon Sep  7 08:23:29 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 08:23:29 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: Allow
	adding file with specific alignment requirement
References: <I526483296b494363f15dc169f163d93a6fc71bb0+0@gerrit.coreboot.org>
Message-ID: <I526483296b494363f15dc169f163d93a6fc71bb0+2@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11525

-gerrit

commit cbe83ac4aa20848d1d44cd2a233f29140246506d
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:05:44 2015 -0700

    cbfstool: Allow adding file with specific alignment requirement
    
    Whenever we want to add a file to CBFS with a specific alignment, we
    have to do two cbfstool invocations: one to find a place for the file,
    and another to actually add the file to CBFS. Get rid of this nonsense
    and allow this to be done in one step.
    
    Change-Id: I526483296b494363f15dc169f163d93a6fc71bb0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/cbfstool/cbfstool.c | 98 ++++++++++++++++++++++++++++++------------------
 1 file changed, 61 insertions(+), 37 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index a91b600..d6c116a 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -328,8 +328,65 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer,
 	return 0;
 }
 
+static int do_cbfs_locate(int32_t *cbfs_addr)
+{
+	if (!param.filename) {
+		ERROR("You need to specify -f/--filename.\n");
+		return 1;
+	}
+
+	if (!param.name) {
+		ERROR("You need to specify -n/--name.\n");
+		return 1;
+	}
+
+	struct cbfs_image image;
+	if (cbfs_image_from_buffer(&image, param.image_region,
+							param.headeroffset))
+		return 1;
+
+	if (cbfs_get_entry(&image, param.name))
+		WARN("'%s' already in CBFS.\n", param.name);
+
+	struct buffer buffer;
+	if (buffer_from_file(&buffer, param.filename) != 0) {
+		ERROR("Cannot load %s.\n", param.filename);
+		return 1;
+	}
+
+	int32_t address = cbfs_locate_entry(&image, param.name, buffer.size,
+				    param.pagesize, param.alignment);
+	buffer_delete(&buffer);
+
+	if (address == -1) {
+		ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n",
+		      param.name, param.pagesize, param.alignment);
+		return 1;
+	}
+
+	if (param.top_aligned)
+		address = -convert_to_from_top_aligned(param.image_region,
+								address);
+
+	*cbfs_addr = address;
+	return 0;
+}
+
 static int cbfs_add(void)
 {
+	int32_t address;
+
+	if (param.alignment && param.baseaddress) {
+		ERROR("Cannot specify both alignment and base address\n");
+		return 1;
+	}
+
+	if (param.alignment) {
+		if (do_cbfs_locate(&address))
+			return 1;
+		param.baseaddress = address;
+	}
+
 	return cbfs_add_component(param.filename,
 				  param.name,
 				  param.type,
@@ -494,43 +551,10 @@ static int cbfs_create(void)
 
 static int cbfs_locate(void)
 {
-	if (!param.filename) {
-		ERROR("You need to specify -f/--filename.\n");
-		return 1;
-	}
-
-	if (!param.name) {
-		ERROR("You need to specify -n/--name.\n");
-		return 1;
-	}
-
-	struct cbfs_image image;
-	if (cbfs_image_from_buffer(&image, param.image_region,
-							param.headeroffset))
-		return 1;
-
-	if (cbfs_get_entry(&image, param.name))
-		WARN("'%s' already in CBFS.\n", param.name);
+	int32_t address;
 
-	struct buffer buffer;
-	if (buffer_from_file(&buffer, param.filename) != 0) {
-		ERROR("Cannot load %s.\n", param.filename);
+	if (do_cbfs_locate(&address) != 0)
 		return 1;
-	}
-
-	int32_t address = cbfs_locate_entry(&image, param.name, buffer.size,
-				    param.pagesize, param.alignment);
-	buffer_delete(&buffer);
-
-	if (address == -1) {
-		ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n",
-		      param.name, param.pagesize, param.alignment);
-		return 1;
-	}
-
-	if (param.top_aligned)
-		address = -convert_to_from_top_aligned(param.image_region,
-								address);
 
 	printf("0x%x\n", address);
 	return 0;
@@ -781,7 +805,7 @@ static bool cbfs_is_legacy_format(struct buffer *buffer)
 }
 
 static const struct command commands[] = {
-	{"add", "H:r:f:n:t:c:b:vh?", cbfs_add, true, true},
+	{"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true},
 	{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
 									true},
 	{"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true},
@@ -896,7 +920,7 @@ static void usage(char *name)
 	     "  -h               Display this help message\n\n"
 	     "COMMANDs:\n"
 	     " add [-r image,regions] -f FILE -n NAME -t TYPE \\\n"
-	     "        [-c compression] [-b base-address]                   "
+	     "        [-c compression] [-b base-address | -a alignment]    "
 			"Add a component\n"
 	     " add-payload [-r image,regions] -f FILE -n NAME \\\n"
 	     "        [-c compression] [-b base-address]                   "


From gerrit at coreboot.org  Mon Sep  7 08:23:32 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 08:23:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: microcode: Unify
	rules to add microcode to CBFS once again
References: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+0@gerrit.coreboot.org>
Message-ID: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+3@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526

-gerrit

commit 61b725eccbffe006fd7cd4060f3add5ae0d427f1
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:35:55 2015 -0700

    microcode: Unify rules to add microcode to CBFS once again
    
    Now that cbfstool supports file alignment, we can use the conveniently
    available <filename>-align handler, and remove the need to have a
    separate rule in src/Makefile.inc just for adding the microcode.
    
    We can also get rid of the layering violation of having the
    CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
    Note that we still have a layering violation by the use of the
    CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
    for the time being.
    
    Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 Makefile.inc                                  |  1 -
 src/cpu/Makefile.inc                          | 20 +++++++-------------
 src/soc/intel/braswell/microcode/Makefile.inc | 11 -----------
 src/soc/intel/skylake/microcode/Makefile.inc  | 11 -----------
 4 files changed, 7 insertions(+), 36 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..be6021b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(
 	-B $(objcbfs)/bootblock.bin \
 	$(CBFSTOOL_PRE1_OPTS)
 	$(prebuild-files) true
-	$(call add-cpu-microcode-to-cbfs,$@.tmp)
 	mv $@.tmp $@
 else
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index cdd353f..9f28b36 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64))
 ## Rules for building the microcode blob in CBFS
 ################################################################################
 
-cpu_ucode_cbfs_name = cpu_microcode_blob.bin
-
 # External microcode file, or are we generating one ?
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
 cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
@@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y)
-cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)"
-else
-cpu_ucode_cbfs_offset = "-b"
-endif
-
 # In case we have more than one "source" (cough) files containing microcode, we
 # link them together in one large blob, so that we get all the microcode updates
 # in one file. This makes it easier for objcopy in the final step.
@@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
 	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
 
-ifeq ($(cbfs_include_ucode),y)
-# Add CPU microcode to specified rom image $(1)
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset)
+cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
+cpu_microcode_blob.bin-file = $(cpu_ucode_cbfs_file)
+cpu_microcode_blob.bin-type = 0x53
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
+cpu_microcode_blob.bin-position = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
 else
-add-cpu-microcode-to-cbfs = true
+cpu_microcode_blob.bin-align = 16
 endif
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
index da25b8b..3497328 100644
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ b/src/soc/intel/braswell/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-y += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
index a5e8981..ba308f6 100644
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ b/src/soc/intel/skylake/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-


From gerrit at coreboot.org  Mon Sep  7 08:44:09 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 7 Sep 2015 08:44:09 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	Allow adding file with specific alignment requirement
References: <I526483296b494363f15dc169f163d93a6fc71bb0+0@gerrit.coreboot.org>
Message-ID: <E1ZYs25-0002WN-DM@mail.coreboot.org>

the following patch was just integrated into master:
commit 38bc916def3a95f2a32309c5437ac0f868455a94
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:05:44 2015 -0700

    cbfstool: Allow adding file with specific alignment requirement
    
    Whenever we want to add a file to CBFS with a specific alignment, we
    have to do two cbfstool invocations: one to find a place for the file,
    and another to actually add the file to CBFS. Get rid of this nonsense
    and allow this to be done in one step.
    
    Change-Id: I526483296b494363f15dc169f163d93a6fc71bb0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11525
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11525 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep  7 09:05:06 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 09:05:06 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: microcode: Unify
	rules to add microcode to CBFS once again
References: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+0@gerrit.coreboot.org>
Message-ID: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+4@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526

-gerrit

commit d08a25c56b869148ec05b8408551cc487995505f
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:35:55 2015 -0700

    microcode: Unify rules to add microcode to CBFS once again
    
    Now that cbfstool supports file alignment, we can use the conveniently
    available <filename>-align handler, and remove the need to have a
    separate rule in src/Makefile.inc just for adding the microcode.
    
    We can also get rid of the layering violation of having the
    CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
    Note that we still have a layering violation by the use of the
    CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
    for the time being.
    
    Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 Makefile.inc                                  |  1 -
 src/cpu/Makefile.inc                          | 20 +++++++-------------
 src/soc/intel/braswell/microcode/Makefile.inc | 11 -----------
 src/soc/intel/skylake/microcode/Makefile.inc  | 11 -----------
 4 files changed, 7 insertions(+), 36 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..be6021b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(
 	-B $(objcbfs)/bootblock.bin \
 	$(CBFSTOOL_PRE1_OPTS)
 	$(prebuild-files) true
-	$(call add-cpu-microcode-to-cbfs,$@.tmp)
 	mv $@.tmp $@
 else
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index cdd353f..4ac4416 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64))
 ## Rules for building the microcode blob in CBFS
 ################################################################################
 
-cpu_ucode_cbfs_name = cpu_microcode_blob.bin
-
 # External microcode file, or are we generating one ?
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
 cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
@@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y)
-cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)"
-else
-cpu_ucode_cbfs_offset = "-b"
-endif
-
 # In case we have more than one "source" (cough) files containing microcode, we
 # link them together in one large blob, so that we get all the microcode updates
 # in one file. This makes it easier for objcopy in the final step.
@@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
 	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
 
-ifeq ($(cbfs_include_ucode),y)
-# Add CPU microcode to specified rom image $(1)
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset)
+cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
+cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
+cpu_microcode_blob.bin-type := 0x53
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
+cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
 else
-add-cpu-microcode-to-cbfs = true
+cpu_microcode_blob.bin-align := 16
 endif
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
index da25b8b..3497328 100644
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ b/src/soc/intel/braswell/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-y += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
index a5e8981..ba308f6 100644
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ b/src/soc/intel/skylake/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-


From gerrit at coreboot.org  Mon Sep  7 09:05:07 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 09:05:07 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: intel: Do not
	hardcode the position of mrc.cache
References: <I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd+0@gerrit.coreboot.org>
Message-ID: <I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11527

-gerrit

commit 0e7badc4289cd72d6f6947e73ba9dbf4e12e582d
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 01:54:23 2015 -0700

    intel: Do not hardcode the position of mrc.cache
    
    The reason for hardcoding the position of the MRC cache was to satisfy
    the alignment to the erase size of the flash chip. Hardcoding is no
    longer needed, as we can specify alignment directly. In the long term,
    the MRC cache will have to move to FMAP, but for now, we reduce
    fragmentation in CBFS.
    
    Note that soc/intel/common hardcoding of mrc.cache is not removed, as
    the mrc cache implementation there does not use CBFS to find the cache
    region, and needs a hardcoded address.
    
    Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/drivers/intel/fsp1_0/Kconfig               | 11 -----------
 src/drivers/intel/fsp1_0/Makefile.inc          |  2 +-
 src/mainboard/intel/bakersport_fsp/Kconfig     |  5 -----
 src/mainboard/intel/bayleybay_fsp/Kconfig      |  5 -----
 src/mainboard/intel/minnowmax/Kconfig          |  5 -----
 src/mainboard/siemens/mc_tcu3/Kconfig          |  5 -----
 src/northbridge/intel/haswell/Makefile.inc     |  2 +-
 src/northbridge/intel/nehalem/Makefile.inc     |  2 +-
 src/northbridge/intel/sandybridge/Makefile.inc |  6 +-----
 9 files changed, 4 insertions(+), 39 deletions(-)

diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig
index 020235a..8d3bf4c 100644
--- a/src/drivers/intel/fsp1_0/Kconfig
+++ b/src/drivers/intel/fsp1_0/Kconfig
@@ -82,17 +82,6 @@ config MRC_CACHE_SIZE
 	  should be a full sector of the flash ROM chip and nothing else should
 	  be included in CBFS in any sector that the fast boot cache data is in.
 
-config MRC_CACHE_LOC
-	hex "Fast Boot Data Cache location in CBFS"
-	default 0xfff50000
-	depends on ENABLE_MRC_CACHE
-	help
-	  The location in CBFS for the MRC data to be cached.
-
-	  WARNING: This should be on a sector boundary of the BIOS ROM chip
-	  and nothing else should be included in that sector, or IT WILL BE
-	  ERASED.
-
 config VIRTUAL_ROM_SIZE
 	hex "Virtual ROM Size"
 	default ROM_SIZE
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index ddc6bef..11ff31a 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -42,6 +42,6 @@ $(obj)/mrc.cache:
 
 cbfs-files-y += mrc.cache
 mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-position := $(CONFIG_MRC_CACHE_LOC)
+mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig
index c382bac..3575ab3 100644
--- a/src/mainboard/intel/bakersport_fsp/Kconfig
+++ b/src/mainboard/intel/bakersport_fsp/Kconfig
@@ -50,11 +50,6 @@ config FSP_FILE
 	string
 	default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
 
-config MRC_CACHE_LOC
-	hex
-	default 0xfff80000
-	depends on ENABLE_FSP_FAST_BOOT
-
 config CBFS_SIZE
 	hex
 	default 0x00200000
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
index a5c7605..9897cfc 100644
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -50,11 +50,6 @@ config FSP_FILE
 	string
 	default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
 
-config MRC_CACHE_LOC
-	hex
-	default 0xfff80000
-	depends on ENABLE_FSP_FAST_BOOT
-
 config CBFS_SIZE
 	hex
 	default 0x00200000
diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
index 636972f..39f84f1 100644
--- a/src/mainboard/intel/minnowmax/Kconfig
+++ b/src/mainboard/intel/minnowmax/Kconfig
@@ -49,11 +49,6 @@ config FSP_FILE
 	string
 	default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
 
-config MRC_CACHE_LOC
-	hex
-	default 0xfff80000
-	depends on ENABLE_FSP_FAST_BOOT
-
 config CBFS_SIZE
 	hex
 	default 0x00300000
diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig
index a4939bf..f46c528 100644
--- a/src/mainboard/siemens/mc_tcu3/Kconfig
+++ b/src/mainboard/siemens/mc_tcu3/Kconfig
@@ -49,11 +49,6 @@ config CACHE_ROM_SIZE_OVERRIDE
 	hex
 	default 0x1000000
 
-config MRC_CACHE_LOC
-	hex
-	default 0xfff80000
-	depends on ENABLE_FSP_FAST_BOOT
-
 config CBFS_SIZE
 	hex
 	default 0x00e00000
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index ad4b2ba..8d038da 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -50,7 +50,7 @@ $(obj)/mrc.cache: $(obj)/config.h
 
 cbfs-files-y += mrc.cache
 mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-position := 0xfffe0000
+mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
 
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index e5b4385..63c49f2 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -42,7 +42,7 @@ $(obj)/mrc.cache:
 
 cbfs-files-y += mrc.cache
 mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-position := 0xfffe0000
+mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 
 endif
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 407b61d..52fe23c 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -59,11 +59,7 @@ $(obj)/mrc.cache: $(obj)/config.h
 
 cbfs-files-y += mrc.cache
 mrc.cache-file := $(obj)/mrc.cache
-mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000
-mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000
-mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000
-mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) := 0xfffe0000
-mrc.cache-position := $(mrc-cache-position-y)
+mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
 


From gerrit at coreboot.org  Mon Sep  7 09:10:34 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 09:10:34 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: drivers/pc80: Do
	not initialize PS2 keyboard by default
References: <I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4+0@gerrit.coreboot.org>
Message-ID: <I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4+2@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8599

-gerrit

commit f0c3d7b2eebde37422083e8bd251726e3a926e8f
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Tue Mar 3 22:37:44 2015 -0600

    drivers/pc80: Do not initialize PS2 keyboard by default
    
    The most common payloads do not need this set, so optimize for the
    common case.
    
    Change-Id: I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 3rdparty/arm-trusted-firmware | 1 -
 3rdparty/blobs                | 1 -
 3rdparty/vboot                | 1 -
 src/drivers/pc80/Kconfig      | 2 +-
 4 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
deleted file mode 160000
index 649591b..0000000
--- a/3rdparty/arm-trusted-firmware
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 649591bbabbc737534943136751722307429b7d6
diff --git a/3rdparty/blobs b/3rdparty/blobs
deleted file mode 160000
index b4ade40..0000000
--- a/3rdparty/blobs
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7
diff --git a/3rdparty/vboot b/3rdparty/vboot
deleted file mode 160000
index fbf631c..0000000
--- a/3rdparty/vboot
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fbf631c845c08299f0bcbae3f311c5807d34c0d6
diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig
index 0ed1ecf..18c626c 100644
--- a/src/drivers/pc80/Kconfig
+++ b/src/drivers/pc80/Kconfig
@@ -4,7 +4,7 @@ if PC80_SYSTEM
 
 config DRIVERS_PS2_KEYBOARD
 	bool "PS/2 keyboard init"
-	default y
+	default n
 	help
 	  Enable this option to initialize PS/2 keyboards found connected
 	  to the PS/2 port.


From gerrit at coreboot.org  Mon Sep  7 09:28:26 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 09:28:26 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
References: <Iaa3e6533e8406b16ec0689abd704984d79293952+0@gerrit.coreboot.org>
Message-ID: <Iaa3e6533e8406b16ec0689abd704984d79293952+4@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8485

-gerrit

commit 782b1ab60f17e089da321b175a771f533f2664d5
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Feb 18 14:51:41 2015 -0600

    fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
    
    POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
    mess of it, by forcing a build-time error when CONFIG_POST_IO was not
    being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.
    
    Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
    "select POST_IO" from boards that have it.
    
    Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/drivers/intel/fsp1_0/cache_as_ram.inc  | 18 +++++-------------
 src/mainboard/intel/bakersport_fsp/Kconfig |  1 -
 src/mainboard/intel/bayleybay_fsp/Kconfig  |  1 -
 src/mainboard/intel/minnowmax/Kconfig      |  4 ----
 src/mainboard/intel/mohonpeak/Kconfig      |  1 -
 5 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc
index cdbda54..b025932 100644
--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -29,16 +29,6 @@
 # error "CONFIG_FSP_LOC must be set."
 #endif
 
-#ifndef CONFIG_POST_IO
-# error "CONFIG_POST_IO must be set."
-#endif
-
-#if CONFIG_POST_IO
-# ifndef CONFIG_POST_IO_PORT
-#  error "CONFIG_POST_IO_PORT must be set."
-# endif
-#endif
-
 #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC
 # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set."
 #endif
@@ -145,11 +135,13 @@ halt2:
 	movb  $0xBB, %ah
 
 .Lhlt:
+	/*
+	 * Here, we show a 16-bit POST code. %al is the return value from the
+	 * FSP blob, and %ah is an indicator of where we came from.
+	 */
 	xchg  %al, %ah
-#if CONFIG_POST_IO
+if IS_ENABLED(CONFIG_POST_IO)
 	outb  %al, $CONFIG_POST_IO_PORT
-#else
-	post_code(POST_DEAD_CODE)
 #endif
 	movl  $LHLT_DELAY, %ecx
 .Lhlt_Delay:
diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig
index c382bac..c42f7fc 100644
--- a/src/mainboard/intel/bakersport_fsp/Kconfig
+++ b/src/mainboard/intel/bakersport_fsp/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
-	select POST_IO
 	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select TSC_MONOTONIC_TIMER
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
index a5c7605..e4a5ace 100644
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
-	select POST_IO
 	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select TSC_MONOTONIC_TIMER
diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
index 636972f..c3265d7 100644
--- a/src/mainboard/intel/minnowmax/Kconfig
+++ b/src/mainboard/intel/minnowmax/Kconfig
@@ -68,10 +68,6 @@ config VIRTUAL_ROM_SIZE
 	depends on ENABLE_FSP_FAST_BOOT
 	default 0x800000
 
-config POST_IO
-	bool
-	default n
-
 config POST_DEVICE
 	bool
 	default n
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
index 996cea2..0085da4 100644
--- a/src/mainboard/intel/mohonpeak/Kconfig
+++ b/src/mainboard/intel/mohonpeak/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select MMCONF_SUPPORT
-	select POST_IO
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 
 config MAINBOARD_DIR


From gerrit at coreboot.org  Mon Sep  7 09:44:51 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 09:44:51 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: drivers/pc80: Do
	not initialize PS2 keyboard by default
References: <I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4+0@gerrit.coreboot.org>
Message-ID: <I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4+3@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8599

-gerrit

commit 4a1dd447e053f574c02278823f458723c56b5398
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Tue Mar 3 22:37:44 2015 -0600

    drivers/pc80: Do not initialize PS2 keyboard by default
    
    The most common payloads do not need this set, so optimize for the
    common case.
    
    Change-Id: I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/drivers/pc80/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig
index 0ed1ecf..18c626c 100644
--- a/src/drivers/pc80/Kconfig
+++ b/src/drivers/pc80/Kconfig
@@ -4,7 +4,7 @@ if PC80_SYSTEM
 
 config DRIVERS_PS2_KEYBOARD
 	bool "PS/2 keyboard init"
-	default y
+	default n
 	help
 	  Enable this option to initialize PS/2 keyboards found connected
 	  to the PS/2 port.


From gerrit at coreboot.org  Mon Sep  7 09:46:23 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 09:46:23 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
References: <Iaa3e6533e8406b16ec0689abd704984d79293952+0@gerrit.coreboot.org>
Message-ID: <Iaa3e6533e8406b16ec0689abd704984d79293952+5@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8485

-gerrit

commit f644a4dbbd823c8a48bde75b71f67429f93b9b5b
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Feb 18 14:51:41 2015 -0600

    fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
    
    POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
    mess of it, by forcing a build-time error when CONFIG_POST_IO was not
    being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.
    
    Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
    "select POST_IO" from boards that have it.
    
    Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/drivers/intel/fsp1_0/cache_as_ram.inc  | 18 +++++-------------
 src/mainboard/intel/bakersport_fsp/Kconfig |  1 -
 src/mainboard/intel/bayleybay_fsp/Kconfig  |  1 -
 src/mainboard/intel/minnowmax/Kconfig      |  4 ----
 src/mainboard/intel/mohonpeak/Kconfig      |  1 -
 5 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc
index cdbda54..32da60f8 100644
--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -29,16 +29,6 @@
 # error "CONFIG_FSP_LOC must be set."
 #endif
 
-#ifndef CONFIG_POST_IO
-# error "CONFIG_POST_IO must be set."
-#endif
-
-#if CONFIG_POST_IO
-# ifndef CONFIG_POST_IO_PORT
-#  error "CONFIG_POST_IO_PORT must be set."
-# endif
-#endif
-
 #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC
 # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set."
 #endif
@@ -145,11 +135,13 @@ halt2:
 	movb  $0xBB, %ah
 
 .Lhlt:
+	/*
+	 * Here, we show a 16-bit POST code. %al is the return value from the
+	 * FSP blob, and %ah is an indicator of where we came from.
+	 */
 	xchg  %al, %ah
-#if CONFIG_POST_IO
+#if IS_ENABLED(CONFIG_POST_IO)
 	outb  %al, $CONFIG_POST_IO_PORT
-#else
-	post_code(POST_DEAD_CODE)
 #endif
 	movl  $LHLT_DELAY, %ecx
 .Lhlt_Delay:
diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig
index c382bac..c42f7fc 100644
--- a/src/mainboard/intel/bakersport_fsp/Kconfig
+++ b/src/mainboard/intel/bakersport_fsp/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
-	select POST_IO
 	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select TSC_MONOTONIC_TIMER
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
index a5c7605..e4a5ace 100644
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
-	select POST_IO
 	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select TSC_MONOTONIC_TIMER
diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
index 636972f..c3265d7 100644
--- a/src/mainboard/intel/minnowmax/Kconfig
+++ b/src/mainboard/intel/minnowmax/Kconfig
@@ -68,10 +68,6 @@ config VIRTUAL_ROM_SIZE
 	depends on ENABLE_FSP_FAST_BOOT
 	default 0x800000
 
-config POST_IO
-	bool
-	default n
-
 config POST_DEVICE
 	bool
 	default n
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
index 996cea2..0085da4 100644
--- a/src/mainboard/intel/mohonpeak/Kconfig
+++ b/src/mainboard/intel/mohonpeak/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select MMCONF_SUPPORT
-	select POST_IO
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 
 config MAINBOARD_DIR


From gerrit at coreboot.org  Mon Sep  7 15:54:54 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 7 Sep 2015 15:54:54 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: Drop "See file
	CREDITS..." comment
References: <Iaa4686979ba1385b00ad1dbb6ea91e58f5014384+0@gerrit.coreboot.org>
Message-ID: <E1ZYykw-0004Bt-0c@mail.coreboot.org>

the following patch was just integrated into master:
commit 4460703f59c58626c762a8a1244842b7a3efe0db
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Sat Sep 5 07:51:32 2015 -0700

    Drop "See file CREDITS..." comment
    
    coreboot has no CREDITS file.
    
    Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Reviewed-on: http://review.coreboot.org/11514
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11514 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep  7 17:40:35 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 7 Sep 2015 17:40:35 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel: Do not
	hardcode the position of mrc.cache
References: <I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd+0@gerrit.coreboot.org>
Message-ID: <E1ZZ0PD-0001eE-FM@mail.coreboot.org>

the following patch was just integrated into master:
commit 2c482a969a546a70c2787d4d96d1ac212da11eff
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 01:54:23 2015 -0700

    intel: Do not hardcode the position of mrc.cache
    
    The reason for hardcoding the position of the MRC cache was to satisfy
    the alignment to the erase size of the flash chip. Hardcoding is no
    longer needed, as we can specify alignment directly. In the long term,
    the MRC cache will have to move to FMAP, but for now, we reduce
    fragmentation in CBFS.
    
    Note that soc/intel/common hardcoding of mrc.cache is not removed, as
    the mrc cache implementation there does not use CBFS to find the cache
    region, and needs a hardcoded address.
    
    Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11527
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11527 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep  7 18:41:52 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:41:52 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Update
	4GB DIMM SPD for 1866
References: <Ibb84f77565d46894afe2153f5951e17a450413fc+0@gerrit.coreboot.org>
Message-ID: <Ibb84f77565d46894afe2153f5951e17a450413fc+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11528

-gerrit

commit 4274c420ffb41059cea66364645c63b9df6845ce
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 21 13:09:10 2015 -0700

    glados: Update 4GB DIMM SPD for 1866
    
    Enable 1866 timings in the 4GB Hynix SPD.
    
    BUG=chrome-os-partner:44394
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423
    Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295174
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex
index c296c88..c23ecbd 100644
--- a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex
+++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex
@@ -1,6 +1,6 @@
-91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01
+91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 50 05
 78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
-00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


From gerrit at coreboot.org  Mon Sep  7 18:41:54 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:41:54 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Fix and clean up PCIE _PRT entries
References: <I76ff07d2bf7001aed504558d55cca9e19c692d7e+0@gerrit.coreboot.org>
Message-ID: <I76ff07d2bf7001aed504558d55cca9e19c692d7e+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11529

-gerrit

commit f441c0308c5347ac7bf53d018fcdc9ac31627485
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 15:49:12 2015 -0700

    skylake: ACPI: Fix and clean up PCIE _PRT entries
    
    Fix the code for PCIE _PRT entries to use an actual root
    port number from the device instead of NVS that was never
    initialized from zero.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=build and boot on glados with pci=nomsi to ensure interrupts work
    
    Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
    Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295902
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/globalnvs.asl |  14 +-
 src/soc/intel/skylake/acpi/pcie.asl      | 225 +++++++++++++++++++++----------
 src/soc/intel/skylake/include/soc/nvs.h  |   5 +-
 3 files changed, 156 insertions(+), 88 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index b3d1bd2..b41fa42 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -63,19 +63,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	CBMC,	32,	// 0x1c - 0x1f - Coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
 	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
-	RPA1,	32,	// 0x30 - 0x33 - Root port address 1
-	RPA2,	32,	// 0x34 - 0x37 - Root port address 2
-	RPA3,	32,	// 0x38 - 0x3b - Root port address 3
-	RPA4,	32,	// 0x3c - 0x3f - Root port address 4
-	RPA5,	32,	// 0x40 - 0x43 - Root port address 5
-	RPA6,	32,	// 0x44 - 0x47 - Root port address 6
-	RPA7,	32,	// 0x48 - 0x4b - Root port address 7
-	RPA8,	32,	// 0x4c - 0x4f - Root port address 8
-	RPA9,	32,	// 0x50 - 0x53 - Root port address 9
-	RPAA,	32,	// 0x54 - 0x57 - Root port address 10
-	RPAB,	32,	// 0x58 - 0x5b - Root port address 11
-	RPAC,	32,	// 0x5c - 0x5f - Root port address 12
-	DPTE,	8,	// 0x60 - Enable DPTF
+	DPTE,	8,	// 0x30 - Enable DPTF
 
 	/* ChromeOS specific */
 	Offset (0x100),
diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl
index 7ab78e0..52b07da 100644
--- a/src/soc/intel/skylake/acpi/pcie.asl
+++ b/src/soc/intel/skylake/acpi/pcie.asl
@@ -24,56 +24,56 @@
 Method (IRQM, 1, Serialized) {
 
 	/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
-	Name (IQAA, Package() {
-		Package() { 0x0000ffff, 0, 0, 16 },
-		Package() { 0x0000ffff, 1, 0, 17 },
-		Package() { 0x0000ffff, 2, 0, 18 },
-		Package() { 0x0000ffff, 3, 0, 19 } })
-	Name (IQAP, Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } })
+	Name (IQAA, Package () {
+		Package () { 0x0000ffff, 0, 0, 16 },
+		Package () { 0x0000ffff, 1, 0, 17 },
+		Package () { 0x0000ffff, 2, 0, 18 },
+		Package () { 0x0000ffff, 3, 0, 19 } })
+	Name (IQAP, Package () {
+		Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 },
+		Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 },
+		Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 },
+		Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } })
 
 	/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
-	Name (IQBA, Package() {
-		Package() { 0x0000ffff, 0, 0, 17 },
-		Package() { 0x0000ffff, 1, 0, 18 },
-		Package() { 0x0000ffff, 2, 0, 19 },
-		Package() { 0x0000ffff, 3, 0, 16 } })
-	Name (IQBP, Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 },
-		Package() { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } })
+	Name (IQBA, Package () {
+		Package () { 0x0000ffff, 0, 0, 17 },
+		Package () { 0x0000ffff, 1, 0, 18 },
+		Package () { 0x0000ffff, 2, 0, 19 },
+		Package () { 0x0000ffff, 3, 0, 16 } })
+	Name (IQBP, Package () {
+		Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 },
+		Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 },
+		Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 },
+		Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } })
 
 	/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
-	Name (IQCA, Package() {
-		Package() { 0x0000ffff, 0, 0, 18 },
-		Package() { 0x0000ffff, 1, 0, 19 },
-		Package() { 0x0000ffff, 2, 0, 16 },
-		Package() { 0x0000ffff, 3, 0, 17 } })
-	Name (IQCP, Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 },
-		Package() { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } })
+	Name (IQCA, Package () {
+		Package () { 0x0000ffff, 0, 0, 18 },
+		Package () { 0x0000ffff, 1, 0, 19 },
+		Package () { 0x0000ffff, 2, 0, 16 },
+		Package () { 0x0000ffff, 3, 0, 17 } })
+	Name (IQCP, Package () {
+		Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 },
+		Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 },
+		Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 },
+		Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } })
 
 	/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
-	Name (IQDA, Package() {
-		Package() { 0x0000ffff, 0, 0, 19 },
-		Package() { 0x0000ffff, 1, 0, 16 },
-		Package() { 0x0000ffff, 2, 0, 17 },
-		Package() { 0x0000ffff, 3, 0, 18 } })
-	Name (IQDP, Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 },
-		Package() { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })
-
-	Switch (ToInteger (Arg0)) {
-		/* PCIe Root Port 1 and 5 */
-		Case (Package() { 1, 5 }) {
+	Name (IQDA, Package () {
+		Package () { 0x0000ffff, 0, 0, 19 },
+		Package () { 0x0000ffff, 1, 0, 16 },
+		Package () { 0x0000ffff, 2, 0, 17 },
+		Package () { 0x0000ffff, 3, 0, 18 } })
+	Name (IQDP, Package () {
+		Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 },
+		Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 },
+		Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },
+		Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })
+
+	Switch (ToInteger (Arg0))
+	{
+		Case (Package () { 1, 5, 9 }) {
 			If (PICM) {
 				Return (IQAA)
 			} Else {
@@ -81,8 +81,7 @@ Method (IRQM, 1, Serialized) {
 			}
 		}
 
-		/* PCIe Root Port 2 and 6 */
-		Case (Package() { 2, 6 }) {
+		Case (Package () { 2, 6, 10 }) {
 			If (PICM) {
 				Return (IQBA)
 			} Else {
@@ -90,8 +89,7 @@ Method (IRQM, 1, Serialized) {
 			}
 		}
 
-		/* PCIe Root Port 3 and 7 */
-		Case (Package() { 3, 7 }) {
+		Case (Package () { 3, 7, 11 }) {
 			If (PICM) {
 				Return (IQCA)
 			} Else {
@@ -99,8 +97,7 @@ Method (IRQM, 1, Serialized) {
 			}
 		}
 
-		/* PCIe Root Port 4 and 8 */
-		Case (Package() { 4, 8 }) {
+		Case (Package () { 4, 8, 12 }) {
 			If (PICM) {
 				Return (IQDA)
 			} Else {
@@ -120,90 +117,154 @@ Method (IRQM, 1, Serialized) {
 
 Device (RP01)
 {
-	Name (_ADR, 0x001c0000)
+	Name (_ADR, 0x001C0000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
 	Method (_PRT)
 	{
-		Return (IRQM (RPA1))
+		Return (IRQM (RPPN))
 	}
 }
 
 Device (RP02)
 {
-	Name (_ADR, 0x001c0001)
+	Name (_ADR, 0x001C0001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
 	Method (_PRT)
 	{
-		Return (IRQM (RPA2))
+		Return (IRQM (RPPN))
 	}
 }
 
 Device (RP03)
 {
-	Name (_ADR, 0x001c0002)
+	Name (_ADR, 0x001C0002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
 	Method (_PRT)
 	{
-		Return (IRQM (RPA3))
+		Return (IRQM (RPPN))
 	}
 }
 
 Device (RP04)
 {
-	Name (_ADR, 0x001c0003)
+	Name (_ADR, 0x001C0003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
 	Method (_PRT)
 	{
-		Return (IRQM (RPA4))
+		Return (IRQM (RPPN))
 	}
 }
 
 Device (RP05)
 {
-	Name (_ADR, 0x001c0004)
+	Name (_ADR, 0x001C0004)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
 	Method (_PRT)
 	{
-		Return (IRQM (RPA5))
+		Return (IRQM (RPPN))
 	}
 }
 
 Device (RP06)
 {
-	Name (_ADR, 0x001c0005)
+	Name (_ADR, 0x001C0005)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
 	Method (_PRT)
 	{
-		Return (IRQM (RPA6))
+		Return (IRQM (RPPN))
 	}
 }
 
 Device (RP07)
 {
-	Name (_ADR, 0x001c0006)
+	Name (_ADR, 0x001C0006)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
 	Method (_PRT)
 	{
-		Return (IRQM (RPA7))
+		Return (IRQM (RPPN))
 	}
 }
 
 Device (RP08)
 {
-	Name (_ADR, 0x001c0007)
+	Name (_ADR, 0x001C0007)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
 	Method (_PRT)
 	{
-		Return (IRQM (RPA8))
+		Return (IRQM (RPPN))
 	}
 }
+
 Device (RP09)
 {
         Name (_ADR, 0x001D0000)
 
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
         Method (_PRT)
         {
-		Return (IRQM (RPA9))
+		Return (IRQM (RPPN))
         }
 }
 
@@ -211,9 +272,16 @@ Device (RP10)
 {
         Name (_ADR, 0x001D0001)
 
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
         Method (_PRT)
         {
-		Return (IRQM (RPAA))
+		Return (IRQM (RPPN))
         }
 }
 
@@ -221,19 +289,32 @@ Device (RP11)
 {
         Name (_ADR, 0x001D0002)
 
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
         Method (_PRT)
         {
-		Return (IRQM (RPAB))
+		Return (IRQM (RPPN))
         }
 }
 
 Device (RP12)
 {
-        Name (_ADR, 0x001D0003)
+	Name (_ADR, 0x001D0003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
 
         Method (_PRT)
         {
-		Return (IRQM (RPAC))
+		Return (IRQM (RPPN))
         }
 }
-
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 7fef190..2d8129b 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -55,10 +55,9 @@ typedef struct {
 	u32	cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
-	u32	rpa[12]; /* 0x30 - 0x5f - Root Port Address */
-	u8	dpte; /* 0x60 - Enable DPTF */
+	u8	dpte; /* 0x30 - Enable DPTF */
 
-	u8	unused[159];
+	u8	unused[207];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;


From gerrit at coreboot.org  Mon Sep  7 18:41:56 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:41:56 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Clean up pch.asl
References: <I51b1c5286fc344df6942a24c1dea71abf10ab561+0@gerrit.coreboot.org>
Message-ID: <I51b1c5286fc344df6942a24c1dea71abf10ab561+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11530

-gerrit

commit 8bd80cd399905cef6863e5925564b5d3598bd872
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:01:08 2015 -0700

    skylake: ACPI: Clean up pch.asl
    
    Clean up the code in pch.asl:
    - move all the C header includes into here instead of duplicated
    in various ASL files included from here
    - move the trap field definition into platform.asl with the method
    - alphebetize the includes
    - move gpio.asl include into pch.asl
    - remove duplicate irqlinks.asl include from lpc.asl
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I51b1c5286fc344df6942a24c1dea71abf10ab561
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3ee9c4afa031191d275f0d3d40b2b15b85369b2f
    Original-Change-Id: I3bae434ad227273885d8436db23e17e593739f77
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295903
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/gpio.asl     |  4 ----
 src/soc/intel/skylake/acpi/lpc.asl      |  3 ---
 src/soc/intel/skylake/acpi/pch.asl      | 40 +++++++++++++++------------------
 src/soc/intel/skylake/acpi/platform.asl | 10 +++++++++
 src/soc/intel/skylake/acpi/serialio.asl |  1 -
 5 files changed, 28 insertions(+), 30 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
index 3b4740b..7c2efa6 100644
--- a/src/soc/intel/skylake/acpi/gpio.asl
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -18,10 +18,6 @@
  * Foundation, Inc.
  */
 
-#include <soc/irq.h>
-#include <soc/iomap.h>
-#include <soc/pcr.h>
-#include <soc/gpio_defs.h>
 
 /* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */
 Method (PCRR, 2, Serialized)
diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl
index 8332980..877be99 100644
--- a/src/soc/intel/skylake/acpi/lpc.asl
+++ b/src/soc/intel/skylake/acpi/lpc.asl
@@ -19,7 +19,6 @@
  * Foundation, Inc.
  */
 
-#include <soc/iomap.h>
 
 // Intel LPC Bus Device  - 0:1f.0
 
@@ -169,8 +168,6 @@ Device (LPCB)
 		})
 	}
 
-	#include "gpio.asl"
-	#include "irqlinks.asl"
 	#include <acpi/ec.asl>
 	#include <acpi/superio.asl>
 }
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 2621eb2..18a41f2 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -20,38 +20,34 @@
  */
 
 #include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/gpio_defs.h>
+#include <soc/gpe.h>
+#include <soc/pcr.h>
 
-Scope (\)
-{
-	/* IO-Trap at 0x800.
-	 * This is the ACPI->SMI communication interface.
-	 */
-	OperationRegion (IO_T, SystemIO, 0x800, 0x10)
-	Field (IO_T, ByteAcc, NoLock, Preserve)
-	{
-		Offset (0x8),
-		TRP0, 8		/* IO-Trap at 0x808 */
-	}
-}
+/* GPIO Controller */
+#include "gpio.asl"
+
+/* Interrupt Routing */
+#include "irqlinks.asl"
 
-/* PCI Express Ports 0:1c.x */
+/* LPC 0:1f.0 */
+#include "lpc.asl"
+
+/* PCIE Ports */
 #include "pcie.asl"
 
-/* USB XHCI 0:14.0 */
-#include "xhci.asl"
 
-/* LPC Bridge 0:1f.0 */
-#include "lpc.asl"
+/* Serial IO */
+#include "serialio.asl"
 
 /* SMBus 0:1f.3 */
 #include "smbus.asl"
 
-/* Serial IO */
-#include "serialio.asl"
 
-/* Interrupt Routing */
 #include "itss.asl"
-#include "irqlinks.asl"
+/* USB XHCI 0:14.0 */
+#include "xhci.asl"
 
 Method (_OSC, 4)
 {
diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl
index 2bbe97b..f0ed4e0 100644
--- a/src/soc/intel/skylake/acpi/platform.asl
+++ b/src/soc/intel/skylake/acpi/platform.asl
@@ -36,6 +36,16 @@ Field (POST, ByteAcc, Lock, Preserve)
 	DBG0, 8
 }
 
+/* IO-Trap at 0x800.
+ * This is the ACPI->SMI communication interface.
+ */
+OperationRegion (IO_T, SystemIO, 0x800, 0x10)
+Field (IO_T, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x8),
+	TRP0, 8		/* IO-Trap at 0x808 */
+}
+
 /* SMI I/O Trap */
 Method (TRAP, 1, Serialized)
 {
diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl
index c6f5446..e57b937 100644
--- a/src/soc/intel/skylake/acpi/serialio.asl
+++ b/src/soc/intel/skylake/acpi/serialio.asl
@@ -17,7 +17,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc.
  */
-#include <soc/irq.h>
 
 // Intel Serial IO Devices in ACPI Mode
 


From gerrit at coreboot.org  Mon Sep  7 18:41:57 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:41:57 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Add functions for PCR access
References: <Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d+0@gerrit.coreboot.org>
Message-ID: <Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11531

-gerrit

commit b4a6e17f80dd95bd6f0d4666815d336b026cd401
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:03:45 2015 -0700

    skylake: ACPI: Add functions for PCR access
    
    There are a few places in ACPI that touch PCR registers,
    either to read a value or to set some magic bits.
    
    Expose some functions for this that will keep all the PCR
    access in one location instead of spread throughout the code.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e78b2801fbc5c00ba452ae5e4ecb07c3e23bf6c1
    Original-Change-Id: I2e4d491157f7ac6d2ebc231b11661c059b4a7fa0
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295904
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/pch.asl |  2 +
 src/soc/intel/skylake/acpi/pcr.asl | 75 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 77 insertions(+)

diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 18a41f2..581efa0 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -37,6 +37,8 @@
 /* PCIE Ports */
 #include "pcie.asl"
 
+/* PCR Access */
+#include "pcr.asl"
 
 /* Serial IO */
 #include "serialio.asl"
diff --git a/src/soc/intel/skylake/acpi/pcr.asl b/src/soc/intel/skylake/acpi/pcr.asl
new file mode 100644
index 0000000..a6fb46e
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/pcr.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/*
+ * Calculate PCR register base at specified PID
+ * Arg0 - PCR Port ID
+ */
+Method (PCRB, 1, NotSerialized)
+{
+	Return (Add (PCH_PCR_BASE_ADDRESS, ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
+}
+
+/*
+ * Read a PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ */
+Method (PCRR, 2, NotSerialized)
+{
+	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+	Field (PCRD, DWordAcc, NoLock, Preserve)
+	{
+		DATA, 32
+	}
+	Return (DATA)
+}
+
+/*
+ * AND a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to AND
+ */
+Method (PCRA, 3, Serialized)
+{
+	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+	Field (PCRD, DWordAcc, NoLock, Preserve)
+	{
+		DATA, 32
+	}
+	And (DATA, Arg2, DATA)
+}
+
+/*
+ * OR a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to OR
+ */
+Method (PCRO, 3, Serialized)
+{
+	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+	Field (PCRD, DWordAcc, NoLock, Preserve)
+	{
+		DATA, 32
+	}
+	Or (DATA, Arg2, DATA)
+}


From gerrit at coreboot.org  Mon Sep  7 18:41:59 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:41:59 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: PCR:
	Add Port ID for SCS
References: <I0f0144ef79d3691fa120dafc9a31d2a681bf2a28+0@gerrit.coreboot.org>
Message-ID: <I0f0144ef79d3691fa120dafc9a31d2a681bf2a28+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11532

-gerrit

commit 36afa64e8c8573178c3c91d09a6250bf2c3184ef
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:35:06 2015 -0700

    skylake: PCR: Add Port ID for SCS
    
    Add the PCR Port ID for the storage controllers and
    reformat to put the PCR PIDs in increasing order.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9
    Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295905
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/include/soc/pcr.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h
index c8a4425..bf3161b 100644
--- a/src/soc/intel/skylake/include/soc/pcr.h
+++ b/src/soc/intel/skylake/include/soc/pcr.h
@@ -78,9 +78,10 @@
 #define PID_GPIOCOM2	0xAD
 #define PID_GPIOCOM1	0xAE
 #define PID_GPIOCOM0	0xAF
-#define PID_LPC		0xC7
-#define PID_ITSS	0xC4
+#define PID_SCS		0xC0
 #define PID_RTC		0xC3
+#define PID_ITSS	0xC4
+#define PID_LPC		0xC7
 #define PID_SERIALIO	0xCB
 #define PID_DMI		0xEF
 


From gerrit at coreboot.org  Mon Sep  7 18:42:02 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:02 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: iomap:
	Remove unused RCBA region
References: <If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48+0@gerrit.coreboot.org>
Message-ID: <If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11533

-gerrit

commit f5567159bdf275eba08a3b349ccca7a08a6bb3a1
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:39:31 2015 -0700

    skylake: iomap: Remove unused RCBA region
    
    Remove the now unused RCBA base and size from iomap.h
    and fix a trivial typo that doesn't seem to get used
    anywhere.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emege-glados coreboot
    
    Change-Id: If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: ee7b1a8a75a9e9dc191c16ddc32b6a38acec398c
    Original-Change-Id: I0c49803d47105c3c55121caedaffaa249c4f0189
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295906
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/include/soc/iomap.h | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index 916719d..333906b 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -28,7 +28,7 @@
 #define MCFG_BASE_SIZE		0x4000000
 
 #define PCH_PCR_BASE_ADDRESS	0xfd000000
-#define PCH_BCR_BASE_SIZE	0x1000000
+#define PCH_PCR_BASE_SIZE	0x1000000
 
 #define UART_DEBUG_BASE_ADDRESS	0xfe034000
 #define UART_DEBUG_BASE_SIZE	0x1000
@@ -48,10 +48,6 @@
 #define GDXC_BASE_ADDRESS	0xfed84000
 #define GDXC_BASE_SIZE		0x1000
 
-/* TODO: need to remove RCBA code after ASL clean up */
-#define RCBA_BASE_ADDRESS	0xfed1c000
-#define RCBA_BASE_SIZE		0x4000
-
 #define HPET_BASE_ADDRESS	0xfed00000
 
 #define PCH_PWRM_BASE_ADDRESS	0xfe000000


From gerrit at coreboot.org  Mon Sep  7 18:42:05 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:05 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Remove itss.asl and cleanup irqlinks.asl
References: <I1af7d730542fd0e79b9f3db9f0796e7c701c59e6+0@gerrit.coreboot.org>
Message-ID: <I1af7d730542fd0e79b9f3db9f0796e7c701c59e6+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11534

-gerrit

commit ded08000f5e8aa68491ef019193c7f43d726d51b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:48:11 2015 -0700

    skylake: ACPI: Remove itss.asl and cleanup irqlinks.asl
    
    Move the itss.asl code that was exporting PIRQ routing
    control registers into irqlinks.asl and use the PCR access
    methods to find the appropriate address.  At the same time
    clean up the code in irqlinks.asl to follow formatting rules.
    
    Also now that the GPIO code in itss.asl is unused the file
    can be removed.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I1af7d730542fd0e79b9f3db9f0796e7c701c59e6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 39a96063d01d00ab768db1c723f78b5af9ed6513
    Original-Change-Id: Iafa03c276cb276ec8c00c24ed2dba48d0dc9612b
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295907
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/irqlinks.asl | 337 +++++++++++++-------------------
 src/soc/intel/skylake/acpi/itss.asl     |  96 ---------
 src/soc/intel/skylake/acpi/pch.asl      |   1 -
 3 files changed, 137 insertions(+), 297 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl
index 1f6e623..b7a78f0 100644
--- a/src/soc/intel/skylake/acpi/irqlinks.asl
+++ b/src/soc/intel/skylake/acpi/irqlinks.asl
@@ -19,475 +19,412 @@
  * Foundation, Inc.
  */
 
+/* PIRQ routing control is in PCR ITSS region */
+OperationRegion (ITSS, SystemMemory,
+		 Add (PCRB (PID_ITSS), R_PCH_PCR_ITSS_PIRQA_ROUT), 8)
+Field (ITSS, ByteAcc, NoLock, Preserve)
+{
+	PIRA, 8,	/* PIRQA Routing Control */
+	PIRB, 8,	/* PIRQB Routing Control */
+	PIRC, 8,	/* PIRQC Routing Control */
+	PIRD, 8,	/* PIRQD Routing Control */
+	PIRE, 8,	/* PIRQE Routing Control */
+	PIRF, 8,	/* PIRQF Routing Control */
+	PIRG, 8,	/* PIRQG Routing Control */
+	PIRH, 8,	/* PIRQH Routing Control */
+}
+
+Name (IREN, 0x80)	/* Interrupt Routing Enable */
+Name (IREM, 0x0f)	/* Interrupt Routing Mask */
+
 Device (LNKA)
 {
-	Name (_HID, EISAID("PNP0C0F"))
+	Name (_HID, EISAID ("PNP0C0F"))
 	Name (_UID, 1)
 
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Or (\_SB.PARC, 0x80, \_SB.PARC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
+	Name (_PRS, ResourceTemplate ()
 	{
 		IRQ (Level, ActiveLow, Shared)
 			{ 3, 4, 5, 6, 10, 12, 14, 15 }
 	})
 
-	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
-		Name (RTLA, ResourceTemplate()
+		Name (RTLA, ResourceTemplate ()
 		{
 			IRQ (Level, ActiveLow, Shared) {}
 		})
 		CreateWordField (RTLA, 1, IRQ0)
-
-		// Clear the WordField
 		Store (Zero, IRQ0)
 
-		// Set the bit from PRTA
-		ShiftLeft (1, And (\_SB.PARC, 0x0f), IRQ0)
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0)
 
 		Return (RTLA)
 	}
 
-	// Set Resource Setting for this IRQ link
 	Method (_SRS, 1, Serialized)
 	{
 		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
 		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, \_SB.PARC)
+		Decrement (Local0)
+		Store (Local0, ^^PIRA)
 	}
 
-	// Status
 	Method (_STA, 0, Serialized)
 	{
-		If(And (\_SB.PARC, 0x80)) {
+		If (And (^^PIRA, ^^IREN)) {
 			Return (0x9)
 		} Else {
 			Return (0xb)
 		}
 	}
+
+	Method (_DIS, 0, Serialized)
+	{
+		Or (^^PIRA, ^^IREN, ^^PIRA)
+	}
 }
 
 Device (LNKB)
 {
-	Name (_HID, EISAID("PNP0C0F"))
+	Name (_HID, EISAID ("PNP0C0F"))
 	Name (_UID, 2)
 
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Or (\_SB.PBRC, 0x80, \_SB.PBRC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
+	Name (_PRS, ResourceTemplate ()
 	{
 		IRQ (Level, ActiveLow, Shared)
 			{ 3, 4, 5, 6, 10, 12, 14, 15 }
 	})
 
-	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
-		Name (RTLB, ResourceTemplate()
+		Name (RTLA, ResourceTemplate ()
 		{
 			IRQ (Level, ActiveLow, Shared) {}
 		})
-		CreateWordField (RTLB, 1, IRQ0)
-
-		// Clear the WordField
+		CreateWordField (RTLA, 1, IRQ0)
 		Store (Zero, IRQ0)
 
-		// Set the bit from PRTB
-		ShiftLeft (1, And (\_SB.PBRC, 0x0f), IRQ0)
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0)
 
-		Return (RTLB)
+		Return (RTLA)
 	}
 
-	// Set Resource Setting for this IRQ link
 	Method (_SRS, 1, Serialized)
 	{
 		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
 		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, \_SB.PBRC)
+		Decrement (Local0)
+		Store (Local0, ^^PIRB)
 	}
 
-	// Status
 	Method (_STA, 0, Serialized)
 	{
-		If(And (\_SB.PBRC, 0x80)) {
+		If (And (^^PIRB, ^^IREN)) {
 			Return (0x9)
 		} Else {
 			Return (0xb)
 		}
 	}
+
+	Method (_DIS, 0, Serialized)
+	{
+		Or (^^PIRB, ^^IREN, ^^PIRB)
+	}
 }
 
 Device (LNKC)
 {
-	Name (_HID, EISAID("PNP0C0F"))
+	Name (_HID, EISAID ("PNP0C0F"))
 	Name (_UID, 3)
 
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Or (\_SB.PCRC, 0x80, \_SB.PCRC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
+	Name (_PRS, ResourceTemplate ()
 	{
 		IRQ (Level, ActiveLow, Shared)
 			{ 3, 4, 5, 6, 10, 12, 14, 15 }
 	})
 
-	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
-		Name (RTLC, ResourceTemplate()
+		Name (RTLA, ResourceTemplate ()
 		{
 			IRQ (Level, ActiveLow, Shared) {}
 		})
-		CreateWordField (RTLC, 1, IRQ0)
-
-		// Clear the WordField
+		CreateWordField (RTLA, 1, IRQ0)
 		Store (Zero, IRQ0)
 
-		// Set the bit from PRTC
-		ShiftLeft (1, And (\_SB.PCRC, 0x0f), IRQ0)
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0)
 
-		Return (RTLC)
+		Return (RTLA)
 	}
 
-	// Set Resource Setting for this IRQ link
 	Method (_SRS, 1, Serialized)
 	{
 		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
 		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, \_SB.PCRC)
+		Decrement (Local0)
+		Store (Local0, ^^PIRC)
 	}
 
-	// Status
 	Method (_STA, 0, Serialized)
 	{
-		If(And (\_SB.PCRC, 0x80)) {
+		If (And (^^PIRC, ^^IREN)) {
 			Return (0x9)
 		} Else {
 			Return (0xb)
 		}
 	}
+
+	Method (_DIS, 0, Serialized)
+	{
+		Or (^^PIRC, ^^IREN, ^^PIRC)
+	}
 }
 
 Device (LNKD)
 {
-	Name (_HID, EISAID("PNP0C0F"))
+	Name (_HID, EISAID ("PNP0C0F"))
 	Name (_UID, 4)
 
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Or (\_SB.PDRC, 0x80, \_SB.PDRC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
+	Name (_PRS, ResourceTemplate ()
 	{
 		IRQ (Level, ActiveLow, Shared)
 			{ 3, 4, 5, 6, 10, 12, 14, 15 }
 	})
 
-	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
-		Name (RTLD, ResourceTemplate()
+		Name (RTLA, ResourceTemplate ()
 		{
 			IRQ (Level, ActiveLow, Shared) {}
 		})
-		CreateWordField (RTLD, 1, IRQ0)
-
-		// Clear the WordField
+		CreateWordField (RTLA, 1, IRQ0)
 		Store (Zero, IRQ0)
 
-		// Set the bit from PRTD
-		ShiftLeft (1, And (\_SB.PDRC, 0x0f), IRQ0)
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0)
 
-		Return (RTLD)
+		Return (RTLA)
 	}
 
-	// Set Resource Setting for this IRQ link
 	Method (_SRS, 1, Serialized)
 	{
 		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
 		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, \_SB.PDRC)
+		Decrement (Local0)
+		Store (Local0, ^^PIRD)
 	}
 
-	// Status
 	Method (_STA, 0, Serialized)
 	{
-		If(And (\_SB.PDRC, 0x80)) {
+		If (And (^^PIRD, ^^IREN)) {
 			Return (0x9)
 		} Else {
 			Return (0xb)
 		}
 	}
+
+	Method (_DIS, 0, Serialized)
+	{
+		Or (^^PIRD, ^^IREN, ^^PIRD)
+	}
 }
 
 Device (LNKE)
 {
-	Name (_HID, EISAID("PNP0C0F"))
+	Name (_HID, EISAID ("PNP0C0F"))
 	Name (_UID, 5)
 
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Or (\_SB.PERC, 0x80, \_SB.PERC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
+	Name (_PRS, ResourceTemplate ()
 	{
 		IRQ (Level, ActiveLow, Shared)
 			{ 3, 4, 5, 6, 10, 12, 14, 15 }
 	})
 
-	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
-		Name (RTLE, ResourceTemplate()
+		Name (RTLA, ResourceTemplate ()
 		{
 			IRQ (Level, ActiveLow, Shared) {}
 		})
-		CreateWordField (RTLE, 1, IRQ0)
-
-		// Clear the WordField
+		CreateWordField (RTLA, 1, IRQ0)
 		Store (Zero, IRQ0)
 
-		// Set the bit from PRTE
-		ShiftLeft (1, And (\_SB.PERC, 0x0f), IRQ0)
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0)
 
-		Return (RTLE)
+		Return (RTLA)
 	}
 
-	// Set Resource Setting for this IRQ link
 	Method (_SRS, 1, Serialized)
 	{
 		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
 		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, \_SB.PERC)
+		Decrement (Local0)
+		Store (Local0, ^^PIRE)
 	}
 
-	// Status
 	Method (_STA, 0, Serialized)
 	{
-		If(And (\_SB.PERC, 0x80)) {
+		If (And (^^PIRE, ^^IREN)) {
 			Return (0x9)
 		} Else {
 			Return (0xb)
 		}
 	}
+
+	Method (_DIS, 0, Serialized)
+	{
+		Or (^^PIRE, ^^IREN, ^^PIRE)
+	}
 }
 
 Device (LNKF)
 {
-	Name (_HID, EISAID("PNP0C0F"))
+	Name (_HID, EISAID ("PNP0C0F"))
 	Name (_UID, 6)
 
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Or (\_SB.PFRC, 0x80, \_SB.PFRC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
+	Name (_PRS, ResourceTemplate ()
 	{
 		IRQ (Level, ActiveLow, Shared)
 			{ 3, 4, 5, 6, 10, 12, 14, 15 }
 	})
 
-	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
-		Name (RTLF, ResourceTemplate()
+		Name (RTLA, ResourceTemplate ()
 		{
 			IRQ (Level, ActiveLow, Shared) {}
 		})
-		CreateWordField (RTLF, 1, IRQ0)
-
-		// Clear the WordField
+		CreateWordField (RTLA, 1, IRQ0)
 		Store (Zero, IRQ0)
 
-		// Set the bit from PRTF
-		ShiftLeft (1, And (\_SB.PFRC, 0x0f), IRQ0)
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0)
 
-		Return (RTLF)
+		Return (RTLA)
 	}
 
-	// Set Resource Setting for this IRQ link
 	Method (_SRS, 1, Serialized)
 	{
 		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
 		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, \_SB.PFRC)
+		Decrement (Local0)
+		Store (Local0, ^^PIRF)
 	}
 
-	// Status
 	Method (_STA, 0, Serialized)
 	{
-		If(And (\_SB.PFRC, 0x80)) {
+		If (And (^^PIRF, ^^IREN)) {
 			Return (0x9)
 		} Else {
 			Return (0xb)
 		}
 	}
+
+	Method (_DIS, 0, Serialized)
+	{
+		Or (^^PIRF, ^^IREN, ^^PIRF)
+	}
 }
 
 Device (LNKG)
 {
-	Name (_HID, EISAID("PNP0C0F"))
+	Name (_HID, EISAID ("PNP0C0F"))
 	Name (_UID, 7)
 
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Or (\_SB.PGRC, 0x80, \_SB.PGRC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
+	Name (_PRS, ResourceTemplate ()
 	{
 		IRQ (Level, ActiveLow, Shared)
 			{ 3, 4, 5, 6, 10, 12, 14, 15 }
 	})
 
-	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
-		Name (RTLG, ResourceTemplate()
+		Name (RTLA, ResourceTemplate ()
 		{
 			IRQ (Level, ActiveLow, Shared) {}
 		})
-		CreateWordField (RTLG, 1, IRQ0)
-
-		// Clear the WordField
+		CreateWordField (RTLA, 1, IRQ0)
 		Store (Zero, IRQ0)
 
-		// Set the bit from PRTG
-		ShiftLeft (1, And (\_SB.PGRC, 0x0f), IRQ0)
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0)
 
-		Return (RTLG)
+		Return (RTLA)
 	}
 
-	// Set Resource Setting for this IRQ link
 	Method (_SRS, 1, Serialized)
 	{
 		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
 		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, \_SB.PGRC)
+		Decrement (Local0)
+		Store (Local0, ^^PIRG)
 	}
 
-	// Status
 	Method (_STA, 0, Serialized)
 	{
-		If(And (\_SB.PGRC, 0x80)) {
+		If (And (^^PIRG, ^^IREN)) {
 			Return (0x9)
 		} Else {
 			Return (0xb)
 		}
 	}
-}
 
-Device (LNKH)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 8)
-
-	// Disable method
 	Method (_DIS, 0, Serialized)
 	{
-		Or (\_SB.PHRC, 0x80, \_SB.PHRC)
+		Or (^^PIRG, ^^IREN, ^^PIRG)
 	}
+}
 
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
+Device (LNKH)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 1)
+
+	Name (_PRS, ResourceTemplate ()
 	{
 		IRQ (Level, ActiveLow, Shared)
 			{ 3, 4, 5, 6, 10, 12, 14, 15 }
 	})
 
-	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
-		Name (RTLH, ResourceTemplate()
+		Name (RTLA, ResourceTemplate ()
 		{
 			IRQ (Level, ActiveLow, Shared) {}
 		})
-		CreateWordField (RTLH, 1, IRQ0)
-
-		// Clear the WordField
+		CreateWordField (RTLA, 1, IRQ0)
 		Store (Zero, IRQ0)
 
-		// Set the bit from PRTH
-		ShiftLeft (1, And (\_SB.PHRC, 0x0f), IRQ0)
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0)
 
-		Return (RTLH)
+		Return (RTLA)
 	}
 
-	// Set Resource Setting for this IRQ link
 	Method (_SRS, 1, Serialized)
 	{
 		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
 		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, \_SB.PHRC)
+		Decrement (Local0)
+		Store (Local0, ^^PIRH)
 	}
 
-	// Status
 	Method (_STA, 0, Serialized)
 	{
-		If(And (\_SB.PHRC, 0x80)) {
+		If (And (^^PIRH, ^^IREN)) {
 			Return (0x9)
 		} Else {
 			Return (0xb)
 		}
 	}
-}
 
+	Method (_DIS, 0, Serialized)
+	{
+		Or (^^PIRH, ^^IREN, ^^PIRH)
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/itss.asl b/src/soc/intel/skylake/acpi/itss.asl
deleted file mode 100644
index 8ba9513..0000000
--- a/src/soc/intel/skylake/acpi/itss.asl
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * This file is part of the coreboot project.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* ITSS */
-/* Define the needed ITSS registers used by ASL on Interrupt */
-
-Scope (\_SB)
-{
-	OperationRegion (ITSS, SystemMemory, 0xfdc43100, 0x8)
-	Field (ITSS, ByteAcc, NoLock, Preserve)
-	{
-		PARC, 8,
-		PBRC, 8,
-		PCRC, 8,
-		PDRC, 8,
-		PERC, 8,
-		PFRC, 8,
-		PGRC, 8,
-		PHRC, 8,
-	}
-
-	/*
-	 * Pin# = group_pad# + group# * 24.
-	 * For instance, GPP_A_6 would be pin#6,
-	 * 	GPP_D_23 would be 23+(3*24), pin#95.
-	 */
-	Name (GPPG, Package (0x02)
-	{
-		Package (0x08)
-		{
-			0x18,
-			0x18,
-			0x18,
-			0x18,
-			0x18,
-			0x18,
-			0x08,
-			0x0C
-		},
-
-		Package (0x0A)
-		{
-			0x18,
-			0x18,
-			0x18,
-			0x18,
-			0x0D,
-			0x18,
-			0x18,
-			0x18,
-			0x0B,
-			0x0C
-		}
-	})
-
-	Method (GNMB, 1, Serialized)
-	{
-		Return (And (Arg0, 0xFFFF))
-	}
-
-	Method (GGRP, 1, Serialized)
-	{
-		ShiftRight (And (Arg0, 0x00FF0000), 0x10, Local0)
-		Return (Local0)
-	}
-
-	/* Convert GPIO PAD name to GPIO number */
-	Method (INUM, 1, NotSerialized)
-	{
-		Store (One, Local0)
-		Store (GNMB (Arg0), Local1)
-		Store (GGRP (Arg0), Local2)
-		Store (Zero, Local3)
-
-		While (LLess (Local3, Local2))
-		{
-			Add (DerefOf (Index (DerefOf (Index
-					(GPPG, Local0)), Local3)),
-					Local1, Local1)
-			Increment (Local3)
-		}
-
-		Return (Add (0x18, Mod (Local1, 0x60)))
-	}
-}
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 581efa0..c72a704 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -47,7 +47,6 @@
 #include "smbus.asl"
 
 
-#include "itss.asl"
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
 


From gerrit at coreboot.org  Mon Sep  7 18:42:08 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:08 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Move storage controllers to separate file
References: <I43081e661b7220bfa635c2d166c3675a0ff910d6+0@gerrit.coreboot.org>
Message-ID: <I43081e661b7220bfa635c2d166c3675a0ff910d6+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11535

-gerrit

commit b554ae8eedfea1c8c961391ea58522eeef253343
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:53:45 2015 -0700

    skylake: ACPI: Move storage controllers to separate file
    
    Move the storage controller devices out of serialio.asl
    and into a new scs.asl file and implement the power
    gating workarounds for D0 and D3 transitions.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529
    Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295908
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/pch.asl      |   2 +
 src/soc/intel/skylake/acpi/scs.asl      | 125 ++++++++++++++++++++++++++++++++
 src/soc/intel/skylake/acpi/serialio.asl |  29 --------
 3 files changed, 127 insertions(+), 29 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index c72a704..f2c1a16 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -46,6 +46,8 @@
 /* SMBus 0:1f.3 */
 #include "smbus.asl"
 
+/* Storage Controllers */
+#include "scs.asl"
 
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
new file mode 100644
index 0000000..4eb9683
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* Intel Storage Controllers */
+
+Device (EMMC)
+{
+	Name (_ADR, 0x001E0004)
+	Name (_DDN, "eMMC Controller")
+
+	OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
+	Field (EMCR, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x84),	/* PMECTRLSTATUS */
+		D0D3, 2,	/* POWERSTATE */
+		Offset (0xa2),	/* PG_CONFIG */
+		, 2,
+		PGEN, 1,	/* PG_ENABLE */
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		/* Disable Power Good */
+		Store (0, ^PGEN)
+
+		/* Clear bits 31, 6, 2, 0 */
+		^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA)
+		Sleep (2)
+
+		/* Set bits 31, 6, 2, 0 */
+		^^PCRO (PID_SCS, 0x600, 0x80000045)
+
+		/* Set Power State to D0 */
+		Store (0, ^D0D3)
+		Store (^D0D3, Local0)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		/* Enable Power Good */
+		Store (1, ^PGEN)
+
+		/* Set Power State to D0 */
+		Store (3, ^D0D3)
+		Store (^D0D3, Local0)
+	}
+
+	Device (CARD)
+	{
+		Name (_ADR, 0x00000008)
+		Method (_RMV, 0, NotSerialized)
+		{
+			Return (0)
+		}
+	}
+}
+
+Device (SDXC)
+{
+	Name (_ADR, 0x001E0006)
+	Name (_DDN, "SD Controller")
+
+	OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
+	Field (SDCR, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x84),	/* PMECTRLSTATUS */
+		D0D3, 2,	/* POWERSTATE */
+		Offset (0xa2),	/* PG_CONFIG */
+		, 2,
+		PGEN, 1,	/* PG_ENABLE */
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		/* Disable Power Good */
+		Store (0, ^PGEN)
+
+		/* Clear bits 8, 7, 2, 0 */
+		^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
+		Sleep (2)
+
+		/* Set bits 31, 6, 2, 0 */
+		^^PCRO (PID_SCS, 0x600, 0x00000185)
+
+		/* Set Power State to D0 */
+		Store (0, ^D0D3)
+		Store (^D0D3, Local0)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		/* Enable Power Good */
+		Store (1, ^PGEN)
+
+		/* Set Power State to D0 */
+		Store (3, ^D0D3)
+		Store (^D0D3, Local0)
+	}
+
+	Device (CARD)
+	{
+		Name (_ADR, 0x00000008)
+		Method (_RMV, 0, NotSerialized)
+		{
+			Return (1)
+		}
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl
index e57b937..d3dca7f 100644
--- a/src/soc/intel/skylake/acpi/serialio.asl
+++ b/src/soc/intel/skylake/acpi/serialio.asl
@@ -618,32 +618,3 @@ Device (UAR2)
 		^^LPD3 (\SAB1, \SAEN)
 	}
 }
-
-
-Device (PEMC)
-{
-	Name (_ADR, 0x001E0004)
-	Device (CARD)
-	{
-		Name (_ADR, 0x00000008)
-		Method (_RMV, 0x0, NotSerialized)
-		{
-			Return (0)
-		}
-	}
-}
-
-/* SD controller */
-Device (PSDC)
-{
-	Name (_ADR, 0x001E0006)
-	Device (CARD)
-	{
-		Name (_ADR, 0x00000008)
-		Method (_RMV, 0x0, NotSerialized)
-		{
-			Return (1)
-		}
-	}
-}
-


From gerrit at coreboot.org  Mon Sep  7 18:42:10 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:10 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Remove SerialIO ACPI mode code
References: <Id0112830211707ba3d67d4dda29dd93397b5b180+0@gerrit.coreboot.org>
Message-ID: <Id0112830211707ba3d67d4dda29dd93397b5b180+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11536

-gerrit

commit 73c4a6dd93d45298cd436aa45bd2dfc1db4cfa26
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:58:23 2015 -0700

    skylake: ACPI: Remove SerialIO ACPI mode code
    
    Skylake moves back to having SerialIO devices be enumerated
    as PCI devices instead of putting them all in ACPI mode.
    
    There is currently no code that populates the device_nvs
    fields so all the ACPI code to support that is dead.
    
    Additionally because it contains _PS0/_PS3 methods that
    causes the kernel to not use the standard PCIe PME handlers
    and results in confusing messages at boot about not being
    able to transition to a non-D0 state from D3.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=build and boot on glados and ensure I2C devices work
    
    Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b
    Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295909
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/device_nvs.asl |  60 ----
 src/soc/intel/skylake/acpi/globalnvs.asl  |   3 -
 src/soc/intel/skylake/acpi/serialio.asl   | 552 +-----------------------------
 src/soc/intel/skylake/include/soc/nvs.h   |   5 +-
 4 files changed, 20 insertions(+), 600 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/device_nvs.asl b/src/soc/intel/skylake/acpi/device_nvs.asl
deleted file mode 100644
index e84d25a..0000000
--- a/src/soc/intel/skylake/acpi/device_nvs.asl
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* Device Enabled in ACPI Mode */
-
-S0EN,	8,	// I2C0 Enable
-S1EN,	8,	// I2C1 Enable
-S2EN,	8,	// I2C2 Enable
-S3EN,	8,	// I2C3 Enable
-S4EN,	8,	// I2C4 Enable
-S5EN,	8,	// I2C5 Enable
-S6EN,	8,	// SPI0 Enable
-S7EN,	8,	// SPI1 Enable
-S8EN,	8,	// UART0 Enable
-S9EN,	8,	// UART1 Enable
-SAEN,	8,	// UART2 Enable
-
-/* BAR 0 */
-S0B0,	32,	// I2C0 BAR0
-S1B0,	32,	// I2C1 BAR0
-S2B0,	32,	// I2C2 BAR0
-S3B0,	32,	// I2C3 BAR0
-S4B0,	32,	// I2C4 BAR0
-S5B0,	32,	// I2C5 BAR0
-S6B0,	32,	// SPI0 BAR0
-S7B0,	32,	// SPI1 BAR0
-S8B0,	32,	// UART0 BAR0
-S9B0,	32,	// UART1 BAR0
-SAB0,	32,	// UART2 BAR0
-
-/* BAR 1 */
-S0B1,	32,	// I2C0 BAR1
-S1B1,	32,	// I2C1 BAR1
-S2B1,	32,	// I2C2 BAR1
-S3B1,	32,	// I2C3 BAR1
-S4B1,	32,	// I2C4 BAR1
-S5B1,	32,	// I2C5 BAR1
-S6B1,	32,	// SPI0 BAR1
-S7B1,	32,	// SPI1 BAR1
-S8B1,	32,	// UART0 BAR1
-S9B1,	32,	// UART1 BAR1
-SAB1,	32,	// UART2 BAR1
-
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index b41fa42..0208198 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -69,9 +69,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 
-	/* Device specific */
-	Offset (0x1000),
-	#include "device_nvs.asl"
 }
 
 /* Set flag to enable USB charging in S5 */
diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl
index d3dca7f..da38891 100644
--- a/src/soc/intel/skylake/acpi/serialio.asl
+++ b/src/soc/intel/skylake/acpi/serialio.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,603 +18,89 @@
  * Foundation, Inc.
  */
 
-// Intel Serial IO Devices in ACPI Mode
-
-/* Serial IO Device BAR0 and BAR1 is 4KB */
-#define SIO_BAR_LEN 0x1000
-
-/* Put SerialIO device in D0 state */
-/* Arg0 - BAR1 of device */
-/* Arg1 - Set if device is in ACPI mode */
-
-Method (LPD0, 2, Serialized)
-{
-	/* PCI mode devices will be handled by OS PCI bus driver */
-	If (LEqual (Arg1, 0)) {
-		Return
-	}
-
-	OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	And (SPCS, 0xFFFFFFFC, SPCS)
-	/* Read back after writing */
-	Store (SPCS, Local0)
-}
-
-/* Put SerialIO device in D3 state */
-/* Arg0 - BAR1 of device */
-/* Arg1 - Set if device is in ACPI mode */
-
-Method (LPD3, 2, Serialized)
-{
-	/* PCI mode devices will be handled by OS PCI bus driver */
-	If (LEqual (Arg1, 0)) {
-		Return
-	}
-	OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-	Or (SPCS, 0x3, SPCS)
-	Store (SPCS, Local0) // Read back after writing
-}
-
-/* Serial IO Resource Consumption for BAR1 */
-Device (SIOR)
-{
-	Name (_HID, EISAID("PNP0C02"))
-	Name (_UID, 5)
-	Method(ADDB,3,Serialized) {
-	Name (BUFF, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x1000, BUF)
-	})
-	CreateDWordField(BUFF,BUF._BAS,ADDR)
-	CreateDWordField(BUFF,BUF._LEN,LENG)
-	Store(ResourceTemplate(){}, Local0)
-	//Return (RBUF)
-	}
-}
+/* Intel Serial IO Devices */
 
 Device (I2C0)
 {
-	/* Serial IO I2C0 Controller */
-	Name (_HID,"INT3442")
-	Name (_UID, 1)
 	Name (_ADR, 0x00150000)
+	Name (_DDN, "Serial IO I2C Controller 0")
+
 	Name (SSCN, Package () { 432, 507, 30 })
 	Name (FMCN, Package () { 72, 160, 30 })
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_I2C0_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		If (LNotEqual (\S0B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S0B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S0EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S0B1, \S0EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S0B1, \S0EN)
-	}
-
 }
 
 Device (I2C1)
 {
-	/* Serial IO I2C1 Controller */
-	Name (_HID,"INT3443")
-	Name (_UID, 1)
 	Name (_ADR, 0x00150001)
+	Name (_DDN, "Serial IO I2C Controller 1")
+
 	Name (SSCN, Package () { 528, 640, 30 })
 	Name (FMCN, Package () { 128, 160, 30 })
 	Name (FPCN, Package () { 48, 64, 30})
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_I2C1_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		If (LNotEqual (\S1B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S1B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S1EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S1B1, \S1EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S1B1, \S1EN)
-	}
 }
 
-
 Device (I2C2)
 {
-	/* Serial IO I2C1 Controller */
-	Name (_HID,"INT3444")
-	Name (_UID, 1)
 	Name (_ADR, 0x00150002)
+	Name (_DDN, "Serial IO I2C Controller 2")
+
 	Name (SSCN, Package () { 432, 507, 30 })
 	Name (FMCN, Package () { 72, 160, 30 })
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_I2C2_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		If (LNotEqual (\S2B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S2B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S2EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S2B1, \S2EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S2B1, \S2EN)
-	}
 }
 
 Device (I2C3)
 {
-	/* Serial IO I2C3 Controller */
-	Name (_HID,"INT3445")
-	Name (_UID, 1)
 	Name (_ADR, 0x00150003)
+	Name (_DDN, "Serial IO I2C Controller 3")
+
 	Name (SSCN, Package () { 432, 507, 30 })
 	Name (FMCN, Package () { 72, 160, 30 })
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-				{ LPSS_I2C3_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		If (LNotEqual (\S3B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S3B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S3EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S3B1, \S3EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S3B1, \S3EN)
-	}
-
 }
 
 Device (I2C4)
 {
-	/* Serial IO I2C4 Controller */
-	Name (_HID,"INT3446")
-	Name (_UID, 1)
 	Name (_ADR, 0x00190002)
+	Name (_DDN, "Serial IO I2C Controller 4")
+
 	Name (SSCN, Package () { 432, 507, 30 })
 	Name (FMCN, Package () { 72, 160, 30 })
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_I2C4_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS*/
-		 If (LNotEqual (\S4B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S4B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S4EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S4B1, \S4EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S4B1, \S4EN)
-	}
 }
 
 Device (I2C5)
 {
-	/* Serial IO I2C1 Controller */
-	Name (_HID,"INT3447")
-	Name (_UID, 1)
 	Name (_ADR, 0x00190002)
+	Name (_DDN, "Serial IO I2C Controller 5")
+
 	Name (SSCN, Package () { 432, 507, 30 })
 	Name (FMCN, Package () { 72, 160, 30 })
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_I2C5_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-		CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-		Store (0xFE02A000, B0AD)
-		Store (SIO_BAR_LEN, B0LN)
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S5EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S5B1, \S5EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S5B1, \S5EN)
-	}
 }
 
 Device (SPI0)
 {
-	/* Serial IO PI0 Controller */
-	Name (_HID,"INT3440")
-	Name (_UID, 1)
 	Name (_ADR, 0x001E0002)
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_SPI0_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		If (LNotEqual (\S6B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S6B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S6EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S6B1, \S6EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S6B1, \S6EN)
-	}
+	Name (_DDN, "Serial IO SPI Controller 0")
 }
 
 Device (SPI1)
 {
-	/* Serial IO SPI1 Controller */
-	Name (_HID,"INT3441")
-	Name (_UID, 1)
 	Name (_ADR, 0x001E0003)
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_SPI1_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		If (LNotEqual (\S7B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S7B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S7EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S7B1, \S7EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S7B1, \S7EN)
-	}
+	Name (_DDN, "Serial IO SPI Controller 1")
 }
 
 Device (UAR0)
 {
-	/* Serial IO UART0 Controller */
-	Name (_HID,"INT3448")
-	Name (_UID, 1)
 	Name (_ADR, 0x001E0000)
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_UART0_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		If (LNotEqual (\S8B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S8B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S8EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S8B1, \S8EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S8B1, \S8EN)
-	}
+	Name (_DDN, "Serial IO UART Controller 0")
 }
 
 Device (UAR1)
 {
-	/* Serial IO UART1 Controller */
-	Name (_HID,"INT3449")
-	Name (_UID, 1)
 	Name (_ADR, 0x001E0001)
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_UART1_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S9B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S9B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S9EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S9B1, \S9EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S9B1, \S9EN)
-	}
+	Name (_DDN, "Serial IO UART Controller 1")
 }
 
 Device (UAR2)
 {
-	/* Serial IO UART1 Controller */
-	Name (_HID,"INT344A")
-	Name (_UID, 1)
 	Name (_ADR, 0x00190000)
-
-	/* BAR0 is assigned during PCI enumeration and saved into NVS */
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ LPSS_UART2_IRQ }
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		/* Update BAR0 address and length if set in NVS */
-		If (LNotEqual (\SAB0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\SAB0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\SAEN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\SAB1, \SAEN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\SAB1, \SAEN)
-	}
+	Name (_DDN, "Serial IO UART Controller 2")
 }
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 2d8129b..c9fcb4e 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -24,7 +24,6 @@
 
 #include <rules.h>
 #include <vendorcode/google/chromeos/gnvs.h>
-#include <soc/device_nvs.h>
 
 typedef struct {
 	/* Miscellaneous */
@@ -61,12 +60,10 @@ typedef struct {
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;
-
-	/* Device specific (0x1000) */
-	device_nvs_t dev;
 } __attribute__((packed)) global_nvs_t;
 
 void acpi_create_gnvs(global_nvs_t *gnvs);
+
 #if ENV_SMM
 /* Used in SMM to find the ACPI GNVS address */
 global_nvs_t *smm_get_gnvs(void);


From gerrit at coreboot.org  Mon Sep  7 18:42:12 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:12 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Clean up and fix XHCI ACPI Device
References: <I535c9d22308c45a3b9bf7e4045c3d01481acc19c+0@gerrit.coreboot.org>
Message-ID: <I535c9d22308c45a3b9bf7e4045c3d01481acc19c+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11537

-gerrit

commit d86a0ea1774a5d9c67ce970ef8ad031aa6f94be5
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 17:09:02 2015 -0700

    skylake: ACPI: Clean up and fix XHCI ACPI Device
    
    - Remove the old workarounds for XHCI from broadwell
    - Add PMC device to expose bits needed for XHCI workarounds
    - Implement the new workarounds for XHCI, the first will set
    a bit in the XHCI MMIO and the second will send a message
    to the PMC if a bit is set indicating the workaround is available.
    - Clean up the HS/SS port defines and remove unnecessary
    methods to determine the port count since we only support SPT-LP.
    
    BUG=chrome-os-partner:44622,chrome-os-partner:44518
    BRANCH=none
    TEST=build and boot on glados, verify that D0 and D3 can be
    made to work (by disabling unused USB and the misbehaving camera)
    
    Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88
    Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295950
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/pch.asl  |   3 +
 src/soc/intel/skylake/acpi/pmc.asl  |  45 +++++
 src/soc/intel/skylake/acpi/xhci.asl | 369 ++++++++++++------------------------
 3 files changed, 165 insertions(+), 252 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index f2c1a16..951b97a 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -40,6 +40,9 @@
 /* PCR Access */
 #include "pcr.asl"
 
+/* PMC 0:1f.2 */
+#include "pmc.asl"
+
 /* Serial IO */
 #include "serialio.asl"
 
diff --git a/src/soc/intel/skylake/acpi/pmc.asl b/src/soc/intel/skylake/acpi/pmc.asl
new file mode 100644
index 0000000..2d826f6
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/pmc.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device (PMC)
+{
+	Name (_ADR, 0x001f0002)
+	Name (_DDN, "Power Management Controller")
+
+	OperationRegion (PMCP, PCI_Config, 0x00, 0x100)
+	Field (PMCP, AnyAcc, NoLock, Preserve)
+	{
+		Offset (0x48),
+		, 12,
+		PWRM, 20,	/* PWRMBASE */
+	}
+
+	OperationRegion (PMCM, SystemMemory, ShiftLeft (PWRM, 12), 0x3f)
+	Field (PMCM, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x1c),	/* PCH_PM_STS */
+		, 24,
+		PMFS, 1,	/* PMC_MSG_FULL_STS */
+		Offset (0x20),
+		MPMC, 32,	/* MTPMC */
+		Offset (0x24),	/* PCH_PM_STS2 */
+		, 20,
+		UWAB, 1,	/* USB2 Workaround Available */
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index f0ee414..5e49087 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -25,297 +25,162 @@ Device (XHCI)
 {
 	Name (_ADR, 0x00140000)
 
-	Name (PLSD, 5) /* Port Link State - RxDetect */
-	Name (PLSP, 7) /* Port Link State - Polling */
+	Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+	Method (_DSW, 3)
+	{
+		Store (Arg0, PMEE)
+	}
+
+	Name (_S3D, 3)	/* D3 supported in S3 */
+	Name (_S4D, 3)	/* D3 supported in S4 */
+	Name (_S0W, 3)	/* D3 can wake device in S0 */
+	Name (_S3W, 3)	/* D3 can wake system from S3 */
+	Name (_S4W, 3)	/* D3 can wake system from S4 */
 
 	OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
 	Field (XPRT, AnyAcc, NoLock, Preserve)
 	{
 		Offset (0x0),
-		DVID, 16,
+		DVID, 16,	/* VENDORID */
 		Offset (0x10),
 		, 16,
 		XMEM, 16,	/* MEM_BASE */
 		Offset (0x74),
-		D0D3, 2,
+		D0D3, 2,	/* POWERSTATE */
 		, 6,
 		PMEE, 1,	/* PME_EN */
 		, 6,
 		PMES, 1,	/* PME_STS */
-		Offset (0xA8),
-		, 13,
-		MW13, 1,
-		MW14, 1,
-		, 17,
-		Offset (0xb0),
-		, 13,
-		MB13, 1,
-		MB14, 1,
-		, 17,
-		Offset (0xd0),
-		PR2, 32,	/* USB2PR */
-		PR2M, 32,	/* USB2PRM */
-		PR3, 32,	/* USB3PR */
-		PR3M, 32,	/* USB3PRM */
 	}
 
-	Method (USRA,0){
-		Return(11)
+	OperationRegion (XREG, SystemMemory,
+			 Add (ShiftLeft (XMEM, 16), 0x8000), 0x200)
+	Field (XREG, DWordAcc, Lock, Preserve)
+	{
+		Offset (0x1c4),	/* USB2PMCTRL */
+		, 2,
+		UPSW, 2,	/* U2PSUSPGP */
 	}
 
-	Method (SSPA,0){
-		Return (13)
+	Method (_PSC, 0, Serialized)
+	{
+		Return (^D0D3)
 	}
 
-	/* Clear status bits */
-	Method (LPCL, 0, Serialized)
+	Method (_PS0, 0, Serialized)
 	{
-		OperationRegion (XREG, SystemMemory,
-			 ShiftLeft (^XMEM, 16), 0x600)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x510), /* PORTSCNUSB3[0]*/
-			PSC0, 32,
-			Offset (0x520), /* PORTSCNUSB3[1]*/
-			PSC1, 32,
-			Offset (0x530), /* PORTSCNUSB3[2]*/
-			PSC2, 32,
-			Offset (0x540), /* PORTSCNUSB3[3]*/
-			PSC3, 32,
+		If (LEqual (^DVID, 0xFFFF)) {
+			Return
+		}
+		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
+			Return
 		}
 
-		/* Port Enabled/Disabled (Bit 1)*/
-		Name (PEDB, ShiftLeft (1, 1))
-
-		/* Change Status (Bits 23:17)*/
-		Name (CHST, ShiftLeft (0x7f, 17))
-
-		/* Port 0 */
-		And (PSC0, Not (PEDB), Local0)
-		Or (Local0, CHST, PSC0)
-
-		/* Port 1 */
-		And (PSC1, Not (PEDB), Local0)
-		Or (Local0, CHST, PSC1)
-
-		/* Port 2 */
-		And (PSC2, Not (PEDB), Local0)
-		Or (Local0, CHST, PSC2)
+		/* If device is in D3, set back to D0 */
+		If (LEqual (^D0D3, 3)) {
+			Store (Zero, ^D0D3)
+			Store (^D0D3, Local0)
+		}
 
-		/* Port 3 */
-		And (PSC3, Not (PEDB), Local0)
-		Or (Local0, CHST, PSC3)
+		/* Disable USB2 PHY SUS Well Power Gating */
+		Store (Zero, ^UPSW)
+
+		/*
+		 * Apply USB2 PHPY Power Gating workaround if needed.
+		 */
+		If (^^PMC.UWAB) {
+			/* Write to MTPMC to have PMC disable power gating */
+			Store (1, ^^PMC.MPMC)
+
+			/* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */
+			Store (10, Local0)
+			While (^^PMC.PMFS) {
+				If (LNot (Local0)) {
+					Break
+				}
+				Decrement (Local0)
+				Sleep (10)
+			}
+		}
 	}
 
-	Method (LPS0, 0, Serialized)
+	Method (_PS3, 0, Serialized)
 	{
-		OperationRegion (XREG, SystemMemory,
-				 ShiftLeft (^XMEM, 16), 0x600)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x510), // PORTSCNUSB3
-			, 5,
-			PLS1, 4,	// [8:5] Port Link State
-			PPR1, 1,	// [9] Port Power
-			, 7,
-			CSC1, 1,	// [17] Connect Status Change
-			, 1,
-			WRC1, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR1, 1,	// [31] Warm Port Reset
-			Offset (0x520), // PORTSCNUSB3
-			, 5,
-			PLS2, 4,	// [8:5] Port Link State
-			PPR2, 1,	// [9] Port Power
-			, 7,
-			CSC2, 1,	// [17] Connect Status Change
-			, 1,
-			WRC2, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR2, 1,	// [31] Warm Port Reset
-			Offset (0x530), // PORTSCNUSB3
-			, 5,
-			PLS3, 4,	// [8:5] Port Link State
-			PPR3, 1,	// [9] Port Power
-			, 7,
-			CSC3, 1,	// [17] Connect Status Change
-			, 1,
-			WRC3, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR3, 1,	// [31] Warm Port Reset
-			Offset (0x540), // PORTSCNUSB3
-			, 5,
-			PLS4, 4,	// [8:5] Port Link State
-			PPR4, 1,	// [9] Port Power
-			, 7,
-			CSC4, 1,	// [17] Connect Status Change
-			, 1,
-			WRC4, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR4, 1,	// [31] Warm Port Reset
+		If (LEqual (^DVID, 0xFFFF)) {
+			Return
 		}
-
-		/* Wait for all powered ports to finish polling*/
-		Store (10, Local0)
-		While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)),
-				 LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))),
-			    LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)),
-				 LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP)))))
-		{
-			If (LEqual (Local0, 0)) {
-				Break
-			}
-			Decrement (Local0)
-			Stall (10)
+		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
+			Return
 		}
 
-		/* For each USB3 Port:*/
-		/*   If port is disconnected (PLS=5 PP=1 CSC=0)*/
-		/*     1) Issue warm reset (WPR=1)*/
-		/*     2) Poll for warm reset complete (WRC=0)*/
-		/*     3) Write 1 to port status to clear*/
+		/* Clear PME Status */
+		Store (1, ^PMES)
 
-		/* Local# indicate if port is reset*/
-		Store (0, Local1)
-		Store (0, Local2)
-		Store (0, Local3)
-		Store (0, Local4)
+		/* Enable PME */
+		Store (1, ^PMEE)
 
-		If (LAnd (LEqual (PLS1, PLSD),
-		          LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) {
-			Store (1, WPR1)	      /* Issue warm reset*/
-			Store (1, Local1)
-		}
-		If (LAnd (LEqual (PLS2, PLSD),
-		          LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) {
-			Store (1, WPR2)	      /* Issue warm reset*/
-			Store (1, Local2)
-		}
-		If (LAnd (LEqual (PLS3, PLSD),
-		          LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) {
-			Store (1, WPR3)	      /* Issue warm reset*/
-			Store (1, Local3)
-		}
-		If (LAnd (LEqual (PLS4, PLSD),
-		          LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) {
-			Store (1, WPR4)	      /* Issue warm reset*/
-			Store (1, Local4)
+		/* If device is in D3, set back to D0 */
+		If (LEqual (^D0D3, 3)) {
+			Store (Zero, ^D0D3)
+			Store (^D0D3, Local0)
 		}
 
-		/* Poll for warm reset complete on all ports that were reset*/
-		Store (10, Local0)
-		While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)),
-				 LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))),
-			    LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)),
-			         LAnd (LEqual (Local4, 1), LEqual (WRC4, 0)))))
-		{
-			If (LEqual (Local0, 0)) {
-				Break
+		/* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */
+		Store (3, ^UPSW)
+
+		/* Now put device in D3 */
+		Store (3, ^D0D3)
+		Store (^D0D3, Local0)
+
+		/*
+		 * Apply USB2 PHPY Power Gating workaround if needed.
+		 * This code assumes XDCI is disabled, if it is enabled
+		 * then this must also check if it is in D3 state too.
+		 */
+		If (^^PMC.UWAB) {
+			/* Write to MTPMC to have PMC enable power gating */
+			Store (3, ^^PMC.MPMC)
+
+			/* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */
+			Store (10, Local0)
+			While (^^PMC.PMFS) {
+				If (LNot (Local0)) {
+					Break
+				}
+				Decrement (Local0)
+				Sleep (10)
 			}
-			Decrement (Local0)
-			Stall (10)
 		}
-
-		/* Clear status bits in all ports */
-		LPCL ()
 	}
 
-	Method (_PSC, 0, NotSerialized)
-	{
-		Return (^D0D3)
-	}
-
-	Method (_PS0, 0, Serialized)
+	/* Root Hub for Skylake-LP PCH */
+	Device (RHUB)
 	{
-	}
-	Method (_PS3, 0, Serialized)
-	{
-	}
+		Name (_ADR, Zero)
 
-	Name (_PRW, Package(){ 0x6d, 3 })
+		/* USB2 */
+		Device (HS01) { Name (_ADR, 1) }
+		Device (HS02) { Name (_ADR, 2) }
+		Device (HS03) { Name (_ADR, 3) }
+		Device (HS04) { Name (_ADR, 4) }
+		Device (HS05) { Name (_ADR, 5) }
+		Device (HS06) { Name (_ADR, 6) }
+		Device (HS07) { Name (_ADR, 7) }
+		Device (HS08) { Name (_ADR, 8) }
+		Device (HS09) { Name (_ADR, 9) }
+		Device (HS10) { Name (_ADR, 10) }
 
-	/* Leave USB ports on for to allow Wake from USB */
+		/* USBr */
+		Device (USR1) { Name (_ADR, 11) }
+		Device (USR2) { Name (_ADR, 12) }
 
-	Method (_S3D,0)	/* Highest D State in S3 State*/
-	{
-		Return (3)
-	}
-
-	Method (_S4D,0)	/* Highest D State in S4 State*/
-	{
-		Return (3)
-	}
-	Device (HS01)
-	{
-		Name(_ADR, 0x01)
-	}
-	Device (HS02)
-	{
-		Name(_ADR, 0x02)
-	}
-	Device (HS03)
-	{
-		Name(_ADR, 0x03)
-	}
-	Device (HS04)
-	{
-		Name(_ADR, 0x04)
-	}
-	Device (HS05)
-	{
-		Name(_ADR, 0x05)
-	}
-	Device (HS06)
-	{
-		Name(_ADR, 0x06)
-	}
-	Device (HS07)
-	{
-		Name(_ADR, 0x07)
-	}
-	Device (HS08)
-	{
-		Name(_ADR, 0x08)
-	}
-	Device (HS09)
-	{
-		Name(_ADR, 0x09)
-	}
-	Device (HS10)
-	{
-		Name(_ADR, 0x10)
-	}
-	Device (USR1)
-	{
-		Method(_ADR) { Return (Add(USRA(),0)) }
-	}
-	Device (USR2)
-	{
-		Method(_ADR) { Return (Add(USRA(),1)) }
-	}
-	Device (SS01)
-	{
-		Method(_ADR) { Return (Add(SSPA(),0)) }
-	}
-	Device (SS02)
-	{
-		Method(_ADR) { Return (Add(SSPA(),1)) }
-	}
-	Device (SS03)
-	{
-		Method(_ADR) { Return (Add(SSPA(),2)) }
-	}
-	Device (SS04)
-	{
-		Method(_ADR) { Return (Add(SSPA(),3)) }
-	}
-	Device (SS05)
-	{
-		Method(_ADR) { Return (Add(SSPA(),4)) }
-	}
-	Device (SS06)
-	{
-		Method(_ADR) { Return (Add(SSPA(),5)) }
+		/* USB3 */
+		Device (SS01) { Name (_ADR, 13) }
+		Device (SS02) { Name (_ADR, 14) }
+		Device (SS03) { Name (_ADR, 15) }
+		Device (SS04) { Name (_ADR, 16) }
+		Device (SS05) { Name (_ADR, 17) }
+		Device (SS06) { Name (_ADR, 18) }
 	}
 }
-


From gerrit at coreboot.org  Mon Sep  7 18:42:14 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:14 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Clean up GPIO controller
References: <Ic82fcb00285aeb2515e24001ef69a882c3df1417+0@gerrit.coreboot.org>
Message-ID: <Ic82fcb00285aeb2515e24001ef69a882c3df1417+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11538

-gerrit

commit c679e9bbd542318dd588cded1988fced69091a63
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 17:15:00 2015 -0700

    skylake: ACPI: Clean up GPIO controller
    
    Switch the GPIO controller to use the PCR functions that are
    defined in pcr.asl.
    
    Have the default memory regions declare a size of zero and
    be fixed up in the _CRS in order to fix compile issues on
    some versions of iasl.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ic82fcb00285aeb2515e24001ef69a882c3df1417
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: be24d9ccd9db62ca694f3a67436af25a73f59c5a
    Original-Change-Id: I13acd891427f467e289d5671add5617befef4380
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295951
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/gpio.asl | 64 ++++++++++++++++---------------------
 1 file changed, 27 insertions(+), 37 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
index 7c2efa6..fed25c3 100644
--- a/src/soc/intel/skylake/acpi/gpio.asl
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -18,54 +18,44 @@
  * Foundation, Inc.
  */
 
-
-/* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */
-Method (PCRR, 2, Serialized)
-{
-	Add (ShiftLeft (Arg0, PCR_PORTID_SHIFT), Arg1, Local0)
-	Add (PCH_PCR_BASE_ADDRESS, Local0, Local0)
-	OperationRegion (PCR0, SystemMemory, Local0, 0x4)
-
-	Field(PCR0, DWordAcc, Lock, Preserve)
-	{
-		Offset(0x00),
-		DAT0, 32
-	}
-	Return (DAT0)
-}
-
 Device (GPIO)
 {
-	/* GPIO Controller */
 	Name (_HID, "INT344B")
 	Name (_UID, 1)
+	Name (_DDN, "GPIO Controller")
 
 	Name (RBUF, ResourceTemplate()
 	{
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R0)
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R1)
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R3)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _R4)
-		{
-			GPIO_IRQ14,
-		}
+		Memory32Fixed (ReadWrite, 0, 0, COM0)
+		Memory32Fixed (ReadWrite, 0, 0, COM1)
+		Memory32Fixed (ReadWrite, 0, 0, COM3)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+			{ 0 }
 	})
 
-	Method (_CRS, 0, NotSerialized)  /* _CRS: Current Resource Settings */
+	Method (_CRS, 0, NotSerialized)
 	{
-		CreateDWordField (^RBUF, ^_R0._BAS, COM0)
-		CreateDWordField (^RBUF, ^_R1._BAS, COM1)
-		CreateDWordField (^RBUF, ^_R3._BAS, COM3)
-		CreateDWordField (^RBUF, ^_R4._INT, IRQN)
+		/* GPIO Community 0 */
+		CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+		CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+		Store (^^PCRB (PID_GPIOCOM0), BAS0)
+		Store (GPIO_BASE_SIZE, LEN0)
+
+		/* GPIO Community 1 */
+		CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+		CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+		Store (^^PCRB (PID_GPIOCOM1), BAS1)
+		Store (GPIO_BASE_SIZE, LEN1)
+
+		/* GPIO Community 3 */
+		CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
+		CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
+		Store (^^PCRB (PID_GPIOCOM3), BAS3)
+		Store (GPIO_BASE_SIZE, LEN3)
 
-		Store (Add (PCH_PCR_BASE_ADDRESS,
-			ShiftLeft (PID_GPIOCOM0, PCR_PORTID_SHIFT)), COM0)
-		Store (Add (PCH_PCR_BASE_ADDRESS,
-			ShiftLeft (PID_GPIOCOM1, PCR_PORTID_SHIFT)), COM1)
-		Store (Add (PCH_PCR_BASE_ADDRESS,
-			ShiftLeft (PID_GPIOCOM3, PCR_PORTID_SHIFT)), COM3)
-		Store (And (PCRR (PID_GPIOCOM0, MISCCFG_OFFSET),
-			GPIO_DRIVER_IRQ_ROUTE_MASK), Local0)
+		CreateDWordField (^RBUF, ^GIRQ._INT, IRQN)
+		And (^^PCRR (PID_GPIOCOM0, MISCCFG_OFFSET),
+			GPIO_DRIVER_IRQ_ROUTE_MASK, Local0)
 
 		If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) {
 			Store (GPIO_IRQ14, IRQN)


From gerrit at coreboot.org  Mon Sep  7 18:42:16 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:16 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Clean up formatting in ASL code
References: <I9726fb337bf53fa7dce72c5f30524b58abb4cab6+0@gerrit.coreboot.org>
Message-ID: <I9726fb337bf53fa7dce72c5f30524b58abb4cab6+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11539

-gerrit

commit 7bf0922d8ec1746c27de0adba3d6229c04ab0226
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 17:19:24 2015 -0700

    skylake: ACPI: Clean up formatting in ASL code
    
    Clean up the formatting in various ASL files and remove
    unused and/or incorrect field definitions.
    
    Add back the methods to set the USB power in S3 field
    in NVS as it is called by the chromium kernel at boot and
    is currently complaining that the method is not found.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I9726fb337bf53fa7dce72c5f30524b58abb4cab6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3a47eeba2792c3abed07be175034c709dbf60879
    Original-Change-Id: I8e8388c9b834fd060990f8e069929ba829e29ab6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295952
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/globalnvs.asl   |  11 ++
 src/soc/intel/skylake/acpi/lpc.asl         |  99 +++++--------
 src/soc/intel/skylake/acpi/pci_irqs.asl    | 230 ++++++++++++++---------------
 src/soc/intel/skylake/acpi/systemagent.asl | 172 +++++++--------------
 4 files changed, 216 insertions(+), 296 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 0208198..31711d1 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -68,7 +68,18 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+}
 
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+	Store (One, \S3U0)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+	Store (Zero, \S3U0)
 }
 
 /* Set flag to enable USB charging in S5 */
diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl
index 877be99..c841311 100644
--- a/src/soc/intel/skylake/acpi/lpc.asl
+++ b/src/soc/intel/skylake/acpi/lpc.asl
@@ -19,33 +19,16 @@
  * Foundation, Inc.
  */
 
-
-// Intel LPC Bus Device  - 0:1f.0
-
 Device (LPCB)
 {
 	Name (_ADR, 0x001f0000)
+	Name (_DDN, "LPC Bus Device")
 
-	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
-	Field (LPC0, AnyAcc, NoLock, Preserve)
-	{
-		Offset (0x02),
-		PDID,	16,	// Device ID
-		Offset (0x40),
-		PMBS,	16,	// PMBASE
-		Offset (0x48),
-		GPBS,	16,	// GPIOBASE
-
-
-		Offset (0x80),	// IO Decode Ranges
-		IOD0,	8,
-		IOD1,	8,
-	}
-
-	Device (DMAC)	// DMA Controller
+	Device (DMAC)
 	{
-		Name (_HID, EISAID("PNP0200"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0200"))
+		Name (_DDN, "DMA Controller")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
 			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
@@ -55,40 +38,34 @@ Device (LPCB)
 		})
 	}
 
-	Device (FWH)	// Firmware Hub
+	Device (FWH)
 	{
-		Name (_HID, EISAID("INT0800"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("INT0800"))
+		Name (_DDN, "Firmware Hub")
+		Name (_CRS, ResourceTemplate ()
 		{
-			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+			Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
 		})
 	}
 
 	Device (HPET)
 	{
-		Name (_HID, EISAID("PNP0103"))
-		Name (BUF0, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0103"))
+		Name (_DDN, "High Precision Event Timer")
+		Name (_CRS, ResourceTemplate ()
 		{
-			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
+			Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
 		})
-
-		Method (_STA, 0)	// Device Status
+		Method (_STA, 0)
 		{
 			Return (0xf)
 		}
-		Method (_CRS, 0, Serialized) // Current resources
-		{
-			CreateDWordField (BUF0, ^FED0._BAS, HPT0)
-			/* TODO: Base address configured need to pass as GNVS */
-			Store(HPET_BASE_ADDRESS, HPT0)
-
-			Return(BUF0)
-		}
 	}
 
-	Device(PIC)	// 8259 Interrupt Controller
+	Device (PIC)
 	{
-		Name (_HID,EISAID("PNP0000"))
+		Name (_HID, EISAID ("PNP0000"))
+		Name (_DDN, "8259 Interrupt Controller")
 		Name (_CRS, ResourceTemplate()
 		{
 			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
@@ -112,22 +89,23 @@ Device (LPCB)
 		})
 	}
 
-	Device(MATH)	// FPU
+	Device (MATH)
 	{
-		Name (_HID, EISAID("PNP0C04"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0C04"))
+		Name (_DDN, "Floating Point Unit")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
-			IRQNoFlags() { 13 }
+			IRQNoFlags () { 13 }
 		})
 	}
 
-	Device(LDRC)	// LPC device: Resource consumption
+	Device (LDRC)
 	{
-		Name (_HID, EISAID("PNP0C02"))
+		Name (_HID, EISAID ("PNP0C02"))
 		Name (_UID, 2)
-
-		Name (RBUF, ResourceTemplate()
+		Name (_DDN, "Legacy Device Resources")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
 			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
@@ -141,30 +119,27 @@ Device (LPCB)
 			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
 			    0x1, 0xff)
 		})
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Return (RBUF)
-		}
 	}
 
-	Device (RTC)	// Real Time Clock
+	Device (RTC)
 	{
-		Name (_HID, EISAID("PNP0B00"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0B00"))
+		Name (_DDN, "Real Time Clock")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x70, 0x70, 1, 8)
-			//IRQNoFlags() { 8 }
 		})
 	}
 
-	Device (TIMR)	// Intel 8254 timer
+	Device (TIMR)
 	{
-		Name (_HID, EISAID("PNP0100"))
-		Name (_CRS, ResourceTemplate() {
+		Name (_HID, EISAID ("PNP0100"))
+		Name (_DDN, "8254 Timer")
+		Name (_CRS, ResourceTemplate ()
+		{
 			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
 			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
-			IRQNoFlags() {0}
+			IRQNoFlags () {0}
 		})
 	}
 
diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl
index c43e42d..3bf5f3e 100644
--- a/src/soc/intel/skylake/acpi/pci_irqs.asl
+++ b/src/soc/intel/skylake/acpi/pci_irqs.asl
@@ -19,125 +19,121 @@
  * Foundation, Inc.
  */
 
-Method(_PRT)
+Name (PICP, Package () {
+	/* D31: cAVS, SMBus, GbE, Nothpeak */
+	Package () { 0x001FFFFF, 0, 0, 16 },
+	Package () { 0x001FFFFF, 1, 0, 17 },
+	Package () { 0x001FFFFF, 2, 0, 18 },
+	Package () { 0x001FFFFF, 3, 0, 19 },
+	/* D30: SerialIo and SCS */
+	Package () { 0x001EFFFF, 0, 0, 20 },
+	Package () { 0x001EFFFF, 1, 0, 21 },
+	Package () { 0x001EFFFF, 2, 0, 22 },
+	Package () { 0x001EFFFF, 3, 0, 23 },
+	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001DFFFF, 0, 0, 16 },
+	Package () { 0x001DFFFF, 1, 0, 17 },
+	Package () { 0x001DFFFF, 2, 0, 18 },
+	Package () { 0x001DFFFF, 3, 0, 19 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, 0, 16 },
+	Package () { 0x001CFFFF, 1, 0, 17 },
+	Package () { 0x001CFFFF, 2, 0, 18 },
+	Package () { 0x001CFFFF, 3, 0, 19 },
+	/* D27: PCI Express Port 17-20 */
+	Package () { 0x001BFFFF, 0, 0, 16 },
+	Package () { 0x001BFFFF, 1, 0, 17 },
+	Package () { 0x001BFFFF, 2, 0, 18 },
+	Package () { 0x001BFFFF, 3, 0, 19 },
+	/* D25: SerialIo */
+	Package () { 0x0019FFFF, 0, 0, 32 },
+	Package () { 0x0019FFFF, 1, 0, 33 },
+	Package () { 0x0019FFFF, 2, 0, 34 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, 0, 16 },
+	Package () { 0x0016FFFF, 1, 0, 17 },
+	Package () { 0x0016FFFF, 2, 0, 18 },
+	Package () { 0x0016FFFF, 3, 0, 19 },
+	/* D21: SerialIo */
+	Package () { 0x0015FFFF, 0, 0, 16 },
+	Package () { 0x0015FFFF, 1, 0, 17 },
+	Package () { 0x0015FFFF, 2, 0, 18 },
+	Package () { 0x0015FFFF, 3, 0, 19 },
+	/* D20: xHCI, OTG, Thermal, Camera */
+	Package () { 0x0014FFFF, 0, 0, 16 },
+	Package () { 0x0014FFFF, 1, 0, 17 },
+	Package () { 0x0014FFFF, 2, 0, 18 },
+	Package () { 0x0014FFFF, 3, 0, 19 },
+	/* D19: Integrated Sensor Hub */
+	Package () { 0x0013FFFF, 0, 0, 20 },
+	/* P.E.G. Root Port D1F0 */
+	Package () { 0x0001FFFF, 0, 0, 16 },
+	Package () { 0x0001FFFF, 1, 0, 17 },
+	Package () { 0x0001FFFF, 2, 0, 18 },
+	Package () { 0x0001FFFF, 3, 0, 19 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, 0, 16 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, 0, 16 },
+	/* SA SkyCam Device */
+	Package () { 0x0005FFFF, 0, 0, 16 },
+	/* SA GMM Device */
+	Package () { 0x0008FFFF, 0, 0, 16 },
+})
+
+Name (PICN, Package () {
+	/* D31: cAVS, SMBus, GbE, Nothpeak */
+	Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D27: PCI Express Port 17-20 */
+	Package () { 0x001BFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001BFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001BFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001BFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D23 */
+	Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D20: xHCI, OTG, Thermal, Camera */
+	Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* P.E.G. Root Port D1F0 */
+	Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA Skycam Device */
+	Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA GMM Device */
+	Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
+})
+
+Method (_PRT)
 {
 	If (PICM) {
-		Return (Package() {
-		/* PCI Bridge */
-		/* D31: cAVS, SMBus, GbE, Nothpeak */
-			Package(){0x001FFFFF, 0, 0, 16 },
-			Package(){0x001FFFFF, 1, 0, 17 },
-			Package(){0x001FFFFF, 2, 0, 18 },
-			Package(){0x001FFFFF, 3, 0, 19 },
-		/* D30: SerialIo and SCS */
-			Package(){0x001EFFFF, 0, 0, 20 },
-			Package(){0x001EFFFF, 1, 0, 21 },
-			Package(){0x001EFFFF, 2, 0, 22 },
-			Package(){0x001EFFFF, 3, 0, 23 },
-		/* D29: PCI Express Port 9-16 */
-			Package(){0x001DFFFF, 0, 0, 16 },
-			Package(){0x001DFFFF, 1, 0, 17 },
-			Package(){0x001DFFFF, 2, 0, 18 },
-			Package(){0x001DFFFF, 3, 0, 19 },
-		/* D28: PCI Express Port 1-8 */
-			Package(){0x001CFFFF, 0, 0, 16 },
-			Package(){0x001CFFFF, 1, 0, 17 },
-			Package(){0x001CFFFF, 2, 0, 18 },
-			Package(){0x001CFFFF, 3, 0, 19 },
-		/* D27: PCI Express Port 17-20 */
-			Package(){0x001BFFFF, 0, 0, 16 },
-			Package(){0x001BFFFF, 1, 0, 17 },
-			Package(){0x001BFFFF, 2, 0, 18 },
-			Package(){0x001BFFFF, 3, 0, 19 },
-		/* D25: SerialIo */
-			Package(){0x0019FFFF, 0, 0, 32 },
-			Package(){0x0019FFFF, 1, 0, 33 },
-			Package(){0x0019FFFF, 2, 0, 34 },
-		/* D22: CSME (HECI, IDE-R, Keyboard and Text redirection */
-			Package(){0x0016FFFF, 0, 0, 16 },
-			Package(){0x0016FFFF, 1, 0, 17 },
-			Package(){0x0016FFFF, 2, 0, 18 },
-			Package(){0x0016FFFF, 3, 0, 19 },
-		/* D21: SerialIo */
-			Package(){0x0015FFFF, 0, 0, 16 },
-			Package(){0x0015FFFF, 1, 0, 17 },
-			Package(){0x0015FFFF, 2, 0, 18 },
-			Package(){0x0015FFFF, 3, 0, 19 },
-		/* D20: xHCI, OTG,
-		 * Thermal Subsystem, Camera IO Host Controller
-		 */
-			Package(){0x0014FFFF, 0, 0, 16 },
-			Package(){0x0014FFFF, 1, 0, 17 },
-			Package(){0x0014FFFF, 2, 0, 18 },
-			Package(){0x0014FFFF, 3, 0, 19 },
-		/* D19: Integrated Sensor Hub */
-			Package(){0x0013FFFF, 0, 0, 20 },
-
-		/* Host Bridge */
-		/* P.E.G. Root Port D1F0 */
-			Package(){0x0001FFFF, 0, 0, 16 },
-			Package(){0x0001FFFF, 1, 0, 17 },
-			Package(){0x0001FFFF, 2, 0, 18 },
-			Package(){0x0001FFFF, 3, 0, 19 },
-		/* P.E.G. Root Port D1F1 */
-		/* P.E.G. Root Port D1F2 */
-		/* SA IGFX Device */
-			Package(){0x0002FFFF, 0, 0, 16 },
-		/* SA Thermal Device */
-			Package(){0x0004FFFF, 0, 0, 16 },
-		/* SA SkyCam Device */
-			Package(){0x0005FFFF, 0, 0, 16 },
-		/* SA GMM Device */
-			Package(){0x0008FFFF, 0, 0, 16 },
-		})
+		Return (^PICP)
 	} Else {
-		Return (Package() {
-		/* D31 */
-		Package() { 0x001fffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001fffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001fffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001fffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D29 */
-		Package() { 0x001dffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001dffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001dffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001dffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D28 */
-		Package() { 0x001cffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001cffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001cffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001cffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D27 */
-		Package() { 0x001bffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001bffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001bffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001bffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D23 */
-		Package() { 0x0017ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* D22 */
-		Package() { 0x0016ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0016ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0016ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0016ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D20 */
-		Package() { 0x0014ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0014ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0014ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0014ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* Host bridge */
-		Package() { 0x0001ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0001ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0001ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0001ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* SA IGFX Device */
-		Package() { 0x0002ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA Thermal Device */
-		Package() { 0x0004ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA Skycam Device */
-		Package() { 0x0005ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA GMM Device */
-		Package() { 0x0008ffff, 0, \_SB.PCI0.LNKA, 0 },
-		})
+		Return (^PICN)
 	}
 }
-
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index b8fec94..9c9fc17 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -24,121 +24,73 @@
 #define BASE_32GB	0x800000000
 #define SIZE_16GB	0x400000000
 
-Name (_HID, EISAID ("PNP0A08"))	// PCIe
-Name (_CID, EISAID ("PNP0A03"))	// PCI
+Name (_HID, EISAID ("PNP0A08"))	/* PCIe */
+Name (_CID, EISAID ("PNP0A03"))	/* PCI */
 
 Name (_ADR, 0)
 Name (_BBN, 0)
 
 Device (MCHC)
 {
-	Name (_ADR, 0x00000000)	// 0:0.0
+	Name (_ADR, 0x00000000)
 
 	OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
 	Field (MCHP, DWordAcc, NoLock, Preserve)
 	{
-		Offset(0x40),	// EPBAR (0:0:0:40)
-		EPEN, 1,		// Enable
-			, 11,
-		EPBR, 20,		// EPBAR [31:12]
-
-		Offset(0x48),	// MCHBAR (0:0:0:48)
-		MHEN, 1,		// Enable
-			, 14,
-		MHBR, 17,	// MCHBAR [31:15]
-
-		Offset(0x54),	// DEVEN (0:0:0:54)
-		D0EN, 1,		// DEV0 Enable
-		D1F2, 1,		// DEV1 FUN2 Enable
-		D1F1, 1,		// DEV1 FUN1 Enable
-		D1F0, 1,		// DEV1 FUN0 Enable
-
-		Offset(0x60),	// PCIEXBAR (0:0:0:60)
-		PXEN, 1,		// Enable
-		PXSZ, 2,		// PCI Express Size
-			, 23,
-		PXBR, 6,		// PCI Express BAR [31:26]
-
-		Offset(0x68),	// DMIBAR (0:0:0:68)
-		DIEN, 1,		// Enable
-			, 11,
-		DIBR, 20,		// DMIBAR [31:12]
-
-		Offset (0x70),	// ME Base Address
+		Offset(0x40),	/* EPBAR (0:0:0:40) */
+		EPEN, 1,	/* Enable */
+		, 11,
+		EPBR, 20,	/* EPBAR [31:12] */
+
+		Offset(0x48),	/* MCHBAR (0:0:0:48) */
+		MHEN, 1,	/* Enable */
+		, 14,
+		MHBR, 17,	/* MCHBAR [31:15] */
+
+		Offset(0x60),	/* PCIEXBAR (0:0:0:60) */
+		PXEN, 1,	/* Enable */
+		PXSZ, 2,	/* PCI Express Size */
+		, 23,
+		PXBR, 6,	/* PCI Express BAR [31:26] */
+
+		Offset(0x68),	/* DMIBAR (0:0:0:68) */
+		DIEN, 1,	/* Enable */
+		, 11,
+		DIBR, 20,	/* DMIBAR [31:12] */
+
+		Offset (0x70),	/* ME Base Address */
 		MEBA, 64,
 
-		Offset(0x80),	// PAM0 Register (0:0:0:80)
-		PMLK, 1,		// PAM Lock bit.
-			, 3,
-		PM0H, 2,		// PAM 0, High Nibble
-			, 2,
-
-		Offset(0x81),	// PAM1 Register (0:0:0:81)
-		PM1L, 2,		// PAM1, Low  Nibble
-			, 2,
-		PM1H, 2,		// PAM1, High Nibble
-			, 2,
-
-		Offset(0x82),	// PAM2 Register (0:0:0:82)
-		PM2L, 2,		// PAM2, Low  Nibble
-			, 2,
-		PM2H, 2,		// PAM2, High Nibble
-			, 2,
-
-		Offset(0x83),	// PAM3 Register (0:0:0:83)
-		PM3L, 2,		// PAM3, Low  Nibble
-			, 2,
-		PM3H, 2,		// PAM3, High Nibble
-			, 2,
-
-		Offset(0x84),	// PAM4 Register (0:0:0:84)
-		PM4L, 2,		// PAM4, Low  Nibble
-			, 2,
-		PM4H, 2,		// PAM4, High Nibble
-			, 2,
-
-		Offset(0x85),	// PAM5 Register (0:0:0:85)
-		PM5L, 2,		// PAM5, Low  Nibble
-			, 2,
-		PM5H, 2,		// PAM5, High Nibble
-			, 2,
-
-		Offset(0x86),	// PAM6 Register (0:0:0:86)
-		PM6L, 2,		// PAM6, Low  Nibble
-			, 2,
-		PM6H, 2,		// PAM6, High Nibble
-			, 2,
-
-		Offset (0xa0),	// Top of Used Memory
+		Offset (0xa0),	/* Top of Used Memory */
 		TOM, 64,
 
-		Offset (0xa8),	// Top of Upper Used Memory
+		Offset (0xa8),	/* Top of Upper Used Memory */
 		TUUD, 64,
 
-		Offset (0xbc),	// Top of Low Used Memory
+		Offset (0xbc),	/* Top of Low Used Memory */
 		TLUD, 32,
 	}
 }
 
-// Current Resource Settings
-
 Method (_CRS, 0, Serialized)
 {
-	Name (MCRS, ResourceTemplate()
+	Name (MCRS, ResourceTemplate ()
 	{
 		/* Bus Numbers */
 		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
 				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
 
 		/* IO Region 0 */
-		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				EntireRange,
 				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
 
 		/* PCI Config Space */
 		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
 
 		/* IO Region 1 */
-		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				EntireRange,
 				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
 
 		/* VGA memory (0xa0000-0xbffff) */
@@ -278,13 +230,10 @@ Method (_CRS, 0, Serialized)
 
 	Store (^MCHC.TUUD, Local0)
 
-	If (LLessEqual (Local0, BASE_32GB))
-	{
+	If (LLessEqual (Local0, BASE_32GB)) {
 		Store (BASE_32GB, MMIN)
 		Store (SIZE_16GB, MLEN)
-	}
-	else
-	{
+	} Else {
 		Store (0, MMIN)
 		Store (0, MLEN)
 	}
@@ -300,50 +249,45 @@ Name (PC_L, 0) /* to store PCIe BAR Length */
 Name (DM_B, 0) /* to store DMI BAR */
 
 /* Get MCH BAR */
-Method (GMHB,0,Serialized)
+Method (GMHB, 0, Serialized)
 {
-	if (LEqual (MH_B,0))
-	{
+	If (LEqual (MH_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
 	}
 	Return (MH_B)
 }
 
 /* Get EP BAR */
-Method (GEPB,0,Serialized)
+Method (GEPB, 0, Serialized)
 {
-	if (LEqual (EP_B,0))
-	{
+	If (LEqual (EP_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
 	}
 	Return (EP_B)
 }
 
 /* Get PCIe BAR */
-Method (GPCB,0,Serialized)
+Method (GPCB, 0, Serialized)
 {
-	if (LEqual (PC_B,0))
-	{
+	If (LEqual (PC_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
 	}
 	Return (PC_B)
 }
 
 /* Get PCIe Length */
-Method (GPCL,0,Serialized)
+Method (GPCL, 0, Serialized)
 {
-	if (LEqual (PC_L,0))
-	{
+	If (LEqual (PC_L, 0)) {
 		ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
 	}
 	Return (PC_L)
 }
 
 /* Get DMI BAR */
-Method (GDMB,0,Serialized)
+Method (GDMB, 0, Serialized)
 {
-	if (LEqual (DM_B,0))
-	{
+	If (LEqual (DM_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
 	}
 	Return (DM_B)
@@ -352,10 +296,10 @@ Method (GDMB,0,Serialized)
 /* PCI Device Resource Consumption */
 Device (PDRC)
 {
-	Name (_HID, EISAID("PNP0C02"))
+	Name (_HID, EISAID ("PNP0C02"))
 	Name (_UID, 1)
 
-	Name (BUF0,ResourceTemplate()
+	Name (BUF0, ResourceTemplate ()
 	{
 		/* MCH BAR _BAS will be updated in _CRS below according to
 		 * B0:D0:F0:Reg.48h
@@ -398,8 +342,8 @@ Device (PDRC)
 		/* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
 		Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
 
-		/* Reserve HPET address decode range */
-		Memory32Fixed (ReadWrite, 0, 0, HPET)
+		/* HPET address decode range */
+		Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
 
 		/* Debug Base Address
 		 * Base Address for ACPI debug output memory buffer
@@ -407,28 +351,22 @@ Device (PDRC)
 		Memory32Fixed (ReadWrite, 0, 0, DBAD)
 	})
 
-	// Current Resource Settings
 	Method (_CRS, 0, Serialized)
 	{
 		CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
-		Store (\_SB.PCI0.GMHB(), MBR0)
+		Store (\_SB.PCI0.GMHB (), MBR0)
 
 		CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
-		Store (\_SB.PCI0.GDMB(), DBR0)
+		Store (\_SB.PCI0.GDMB (), DBR0)
 
 		CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
-		Store (\_SB.PCI0.GEPB(), EBR0)
+		Store (\_SB.PCI0.GEPB (), EBR0)
 
 		CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
-		Store (\_SB.PCI0.GPCB(), XBR0)
+		Store (\_SB.PCI0.GPCB (), XBR0)
 
 		CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
-		Store (\_SB.PCI0.GPCL(),  XSZ0)
-
-		CreateDwordField (BUF0, ^HPET._BAS, HBAS)
-		CreateDwordField (BUF0, ^HPET._LEN, HLEN)
-		Store (0xfed00000, HBAS)
-		Store (0x400, HLEN)
+		Store (\_SB.PCI0.GPCL (), XSZ0)
 
 		Return (BUF0)
 	}


From gerrit at coreboot.org  Mon Sep  7 18:42:17 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:17 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: allow
	timer_monotonic_get() in all stages
References: <I8294c74abe09947fb4438bf5c1d0fc5265491694+0@gerrit.coreboot.org>
Message-ID: <I8294c74abe09947fb4438bf5c1d0fc5265491694+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11540

-gerrit

commit 37fa5de61c1751104e26eb6f7e5143ce1fd7055c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Aug 28 01:58:18 2015 -0500

    skylake: allow timer_monotonic_get() in all stages
    
    The timer_monotonic_get() function wasn't being compiled for
    romstage. To simplify the implementation don't keep track of
    partial microsecond ticks and just return the MSR value divided
    by 24 (24MHz clock).
    
    BUG=chrome-os-partner:42115
    BRANCH=None
    TEST=Build and booted glados. Used monotonic timers in romstage
         in subsequent patches.
    
    Change-Id: I8294c74abe09947fb4438bf5c1d0fc5265491694
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6d60ef204fc92c26748ab57d4ff37830cd8dc664
    Original-Change-Id: Ibdb6b9e20b9f2d48ff0f8a8c782f5c1f7ddde4f7
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295237
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/Makefile.inc      |  1 +
 src/soc/intel/skylake/monotonic_timer.c | 27 ++-------------------------
 2 files changed, 3 insertions(+), 25 deletions(-)

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..3bd9823 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -13,6 +13,7 @@ subdirs-y += ../../../cpu/x86/tsc
 romstage-y += flash_controller.c
 romstage-y += gpio.c
 romstage-y += memmap.c
+romstage-y += monotonic_timer.c
 romstage-y += pch.c
 romstage-y += pcr.c
 romstage-y += pei_data.c
diff --git a/src/soc/intel/skylake/monotonic_timer.c b/src/soc/intel/skylake/monotonic_timer.c
index 35ad911..55430ef 100644
--- a/src/soc/intel/skylake/monotonic_timer.c
+++ b/src/soc/intel/skylake/monotonic_timer.c
@@ -23,12 +23,6 @@
 #include <timer.h>
 #include <soc/msr.h>
 
-static struct monotonic_counter {
-	int initialized;
-	struct mono_time time;
-	uint32_t last_value;
-} mono_counter;
-
 static inline uint32_t read_counter_msr(void)
 {
 	/*
@@ -44,23 +38,6 @@ static inline uint32_t read_counter_msr(void)
 
 void timer_monotonic_get(struct mono_time *mt)
 {
-	uint32_t current_tick;
-	uint32_t usecs_elapsed;
-
-	if (!mono_counter.initialized) {
-		mono_counter.last_value = read_counter_msr();
-		mono_counter.initialized = 1;
-	}
-
-	current_tick = read_counter_msr();
-	usecs_elapsed = (current_tick - mono_counter.last_value) / 24;
-
-	/* Update current time and tick values only if a full tick occurred. */
-	if (usecs_elapsed) {
-		mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
-		mono_counter.last_value = current_tick;
-	}
-
-	/* Save result. */
-	*mt = mono_counter.time;
+	/* Always increases. Don't normalize to 0 between stages. */
+	mono_time_set_usecs(mt, read_counter_msr() / 24);
 }


From gerrit at coreboot.org  Mon Sep  7 18:42:20 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:20 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: fix
	eventlog on resume path
References: <I187baa940bb45ef90ab82e67c02f13d8855d364e+0@gerrit.coreboot.org>
Message-ID: <I187baa940bb45ef90ab82e67c02f13d8855d364e+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11541

-gerrit

commit 272ccdb7ac76329e92c3b71e5666c2b2dfe634c9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Aug 28 02:14:48 2015 -0500

    skylake: fix eventlog on resume path
    
    The spi_init() routine needs to be called in all boot paths to allow
    writes to the SPI part. The reason is that the write enable is done
    in spi_init(). Moreover, this is also required for a writing a firmware
    update after a resume.
    
    BUG=chrome-os-partner:42115
    BRANCH=None
    TEST=Built and booted glados. Suspended and resumed. Eventlogs show
         up in resume path.
    
    Change-Id: I187baa940bb45ef90ab82e67c02f13d8855d364e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8813ab227395cfcba46ad4109730a1eb5897e538
    Original-Change-Id: Ida726fc29e6d49cd9af02c4e57125e09f2599c36
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295238
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/flash_controller.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index 549e883..a243eb1 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -457,3 +457,15 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi)
 }
 #endif
 
+#if ENV_RAMSTAGE
+/*
+ * spi_init() needs run unconditionally in every boot (including resume) to
+ * allow write protect to be disabled for eventlog and firmware updates.
+ */
+static void spi_init_cb(void *unused)
+{
+	spi_init();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, spi_init_cb, NULL);
+#endif


From gerrit at coreboot.org  Mon Sep  7 18:42:21 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:21 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: move
	flash_controller.h to the proper place
References: <Ia018c20f97f267b8f7592b2459d10eafe5ec7159+0@gerrit.coreboot.org>
Message-ID: <Ia018c20f97f267b8f7592b2459d10eafe5ec7159+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11542

-gerrit

commit 11c79f01c018c3bef32b2b6770f7f07e725551b4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Aug 27 14:28:35 2015 -0500

    skylake: move flash_controller.h to the proper place
    
    I missed this in code review. This should be under the soc
    directory.
    
    BUG=chrome-os-partner:43522
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: Ia018c20f97f267b8f7592b2459d10eafe5ec7159
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9c081ed6de46605b7d0a72962ac2a041c470b12c
    Original-Change-Id: Ic3938fe5d71bd24a395304cfabe40eff48bc4a40
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295239
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/flash_controller.c           |   2 +-
 src/soc/intel/skylake/include/flash_controller.h   | 176 ---------------------
 .../intel/skylake/include/soc/flash_controller.h   | 176 +++++++++++++++++++++
 src/soc/intel/skylake/romstage/spi.c               |   2 +-
 4 files changed, 178 insertions(+), 178 deletions(-)

diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index a243eb1..dac5df8 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -26,9 +26,9 @@
 #include <bootstate.h>
 #include <delay.h>
 #include <device/pci_ids.h>
-#include <flash_controller.h>
 #include <spi_flash.h>
 #include <spi-generic.h>
+#include <soc/flash_controller.h>
 #include <soc/pci_devs.h>
 #include <soc/spi.h>
 
diff --git a/src/soc/intel/skylake/include/flash_controller.h b/src/soc/intel/skylake/include/flash_controller.h
deleted file mode 100644
index c79d265..0000000
--- a/src/soc/intel/skylake/include/flash_controller.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.,
- */
-
-#ifndef _FLASH_CONTROLLER__H_
-#define _FLASH_CONTROLLER__H_
-
-#include <rules.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <spi_flash.h>
-
-int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len);
-int pch_hwseq_write(struct spi_flash *flash,
-			   u32 addr, size_t len, const void *buf);
-
-int pch_hwseq_read(struct spi_flash *flash,
-			  u32 addr, size_t len, void *buf);
-int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg);
-
-
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
-static u8 readb_(const void *addr)
-{
-	u8 v = read8(addr);
-	printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
-	return v;
-}
-
-static u16 readw_(const void *addr)
-{
-	u16 v = read16(addr);
-	printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
-	return v;
-}
-
-static u32 readl_(const void *addr)
-{
-	u32 v = read32(addr);
-	printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
-	return v;
-}
-
-static void writeb_(u8 b, void *addr)
-{
-	write8(addr, b);
-	printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
-}
-
-static void writew_(u16 b, void *addr)
-{
-	write16(addr, b);
-	printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
-}
-
-static void writel_(u32 b, void *addr)
-{
-	write32(addr, b);
-	printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
-}
-
-#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
-
-#define readb_(a) read8(a)
-#define readw_(a) read16(a)
-#define readl_(a) read32(a)
-#define writeb_(val, addr) write8(addr, val)
-#define writew_(val, addr) write16(addr, val)
-#define writel_(val, addr) write32(addr, val)
-
-#endif  /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
-
-#if ENV_SMM
-#define pci_read_config_byte(dev, reg, targ)\
-	(*(targ) = pci_read_config8(dev, reg))
-#define pci_read_config_word(dev, reg, targ)\
-	(*(targ) = pci_read_config16(dev, reg))
-#define pci_read_config_dword(dev, reg, targ)\
-	(*(targ) = pci_read_config32(dev, reg))
-#define pci_write_config_byte(dev, reg, val)\
-	pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
-	pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
-	pci_write_config32(dev, reg, val)
-#else /* !ENV_SMM */
-#include <device/device.h>
-#include <device/pci.h>
-#define pci_read_config_byte(dev, reg, targ)\
-	(*(targ) = pci_read_config8(dev, reg))
-#define pci_read_config_word(dev, reg, targ)\
-	(*(targ) = pci_read_config16(dev, reg))
-#define pci_read_config_dword(dev, reg, targ)\
-	(*(targ) = pci_read_config32(dev, reg))
-#define pci_write_config_byte(dev, reg, val)\
-	pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
-	pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
-	pci_write_config32(dev, reg, val)
-#endif /* ENV_SMM */
-
-#define HSFC_FCYCLE		(0x3 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_WR		(0x2 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_RS		(0x8 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FDBC		(0x3f << HSFC_FDBC_SHIFT)
-
-#define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */
-
-#define WPSR_MASK_SRP0_BIT 0x80
-
-typedef struct pch_spi_regs {
-	uint32_t bfpr;
-	uint16_t hsfs;
-	uint16_t hsfc;
-	uint32_t faddr;
-	uint32_t _reserved0;
-	uint32_t fdata[16];
-	uint32_t frap;
-	uint32_t freg[6];
-	uint32_t _reserved1[6];
-	uint32_t pr[5];
-	uint32_t gpr0;
-	uint32_t _reserved2;
-	uint32_t _reserved3;
-	uint16_t preop;
-	uint16_t optype;
-	uint8_t opmenu[8];
-	uint32_t bbar;
-	uint32_t  fdoc;
-	uint32_t fdod;
-	uint8_t _reserved4[8];
-	uint32_t afc;
-	uint32_t lvscc;
-	uint32_t uvscc;
-	uint8_t _reserved5[4];
-	uint32_t fpb;
-	uint8_t _reserved6[28];
-	uint32_t srdl;
-	uint32_t srdc;
-	uint32_t srd;
-} __attribute__((packed)) pch_spi_regs;
-
-enum {
-	HSFS_FDONE =		0x0001,
-	HSFS_FCERR =		0x0002,
-	HSFS_FDV =		0x4000,
-};
-
-enum {
-	HSFC_FGO =		0x0001,
-	HSFC_FCYCLE_SHIFT =	1,
-	HSFC_FDBC_SHIFT =	8,
-};
-#endif	/* _FLASH_CONTROLLER__H_ */
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
new file mode 100644
index 0000000..25cbce9
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -0,0 +1,176 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.,
+ */
+
+#ifndef _SOC_FLASH_CONTROLLER__H_
+#define _SOC_FLASH_CONTROLLER__H_
+
+#include <rules.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <spi_flash.h>
+
+int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len);
+int pch_hwseq_write(struct spi_flash *flash,
+			   u32 addr, size_t len, const void *buf);
+
+int pch_hwseq_read(struct spi_flash *flash,
+			  u32 addr, size_t len, void *buf);
+int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg);
+
+
+#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+static u8 readb_(const void *addr)
+{
+	u8 v = read8(addr);
+	printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
+	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	return v;
+}
+
+static u16 readw_(const void *addr)
+{
+	u16 v = read16(addr);
+	printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
+	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	return v;
+}
+
+static u32 readl_(const void *addr)
+{
+	u32 v = read32(addr);
+	printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
+	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	return v;
+}
+
+static void writeb_(u8 b, void *addr)
+{
+	write8(addr, b);
+	printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
+	       b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+static void writew_(u16 b, void *addr)
+{
+	write16(addr, b);
+	printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
+	       b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+static void writel_(u32 b, void *addr)
+{
+	write32(addr, b);
+	printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
+	       b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
+
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
+
+#endif  /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
+
+#if ENV_SMM
+#define pci_read_config_byte(dev, reg, targ)\
+	(*(targ) = pci_read_config8(dev, reg))
+#define pci_read_config_word(dev, reg, targ)\
+	(*(targ) = pci_read_config16(dev, reg))
+#define pci_read_config_dword(dev, reg, targ)\
+	(*(targ) = pci_read_config32(dev, reg))
+#define pci_write_config_byte(dev, reg, val)\
+	pci_write_config8(dev, reg, val)
+#define pci_write_config_word(dev, reg, val)\
+	pci_write_config16(dev, reg, val)
+#define pci_write_config_dword(dev, reg, val)\
+	pci_write_config32(dev, reg, val)
+#else /* !ENV_SMM */
+#include <device/device.h>
+#include <device/pci.h>
+#define pci_read_config_byte(dev, reg, targ)\
+	(*(targ) = pci_read_config8(dev, reg))
+#define pci_read_config_word(dev, reg, targ)\
+	(*(targ) = pci_read_config16(dev, reg))
+#define pci_read_config_dword(dev, reg, targ)\
+	(*(targ) = pci_read_config32(dev, reg))
+#define pci_write_config_byte(dev, reg, val)\
+	pci_write_config8(dev, reg, val)
+#define pci_write_config_word(dev, reg, val)\
+	pci_write_config16(dev, reg, val)
+#define pci_write_config_dword(dev, reg, val)\
+	pci_write_config32(dev, reg, val)
+#endif /* ENV_SMM */
+
+#define HSFC_FCYCLE		(0x3 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_WR		(0x2 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_RS		(0x8 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FDBC		(0x3f << HSFC_FDBC_SHIFT)
+
+#define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */
+
+#define WPSR_MASK_SRP0_BIT 0x80
+
+typedef struct pch_spi_regs {
+	uint32_t bfpr;
+	uint16_t hsfs;
+	uint16_t hsfc;
+	uint32_t faddr;
+	uint32_t _reserved0;
+	uint32_t fdata[16];
+	uint32_t frap;
+	uint32_t freg[6];
+	uint32_t _reserved1[6];
+	uint32_t pr[5];
+	uint32_t gpr0;
+	uint32_t _reserved2;
+	uint32_t _reserved3;
+	uint16_t preop;
+	uint16_t optype;
+	uint8_t opmenu[8];
+	uint32_t bbar;
+	uint32_t  fdoc;
+	uint32_t fdod;
+	uint8_t _reserved4[8];
+	uint32_t afc;
+	uint32_t lvscc;
+	uint32_t uvscc;
+	uint8_t _reserved5[4];
+	uint32_t fpb;
+	uint8_t _reserved6[28];
+	uint32_t srdl;
+	uint32_t srdc;
+	uint32_t srd;
+} __attribute__((packed)) pch_spi_regs;
+
+enum {
+	HSFS_FDONE =		0x0001,
+	HSFS_FCERR =		0x0002,
+	HSFS_FDV =		0x4000,
+};
+
+enum {
+	HSFC_FGO =		0x0001,
+	HSFC_FCYCLE_SHIFT =	1,
+	HSFC_FDBC_SHIFT =	8,
+};
+#endif	/* _SOC_FLASH_CONTROLLER__H_ */
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
index be6db41..2194d21 100644
--- a/src/soc/intel/skylake/romstage/spi.c
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -18,7 +18,7 @@
  * Foundation, Inc.
  */
 
-#include <flash_controller.h>
+#include <soc/flash_controller.h>
 #include <soc/romstage.h>
 
 int early_spi_read(u32 offset, u32 size, u8 *buffer)


From gerrit at coreboot.org  Mon Sep  7 18:42:23 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:23 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake:
	refactor flash_controller code
References: <I0ddd42f0744cf8f88da832d7d715663238209a71+0@gerrit.coreboot.org>
Message-ID: <I0ddd42f0744cf8f88da832d7d715663238209a71+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11543

-gerrit

commit b1972b7daaf5714100b10211b0c04db064730b0b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Aug 27 14:30:22 2015 -0500

    skylake: refactor flash_controller code
    
    There's no need to add any typedefs nor guard code with
    ENV_ROMSTAGE. The linker will garbage collect unused functions.
    Additionally there were a few errors in the code including
    the operation mask wasn't wide enough to clear out old operations
    as well as component size decoding was incorrect.
    
    The big difference in the code flow is that the operation
    setup is now in one place. The stopwatch API is also used in
    order to not open code time calculations.
    
    BUG=chrome-os-partner:42115
    BUG=chrome-os-partner:43522
    BRANCH=None
    TEST=Built and booted. Suspended and resumed. event log is populated
         for all.
    
    Change-Id: I0ddd42f0744cf8f88da832d7d715663238209a71
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9893fe309104c05edfb158afda6bb029801c0489
    Original-Change-Id: I6468f5b9b4a73885b69ebd916861dd2e8e3746b6
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295980
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/flash_controller.c           | 349 +++++++++------------
 .../intel/skylake/include/soc/flash_controller.h   |  17 +-
 2 files changed, 158 insertions(+), 208 deletions(-)

diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index dac5df8..26d8a1f 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -24,73 +24,135 @@
 #include <stdlib.h>
 #include <string.h>
 #include <bootstate.h>
-#include <delay.h>
-#include <device/pci_ids.h>
 #include <spi_flash.h>
-#include <spi-generic.h>
+#include <timer.h>
 #include <soc/flash_controller.h>
 #include <soc/pci_devs.h>
 #include <soc/spi.h>
 
-#if !(ENV_ROMSTAGE)
-typedef struct spi_slave pch_spi_slave;
-static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi);
-#endif
+static inline uint16_t spi_read_hsfs(pch_spi_regs * const regs)
+{
+	return readw_(&regs->hsfs);
+}
 
-unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+static inline void spi_clear_status(pch_spi_regs * const regs)
 {
-	pch_spi_regs *spi_bar;
+	/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
+	writew_(spi_read_hsfs(regs), &regs->hsfs);
+}
 
-	spi_bar = get_spi_bar();
-	return min(sizeof(spi_bar->fdata), buf_len);
+static inline uint16_t spi_read_hsfc(pch_spi_regs * const regs)
+{
+	return readw_(&regs->hsfc);
 }
 
-#if !(ENV_ROMSTAGE)
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
+static inline uint32_t spi_read_faddr(pch_spi_regs * const regs)
 {
-	pch_spi_slave *slave = malloc(sizeof(*slave));
+	return readl_(&regs->faddr) & SPIBAR_FADDR_MASK;
+}
 
-	if (!slave) {
-		printk(BIOS_DEBUG, "PCH SPI: Bad allocation\n");
-		return NULL;
+/*
+ * Polls for Cycle Done Status, Flash Cycle Error
+ * Resets all error flags in HSFS.
+ * Returns 0 if the cycle completes successfully without errors within
+ * timeout, 1 on errors.
+ */
+static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms,
+				size_t len)
+{
+	uint16_t hsfs;
+	uint16_t hsfc;
+	uint32_t addr;
+	struct stopwatch sw;
+	int timeout = 0;
+
+	stopwatch_init_msecs_expire(&sw, timeout_ms);
+
+	while (!(timeout = stopwatch_expired(&sw))) {
+		hsfs = spi_read_hsfs(regs);
+
+		if ((hsfs & (HSFS_FDONE | HSFS_FCERR)))
+			break;
 	}
 
-	memset(slave, 0, sizeof(*slave));
+	if (timeout) {
+		addr = spi_read_faddr(regs);
+		hsfc = spi_read_hsfc(regs);
+		printk(BIOS_ERR, "%ld ms Transaction timeout between offset "
+			"0x%08x and 0x%08x (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n",
+			stopwatch_duration_msecs(&sw), addr, addr + len - 1,
+			addr, len - 1, hsfc, hsfs);
+		return 1;
+	}
 
-	slave->bus = bus;
-	slave->cs = cs;
-	slave->force_programmer_specific = 1;
-	slave->programmer_specific_probe = spi_flash_hwseq_probe;
+	if (hsfs & HSFS_FCERR) {
+		addr = spi_read_faddr(regs);
+		hsfc = spi_read_hsfc(regs);
+		printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
+		       "0x%08x (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n",
+		       addr, addr + len - 1, addr, len - 1,
+		       hsfc, hsfs);
+		return 1;
+	}
 
-	return slave;
+	return 0;
 }
-#endif
 
-static u32 spi_get_flash_size(pch_spi_regs *spi_bar)
+/* Start operation returning 0 on success, non-zero on error or timeout. */
+static int spi_do_operation(int op, size_t offset, size_t size, int timeout_ms)
+{
+	uint16_t hsfc;
+	pch_spi_regs * const regs = get_spi_bar();
+
+	/* Clear status prior to operation. */
+	spi_clear_status(regs);
+
+	/* Set the FADDR */
+	writel_(offset & SPIBAR_FADDR_MASK, &regs->faddr);
+
+	hsfc = readw_(&regs->hsfc);
+	/* Clear then set the correct op. */
+	hsfc &= ~HSFC_FCYCLE_MASK;
+	hsfc |= op;
+	/* Set the size field */
+	hsfc &= ~HSFC_FDBC_MASK;
+	/* Check for sizes of confirming operations. */
+	if (size && size <= SPI_FDATA_BYTES)
+		hsfc |= ((size - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC_MASK;
+	/* start operation */
+	hsfc |= HSFC_FGO;
+	writew_(hsfc, &regs->hsfc);
+
+	return wait_for_completion(regs, timeout_ms, size);
+}
+
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+	return min(SPI_FDATA_BYTES, buf_len);
+}
+
+static size_t spi_get_flash_size(pch_spi_regs *spi_bar)
 {
 	uint32_t flcomp;
-	u32 size;
+	size_t size;
 
 	writel_(SPIBAR_FDOC_COMPONENT, &spi_bar->fdoc);
 	flcomp = readl_(&spi_bar->fdod);
-	printk(BIOS_DEBUG, "flcomp = %x\n", flcomp);
 
 	switch (flcomp & FLCOMP_C0DEN_MASK) {
 	case FLCOMP_C0DEN_8MB:
-		size = 0x100000;
+		size = 8*MiB;
 		break;
 	case FLCOMP_C0DEN_16MB:
-		size = 0x1000000;
+		size = 16*MiB;
 		break;
 	case FLCOMP_C0DEN_32MB:
-		size = 0x10000000;
+		size = 32*MiB;
 		break;
 	default:
-		size = 0x1000000;
+		size = 16*MiB;
 	}
 
-	printk(BIOS_DEBUG, "flash size 0x%x bytes\n", size);
-
 	return size;
 }
 
@@ -105,16 +167,6 @@ void spi_init(void)
 {
 	uint8_t bios_cntl;
 	device_t dev = PCH_DEV_SPI;
-	pch_spi_regs *spi_bar;
-	uint16_t hsfs;
-
-	/* Root Complex Register Block */
-	spi_bar = get_spi_bar();
-	hsfs = readw_(&spi_bar->hsfs);
-	if (hsfs & HSFS_FDV) {
-		/* Select Flash Descriptor Section Index to 1 */
-		writel_(SPIBAR_FDOC_FDSI_1, &spi_bar->fdoc);
-	}
 
 	/* Disable the BIOS write protect so write commands are allowed. */
 	pci_read_config_byte(dev, SPIBAR_BIOS_CNTL, &bios_cntl);
@@ -134,64 +186,11 @@ void spi_release_bus(struct spi_slave *slave)
 	/* Handled by PCH automatically. */
 }
 
-static void pch_hwseq_set_addr(uint32_t addr, pch_spi_regs *spi_bar)
-{
-	uint32_t addr_old = readl_(&spi_bar->faddr) & ~SPIBAR_FADDR_MASK;
-	writel_((addr & SPIBAR_FADDR_MASK) | addr_old, &spi_bar->faddr);
-}
-
-/*
- * Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
- * Resets all error flags in HSFS.
- * Returns 0 if the cycle completes successfully without errors within
- * timeout us, 1 on errors.
- */
-static int pch_hwseq_wait_for_cycle_complete(unsigned int timeout,
-			unsigned int len, pch_spi_regs *spi_bar)
-{
-	uint16_t hsfs;
-	uint32_t addr;
-
-	timeout /= 8; /* scale timeout duration to counter */
-	while ((((hsfs = readw_(&spi_bar->hsfs)) &
-		 (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) {
-		udelay(8);
-	}
-	writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs);
-
-	if (!timeout) {
-		uint16_t hsfc;
-		addr = readl_(&spi_bar->faddr) & SPIBAR_FADDR_MASK;
-		hsfc = readw_(&spi_bar->hsfc);
-		printk(BIOS_ERR, "Transaction timeout between offset 0x%08x \
-			and 0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
-			addr, addr + len - 1, addr, len - 1,
-			hsfc, hsfs);
-		return 1;
-	}
-
-	if (hsfs & HSFS_FCERR) {
-		uint16_t hsfc;
-		addr = readl_(&spi_bar->faddr) & SPIBAR_FADDR_MASK;
-		hsfc = readw_(&spi_bar->hsfc);
-		printk(BIOS_ERR, "Transaction error between offset 0x%08x and \
-		       0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
-		       addr, addr + len - 1, addr, len - 1,
-		       hsfc, hsfs);
-		return 1;
-	}
-	return 0;
-}
-
 int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
 {
 	u32 start, end, erase_size;
 	int ret;
-	uint16_t hsfc;
-	uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
-	pch_spi_regs *spi_bar;
 
-	spi_bar = get_spi_bar();
 	erase_size = flash->sector_size;
 	if (offset % erase_size || len % erase_size) {
 		printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
@@ -209,27 +208,13 @@ int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
 	end = start + len;
 
 	while (offset < end) {
-		/*
-		 * Make sure FDONE, FCERR, AEL are
-		 * cleared by writing 1 to them.
-		 */
-		writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs);
-
-		pch_hwseq_set_addr(offset, spi_bar);
-
-		offset += erase_size;
-
-		hsfc = readw_(&spi_bar->hsfc);
-		hsfc &= ~HSFC_FCYCLE; /* clear operation */
-		hsfc |= HSFC_FCYCLE; /* set erase operation */
-		hsfc |= HSFC_FGO; /* start */
-		writew_(hsfc, &spi_bar->hsfc);
-		if (pch_hwseq_wait_for_cycle_complete(timeout, len, spi_bar)) {
-			printk(BIOS_ERR, "SF: Erase failed at %x\n",
-				offset - erase_size);
+		if (spi_do_operation(HSFC_FCYCLE_4KE, offset, 0, 5000)) {
+			printk(BIOS_ERR, "SF: Erase failed at %x\n", offset);
 			ret = -1;
 			goto out;
 		}
+
+		offset += erase_size;
 	}
 
 	printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n",
@@ -240,11 +225,14 @@ out:
 	return ret;
 }
 
-static void pch_read_data(uint8_t *data, int len, pch_spi_regs *spi_bar)
+static void pch_read_data(uint8_t *data, int len)
 {
 	int i;
+	pch_spi_regs *spi_bar;
 	uint32_t temp32 = 0;
 
+	spi_bar = get_spi_bar();
+
 	for (i = 0; i < len; i++) {
 		if ((i % 4) == 0)
 			temp32 = readl_((uint8_t *)spi_bar->fdata + i);
@@ -252,16 +240,12 @@ static void pch_read_data(uint8_t *data, int len, pch_spi_regs *spi_bar)
 		data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
 	}
 }
-int pch_hwseq_read(struct spi_flash *flash,
-			  u32 addr, size_t len, void *buf)
+
+int pch_hwseq_read(struct spi_flash *flash, u32 addr, size_t len, void *buf)
 {
-	uint16_t hsfc;
-	uint16_t timeout = 100 * 60;  /* 6 mili secs timeout */
 	uint8_t block_len;
-	pch_spi_regs *spi_bar;
 
-	spi_bar = get_spi_bar();
-	if (addr + len > spi_get_flash_size(spi_bar)) {
+	if (addr + len > spi_get_flash_size(get_spi_bar())) {
 		printk(BIOS_ERR,
 			"Attempt to read %x-%x which is out of chip\n",
 			(unsigned) addr,
@@ -269,26 +253,18 @@ int pch_hwseq_read(struct spi_flash *flash,
 		return -1;
 	}
 
-	/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
-	writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs);
-
 	while (len > 0) {
-		block_len = min(len, sizeof(spi_bar->fdata));
+		const int timeout_ms = 6;
+
+		block_len = min(len, SPI_FDATA_BYTES);
 		if (block_len > (~addr & 0xff))
 			block_len = (~addr & 0xff) + 1;
-		pch_hwseq_set_addr(addr, spi_bar);
-		hsfc = readw_(&spi_bar->hsfc);
-		hsfc &= ~HSFC_FCYCLE; /* set read operation */
-		hsfc &= ~HSFC_FDBC; /* clear byte count */
-		/* set byte count */
-		hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC);
-		hsfc |= HSFC_FGO; /* start */
-		writew_(hsfc, &spi_bar->hsfc);
-
-		if (pch_hwseq_wait_for_cycle_complete
-			(timeout, block_len, spi_bar))
+
+		if (spi_do_operation(HSFC_FCYCLE_RD, addr, block_len,
+					timeout_ms))
 			return -1;
-		pch_read_data(buf, block_len, spi_bar);
+
+		pch_read_data(buf, block_len);
 		addr += block_len;
 		buf += block_len;
 		len -= block_len;
@@ -329,8 +305,6 @@ static void pch_fill_data(const uint8_t *data, int len)
 int pch_hwseq_write(struct spi_flash *flash,
 			   u32 addr, size_t len, const void *buf)
 {
-	uint16_t hsfc;
-	uint16_t timeout = 100 * 60;   /* 6 mili secs  timeout */
 	uint8_t block_len;
 	uint32_t start = addr;
 	pch_spi_regs *spi_bar;
@@ -344,28 +318,16 @@ int pch_hwseq_write(struct spi_flash *flash,
 		return -1;
 	}
 
-	/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
-	writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs);
-
 	while (len > 0) {
+		const int timeout_ms = 6;
+
 		block_len = min(len, sizeof(spi_bar->fdata));
 		if (block_len > (~addr & 0xff))
 			block_len = (~addr & 0xff) + 1;
 
-		pch_hwseq_set_addr(addr, spi_bar);
-
 		pch_fill_data(buf, block_len);
-		hsfc = readw_(&spi_bar->hsfc);
-		hsfc &= ~HSFC_FCYCLE; /* clear operation */
-		hsfc |= HSFC_FCYCLE_WR; /* set write operation */
-		hsfc &= ~HSFC_FDBC; /* clear byte count */
-		/* set byte count */
-		hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC);
-		hsfc |= HSFC_FGO; /* start */
-		writew_(hsfc, &spi_bar->hsfc);
-
-		if (pch_hwseq_wait_for_cycle_complete
-			(timeout, block_len, spi_bar)) {
+		if (spi_do_operation(HSFC_FCYCLE_WR, addr, block_len,
+					timeout_ms)) {
 			printk(BIOS_ERR, "SF: write failure at %x\n", addr);
 			return -1;
 		}
@@ -380,44 +342,21 @@ int pch_hwseq_write(struct spi_flash *flash,
 
 int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg)
 {
-	uint16_t hsfc;
-	uint16_t timeout = 100 * 60;   /* 6 mili secs timeout */
-	uint8_t block_len = SPI_READ_STATUS_LENGTH;
-	pch_spi_regs *spi_bar;
+	size_t block_len = SPI_READ_STATUS_LENGTH;
+	const int timeout_ms = 6;
 
-	spi_bar = get_spi_bar();
-	/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
-	writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs);
-
-	hsfc = readw_(&spi_bar->hsfc);
-	hsfc &= ~HSFC_FCYCLE; /* set read operation */
-	/* read status register */
-	hsfc |= HSFC_FCYCLE_RS;
-	hsfc &= ~HSFC_FDBC; /* clear byte count */
-	/* set byte count */
-	hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC);
-	hsfc |= HSFC_FGO; /* start */
-	writew_(hsfc, &spi_bar->hsfc);
-
-	if (pch_hwseq_wait_for_cycle_complete(timeout,
-			block_len, spi_bar))
+	if (spi_do_operation(HSFC_FCYCLE_RS, 0, block_len, timeout_ms))
 		return -1;
-	pch_read_data(reg, block_len, spi_bar);
-	/* clear read status register */
-	writew_(readw_(&spi_bar->hsfc) &
-			~HSFC_FCYCLE_RS, &spi_bar->hsfc);
+
+	pch_read_data(reg, block_len);
 
 	return 0;
 }
 
-#if !(ENV_ROMSTAGE)
 static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi)
 {
-	struct spi_flash *flash = NULL;
-	u32 berase;
-	pch_spi_regs *spi_bar;
+	struct spi_flash *flash;
 
-	spi_bar = get_spi_bar();
 	flash = malloc(sizeof(*flash));
 	if (!flash) {
 		printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
@@ -431,31 +370,33 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi)
 	flash->erase = pch_hwseq_erase;
 	flash->read = pch_hwseq_read;
 	flash->status = pch_hwseq_read_status;
-	pch_hwseq_set_addr(0, spi_bar);
 
-	berase = ((readw_(&spi_bar->hsfs)) >> SPIBAR_HSFS_BERASE_OFFSET) &
-		  SPIBAR_HSFS_BERASE_MASK;
+	/* The hardware sequencing supports 4KiB or 64KiB erase. Use 4KiB. */
+	flash->sector_size = 4*KiB;
 
-	switch (berase) {
-	case 0:
-		flash->sector_size = 256;
-		break;
-	case 1:
-		flash->sector_size = 4096;
-		break;
-	case 2:
-		flash->sector_size = 8192;
-		break;
-	case 3:
-		flash->sector_size = 65536;
-		break;
+	flash->size = spi_get_flash_size(get_spi_bar());
+
+	return flash;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
+{
+	struct spi_slave *slave = malloc(sizeof(*slave));
+
+	if (!slave) {
+		printk(BIOS_DEBUG, "PCH SPI: Bad allocation\n");
+		return NULL;
 	}
 
-	flash->size = spi_get_flash_size(spi_bar);
+	memset(slave, 0, sizeof(*slave));
+
+	slave->bus = bus;
+	slave->cs = cs;
+	slave->force_programmer_specific = 1;
+	slave->programmer_specific_probe = spi_flash_hwseq_probe;
 
-	return flash;
+	return slave;
 }
-#endif
 
 #if ENV_RAMSTAGE
 /*
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index 25cbce9..91693e3 100644
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -121,22 +121,31 @@ static void writel_(u32 b, void *addr)
 	pci_write_config32(dev, reg, val)
 #endif /* ENV_SMM */
 
-#define HSFC_FCYCLE		(0x3 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_MASK	(0xf << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_RD		(0x0 << HSFC_FCYCLE_SHIFT)
 #define HSFC_FCYCLE_WR		(0x2 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_4KE		(0x3 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_64KE	(0x4 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_SFDP	(0x5 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_JEDECID	(0x6 << HSFC_FCYCLE_SHIFT)
+#define HSFC_FCYCLE_WS		(0x7 << HSFC_FCYCLE_SHIFT)
 #define HSFC_FCYCLE_RS		(0x8 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FDBC		(0x3f << HSFC_FDBC_SHIFT)
+#define HSFC_FDBC_MASK		(0x3f << HSFC_FDBC_SHIFT)
 
 #define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */
 
 #define WPSR_MASK_SRP0_BIT 0x80
 
+#define SPI_FDATA_REGS 16
+#define SPI_FDATA_BYTES (SPI_FDATA_REGS * sizeof(uint32_t))
+
 typedef struct pch_spi_regs {
 	uint32_t bfpr;
 	uint16_t hsfs;
 	uint16_t hsfc;
 	uint32_t faddr;
-	uint32_t _reserved0;
-	uint32_t fdata[16];
+	uint32_t dlock;
+	uint32_t fdata[SPI_FDATA_REGS];
 	uint32_t frap;
 	uint32_t freg[6];
 	uint32_t _reserved1[6];


From gerrit at coreboot.org  Mon Sep  7 18:42:25 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:25 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: Remove
	dead code
References: <I3d457a196d12d03340bceb444d1d6c95afef13df+0@gerrit.coreboot.org>
Message-ID: <I3d457a196d12d03340bceb444d1d6c95afef13df+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11544

-gerrit

commit c139a3472626ae654862b32ad6c75f275696412e
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Thu Aug 20 19:04:31 2015 -0700

    skylake: Remove dead code
    
    Remove dead code not called by any part of coreboot.
    
    BRANCH=none
    BUG=None
    TEST=Build and run on skylake
    
    Change-Id: I3d457a196d12d03340bceb444d1d6c95afef13df
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 58ea135813afeef773f37023fda58f36d544beef
    Original-Change-Id: Id8f4591f20d41f875348c6583618bbcaaf9d9a3a
    Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/294953
    Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Tested-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/include/soc/romstage.h |  1 -
 src/soc/intel/skylake/romstage/spi.c         | 20 --------------------
 2 files changed, 21 deletions(-)

diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index f030301..d1c846b 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -33,7 +33,6 @@ void intel_early_me_status(void);
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
 
-int early_spi_read(u32 offset, u32 size, u8 *buffer);
 int early_spi_read_wpsr(u8 *sr);
 void mainboard_fill_spd_data(struct pei_data *pei_data);
 
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
index 2194d21..41a144b 100644
--- a/src/soc/intel/skylake/romstage/spi.c
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -21,26 +21,6 @@
 #include <soc/flash_controller.h>
 #include <soc/romstage.h>
 
-int early_spi_read(u32 offset, u32 size, u8 *buffer)
-{
-	u32 current = 0;
-
-	spi_init();
-	while (size > 0) {
-		u8 count = (size < 64) ? size : 64;
-		/* sending NULL for spiflash struct parameter since we are not
-		 * calling HWSEQ read() call via Probe.
-		 */
-		if (pch_hwseq_read(NULL, offset + current, count,
-				   buffer + current) != 0)
-			return -1;
-		size -= count;
-		current += count;
-	}
-
-	return 0;
-}
-
 /*
  * Minimal set of commands to read WPSR from SPI.
  * Returns 0 on success, < 0 on failure.


From gerrit at coreboot.org  Mon Sep  7 18:42:26 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:26 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: FSP: Pass FSP
	image base address to find_fsp
References: <Iac43c8aac8491390479af551765b514ca919928a+0@gerrit.coreboot.org>
Message-ID: <Iac43c8aac8491390479af551765b514ca919928a+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11545

-gerrit

commit fc61046cfaaf5ec36bb89ae3a068207b876285cd
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Wed Aug 26 14:58:29 2015 -0700

    FSP: Pass FSP image base address to find_fsp
    
    Add a parameter to find_fsp which is the image base address.  Adjust the
    fake stack in cache_as_ram.inc to pass in the read-only FSP image base
    address.  In fsp_notify, pass in the read-only FSP image base address
    when the FSP header pointer is NULL.  In find_fsp, validate the FSP
    binary image starting from the specified image base address.
    
    BRANCH=none
    BUG=None
    TEST=Build and run on Skylake
    
    Change-Id: Iac43c8aac8491390479af551765b514ca919928a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95
    Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e
    Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295593
    Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Tested-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp1_1/cache_as_ram.inc | 1 +
 src/drivers/intel/fsp1_1/fsp_util.c       | 8 ++++----
 src/drivers/intel/fsp1_1/fsp_util.h       | 2 +-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 6af30ce..d4df67b 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -342,6 +342,7 @@ halt3:
 	.align 4
 fake_fsp_stack:
 	.long	find_fsp_ret
+	.long	CONFIG_FSP_LOC		/* FSP base address */
 
 CAR_init_params:
 	.long	CONFIG_CPU_MICROCODE_CBFS_LOC		/* Microcode Location */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index bce4337..f699569 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -25,7 +25,7 @@
 #include <timestamp.h>
 
 /* Locate the FSP binary in the coreboot filesystem */
-FSP_INFO_HEADER *find_fsp(void)
+FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address)
 {
 	union {
 		EFI_FFS_FILE_HEADER *ffh;
@@ -40,7 +40,7 @@ FSP_INFO_HEADER *find_fsp(void)
 
 	for (;;) {
 		/* Get the FSP binary base address in CBFS */
-		fsp_ptr.u8 = (u8 *)CONFIG_FSP_LOC;
+		fsp_ptr.u32 = fsp_base_address;
 
 		/* Check the FV signature, _FVH */
 		if (fsp_ptr.fvh->Signature != 0x4856465F) {
@@ -74,7 +74,7 @@ FSP_INFO_HEADER *find_fsp(void)
 		fsp_ptr.u8 += sizeof(EFI_RAW_SECTION);
 
 		/* Verify that the FSP base address.*/
-		if (fsp_ptr.fih->ImageBase != CONFIG_FSP_LOC) {
+		if (fsp_ptr.fih->ImageBase != fsp_base_address) {
 			fsp_ptr.u8 = (u8 *)ERROR_IMAGEBASE_MISMATCH;
 			break;
 		}
@@ -143,7 +143,7 @@ void fsp_notify(u32 phase)
 
 	fsp_header_ptr = fsp_get_fih();
 	if (fsp_header_ptr == NULL) {
-		fsp_header_ptr = (void *)find_fsp();
+		fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC);
 		if ((u32)fsp_header_ptr < 0xff) {
 			/* output something in case there is no serial */
 			post_code(0x4F);
diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h
index 8f6f77a..51ecb98 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.h
+++ b/src/drivers/intel/fsp1_1/fsp_util.h
@@ -42,7 +42,7 @@
 #include <soc/chipset_fsp_util.h>
 
 /* find_fsp() should only be called from assembly code. */
-FSP_INFO_HEADER *find_fsp(void);
+FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
 /* Set FSP's runtime information. */
 void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
 /* Use a new FSP_INFO_HEADER at runtime. */


From gerrit at coreboot.org  Mon Sep  7 18:42:28 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:28 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: braswell: acpi:
	Allow DPTF thresholds to be defined at board-level
References: <Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0+0@gerrit.coreboot.org>
Message-ID: <Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11546

-gerrit

commit 142849ef81a8268b5cd8bf11acfb7ef5b0926029
Author: Shawn Nematbakhsh <shawnn at chromium.org>
Date:   Tue Aug 25 18:03:31 2015 -0700

    braswell: acpi: Allow DPTF thresholds to be defined at board-level
    
    Similar to Skylake, allow braswell mainboards to override the default
    DPTF thresholds.
    
    BUG=chrome-os-partner:43884
    TEST=Build for Strago
    BRANCH=Strago
    
    Change-Id: Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 799a7006e8fcacfea8e8e0de5c99c3ce3c4ac34f
    Original-Signed-off-by: Shawn Nematbakhsh <shawnn at chromium.org>
    Original-Change-Id: If69627163237674a28fb8a26b4ce1886e5dbfc17
    Original-Reviewed-on: https://chromium-review.googlesource.com/296033
    Original-Commit-Ready: Shawn N <shawnn at chromium.org>
    Original-Tested-by: Shawn N <shawnn at chromium.org>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/braswell/acpi/cpu.asl      | 11 ------
 src/soc/intel/braswell/acpi/dptf/cpu.asl | 63 +++++++++++++++++++++++++-------
 2 files changed, 49 insertions(+), 25 deletions(-)

diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl
index 0ae51f2..c9cb83b 100644
--- a/src/soc/intel/braswell/acpi/cpu.asl
+++ b/src/soc/intel/braswell/acpi/cpu.asl
@@ -18,17 +18,6 @@
  * Foundation, Inc.
  */
 
-/* CPU */
-#define DPTF_CPU_PASSIVE	80
-#define DPTF_CPU_CRITICAL	90
-#define DPTF_CPU_PASSIVE	80
-#define DPTF_CPU_CRITICAL	90
-#define DPTF_CPU_ACTIVE_AC0	90
-#define DPTF_CPU_ACTIVE_AC1	80
-#define DPTF_CPU_ACTIVE_AC2	70
-#define DPTF_CPU_ACTIVE_AC3	60
-#define DPTF_CPU_ACTIVE_AC4	50
-
 /* These devices are created at runtime */
 External (\_PR.CP00, DeviceObj)
 External (\_PR.CP01, DeviceObj)
diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl
index 018144c..3e51c29 100644
--- a/src/soc/intel/braswell/acpi/dptf/cpu.asl
+++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl
@@ -1,3 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE	80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL	90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC0	90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC1	80
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC2	70
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC3	60
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC4	50
+#endif
+
 External (\_PR.CP00._TSS, MethodObj)
 External (\_PR.CP00._TPC, MethodObj)
 External (\_PR.CP00._PTC, PkgObj)
@@ -127,52 +175,39 @@ Device (B0DB)
 	{
 		Return (\_SB.MPPC)
 	}
-#ifdef DPTF_CPU_CRITICAL
+
 	Method (_CRT)
 	{
 		Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL))
 	}
-#endif
 
-#ifdef DPTF_CPU_PASSIVE
 	Method (_PSV)
 	{
 		Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE))
 	}
-#endif
 
-#ifdef DPTF_CPU_ACTIVE_AC0
 	Method (_AC0)
 	{
 		Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0))
 	}
-#endif
 
-#ifdef DPTF_CPU_ACTIVE_AC1
 	Method (_AC1)
 	{
 		Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1))
 	}
-#endif
 
-#ifdef DPTF_CPU_ACTIVE_AC2
 	Method (_AC2)
 	{
 		Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2))
 	}
-#endif
 
-#ifdef DPTF_CPU_ACTIVE_AC3
 	Method (_AC3)
 	{
 		Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3))
 	}
-#endif
 
-#ifdef DPTF_CPU_ACTIVE_AC4
 	Method (_AC4)
 	{
 		Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4))
 	}
-#endif
 }


From gerrit at coreboot.org  Mon Sep  7 18:42:30 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:30 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: Apply
	USB2 and USB3 port enable/disable settings
References: <I13d4eb901215308de4b59083339832d29ce0049f+0@gerrit.coreboot.org>
Message-ID: <I13d4eb901215308de4b59083339832d29ce0049f+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11547

-gerrit

commit 7a5a9e8da19b2e3f624dfe641355aadf51e12d1b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 28 17:21:07 2015 -0700

    skylake: Apply USB2 and USB3 port enable/disable settings
    
    The USB port enable/disable settings were never getting applied to
    the UPD configuration and so were not getting used by FSP.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=build and boot on glados
    
    Change-Id: I13d4eb901215308de4b59083339832d29ce0049f
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4
    Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296034
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.c | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 8bd62b4..2c49883 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -26,6 +26,7 @@
 #include <fsp_util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
+#include <string.h>
 
 static void pci_domain_set_resources(device_t dev)
 {
@@ -69,18 +70,15 @@ struct chip_operations soc_intel_skylake_ops = {
 /* UPD parameters to be initialized before SiliconInit */
 void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
-	const struct device *dev;
-	const struct soc_intel_skylake_config *config;
-	int i;
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *config = dev->chip_info;
 
-	/* Set the parameters for SiliconInit */
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
-	if (!dev || !dev->chip_info)
-		return;
-	config = dev->chip_info;
-
-	for (i = 0; i < PchSerialIoIndexMax; i++)
-		params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
+	memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
+	       sizeof(params->SerialIoDevMode));
+	memcpy(params->PortUsb20Enable, config->PortUsb20Enable,
+	       sizeof(params->PortUsb20Enable));
+	memcpy(params->PortUsb30Enable, config->PortUsb30Enable,
+	       sizeof(params->PortUsb30Enable));
 
 	params->SataSalpSupport = config->SataSalpSupport;
 	params->SataPortsEnable[0] = config->SataPortsEnable[0];


From gerrit at coreboot.org  Mon Sep  7 18:42:32 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:32 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Disable
	unused USB ports
References: <I8c999e3b17478effc39cf078f8420f63413d091b+0@gerrit.coreboot.org>
Message-ID: <I8c999e3b17478effc39cf078f8420f63413d091b+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11548

-gerrit

commit ea7d9f3ae48fc3d9b29bb3e4256591a773efc9e8
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 28 17:22:04 2015 -0700

    glados: Disable unused USB ports
    
    Enable only the USB ports that are connected on-board or to an
    external port, all others will be disabled.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=build and boot on glados, ensure expected USB ports still work
    
    Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163
    Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296035
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/devicetree.cb | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 9bb065d..2c6d997 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -20,6 +20,18 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoPci, \
 	}"
 
+	register "PortUsb20Enable[0]" = "1"	/* Type-C Port 1 */
+	register "PortUsb20Enable[1]" = "1"	/* Type-C Port 2 */
+	register "PortUsb20Enable[2]" = "1"	/* Bluetooth */
+	register "PortUsb20Enable[4]" = "1"	/* Type-A Port 1 */
+	register "PortUsb20Enable[6]" = "1"	/* Camera */
+	register "PortUsb20Enable[8]" = "1"	/* Type-A Port 2 */
+
+	register "PortUsb30Enable[0]" = "1"	/* Type-C Port 1 */
+	register "PortUsb30Enable[1]" = "1"	/* Type-C Port 2 */
+	register "PortUsb30Enable[2]" = "1"	/* Type-A Port 1 */
+	register "PortUsb30Enable[3]" = "1"	/* Type-A Port 2 */
+
 	# Enable Root port 1 and 5.
 	register "PcieRpEnable[0]" = "1"
 	register "PcieRpEnable[4]" = "1"


From gerrit at coreboot.org  Mon Sep  7 18:42:33 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:33 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Disable unused USB ports
References: <I909a6fab553bba829349dd08fa9cc3f26e5adeb2+0@gerrit.coreboot.org>
Message-ID: <I909a6fab553bba829349dd08fa9cc3f26e5adeb2+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11549

-gerrit

commit 8df84475b3b3a8c4d4471ece035b867078ce0fba
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 28 17:48:11 2015 -0700

    kunimitsu: Disable unused USB ports
    
    Enable only the USB ports that are connected on-board or to an
    external port, all others will be disabled.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=emerge-kunimitsu coreboot, change verified in schematic but not tested
    
    Change-Id: I909a6fab553bba829349dd08fa9cc3f26e5adeb2
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 1b0ce28d093e3b12273d7e0f56b47fb5b13d712f
    Original-Change-Id: I0c4b7de6e559595efa97d756e43f8398feccdffd
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296036
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/devicetree.cb | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 6d0e2f4..1c3cf67 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -15,6 +15,18 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoPci, \
 	}"
 
+	register "PortUsb20Enable[0]" = "1"	/* Type-C Port 1 */
+	register "PortUsb20Enable[1]" = "1"	/* Type-C Port 2 */
+	register "PortUsb20Enable[2]" = "1"	/* Bluetooth */
+	register "PortUsb20Enable[4]" = "1"	/* Type-A Port (card) */
+	register "PortUsb20Enable[6]" = "1"	/* Camera */
+	register "PortUsb20Enable[8]" = "1"	/* Type-A Port (board) */
+
+	register "PortUsb30Enable[0]" = "1"	/* Type-C Port 1 */
+	register "PortUsb30Enable[1]" = "1"	/* Type-C Port 2 */
+	register "PortUsb30Enable[2]" = "1"	/* Type-A Port (card) */
+	register "PortUsb30Enable[3]" = "1"	/* Type-A Port (board) */
+
 	register "pirqa_routing" = "0x8b"
 	register "pirqb_routing" = "0x8a"
 	register "pirqc_routing" = "0x8b"


From gerrit at coreboot.org  Mon Sep  7 18:42:35 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:35 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Skylake:Set
	DISB inside romstage after mrc init
References: <I230ff76287f90c5d3655a77bbaca666af37c4aae+0@gerrit.coreboot.org>
Message-ID: <I230ff76287f90c5d3655a77bbaca666af37c4aae+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11550

-gerrit

commit 91722e80f765821ac5b32e3a77f7f5554c424091
Author: Dhaval Sharma <dhaval.v.sharma at intel.com>
Date:   Thu Aug 27 17:13:19 2015 +0530

    Skylake:Set DISB inside romstage after mrc init
    
    Set DISB inside romstage right after successful mrc init such that
    any reset events afterwards can take fast boot path and in turn
    achieve better boot performance
    
    BRANCH=NONE
    BUG=chrome-os-partner:43637
    TEST=Built for kunimitsu and tested DISB is set correctly and fast
    boot path is taken.
    
    Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61
    Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00
    Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295509
    Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma at intel.com>
    Original-Tested-by: dhaval v sharma <dhaval.v.sharma at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/pmc.c               |  2 --
 src/soc/intel/skylake/romstage/romstage.c | 17 +++++++++++++++++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 2704956..fb09589 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -47,8 +47,6 @@ static const struct reg_script pch_pmc_misc_init_script[] = {
 			DIS_SLP_X_STRCH_SUS_UP),
 	/* Enable SCI and clear SLP requests. */
 	REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
-	/* Indicate DRAM init done for MRC */
-	REG_PCI_OR32(GEN_PMCON_A, DISB),
 	REG_SCRIPT_END
 };
 
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 91a496e..6c5d64a 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -30,6 +30,7 @@
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include <reset.h>
@@ -37,6 +38,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pei_wrapper.h>
 #include <soc/pm.h>
+#include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/romstage.h>
 #include <soc/spi.h>
@@ -405,3 +407,18 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 	soc_display_upd_value("SaGv", 1, old->SaGv, new->SaGv);
 	soc_display_upd_value("RMT", 1, old->RMT, new->RMT);
 }
+
+/* SOC initialization after RAM is enabled. */
+void soc_after_ram_init(struct romstage_params *params)
+{
+	/* Set the DISB as soon as possible after DRAM
+	 * init and MRC cache is saved.
+	 */
+	u32 disb_val = 0;
+	device_t dev = PCH_DEV_PMC;
+	disb_val = pci_read_config32(dev, GEN_PMCON_A);
+	disb_val |= DISB;
+	/* Preserve bits which get cleared up if written 1 */
+	disb_val &= ~(GBL_RST_STS | MS4V);
+	pci_write_config32(dev, GEN_PMCON_A, disb_val);
+}


From gerrit at coreboot.org  Mon Sep  7 18:42:36 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:36 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Modify DQ/DQS mapping
References: <I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb+0@gerrit.coreboot.org>
Message-ID: <I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11551

-gerrit

commit bc8a9d1fa1e9431b2fa366419f2e5b78821295ef
Author: Mike M Hsieh <mike.m.hsieh at intel.com>
Date:   Fri Aug 28 09:27:22 2015 +0800

    kunimitsu: Modify DQ/DQS mapping
    
    Modify DQ Byte Map and DQS Byte Swizzling to match up with design
    
    BUG=chrome-os-partner:44647
    BRANCH=none
    TEST=System boot up and pass memory initialization
    Signed-off-by: Mike Hsieh <mike.m.hsieh at intel.com>
    
    Change-Id: I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7d0a30d4b12bf4dc588d525399a8d223ff35e3de
    Original-Change-Id: I6001c853e4c5540717acf813e039c5c5dbe14c78
    Original-Reviewed-on: https://chromium-review.googlesource.com/295518
    Original-Commit-Ready: Wenkai Du <wenkai.du at intel.com>
    Original-Tested-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Reviewed-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/pei_data.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c
index af9462f..00451bf 100644
--- a/src/mainboard/intel/kunimitsu/pei_data.c
+++ b/src/mainboard/intel/kunimitsu/pei_data.c
@@ -29,12 +29,12 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	const u8 dq_map[2][12] = {
 		  {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
 		   0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00},
-		  {0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC ,
-		   0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
-	/* DQS CPU<>DRAM map for sklrvp board */
+		  {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
+		   0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
+	/* DQS CPU<>DRAM map for kunimitsu board */
 	const u8 dqs_map[2][8] = {
-		{0, 1, 3, 2, 4, 5, 6, 7},
-		{1, 0, 4, 5, 2, 3, 6, 7} };
+		{0, 1, 3, 2, 6, 5, 4, 7},
+		{2, 3, 0, 1, 6, 7, 4, 5} };
 
 	/* Rcomp resistor*/
 	const u16 RcompResistor[3] = {200, 81, 162 };


From gerrit at coreboot.org  Mon Sep  7 18:42:40 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:40 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Skylake: Print
	GPIO MMIO base and pad config using gpio_debug token
References: <I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42+0@gerrit.coreboot.org>
Message-ID: <I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11552

-gerrit

commit 3ebac819793a420579cf4035830e7403bf6f8320
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Mon Aug 31 17:10:35 2015 +0530

    Skylake: Print GPIO MMIO base and pad config using gpio_debug token
    
    This will help development activity. Default GPIO print settings is
    disable, need to set gpio_debug = 1 to get GPIO MMIO dump.
    
    BUG=None
    BRANCH=None
    TEST=build coreboot and boot on Kunimitsu.
    
    Change-Id: I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 19102612ea40184307ecb0ce8b165b5b989f6911
    Original-Change-Id: I4ea6349866c108382de9787bb9ed09fc78d9c770
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296280
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/gpio.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 3610a6c..64b3dda 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -25,6 +25,7 @@
 #include <soc/iomap.h>
 #include <soc/pm.h>
 
+static const int gpio_debug = 0;
 
 /* There are 4 communities with 8 GPIO groups (GPP_[A:G] and GPD) */
 struct gpio_community {
@@ -323,6 +324,11 @@ static void gpio_configure_pad(const struct pad_config *cfg)
 
 	if ((dw0 & PAD_FIELD(GPIROUTSMI, MASK)) == PAD_FIELD(GPIROUTSMI, YES))
 		gpi_enable_smi(cfg->pad);
+
+	if(gpio_debug)
+		printk(BIOS_DEBUG,
+			"Write Pad: Base(%p) - conf0 = %x conf1= %x pad # = %d\n",
+			&dw_regs[0], dw0, reg, cfg->pad);
 }
 
 void gpio_configure_pads(const struct pad_config *cfgs, size_t num)


From gerrit at coreboot.org  Mon Sep  7 18:42:42 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:42 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Fix
	incorrect comment format in devicetree.cb
References: <I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b+0@gerrit.coreboot.org>
Message-ID: <I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11553

-gerrit

commit d9aceefb964ddef553e5d28ad1155ab575db4c66
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 31 09:49:08 2015 -0700

    glados: Fix incorrect comment format in devicetree.cb
    
    The devicetree.cb compiler can't handle C style /**/ comments,
    they need to be shell-style #.  Due to a last minute formatting
    change in my commit to enable USB ports this broke the glados
    build.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2
    Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296301
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/devicetree.cb | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 2c6d997..40fe2b1 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -20,17 +20,17 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoPci, \
 	}"
 
-	register "PortUsb20Enable[0]" = "1"	/* Type-C Port 1 */
-	register "PortUsb20Enable[1]" = "1"	/* Type-C Port 2 */
-	register "PortUsb20Enable[2]" = "1"	/* Bluetooth */
-	register "PortUsb20Enable[4]" = "1"	/* Type-A Port 1 */
-	register "PortUsb20Enable[6]" = "1"	/* Camera */
-	register "PortUsb20Enable[8]" = "1"	/* Type-A Port 2 */
+	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb20Enable[2]" = "1"	# Bluetooth
+	register "PortUsb20Enable[4]" = "1"	# Type-A Port 1
+	register "PortUsb20Enable[6]" = "1"	# Camera
+	register "PortUsb20Enable[8]" = "1"	# Type-A Port 2
 
-	register "PortUsb30Enable[0]" = "1"	/* Type-C Port 1 */
-	register "PortUsb30Enable[1]" = "1"	/* Type-C Port 2 */
-	register "PortUsb30Enable[2]" = "1"	/* Type-A Port 1 */
-	register "PortUsb30Enable[3]" = "1"	/* Type-A Port 2 */
+	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb30Enable[2]" = "1"	# Type-A Port 1
+	register "PortUsb30Enable[3]" = "1"	# Type-A Port 2
 
 	# Enable Root port 1 and 5.
 	register "PcieRpEnable[0]" = "1"


From gerrit at coreboot.org  Mon Sep  7 18:42:43 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:43 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu: Fix
	incorrect comment format in devicetree.cb
References: <I7a77f0f51345f779fcae43338cdc078bc91bb51c+0@gerrit.coreboot.org>
Message-ID: <I7a77f0f51345f779fcae43338cdc078bc91bb51c+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11554

-gerrit

commit ed2211e7ff053cc105151c6643ece24d91a3e074
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 31 10:01:03 2015 -0700

    kunimitsu: Fix incorrect comment format in devicetree.cb
    
    The devicetree.cb compiler can't handle C style /**/ comments,
    they need to be shell-style #.  Due to a last minute formatting
    change in my commit to enable USB ports this broke the kunimitsu
    build.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5
    Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296302
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/devicetree.cb | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 1c3cf67..5cc4f2e 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -15,17 +15,17 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoPci, \
 	}"
 
-	register "PortUsb20Enable[0]" = "1"	/* Type-C Port 1 */
-	register "PortUsb20Enable[1]" = "1"	/* Type-C Port 2 */
-	register "PortUsb20Enable[2]" = "1"	/* Bluetooth */
-	register "PortUsb20Enable[4]" = "1"	/* Type-A Port (card) */
-	register "PortUsb20Enable[6]" = "1"	/* Camera */
-	register "PortUsb20Enable[8]" = "1"	/* Type-A Port (board) */
-
-	register "PortUsb30Enable[0]" = "1"	/* Type-C Port 1 */
-	register "PortUsb30Enable[1]" = "1"	/* Type-C Port 2 */
-	register "PortUsb30Enable[2]" = "1"	/* Type-A Port (card) */
-	register "PortUsb30Enable[3]" = "1"	/* Type-A Port (board) */
+	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb20Enable[2]" = "1"	# Bluetooth
+	register "PortUsb20Enable[4]" = "1"	# Type-A Port (card)
+	register "PortUsb20Enable[6]" = "1"	# Camera
+	register "PortUsb20Enable[8]" = "1"	# Type-A Port (board)
+
+	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb30Enable[2]" = "1"	# Type-A Port (card)
+	register "PortUsb30Enable[3]" = "1"	# Type-A Port (board)
 
 	register "pirqa_routing" = "0x8b"
 	register "pirqb_routing" = "0x8a"


From gerrit at coreboot.org  Mon Sep  7 18:42:59 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:42:59 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: veyron: Unify
	identical mainboards
References: <I4bd590429b9539a91f837459a804888904cd6f2d+0@gerrit.coreboot.org>
Message-ID: <I4bd590429b9539a91f837459a804888904cd6f2d+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11555

-gerrit

commit b0faa14653c98b67d18d0a210a2e4733a98dc72a
Author: Julius Werner <jwerner at chromium.org>
Date:   Fri Aug 28 14:34:09 2015 -0700

    veyron: Unify identical mainboards
    
    This patch removes a lot of code duplication between the virtually
    identical Veyron Chromebook variants by merging the code into a single
    directory and handling the different names solely within Kconfig. This
    also allows us to easily add all the other Chromebook variants that have
    only been kept in Google's firmware branch to avoid cluttering coreboot
    too much, making it possible to build these boards with upstream
    coreboot out of the box.
    
    The only effective change this will have on the affected boards is
    removing quirks for early board revisions (since revision numbers differ
    between variants). Since all those quirks concerned early pre-MP
    revisions, I doubt this will bother anyone (and the old code is still
    available through the Google firmware branch if anyone needs it). It
    will also expand a recent fix in Jerry that increased an LCD power-on
    delay to make it compatible with another kind of panel to all boards,
    which is probably not a bad idea anyway.
    
    Leaving all non-Chromebook boards as they are for now since they often
    contain more extensive differences.
    
    BRANCH=None
    BUG=None
    TEST=Booted Jerry.
    
    Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9
    Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296053
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/veyron/Kconfig                |  88 +++++++++
 src/mainboard/google/veyron/Kconfig.name           |  39 ++++
 src/mainboard/google/veyron/Makefile.inc           |  42 ++++
 src/mainboard/google/veyron/board.h                |  31 +++
 src/mainboard/google/veyron/boardid.c              |  49 +++++
 src/mainboard/google/veyron/bootblock.c            |  78 ++++++++
 src/mainboard/google/veyron/chromeos.c             | 148 ++++++++++++++
 src/mainboard/google/veyron/devicetree.cb          |  26 +++
 src/mainboard/google/veyron/mainboard.c            | 148 ++++++++++++++
 src/mainboard/google/veyron/memlayout.ld           |   1 +
 src/mainboard/google/veyron/reset.c                |  30 +++
 src/mainboard/google/veyron/romstage.c             | 117 +++++++++++
 src/mainboard/google/veyron/sdram_configs.c        |  54 ++++++
 .../veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc      |  78 ++++++++
 .../veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc      |  78 ++++++++
 .../veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc      |  78 ++++++++
 .../veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc    |  78 ++++++++
 .../veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc    |  78 ++++++++
 .../veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc   |  78 ++++++++
 .../veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc   |  78 ++++++++
 .../veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc    |  78 ++++++++
 .../veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc    |  77 ++++++++
 .../veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc  |  78 ++++++++
 .../veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc  |  77 ++++++++
 .../google/veyron/sdram_inf/sdram-unused.inc       |   3 +
 src/mainboard/google/veyron_jerry/Kconfig          |  85 --------
 src/mainboard/google/veyron_jerry/Kconfig.name     |   2 -
 src/mainboard/google/veyron_jerry/Makefile.inc     |  42 ----
 src/mainboard/google/veyron_jerry/board.h          |  31 ---
 src/mainboard/google/veyron_jerry/boardid.c        |  49 -----
 src/mainboard/google/veyron_jerry/bootblock.c      |  78 --------
 src/mainboard/google/veyron_jerry/chromeos.c       | 148 --------------
 src/mainboard/google/veyron_jerry/devicetree.cb    |  26 ---
 src/mainboard/google/veyron_jerry/mainboard.c      | 167 ----------------
 src/mainboard/google/veyron_jerry/memlayout.ld     |   1 -
 src/mainboard/google/veyron_jerry/reset.c          |  30 ---
 src/mainboard/google/veyron_jerry/romstage.c       | 117 -----------
 src/mainboard/google/veyron_jerry/sdram_configs.c  |  54 ------
 .../sdram_inf/sdram-ddr3-hynix-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-hynix-4GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-nanya-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-2GB.inc           |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-4GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-2GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-4GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-2GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-4GB.inc           |  77 --------
 .../sdram_inf/sdram-lpddr3-samsung-2GB.inc         |  78 --------
 .../sdram_inf/sdram-lpddr3-samsung-4GB.inc         |  77 --------
 .../google/veyron_jerry/sdram_inf/sdram-unused.inc |   3 -
 src/mainboard/google/veyron_mighty/Kconfig         |  85 --------
 src/mainboard/google/veyron_mighty/Kconfig.name    |   2 -
 src/mainboard/google/veyron_mighty/Makefile.inc    |  42 ----
 src/mainboard/google/veyron_mighty/board.h         |  31 ---
 src/mainboard/google/veyron_mighty/boardid.c       |  49 -----
 src/mainboard/google/veyron_mighty/bootblock.c     |  78 --------
 src/mainboard/google/veyron_mighty/chromeos.c      | 148 --------------
 src/mainboard/google/veyron_mighty/devicetree.cb   |  26 ---
 src/mainboard/google/veyron_mighty/mainboard.c     | 167 ----------------
 src/mainboard/google/veyron_mighty/memlayout.ld    |   1 -
 src/mainboard/google/veyron_mighty/reset.c         |  30 ---
 src/mainboard/google/veyron_mighty/romstage.c      | 117 -----------
 src/mainboard/google/veyron_mighty/sdram_configs.c |  54 ------
 .../sdram_inf/sdram-ddr3-hynix-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-hynix-4GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-nanya-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-2GB.inc           |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-4GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-2GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-4GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-2GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-4GB.inc           |  77 --------
 .../sdram_inf/sdram-lpddr3-samsung-2GB.inc         |  78 --------
 .../sdram_inf/sdram-lpddr3-samsung-4GB.inc         |  77 --------
 .../veyron_mighty/sdram_inf/sdram-unused.inc       |   3 -
 src/mainboard/google/veyron_minnie/Kconfig         |  85 --------
 src/mainboard/google/veyron_minnie/Kconfig.name    |   2 -
 src/mainboard/google/veyron_minnie/Makefile.inc    |  42 ----
 src/mainboard/google/veyron_minnie/board.h         |  31 ---
 src/mainboard/google/veyron_minnie/board_info.txt  |   1 -
 src/mainboard/google/veyron_minnie/boardid.c       |  49 -----
 src/mainboard/google/veyron_minnie/bootblock.c     |  78 --------
 src/mainboard/google/veyron_minnie/chromeos.c      | 148 --------------
 src/mainboard/google/veyron_minnie/devicetree.cb   |  26 ---
 src/mainboard/google/veyron_minnie/mainboard.c     | 148 --------------
 src/mainboard/google/veyron_minnie/memlayout.ld    |   1 -
 src/mainboard/google/veyron_minnie/reset.c         |  30 ---
 src/mainboard/google/veyron_minnie/romstage.c      | 118 ------------
 src/mainboard/google/veyron_minnie/sdram_configs.c |  54 ------
 .../sdram_inf/sdram-ddr3-hynix-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-hynix-4GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-nanya-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-2GB.inc           |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-4GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-2GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-4GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-2GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-4GB.inc           |  77 --------
 .../sdram_inf/sdram-lpddr3-samsung-2GB.inc         |  78 --------
 .../sdram_inf/sdram-lpddr3-samsung-4GB.inc         |  77 --------
 .../veyron_minnie/sdram_inf/sdram-unused.inc       |   3 -
 src/mainboard/google/veyron_pinky/Kconfig          |  85 --------
 src/mainboard/google/veyron_pinky/Kconfig.name     |   2 -
 src/mainboard/google/veyron_pinky/Makefile.inc     |  42 ----
 src/mainboard/google/veyron_pinky/board.h          |  31 ---
 src/mainboard/google/veyron_pinky/boardid.c        |  49 -----
 src/mainboard/google/veyron_pinky/bootblock.c      |  78 --------
 src/mainboard/google/veyron_pinky/chromeos.c       | 149 --------------
 src/mainboard/google/veyron_pinky/devicetree.cb    |  26 ---
 src/mainboard/google/veyron_pinky/mainboard.c      | 213 ---------------------
 src/mainboard/google/veyron_pinky/memlayout.ld     |   1 -
 src/mainboard/google/veyron_pinky/reset.c          |  30 ---
 src/mainboard/google/veyron_pinky/romstage.c       | 125 ------------
 src/mainboard/google/veyron_pinky/sdram_configs.c  |  54 ------
 .../sdram_inf/sdram-ddr3-hynix-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-hynix-4GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-nanya-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-2GB.inc           |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-4GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-2GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-4GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-2GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-4GB.inc           |  77 --------
 .../sdram_inf/sdram-lpddr3-samsung-2GB.inc         |  78 --------
 .../sdram_inf/sdram-lpddr3-samsung-4GB.inc         |  77 --------
 .../google/veyron_pinky/sdram_inf/sdram-unused.inc |   3 -
 src/mainboard/google/veyron_shark/Kconfig          |  85 --------
 src/mainboard/google/veyron_shark/Kconfig.name     |   2 -
 src/mainboard/google/veyron_shark/Makefile.inc     |  42 ----
 src/mainboard/google/veyron_shark/board.h          |  31 ---
 src/mainboard/google/veyron_shark/boardid.c        |  49 -----
 src/mainboard/google/veyron_shark/bootblock.c      |  78 --------
 src/mainboard/google/veyron_shark/chromeos.c       | 148 --------------
 src/mainboard/google/veyron_shark/devicetree.cb    |  26 ---
 src/mainboard/google/veyron_shark/mainboard.c      | 157 ---------------
 src/mainboard/google/veyron_shark/memlayout.ld     |   1 -
 src/mainboard/google/veyron_shark/reset.c          |  30 ---
 src/mainboard/google/veyron_shark/romstage.c       | 118 ------------
 src/mainboard/google/veyron_shark/sdram_configs.c  |  54 ------
 .../sdram_inf/sdram-ddr3-hynix-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-hynix-4GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-nanya-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-2GB.inc           |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-4GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-2GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-4GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-2GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-4GB.inc           |  77 --------
 .../sdram_inf/sdram-lpddr3-samsung-2GB.inc         |  78 --------
 .../sdram_inf/sdram-lpddr3-samsung-4GB.inc         |  77 --------
 .../google/veyron_shark/sdram_inf/sdram-unused.inc |   3 -
 src/mainboard/google/veyron_speedy/Kconfig         |  85 --------
 src/mainboard/google/veyron_speedy/Kconfig.name    |   2 -
 src/mainboard/google/veyron_speedy/Makefile.inc    |  42 ----
 src/mainboard/google/veyron_speedy/board.h         |  31 ---
 src/mainboard/google/veyron_speedy/boardid.c       |  49 -----
 src/mainboard/google/veyron_speedy/bootblock.c     |  78 --------
 src/mainboard/google/veyron_speedy/chromeos.c      | 148 --------------
 src/mainboard/google/veyron_speedy/devicetree.cb   |  26 ---
 src/mainboard/google/veyron_speedy/mainboard.c     | 167 ----------------
 src/mainboard/google/veyron_speedy/memlayout.ld    |   1 -
 src/mainboard/google/veyron_speedy/reset.c         |  30 ---
 src/mainboard/google/veyron_speedy/romstage.c      | 118 ------------
 src/mainboard/google/veyron_speedy/sdram_configs.c |  54 ------
 .../sdram_inf/sdram-ddr3-hynix-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-hynix-4GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-nanya-2GB.inc             |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-2GB.inc           |  78 --------
 .../sdram_inf/sdram-ddr3-samsung-4GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-2GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-elpida-4GB.inc          |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-2GB.inc           |  78 --------
 .../sdram_inf/sdram-lpddr3-hynix-4GB.inc           |  77 --------
 .../sdram_inf/sdram-lpddr3-samsung-2GB.inc         |  78 --------
 .../sdram_inf/sdram-lpddr3-samsung-4GB.inc         |  77 --------
 .../veyron_speedy/sdram_inf/sdram-unused.inc       |   3 -
 176 files changed, 1710 insertions(+), 10164 deletions(-)

diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
new file mode 100644
index 0000000..c474bd6
--- /dev/null
+++ b/src/mainboard/google/veyron/Kconfig
@@ -0,0 +1,88 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards
+	def_bool n
+
+if BOARD_GOOGLE_VEYRON
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select BOARD_ID_AUTO
+	select COMMON_CBFS_SPI_WRAPPER
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_SPI
+	select RAM_CODE_SUPPORT
+	select SOC_ROCKCHIP_RK3288
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select MAINBOARD_DO_NATIVE_VGA_INIT
+	select MAINBOARD_HAS_CHROMEOS
+	select BOARD_ROMSIZE_KB_4096
+	select HAVE_HARD_RESET
+	select SPI_FLASH
+	select SPI_FLASH_GIGADEVICE
+	select SPI_FLASH_WINBOND
+
+config CHROMEOS
+	select CHROMEOS_VBNV_EC
+	select EC_SOFTWARE_SYNC
+	select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+	string
+	default google/veyron
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Veyron"
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	hex
+	default 0
+
+config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
+	int
+	default 100
+
+config BOOT_MEDIA_SPI_BUS
+	int
+	default 2
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x20
+
+config CONSOLE_SERIAL_UART_ADDRESS
+	hex
+	depends on DRIVERS_UART
+	default 0xFF690000
+
+config PMIC_BUS
+	int
+	default 0
+
+endif #  BOARD_GOOGLE_VEYRON
diff --git a/src/mainboard/google/veyron/Kconfig.name b/src/mainboard/google/veyron/Kconfig.name
new file mode 100644
index 0000000..5c7a44b
--- /dev/null
+++ b/src/mainboard/google/veyron/Kconfig.name
@@ -0,0 +1,39 @@
+config BOARD_GOOGLE_VEYRON_GUS
+	bool "Veyron_Gus"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_JAQ
+	bool "Veyron_Jaq"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_JERRY
+	bool "Veyron_Jerry"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_MIGHTY
+	bool "Veyron_Mighty"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_MINNIE
+	bool "Veyron_Minnie"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_NICKY
+	bool "Veyron_Nicky"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_PINKY
+	bool "Veyron_Pinky"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_SHARK
+	bool "Veyron_Shark"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_SPEEDY
+	bool "Veyron_Speedy"
+	select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_THEA
+	bool "Veyron_Thea"
+	select BOARD_GOOGLE_VEYRON
diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc
new file mode 100644
index 0000000..ea1c606
--- /dev/null
+++ b/src/mainboard/google/veyron/Makefile.inc
@@ -0,0 +1,42 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+bootblock-y += bootblock.c
+bootblock-y += boardid.c
+bootblock-y += chromeos.c
+bootblock-y += reset.c
+
+verstage-y += boardid.c
+verstage-y += chromeos.c
+verstage-y += reset.c
+
+romstage-y += boardid.c
+romstage-y += chromeos.c
+romstage-y += romstage.c
+romstage-y += sdram_configs.c
+romstage-y += reset.c
+
+ramstage-y += boardid.c
+ramstage-y += chromeos.c
+ramstage-y += mainboard.c
+ramstage-y += reset.c
+
+bootblock-y += memlayout.ld
+verstage-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron/board.h b/src/mainboard/google/veyron/board.h
new file mode 100644
index 0000000..a200e16
--- /dev/null
+++ b/src/mainboard/google/veyron/board.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MAINBOARD_GOOGLE_VEYRON_BOARD_H
+#define __MAINBOARD_GOOGLE_VEYRON_BOARD_H
+
+#include <boardid.h>
+#include <gpio.h>
+
+#define GPIO_BACKLIGHT	GPIO(7, A, 2)
+#define GPIO_RESET	GPIO(0, B, 5)
+
+void setup_chromeos_gpios(void);
+
+#endif	/* __MAINBOARD_GOOGLE_VEYRON_BOARD_H */
diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c
new file mode 100644
index 0000000..f7cddcc
--- /dev/null
+++ b/src/mainboard/google/veyron/boardid.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <stdlib.h>
+
+uint8_t board_id(void)
+{
+	static int id = -1;
+	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
+		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
+
+	if (id < 0) {
+		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
+		printk(BIOS_SPEW, "Board ID: %d.\n", id);
+	}
+
+	return id;
+}
+
+uint32_t ram_code(void)
+{
+	uint32_t code;
+	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
+		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
+
+	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
+	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
+
+	return code;
+}
diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c
new file mode 100644
index 0000000..ae74972
--- /dev/null
+++ b/src/mainboard/google/veyron/bootblock.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <delay.h>
+#include <reset.h>
+#include <soc/clock.h>
+#include <soc/i2c.h>
+#include <soc/grf.h>
+#include <soc/pmu.h>
+#include <soc/rk808.h>
+#include <soc/spi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+void bootblock_mainboard_early_init()
+{
+	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
+		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
+		write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
+	}
+
+}
+
+void bootblock_mainboard_init(void)
+{
+	if (rkclk_was_watchdog_reset())
+		reboot_from_watchdog();
+
+	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
+	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
+	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
+	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
+	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
+
+	/* Slowly raise to max CPU voltage to prevent overshoot */
+	rk808_configure_buck(1, 1200);
+	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
+	rk808_configure_buck(1, 1400);
+	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
+	rkclk_configure_cpu();
+
+	/* i2c1 for tpm */
+	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
+	i2c_init(1, 400*KHz);
+
+	/* spi2 for firmware ROM */
+	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
+	/* spi0 for chrome ec */
+	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
+	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
+
+	setup_chromeos_gpios();
+}
diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c
new file mode 100644
index 0000000..5489639
--- /dev/null
+++ b/src/mainboard/google/veyron/chromeos.c
@@ -0,0 +1,148 @@
+?/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <gpio.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+#define GPIO_WP		GPIO(7, A, 6)
+#define GPIO_LID	GPIO(0, A, 6)
+#define GPIO_POWER	GPIO(0, A, 5)
+#define GPIO_RECOVERY	GPIO(0, B, 1)
+#define GPIO_ECINRW	GPIO(0, A, 7)
+#define GPIO_ECIRQ	GPIO(7, A, 7)
+
+void setup_chromeos_gpios(void)
+{
+	gpio_input(GPIO_WP);
+	gpio_input_pullup(GPIO_LID);
+	gpio_input(GPIO_POWER);
+	gpio_input_pullup(GPIO_RECOVERY);
+	gpio_input(GPIO_ECIRQ);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	int count = 0;
+
+	/* Write Protect: active low */
+	gpios->gpios[count].port = GPIO_WP.raw;
+	gpios->gpios[count].polarity = ACTIVE_LOW;
+	gpios->gpios[count].value = gpio_get(GPIO_WP);
+	strncpy((char *)gpios->gpios[count].name, "write protect",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Recovery: active low */
+	gpios->gpios[count].port = GPIO_RECOVERY.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = get_recovery_mode_switch();
+	strncpy((char *)gpios->gpios[count].name, "recovery",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Lid: active high */
+	gpios->gpios[count].port = GPIO_LID.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = -1;
+	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Power:GPIO active high */
+	gpios->gpios[count].port = GPIO_POWER.raw;
+	gpios->gpios[count].polarity = ACTIVE_LOW;
+	gpios->gpios[count].value = -1;
+	strncpy((char *)gpios->gpios[count].name, "power",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Developer: GPIO active high */
+	gpios->gpios[count].port = -1;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = get_developer_mode_switch();
+	strncpy((char *)gpios->gpios[count].name, "developer",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* EC in RW: GPIO active high */
+	gpios->gpios[count].port = GPIO_ECINRW.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = -1;
+	strncpy((char *)gpios->gpios[count].name, "EC in RW",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* EC interrupt: GPIO active high */
+	gpios->gpios[count].port = GPIO_ECIRQ.raw;
+	gpios->gpios[count].polarity = ACTIVE_LOW;
+	gpios->gpios[count].value = -1;
+	strncpy((char *)gpios->gpios[count].name, "EC interrupt",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Reset: GPIO active high (output) */
+	gpios->gpios[count].port = GPIO_RESET.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = -1;
+	strncpy((char *)gpios->gpios[count].name, "reset",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Backlight: GPIO active high (output) */
+	gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = -1;
+	strncpy((char *)gpios->gpios[count].name, "backlight",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+	gpios->count = count;
+
+	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+	uint32_t ec_events;
+
+	/* The GPIO is active low. */
+	if (!gpio_get(GPIO_RECOVERY))
+		return 1;
+
+	ec_events = google_chromeec_get_events_b();
+	return !!(ec_events &
+		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+	return !gpio_get(GPIO_WP);
+}
diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb
new file mode 100644
index 0000000..b958e26
--- /dev/null
+++ b/src/mainboard/google/veyron/devicetree.cb
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+# TODO fill with Versatile Express board data in QEMU.
+chip soc/rockchip/rk3288
+	device cpu_cluster 0 on end
+	register "vop_id" = "1"
+	register "vop_mode" = "VOP_MODE_EDP"
+	register "framebuffer_bits_per_pixel" = "16"
+end
diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c
new file mode 100644
index 0000000..b8f9aae
--- /dev/null
+++ b/src/mainboard/google/veyron/mainboard.c
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cache.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/i2c.h>
+#include <edid.h>
+#include <elog.h>
+#include <gpio.h>
+#include <soc/display.h>
+#include <soc/grf.h>
+#include <soc/soc.h>
+#include <soc/pmu.h>
+#include <soc/clock.h>
+#include <soc/rk808.h>
+#include <soc/spi.h>
+#include <soc/i2c.h>
+#include <symbols.h>
+#include <vbe.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+static void configure_usb(void)
+{
+	gpio_output(GPIO(0, B, 3), 1);			/* HOST1_PWR_EN */
+	gpio_output(GPIO(0, B, 4), 1);			/* USBOTG_PWREN_H */
+	gpio_output(GPIO(7, C, 5), 1);			/* 5V_DRV */
+}
+
+static void configure_sdmmc(void)
+{
+	write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
+
+	/* use sdmmc0 io, disable JTAG function */
+	write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
+
+	/* Note: these power rail definitions are copied in romstage.c */
+	rk808_configure_ldo(4, 3300); /* VCCIO_SD */
+	rk808_configure_ldo(5, 3300); /* VCC33_SD */
+
+	gpio_input(GPIO(7, A, 5));		/* SD_DET */
+}
+
+static void configure_emmc(void)
+{
+	write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+	write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+	write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
+
+	gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
+}
+
+static void configure_codec(void)
+{
+	write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);	/* CODEC I2C */
+	i2c_init(2, 400*KHz);				/* CODEC I2C */
+
+	write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+	write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
+
+	rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
+
+	/* AUDIO IO domain 1.8V voltage selection */
+	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
+	rkclk_configure_i2s(12288000);
+}
+
+static void configure_vop(void)
+{
+	write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
+
+	/* lcdc(vop) iodomain select 1.8V */
+	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
+
+	gpio_output(GPIO(2, B, 5), 1);	/* AVDD_1V8_DISP_EN */
+	rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
+	gpio_output(GPIO(7, B, 6), 1);	/* LCD_EN */
+	rk808_configure_switch(1, 1);	/* VCC33_LCD */
+
+	/* enable edp HPD */
+	gpio_input_pulldown(GPIO(7, B, 3));
+	write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
+}
+
+static void mainboard_init(device_t dev)
+{
+	gpio_output(GPIO_RESET, 0);
+
+	configure_usb();
+	configure_sdmmc();
+	configure_emmc();
+	configure_codec();
+	configure_vop();
+
+	elog_init();
+	elog_add_watchdog_reset();
+	elog_add_boot_reason();
+}
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
+
+void lb_board(struct lb_header *header)
+{
+	struct lb_range *dma;
+
+	dma = (struct lb_range *)lb_new_record(header);
+	dma->tag = LB_TAB_DMA;
+	dma->size = sizeof(*dma);
+	dma->range_start = (uintptr_t)_dma_coherent;
+	dma->range_size = _dma_coherent_size;
+}
+
+void mainboard_power_on_backlight(void)
+{
+	gpio_output(GPIO(2, B, 4), 1);	/* BL_PWR_EN */
+	mdelay(120);
+	gpio_output(GPIO(7, A, 0), 1);	/* LCD_BL */
+	mdelay(10);
+	gpio_output(GPIO_BACKLIGHT, 1);	/* BL_EN */
+}
diff --git a/src/mainboard/google/veyron/memlayout.ld b/src/mainboard/google/veyron/memlayout.ld
new file mode 100644
index 0000000..ead7f47
--- /dev/null
+++ b/src/mainboard/google/veyron/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron/reset.c b/src/mainboard/google/veyron/reset.c
new file mode 100644
index 0000000..bc26ece
--- /dev/null
+++ b/src/mainboard/google/veyron/reset.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <gpio.h>
+#include <reset.h>
+
+#include "board.h"
+
+void hard_reset(void)
+{
+	gpio_output(GPIO_RESET, 1);
+	while (1);
+}
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
new file mode 100644
index 0000000..5ccbe3e
--- /dev/null
+++ b/src/mainboard/google/veyron/romstage.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cache.h>
+#include <arch/exception.h>
+#include <arch/stages.h>
+#include <armv7.h>
+#include <assert.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <delay.h>
+#include <program_loading.h>
+#include <soc/sdram.h>
+#include <soc/clock.h>
+#include <soc/pwm.h>
+#include <soc/grf.h>
+#include <soc/rk808.h>
+#include <soc/tsadc.h>
+#include <stdlib.h>
+#include <symbols.h>
+#include <timestamp.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+static void regulate_vdd_log(unsigned int mv)
+{
+	unsigned int duty_ns;
+	const u32 period_ns = 2000;	/* pwm period: 2000ns */
+	const u32 max_regulator_mv = 1350;	/* 1.35V */
+	const u32 min_regulator_mv = 870;	/* 0.87V */
+
+	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
+
+	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
+
+	duty_ns = (max_regulator_mv - mv) * period_ns /
+			(max_regulator_mv - min_regulator_mv);
+
+	pwm_init(1, period_ns, duty_ns);
+}
+
+static void configure_l2ctlr(void)
+{
+	uint32_t l2ctlr;
+
+	l2ctlr = read_l2ctlr();
+	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+	/*
+	* Data RAM write latency: 2 cycles
+	* Data RAM read latency: 2 cycles
+	* Data RAM setup latency: 1 cycle
+	* Tag RAM write latency: 1 cycle
+	* Tag RAM read latency: 1 cycle
+	* Tag RAM setup latency: 1 cycle
+	*/
+	l2ctlr |= (1 << 3 | 1 << 0);
+	write_l2ctlr(l2ctlr);
+}
+
+static void sdmmc_power_off(void)
+{
+	rk808_configure_ldo(4, 0); /* VCCIO_SD */
+	rk808_configure_ldo(5, 0); /* VCC33_SD */
+}
+
+void main(void)
+{
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	console_init();
+	configure_l2ctlr();
+	tsadc_init();
+
+	/* Need to power cycle SD card to ensure it is properly reset. */
+	sdmmc_power_off();
+
+	/* vdd_log 1200mv is enough for ddr run 666Mhz */
+	regulate_vdd_log(1200);
+
+	timestamp_add_now(TS_BEFORE_INITRAM);
+
+	sdram_init(get_sdram_config());
+
+	timestamp_add_now(TS_AFTER_INITRAM);
+
+	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
+	mmu_config_range((uintptr_t)_dram/MiB,
+			 sdram_size_mb(), DCACHE_WRITEBACK);
+	mmu_config_range((uintptr_t)_dma_coherent/MiB,
+			 _dma_coherent_size/MiB, DCACHE_OFF);
+
+	cbmem_initialize_empty();
+
+	timestamp_add_now(TS_END_ROMSTAGE);
+
+	run_ramstage();
+}
diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c
new file mode 100644
index 0000000..023eb37
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_configs.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <arch/io.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <soc/sdram.h>
+#include <string.h>
+#include <types.h>
+
+static struct rk3288_sdram_params sdram_configs[] = {
+#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
+#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
+#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
+#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
+#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0110 */
+#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc"	/* ram_code = 0111 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc"	/* ram_code = 1000 */
+#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
+#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
+#include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
+#include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
+};
+
+const struct rk3288_sdram_params *get_sdram_config()
+{
+	u32 ramcode = ram_code();
+
+	if (ramcode >= ARRAY_SIZE(sdram_configs)
+			|| sdram_configs[ramcode].dramtype == UNUSED)
+		die("Invalid RAMCODE.");
+	return &sdram_configs[ramcode];
+}
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
new file mode 100644
index 0000000..5b784cd
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
@@ -0,0 +1,78 @@
+{
+	/* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x29A,
+		.tinit = 0xC8,
+		.trsth = 0x1F4,
+		.togcnt100n = 0x42,
+		.trefi = 0x4E,
+		.tmrd = 0x4,
+		.trfc = 0xEA,
+		.trp = 0xA,
+		.trtw = 0x5,
+		.tal = 0x0,
+		.tcl = 0xA,
+		.tcwl = 0x7,
+		.tras = 0x19,
+		.trc = 0x24,
+		.trcd = 0xA,
+		.trrd = 0x7,
+		.trtp = 0x5,
+		.twr = 0xA,
+		.twtr = 0x5,
+		.texsr = 0x200,
+		.txp = 0x5,
+		.txpdll = 0x10,
+		.tzqcs = 0x40,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x7,
+		.tcksrx = 0x7,
+		.tcke = 0x4,
+		.tmod = 0xC,
+		.trstl = 0x43,
+		.tzqcl = 0x100,
+		.tmrr = 0x0,
+		.tckesr = 0x5,
+		.tdpd = 0x0
+	},
+	{
+		.dtpr0 = 0x48F9AAB4,
+		.dtpr1 = 0xEA0910,
+		.dtpr2 = 0x1002C200,
+		.mr[0] = 0xA60,
+		.mr[1] = 0x40,
+		.mr[2] = 0x10,
+		.mr[3] = 0x0
+	},
+	.noc_timing = 0x30B25564,
+	.noc_activate = 0x627,
+	.ddrconfig = 3,
+	.ddr_freq = 666*MHz,
+	.dramtype = DDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc
new file mode 100644
index 0000000..9f2ca8a
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc
@@ -0,0 +1,78 @@
+{
+	/* 4 Hynix H5TC8G63xxx chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x29A,
+		.tinit = 0xC8,
+		.trsth = 0x1F4,
+		.togcnt100n = 0x42,
+		.trefi = 0x4E,
+		.tmrd = 0x4,
+		.trfc = 0xEA,
+		.trp = 0xA,
+		.trtw = 0x5,
+		.tal = 0x0,
+		.tcl = 0xA,
+		.tcwl = 0x7,
+		.tras = 0x19,
+		.trc = 0x24,
+		.trcd = 0xA,
+		.trrd = 0x7,
+		.trtp = 0x5,
+		.twr = 0xA,
+		.twtr = 0x5,
+		.texsr = 0x200,
+		.txp = 0x5,
+		.txpdll = 0x10,
+		.tzqcs = 0x40,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x7,
+		.tcksrx = 0x7,
+		.tcke = 0x4,
+		.tmod = 0xC,
+		.trstl = 0x43,
+		.tzqcl = 0x100,
+		.tmrr = 0x0,
+		.tckesr = 0x5,
+		.tdpd = 0x0
+	},
+	{
+		.dtpr0 = 0x48F9AAB4,
+		.dtpr1 = 0xEA0910,
+		.dtpr2 = 0x1002C200,
+		.mr[0] = 0xA60,
+		.mr[1] = 0x40,
+		.mr[2] = 0x10,
+		.mr[3] = 0x0
+	},
+	.noc_timing = 0x30B25564,
+	.noc_activate = 0x627,
+	.ddrconfig = 3,
+	.ddr_freq = 666*MHz,
+	.dramtype = DDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+	/* 4 Nanya NT5CC256M16DP chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x29A,
+		.tinit = 0xC8,
+		.trsth = 0x1F4,
+		.togcnt100n = 0x42,
+		.trefi = 0x4E,
+		.tmrd = 0x4,
+		.trfc = 0xEA,
+		.trp = 0xA,
+		.trtw = 0x5,
+		.tal = 0x0,
+		.tcl = 0xA,
+		.tcwl = 0x7,
+		.tras = 0x19,
+		.trc = 0x24,
+		.trcd = 0xA,
+		.trrd = 0x7,
+		.trtp = 0x5,
+		.twr = 0xA,
+		.twtr = 0x5,
+		.texsr = 0x200,
+		.txp = 0x5,
+		.txpdll = 0x10,
+		.tzqcs = 0x40,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x7,
+		.tcksrx = 0x7,
+		.tcke = 0x4,
+		.tmod = 0xC,
+		.trstl = 0x43,
+		.tzqcl = 0x100,
+		.tmrr = 0x0,
+		.tckesr = 0x5,
+		.tdpd = 0x0
+	},
+	{
+		.dtpr0 = 0x48F9AAB4,
+		.dtpr1 = 0xEA0910,
+		.dtpr2 = 0x1002C200,
+		.mr[0] = 0xA60,
+		.mr[1] = 0x40,
+		.mr[2] = 0x10,
+		.mr[3] = 0x0
+	},
+	.noc_timing = 0x30B25564,
+	.noc_activate = 0x627,
+	.ddrconfig = 3,
+	.ddr_freq = 666*MHz,
+	.dramtype = DDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc
new file mode 100644
index 0000000..f5793d1
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc
@@ -0,0 +1,78 @@
+{
+	/* two Samsung K4B4G1646D-BYK0 chips */
+        {
+                {
+                        .rank = 0x1,
+                        .col = 0xA,
+                        .bk = 0x3,
+                        .bw = 0x2,
+                        .dbw = 0x1,
+                        .row_3_4 = 0x0,
+                        .cs0_row = 0xF,
+                        .cs1_row = 0xF
+                },
+                {
+                        .rank = 0x1,
+                        .col = 0xA,
+                        .bk = 0x3,
+                        .bw = 0x2,
+                        .dbw = 0x1,
+                        .row_3_4 = 0x0,
+                        .cs0_row = 0xF,
+                        .cs1_row = 0xF
+                }
+        },
+        {
+                .togcnt1u = 0x29A,
+                .tinit = 0xC8,
+                .trsth = 0x1F4,
+                .togcnt100n = 0x42,
+                .trefi = 0x4E,
+                .tmrd = 0x4,
+                .trfc = 0xEA,
+                .trp = 0xA,
+                .trtw = 0x5,
+                .tal = 0x0,
+                .tcl = 0xA,
+                .tcwl = 0x7,
+                .tras = 0x19,
+                .trc = 0x24,
+                .trcd = 0xA,
+                .trrd = 0x7,
+                .trtp = 0x5,
+                .twr = 0xA,
+                .twtr = 0x5,
+                .texsr = 0x200,
+                .txp = 0x5,
+                .txpdll = 0x10,
+                .tzqcs = 0x40,
+                .tzqcsi = 0x0,
+                .tdqs = 0x1,
+                .tcksre = 0x7,
+                .tcksrx = 0x7,
+                .tcke = 0x4,
+                .tmod = 0xC,
+                .trstl = 0x43,
+                .tzqcl = 0x100,
+                .tmrr = 0x0,
+                .tckesr = 0x5,
+                .tdpd = 0x0
+        },
+        {
+                .dtpr0 = 0x48F9AAB4,
+                .dtpr1 = 0xEA0910,
+                .dtpr2 = 0x1002C200,
+                .mr[0] = 0xA60,
+                .mr[1] = 0x40,
+                .mr[2] = 0x10,
+                .mr[3] = 0x0
+        },
+        .noc_timing = 0x30B25564,
+        .noc_activate = 0x627,
+        .ddrconfig = 3,
+        .ddr_freq = 666*MHz,
+        .dramtype = DDR3,
+        .num_channels = 2,
+        .stride = 9,
+        .odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc
new file mode 100644
index 0000000..a32f1a6
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc
@@ -0,0 +1,78 @@
+{
+	/* 4 Samsung K4B8G1646Q chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x29A,
+		.tinit = 0xC8,
+		.trsth = 0x1F4,
+		.togcnt100n = 0x42,
+		.trefi = 0x4E,
+		.tmrd = 0x4,
+		.trfc = 0xEA,
+		.trp = 0xA,
+		.trtw = 0x5,
+		.tal = 0x0,
+		.tcl = 0xA,
+		.tcwl = 0x7,
+		.tras = 0x19,
+		.trc = 0x24,
+		.trcd = 0xA,
+		.trrd = 0x7,
+		.trtp = 0x5,
+		.twr = 0xA,
+		.twtr = 0x5,
+		.texsr = 0x200,
+		.txp = 0x5,
+		.txpdll = 0x10,
+		.tzqcs = 0x40,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x7,
+		.tcksrx = 0x7,
+		.tcke = 0x4,
+		.tmod = 0xC,
+		.trstl = 0x43,
+		.tzqcl = 0x100,
+		.tmrr = 0x0,
+		.tckesr = 0x5,
+		.tdpd = 0x0
+	},
+	{
+		.dtpr0 = 0x48F9AAB4,
+		.dtpr1 = 0xEA0910,
+		.dtpr2 = 0x1002C200,
+		.mr[0] = 0xA60,
+		.mr[1] = 0x40,
+		.mr[2] = 0x10,
+		.mr[3] = 0x0
+	},
+	.noc_timing = 0x30B25564,
+	.noc_activate = 0x627,
+	.ddrconfig = 3,
+	.ddr_freq = 666*MHz,
+	.dramtype = DDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc
new file mode 100644
index 0000000..ef82b277
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc
@@ -0,0 +1,78 @@
+{
+	/* two ELPIDA F8132A3MA-GD-F chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 2,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc
new file mode 100644
index 0000000..e071646
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc
@@ -0,0 +1,78 @@
+{
+	/* two ELPIDA FA232A2MA-GC-F chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xB,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		},
+		{
+			.rank = 0x2,
+			.col = 0xB,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 6,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
new file mode 100644
index 0000000..00dc549
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Hynix H9CCNNN8GTMLAR chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 14,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc
new file mode 100644
index 0000000..a48ac42
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc
@@ -0,0 +1,77 @@
+{
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
new file mode 100644
index 0000000..0f15ba5
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
@@ -0,0 +1,78 @@
+{
+	/* two Samsung K4E8E304ED-EGCE000 chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 2,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
new file mode 100644
index 0000000..09d260b
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
@@ -0,0 +1,77 @@
+{
+	{
+		{
+			.rank = 0x2,
+			.col = 0xB,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		},
+		{
+			.rank = 0x2,
+			.col = 0xB,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 6,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
new file mode 100644
index 0000000..06498f7
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
@@ -0,0 +1,3 @@
+{
+	.dramtype= UNUSED
+},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig
deleted file mode 100644
index 1bbcf94..0000000
--- a/src/mainboard/google/veyron_jerry/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_JERRY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select BOARD_ID_AUTO
-	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select RAM_CODE_SUPPORT
-	select SOC_ROCKCHIP_RK3288
-	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_DO_NATIVE_VGA_INIT
-	select MAINBOARD_HAS_CHROMEOS
-	select BOARD_ROMSIZE_KB_4096
-	select HAVE_HARD_RESET
-	select SPI_FLASH
-	select SPI_FLASH_GIGADEVICE
-	select SPI_FLASH_WINBOND
-
-config CHROMEOS
-	select CHROMEOS_VBNV_EC
-	select EC_SOFTWARE_SYNC
-	select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
-	string
-	default google/veyron_jerry
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Veyron_Jerry"
-
-config MAINBOARD_VENDOR
-	string
-	default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
-	int
-	default 100
-
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 2
-
-config DRIVER_TPM_I2C_BUS
-	hex
-	default 0x1
-
-config DRIVER_TPM_I2C_ADDR
-	hex
-	default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	depends on DRIVERS_UART
-	default 0xFF690000
-
-config PMIC_BUS
-	int
-	default 0
-
-endif #  BOARD_GOOGLE_VEYRON_JERRY
diff --git a/src/mainboard/google/veyron_jerry/Kconfig.name b/src/mainboard/google/veyron_jerry/Kconfig.name
deleted file mode 100644
index 10c5f4e..0000000
--- a/src/mainboard/google/veyron_jerry/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_JERRY
-	bool "Veyron_Jerry"
diff --git a/src/mainboard/google/veyron_jerry/Makefile.inc b/src/mainboard/google/veyron_jerry/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_jerry/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_jerry/board.h b/src/mainboard/google/veyron_jerry/board.h
deleted file mode 100644
index 01be2cd..0000000
--- a/src/mainboard/google/veyron_jerry/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT	GPIO(7, A, 2)
-#define GPIO_RESET	GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif	/* __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H */
diff --git a/src/mainboard/google/veyron_jerry/boardid.c b/src/mainboard/google/veyron_jerry/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_jerry/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
-	static int id = -1;
-	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
-		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
-	if (id < 0) {
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-		printk(BIOS_SPEW, "Board ID: %d.\n", id);
-	}
-
-	return id;
-}
-
-uint32_t ram_code(void)
-{
-	uint32_t code;
-	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
-		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
-	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
-	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
-	return code;
-}
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
-	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
-		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
-		write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
-	}
-
-}
-
-void bootblock_mainboard_init(void)
-{
-	if (rkclk_was_watchdog_reset())
-		reboot_from_watchdog();
-
-	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
-	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
-	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	rk808_configure_buck(1, 1200);
-	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
-	rk808_configure_buck(1, 1400);
-	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
-
-	/* i2c1 for tpm */
-	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
-	i2c_init(1, 400*KHz);
-
-	/* spi2 for firmware ROM */
-	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
-	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
-	/* spi0 for chrome ec */
-	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
-	setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_jerry/chromeos.c b/src/mainboard/google/veyron_jerry/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_jerry/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-?/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP		GPIO(7, A, 6)
-#define GPIO_LID	GPIO(0, A, 6)
-#define GPIO_POWER	GPIO(0, A, 5)
-#define GPIO_RECOVERY	GPIO(0, B, 1)
-#define GPIO_ECINRW	GPIO(0, A, 7)
-#define GPIO_ECIRQ	GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
-	gpio_input(GPIO_WP);
-	gpio_input_pullup(GPIO_LID);
-	gpio_input(GPIO_POWER);
-	gpio_input_pullup(GPIO_RECOVERY);
-	gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	int count = 0;
-
-	/* Write Protect: active low */
-	gpios->gpios[count].port = GPIO_WP.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = gpio_get(GPIO_WP);
-	strncpy((char *)gpios->gpios[count].name, "write protect",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Recovery: active low */
-	gpios->gpios[count].port = GPIO_RECOVERY.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_recovery_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "recovery",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Lid: active high */
-	gpios->gpios[count].port = GPIO_LID.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Power:GPIO active high */
-	gpios->gpios[count].port = GPIO_POWER.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "power",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Developer: GPIO active high */
-	gpios->gpios[count].port = -1;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_developer_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "developer",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC in RW: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECINRW.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC in RW",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC interrupt: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECIRQ.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC interrupt",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Reset: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_RESET.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "reset",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Backlight: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "backlight",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
-	gpios->count = count;
-
-	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
-	return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
-	uint32_t ec_events;
-
-	/* The GPIO is active low. */
-	if (!gpio_get(GPIO_RECOVERY))
-		return 1;
-
-	ec_events = google_chromeec_get_events_b();
-	return !!(ec_events &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
-	return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_jerry/devicetree.cb b/src/mainboard/google/veyron_jerry/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_jerry/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
-	device cpu_cluster 0 on end
-	register "vop_id" = "1"
-	register "vop_mode" = "VOP_MODE_EDP"
-	register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c
deleted file mode 100644
index 2a945c4..0000000
--- a/src/mainboard/google/veyron_jerry/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
-	gpio_output(GPIO(0, B, 3), 1);			/* HOST1_PWR_EN */
-	gpio_output(GPIO(0, B, 4), 1);			/* USBOTG_PWREN_H */
-	gpio_output(GPIO(7, C, 5), 1);			/* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
-	write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
-	/* use sdmmc0 io, disable JTAG function */
-	write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
-	/* Note: these power rail definitions are copied in romstage.c */
-	rk808_configure_ldo(4, 3300); /* VCCIO_SD */
-	rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
-	gpio_input(GPIO(7, A, 5));		/* SD_DET */
-}
-
-static void configure_emmc(void)
-{
-	write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
-	write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
-	write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
-	gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
-	write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);	/* CODEC I2C */
-	i2c_init(2, 400*KHz);				/* CODEC I2C */
-
-	write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
-	write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
-	rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
-
-	/* AUDIO IO domain 1.8V voltage selection */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
-	rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
-	write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
-	/* lcdc(vop) iodomain select 1.8V */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
-	switch (board_id()) {
-	case 2:
-		rk808_configure_switch(2, 1);	/* VCC18_LCD */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 5), 1);	/* AVDD_1V8_DISP_EN */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		gpio_output(GPIO(7, B, 6), 1);	/* LCD_EN */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-
-		/* enable edp HPD */
-		gpio_input_pulldown(GPIO(7, B, 3));
-		write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
-		break;
-	}
-}
-
-static void mainboard_init(device_t dev)
-{
-	gpio_output(GPIO_RESET, 0);
-
-	configure_usb();
-	configure_sdmmc();
-	configure_emmc();
-	configure_codec();
-	configure_vop();
-
-	elog_init();
-	elog_add_watchdog_reset();
-	elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
-	struct lb_range *dma;
-
-	dma = (struct lb_range *)lb_new_record(header);
-	dma->tag = LB_TAB_DMA;
-	dma->size = sizeof(*dma);
-	dma->range_start = (uintptr_t)_dma_coherent;
-	dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
-	switch (board_id()) {
-	case 2:
-		gpio_output(GPIO(7, A, 0), 0);	/* BL_EN */
-		gpio_output(GPIO(7, A, 2), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO(7, A, 0), 1);	/* BL_EN */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 4), 1);	/* BL_PWR_EN */
-		mdelay(120);
-		gpio_output(GPIO(7, A, 0), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO_BACKLIGHT, 1);	/* BL_EN */
-		break;
-	}
-}
diff --git a/src/mainboard/google/veyron_jerry/memlayout.ld b/src/mainboard/google/veyron_jerry/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_jerry/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_jerry/reset.c b/src/mainboard/google/veyron_jerry/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_jerry/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
-	gpio_output(GPIO_RESET, 1);
-	while (1);
-}
diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c
deleted file mode 100644
index 5ccbe3e..0000000
--- a/src/mainboard/google/veyron_jerry/romstage.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
-	unsigned int duty_ns;
-	const u32 period_ns = 2000;	/* pwm period: 2000ns */
-	const u32 max_regulator_mv = 1350;	/* 1.35V */
-	const u32 min_regulator_mv = 870;	/* 0.87V */
-
-	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
-	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
-	duty_ns = (max_regulator_mv - mv) * period_ns /
-			(max_regulator_mv - min_regulator_mv);
-
-	pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
-	rk808_configure_ldo(4, 0); /* VCCIO_SD */
-	rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-	configure_l2ctlr();
-	tsadc_init();
-
-	/* Need to power cycle SD card to ensure it is properly reset. */
-	sdmmc_power_off();
-
-	/* vdd_log 1200mv is enough for ddr run 666Mhz */
-	regulate_vdd_log(1200);
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	sdram_init(get_sdram_config());
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
-	mmu_config_range((uintptr_t)_dram/MiB,
-			 sdram_size_mb(), DCACHE_WRITEBACK);
-	mmu_config_range((uintptr_t)_dma_coherent/MiB,
-			 _dma_coherent_size/MiB, DCACHE_OFF);
-
-	cbmem_initialize_empty();
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
-	run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron_jerry/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc"	/* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc"	/* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
-	u32 ramcode = ram_code();
-
-	if (ramcode >= ARRAY_SIZE(sdram_configs)
-			|| sdram_configs[ramcode].dramtype == UNUSED)
-		die("Invalid RAMCODE.");
-	return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 5b784cd..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynix H5TC8G63xxx chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Nanya NT5CC256M16DP chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4B4G1646D-BYK0 chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Samsung K4B8G1646Q chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA F8132A3MA-GD-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA FA232A2MA-GC-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 2 Hynix H9CCNNN8GTMLAR chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 14,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 3,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4E8E304ED-EGCE000 chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
-	.dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig
deleted file mode 100644
index 4dad49c..0000000
--- a/src/mainboard/google/veyron_mighty/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_MIGHTY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select BOARD_ID_AUTO
-	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select RAM_CODE_SUPPORT
-	select SOC_ROCKCHIP_RK3288
-	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_DO_NATIVE_VGA_INIT
-	select MAINBOARD_HAS_CHROMEOS
-	select BOARD_ROMSIZE_KB_4096
-	select HAVE_HARD_RESET
-	select SPI_FLASH
-	select SPI_FLASH_GIGADEVICE
-	select SPI_FLASH_WINBOND
-
-config CHROMEOS
-	select CHROMEOS_VBNV_EC
-	select EC_SOFTWARE_SYNC
-	select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
-	string
-	default google/veyron_mighty
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Veyron_Mighty"
-
-config MAINBOARD_VENDOR
-	string
-	default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
-	int
-	default 100
-
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 2
-
-config DRIVER_TPM_I2C_BUS
-	hex
-	default 0x1
-
-config DRIVER_TPM_I2C_ADDR
-	hex
-	default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	depends on DRIVERS_UART
-	default 0xFF690000
-
-config PMIC_BUS
-	int
-	default 0
-
-endif #  BOARD_GOOGLE_VEYRON_MIGHTY
diff --git a/src/mainboard/google/veyron_mighty/Kconfig.name b/src/mainboard/google/veyron_mighty/Kconfig.name
deleted file mode 100644
index 0eb4536..0000000
--- a/src/mainboard/google/veyron_mighty/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_MIGHTY
-	bool "Veyron_Mighty"
diff --git a/src/mainboard/google/veyron_mighty/Makefile.inc b/src/mainboard/google/veyron_mighty/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_mighty/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_mighty/board.h b/src/mainboard/google/veyron_mighty/board.h
deleted file mode 100644
index 909f9a7..0000000
--- a/src/mainboard/google/veyron_mighty/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT	GPIO(7, A, 2)
-#define GPIO_RESET	GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif	/* __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H */
diff --git a/src/mainboard/google/veyron_mighty/boardid.c b/src/mainboard/google/veyron_mighty/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_mighty/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
-	static int id = -1;
-	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
-		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
-	if (id < 0) {
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-		printk(BIOS_SPEW, "Board ID: %d.\n", id);
-	}
-
-	return id;
-}
-
-uint32_t ram_code(void)
-{
-	uint32_t code;
-	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
-		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
-	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
-	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
-	return code;
-}
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
-	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
-		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
-		write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
-	}
-
-}
-
-void bootblock_mainboard_init(void)
-{
-	if (rkclk_was_watchdog_reset())
-		reboot_from_watchdog();
-
-	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
-	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
-	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	rk808_configure_buck(1, 1200);
-	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
-	rk808_configure_buck(1, 1400);
-	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
-
-	/* i2c1 for tpm */
-	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
-	i2c_init(1, 400*KHz);
-
-	/* spi2 for firmware ROM */
-	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
-	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
-	/* spi0 for chrome ec */
-	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
-	setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_mighty/chromeos.c b/src/mainboard/google/veyron_mighty/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_mighty/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-?/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP		GPIO(7, A, 6)
-#define GPIO_LID	GPIO(0, A, 6)
-#define GPIO_POWER	GPIO(0, A, 5)
-#define GPIO_RECOVERY	GPIO(0, B, 1)
-#define GPIO_ECINRW	GPIO(0, A, 7)
-#define GPIO_ECIRQ	GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
-	gpio_input(GPIO_WP);
-	gpio_input_pullup(GPIO_LID);
-	gpio_input(GPIO_POWER);
-	gpio_input_pullup(GPIO_RECOVERY);
-	gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	int count = 0;
-
-	/* Write Protect: active low */
-	gpios->gpios[count].port = GPIO_WP.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = gpio_get(GPIO_WP);
-	strncpy((char *)gpios->gpios[count].name, "write protect",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Recovery: active low */
-	gpios->gpios[count].port = GPIO_RECOVERY.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_recovery_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "recovery",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Lid: active high */
-	gpios->gpios[count].port = GPIO_LID.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Power:GPIO active high */
-	gpios->gpios[count].port = GPIO_POWER.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "power",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Developer: GPIO active high */
-	gpios->gpios[count].port = -1;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_developer_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "developer",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC in RW: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECINRW.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC in RW",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC interrupt: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECIRQ.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC interrupt",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Reset: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_RESET.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "reset",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Backlight: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "backlight",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
-	gpios->count = count;
-
-	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
-	return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
-	uint32_t ec_events;
-
-	/* The GPIO is active low. */
-	if (!gpio_get(GPIO_RECOVERY))
-		return 1;
-
-	ec_events = google_chromeec_get_events_b();
-	return !!(ec_events &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
-	return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_mighty/devicetree.cb b/src/mainboard/google/veyron_mighty/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_mighty/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
-	device cpu_cluster 0 on end
-	register "vop_id" = "1"
-	register "vop_mode" = "VOP_MODE_EDP"
-	register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_mighty/mainboard.c b/src/mainboard/google/veyron_mighty/mainboard.c
deleted file mode 100644
index d76e2e5..0000000
--- a/src/mainboard/google/veyron_mighty/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
-	gpio_output(GPIO(0, B, 3), 1);			/* HOST1_PWR_EN */
-	gpio_output(GPIO(0, B, 4), 1);			/* USBOTG_PWREN_H */
-	gpio_output(GPIO(7, C, 5), 1);			/* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
-	write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
-	/* use sdmmc0 io, disable JTAG function */
-	write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
-	/* Note: these power rail definitions are copied in romstage.c */
-	rk808_configure_ldo(4, 3300); /* VCCIO_SD */
-	rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
-	gpio_input(GPIO(7, A, 5));		/* SD_DET */
-}
-
-static void configure_emmc(void)
-{
-	write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
-	write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
-	write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
-	gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
-	write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);	/* CODEC I2C */
-	i2c_init(2, 400*KHz);				/* CODEC I2C */
-
-	write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
-	write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
-	rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
-
-	/* AUDIO IO domain 1.8V voltage selection */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
-	rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
-	write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
-	/* lcdc(vop) iodomain select 1.8V */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
-	switch (board_id()) {
-	case 0:
-		rk808_configure_switch(2, 1);	/* VCC18_LCD */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 5), 1);	/* AVDD_1V8_DISP_EN */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		gpio_output(GPIO(7, B, 6), 1);	/* LCD_EN */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-
-		/* enable edp HPD */
-		gpio_input_pulldown(GPIO(7, B, 3));
-		write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
-		break;
-	}
-}
-
-static void mainboard_init(device_t dev)
-{
-	gpio_output(GPIO_RESET, 0);
-
-	configure_usb();
-	configure_sdmmc();
-	configure_emmc();
-	configure_codec();
-	configure_vop();
-
-	elog_init();
-	elog_add_watchdog_reset();
-	elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
-	struct lb_range *dma;
-
-	dma = (struct lb_range *)lb_new_record(header);
-	dma->tag = LB_TAB_DMA;
-	dma->size = sizeof(*dma);
-	dma->range_start = (uintptr_t)_dma_coherent;
-	dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
-	switch (board_id()) {
-	case 0:
-		gpio_output(GPIO(7, A, 0), 0);	/* BL_EN */
-		gpio_output(GPIO(7, A, 2), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO(7, A, 0), 1);	/* BL_EN */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 4), 1);	/* BL_PWR_EN */
-		mdelay(20);
-		gpio_output(GPIO(7, A, 0), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO_BACKLIGHT, 1);	/* BL_EN */
-		break;
-	}
-}
diff --git a/src/mainboard/google/veyron_mighty/memlayout.ld b/src/mainboard/google/veyron_mighty/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_mighty/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_mighty/reset.c b/src/mainboard/google/veyron_mighty/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_mighty/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
-	gpio_output(GPIO_RESET, 1);
-	while (1);
-}
diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c
deleted file mode 100644
index 5ccbe3e..0000000
--- a/src/mainboard/google/veyron_mighty/romstage.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
-	unsigned int duty_ns;
-	const u32 period_ns = 2000;	/* pwm period: 2000ns */
-	const u32 max_regulator_mv = 1350;	/* 1.35V */
-	const u32 min_regulator_mv = 870;	/* 0.87V */
-
-	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
-	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
-	duty_ns = (max_regulator_mv - mv) * period_ns /
-			(max_regulator_mv - min_regulator_mv);
-
-	pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
-	rk808_configure_ldo(4, 0); /* VCCIO_SD */
-	rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-	configure_l2ctlr();
-	tsadc_init();
-
-	/* Need to power cycle SD card to ensure it is properly reset. */
-	sdmmc_power_off();
-
-	/* vdd_log 1200mv is enough for ddr run 666Mhz */
-	regulate_vdd_log(1200);
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	sdram_init(get_sdram_config());
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
-	mmu_config_range((uintptr_t)_dram/MiB,
-			 sdram_size_mb(), DCACHE_WRITEBACK);
-	mmu_config_range((uintptr_t)_dma_coherent/MiB,
-			 _dma_coherent_size/MiB, DCACHE_OFF);
-
-	cbmem_initialize_empty();
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
-	run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_mighty/sdram_configs.c b/src/mainboard/google/veyron_mighty/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc"	/* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc"	/* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
-	u32 ramcode = ram_code();
-
-	if (ramcode >= ARRAY_SIZE(sdram_configs)
-			|| sdram_configs[ramcode].dramtype == UNUSED)
-		die("Invalid RAMCODE.");
-	return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynix H5TC8G63xxx chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Nanya NT5CC256M16DP chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4B4G1646D-BYK0 chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Samsung K4B8G1646Q chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA F8132A3MA-GD-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA FA232A2MA-GC-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 2 Hynix H9CCNNN8GTMLAR chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 14,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 3,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4E8E304ED-EGCE000 chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
-	.dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_minnie/Kconfig b/src/mainboard/google/veyron_minnie/Kconfig
deleted file mode 100644
index f2cd87b..0000000
--- a/src/mainboard/google/veyron_minnie/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_MINNIE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select BOARD_ID_AUTO
-	select BOARD_ROMSIZE_KB_4096
-	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select RAM_CODE_SUPPORT
-	select SOC_ROCKCHIP_RK3288
-	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_DO_NATIVE_VGA_INIT
-	select MAINBOARD_HAS_CHROMEOS
-	select HAVE_HARD_RESET
-	select SPI_FLASH
-	select SPI_FLASH_GIGADEVICE
-	select SPI_FLASH_WINBOND
-
-config CHROMEOS
-	select CHROMEOS_VBNV_EC
-	select EC_SOFTWARE_SYNC
-	select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
-	string
-	default google/veyron_minnie
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Veyron_Minnie"
-
-config MAINBOARD_VENDOR
-	string
-	default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
-	int
-	default 100
-
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 2
-
-config DRIVER_TPM_I2C_BUS
-	hex
-	default 0x1
-
-config DRIVER_TPM_I2C_ADDR
-	hex
-	default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	depends on DRIVERS_UART
-	default 0xFF690000
-
-config PMIC_BUS
-	int
-	default 0
-
-endif #  BOARD_GOOGLE_VEYRON_MINNIE
diff --git a/src/mainboard/google/veyron_minnie/Kconfig.name b/src/mainboard/google/veyron_minnie/Kconfig.name
deleted file mode 100644
index bb7b75e..0000000
--- a/src/mainboard/google/veyron_minnie/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_MINNIE
-	bool "Veyron_Minnie"
diff --git a/src/mainboard/google/veyron_minnie/Makefile.inc b/src/mainboard/google/veyron_minnie/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_minnie/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_minnie/board.h b/src/mainboard/google/veyron_minnie/board.h
deleted file mode 100644
index 07b302b..0000000
--- a/src/mainboard/google/veyron_minnie/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT	GPIO(7, A, 2)
-#define GPIO_RESET	GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif	/* __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H */
diff --git a/src/mainboard/google/veyron_minnie/board_info.txt b/src/mainboard/google/veyron_minnie/board_info.txt
deleted file mode 100644
index 4ce92d3..0000000
--- a/src/mainboard/google/veyron_minnie/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: laptop
diff --git a/src/mainboard/google/veyron_minnie/boardid.c b/src/mainboard/google/veyron_minnie/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_minnie/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
-	static int id = -1;
-	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
-		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
-	if (id < 0) {
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-		printk(BIOS_SPEW, "Board ID: %d.\n", id);
-	}
-
-	return id;
-}
-
-uint32_t ram_code(void)
-{
-	uint32_t code;
-	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
-		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
-	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
-	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
-	return code;
-}
diff --git a/src/mainboard/google/veyron_minnie/bootblock.c b/src/mainboard/google/veyron_minnie/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_minnie/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
-	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
-		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
-		write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
-	}
-
-}
-
-void bootblock_mainboard_init(void)
-{
-	if (rkclk_was_watchdog_reset())
-		reboot_from_watchdog();
-
-	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
-	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
-	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	rk808_configure_buck(1, 1200);
-	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
-	rk808_configure_buck(1, 1400);
-	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
-
-	/* i2c1 for tpm */
-	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
-	i2c_init(1, 400*KHz);
-
-	/* spi2 for firmware ROM */
-	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
-	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
-	/* spi0 for chrome ec */
-	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
-	setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_minnie/chromeos.c b/src/mainboard/google/veyron_minnie/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_minnie/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-?/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP		GPIO(7, A, 6)
-#define GPIO_LID	GPIO(0, A, 6)
-#define GPIO_POWER	GPIO(0, A, 5)
-#define GPIO_RECOVERY	GPIO(0, B, 1)
-#define GPIO_ECINRW	GPIO(0, A, 7)
-#define GPIO_ECIRQ	GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
-	gpio_input(GPIO_WP);
-	gpio_input_pullup(GPIO_LID);
-	gpio_input(GPIO_POWER);
-	gpio_input_pullup(GPIO_RECOVERY);
-	gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	int count = 0;
-
-	/* Write Protect: active low */
-	gpios->gpios[count].port = GPIO_WP.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = gpio_get(GPIO_WP);
-	strncpy((char *)gpios->gpios[count].name, "write protect",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Recovery: active low */
-	gpios->gpios[count].port = GPIO_RECOVERY.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_recovery_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "recovery",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Lid: active high */
-	gpios->gpios[count].port = GPIO_LID.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Power:GPIO active high */
-	gpios->gpios[count].port = GPIO_POWER.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "power",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Developer: GPIO active high */
-	gpios->gpios[count].port = -1;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_developer_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "developer",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC in RW: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECINRW.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC in RW",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC interrupt: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECIRQ.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC interrupt",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Reset: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_RESET.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "reset",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Backlight: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "backlight",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
-	gpios->count = count;
-
-	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
-	return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
-	uint32_t ec_events;
-
-	/* The GPIO is active low. */
-	if (!gpio_get(GPIO_RECOVERY))
-		return 1;
-
-	ec_events = google_chromeec_get_events_b();
-	return !!(ec_events &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
-	return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_minnie/devicetree.cb b/src/mainboard/google/veyron_minnie/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_minnie/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
-	device cpu_cluster 0 on end
-	register "vop_id" = "1"
-	register "vop_mode" = "VOP_MODE_EDP"
-	register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_minnie/mainboard.c b/src/mainboard/google/veyron_minnie/mainboard.c
deleted file mode 100644
index 0de89af..0000000
--- a/src/mainboard/google/veyron_minnie/mainboard.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
-	gpio_output(GPIO(0, B, 3), 1);			/* HOST1_PWR_EN */
-	gpio_output(GPIO(0, B, 4), 1);			/* USBOTG_PWREN_H */
-	gpio_output(GPIO(7, C, 5), 1);			/* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
-	write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
-	/* use sdmmc0 io, disable JTAG function */
-	write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
-	/* Note: these power rail definitions are copied in romstage.c */
-	rk808_configure_ldo(4, 3300); /* VCCIO_SD */
-	rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
-	gpio_input(GPIO(7, A, 5));		/* SD_DET */
-}
-
-static void configure_emmc(void)
-{
-	write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
-	write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
-	write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
-	gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
-	write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);	/* CODEC I2C */
-	i2c_init(2, 400*KHz);				/* CODEC I2C */
-
-	write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
-	write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
-	rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
-
-	/* AUDIO IO domain 1.8V voltage selection */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
-	rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
-	write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
-	/* lcdc(vop) iodomain select 1.8V */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
-	gpio_output(GPIO(2, B, 5), 1);	/* AVDD_1V8_DISP_EN */
-	rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-	gpio_output(GPIO(7, B, 6), 1);	/* LCD_EN */
-	rk808_configure_switch(1, 1);	/* VCC33_LCD */
-
-	/* enable edp HPD */
-	gpio_input_pulldown(GPIO(7, B, 3));
-	write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
-}
-
-static void mainboard_init(device_t dev)
-{
-	gpio_output(GPIO_RESET, 0);
-
-	configure_usb();
-	configure_sdmmc();
-	configure_emmc();
-	configure_codec();
-	configure_vop();
-
-	elog_init();
-	elog_add_watchdog_reset();
-	elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
-	struct lb_range *dma;
-
-	dma = (struct lb_range *)lb_new_record(header);
-	dma->tag = LB_TAB_DMA;
-	dma->size = sizeof(*dma);
-	dma->range_start = (uintptr_t)_dma_coherent;
-	dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
-	gpio_output(GPIO(2, B, 4), 1);	/* BL_PWR_EN */
-	mdelay(20);
-	gpio_output(GPIO(7, A, 0), 1);	/* LCD_BL */
-	mdelay(10);
-	gpio_output(GPIO_BACKLIGHT, 1);	/* BL_EN */
-}
diff --git a/src/mainboard/google/veyron_minnie/memlayout.ld b/src/mainboard/google/veyron_minnie/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_minnie/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_minnie/reset.c b/src/mainboard/google/veyron_minnie/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_minnie/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
-	gpio_output(GPIO_RESET, 1);
-	while (1);
-}
diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c
deleted file mode 100644
index 9cdacc3..0000000
--- a/src/mainboard/google/veyron_minnie/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
-	unsigned int duty_ns;
-	const u32 period_ns = 2000;	/* pwm period: 2000ns */
-	const u32 max_regulator_mv = 1350;	/* 1.35V */
-	const u32 min_regulator_mv = 870;	/* 0.87V */
-
-	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
-	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
-	duty_ns = (max_regulator_mv - mv) * period_ns /
-			(max_regulator_mv - min_regulator_mv);
-
-	pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
-	rk808_configure_ldo(4, 0); /* VCCIO_SD */
-	rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-	configure_l2ctlr();
-	tsadc_init();
-
-	/* Need to power cycle SD card to ensure it is properly reset. */
-	sdmmc_power_off();
-
-	/* vdd_log 1200mv is enough for ddr run 666Mhz */
-	regulate_vdd_log(1200);
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	sdram_init(get_sdram_config());
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
-	mmu_config_range((uintptr_t)_dram/MiB,
-			 sdram_size_mb(), DCACHE_WRITEBACK);
-	mmu_config_range((uintptr_t)_dma_coherent/MiB,
-			 _dma_coherent_size/MiB, DCACHE_OFF);
-
-	cbmem_initialize_empty();
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
-	run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_minnie/sdram_configs.c b/src/mainboard/google/veyron_minnie/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc"	/* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc"	/* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
-	u32 ramcode = ram_code();
-
-	if (ramcode >= ARRAY_SIZE(sdram_configs)
-			|| sdram_configs[ramcode].dramtype == UNUSED)
-		die("Invalid RAMCODE.");
-	return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynix H5TC8G63xxx chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Nanya NT5CC256M16DP chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4B4G1646D-BYK0 chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Samsung K4B8G1646Q chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA F8132A3MA-GD-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA FA232A2MA-GC-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 2 Hynix H9CCNNN8GTMLAR chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 14,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 3,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4E8E304ED-EGCE000 chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
-	.dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig
deleted file mode 100644
index 5c6e7cd..0000000
--- a/src/mainboard/google/veyron_pinky/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_PINKY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select BOARD_ID_AUTO
-	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select RAM_CODE_SUPPORT
-	select SOC_ROCKCHIP_RK3288
-	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_DO_NATIVE_VGA_INIT
-	select MAINBOARD_HAS_CHROMEOS
-	select BOARD_ROMSIZE_KB_4096
-	select HAVE_HARD_RESET
-	select SPI_FLASH
-	select SPI_FLASH_GIGADEVICE
-	select SPI_FLASH_WINBOND
-
-config CHROMEOS
-	select CHROMEOS_VBNV_EC
-	select EC_SOFTWARE_SYNC
-	select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
-	string
-	default google/veyron_pinky
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Veyron_Pinky"
-
-config MAINBOARD_VENDOR
-	string
-	default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
-	int
-	default 100
-
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 2
-
-config DRIVER_TPM_I2C_BUS
-	hex
-	default 0x1
-
-config DRIVER_TPM_I2C_ADDR
-	hex
-	default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	depends on DRIVERS_UART
-	default 0xFF690000
-
-config PMIC_BUS
-	int
-	default 0
-
-endif #  BOARD_GOOGLE_VEYRON_PINKY
diff --git a/src/mainboard/google/veyron_pinky/Kconfig.name b/src/mainboard/google/veyron_pinky/Kconfig.name
deleted file mode 100644
index 37d92f2..0000000
--- a/src/mainboard/google/veyron_pinky/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_PINKY
-	bool "Veyron_Pinky"
diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc
deleted file mode 100644
index a41b3bf..0000000
--- a/src/mainboard/google/veyron_pinky/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += romstage.c
-romstage-y += chromeos.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_pinky/board.h b/src/mainboard/google/veyron_pinky/board.h
deleted file mode 100644
index 24690df..0000000
--- a/src/mainboard/google/veyron_pinky/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT	GPIO(7, A, 2)
-#define GPIO_RESET	(board_id() > 0 ? GPIO(0, B, 5) : GPIO(0, B, 2))
-
-void setup_chromeos_gpios(void);
-
-#endif	/* __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H */
diff --git a/src/mainboard/google/veyron_pinky/boardid.c b/src/mainboard/google/veyron_pinky/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_pinky/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
-	static int id = -1;
-	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
-		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
-	if (id < 0) {
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-		printk(BIOS_SPEW, "Board ID: %d.\n", id);
-	}
-
-	return id;
-}
-
-uint32_t ram_code(void)
-{
-	uint32_t code;
-	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
-		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
-	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
-	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
-	return code;
-}
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
-	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
-		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
-		write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
-	}
-
-}
-
-void bootblock_mainboard_init(void)
-{
-	if (rkclk_was_watchdog_reset())
-		reboot_from_watchdog();
-
-	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
-	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
-	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	rk808_configure_buck(1, 1200);
-	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
-	rk808_configure_buck(1, 1400);
-	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
-
-	/* i2c1 for tpm */
-	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
-	i2c_init(1, 400*KHz);
-
-	/* spi2 for firmware ROM */
-	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
-	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
-	/* spi0 for chrome ec */
-	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
-	setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c
deleted file mode 100644
index 5e81dad..0000000
--- a/src/mainboard/google/veyron_pinky/chromeos.c
+++ /dev/null
@@ -1,149 +0,0 @@
-?/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP		GPIO(7, A, 6)
-#define GPIO_LID	(board_id() > 0 ? GPIO(0, A, 6) : GPIO(7, B, 5))
-#define GPIO_POWER	GPIO(0, A, 5)
-#define GPIO_RECOVERY	GPIO(0, B, 1)
-#define GPIO_ECINRW	GPIO(0, A, 7)
-#define GPIO_ECIRQ	GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
-	gpio_input(GPIO_WP);
-	gpio_input_pullup(GPIO_LID);
-	gpio_input(GPIO_POWER);
-	gpio_input_pullup(GPIO_RECOVERY);
-	gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	int count = 0;
-
-	/* Write Protect: active low */
-	gpios->gpios[count].port = GPIO_WP.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = gpio_get(GPIO_WP);
-	strncpy((char *)gpios->gpios[count].name, "write protect",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Recovery: active low */
-	gpios->gpios[count].port = GPIO_RECOVERY.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_recovery_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "recovery",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Lid: active high */
-	gpios->gpios[count].port = GPIO_LID.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Power:GPIO active high */
-	gpios->gpios[count].port = GPIO_POWER.raw;
-	gpios->gpios[count].polarity = board_id() > 1 ? ACTIVE_LOW :
-							ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "power",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Developer: GPIO active high */
-	gpios->gpios[count].port = -1;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_developer_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "developer",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC in RW: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECINRW.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC in RW",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC interrupt: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECIRQ.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC interrupt",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Reset: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_RESET.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "reset",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Backlight: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "backlight",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
-	gpios->count = count;
-
-	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
-	return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
-	uint32_t ec_events;
-
-	/* The GPIO is active low. */
-	if (!gpio_get(GPIO_RECOVERY))
-		return 1;
-
-	ec_events = google_chromeec_get_events_b();
-	return !!(ec_events &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
-	return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_pinky/devicetree.cb b/src/mainboard/google/veyron_pinky/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_pinky/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
-	device cpu_cluster 0 on end
-	register "vop_id" = "1"
-	register "vop_mode" = "VOP_MODE_EDP"
-	register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
deleted file mode 100644
index 2caa2be..0000000
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
-	gpio_output(GPIO(0, B, 3), 1);			/* HOST1_PWR_EN */
-	gpio_output(GPIO(0, B, 4), 1);			/* USBOTG_PWREN_H */
-
-	switch (board_id()) {
-	case 0:
-		gpio_output(GPIO(7, B, 3), 1);		/* 5V_DRV */
-		break;
-	case 1:
-		break;	/* 5V_DRV moved to EC in rev2 */
-	default:
-		gpio_output(GPIO(7, C, 5), 1);		/* 5V_DRV, again */
-		break;
-	}
-}
-
-static void configure_sdmmc(void)
-{
-	write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
-	/* use sdmmc0 io, disable JTAG function */
-	write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
-	/* Note: these power rail definitions are copied in romstage.c */
-	switch (board_id()) {
-	case 0:
-		rk808_configure_ldo(8, 3300);	/* VCCIO_SD */
-		gpio_output(GPIO(7, C, 5), 1);		/* SD_EN */
-		break;
-	default:
-		rk808_configure_ldo(4, 3300); /* VCCIO_SD */
-		rk808_configure_ldo(5, 3300); /* VCC33_SD */
-		break;
-	}
-
-	gpio_input(GPIO(7, A, 5));		/* SD_DET */
-}
-
-static void configure_emmc(void)
-{
-	write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
-	write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
-	write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
-	switch (board_id()) {
-	case 0:
-	case 1:
-	/*
-	 * Use a pullup instead of a drive since the output is 3.3V and
-	 * really should be 1.8V (oops).  The external pulldown will help
-	 * bring the voltage down if we only drive with a pullup here.
-	 */
-		gpio_input_pullup(GPIO(7, B, 4));	/* EMMC_RST_L */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
-		break;
-	}
-}
-
-static void configure_codec(void)
-{
-	write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);	/* CODEC I2C */
-	i2c_init(2, 400*KHz);				/* CODEC I2C */
-
-	write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
-	write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
-	switch (board_id()) {
-	case 0:
-		rk808_configure_ldo(5, 1800);	/* VCC18_CODEC */
-		break;
-	default:
-		rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
-		break;
-	}
-
-	/* AUDIO IO domain 1.8V voltage selection */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
-	rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
-	write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
-	/* lcdc(vop) iodomain select 1.8V */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
-	switch (board_id()) {
-	case 0:
-		rk808_configure_ldo(4, 1800); /* VCC18_LCD */
-		rk808_configure_ldo(6, 1000); /* VCC10_LCD */
-		gpio_output(GPIO(7, B, 7), 1); /* LCD_EN */
-		break;
-	case 1:
-	case 2:
-		rk808_configure_switch(2, 1);	/* VCC18_LCD */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 5), 1);	/* AVDD_1V8_DISP_EN */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-		gpio_output(GPIO(7, B, 6), 1);	/* LCD_EN */
-
-		/* enable edp HPD */
-		gpio_input_pulldown(GPIO(7, B, 3));
-		write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
-		break;
-	}
-}
-
-static void mainboard_init(device_t dev)
-{
-	gpio_output(GPIO_RESET, 0);
-
-	configure_usb();
-	configure_sdmmc();
-	configure_emmc();
-	configure_codec();
-	configure_vop();
-
-	elog_init();
-	elog_add_watchdog_reset();
-	elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
-	struct lb_range *dma;
-
-	dma = (struct lb_range *)lb_new_record(header);
-	dma->tag = LB_TAB_DMA;
-	dma->size = sizeof(*dma);
-	dma->range_start = (uintptr_t)_dma_coherent;
-	dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
-	switch (board_id()) {
-	case 0:
-	case 1:
-	case 2:
-		gpio_output(GPIO(7, A, 0), 0);	/* BL_EN */
-		gpio_output(GPIO(7, A, 2), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO(7, A, 0), 1);	/* BL_EN */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 4), 1);	/* BL_PWR_EN */
-		mdelay(20);
-		gpio_output(GPIO(7, A, 0), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO_BACKLIGHT, 1);	/* BL_EN */
-		break;
-	}
-}
diff --git a/src/mainboard/google/veyron_pinky/memlayout.ld b/src/mainboard/google/veyron_pinky/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_pinky/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_pinky/reset.c b/src/mainboard/google/veyron_pinky/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_pinky/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
-	gpio_output(GPIO_RESET, 1);
-	while (1);
-}
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c
deleted file mode 100644
index 3792e62..0000000
--- a/src/mainboard/google/veyron_pinky/romstage.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
-	unsigned int duty_ns;
-	const u32 period_ns = 2000;	/* pwm period: 2000ns */
-	const u32 max_regulator_mv = 1350;	/* 1.35V */
-	const u32 min_regulator_mv = 870;	/* 0.87V */
-
-	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
-	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
-	duty_ns = (max_regulator_mv - mv) * period_ns /
-			(max_regulator_mv - min_regulator_mv);
-
-	pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
-	switch (board_id()) {
-	case 0:
-		rk808_configure_ldo(8, 0);	/* VCCIO_SD */
-		gpio_output(GPIO(7, C, 5), 0);		/* SD_EN */
-		break;
-	default:
-		rk808_configure_ldo(4, 0); /* VCCIO_SD */
-		rk808_configure_ldo(5, 0); /* VCC33_SD */
-		break;
-	}
-}
-
-void main(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-	configure_l2ctlr();
-	tsadc_init();
-
-	/* Need to power cycle SD card to ensure it is properly reset. */
-	sdmmc_power_off();
-
-	/* vdd_log 1200mv is enough for ddr run 666Mhz */
-	regulate_vdd_log(1200);
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	sdram_init(get_sdram_config());
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
-	mmu_config_range((uintptr_t)_dram/MiB,
-			 sdram_size_mb(), DCACHE_WRITEBACK);
-	mmu_config_range((uintptr_t)_dma_coherent/MiB,
-			 _dma_coherent_size/MiB, DCACHE_OFF);
-
-	cbmem_initialize_empty();
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
-	run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc"	/* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc"	/* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
-	u32 ramcode = ram_code();
-
-	if (ramcode >= ARRAY_SIZE(sdram_configs)
-			|| sdram_configs[ramcode].dramtype == UNUSED)
-		die("Invalid RAMCODE.");
-	return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynix H5TC8G63xxx chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Nanya NT5CC256M16DP chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4B4G1646D-BYK0 chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Samsung K4B8G1646Q chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA F8132A3MA-GD-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA FA232A2MA-GC-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 2 Hynix H9CCNNN8GTMLAR chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 14,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 3,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4E8E304ED-EGCE000 chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
-	.dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_shark/Kconfig b/src/mainboard/google/veyron_shark/Kconfig
deleted file mode 100644
index 829fb85..0000000
--- a/src/mainboard/google/veyron_shark/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_SHARK
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select BOARD_ID_AUTO
-	select BOARD_ROMSIZE_KB_4096
-	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select RAM_CODE_SUPPORT
-	select SOC_ROCKCHIP_RK3288
-	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_DO_NATIVE_VGA_INIT
-	select MAINBOARD_HAS_CHROMEOS
-	select HAVE_HARD_RESET
-	select SPI_FLASH
-	select SPI_FLASH_GIGADEVICE
-	select SPI_FLASH_WINBOND
-
-config CHROMEOS
-	select CHROMEOS_VBNV_EC
-	select EC_SOFTWARE_SYNC
-	select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
-	string
-	default google/veyron_shark
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Veyron_Shark"
-
-config MAINBOARD_VENDOR
-	string
-	default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
-	int
-	default 100
-
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 2
-
-config DRIVER_TPM_I2C_BUS
-	hex
-	default 0x1
-
-config DRIVER_TPM_I2C_ADDR
-	hex
-	default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	depends on DRIVERS_UART
-	default 0xFF690000
-
-config PMIC_BUS
-	int
-	default 0
-
-endif #  BOARD_GOOGLE_VEYRON_SHARK
diff --git a/src/mainboard/google/veyron_shark/Kconfig.name b/src/mainboard/google/veyron_shark/Kconfig.name
deleted file mode 100644
index 16c82a9..0000000
--- a/src/mainboard/google/veyron_shark/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_SHARK
-	bool "Veyron_Shark"
diff --git a/src/mainboard/google/veyron_shark/Makefile.inc b/src/mainboard/google/veyron_shark/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_shark/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_shark/board.h b/src/mainboard/google/veyron_shark/board.h
deleted file mode 100644
index 47bbbdf..0000000
--- a/src/mainboard/google/veyron_shark/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT	GPIO(7, A, 2)
-#define GPIO_RESET	GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif	/* __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H */
diff --git a/src/mainboard/google/veyron_shark/boardid.c b/src/mainboard/google/veyron_shark/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_shark/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
-	static int id = -1;
-	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
-		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
-	if (id < 0) {
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-		printk(BIOS_SPEW, "Board ID: %d.\n", id);
-	}
-
-	return id;
-}
-
-uint32_t ram_code(void)
-{
-	uint32_t code;
-	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
-		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
-	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
-	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
-	return code;
-}
diff --git a/src/mainboard/google/veyron_shark/bootblock.c b/src/mainboard/google/veyron_shark/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_shark/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
-	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
-		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
-		write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
-	}
-
-}
-
-void bootblock_mainboard_init(void)
-{
-	if (rkclk_was_watchdog_reset())
-		reboot_from_watchdog();
-
-	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
-	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
-	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	rk808_configure_buck(1, 1200);
-	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
-	rk808_configure_buck(1, 1400);
-	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
-
-	/* i2c1 for tpm */
-	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
-	i2c_init(1, 400*KHz);
-
-	/* spi2 for firmware ROM */
-	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
-	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
-	/* spi0 for chrome ec */
-	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
-	setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_shark/chromeos.c b/src/mainboard/google/veyron_shark/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_shark/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-?/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP		GPIO(7, A, 6)
-#define GPIO_LID	GPIO(0, A, 6)
-#define GPIO_POWER	GPIO(0, A, 5)
-#define GPIO_RECOVERY	GPIO(0, B, 1)
-#define GPIO_ECINRW	GPIO(0, A, 7)
-#define GPIO_ECIRQ	GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
-	gpio_input(GPIO_WP);
-	gpio_input_pullup(GPIO_LID);
-	gpio_input(GPIO_POWER);
-	gpio_input_pullup(GPIO_RECOVERY);
-	gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	int count = 0;
-
-	/* Write Protect: active low */
-	gpios->gpios[count].port = GPIO_WP.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = gpio_get(GPIO_WP);
-	strncpy((char *)gpios->gpios[count].name, "write protect",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Recovery: active low */
-	gpios->gpios[count].port = GPIO_RECOVERY.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_recovery_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "recovery",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Lid: active high */
-	gpios->gpios[count].port = GPIO_LID.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Power:GPIO active high */
-	gpios->gpios[count].port = GPIO_POWER.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "power",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Developer: GPIO active high */
-	gpios->gpios[count].port = -1;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_developer_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "developer",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC in RW: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECINRW.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC in RW",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC interrupt: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECIRQ.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC interrupt",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Reset: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_RESET.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "reset",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Backlight: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "backlight",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
-	gpios->count = count;
-
-	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
-	return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
-	uint32_t ec_events;
-
-	/* The GPIO is active low. */
-	if (!gpio_get(GPIO_RECOVERY))
-		return 1;
-
-	ec_events = google_chromeec_get_events_b();
-	return !!(ec_events &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
-	return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_shark/devicetree.cb b/src/mainboard/google/veyron_shark/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_shark/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
-	device cpu_cluster 0 on end
-	register "vop_id" = "1"
-	register "vop_mode" = "VOP_MODE_EDP"
-	register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_shark/mainboard.c b/src/mainboard/google/veyron_shark/mainboard.c
deleted file mode 100644
index c8cb248..0000000
--- a/src/mainboard/google/veyron_shark/mainboard.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
-	gpio_output(GPIO(0, B, 3), 1);			/* HOST1_PWR_EN */
-	gpio_output(GPIO(0, B, 4), 1);			/* USBOTG_PWREN_H */
-	gpio_output(GPIO(7, C, 5), 1);			/* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
-	write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
-	/* use sdmmc0 io, disable JTAG function */
-	write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
-	/* Note: these power rail definitions are copied in romstage.c */
-	rk808_configure_ldo(4, 3300); /* VCCIO_SD */
-	rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
-	gpio_input(GPIO(7, A, 5));		/* SD_DET */
-}
-
-static void configure_emmc(void)
-{
-	write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
-	write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
-	write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
-	gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
-	write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);	/* CODEC I2C */
-	i2c_init(2, 400*KHz);				/* CODEC I2C */
-
-	write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
-	write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
-	rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
-
-	/* AUDIO IO domain 1.8V voltage selection */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
-	rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
-	write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
-	/* lcdc(vop) iodomain select 1.8V */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
-	switch (board_id()) {
-	case 0:
-		rk808_configure_switch(2, 1);	/* VCC18_LCD */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 5), 1);	/* AVDD_1V8_DISP_EN */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		gpio_output(GPIO(7, B, 6), 1);	/* LCD_EN */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-
-		/* enable edp HPD */
-		gpio_input_pulldown(GPIO(7, B, 3));
-		write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
-		break;
-	}
-}
-
-static void mainboard_init(device_t dev)
-{
-	gpio_output(GPIO_RESET, 0);
-
-	configure_usb();
-	configure_sdmmc();
-	configure_emmc();
-	configure_codec();
-	configure_vop();
-
-	elog_init();
-	elog_add_watchdog_reset();
-	elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
-	struct lb_range *dma;
-
-	dma = (struct lb_range *)lb_new_record(header);
-	dma->tag = LB_TAB_DMA;
-	dma->size = sizeof(*dma);
-	dma->range_start = (uintptr_t)_dma_coherent;
-	dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
-	gpio_output(GPIO(2, B, 4), 1);	/* BL_PWR_EN */
-	mdelay(20);
-	gpio_output(GPIO(7, A, 0), 1);	/* LCD_BL */
-	mdelay(10);
-	gpio_output(GPIO_BACKLIGHT, 1);	/* BL_EN */
-}
diff --git a/src/mainboard/google/veyron_shark/memlayout.ld b/src/mainboard/google/veyron_shark/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_shark/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_shark/reset.c b/src/mainboard/google/veyron_shark/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_shark/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
-	gpio_output(GPIO_RESET, 1);
-	while (1);
-}
diff --git a/src/mainboard/google/veyron_shark/romstage.c b/src/mainboard/google/veyron_shark/romstage.c
deleted file mode 100644
index 9cdacc3..0000000
--- a/src/mainboard/google/veyron_shark/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
-	unsigned int duty_ns;
-	const u32 period_ns = 2000;	/* pwm period: 2000ns */
-	const u32 max_regulator_mv = 1350;	/* 1.35V */
-	const u32 min_regulator_mv = 870;	/* 0.87V */
-
-	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
-	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
-	duty_ns = (max_regulator_mv - mv) * period_ns /
-			(max_regulator_mv - min_regulator_mv);
-
-	pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
-	rk808_configure_ldo(4, 0); /* VCCIO_SD */
-	rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-	configure_l2ctlr();
-	tsadc_init();
-
-	/* Need to power cycle SD card to ensure it is properly reset. */
-	sdmmc_power_off();
-
-	/* vdd_log 1200mv is enough for ddr run 666Mhz */
-	regulate_vdd_log(1200);
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	sdram_init(get_sdram_config());
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
-	mmu_config_range((uintptr_t)_dram/MiB,
-			 sdram_size_mb(), DCACHE_WRITEBACK);
-	mmu_config_range((uintptr_t)_dma_coherent/MiB,
-			 _dma_coherent_size/MiB, DCACHE_OFF);
-
-	cbmem_initialize_empty();
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
-	run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_shark/sdram_configs.c b/src/mainboard/google/veyron_shark/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_shark/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc"	/* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc"	/* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
-	u32 ramcode = ram_code();
-
-	if (ramcode >= ARRAY_SIZE(sdram_configs)
-			|| sdram_configs[ramcode].dramtype == UNUSED)
-		die("Invalid RAMCODE.");
-	return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynix H5TC8G63xxx chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Nanya NT5CC256M16DP chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4B4G1646D-BYK0 chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Samsung K4B8G1646Q chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA F8132A3MA-GD-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA FA232A2MA-GC-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 2 Hynix H9CCNNN8GTMLAR chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 14,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 3,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4E8E304ED-EGCE000 chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
-	.dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig
deleted file mode 100644
index 411ea42..0000000
--- a/src/mainboard/google/veyron_speedy/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_SPEEDY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select BOARD_ID_AUTO
-	select BOARD_ROMSIZE_KB_4096
-	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select RAM_CODE_SUPPORT
-	select SOC_ROCKCHIP_RK3288
-	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_DO_NATIVE_VGA_INIT
-	select MAINBOARD_HAS_CHROMEOS
-	select HAVE_HARD_RESET
-	select SPI_FLASH
-	select SPI_FLASH_GIGADEVICE
-	select SPI_FLASH_WINBOND
-
-config CHROMEOS
-	select CHROMEOS_VBNV_EC
-	select EC_SOFTWARE_SYNC
-	select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
-	string
-	default google/veyron_speedy
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Veyron_Speedy"
-
-config MAINBOARD_VENDOR
-	string
-	default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
-	int
-	default 100
-
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 2
-
-config DRIVER_TPM_I2C_BUS
-	hex
-	default 0x1
-
-config DRIVER_TPM_I2C_ADDR
-	hex
-	default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	depends on DRIVERS_UART
-	default 0xFF690000
-
-config PMIC_BUS
-	int
-	default 0
-
-endif #  BOARD_GOOGLE_VEYRON_SPEEDY
diff --git a/src/mainboard/google/veyron_speedy/Kconfig.name b/src/mainboard/google/veyron_speedy/Kconfig.name
deleted file mode 100644
index a5b2c9d..0000000
--- a/src/mainboard/google/veyron_speedy/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_SPEEDY
-	bool "Veyron_Speedy"
diff --git a/src/mainboard/google/veyron_speedy/Makefile.inc b/src/mainboard/google/veyron_speedy/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_speedy/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_speedy/board.h b/src/mainboard/google/veyron_speedy/board.h
deleted file mode 100644
index ee705df..0000000
--- a/src/mainboard/google/veyron_speedy/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT	GPIO(7, A, 2)
-#define GPIO_RESET	GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif	/* __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H */
diff --git a/src/mainboard/google/veyron_speedy/boardid.c b/src/mainboard/google/veyron_speedy/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_speedy/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
-	static int id = -1;
-	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
-		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
-	if (id < 0) {
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-		printk(BIOS_SPEW, "Board ID: %d.\n", id);
-	}
-
-	return id;
-}
-
-uint32_t ram_code(void)
-{
-	uint32_t code;
-	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
-		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
-	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
-	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
-	return code;
-}
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
-	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
-		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
-		write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
-	}
-
-}
-
-void bootblock_mainboard_init(void)
-{
-	if (rkclk_was_watchdog_reset())
-		reboot_from_watchdog();
-
-	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
-	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
-	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	rk808_configure_buck(1, 1200);
-	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
-	rk808_configure_buck(1, 1400);
-	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
-
-	/* i2c1 for tpm */
-	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
-	i2c_init(1, 400*KHz);
-
-	/* spi2 for firmware ROM */
-	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
-	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
-	/* spi0 for chrome ec */
-	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
-	setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_speedy/chromeos.c b/src/mainboard/google/veyron_speedy/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_speedy/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-?/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP		GPIO(7, A, 6)
-#define GPIO_LID	GPIO(0, A, 6)
-#define GPIO_POWER	GPIO(0, A, 5)
-#define GPIO_RECOVERY	GPIO(0, B, 1)
-#define GPIO_ECINRW	GPIO(0, A, 7)
-#define GPIO_ECIRQ	GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
-	gpio_input(GPIO_WP);
-	gpio_input_pullup(GPIO_LID);
-	gpio_input(GPIO_POWER);
-	gpio_input_pullup(GPIO_RECOVERY);
-	gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	int count = 0;
-
-	/* Write Protect: active low */
-	gpios->gpios[count].port = GPIO_WP.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = gpio_get(GPIO_WP);
-	strncpy((char *)gpios->gpios[count].name, "write protect",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Recovery: active low */
-	gpios->gpios[count].port = GPIO_RECOVERY.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_recovery_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "recovery",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Lid: active high */
-	gpios->gpios[count].port = GPIO_LID.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Power:GPIO active high */
-	gpios->gpios[count].port = GPIO_POWER.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "power",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Developer: GPIO active high */
-	gpios->gpios[count].port = -1;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_developer_mode_switch();
-	strncpy((char *)gpios->gpios[count].name, "developer",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC in RW: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECINRW.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC in RW",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* EC interrupt: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECIRQ.raw;
-	gpios->gpios[count].polarity = ACTIVE_LOW;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC interrupt",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Reset: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_RESET.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "reset",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Backlight: GPIO active high (output) */
-	gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "backlight",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
-	gpios->count = count;
-
-	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
-	return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
-	uint32_t ec_events;
-
-	/* The GPIO is active low. */
-	if (!gpio_get(GPIO_RECOVERY))
-		return 1;
-
-	ec_events = google_chromeec_get_events_b();
-	return !!(ec_events &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
-	return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_speedy/devicetree.cb b/src/mainboard/google/veyron_speedy/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_speedy/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
-	device cpu_cluster 0 on end
-	register "vop_id" = "1"
-	register "vop_mode" = "VOP_MODE_EDP"
-	register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_speedy/mainboard.c b/src/mainboard/google/veyron_speedy/mainboard.c
deleted file mode 100644
index d76e2e5..0000000
--- a/src/mainboard/google/veyron_speedy/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
-	gpio_output(GPIO(0, B, 3), 1);			/* HOST1_PWR_EN */
-	gpio_output(GPIO(0, B, 4), 1);			/* USBOTG_PWREN_H */
-	gpio_output(GPIO(7, C, 5), 1);			/* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
-	write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
-	/* use sdmmc0 io, disable JTAG function */
-	write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
-	/* Note: these power rail definitions are copied in romstage.c */
-	rk808_configure_ldo(4, 3300); /* VCCIO_SD */
-	rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
-	gpio_input(GPIO(7, A, 5));		/* SD_DET */
-}
-
-static void configure_emmc(void)
-{
-	write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
-	write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
-	write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
-	gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
-	write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);	/* CODEC I2C */
-	i2c_init(2, 400*KHz);				/* CODEC I2C */
-
-	write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
-	write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
-	rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
-
-	/* AUDIO IO domain 1.8V voltage selection */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
-	rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
-	write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
-	/* lcdc(vop) iodomain select 1.8V */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
-	switch (board_id()) {
-	case 0:
-		rk808_configure_switch(2, 1);	/* VCC18_LCD */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 5), 1);	/* AVDD_1V8_DISP_EN */
-		rk808_configure_ldo(7, 2500);	/* VCC10_LCD_PWREN_H */
-		gpio_output(GPIO(7, B, 6), 1);	/* LCD_EN */
-		rk808_configure_switch(1, 1);	/* VCC33_LCD */
-
-		/* enable edp HPD */
-		gpio_input_pulldown(GPIO(7, B, 3));
-		write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
-		break;
-	}
-}
-
-static void mainboard_init(device_t dev)
-{
-	gpio_output(GPIO_RESET, 0);
-
-	configure_usb();
-	configure_sdmmc();
-	configure_emmc();
-	configure_codec();
-	configure_vop();
-
-	elog_init();
-	elog_add_watchdog_reset();
-	elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
-	struct lb_range *dma;
-
-	dma = (struct lb_range *)lb_new_record(header);
-	dma->tag = LB_TAB_DMA;
-	dma->size = sizeof(*dma);
-	dma->range_start = (uintptr_t)_dma_coherent;
-	dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
-	switch (board_id()) {
-	case 0:
-		gpio_output(GPIO(7, A, 0), 0);	/* BL_EN */
-		gpio_output(GPIO(7, A, 2), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO(7, A, 0), 1);	/* BL_EN */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 4), 1);	/* BL_PWR_EN */
-		mdelay(20);
-		gpio_output(GPIO(7, A, 0), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO_BACKLIGHT, 1);	/* BL_EN */
-		break;
-	}
-}
diff --git a/src/mainboard/google/veyron_speedy/memlayout.ld b/src/mainboard/google/veyron_speedy/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_speedy/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_speedy/reset.c b/src/mainboard/google/veyron_speedy/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_speedy/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
-	gpio_output(GPIO_RESET, 1);
-	while (1);
-}
diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c
deleted file mode 100644
index 9cdacc3..0000000
--- a/src/mainboard/google/veyron_speedy/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
-	unsigned int duty_ns;
-	const u32 period_ns = 2000;	/* pwm period: 2000ns */
-	const u32 max_regulator_mv = 1350;	/* 1.35V */
-	const u32 min_regulator_mv = 870;	/* 0.87V */
-
-	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
-	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
-	duty_ns = (max_regulator_mv - mv) * period_ns /
-			(max_regulator_mv - min_regulator_mv);
-
-	pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
-	rk808_configure_ldo(4, 0); /* VCCIO_SD */
-	rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-	configure_l2ctlr();
-	tsadc_init();
-
-	/* Need to power cycle SD card to ensure it is properly reset. */
-	sdmmc_power_off();
-
-	/* vdd_log 1200mv is enough for ddr run 666Mhz */
-	regulate_vdd_log(1200);
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	sdram_init(get_sdram_config());
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
-	mmu_config_range((uintptr_t)_dram/MiB,
-			 sdram_size_mb(), DCACHE_WRITEBACK);
-	mmu_config_range((uintptr_t)_dma_coherent/MiB,
-			 _dma_coherent_size/MiB, DCACHE_OFF);
-
-	cbmem_initialize_empty();
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
-	run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc"	/* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc"	/* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
-	u32 ramcode = ram_code();
-
-	if (ramcode >= ARRAY_SIZE(sdram_configs)
-			|| sdram_configs[ramcode].dramtype == UNUSED)
-		die("Invalid RAMCODE.");
-	return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Hynix H5TC8G63xxx chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Nanya NT5CC256M16DP chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4B4G1646D-BYK0 chips */
-        {
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                },
-                {
-                        .rank = 0x1,
-                        .col = 0xA,
-                        .bk = 0x3,
-                        .bw = 0x2,
-                        .dbw = 0x1,
-                        .row_3_4 = 0x0,
-                        .cs0_row = 0xF,
-                        .cs1_row = 0xF
-                }
-        },
-        {
-                .togcnt1u = 0x29A,
-                .tinit = 0xC8,
-                .trsth = 0x1F4,
-                .togcnt100n = 0x42,
-                .trefi = 0x4E,
-                .tmrd = 0x4,
-                .trfc = 0xEA,
-                .trp = 0xA,
-                .trtw = 0x5,
-                .tal = 0x0,
-                .tcl = 0xA,
-                .tcwl = 0x7,
-                .tras = 0x19,
-                .trc = 0x24,
-                .trcd = 0xA,
-                .trrd = 0x7,
-                .trtp = 0x5,
-                .twr = 0xA,
-                .twtr = 0x5,
-                .texsr = 0x200,
-                .txp = 0x5,
-                .txpdll = 0x10,
-                .tzqcs = 0x40,
-                .tzqcsi = 0x0,
-                .tdqs = 0x1,
-                .tcksre = 0x7,
-                .tcksrx = 0x7,
-                .tcke = 0x4,
-                .tmod = 0xC,
-                .trstl = 0x43,
-                .tzqcl = 0x100,
-                .tmrr = 0x0,
-                .tckesr = 0x5,
-                .tdpd = 0x0
-        },
-        {
-                .dtpr0 = 0x48F9AAB4,
-                .dtpr1 = 0xEA0910,
-                .dtpr2 = 0x1002C200,
-                .mr[0] = 0xA60,
-                .mr[1] = 0x40,
-                .mr[2] = 0x10,
-                .mr[3] = 0x0
-        },
-        .noc_timing = 0x30B25564,
-        .noc_activate = 0x627,
-        .ddrconfig = 3,
-        .ddr_freq = 666*MHz,
-        .dramtype = DDR3,
-        .num_channels = 2,
-        .stride = 9,
-        .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 4 Samsung K4B8G1646Q chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x29A,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x42,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xEA,
-		.trp = 0xA,
-		.trtw = 0x5,
-		.tal = 0x0,
-		.tcl = 0xA,
-		.tcwl = 0x7,
-		.tras = 0x19,
-		.trc = 0x24,
-		.trcd = 0xA,
-		.trrd = 0x7,
-		.trtp = 0x5,
-		.twr = 0xA,
-		.twtr = 0x5,
-		.texsr = 0x200,
-		.txp = 0x5,
-		.txpdll = 0x10,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x7,
-		.tcksrx = 0x7,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x43,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x48F9AAB4,
-		.dtpr1 = 0xEA0910,
-		.dtpr2 = 0x1002C200,
-		.mr[0] = 0xA60,
-		.mr[1] = 0x40,
-		.mr[2] = 0x10,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x30B25564,
-	.noc_activate = 0x627,
-	.ddrconfig = 3,
-	.ddr_freq = 666*MHz,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA F8132A3MA-GD-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two ELPIDA FA232A2MA-GC-F chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* 2 Hynix H9CCNNN8GTMLAR chips */
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 14,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 3,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
-	/* two Samsung K4E8E304ED-EGCE000 chips */
-	{
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x2,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 2,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		},
-		{
-			.rank = 0x2,
-			.col = 0xB,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xE,
-			.cs1_row = 0xE
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x0,
-		.togcnt100n = 0x35,
-		.trefi = 0x26,
-		.tmrd = 0x2,
-		.trfc = 0x70,
-		.trp = 0x2000D,
-		.trtw = 0x6,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x4,
-		.tras = 0x17,
-		.trc = 0x24,
-		.trcd = 0xD,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x76,
-		.txp = 0x4,
-		.txpdll = 0x0,
-		.tzqcs = 0x30,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x2,
-		.tcksrx = 0x2,
-		.tcke = 0x4,
-		.tmod = 0x0,
-		.trstl = 0x0,
-		.tzqcl = 0xC0,
-		.tmrr = 0x4,
-		.tckesr = 0x8,
-		.tdpd = 0x1F4
-	},
-	{
-		.dtpr0 = 0x48D7DD93,
-		.dtpr1 = 0x187008D8,
-		.dtpr2 = 0x121076,
-		.mr[0] = 0x0,
-		.mr[1] = 0xC3,
-		.mr[2] = 0x6,
-		.mr[3] = 0x1
-	},
-	.noc_timing = 0x20D266A4,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 6,
-	.ddr_freq = 533*MHz,
-	.dramtype = LPDDR3,
-	.num_channels = 2,
-	.stride = 13,
-	.odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
-	.dramtype= UNUSED
-},
\ No newline at end of file


From gerrit at coreboot.org  Mon Sep  7 18:43:00 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:00 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: braswell:
	Tristate CFIO 139 and CFIO 140
References: <I6d78d2ccc08167b2cd6fc3405cfcb5c69a77d4b8+0@gerrit.coreboot.org>
Message-ID: <I6d78d2ccc08167b2cd6fc3405cfcb5c69a77d4b8+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11556

-gerrit

commit afe2fd6e2baaa042101e4f8fa6239cf0d519a219
Author: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Date:   Tue Aug 11 14:06:15 2015 -0700

    braswell: Tristate CFIO 139 and CFIO 140
    
    CFIO 139 and CFIO 140 are consuming ~5 during stanndby. The reason
    for this leakage is internally it is configured to 1K PU. So there
    is leakage of ~2mW in standby. Total impact ~2.5 mw in Srandby.
    
    Configure these CFIOs as tristate for ~5mW power saving at platform
    level.
    
    BRANCH=none
    TEST=PnP Team to verify that the CFIO's are tri-stated.
    
    Change-Id: I6d78d2ccc08167b2cd6fc3405cfcb5c69a77d4b8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f11eb98cb36c504dfebe6f0fa53e9af120d21f24
    Original-Change-Id: Ib309ad0c6abffa4515fdf2a2f2d9174fad7f8e8d
    Original-Signed-off-by: Hannah Williams <hannah.williams at intel.com>
    Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/292863
    Original-Commit-Ready: Rajmohan Mani <rajmohan.mani at intel.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/braswell/include/soc/gpio.h | 2 ++
 src/soc/intel/braswell/smihandler.c       | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 5dda732..3cc5cf0 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -110,6 +110,8 @@
 #define MMC1_D7_MMIO_OFFSET		GPIO_OFFSET(68)
 #define HV_DDI2_DDC_SDA_MMIO_OFFSET	GPIO_OFFSET(62)
 #define HV_DDI2_DDC_SCL_MMIO_OFFSET	GPIO_OFFSET(67)
+#define CFIO_139_MMIO_OFFSET		GPIO_OFFSET(64)
+#define CFIO_140_MMIO_OFFSET		GPIO_OFFSET(67)
 
 /* GPIO Security registers offset */
 #define GPIO_READ_ACCESS_POLICY_REG	0x0000
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index eb8ee63..576e118 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -127,6 +127,12 @@ static void tristate_gpios(uint32_t val)
 			HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
 	write32((void *)COMMUNITY_GPNORTH_BASE +
 			HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
+
+	/* Tri-state CFIO 139 and 140 */
+	write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
+			CFIO_139_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
+			CFIO_140_MMIO_OFFSET, val);
 }
 
 


From gerrit at coreboot.org  Mon Sep  7 18:43:01 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:01 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfs: read cbfs
	offset and size from sysinfo
References: <I86434fd249467e7c90d59d6b82f0e6c514bc2d05+0@gerrit.coreboot.org>
Message-ID: <I86434fd249467e7c90d59d6b82f0e6c514bc2d05+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11557

-gerrit

commit 6e80dfee3faacb7bc8ed1e59cf1dac4ba6b4d143
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Sep 2 10:53:13 2015 -0700

    cbfs: read cbfs offset and size from sysinfo
    
    This change allows libpayload to read cbfs offset and size from sysinfo.
    Legacy way of locating cbfs reagion is still supported in case sysinfo
    doesn't store the offset and the size.
    
    BUG=none
    BRANCH=master
    TEST=tested on samus and smaug
    
    Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c
    Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296993
    Original-Commit-Ready: Daisuke Nojiri <dnojiri at google.com>
    Original-Tested-by: Daisuke Nojiri <dnojiri at google.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 payloads/libpayload/libcbfs/cbfs_core.c | 70 +++++++++++++++++++++------------
 1 file changed, 45 insertions(+), 25 deletions(-)

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 7926d9d..90f600c 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -47,6 +47,7 @@
 
 #include <cbfs.h>
 #include <string.h>
+#include <sysinfo.h>
 
 /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS
  *  on failure */
@@ -94,52 +95,71 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
 	return header;
 }
 
-/* public API starts here*/
-struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end,
+			  struct cbfs_media *media)
 {
-	const char *file_name;
-	uint32_t offset, romsize, name_len;
 	const struct cbfs_header *header;
-	struct cbfs_file file, *file_ptr;
-	struct cbfs_media default_media;
 
-	if (media == CBFS_DEFAULT_MEDIA) {
-		media = &default_media;
-		if (init_default_cbfs_media(media) != 0) {
-			ERROR("Failed to initialize default media.\n");
-			return NULL;
-		}
+	if (lib_sysinfo.cbfs_offset && lib_sysinfo.cbfs_size) {
+		*offset = lib_sysinfo.cbfs_offset;
+		*cbfs_end = *offset + lib_sysinfo.cbfs_size;
+		return 0;
 	}
 
-	if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media)))
-		return NULL;
-
+	/*
+	 * If sysinfo doesn't have offset or size, we read them from
+	 * a master header.
+	 */
+	DEBUG("CBFS offset & size not found in sysinfo\n");
+	header = cbfs_get_header(media);
+	if (header == CBFS_HEADER_INVALID_ADDRESS)
+		return -1;
 	// Logical offset (for source media) of first file.
-	offset = ntohl(header->offset);
-	romsize = ntohl(header->romsize);
-
-	// TODO Add a "size" in CBFS header for a platform independent way to
-	// determine the end of CBFS data.
+	*offset = ntohl(header->offset);
+	*cbfs_end = ntohl(header->romsize);
 #if IS_ENABLED(CONFIG_LP_ARCH_X86)
 	// resolve actual length of ROM used for CBFS components
 	// the bootblock size was not taken into account
-	romsize -= ntohl(header->bootblocksize);
+	*cbfs_end -= ntohl(header->bootblocksize);
 
 	// fine tune the length to handle alignment positioning.
 	// using (bootblock size) % align, to derive the
 	// number of bytes the bootblock is off from the alignment size.
 	if ((ntohl(header->bootblocksize) % CBFS_ALIGNMENT))
-		romsize -= (CBFS_ALIGNMENT -
+		*cbfs_end -= (CBFS_ALIGNMENT -
 			(ntohl(header->bootblocksize) % CBFS_ALIGNMENT));
 	else
-		romsize -= 1;
+		*cbfs_end -= 1;
 #endif
+	return 0;
+}
+
+/* public API starts here*/
+struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+{
+	const char *file_name;
+	uint32_t offset, cbfs_end, name_len;
+	struct cbfs_file file, *file_ptr;
+	struct cbfs_media default_media;
+
+	if (media == CBFS_DEFAULT_MEDIA) {
+		media = &default_media;
+		if (init_default_cbfs_media(media) != 0) {
+			ERROR("Failed to initialize default media.\n");
+			return NULL;
+		}
+	}
+
+	if (get_cbfs_range(&offset, &cbfs_end, media)) {
+		ERROR("Failed to find cbfs range\n");
+		return NULL;
+	}
 
-	DEBUG("CBFS location: 0x%x~0x%x\n", offset, romsize);
+	DEBUG("CBFS location: 0x%x~0x%x\n", offset, cbfs_end);
 	DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset);
 
 	media->open(media);
-	while (offset < romsize &&
+	while (offset < cbfs_end &&
 	       media->read(media, &file, offset, sizeof(file)) == sizeof(file)) {
 		if (memcmp(CBFS_FILE_MAGIC, file.magic,
 			   sizeof(file.magic)) != 0) {


From gerrit at coreboot.org  Mon Sep  7 18:43:02 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:02 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: dptf:
	Add TSR3 thermal sensor and CPU code cleanup
References: <I1afe7013a24ee1215f5e968e25594f746bbdd17c+0@gerrit.coreboot.org>
Message-ID: <I1afe7013a24ee1215f5e968e25594f746bbdd17c+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11558

-gerrit

commit 716abff6ccf8f5c2c8314dbb607169708cdfac1c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 15:57:56 2015 -0700

    skylake: dptf: Add TSR3 thermal sensor and CPU code cleanup
    
    - glados has more thermal sensors that could be used so add
    another entry in the DTPF thermal sensor ACPI code.
    - fix indentation block in cpu.asl.
    - declare \_SB.MPDL as external (it is already CondRefOf)
    so it does not need to be present in mainboard config if
    the mainboard does not want to override the default.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I1afe7013a24ee1215f5e968e25594f746bbdd17c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8d357437d06349039a94869b088c3c50b32933c0
    Original-Change-Id: Ie87d52e735bf930a003e525cf1918789920922a5
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297335
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/dptf/cpu.asl     | 13 +++---
 src/soc/intel/skylake/acpi/dptf/thermal.asl | 64 +++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl
index 56a0d07..872ef1a 100644
--- a/src/soc/intel/skylake/acpi/dptf/cpu.asl
+++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl
@@ -50,6 +50,7 @@ External (\_PR.CPU0._TSS, MethodObj)
 External (\_PR.CPU0._TPC, MethodObj)
 External (\_PR.CPU0._PTC, PkgObj)
 External (\_PR.CPU0._TSD, PkgObj)
+External (\_SB.MPDL, IntObj)
 
 Device (B0D4)
 {
@@ -146,12 +147,12 @@ Device (B0D4)
 	{
 		If (CondRefOf (\_PR.CP00._PSS)) {
 			Return (\_PR.CP00._PSS)
-			} Else {
-				Return (Package ()
-				{
-					Package () { 0, 0, 0, 0, 0, 0 }
-				})
-			}
+		} Else {
+			Return (Package ()
+			{
+				Package () { 0, 0, 0, 0, 0, 0 }
+			})
+		}
 	}
 
 
diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl
index a6ab847..99c10da 100644
--- a/src/soc/intel/skylake/acpi/dptf/thermal.asl
+++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl
@@ -38,6 +38,11 @@ Method (TEVT, 1, NotSerialized)
 		Notify (^TSR2, 0x90)
 	}
 #endif
+#ifdef DPTF_TSR3_SENSOR_ID
+	If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) {
+		Notify (^TSR3, 0x90)
+	}
+#endif
 }
 
 /* Thermal device initialization - Disable Aux Trip Points */
@@ -52,6 +57,9 @@ Method (TINI)
 #ifdef DPTF_TSR2_SENSOR_ID
 	^TSR2.PATD ()
 #endif
+#ifdef DPTF_TSR3_SENSOR_ID
+	^TSR3.PATD ()
+#endif
 }
 
 #ifdef DPTF_TSR0_SENSOR_ID
@@ -221,3 +229,59 @@ Device (TSR2)
 	}
 }
 #endif
+
+#ifdef DPTF_TSR3_SENSOR_ID
+Device (TSR3)
+{
+	Name (_HID, EISAID ("INT3403"))
+	Name (_UID, 4)
+	Name (PTYP, 0x03)
+	Name (TMPI, DPTF_TSR3_SENSOR_ID)
+	Name (_STR, Unicode (DPTF_TSR3_SENSOR_NAME))
+	Name (GTSH, 20) /* 2 degree hysteresis */
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	Method (_TMP, 0, Serialized)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+	}
+
+	Method (_PSV)
+	{
+		Return (CTOK (DPTF_TSR3_PASSIVE))
+	}
+
+	Method (_CRT)
+	{
+		Return (CTOK (DPTF_TSR3_CRITICAL))
+	}
+
+	Name (PATC, 2)
+
+	/* Set Aux Trip Point */
+	Method (PAT0, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+	}
+
+	/* Set Aux Trip Point */
+	Method (PAT1, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+	}
+
+	/* Disable Aux Trip Point */
+	Method (PATD, 0, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
+	}
+}
+#endif


From gerrit at coreboot.org  Mon Sep  7 18:43:03 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:03 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO level
References: <I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d+0@gerrit.coreboot.org>
Message-ID: <I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11559

-gerrit

commit a72a989d4b427ac30aecc0bfa1d1b010a320cb0d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:00:49 2015 -0700

    drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO level
    
    Having no supplied printk level makes this info message
    printed at all levels and so it shows up when booting with
    DEFAULT_CONSOLE_LOGLEVEL=3.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST="USE=quiet-cb emerge-glados coreboot"
    
    Change-Id: I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e6cffc6d5a9fcda60a04f8a31f2b2ffe4b620c77
    Original-Change-Id: Ie6715d15f950d184805149619bebe328d528e55a
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297336
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/pc80/tpm/tpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index ba2561d..be616a2 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -410,7 +410,7 @@ static u32 tis_probe(void)
 		break;
 	}
 	/* this will have to be converted into debug printout */
-	printf("Found TPM %s by %s\n", device_name, vendor_name);
+	printk(BIOS_INFO, "Found TPM %s by %s\n", device_name, vendor_name);
 	return 0;
 }
 


From gerrit at coreboot.org  Mon Sep  7 18:43:04 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:04 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: sklrvp: Clean
	up devicetree.cb
References: <I232bd62853685bdcda771e3cbaba2d8ee7437b81+0@gerrit.coreboot.org>
Message-ID: <I232bd62853685bdcda771e3cbaba2d8ee7437b81+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11560

-gerrit

commit ea87bb296013551d8d1b7aea1b2a61f2f658334f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:03:09 2015 -0700

    sklrvp: Clean up devicetree.cb
    
    Remove devicetree.cb settings that do not apply to skylake so
    they can be removed from chip.h and clean up the pci device
    comments and add missing devices.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-sklrvp coreboot
    
    Change-Id: I232bd62853685bdcda771e3cbaba2d8ee7437b81
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a22e1fa56c68b06192acbeeb5c76862d84b8f509
    Original-Change-Id: I61f0581069d87ab974b0fffa6478b44a71bdd69b
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297337
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/sklrvp/devicetree.cb | 59 ++++++++++++--------------------
 1 file changed, 21 insertions(+), 38 deletions(-)

diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb
index cfa51a8..deb3ed7 100644
--- a/src/mainboard/intel/sklrvp/devicetree.cb
+++ b/src/mainboard/intel/sklrvp/devicetree.cb
@@ -45,24 +45,6 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "0x80"
 	register "pirqh_routing" = "0x80"
 
-	# EC range is 0x800-0x9ff
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x00fc0901"
-
-	# GPE configuration
-	register "gpe0_en_1" = "0x00000000"
-	# EC_SCI is GPIO36
-	register "gpe0_en_2" = "0x00000010"
-	register "gpe0_en_3" = "0x00000000"
-	register "gpe0_en_4" = "0x00000000"
-
-	# Force enable ASPM for PCIe Port 3
-	register "pcie_port_force_aspm" = "0x04"
-	register "pcie_port_coalesce" = "1"
-
-	# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x013b0000"
-
 	# Enable S0ix
 	register "s0ix_enable" = "0"
 
@@ -113,25 +95,24 @@ chip soc/intel/skylake
 		device lapic 0 on end
 	end
 	device domain 0 on
-					# Refered from SKL EDS Vol 1 : Page No: 31-32
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 14.0 on  end # USB 3.0 xHCI Controller
-		device pci 14.1 off end # USB Device Controller (OTG)
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
-		device pci 15.0 on  end # I2C Controller #0
-		device pci 15.1 on  end # I2C Controller #1
-		device pci 15.2 on  end # I2C Controller #2
-		device pci 15.3 on  end # I2C Controller #3
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 on  end # I2C #2
+		device pci 15.3 on  end # I2C #3
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE Redirection (IDE-R)
-		device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection
-		device pci 16.4 off end # Management Engine Intel MEI #3
-		device pci 17.0 off end # SATA Controller
-		device pci 19.0 on  end # UART Controller #2
-		device pci 19.1 on  end # I2C Controller #5
-		device pci 19.2 on  end # I2C Controller #4
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT-Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 17.0 off end # SATA
+		device pci 19.0 on  end # UART #2
+		device pci 19.1 on  end # I2C #5
+		device pci 19.2 on  end # I2C #4
 		device pci 1c.0 off end # PCI Express Port 1
 		device pci 1c.1 off end # PCI Express Port 2
 		device pci 1c.2 off end # PCI Express Port 3
@@ -146,14 +127,16 @@ chip soc/intel/skylake
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 on  end # UART #1
-		device pci 1e.2 on  end # SPI #0
+		device pci 1e.2 on  end # GSPI #0
+		device pci 1e.3 on  end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 on  end # SDCard
-		device pci 1f.0 on  end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1)
-		device pci 1f.3 on  end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
-		device pci 1f.4 off end # SMBus Controller
-		device pci 1f.5 on  end # SPI
-		device pci 1f.6 off end # GbE Controller
+		device pci 1f.0 on  end # LPC Interface
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 off end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
 	end
 end


From gerrit at coreboot.org  Mon Sep  7 18:43:05 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:05 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Clean
	up devicetree.cb
References: <I0080ab21db006365f34995db06480dae68ac547d+0@gerrit.coreboot.org>
Message-ID: <I0080ab21db006365f34995db06480dae68ac547d+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11561

-gerrit

commit a507eef6fc0da1b7eed8d42d8a43c8cb257c2954
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:04:09 2015 -0700

    glados: Clean up devicetree.cb
    
    Clean up the PCI device list comments to be consistent between
    the skylake mainboards.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I0080ab21db006365f34995db06480dae68ac547d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d
    Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297338
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/devicetree.cb | 138 ++++++++++++++++--------------
 1 file changed, 72 insertions(+), 66 deletions(-)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 40fe2b1..1d2f8bf 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -5,32 +5,40 @@ chip soc/intel/skylake
 	register "deep_s5_enable" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
-	# Must leave UART0 enabled or SD/eMMC will not work as PCI
-	register "SerialIoDevMode" = "{ \
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart0] = PchSerialIoPci, \
-		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart2] = PchSerialIoPci, \
-	}"
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "GPP_C"
+	register "gpe0_dw1" = "GPP_D"
+	register "gpe0_dw2" = "GPP_E"
 
-	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
-	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
-	register "PortUsb20Enable[2]" = "1"	# Bluetooth
-	register "PortUsb20Enable[4]" = "1"	# Type-A Port 1
-	register "PortUsb20Enable[6]" = "1"	# Camera
-	register "PortUsb20Enable[8]" = "1"	# Type-A Port 2
+	# EC host command range is in 0x800-0x8ff
+	register "gen1_dec" = "0x00fc0801"
 
-	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
-	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
-	register "PortUsb30Enable[2]" = "1"	# Type-A Port 1
-	register "PortUsb30Enable[3]" = "1"	# Type-A Port 2
+	# FSP Configuration
+	register "ProbelessTrace" = "0"
+	register "EnableLan" = "0"
+	register "EnableSata" = "0"
+	register "SataSalpSupport" = "0"
+	register "SataMode" = "0"
+	register "SataPortsEnable[0]" = "0"
+	register "EnableAzalia" = "1"
+	register "DspEnable" = "1"
+	register "IoBufferOwnership" = "3"
+	register "EnableTraceHub" = "0"
+	register "XdciEnable" = "0"
+	register "SsicPortEnable" = "0"
+	register "SmbusEnable" = "1"
+	register "Cio2Enable" = "0"
+	register "ScsEmmcEnabled" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+	register "ScsSdCardEnabled" = "2"
+	register "IshEnable" = "0"
+	register "PttSwitch" = "0"
+	register "InternalGfx" = "1"
+	register "SkipExtGfxScan" = "1"
+	register "Device4Enable" = "1"
 
 	# Enable Root port 1 and 5.
 	register "PcieRpEnable[0]" = "1"
@@ -42,35 +50,32 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[0]" = "1"
 	register "PcieRpClkReqNumber[4]" = "2"
 
-	register "ScsEmmcEnabled" = "1"
-	register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "1"
-	register "EnableAzalia" = "1"
-	register "DspEnable" = "1"
-	register "IoBufferOwnership" = "3"
-
-	register "ProbelessTrace" = "0"
-	register "EnableTraceHub" = "0"
-	register "EnableLan" = "0"
-	register "EnableSata" = "0"
-	register "IshEnable" = "0"
-	register "XdciEnable" = "0"
-	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
-	register "Cio2Enable" = "0"
-	register "PttSwitch" = "0"
-	register "SkipExtGfxScan" = "1"
+	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb20Enable[2]" = "1"	# Bluetooth
+	register "PortUsb20Enable[4]" = "1"	# Type-A Port 1
+	register "PortUsb20Enable[6]" = "1"	# Camera
+	register "PortUsb20Enable[8]" = "1"	# Type-A Port 2
 
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_C"
-	register "gpe0_dw1" = "GPP_D"
-	register "gpe0_dw2" = "GPP_E"
+	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb30Enable[2]" = "1"	# Type-A Port 1
+	register "PortUsb30Enable[3]" = "1"	# Type-A Port 2
 
-	# Embedded Controller host command window
-	register "gen1_dec" = "0x00fc0801"
+	# Must leave UART0 enabled or SD/eMMC will not work as PCI
+	register "SerialIoDevMode" = "{ \
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart0] = PchSerialIoPci, \
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart2] = PchSerialIoPci, \
+	}"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end
@@ -78,22 +83,22 @@ chip soc/intel/skylake
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 14.0 on  end # USB 3.0 xHCI Controller
-		device pci 14.1 off end # USB Device Controller (OTG)
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
-		device pci 15.0 on  end # I2C Controller #0
-		device pci 15.1 on  end # I2C Controller #1
-		device pci 15.2 off end # I2C Controller #2
-		device pci 15.3 off end # I2C Controller #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Intel MEI #3
-		device pci 17.0 on  end # SATA Controller
-		device pci 19.0 on  end # UART Controller #2
-		device pci 19.1 off end # I2C Controller #5
-		device pci 19.2 on  end # I2C Controller #4
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 17.0 off end # SATA
+		device pci 19.0 on  end # UART #2
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # I2C #4
 		device pci 1c.0 on  end # PCI Express Port 1
 		device pci 1c.1 off end # PCI Express Port 2
 		device pci 1c.2 off end # PCI Express Port 3
@@ -111,6 +116,7 @@ chip soc/intel/skylake
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
 		device pci 1e.4 on  end # eMMC
+		device pci 1e.5 off end # SDIO
 		device pci 1e.6 on  end # SDCard
 		device pci 1f.0 on
 			chip drivers/pc80/tpm
@@ -121,9 +127,9 @@ chip soc/intel/skylake
 			end
 		end # LPC Interface
 		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel High Definition Audio
-		device pci 1f.4 on  end # SMBus Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
 		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE Controller
+		device pci 1f.6 off end # GbE
 	end
 end


From gerrit at coreboot.org  Mon Sep  7 18:43:06 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:06 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Clean up devicetree.cb
References: <Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a+0@gerrit.coreboot.org>
Message-ID: <Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11562

-gerrit

commit ff1bc7d2b9dac92a7be1f5fea9c9fafe9f2a35dd
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:05:00 2015 -0700

    kunimitsu: Clean up devicetree.cb
    
    Fix the PCI device list comments to be consistent between
    mainboards and remove unused and incorrect register settings.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8
    Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297339
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/devicetree.cb | 182 ++++++++++++----------------
 1 file changed, 79 insertions(+), 103 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 5cc4f2e..f1480f3 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -1,132 +1,104 @@
 chip soc/intel/skylake
 
-	# SerialIO device modes
-	register "SerialIoDevMode" = "{ \
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci, \
-		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart0] = PchSerialIoPci, \
-		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart2] = PchSerialIoPci, \
-	}"
-
-	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
-	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
-	register "PortUsb20Enable[2]" = "1"	# Bluetooth
-	register "PortUsb20Enable[4]" = "1"	# Type-A Port (card)
-	register "PortUsb20Enable[6]" = "1"	# Camera
-	register "PortUsb20Enable[8]" = "1"	# Type-A Port (board)
-
-	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
-	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
-	register "PortUsb30Enable[2]" = "1"	# Type-A Port (card)
-	register "PortUsb30Enable[3]" = "1"	# Type-A Port (board)
-
-	register "pirqa_routing" = "0x8b"
-	register "pirqb_routing" = "0x8a"
-	register "pirqc_routing" = "0x8b"
-	register "pirqd_routing" = "0x8b"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
-	# EC range is 0x800-0x9ff
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x00fc0901"
-
-	# Pcie RootPort
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpClkReqNumber[0]" = "1"
-	register "PcieRpClkReqNumber[4]" = "2"
-	register "PcieRpClkReqSupport[0]" = "1"
-	register "PcieRpClkReqSupport[4]" = "1"
+	# Enable deep Sx states
+	register "deep_s3_enable" = "1"
+	register "deep_s5_enable" = "1"
+	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
 	# GPE configuration
-	register "gpe0_en_1" = "0x00000000"
-
-	# EC_SCI is GPIO36
-	register "gpe0_en_2" = "0x00000010"
-	register "gpe0_en_3" = "0x00000000"
-	register "gpe0_en_4" = "0x00000000"
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "GPP_C"
+	register "gpe0_dw1" = "GPP_D"
+	register "gpe0_dw2" = "GPP_E"
+
+	# EC host command range is in 0x800-0x8ff
+	register "gen1_dec" = "0x00fc0801"
 
-	# Memory related
+	# FSP Configuration
 	register "ProbelessTrace" = "0"
-
-	# Lan
 	register "EnableLan" = "0"
-
-	# SATA related
 	register "EnableSata" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"
-	register "SsicPortEnable" = "0"
-
-	# Audio related
 	register "EnableAzalia" = "1"
-	register "EnableTraceHub" = "0"
 	register "DspEnable" = "1"
-
-	# I/O Buffer Ownership:
-	# 0: HD-A Link
-	# 1 Shared, HD-A Link and I2S Port
-	# 3: I2S Ports
 	register "IoBufferOwnership" = "3"
-
-	# SMBUS
+	register "EnableTraceHub" = "0"
+	register "XdciEnable" = "0"
+	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
-
-	# Camera
 	register "Cio2Enable" = "0"
-
-	# eMMC
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "ScsSdCardEnabled" = "2"
-
-	# Integrated Sensor
 	register "IshEnable" = "0"
+	register "PttSwitch" = "0"
+	register "InternalGfx" = "1"
+	register "SkipExtGfxScan" = "1"
+	register "Device4Enable" = "1"
 
-	# Enable deep Sx states
-	register "deep_s3_enable" = "0"
-	register "deep_s5_enable" = "1"
+	# Enable Root port 1 and 5.
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	# Enable CLKREQ#
+	register "PcieRpClkReqSupport[0]" = "1"
+	register "PcieRpClkReqSupport[4]" = "1"
+	# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
+	register "PcieRpClkReqNumber[0]" = "1"
+	register "PcieRpClkReqNumber[4]" = "2"
 
-	# CPU Thermal participant device
-	register "Device4Enable" = "1"
+	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb20Enable[2]" = "1"	# Bluetooth
+	register "PortUsb20Enable[4]" = "1"	# Type-A Port (card)
+	register "PortUsb20Enable[6]" = "1"	# Camera
+	register "PortUsb20Enable[8]" = "1"	# Type-A Port (board)
 
-	# XDCI controller
-	register "XdciEnable" = "0"
+	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb30Enable[2]" = "1"	# Type-A Port (card)
+	register "PortUsb30Enable[3]" = "1"	# Type-A Port (board)
 
-		device cpu_cluster 0 on
+	# Must leave UART0 enabled or SD/eMMC will not work as PCI
+	register "SerialIoDevMode" = "{ \
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart0] = PchSerialIoPci, \
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart2] = PchSerialIoPci, \
+	}"
+
+	device cpu_cluster 0 on
 		device lapic 0 on end
 	end
 	device domain 0 on
-					# Refered from SKL EDS Vol 1 : Page No: 31-32
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 14.0 on  end # USB 3.0 xHCI Controller
-		device pci 14.1 off end # USB Device Controller (OTG)
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
-		device pci 15.0 on  end # I2C Controller #0
-		device pci 15.1 on  end # I2C Controller #1
-		device pci 15.2 on  end # I2C Controller #2
-		device pci 15.3 on  end # I2C Controller #3
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE Redirection (IDE-R)
-		device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection
-		device pci 16.4 off end # Management Engine Intel MEI #3
-		device pci 17.0 off end # SATA Controller
-		device pci 19.0 on  end # UART Controller #2
-		device pci 19.1 on  end # I2C Controller #5
-		device pci 19.2 on  end # I2C Controller #4
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 17.0 off end # SATA
+		device pci 19.0 on  end # UART #2
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # I2C #4
 		device pci 1c.0 on  end # PCI Express Port 1
 		device pci 1c.1 off end # PCI Express Port 2
 		device pci 1c.2 off end # PCI Express Port 3
@@ -140,20 +112,24 @@ chip soc/intel/skylake
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 on  end # UART #1
-		device pci 1e.2 on  end # SPI #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 on  end # SDCard
 		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
 		end # LPC Interface
 		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
-		device pci 1f.4 on  end # SMBus Controller
-		device pci 1f.5 on  end # SPI
-		device pci 1f.6 off end # GbE Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
 	end
 end


From gerrit at coreboot.org  Mon Sep  7 18:43:07 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:07 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: Clean
	up chip.h
References: <Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3+0@gerrit.coreboot.org>
Message-ID: <Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11563

-gerrit

commit c0cf178cc2f33a952cdb6dd1ef0b2c726a81045a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:05:59 2015 -0700

    skylake: Clean up chip.h
    
    Remove config options that do not apply and are unused on skylake.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3224b89e310909c2836ef2c669c6b2ee826b1b28
    Original-Change-Id: I2b4fe85f78480eac5635e78ce4e848f73967bd27
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297740
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.h | 33 +++++++--------------------------
 1 file changed, 7 insertions(+), 26 deletions(-)

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index e962b37..9b43b7f 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -60,23 +60,6 @@ struct soc_intel_skylake_config {
 	uint32_t gen3_dec;
 	uint32_t gen4_dec;
 
-	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
-
-	/* Force root port ASPM configuration with port bitmap */
-	uint8_t pcie_port_force_aspm;
-
-	/* Enable ADSP power gating features */
-	uint8_t adsp_d3_pg_enable;
-	uint8_t adsp_sram_pg_enable;
-
-	/*
-	 * Clock Disable Map:
-	 * [21:16] = CLKOUT_PCIE# 5-0
-	 *    [24] = CLKOUT_ITPXDP
-	 */
-	uint32_t icc_clock_disable;
-
 	/*
 	 * Digital Port Hotplug Enable:
 	 *  0x04 = Enabled, 2ms short pulse
@@ -100,15 +83,6 @@ struct soc_intel_skylake_config {
 	u32 gpu_cpu_backlight;
 	u32 gpu_pch_backlight;
 
-	/*
-	 * Graphics CD Clock Frequency
-	 * 0 = 337.5MHz
-	 * 1 = 450MHz
-	 * 2 = 540MHz
-	 * 3 = 675MHz
-	 */
-	int cdclk;
-
 	/* Enable S0iX support */
 	int s0ix_enable;
 
@@ -167,6 +141,13 @@ struct soc_intel_skylake_config {
 	/* Audio related */
 	u8 EnableAzalia;
 	u8 DspEnable;
+
+	/*
+	 * I/O Buffer Ownership:
+	 * 0: HD-A Link
+	 * 1 Shared, HD-A Link and I2S Port
+	 * 3: I2S Ports
+	 */
 	u8 IoBufferOwnership;
 
 	/* Trace Hub function */


From gerrit at coreboot.org  Mon Sep  7 18:43:08 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:08 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: igd:
	clean up igd.c
References: <I2d041f61605e0fc96483a1e825ab082668a0fa44+0@gerrit.coreboot.org>
Message-ID: <I2d041f61605e0fc96483a1e825ab082668a0fa44+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11564

-gerrit

commit f940efec62781e5aaa3168193298d5ec46da8f2e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:07:35 2015 -0700

    skylake: igd: clean up igd.c
    
    Remove unused constants, remove unused headers, and fix the
    use of acpi_slp_type variable.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I2d041f61605e0fc96483a1e825ab082668a0fa44
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: bc57147cb7fa3c38169fcdd62cc9e35d8058414a
    Original-Change-Id: If411ad50650e6705da7de50f5be8b1d414766a8c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297741
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/igd.c | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 25d89c3..5422217 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -26,21 +26,15 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <reg_script.h>
 #include <drivers/intel/gma/i915_reg.h>
 #include <soc/cpu.h>
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
+#include <stdlib.h>
+#include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-#define GT_RETRY		1000
-#define GT_CDCLK_337		0
-#define GT_CDCLK_450		1
-#define GT_CDCLK_540		2
-#define GT_CDCLK_675		3
 u32 map_oprom_vendev(u32 vendev)
 {
 	return SA_IGD_OPROM_VENDEV;
@@ -80,16 +74,16 @@ static void igd_init(struct device *dev)
 		return;
 
 	/* Wait for any configured pre-graphics delay */
-	if (acpi_slp_type != SLEEP_STATE_S3) {
+	if (!acpi_is_wakeup_s3()) {
 #if IS_ENABLED(CONFIG_CHROMEOS)
-	if (developer_mode_enabled() || recovery_mode_enabled() ||
-	    vboot_wants_oprom())
-		mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+		if (developer_mode_enabled() || recovery_mode_enabled() ||
+		    vboot_wants_oprom())
+			mdelay(CONFIG_PRE_GRAPHICS_DELAY);
 #else
-	mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+		mdelay(CONFIG_PRE_GRAPHICS_DELAY);
 #endif
-
 	}
+
 	/* Initialize PCI device, load/execute BIOS Option ROM */
 	pci_dev_init(dev);
 
@@ -105,7 +99,7 @@ static void igd_init(struct device *dev)
 		gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
 			  DDI_INIT_DISPLAY_DETECTED);
 	}
-#endif /* CONFIG_CHROMEOS */
+#endif
 }
 
 static struct device_operations igd_ops = {


From gerrit at coreboot.org  Mon Sep  7 18:43:09 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: Enable
	DPTF based on devicetree setting
References: <I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51+0@gerrit.coreboot.org>
Message-ID: <I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11565

-gerrit

commit a43f4da6503801cdf81a94863e061eddb77ed868
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 13:53:14 2015 -0700

    skylake: Enable DPTF based on devicetree setting
    
    Enable DPTF flag in ACPI NVS based on devicetree setting
    for the mainboard.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glaods coreboot
    
    Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5
    Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297755
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi.c | 6 ++++++
 src/soc/intel/skylake/chip.h | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 87d4eb0..1c3ec79 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -169,6 +169,9 @@ static int get_cores_per_package(void)
 
 void acpi_init_gnvs(global_nvs_t *gnvs)
 {
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *config = dev->chip_info;
+
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
@@ -189,6 +192,9 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 #endif
 	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
 #endif
+
+	/* Enable DPTF based on mainboard configuration */
+	gnvs->dpte = config->dptf_enable;
 }
 
 unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 9b43b7f..94aa3a4 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -86,6 +86,9 @@ struct soc_intel_skylake_config {
 	/* Enable S0iX support */
 	int s0ix_enable;
 
+	/* Enable DPTF support */
+	int dptf_enable;
+
 	/* Deep SX enable for both AC and DC */
 	int deep_s3_enable;
 	int deep_s5_enable;


From gerrit at coreboot.org  Mon Sep  7 18:43:10 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:10 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Change
	include headers to relative path
References: <I6d184adab5b6b2df970ddd3998d3413f1330c12e+0@gerrit.coreboot.org>
Message-ID: <I6d184adab5b6b2df970ddd3998d3413f1330c12e+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11566

-gerrit

commit 8fc54183ae1e7778258407299f85c43542845399
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:10:48 2015 -0700

    glados: Change include headers to relative path
    
    To make it easier to port glados to a new board name change
    the include headers to use relative path name instead of
    including the mainboard name.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90
    Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297742
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi/chromeos.asl  | 2 +-
 src/mainboard/google/glados/acpi/ec.asl        | 4 ++--
 src/mainboard/google/glados/acpi/mainboard.asl | 6 +++---
 src/mainboard/google/glados/acpi/superio.asl   | 2 +-
 src/mainboard/google/glados/chromeos.c         | 2 +-
 src/mainboard/google/glados/spd/spd.c          | 2 +-
 6 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl
index b8cef5e..6b16dbc 100644
--- a/src/mainboard/google/glados/acpi/chromeos.asl
+++ b/src/mainboard/google/glados/acpi/chromeos.asl
@@ -17,7 +17,7 @@
  * Foundation, Inc.
  */
 
-#include <mainboard/google/glados/gpio.h>
+#include "../gpio.h"
 
 Name (OIPG, Package () {
 	/* No physical recovery GPIO. */
diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl
index 33a7471..d69ebe2 100644
--- a/src/mainboard/google/glados/acpi/ec.asl
+++ b/src/mainboard/google/glados/acpi/ec.asl
@@ -18,8 +18,8 @@
  */
 
 /* mainboard configuration */
-#include <mainboard/google/glados/ec.h>
-#include <mainboard/google/glados/gpio.h>
+#include "../ec.h"
+#include "../gpio.h"
 
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
index efa7ddd..0184a6a 100644
--- a/src/mainboard/google/glados/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -17,7 +17,7 @@
  * Foundation, Inc.
  */
 
-#include <mainboard/google/glados/gpio.h>
+#include "../gpio.h"
 
 #define BOARD_TOUCHPAD_I2C_ADDR			0x15
 #define BOARD_TOUCHPAD_IRQ			TOUCHPAD_INT_L
@@ -67,7 +67,7 @@ Scope (\_SB.PCI0.I2C0)
 		Name (_UID, 1)
 		Name (_S0W, 4)
 
-		Name (_CRS, ResourceTemplate()
+		Name (_CRS, ResourceTemplate ()
 		{
 			I2cSerialBus (
 				BOARD_TOUCHSCREEN_I2C_ADDR,
@@ -99,7 +99,7 @@ Scope (\_SB.PCI0.I2C1)
 		Name (_UID, 1)
 		Name (_S0W, 4)
 
-		Name (_CRS, ResourceTemplate()
+		Name (_CRS, ResourceTemplate ()
 		{
 			I2cSerialBus (
 				BOARD_TOUCHPAD_I2C_ADDR,
diff --git a/src/mainboard/google/glados/acpi/superio.asl b/src/mainboard/google/glados/acpi/superio.asl
index 932fef7..822821e 100644
--- a/src/mainboard/google/glados/acpi/superio.asl
+++ b/src/mainboard/google/glados/acpi/superio.asl
@@ -18,7 +18,7 @@
  */
 
 /* mainboard configuration */
-#include <mainboard/google/glados/ec.h>
+#include "../ec.h"
 
 #define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
 #define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c
index dba1cbb..7d42808 100644
--- a/src/mainboard/google/glados/chromeos.c
+++ b/src/mainboard/google/glados/chromeos.c
@@ -28,8 +28,8 @@
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <mainboard/google/glados/gpio.h>
 
+#include "gpio.h"
 #include "ec.h"
 
 #if ENV_RAMSTAGE
diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c
index ad05b31..fc9cb53 100644
--- a/src/mainboard/google/glados/spd/spd.c
+++ b/src/mainboard/google/glados/spd/spd.c
@@ -25,7 +25,7 @@
 #include <string.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
-#include <mainboard/google/glados/gpio.h>
+#include "../gpio.h"
 #include "spd.h"
 
 static void mainboard_print_spd_info(uint8_t spd[])


From gerrit at coreboot.org  Mon Sep  7 18:43:12 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:12 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Remove
	thermal.h
References: <Idb716b47875b20e2110741ae9c154cc52307fbcf+0@gerrit.coreboot.org>
Message-ID: <Idb716b47875b20e2110741ae9c154cc52307fbcf+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11567

-gerrit

commit f45cb906734313eac7a943b325807e870fe7bf67
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:13:36 2015 -0700

    glados: Remove thermal.h
    
    The constants defined in thermal.h are never used since there
    is no defined thermal zone.  Remove it to result in less code
    to worry about in board ports.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10
    Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297743
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi_tables.c | 21 -------------------
 src/mainboard/google/glados/thermal.h     | 35 -------------------------------
 2 files changed, 56 deletions(-)

diff --git a/src/mainboard/google/glados/acpi_tables.c b/src/mainboard/google/glados/acpi_tables.c
index cb0afc4..6da1e1d 100644
--- a/src/mainboard/google/glados/acpi_tables.c
+++ b/src/mainboard/google/glados/acpi_tables.c
@@ -18,35 +18,14 @@
  * Foundation, Inc.
  */
 
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
 #include <arch/acpi.h>
 #include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/cpu.h>
 #include <soc/acpi.h>
 #include <soc/nvs.h>
-#include "thermal.h"
-
-extern const unsigned char AmlCode[];
 
 void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	acpi_init_gnvs(gnvs);
-
-	/* Disable USB ports in S5 */
-	gnvs->s5u0 = 0;
-
-	gnvs->tmps = TEMPERATURE_SENSOR_ID;
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/google/glados/thermal.h b/src/mainboard/google/glados/thermal.h
deleted file mode 100644
index ef03d717..0000000
--- a/src/mainboard/google/glados/thermal.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MAINBOARD_THERMAL_H_
-#define _MAINBOARD_THERMAL_H_
-
-#define TEMPERATURE_SENSOR_ID		0	/* PECI */
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE		99
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE		95
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE			100
-
-#endif /* _MAINBOARD_THERMAL_H_ */


From gerrit at coreboot.org  Mon Sep  7 18:43:13 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:13 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Misc
	code cleanups
References: <I0f76a560dc2c4197e66999752c52573ff0278430+0@gerrit.coreboot.org>
Message-ID: <I0f76a560dc2c4197e66999752c52573ff0278430+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11568

-gerrit

commit 78c43fc574106e8458b761a37f30a5b02eeaad5c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:19:42 2015 -0700

    glados: Misc code cleanups
    
    - romstage.c is using gpio_configure_pads so it should really
    include soc/gpio.h instead of relying on it to come from "gpio.h"
    - consistent formatting of array initializers in pei_data.c
    - remove pei_data->ec_present flag as this is unused in skylake
    - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR
    - clean up acpi_slp_type usage in ec.c, remove unnecessary post
    codes, and cleaner console output message.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b
    Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297744
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/ec.c       | 13 ++++---------
 src/mainboard/google/glados/pei_data.c | 22 ++++++++++------------
 src/mainboard/google/glados/romstage.c |  1 +
 src/mainboard/google/glados/spd/spd.c  |  6 ++++--
 4 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/src/mainboard/google/glados/ec.c b/src/mainboard/google/glados/ec.c
index c491ad5..5473cfc 100644
--- a/src/mainboard/google/glados/ec.c
+++ b/src/mainboard/google/glados/ec.c
@@ -25,11 +25,9 @@
 
 void mainboard_ec_init(void)
 {
-	printk(BIOS_DEBUG, "mainboard_ec_init\n");
-	post_code(0xf0);
+	printk(BIOS_DEBUG, "mainboard: EC init\n");
 
-	/* Restore SCI event mask on resume. */
-	if (acpi_slp_type == 3) {
+	if (acpi_is_wakeup_s3()) {
 		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
 					   MAINBOARD_EC_S3_WAKE_EVENTS);
 
@@ -39,10 +37,8 @@ void mainboard_ec_init(void)
 		/* Clear pending events */
 		while (google_chromeec_get_event() != 0)
 			;
-		/*
-		 * Set SCI mask.OS may not generate SMI event to set
-		 * this on S3 resume.
-		 */
+
+		/* Restore SCI event mask */
 		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
 	} else {
 		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
@@ -51,5 +47,4 @@ void mainboard_ec_init(void)
 
 	/* Clear wake event mask */
 	google_chromeec_set_wake_mask(0);
-	post_code(0xf1);
 }
diff --git a/src/mainboard/google/glados/pei_data.c b/src/mainboard/google/glados/pei_data.c
index 55d7f08..6d2ae15 100644
--- a/src/mainboard/google/glados/pei_data.c
+++ b/src/mainboard/google/glados/pei_data.c
@@ -27,22 +27,20 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
-		  {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
-		   0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00},
-		  {0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC ,
-		   0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
 	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
-		{0, 1, 3, 2, 4, 5, 6, 7},
-		{1, 0, 4, 5, 2, 3, 6, 7} };
+		{ 0, 1, 3, 2, 4, 5, 6, 7 },
+		{ 1, 0, 4, 5, 2, 3, 6, 7 } };
 
-	/* Rcomp resistor*/
-	const u16 RcompResistor[3] = {200, 81, 162 };
+	/* Rcomp resistor */
+	const u16 RcompResistor[3] = { 200, 81, 162 };
 
-	/* Rcomp target*/
-	const u16 RcompTarget[5]   = {100, 40, 40, 23, 40};
-
-	pei_data->ec_present = 1;
+	/* Rcomp target */
+	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
 	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
 	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
index 36a8453..44a896f 100644
--- a/src/mainboard/google/glados/romstage.c
+++ b/src/mainboard/google/glados/romstage.c
@@ -24,6 +24,7 @@
 #include <memory_info.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 #include <soc/romstage.h>
diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c
index fc9cb53..0a17d68 100644
--- a/src/mainboard/google/glados/spd/spd.c
+++ b/src/mainboard/google/glados/spd/spd.c
@@ -22,9 +22,11 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <gpio.h>
-#include <string.h>
+#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
+#include <string.h>
+
 #include "../gpio.h"
 #include "spd.h"
 
@@ -94,7 +96,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	};
 
 	spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
-	printk(BIOS_ERR, "SPD index %d\n", spd_index);
+	printk(BIOS_INFO, "SPD index %d\n", spd_index);
 
 	/* Load SPD data from CBFS */
 	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,


From gerrit at coreboot.org  Mon Sep  7 18:43:16 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:16 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Enable
	DPTF
References: <I8cd2e0ea9c322ea92c101995e8e706f063428a45+0@gerrit.coreboot.org>
Message-ID: <I8cd2e0ea9c322ea92c101995e8e706f063428a45+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11569

-gerrit

commit 30bc8ba1e06166c6beb07d513f973b9738b20add
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:22:49 2015 -0700

    glados: Enable DPTF
    
    - Add ACPI code for DPTF support with placeholder thresholds
    - Do not have custom PDL for mainboard
    - Do not have enable charger control for DPTF as there is
    already a complicated charge profile in the EC.  We may still
    want to enable this but it would need to be tuned to work
    well with the EC profile.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a
    Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297745
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi/dptf.asl | 91 +++++++++++++++++++++++++++++++
 src/mainboard/google/glados/devicetree.cb |  3 +
 src/mainboard/google/glados/dsdt.asl      |  3 +
 3 files changed, 97 insertions(+)

diff --git a/src/mainboard/google/glados/acpi/dptf.asl b/src/mainboard/google/glados/acpi/dptf.asl
new file mode 100644
index 0000000..77578f6
--- /dev/null
+++ b/src/mainboard/google/glados/acpi/dptf.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#define DPTF_CPU_PASSIVE        80
+#define DPTF_CPU_CRITICAL       90
+#define DPTF_CPU_ACTIVE_AC0     90
+#define DPTF_CPU_ACTIVE_AC1     80
+#define DPTF_CPU_ACTIVE_AC2     70
+#define DPTF_CPU_ACTIVE_AC3     60
+#define DPTF_CPU_ACTIVE_AC4     50
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"Ambient"
+#define DPTF_TSR0_PASSIVE	55
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"Charger"
+#define DPTF_TSR1_PASSIVE	55
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"DRAM"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_TSR3_SENSOR_ID	4
+#define DPTF_TSR3_SENSOR_NAME	"WiFi"
+#define DPTF_TSR3_PASSIVE	55
+#define DPTF_TSR3_CRITICAL	70
+
+/* SKL-Y EC already has a custom charge profile based on temperature. */
+#undef DPTF_ENABLE_CHARGER
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 3 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		6000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 1d2f8bf..60966c7 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -16,6 +16,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
 	# FSP Configuration
 	register "ProbelessTrace" = "0"
 	register "EnableLan" = "0"
diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl
index 6ac0be4..ba1b263 100644
--- a/src/mainboard/google/glados/dsdt.asl
+++ b/src/mainboard/google/glados/dsdt.asl
@@ -43,6 +43,9 @@ DefinitionBlock(
 			#include <soc/intel/skylake/acpi/systemagent.asl>
 			#include <soc/intel/skylake/acpi/pch.asl>
 		}
+
+		// Dynamic Platform Thermal Framework
+		#include "acpi/dptf.asl"
 	}
 
 	// Chrome OS specific


From gerrit at coreboot.org  Mon Sep  7 18:43:17 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:17 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Add
	Board ID support
References: <Iba93a913b67e3b3230aded289c2e25585dec1195+0@gerrit.coreboot.org>
Message-ID: <Iba93a913b67e3b3230aded289c2e25585dec1195+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11570

-gerrit

commit 8c16d5c1e3a44e162b2a3f1d972b2ac32dad65b5
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:12:59 2015 -0700

    glados: Add Board ID support
    
    Add support for reading board id and populating it in the
    coreboot tables so it is exposed to payloads.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=boot on glados and look for reported board ID
    
    Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004
    Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297746
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/Kconfig      |  1 +
 src/mainboard/google/glados/Makefile.inc |  2 ++
 src/mainboard/google/glados/boardid.c    | 32 ++++++++++++++++++++++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 1f8a130..a80e16f 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -2,6 +2,7 @@ if BOARD_GOOGLE_GLADOS
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BOARD_ID_AUTO
 	select BOARD_ROMSIZE_KB_16384
 	select CACHE_ROM
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc
index 93fc3d6..39129e8 100644
--- a/src/mainboard/google/glados/Makefile.inc
+++ b/src/mainboard/google/glados/Makefile.inc
@@ -19,6 +19,7 @@
 
 subdirs-y += spd
 
+romstage-y += boardid.c
 romstage-y += pei_data.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -26,6 +27,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 
+ramstage-y += boardid.c
 ramstage-y += mainboard.c
 ramstage-y += pei_data.c
 ramstage-y += ramstage.c
diff --git a/src/mainboard/google/glados/boardid.c b/src/mainboard/google/glados/boardid.c
new file mode 100644
index 0000000..59c6fff
--- /dev/null
+++ b/src/mainboard/google/glados/boardid.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <ec/google/chromeec/ec.h>
+
+uint8_t board_id(void)
+{
+	MAYBE_STATIC int id = -1;
+
+	if (id < 0)
+		id = google_chromeec_get_board_version();
+
+	return id;
+}


From gerrit at coreboot.org  Mon Sep  7 18:43:18 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:18 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: chromeec: Add
	kconfig entry for EC PD support
References: <I170271de9b929fcb73d6b0e09171385a6d23f153+0@gerrit.coreboot.org>
Message-ID: <I170271de9b929fcb73d6b0e09171385a6d23f153+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11571

-gerrit

commit 5ed2f05a79f54f662076ff759a6105fe216b87d3
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:14:18 2015 -0700

    chromeec: Add kconfig entry for EC PD support
    
    Add a kconfig entry to indicate that a board has a PD chip and
    try to put it in RO mode before the EC during early init.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c
    Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297747
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/ec/google/chromeec/Kconfig |  6 ++++++
 src/ec/google/chromeec/ec.c    | 11 ++++++++---
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 25cc0e4..2a86f33 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -47,6 +47,12 @@ config EC_GOOGLE_CHROMEEC_MEC
 	help
 	  Microchip EC variant for LPC register access.
 
+config EC_GOOGLE_CHROMEEC_PD
+	depends on EC_GOOGLE_CHROMEEC
+	def_bool n
+	help
+	  Indicates that Google's Chrome USB PD chip is present.
+
 config EC_GOOGLE_CHROMEEC_SPI
 	depends on EC_GOOGLE_CHROMEEC
 	def_bool n
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index de58d97..e1006dc 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -163,9 +163,14 @@ void google_chromeec_check_ec_image(int expected_type)
 /* Check for recovery mode and ensure EC is in RO */
 void google_chromeec_early_init(void)
 {
-	/* If in recovery ensure EC is running RO firmware. */
-	if (recovery_mode_enabled()) {
-		google_chromeec_check_ec_image(EC_IMAGE_RO);
+	if (IS_ENABLED(CONFIG_CHROMEOS)) {
+		/* Check USB PD chip state first */
+		if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_PD))
+			google_chromeec_early_pd_init();
+
+		/* If in recovery ensure EC is running RO firmware. */
+		if (recovery_mode_enabled())
+			google_chromeec_check_ec_image(EC_IMAGE_RO);
 	}
 }
 


From gerrit at coreboot.org  Mon Sep  7 18:43:19 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:19 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: samus: Use EC
	PD kconfig instead of manual PD reboot
References: <I9e7baffec500a83af1fcf9b1e43d418489172918+0@gerrit.coreboot.org>
Message-ID: <I9e7baffec500a83af1fcf9b1e43d418489172918+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11572

-gerrit

commit 82eec0e92cc33fb9fc1effd7e46d8f874ca4e493
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:15:42 2015 -0700

    samus: Use EC PD kconfig instead of manual PD reboot
    
    Use the new kconfig entry to select the EC PD chip and have it
    be rebooted before the EC automatically insetad of being done
    manually by the board.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-samus coreboot
    
    Change-Id: I9e7baffec500a83af1fcf9b1e43d418489172918
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 53b086725d9d595e8eff7e1e35b9ba8db17ca199
    Original-Change-Id: I9c9a7dd2ba2b78d681b448839f2c5d15ba9dfe60
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297748
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/samus/Kconfig    | 1 +
 src/mainboard/google/samus/romstage.c | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig
index 3059b4b..d8509fb 100644
--- a/src/mainboard/google/samus/Kconfig
+++ b/src/mainboard/google/samus/Kconfig
@@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOC_INTEL_BROADWELL
 	select BOARD_ROMSIZE_KB_8192
 	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_PD
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index 50e633b..d9efdd4 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -45,7 +45,6 @@ void mainboard_romstage_entry(struct romstage_params *rp)
 	printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
 
 	/* Ensure the EC and PD are in the right mode for recovery */
-	google_chromeec_early_pd_init();
 	google_chromeec_early_init();
 
 	/* Initialize GPIOs */


From gerrit at coreboot.org  Mon Sep  7 18:43:20 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:20 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Select
	EC PD and call early EC init
References: <Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4+0@gerrit.coreboot.org>
Message-ID: <Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11573

-gerrit

commit 63f24d83bd6e9abc610f9539ae5617a6e574d1f6
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:17:13 2015 -0700

    glados: Select EC PD and call early EC init
    
    Select the EC PD support in kconfig and call the EC early init
    code that will reboot into RO for recovery mode.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=boot on glados in recovery mode
    
    Change-Id: Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 135ef6e0e2c4864be1c25a9761e04cfe17aec51e
    Original-Change-Id: Iac8c092453bfbd94210462be0b377fb77410941d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297749
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/Kconfig    | 3 ++-
 src/mainboard/google/glados/romstage.c | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index a80e16f..26fd08b 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -6,9 +6,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_16384
 	select CACHE_ROM
 	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
 	select EC_GOOGLE_CHROMEEC_LPC
 	select EC_GOOGLE_CHROMEEC_MEC
-	select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
+	select EC_GOOGLE_CHROMEEC_PD
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
index 44a896f..315ddb9 100644
--- a/src/mainboard/google/glados/romstage.c
+++ b/src/mainboard/google/glados/romstage.c
@@ -41,6 +41,9 @@ static void early_config_gpio(void)
 
 void mainboard_romstage_entry(struct romstage_params *params)
 {
+	/* Ensure the EC and PD are in the right mode for recovery */
+	google_chromeec_early_init();
+
 	early_config_gpio();
 
 	/* Fill out PEI DATA */


From gerrit at coreboot.org  Mon Sep  7 18:43:21 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:21 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Select BOARD_ID_AUTO and clean up boardid code
References: <I90bd85ef14543717287cbeaaab77e6c54b94df97+0@gerrit.coreboot.org>
Message-ID: <I90bd85ef14543717287cbeaaab77e6c54b94df97+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11574

-gerrit

commit 30346b5c7ad5e52e3d0408a0c89e2d5639730170
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:24:40 2015 -0700

    kunimitsu: Select BOARD_ID_AUTO and clean up boardid code
    
    Select the BOARD_ID_AUTO kconfig option to have the coreboot
    tables populated with the board ID and print it early in
    romstage as well.  Also clean up the code for it.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I90bd85ef14543717287cbeaaab77e6c54b94df97
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 1fed7de4a0650a497a240b091fd2eb99d59e1433
    Original-Change-Id: I82e9d17ab618b1aae1fd874d9247b7d52b42334d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297750
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/Kconfig      | 1 +
 src/mainboard/intel/kunimitsu/Makefile.inc | 7 +++++--
 src/mainboard/intel/kunimitsu/boardid.c    | 6 ++----
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig
index bc8ab3e..dd9e455 100644
--- a/src/mainboard/intel/kunimitsu/Kconfig
+++ b/src/mainboard/intel/kunimitsu/Kconfig
@@ -2,6 +2,7 @@ if BOARD_INTEL_KUNIMITSU
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BOARD_ID_AUTO
 	select BOARD_ROMSIZE_KB_16384
 	select CACHE_ROM
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc
index 522308f..61fdc7b 100644
--- a/src/mainboard/intel/kunimitsu/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/Makefile.inc
@@ -20,14 +20,17 @@
 
 subdirs-y += spd
 
+romstage-y += boardid.c
 romstage-y += pei_data.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+
+ramstage-y += boardid.c
 ramstage-y += mainboard.c
 ramstage-y += pei_data.c
 ramstage-y += ramstage.c
-ramstage-y += boardid.c
-romstage-y += boardid.c
+
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/intel/kunimitsu/boardid.c b/src/mainboard/intel/kunimitsu/boardid.c
index 58da22e..59c6fff 100644
--- a/src/mainboard/intel/kunimitsu/boardid.c
+++ b/src/mainboard/intel/kunimitsu/boardid.c
@@ -1,8 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright(C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,7 +21,6 @@
 #include <boardid.h>
 #include <ec/google/chromeec/ec.h>
 
-
 uint8_t board_id(void)
 {
 	MAYBE_STATIC int id = -1;
@@ -31,4 +30,3 @@ uint8_t board_id(void)
 
 	return id;
 }
-


From gerrit at coreboot.org  Mon Sep  7 18:43:22 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:22 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Select EC PD and software sync and do early init
References: <I48316df99b796c568c2481c72588b41f7147bec0+0@gerrit.coreboot.org>
Message-ID: <I48316df99b796c568c2481c72588b41f7147bec0+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11575

-gerrit

commit e8fbbff9426accfe07139c8e6b6b7751d9c43e0f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:29:58 2015 -0700

    kunimitsu: Select EC PD and software sync and do early init
    
    Select the EC PD and software sync kconfig options so they are
    supported by the mainboard and call the EC early init function
    to reboot into RO in recovery mode.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I48316df99b796c568c2481c72588b41f7147bec0
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c7507470f82848062bc98da809d3c5fe1ca31998
    Original-Change-Id: I822aac9c24718f226819e5d3fcc82a4024b7c5a7
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297751
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/Kconfig    | 4 +++-
 src/mainboard/intel/kunimitsu/romstage.c | 3 +++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig
index dd9e455..9447f8e 100644
--- a/src/mainboard/intel/kunimitsu/Kconfig
+++ b/src/mainboard/intel/kunimitsu/Kconfig
@@ -6,9 +6,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_16384
 	select CACHE_ROM
 	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
 	select EC_GOOGLE_CHROMEEC_LPC
 	select EC_GOOGLE_CHROMEEC_MEC
-	select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
+	select EC_GOOGLE_CHROMEEC_PD
+	select EC_SOFTWARE_SYNC
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c
index 1491794..269f297 100644
--- a/src/mainboard/intel/kunimitsu/romstage.c
+++ b/src/mainboard/intel/kunimitsu/romstage.c
@@ -42,6 +42,9 @@ static void early_config_gpio(void)
 
 void mainboard_romstage_entry(struct romstage_params *params)
 {
+	/* Ensure the EC and PD are in the right mode for recovery */
+	google_chromeec_early_init();
+
 	post_code(0x31);
 	early_config_gpio();
 


From gerrit at coreboot.org  Mon Sep  7 18:43:24 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:24 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Clean up mainboard code to match glados
References: <I64a053bcec0e0ff25a57f65659f391ab64d9a11a+0@gerrit.coreboot.org>
Message-ID: <I64a053bcec0e0ff25a57f65659f391ab64d9a11a+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11576

-gerrit

commit 3cc6862c1a1e7314bb04e5e350d11b905b7847ad
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:41:02 2015 -0700

    kunimitsu: Clean up mainboard code to match glados
    
    Clean up the intel/kunimitsu mainboard code to match the code
    and cleanups in glados.  Many of these are trivial changes that
    do not impact things in a meaningful way but will make it easier
    to diff the code and keep the mainboards in sync.
    
    - use relative path for mainboard includes to make porting easier
    - fix trivial style issues to match glados so diffs are clean
    - pull GPIO configuration into gpio.h and use from there
    - remove thermal.h as it is not used on this board
    - make info message BIOS_INFO instead of BIOS_ERR
    - add support for SPD manufacturer and part number in SMBIOS
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be
    Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297752
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/acpi/dptf.asl      |   4 -
 src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 111 ++++++++++++-----------
 src/mainboard/intel/kunimitsu/acpi/superio.asl   |   2 +-
 src/mainboard/intel/kunimitsu/acpi_tables.c      |  22 -----
 src/mainboard/intel/kunimitsu/chromeos.c         |   4 +-
 src/mainboard/intel/kunimitsu/devicetree.cb      |   3 +
 src/mainboard/intel/kunimitsu/dsdt.asl           |   3 +-
 src/mainboard/intel/kunimitsu/ec.c               |  13 +--
 src/mainboard/intel/kunimitsu/fadt.c             |   3 +-
 src/mainboard/intel/kunimitsu/gpio.h             |  13 +++
 src/mainboard/intel/kunimitsu/pei_data.c         |  26 +++---
 src/mainboard/intel/kunimitsu/ramstage.c         |   4 +
 src/mainboard/intel/kunimitsu/romstage.c         |  32 ++++---
 src/mainboard/intel/kunimitsu/spd/spd.c          |  23 ++---
 src/mainboard/intel/kunimitsu/spd/spd.h          |   8 +-
 src/mainboard/intel/kunimitsu/thermal.h          |  36 --------
 16 files changed, 136 insertions(+), 171 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl
index a056bf5..742ba71 100644
--- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl
+++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl
@@ -18,7 +18,6 @@
  * Foundation, Inc.
  */
 
-/* CPU */
 #define DPTF_CPU_PASSIVE        80
 #define DPTF_CPU_CRITICAL       90
 #define DPTF_CPU_ACTIVE_AC0     90
@@ -53,9 +52,6 @@ Name (CHPS, Package () {
 	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
 })
 
-/* Mainboard specific _PDL is 1GHz */
-Name (MPDL, 8)
-
 Name (DTRT, Package () {
 	/* CPU Throttle Effect on CPU */
 	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
index 4492a19..dce1371 100644
--- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
+++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
@@ -20,20 +20,22 @@
 
 #include "../gpio.h"
 
-#define BOARD_TRACKPAD_IRQ		0x33
-#define BOARD_TOUCHSCREEN_IRQ		0x1f
+#define BOARD_TOUCHPAD_I2C_ADDR			0x15
+#define BOARD_TOUCHPAD_IRQ			TOUCHPAD_INT_L
 
-#define BOARD_TRACKPAD_I2C_ADDR		0x15
-#define BOARD_TOUCHSCREEN_I2C_ADDR	0x10
-#define BOARD_LEFT_SSM4567_I2C_ADDR	0x34
-#define BOARD_RIGHT_SSM4567_I2C_ADDR	0x35
-#define BOARD_AUDIO_CODEC_I2C_ADDR	0x1A
+#define BOARD_TOUCHSCREEN_I2C_ADDR		0x10
+#define BOARD_TOUCHSCREEN_IRQ			TOUCHSCREEN_INT_L
+
+#define BOARD_HP_MIC_CODEC_I2C_ADDR		0x1a
+#define BOARD_HP_MIC_CODEC_IRQ			MIC_INT_L
+#define BOARD_LEFT_SPEAKER_AMP_I2C_ADDR		0x34
+#define BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR	0x35
 
 Scope (\_SB)
 {
 	Device (LID0)
 	{
-		Name (_HID, EisaId("PNP0C0D"))
+		Name (_HID, EisaId ("PNP0C0D"))
 		Method (_LID, 0)
 		{
 			Return (\_SB.PCI0.LPCB.EC0.LIDS)
@@ -44,9 +46,10 @@ Scope (\_SB)
 
 	Device (PWRB)
 	{
-		Name (_HID, EisaId("PNP0C0C"))
+		Name (_HID, EisaId ("PNP0C0C"))
 	}
 }
+
 /*
  * LPC Trusted Platform Module
  */
@@ -57,13 +60,15 @@ Scope (\_SB.PCI0.LPCB)
 
 Scope (\_SB.PCI0.I2C0)
 {
-	Device (ETSA)
+	/* Touchscreen */
+	Device (ELTS)
 	{
 		Name (_HID, "ELAN0001")
-		Name (_DDN, "ELAN Touchscreen")
-		Name (_UID, 5)
-		Name (ISTP, 0) /* TouchScreen */
-		Name (_CRS, ResourceTemplate()
+		Name (_DDN, "Elan Touchscreen")
+		Name (_UID, 1)
+		Name (_S0W, 4)
+
+		Name (_CRS, ResourceTemplate ()
 		{
 			I2cSerialBus (
 				BOARD_TOUCHSCREEN_I2C_ADDR,
@@ -72,11 +77,13 @@ Scope (\_SB.PCI0.I2C0)
 				AddressingMode7Bit,
 				"\\_SB.PCI0.I2C0",
 			)
-			Interrupt (ResourceConsumer, Edge, ActiveLow) {
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
 				BOARD_TOUCHSCREEN_IRQ
 			}
 		})
-		Method (_STA, 0, NotSerialized)
+
+		Method (_STA)
 		{
 			Return (0xF)
 		}
@@ -85,18 +92,18 @@ Scope (\_SB.PCI0.I2C0)
 
 Scope (\_SB.PCI0.I2C1)
 {
-	Device (ELAN)
+	/* Touchpad */
+	Device (ELTP)
 	{
 		Name (_HID, "ELAN0000")
 		Name (_DDN, "Elan Touchpad")
-		Name (_UID, 3)
-		/* Allow device to power off in S0 */
+		Name (_UID, 1)
 		Name (_S0W, 4)
-		Name (ISTP, 1) /* TouchPad */
-		Name (_CRS, ResourceTemplate()
+
+		Name (_CRS, ResourceTemplate ()
 		{
 			I2cSerialBus (
-				BOARD_TRACKPAD_I2C_ADDR,
+				BOARD_TOUCHPAD_I2C_ADDR,
 				ControllerInitiated,
 				400000,
 				AddressingMode7Bit,
@@ -104,9 +111,10 @@ Scope (\_SB.PCI0.I2C1)
 			)
 			Interrupt (ResourceConsumer, Edge, ActiveLow)
 			{
-				BOARD_TRACKPAD_IRQ
+				BOARD_TOUCHPAD_IRQ
 			}
 		})
+
 		Method (_STA)
 		{
 			Return (0xF)
@@ -116,43 +124,45 @@ Scope (\_SB.PCI0.I2C1)
 
 Scope (\_SB.PCI0.I2C4)
 {
-	// LEFT SSM4567 I2c ADDR 0x34
-	Device (LSPK)
+	/* Headphone Codec */
+	Device (HPMC)
 	{
-		Name (_HID, "INT343B")
-		Name (_CID, "INT343B")
-		Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec")
+		Name (_HID, "10508825")
+		Name (_DDN, "NAU88L25 Codec")
 		Name (_UID, 1)
 
 		Name (_CRS, ResourceTemplate()
 		{
 			I2cSerialBus (
-				BOARD_LEFT_SSM4567_I2C_ADDR,
+				BOARD_HP_MIC_CODEC_I2C_ADDR,
 				ControllerInitiated,
 				400000,
 				AddressingMode7Bit,
 				"\\_SB.PCI0.I2C4",
 			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_HP_MIC_CODEC_IRQ
+			}
 		})
 
-		Method (_STA, 0, NotSerialized)
+		Method (_STA)
 		{
-			Return (0xF) // I2S Codec ADI LEFT SSM4567 Enabled
+			Return (0xF)
 		}
-	} // Device (LSPK)
+	}
 
-	// RIGHT SSM4567 I2C ADDR 0x35
-	Device (RSPK)
+	/* Left Speaker Amp */
+	Device (SPKL)
 	{
 		Name (_HID, "INT343B")
-		Name (_CID, "INT343B")
-		Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec")
-		Name (_UID, 2)
+		Name (_DDN, "SSM4567 Speaker Amp")
+		Name (_UID, 0)
 
 		Name (_CRS, ResourceTemplate()
 		{
 			I2cSerialBus (
-				BOARD_RIGHT_SSM4567_I2C_ADDR,
+				BOARD_LEFT_SPEAKER_AMP_I2C_ADDR,
 				ControllerInitiated,
 				400000,
 				AddressingMode7Bit,
@@ -160,24 +170,23 @@ Scope (\_SB.PCI0.I2C4)
 			)
 		})
 
-		Method (_STA, 0, NotSerialized)
+		Method (_STA)
 		{
-			Return (0xF) // I2S Codec ADI RIGHT SSM4567 Enabled
+			Return (0xF)
 		}
-	} // Device (RSPK)
+	}
 
-	// Nuvoton NAU88L25 (I2SC = 2)
-	Device (HDAC)
+	/* Right Speaker Amp */
+	Device (SPKR)
 	{
-		Name (_HID, "10508825")
-		Name (_CID, "10508825")
-		Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec")
+		Name (_HID, "INT343B")
+		Name (_DDN, "SSM4567 Speaker Amp")
 		Name (_UID, 1)
 
 		Name (_CRS, ResourceTemplate()
 		{
 			I2cSerialBus (
-				BOARD_AUDIO_CODEC_I2C_ADDR,
+				BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR,
 				ControllerInitiated,
 				400000,
 				AddressingMode7Bit,
@@ -185,11 +194,9 @@ Scope (\_SB.PCI0.I2C4)
 			)
 		})
 
-		Method (_STA, 0, NotSerialized)
+		Method (_STA)
 		{
-			Return (0xF) // I2S Codec  Enabled
+			Return (0xF)
 		}
-	} // Device (HDAC)
+	}
 }
-
-
diff --git a/src/mainboard/intel/kunimitsu/acpi/superio.asl b/src/mainboard/intel/kunimitsu/acpi/superio.asl
index 747991e..822821e 100644
--- a/src/mainboard/intel/kunimitsu/acpi/superio.asl
+++ b/src/mainboard/intel/kunimitsu/acpi/superio.asl
@@ -18,7 +18,7 @@
  */
 
 /* mainboard configuration */
-#include <mainboard/intel/kunimitsu/ec.h>
+#include "../ec.h"
 
 #define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
 #define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
diff --git a/src/mainboard/intel/kunimitsu/acpi_tables.c b/src/mainboard/intel/kunimitsu/acpi_tables.c
index 640cd05..801035e 100644
--- a/src/mainboard/intel/kunimitsu/acpi_tables.c
+++ b/src/mainboard/intel/kunimitsu/acpi_tables.c
@@ -18,36 +18,14 @@
  * Foundation, Inc.
  */
 
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
 #include <arch/acpi.h>
 #include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/cpu.h>
 #include <soc/acpi.h>
 #include <soc/nvs.h>
-#include "thermal.h"
-
-extern const unsigned char AmlCode[];
 
 void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	acpi_init_gnvs(gnvs);
-
-	/* Disable USB ports in S5 */
-	gnvs->s5u0 = 0;
-
-	gnvs->tmps = TEMPERATURE_SENSOR_ID;
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
-	gnvs->dpte = 1;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c
index 441a5c8..905de13 100644
--- a/src/mainboard/intel/kunimitsu/chromeos.c
+++ b/src/mainboard/intel/kunimitsu/chromeos.c
@@ -22,11 +22,13 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <ec/google/chromeec/ec.h>
+#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>
+#include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+
 #include "gpio.h"
 #include "ec.h"
 
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index f1480f3..3d69086 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -16,6 +16,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
 	# FSP Configuration
 	register "ProbelessTrace" = "0"
 	register "EnableLan" = "0"
diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl
index f9d67af..ba1b263 100644
--- a/src/mainboard/intel/kunimitsu/dsdt.asl
+++ b/src/mainboard/intel/kunimitsu/dsdt.asl
@@ -43,7 +43,8 @@ DefinitionBlock(
 			#include <soc/intel/skylake/acpi/systemagent.asl>
 			#include <soc/intel/skylake/acpi/pch.asl>
 		}
-		// Thermal handler
+
+		// Dynamic Platform Thermal Framework
 		#include "acpi/dptf.asl"
 	}
 
diff --git a/src/mainboard/intel/kunimitsu/ec.c b/src/mainboard/intel/kunimitsu/ec.c
index c491ad5..5473cfc 100644
--- a/src/mainboard/intel/kunimitsu/ec.c
+++ b/src/mainboard/intel/kunimitsu/ec.c
@@ -25,11 +25,9 @@
 
 void mainboard_ec_init(void)
 {
-	printk(BIOS_DEBUG, "mainboard_ec_init\n");
-	post_code(0xf0);
+	printk(BIOS_DEBUG, "mainboard: EC init\n");
 
-	/* Restore SCI event mask on resume. */
-	if (acpi_slp_type == 3) {
+	if (acpi_is_wakeup_s3()) {
 		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
 					   MAINBOARD_EC_S3_WAKE_EVENTS);
 
@@ -39,10 +37,8 @@ void mainboard_ec_init(void)
 		/* Clear pending events */
 		while (google_chromeec_get_event() != 0)
 			;
-		/*
-		 * Set SCI mask.OS may not generate SMI event to set
-		 * this on S3 resume.
-		 */
+
+		/* Restore SCI event mask */
 		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
 	} else {
 		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
@@ -51,5 +47,4 @@ void mainboard_ec_init(void)
 
 	/* Clear wake event mask */
 	google_chromeec_set_wake_mask(0);
-	post_code(0xf1);
 }
diff --git a/src/mainboard/intel/kunimitsu/fadt.c b/src/mainboard/intel/kunimitsu/fadt.c
index 83a0d36..83fe860 100644
--- a/src/mainboard/intel/kunimitsu/fadt.c
+++ b/src/mainboard/intel/kunimitsu/fadt.c
@@ -47,6 +47,5 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 
 	acpi_fill_in_fadt(fadt);
 
-	header->checksum =
-	    acpi_checksum((void *) fadt, header->length);
+	header->checksum = acpi_checksum((void *) fadt, header->length);
 }
diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index 0ab36f1..87380d2 100755
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -29,8 +29,21 @@
 
 /* BIOS Flash Write Protect */
 #define GPIO_PCH_WP		GPP_C23
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0	GPP_C12
+#define GPIO_MEM_CONFIG_1	GPP_C13
+#define GPIO_MEM_CONFIG_2	GPP_C14
+#define GPIO_MEM_CONFIG_3	GPP_C15
+
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE		GPE0_LAN_WAK
+
+/* Input device interrupt configuration */
+#define TOUCHPAD_INT_L		GPP_B3_IRQ
+#define TOUCHSCREEN_INT_L	GPP_E7_IRQ
+#define MIC_INT_L		GPP_F10_IRQ
+
 /* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */
 #define EC_SCI_GPI		GPE0_DW2_16
 #define EC_SMI_GPI		GPP_E15
diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c
index 00451bf..f7525da 100644
--- a/src/mainboard/intel/kunimitsu/pei_data.c
+++ b/src/mainboard/intel/kunimitsu/pei_data.c
@@ -25,24 +25,22 @@
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	/* DQ byte map for kunimitsu board */
+	/* DQ byte map */
 	const u8 dq_map[2][12] = {
-		  {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
-		   0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00},
-		  {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
-		   0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
-	/* DQS CPU<>DRAM map for kunimitsu board */
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
-		{0, 1, 3, 2, 6, 5, 4, 7},
-		{2, 3, 0, 1, 6, 7, 4, 5} };
+		{ 0, 1, 3, 2, 6, 5, 4, 7 },
+		{ 2, 3, 0, 1, 6, 7, 4, 5 } };
 
-	/* Rcomp resistor*/
-	const u16 RcompResistor[3] = {200, 81, 162 };
+	/* Rcomp resistor */
+	const u16 RcompResistor[3] = { 200, 81, 162 };
 
-	/* Rcomp target*/
-	const u16 RcompTarget[5]   = {100, 40, 40, 23, 40};
-
-	pei_data->ec_present = 1;
+	/* Rcomp target */
+	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
 	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
 	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c
index 563c715..2deaaa3 100644
--- a/src/mainboard/intel/kunimitsu/ramstage.c
+++ b/src/mainboard/intel/kunimitsu/ramstage.c
@@ -11,6 +11,10 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
  */
 
 #include <soc/ramstage.h>
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c
index 269f297..af16dce 100644
--- a/src/mainboard/intel/kunimitsu/romstage.c
+++ b/src/mainboard/intel/kunimitsu/romstage.c
@@ -21,13 +21,12 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <memory_info.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/cpu.h>
 #include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
-#include <soc/pm.h>
 #include <soc/romstage.h>
 #include "gpio.h"
 #include "spd/spd.h"
@@ -45,7 +44,6 @@ void mainboard_romstage_entry(struct romstage_params *params)
 	/* Ensure the EC and PD are in the right mode for recovery */
 	google_chromeec_early_init();
 
-	post_code(0x31);
 	early_config_gpio();
 
 	/* Fill out PEI DATA */
@@ -55,23 +53,14 @@ void mainboard_romstage_entry(struct romstage_params *params)
 	romstage_common(params);
 }
 
-void mainboard_memory_init_params(
-	struct romstage_params *params,
-	MEMORY_INIT_UPD *memory_params)
+void mainboard_memory_init_params(struct romstage_params *params,
+				  MEMORY_INIT_UPD *memory_params)
 {
 	if (params->pei_data->spd_data[0][0][0] != 0) {
 		memory_params->MemorySpdPtr00 =
 				(UINT32)(params->pei_data->spd_data[0][0]);
 		memory_params->MemorySpdPtr10 =
 				(UINT32)(params->pei_data->spd_data[1][0]);
-		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
-				memory_params->MemorySpdPtr00);
-		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n",
-				memory_params->MemorySpdPtr01);
-		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
-				memory_params->MemorySpdPtr10);
-		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n",
-				memory_params->MemorySpdPtr11);
 	}
 	memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
 			sizeof(params->pei_data->dq_map[0]));
@@ -88,3 +77,18 @@ void mainboard_memory_init_params(
 	memory_params->MemorySpdDataLen = SPD_LEN;
 	memory_params->DqPinsInterleaved = FALSE;
 }
+
+void mainboard_add_dimm_info(struct romstage_params *params,
+			     struct memory_info *mem_info,
+			     int channel, int dimm, int index)
+{
+	/* Set the manufacturer */
+	memcpy(&mem_info->dimm[index].mod_id,
+	       &params->pei_data->spd_data[channel][dimm][SPD_MANU_OFF],
+	       sizeof(mem_info->dimm[index].mod_id));
+
+	/* Set the module part number */
+	memcpy(mem_info->dimm[index].module_part_number,
+	       &params->pei_data->spd_data[channel][dimm][SPD_PART_OFF],
+	       sizeof(mem_info->dimm[index].module_part_number));
+}
diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c
index e54f1a6..b8e0be6 100644
--- a/src/mainboard/intel/kunimitsu/spd/spd.c
+++ b/src/mainboard/intel/kunimitsu/spd/spd.c
@@ -19,17 +19,18 @@
  */
 
 #include <arch/byteorder.h>
+#include <boardid.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <string.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/intel/kunimitsu/spd/spd.h>
-#include <boardid.h>
-#include <mainboard/intel/kunimitsu/boardid.h>
+#include <string.h>
+
+#include "../boardid.h"
+#include "../gpio.h"
+#include "spd.h"
 
 static void mainboard_print_spd_info(uint8_t spd[])
 {
@@ -90,10 +91,10 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	int spd_index, sku_id;
 
 	gpio_t spd_gpios[] = {
-		GPP_C12,	/* PCH_MEM_CONFIG[0] */
-		GPP_C13,	/* PCH_MEM_CONFIG[1] */
-		GPP_C14,	/* PCH_MEM_CONFIG[2] */
-		GPP_C15,	/* PCH_MEM_CONFIG[3] */
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
 	};
 
 	spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
@@ -102,8 +103,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	 *      and not SKU ID but on SCRD it indicates SKU.
 	 */
 	sku_id = board_id();
-	printk(BIOS_ERR, "SPD index %d\n", spd_index);
-	printk(BIOS_ERR, "Board ID %d\n", sku_id);
+	printk(BIOS_INFO, "SPD index %d\n", spd_index);
+	printk(BIOS_INFO, "Board ID %d\n", sku_id);
 
 	/* Load SPD data from CBFS */
 	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h
index 18d4e68..eaa873b 100644
--- a/src/mainboard/intel/kunimitsu/spd/spd.h
+++ b/src/mainboard/intel/kunimitsu/spd/spd.h
@@ -18,8 +18,8 @@
  * Foundation, Inc.
  */
 
-#ifndef _MAINBOARD_SPD_H_
-#define _MAINBOARD_SPD_H_
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
 
 #define SPD_LEN			256
 
@@ -32,6 +32,6 @@
 #define SPD_BUS_DEV_WIDTH	8
 #define SPD_PART_OFF		128
 #define  SPD_PART_LEN		18
+#define SPD_MANU_OFF		148
 
-
-#endif /* _MAINBOARD_SPD_H_ */
+#endif
diff --git a/src/mainboard/intel/kunimitsu/thermal.h b/src/mainboard/intel/kunimitsu/thermal.h
deleted file mode 100644
index 41ce631..0000000
--- a/src/mainboard/intel/kunimitsu/thermal.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MAINBOARD_THERMAL_H_
-#define _MAINBOARD_THERMAL_H_
-
-#define TEMPERATURE_SENSOR_ID		0	/* PECI */
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE		104
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE		95
-
-/* Tj_max value for calculating PECI CPU temperature */
-/* Tj_max can be read by MSR 0x1A2, BITS[23:16] */
-#define MAX_TEMPERATURE			100
-
-#endif /* _MAINBOARD_THERMAL_H_ */


From gerrit at coreboot.org  Mon Sep  7 18:43:26 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:26 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: intel/common:
	Print board ID if enabled
References: <I9d50089242b3a2f461dff2b1039adc8f0347179e+0@gerrit.coreboot.org>
Message-ID: <I9d50089242b3a2f461dff2b1039adc8f0347179e+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11577

-gerrit

commit ccdb90ba383a3249d61284a6a7442bfef8cec3d3
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 13:47:34 2015 -0700

    intel/common: Print board ID if enabled
    
    Read and print the board ID if it is enabled in the mainboard.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f
    Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297756
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/common/romstage.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index 7a05e17..ee9c975 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -25,6 +25,7 @@
 #include <arch/cbfs.h>
 #include <arch/stages.h>
 #include <arch/early_variables.h>
+#include <boardid.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
@@ -101,6 +102,13 @@ asmlinkage void *romstage_main(unsigned int bist,
 	/* Perform SOC specific initialization. */
 	soc_romstage_init(&params);
 
+	/*
+	 * Read and print board version.  Done after SOC romstage
+	 * in case PCH needs to be configured to talk to the EC.
+	 */
+	if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
+		printk(BIOS_INFO, "MLB: board version %d\n", board_id());
+
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&params);
 	soc_after_ram_init(&params);


From gerrit at coreboot.org  Mon Sep  7 18:43:27 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:27 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: sklrvp: Remove
	thermal.h and functions from acpi_tables.c
References: <I934fcc451a722f853034c0970074ee3259cc704f+0@gerrit.coreboot.org>
Message-ID: <I934fcc451a722f853034c0970074ee3259cc704f+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11578

-gerrit

commit 6e0036436103eea931816caa397a6fce0867348e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 14:21:14 2015 -0700

    sklrvp: Remove thermal.h and functions from acpi_tables.c
    
    Remove thermal.h as it is not used by this board.
    Remove functions from acpi_tables.c so they can move to SOC.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-sklrvp coreboot (does not compile due to GPIO changes)
    
    Change-Id: I934fcc451a722f853034c0970074ee3259cc704f
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7e3b5c0ed8295091d3d5761b8456f3c13c6bd8bc
    Original-Change-Id: If855f598e895e38c58657af17130158b2f73de81
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297757
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/sklrvp/acpi_tables.c | 43 --------------------------------
 src/mainboard/intel/sklrvp/thermal.h     | 35 --------------------------
 2 files changed, 78 deletions(-)

diff --git a/src/mainboard/intel/sklrvp/acpi_tables.c b/src/mainboard/intel/sklrvp/acpi_tables.c
index f9eb7b0..72a5888 100644
--- a/src/mainboard/intel/sklrvp/acpi_tables.c
+++ b/src/mainboard/intel/sklrvp/acpi_tables.c
@@ -17,46 +17,3 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc.
  */
-
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/cpu.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-#include "thermal.h"
-
-extern const unsigned char AmlCode[];
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	acpi_init_gnvs(gnvs);
-
-	/* Disable USB ports in S5 */
-	gnvs->s5u0 = 0;
-
-	gnvs->tmps = TEMPERATURE_SENSOR_ID;
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	return acpi_madt_irq_overrides(current);
-}
diff --git a/src/mainboard/intel/sklrvp/thermal.h b/src/mainboard/intel/sklrvp/thermal.h
deleted file mode 100644
index 5214e7e..0000000
--- a/src/mainboard/intel/sklrvp/thermal.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MAINBOARD_THERMAL_H_
-#define _MAINBOARD_THERMAL_H_
-
-#define TEMPERATURE_SENSOR_ID		0	/* PECI */
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE		104
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE		95
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE			105
-
-#endif /* _MAINBOARD_THERMAL_H_ */


From gerrit at coreboot.org  Mon Sep  7 18:43:29 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:29 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Remove
	functions from acpi_tables.c
References: <I18e6a0be5eac053598b613b30b622c4963417919+0@gerrit.coreboot.org>
Message-ID: <I18e6a0be5eac053598b613b30b622c4963417919+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11579

-gerrit

commit 9edc04998c3b376d337b4d3285ef272d7ad5fc34
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 14:15:36 2015 -0700

    glados: Remove functions from acpi_tables.c
    
    Remove the acpi_tables.c functions so these functions can move to
    SOC init code.  The file itself is included by x86/arch code and
    must exist for the build to succeed.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I18e6a0be5eac053598b613b30b622c4963417919
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2
    Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297758
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi_tables.c | 22 ----------------------
 1 file changed, 22 deletions(-)

diff --git a/src/mainboard/google/glados/acpi_tables.c b/src/mainboard/google/glados/acpi_tables.c
index 6da1e1d..6b6e038 100644
--- a/src/mainboard/google/glados/acpi_tables.c
+++ b/src/mainboard/google/glados/acpi_tables.c
@@ -17,25 +17,3 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc.
  */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	acpi_init_gnvs(gnvs);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	return acpi_madt_irq_overrides(current);
-}


From gerrit at coreboot.org  Mon Sep  7 18:43:30 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:30 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Remove functions from acpi_tables.c
References: <Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911+0@gerrit.coreboot.org>
Message-ID: <Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11580

-gerrit

commit b10f5ee8f38c5955dc7a463b5a0239aae62d4c3c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 14:16:49 2015 -0700

    kunimitsu: Remove functions from acpi_tables.c
    
    Remove the acpi_tables.c functions so these functions can move to
    SOC init code.  The file itself is included by x86/arch code and
    must exist for the build to succeed.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 93ae87f2429af5cb9d497f8b5ef8b8dffe370df4
    Original-Change-Id: Ifc2f64dc1693e7bd3f5a43144d84ff033b2cfe8b
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297759
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/acpi_tables.c | 22 ----------------------
 1 file changed, 22 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/acpi_tables.c b/src/mainboard/intel/kunimitsu/acpi_tables.c
index 801035e..72a5888 100644
--- a/src/mainboard/intel/kunimitsu/acpi_tables.c
+++ b/src/mainboard/intel/kunimitsu/acpi_tables.c
@@ -17,25 +17,3 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc.
  */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	acpi_init_gnvs(gnvs);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	return acpi_madt_irq_overrides(current);
-}


From gerrit at coreboot.org  Mon Sep  7 18:43:32 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:32 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: Move
	ACPI init to SOC instead of mainboard
References: <I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52+0@gerrit.coreboot.org>
Message-ID: <I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11581

-gerrit

commit 0b3e64ed6a4bae9a8685a5bbfb583ac1790bc51f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 14:19:35 2015 -0700

    skylake: Move ACPI init to SOC instead of mainboard
    
    Move some remaining ACPI init code to the SOC instead of being
    done in each mainboard:
    
    - acpi_create_gnvs is now a local function
    - add a weak acpi_mainboard_gnvs() that can be used for mainboards
    to override or set additional NVS
    - add acpi_fill_madt() function for skylake
    - remove acpi_create_serialio_ssdt() function as it is unused
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c717bb418a0cb6002582572632e42b44b473f718
    Original-Change-Id: I0910ac8ef25de265ae1fde16b68f6cbacedb4462
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297800
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi.c             | 19 ++++++++++++++++---
 src/soc/intel/skylake/include/soc/acpi.h |  3 +--
 src/soc/intel/skylake/include/soc/nvs.h  |  2 --
 3 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 1c3ec79..18cd2d9 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -22,6 +22,7 @@
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
 #include <chip.h>
@@ -167,7 +168,7 @@ static int get_cores_per_package(void)
 	return cores;
 }
 
-void acpi_init_gnvs(global_nvs_t *gnvs)
+static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
@@ -204,6 +205,18 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	return acpi_madt_irq_overrides(current);
+}
+
 void acpi_fill_in_fadt(acpi_fadt_t *fadt)
 {
 	const uint16_t pmbase = ACPI_BASE_ADDRESS;
@@ -550,7 +563,6 @@ unsigned long southcluster_write_acpi_tables(device_t device,
 
 	ssdt2 = (acpi_header_t *)current;
 	memset(ssdt2, 0, sizeof(acpi_header_t));
-	acpi_create_serialio_ssdt(ssdt2);
 	if (ssdt2->length) {
 		current += ssdt2->length;
 		acpi_add_table(rsdp, ssdt2);
@@ -580,6 +592,7 @@ void southcluster_inject_dsdt(device_t device)
 
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
+		acpi_mainboard_gnvs(gnvs);
 		acpi_save_gnvs((unsigned long)gnvs);
 		/* And tell SMI about it */
 		smm_setup_structures(gnvs, NULL, NULL);
@@ -591,6 +604,6 @@ void southcluster_inject_dsdt(device_t device)
 	}
 }
 
-__attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
+__attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs)
 {
 }
diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h
index cd1a663..7418fe0 100644
--- a/src/soc/intel/skylake/include/soc/acpi.h
+++ b/src/soc/intel/skylake/include/soc/acpi.h
@@ -30,10 +30,9 @@
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10
 
-void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
 void acpi_fill_in_fadt(acpi_fadt_t *fadt);
 unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
+void acpi_mainboard_gnvs(global_nvs_t *gnvs);
 void southcluster_inject_dsdt(device_t device);
 unsigned long southcluster_write_acpi_tables(device_t device,
 	unsigned long current, struct acpi_rsdp *rsdp);
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index c9fcb4e..20530f1 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -62,8 +62,6 @@ typedef struct {
 	chromeos_acpi_t chromeos;
 } __attribute__((packed)) global_nvs_t;
 
-void acpi_create_gnvs(global_nvs_t *gnvs);
-
 #if ENV_SMM
 /* Used in SMM to find the ACPI GNVS address */
 global_nvs_t *smm_get_gnvs(void);


From gerrit at coreboot.org  Mon Sep  7 18:43:33 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:43:33 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: rk3288: Allow
	board-specific APLL (CPU clock) settings
References: <I28b332e1d484bd009599944cd9f5cf633ea468dd+0@gerrit.coreboot.org>
Message-ID: <I28b332e1d484bd009599944cd9f5cf633ea468dd+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11582

-gerrit

commit 04e96cb3a282e5d7e013fa4deb6cc8f384dbed46
Author: David Hendricks <dhendrix at chromium.org>
Date:   Wed Sep 2 18:10:14 2015 -0700

    rk3288: Allow board-specific APLL (CPU clock) settings
    
    This changes the API to rkclk_configure_cpu() such that we can pass
    in the desired APLL frequency in each veyron board's bootblock.c.
    
    Devices with a constrainted form facter (rialto and possibly mickey)
    will use this to run firmware at a slower speed to mitigate risk
    of thermal issues (due to the RK808, not the RK3288).
    
    BUG=chrome-os-partner:42054
    BRANCH=none
    TEST=amstan says rialto is noticably cooler (and slower)
    
    Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb
    Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631
    Original-Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297190
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/mainboard/google/veyron/bootblock.c        |  2 +-
 src/mainboard/google/veyron_brain/bootblock.c  |  2 +-
 src/mainboard/google/veyron_danger/bootblock.c |  2 +-
 src/mainboard/google/veyron_mickey/bootblock.c |  2 +-
 src/mainboard/google/veyron_rialto/bootblock.c |  2 +-
 src/mainboard/google/veyron_romy/bootblock.c   |  2 +-
 src/soc/rockchip/rk3288/clock.c                | 13 ++++++++++---
 src/soc/rockchip/rk3288/include/soc/clock.h    |  8 ++++++--
 8 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c
index ae74972..e4126a4 100644
--- a/src/mainboard/google/veyron/bootblock.c
+++ b/src/mainboard/google/veyron/bootblock.c
@@ -59,7 +59,7 @@ void bootblock_mainboard_init(void)
 	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
 	rk808_configure_buck(1, 1400);
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
+	rkclk_configure_cpu(APLL_1800_MHZ);
 
 	/* i2c1 for tpm */
 	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
index a4a756d..50d8ef1 100644
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ b/src/mainboard/google/veyron_brain/bootblock.c
@@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
 	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
 	rk808_configure_buck(1, 1400);
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
+	rkclk_configure_cpu(APLL_1800_MHZ);
 
 	/* i2c1 for tpm */
 	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c
index a4a756d..50d8ef1 100644
--- a/src/mainboard/google/veyron_danger/bootblock.c
+++ b/src/mainboard/google/veyron_danger/bootblock.c
@@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
 	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
 	rk808_configure_buck(1, 1400);
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
+	rkclk_configure_cpu(APLL_1800_MHZ);
 
 	/* i2c1 for tpm */
 	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c
index a4a756d..50d8ef1 100644
--- a/src/mainboard/google/veyron_mickey/bootblock.c
+++ b/src/mainboard/google/veyron_mickey/bootblock.c
@@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
 	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
 	rk808_configure_buck(1, 1400);
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
+	rkclk_configure_cpu(APLL_1800_MHZ);
 
 	/* i2c1 for tpm */
 	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index 38ae277..a539c08 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -65,7 +65,7 @@ void bootblock_mainboard_init(void)
 	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
 	rk808_configure_buck(1, 1400);
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
+	rkclk_configure_cpu(APLL_1392_MHZ);
 
 	/* i2c1 for tpm */
 	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_romy/bootblock.c b/src/mainboard/google/veyron_romy/bootblock.c
index a4a756d..50d8ef1 100644
--- a/src/mainboard/google/veyron_romy/bootblock.c
+++ b/src/mainboard/google/veyron_romy/bootblock.c
@@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
 	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
 	rk808_configure_buck(1, 1400);
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu();
+	rkclk_configure_cpu(APLL_1800_MHZ);
 
 	/* i2c1 for tpm */
 	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index e4d2e3e..31901e7 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -73,10 +73,17 @@ static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE;
 		       "divisors on line " STRINGIFY(__LINE__));
 
 /* Keep divisors as low as possible to reduce jitter and power usage. */
-static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
+/* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
+static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
+static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1);
+static const struct pll_div *apll_cfgs[] = {
+	[APLL_1800_MHZ] = &apll_1800_cfg,
+	[APLL_1392_MHZ] = &apll_1392_cfg,
+};
+
 /*******************PLL CON0 BITS***************************/
 #define PLL_OD_MSK	(0x0F)
 
@@ -314,13 +321,13 @@ void rkclk_init(void)
 
 }
 
-void rkclk_configure_cpu(void)
+void rkclk_configure_cpu(enum apll_frequencies apll_freq)
 {
 	/* pll enter slow-mode */
 	write32(&cru_ptr->cru_mode_con,
 		RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW));
 
-	rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg);
+	rkclk_set_pll(&cru_ptr->cru_apll_con[0], apll_cfgs[apll_freq]);
 
 	/* waiting for pll lock */
 	while (1) {
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h
index 08d9d45..3fccecb 100644
--- a/src/soc/rockchip/rk3288/include/soc/clock.h
+++ b/src/soc/rockchip/rk3288/include/soc/clock.h
@@ -24,11 +24,15 @@
 
 #define OSC_HZ		(24*MHz)
 
-#define APLL_HZ		(1800*MHz)
 #define GPLL_HZ		(594*MHz)
 #define CPLL_HZ		(384*MHz)
 #define NPLL_HZ		(384*MHz)
 
+enum apll_frequencies {
+	APLL_1800_MHZ,
+	APLL_1392_MHZ,
+};
+
 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */
 #define PD_BUS_ACLK_HZ	(297000*KHz)
 #define PD_BUS_HCLK_HZ	(148500*KHz)
@@ -44,7 +48,7 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
 void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
 void rkclk_configure_ddr(unsigned int hz);
 void rkclk_configure_i2s(unsigned int hz);
-void rkclk_configure_cpu(void);
+void rkclk_configure_cpu(enum apll_frequencies apll_freq);
 void rkclk_configure_crypto(unsigned int hz);
 void rkclk_configure_tsadc(unsigned int hz);
 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);


From gerrit at coreboot.org  Mon Sep  7 18:47:14 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:47:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbgfx: coreboot
	graphics library
References: <I6019e5998e65dca3ab4785a90669b5db02463d2e+0@gerrit.coreboot.org>
Message-ID: <I6019e5998e65dca3ab4785a90669b5db02463d2e+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11408

-gerrit

commit 8d200105a717652048c1941551db18ae66257205
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Jul 29 16:03:52 2015 -0700

    cbgfx: coreboot graphics library
    
    This change introduces cbgfx, a graphics library, which provides APIs for
    drawing basic shapes, texts, graphic data, etc. on a screen.
    
    BUG=chrome-os-partner:43444
    BRANCH=tot
    TEST=Drew boxes by draw command of depthcharge cli on Samus
    
    Change-Id: I6019e5998e65dca3ab4785a90669b5db02463d2e
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: 5b3ebce8eae91be742e4f977d3407d24e1537580
    Original-Reviewed-on: https://chromium-review.googlesource.com/290301
    Original-Reviewed-by: Stefan Reinauer <reinauer at google.com>
    Original-Change-Id: I10db27715cb907bdc451a33ed99d257e3af241b7
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/291065
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 payloads/libpayload/drivers/Makefile.inc     |   3 +
 payloads/libpayload/drivers/video/graphics.c | 148 +++++++++++++++++++++++++++
 payloads/libpayload/include/cbgfx.h          |  66 ++++++++++++
 payloads/libpayload/include/libpayload.h     |   1 +
 4 files changed, 218 insertions(+)

diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
index 25ff4fe..083f122 100644
--- a/payloads/libpayload/drivers/Makefile.inc
+++ b/payloads/libpayload/drivers/Makefile.inc
@@ -68,6 +68,9 @@ libc-$(CONFIG_LP_GEODELX_VIDEO_CONSOLE) += video/font8x16.c
 libc-$(CONFIG_LP_COREBOOT_VIDEO_CONSOLE) += video/corebootfb.c
 libc-$(CONFIG_LP_COREBOOT_VIDEO_CONSOLE) += video/font8x16.c
 
+# cbgfx: coreboot graphics library
+libc-y += video/graphics.c
+
 # AHCI/ATAPI driver
 libc-$(CONFIG_LP_STORAGE) += storage/storage.c
 libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci.c
diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c
new file mode 100644
index 0000000..d9270a5
--- /dev/null
+++ b/payloads/libpayload/drivers/video/graphics.c
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2015 Google, Inc.
+ */
+
+#include <libpayload.h>
+#include <sysinfo.h>
+
+/*
+ * 'canvas' is the drawing area located in the center of the screen. It's a
+ * square area, stretching vertically to the edges of the screen, leaving
+ * non-drawing areas on the left and right. The screen is assumed to be
+ * landscape.
+ */
+static struct vector canvas;
+static uint32_t canvas_offset;		/* horizontal position of canvas */
+
+/*
+ * Framebuffer is assumed to assign a higher coordinate (larger x, y) to
+ * a higher address
+ */
+static struct cb_framebuffer *fbinfo;
+static uint8_t *fbaddr;
+
+static char initialized = 0;
+#define LOG(x...)	printf("CBGFX: " x)
+
+static void add_vectors(struct vector *out,
+			const struct vector *v1, const struct vector *v2)
+{
+	out->x = v1->x + v2->x;
+	out->y = v1->y + v2->y;
+}
+
+static void to_canvas(const struct vector *relative, struct vector *absolute)
+{
+	absolute->x = canvas.width * relative->x / CANVAS_SCALE;
+	absolute->y = canvas.height * relative->y / CANVAS_SCALE;
+}
+
+static int within_canvas(const struct vector *v)
+{
+	return v->x < canvas.width && v->y < canvas.height;
+}
+
+static inline uint32_t calculate_color(const struct rgb_color *rgb)
+{
+	uint32_t color = 0;
+	color |= (rgb->red >> (8 - fbinfo->red_mask_size))
+		<< fbinfo->red_mask_pos;
+	color |= (rgb->green >> (8 - fbinfo->green_mask_size))
+		<< fbinfo->green_mask_pos;
+	color |= (rgb->blue >> (8 - fbinfo->blue_mask_size))
+		<< fbinfo->blue_mask_pos;
+	return color;
+}
+
+/*
+ * Plot a pixel in a framebuffer. This is called from tight loops. Keep it slim
+ * and do the validation at callers' site.
+ */
+static inline void set_pixel(struct vector *coord, uint32_t color)
+{
+	const int bpp = fbinfo->bits_per_pixel;
+	int i;
+	uint8_t * const pixel = fbaddr + (coord->x + canvas_offset +
+			coord->y * fbinfo->x_resolution) * bpp / 8;
+	for (i = 0; i < bpp / 8; i++)
+		pixel[i] = (color >> (i * 8));
+}
+
+/*
+ * Initializes the library. Automatically called by APIs. It sets up
+ * the canvas and the framebuffer.
+ */
+static int cbgfx_init(void)
+{
+	if (initialized)
+		return 0;
+
+	fbinfo = lib_sysinfo.framebuffer;
+	if (!fbinfo)
+		return -1;
+
+	fbaddr = phys_to_virt((uint8_t *)(uintptr_t)(fbinfo->physical_address));
+	if (!fbaddr)
+		return -1;
+
+	/* calculate canvas size, assuming the screen is landscape */
+	canvas.height = fbinfo->y_resolution;
+	canvas.width = canvas.height;
+	canvas_offset = (fbinfo->x_resolution - canvas.width) / 2;
+	if (canvas_offset < 0) {
+		LOG("Portrait screens are not supported\n");
+		return -1;
+	}
+
+	initialized = 1;
+	LOG("cbgfx initialized: canvas width=%d, height=%d, offset=%d\n",
+	    canvas.width, canvas.height, canvas_offset);
+
+	return 0;
+}
+
+int draw_box(const struct vector *top_left_rel,
+	     const struct vector *size_rel,
+	     const struct rgb_color *rgb)
+{
+	struct vector top_left;
+	struct vector size;
+	struct vector p, t;
+	const uint32_t color = calculate_color(rgb);
+
+	if (cbgfx_init())
+		return CBGFX_ERROR_INIT;
+
+	to_canvas(top_left_rel, &top_left);
+	to_canvas(size_rel, &size);
+	add_vectors(&t, &top_left, &size);
+	if (!within_canvas(&t)) {
+		LOG("Box exceeds canvas boundary\n");
+		return CBGFX_ERROR_BOUNDARY;
+	}
+
+	for (p.y = top_left.y; p.y < t.y; p.y++)
+		for (p.x = top_left.x; p.x < t.x; p.x++)
+			set_pixel(&p, color);
+
+	return CBGFX_SUCCESS;
+}
+
+int clear_canvas(struct rgb_color *rgb)
+{
+	const struct vector coord = {
+		.x = 0,
+		.y = 0,
+	};
+	const struct vector size = {
+		.width = CANVAS_SCALE,
+		.height = CANVAS_SCALE,
+	};
+
+	if (cbgfx_init())
+		return CBGFX_ERROR_INIT;
+
+	return draw_box(&coord, &size, rgb);
+}
diff --git a/payloads/libpayload/include/cbgfx.h b/payloads/libpayload/include/cbgfx.h
new file mode 100644
index 0000000..1f3e0b4
--- /dev/null
+++ b/payloads/libpayload/include/cbgfx.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2015 Google, Inc.
+ */
+
+#include <stdint.h>
+
+/*
+ * API error codes
+ */
+#define CBGFX_SUCCESS		0
+/* unknown error */
+#define CBGFX_ERROR_UNKNOWN	1
+/* failed to initialize cbgfx library */
+#define CBGFX_ERROR_INIT	2
+/* drawing beyond canvas boundary */
+#define CBGFX_ERROR_BOUNDARY	3
+
+struct vector {
+	union {
+		uint32_t x;
+		uint32_t width;
+	};
+	union {
+		uint32_t y;
+		uint32_t height;
+	};
+};
+
+struct rgb_color {
+	uint8_t red;
+	uint8_t green;
+	uint8_t blue;
+};
+
+/*
+ * Resolution of scale parameters used to describe height, width, coordinate,
+ * etc. relative to the canvas. For example, if it's 100, scales range from 0 to
+ * 100%.
+ */
+#define CANVAS_SCALE		100
+
+/*
+ * The coordinate system is expected to have (0, 0) at top left corner with
+ * y values increasing towards bottom of screen.
+ */
+
+/*
+ * draw a box filled with a color on screen
+ *
+ * top_left_rel: coordinate of top left corner of the box, relative to canvas.
+ * (0 - CANVAS_SCALE).
+ * size_rel: width and height of the box, relative to canvas. (0 - CANVAS_SCALE)
+ * rgb: RGB color of the box.
+ *
+ * return: CBGFX_* error codes
+ */
+int draw_box(const struct vector *top_left_rel,
+	     const struct vector *size_rel,
+	     const struct rgb_color *rgb);
+
+/*
+ * Clear the canvas
+ */
+int clear_canvas(struct rgb_color *rgb);
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 3ae3590..538f2d8 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -44,6 +44,7 @@
 #define _LIBPAYLOAD_H
 
 #include <libpayload-config.h>
+#include <cbgfx.h>
 #include <ctype.h>
 #include <die.h>
 #include <endian.h>


From gerrit at coreboot.org  Mon Sep  7 18:47:16 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:47:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: video: add
	video_printf
References: <I619625f7d4c5bc19cd9de64a0ba07899cf9ba289+0@gerrit.coreboot.org>
Message-ID: <I619625f7d4c5bc19cd9de64a0ba07899cf9ba289+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11407

-gerrit

commit d8d97d82363b93a8ef7d301ef4ce2a2ac19354eb
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Fri Jul 31 15:22:58 2015 -0700

    video: add video_printf
    
    video_printf prints strings on the screen with specified foreground and
    background color.
    
    BUG=none
    BRANCH=smaug
    TEST=verified messages printed on Smaug
    
    Change-Id: I619625f7d4c5bc19cd9de64a0ba07899cf9ba289
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: e0ac4cb4c0d43b40f5c8f8f5a90eac45b0263b77
    Original-Reviewed-on: https://chromium-review.googlesource.com/290130
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-(cherry picked from commit 75ea2c025d629c8fabc0cb859c4e8ab8ba6ce6e3)
    Original-Change-Id: Ief6d1fc820330b54f37ad9260cf3119853460b70
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/290373
---
 payloads/libpayload/drivers/video/video.c | 21 +++++++++++++++++++++
 payloads/libpayload/include/libpayload.h  |  5 +++++
 2 files changed, 26 insertions(+)

diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c
index 834a121..f183517 100644
--- a/payloads/libpayload/drivers/video/video.c
+++ b/payloads/libpayload/drivers/video/video.c
@@ -162,6 +162,27 @@ void video_console_putchar(unsigned int ch)
 	video_console_fixup_cursor();
 }
 
+void video_printf(int foreground, int background, const char *fmt, ...)
+{
+	int i = 0, len;
+	char str[200];
+
+	va_list ap;
+	va_start(ap, fmt);
+	len = vsnprintf(str, ARRAY_SIZE(str), fmt, ap);
+	va_end(ap);
+	if (len <= 0)
+		return;
+
+	foreground &= 0xf;
+	foreground <<= 8;
+	background &= 0xf;
+	background <<= 12;
+
+	while (str[i])
+		video_console_putchar(str[i++] | foreground | background);
+}
+
 void video_console_get_cursor(unsigned int *x, unsigned int *y, unsigned int *en)
 {
 	*x=0;
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 5e787e1..3ae3590 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -206,6 +206,11 @@ void video_console_clear(void);
 void video_console_cursor_enable(int state);
 void video_console_get_cursor(unsigned int *x, unsigned int *y, unsigned int *en);
 void video_console_set_cursor(unsigned int cursorx, unsigned int cursory);
+/*
+ * print characters on video console with colors. note that there is a size
+ * restriction for the internal buffer. so, output string can be truncated.
+ */
+void video_printf(int foreground, int background, const char *fmt, ...);
 /** @} */
 
 /**


From gerrit at coreboot.org  Mon Sep  7 18:47:18 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:47:18 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: video_printf:
	align text
References: <If1d50b7d8ddaa86eddc1618946756184cb87bfe1+0@gerrit.coreboot.org>
Message-ID: <If1d50b7d8ddaa86eddc1618946756184cb87bfe1+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11583

-gerrit

commit 18133055d4697210662fede22074c5c61c12b0d6
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Aug 12 18:49:50 2015 -0700

    video_printf: align text
    
    This change allows video_printf to left/center/right-align text depending on
    the enum value provided by the caller. This is useful especially because usually
    the length of formatted string is unknown before calling video_printf.
    
    BUG=none
    BRANCH=smaug
    TEST=drew fastboot screens on Smaug
    CQ-DEPEND=CL:296460
    
    Reviewed-on: https://chromium-review.googlesource.com/292929
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit 436f05f60c1b88626740a35913e3ad37b5c777a3)
    Change-Id: If1d50b7d8ddaa86eddc1618946756184cb87bfe1
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/295413
---
 payloads/libpayload/drivers/video/video.c | 26 +++++++++++++++++++++++++-
 payloads/libpayload/include/libpayload.h  |  9 ++++++++-
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c
index f183517..71140f0 100644
--- a/payloads/libpayload/drivers/video/video.c
+++ b/payloads/libpayload/drivers/video/video.c
@@ -162,7 +162,8 @@ void video_console_putchar(unsigned int ch)
 	video_console_fixup_cursor();
 }
 
-void video_printf(int foreground, int background, const char *fmt, ...)
+void video_printf(int foreground, int background, enum video_printf_align align,
+		  const char *fmt, ...)
 {
 	int i = 0, len;
 	char str[200];
@@ -174,6 +175,29 @@ void video_printf(int foreground, int background, const char *fmt, ...)
 	if (len <= 0)
 		return;
 
+	/* vsnprintf can return len larger than size. when it happens,
+	 * only size-1 characters have been actually written. */
+	if (len >= ARRAY_SIZE(str))
+		len = ARRAY_SIZE(str) - 1;
+
+	if (len > console->columns) {
+		cursorx = 0;
+	} else {
+		switch (align) {
+		case VIDEO_PRINTF_ALIGN_LEFT:
+			cursorx = 0;
+			break;
+		case VIDEO_PRINTF_ALIGN_CENTER:
+			cursorx = (console->columns - len) / 2;
+			break;
+		case VIDEO_PRINTF_ALIGN_RIGHT:
+			cursorx = console->columns - len;
+			break;
+		default:
+			break;
+		}
+	}
+
 	foreground &= 0xf;
 	foreground <<= 8;
 	background &= 0xf;
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 538f2d8..a1dbb01 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -211,7 +211,14 @@ void video_console_set_cursor(unsigned int cursorx, unsigned int cursory);
  * print characters on video console with colors. note that there is a size
  * restriction for the internal buffer. so, output string can be truncated.
  */
-void video_printf(int foreground, int background, const char *fmt, ...);
+enum video_printf_align {
+	VIDEO_PRINTF_ALIGN_KEEP = 0,
+	VIDEO_PRINTF_ALIGN_LEFT,
+	VIDEO_PRINTF_ALIGN_CENTER,
+	VIDEO_PRINTF_ALIGN_RIGHT,
+};
+void video_printf(int foreground, int background, enum video_printf_align align,
+		  const char *fmt, ...);
 /** @} */
 
 /**


From gerrit at coreboot.org  Mon Sep  7 18:47:19 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 7 Sep 2015 18:47:19 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbgfx: add
	draw_bitmap
References: <Ib599acc85b25626a6aed1fa9884ecd8e169bb860+0@gerrit.coreboot.org>
Message-ID: <Ib599acc85b25626a6aed1fa9884ecd8e169bb860+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11584

-gerrit

commit 216519981c4a3492376b52c2ac0ad185a0f51b62
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Mon Aug 3 10:51:38 2015 -0700

    cbgfx: add draw_bitmap
    
    draw_bitmap renders a bitmap image on screen with position and sizes
    scaled relative to the screen. images are scaled up or down by nearest
    neighbor interpolation.
    
    BUG=chrome-os-partner:43444
    BRANCH=tot
    TEST=drew bitmap images on Samus
    
    Reviewed-on: https://chromium-review.googlesource.com/290302
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Change-Id: Ib599acc85b25626a6aed1fa9884ecd8e169bb860
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/295532
---
 payloads/libpayload/drivers/video/bitmap.h   |  36 ++++
 payloads/libpayload/drivers/video/graphics.c | 236 ++++++++++++++++++++++++++-
 payloads/libpayload/include/cbgfx.h          |  26 ++-
 3 files changed, 295 insertions(+), 3 deletions(-)

diff --git a/payloads/libpayload/drivers/video/bitmap.h b/payloads/libpayload/drivers/video/bitmap.h
new file mode 100644
index 0000000..10d60a3
--- /dev/null
+++ b/payloads/libpayload/drivers/video/bitmap.h
@@ -0,0 +1,36 @@
+#ifndef __BITMAP_H__
+#define __BITMAP_H__
+
+#include <stdint.h>
+
+struct bitmap_file_header {
+	uint8_t signature[2];
+	uint32_t file_size;
+	uint16_t reserved[2];
+	uint32_t bitmap_offset;
+} __attribute__ ((__packed__));
+
+/* Bitmap version 3 */
+
+struct bitmap_header_v3 {
+	uint32_t header_size;
+	int32_t width;
+	int32_t height;
+	uint16_t planes;
+	uint16_t bits_per_pixel;
+	uint32_t compression;
+	uint32_t size;
+	int32_t h_res;
+	int32_t v_res;
+	uint32_t colors_used;
+	uint32_t colors_important;
+} __attribute__ ((__packed__));
+
+struct bitmap_palette_element_v3 {
+	uint8_t blue;
+	uint8_t green;
+	uint8_t red;
+	uint8_t reserved;
+} __attribute__ ((__packed__));
+
+#endif /* __BITMAP_H__ */
diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c
index d9270a5..5f1dab7 100644
--- a/payloads/libpayload/drivers/video/graphics.c
+++ b/payloads/libpayload/drivers/video/graphics.c
@@ -6,6 +6,7 @@
 
 #include <libpayload.h>
 #include <sysinfo.h>
+#include "bitmap.h"
 
 /*
  * 'canvas' is the drawing area located in the center of the screen. It's a
@@ -26,6 +27,16 @@ static uint8_t *fbaddr;
 static char initialized = 0;
 #define LOG(x...)	printf("CBGFX: " x)
 
+/*
+ * This is the range used internally to scale bitmap images. (e.g. 128 = 50%,
+ * 512 = 200%). We choose 256 so that division and multiplication become bit
+ * shift operation.
+ */
+#define BITMAP_SCALE_BASE	256
+
+#define ROUNDUP(x, y)	((x) + ((y) - ((x) % (y))))
+#define ABS(x)		((x) < 0 ? -(x) : (x))
+
 static void add_vectors(struct vector *out,
 			const struct vector *v1, const struct vector *v2)
 {
@@ -33,15 +44,30 @@ static void add_vectors(struct vector *out,
 	out->y = v1->y + v2->y;
 }
 
+static void scale_vector(struct vector *out, const struct vector *in,
+			 size_t scale, size_t base)
+{
+	out->x = in->x * scale / base;
+	out->y = in->y * scale / base;
+}
+
 static void to_canvas(const struct vector *relative, struct vector *absolute)
 {
 	absolute->x = canvas.width * relative->x / CANVAS_SCALE;
 	absolute->y = canvas.height * relative->y / CANVAS_SCALE;
 }
 
+/*
+ * Returns 1 if exclusively within canvas, or 0 if inclusively within canvas.
+ */
 static int within_canvas(const struct vector *v)
 {
-	return v->x < canvas.width && v->y < canvas.height;
+	if (v->x < canvas.width && v->y < canvas.height)
+		return 1;
+	else if (v->x <= canvas.width && v->y <= canvas.height)
+		return 0;
+	else
+		return -1;
 }
 
 static inline uint32_t calculate_color(const struct rgb_color *rgb)
@@ -118,7 +144,7 @@ int draw_box(const struct vector *top_left_rel,
 	to_canvas(top_left_rel, &top_left);
 	to_canvas(size_rel, &size);
 	add_vectors(&t, &top_left, &size);
-	if (!within_canvas(&t)) {
+	if (within_canvas(&t) < 0) {
 		LOG("Box exceeds canvas boundary\n");
 		return CBGFX_ERROR_BOUNDARY;
 	}
@@ -146,3 +172,209 @@ int clear_canvas(struct rgb_color *rgb)
 
 	return draw_box(&coord, &size, rgb);
 }
+
+static int draw_bitmap_v3(const struct vector *top_left,
+			  size_t scale,
+			  const struct vector *image,
+			  const struct bitmap_header_v3 *header,
+			  const struct bitmap_palette_element_v3 *palette,
+			  const uint8_t *pixel_array)
+{
+	const int bpp = header->bits_per_pixel;
+	int32_t dir;
+	struct vector p;
+
+	if (header->compression) {
+		LOG("Compressed bitmaps are not supported\n");
+		return CBGFX_ERROR_BITMAP_FORMAT;
+	}
+	if (bpp >= 16) {
+		LOG("Non-palette bitmaps are not supported\n");
+		return CBGFX_ERROR_BITMAP_FORMAT;
+	}
+	if (bpp != 8) {
+		LOG("Unsupported bits per pixel: %d\n", bpp);
+		return CBGFX_ERROR_BITMAP_FORMAT;
+	}
+	if (scale == 0) {
+		LOG("Scaling out of range\n");
+		return CBGFX_ERROR_SCALE_OUT_OF_RANGE;
+	}
+
+	const int32_t y_stride = ROUNDUP(header->width * bpp / 8, 4);
+	/*
+	 * header->height can be positive or negative.
+	 *
+	 * If it's negative, pixel data is stored from top to bottom. We render
+	 * image from the lowest row to the highest row.
+	 *
+	 * If it's positive, pixel data is stored from bottom to top. We render
+	 * image from the highest row to the lowest row.
+	 */
+	p.y = top_left->y;
+	if (header->height < 0) {
+		dir = 1;
+	} else {
+		p.y += image->height - 1;
+		dir = -1;
+	}
+	/*
+	 * Plot pixels scaled by the nearest neighbor interpolation. We scan
+	 * over the image on canvas (using d) and find the corresponding pixel
+	 * in the bitmap data (using s).
+	 */
+	struct vector s, d;
+	for (d.y = 0; d.y < image->height; d.y++, p.y += dir) {
+		s.y = d.y * BITMAP_SCALE_BASE / scale;
+		const uint8_t *data = pixel_array + s.y * y_stride;
+		p.x = top_left->x;
+		for (d.x = 0; d.x < image->width; d.x++, p.x++) {
+			s.x = d.x * BITMAP_SCALE_BASE / scale;
+			if (s.y * y_stride + s.x > header->size)
+				/*
+				 * Because we're handling integers rounded by
+				 * divisions, we might get here legitimately
+				 * when rendering the last row of a sane image.
+				 */
+				return CBGFX_SUCCESS;
+			uint8_t index = data[s.x];
+			if (index >= header->colors_used) {
+				LOG("Color index exceeds palette boundary\n");
+				return CBGFX_ERROR_BITMAP_DATA;
+			}
+			const struct rgb_color rgb = {
+				.red = palette[index].red,
+				.green = palette[index].green,
+				.blue = palette[index].blue,
+			};
+			set_pixel(&p, calculate_color(&rgb));
+		}
+	}
+
+	return CBGFX_SUCCESS;
+}
+
+static int get_bitmap_file_header(const void *bitmap, size_t size,
+				  struct bitmap_file_header *file_header)
+{
+	const struct bitmap_file_header *fh;
+
+	if (sizeof(*file_header) > size) {
+		LOG("Invalid bitmap data\n");
+		return CBGFX_ERROR_BITMAP_DATA;
+	}
+	fh = (struct bitmap_file_header *)bitmap;
+	if (fh->signature[0] != 'B' || fh->signature[1] != 'M') {
+		LOG("Bitmap signature mismatch\n");
+		return CBGFX_ERROR_BITMAP_SIGNATURE;
+	}
+	file_header->file_size = le32toh(fh->file_size);
+	if (file_header->file_size != size) {
+		LOG("Bitmap file size does not match cbfs file size\n");
+		return CBGFX_ERROR_BITMAP_DATA;
+	}
+	file_header->bitmap_offset = le32toh(fh->bitmap_offset);
+
+	return CBGFX_SUCCESS;
+}
+
+static int parse_bitmap_header_v3(const uint8_t *bitmap,
+			  const struct bitmap_file_header *file_header,
+			  /* ^--- IN / OUT ---v */
+			  struct bitmap_header_v3 *header,
+			  const struct bitmap_palette_element_v3 **palette,
+			  const uint8_t **pixel_array)
+{
+	struct bitmap_header_v3 *h;
+	size_t header_offset = sizeof(struct bitmap_file_header);
+	size_t header_size = sizeof(struct bitmap_header_v3);
+	size_t palette_offset = header_offset + header_size;
+	size_t file_size = file_header->file_size;
+
+	h = (struct bitmap_header_v3 *)(bitmap + header_offset);
+	header->header_size = le32toh(h->header_size);
+	if (header->header_size != header_size) {
+		LOG("Unsupported bitmap format\n");
+		return CBGFX_ERROR_BITMAP_FORMAT;
+	}
+	header->width = le32toh(h->width);
+	header->height = le32toh(h->height);
+	header->bits_per_pixel = le16toh(h->bits_per_pixel);
+	header->compression = le32toh(h->compression);
+	header->size = le32toh(h->size);
+	header->colors_used = le32toh(h->colors_used);
+	size_t palette_size = header->colors_used
+			* sizeof(struct bitmap_palette_element_v3);
+	size_t pixel_offset = file_header->bitmap_offset;
+	if (pixel_offset > file_size) {
+		LOG("Bitmap pixel data exceeds buffer boundary\n");
+		return CBGFX_ERROR_BITMAP_DATA;
+	}
+	if (palette_offset + palette_size > pixel_offset) {
+		LOG("Bitmap palette data exceeds palette boundary\n");
+		return CBGFX_ERROR_BITMAP_DATA;
+	}
+	*palette = (struct bitmap_palette_element_v3 *)(bitmap +
+			palette_offset);
+
+	size_t pixel_size = header->size;
+	if (pixel_size != header->height *
+		ROUNDUP(header->width * header->bits_per_pixel / 8, 4)) {
+		LOG("Bitmap pixel array size does not match expected size\n");
+		return CBGFX_ERROR_BITMAP_DATA;
+	}
+	if (pixel_offset + pixel_size > file_size) {
+		LOG("Bitmap pixel array exceeds buffer boundary\n");
+		return CBGFX_ERROR_BITMAP_DATA;
+	}
+	*pixel_array = bitmap + pixel_offset;
+
+	return CBGFX_SUCCESS;
+}
+
+int draw_bitmap(const struct vector *top_left_rel,
+		size_t scale_rel, const void *bitmap, size_t size)
+{
+	struct bitmap_file_header file_header;
+	struct bitmap_header_v3 header;
+	const struct bitmap_palette_element_v3 *palette;
+	const uint8_t *pixel_array;
+	struct vector top_left, t, image;
+	size_t scale;
+	int rv;
+
+	if (cbgfx_init())
+		return CBGFX_ERROR_INIT;
+
+	rv = get_bitmap_file_header(bitmap, size, &file_header);
+	if (rv)
+		return rv;
+
+	/* only v3 is supported now */
+	rv = parse_bitmap_header_v3(bitmap, &file_header,
+				    &header, &palette, &pixel_array);
+	if (rv)
+		return rv;
+
+	/* convert relative coordinate to canvas coordinate */
+	to_canvas(top_left_rel, &top_left);
+
+	/* convert canvas scale to self scale (relative to image width) */
+	scale = scale_rel * canvas.width * BITMAP_SCALE_BASE /
+			(CANVAS_SCALE * header.width);
+
+	/* calculate height and width of the image on canvas */
+	image.width = header.width;
+	image.height = ABS(header.height);
+	scale_vector(&image, &image, scale, BITMAP_SCALE_BASE);
+
+	/* check whether right bottom corner exceeds canvas boundaries or not */
+	add_vectors(&t, &image, &top_left);
+	if (within_canvas(&t) < 0) {
+		LOG("Bitmap image exceeds canvas boundary\n");
+		return CBGFX_ERROR_BOUNDARY;
+	}
+
+	return draw_bitmap_v3(&top_left, scale, &image,
+			      &header, palette, pixel_array);
+}
diff --git a/payloads/libpayload/include/cbgfx.h b/payloads/libpayload/include/cbgfx.h
index 1f3e0b4..074a42d 100644
--- a/payloads/libpayload/include/cbgfx.h
+++ b/payloads/libpayload/include/cbgfx.h
@@ -4,7 +4,9 @@
  * Copyright (C) 2015 Google, Inc.
  */
 
-#include <stdint.h>
+#include <libpayload.h>
+#include <arch/types.h>
+#include <stddef.h>
 
 /*
  * API error codes
@@ -16,6 +18,14 @@
 #define CBGFX_ERROR_INIT	2
 /* drawing beyond canvas boundary */
 #define CBGFX_ERROR_BOUNDARY	3
+/* bitmap error: signature mismatch */
+#define CBGFX_ERROR_BITMAP_SIGNATURE	0x10
+/* bitmap error: unsupported format */
+#define CBGFX_ERROR_BITMAP_FORMAT	0x11
+/* bitmap error: invalid data */
+#define CBGFX_ERROR_BITMAP_DATA		0x12
+/* bitmap error: scaling out of range */
+#define CBGFX_ERROR_SCALE_OUT_OF_RANGE	0x13
 
 struct vector {
 	union {
@@ -64,3 +74,17 @@ int draw_box(const struct vector *top_left_rel,
  * Clear the canvas
  */
 int clear_canvas(struct rgb_color *rgb);
+
+/*
+ * Draw a bitmap image on screen.
+ *
+ * top_left_rel: coordinate of the top left corner of the image relative to the
+ * canvas (0 - CANVAS_SCALE).
+ * scale_rel: scale factor relative to the canvas width (0 - CANVAS_SCALE).
+ * bitmap: pointer to the bitmap data, starting from the file header.
+ * size: size of the bitmap data
+ *
+ * return: CBGFX_* error codes
+ */
+int draw_bitmap(const struct vector *top_left_rel,
+		size_t scale_rel, const void *bitmap, size_t size);


From gerrit at coreboot.org  Mon Sep  7 19:03:00 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 19:03:00 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: microcode: Unify
	rules to add microcode to CBFS once again
References: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+0@gerrit.coreboot.org>
Message-ID: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+5@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526

-gerrit

commit c8d3703a9c8ba5f42e4a94ff538d989174d5d313
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:35:55 2015 -0700

    microcode: Unify rules to add microcode to CBFS once again
    
    Now that cbfstool supports file alignment, we can use the conveniently
    available <filename>-align handler, and remove the need to have a
    separate rule in src/Makefile.inc just for adding the microcode.
    
    We can also get rid of the layering violation of having the
    CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
    Note that we still have a layering violation by the use of the
    CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
    for the time being.
    
    Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 Makefile.inc                                  |  1 -
 src/cpu/Makefile.inc                          | 20 +++++++-------------
 src/soc/intel/braswell/microcode/Makefile.inc | 11 -----------
 src/soc/intel/skylake/microcode/Makefile.inc  | 11 -----------
 4 files changed, 7 insertions(+), 36 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..be6021b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(
 	-B $(objcbfs)/bootblock.bin \
 	$(CBFSTOOL_PRE1_OPTS)
 	$(prebuild-files) true
-	$(call add-cpu-microcode-to-cbfs,$@.tmp)
 	mv $@.tmp $@
 else
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index cdd353f..d757c79 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64))
 ## Rules for building the microcode blob in CBFS
 ################################################################################
 
-cpu_ucode_cbfs_name = cpu_microcode_blob.bin
-
 # External microcode file, or are we generating one ?
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
 cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
@@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y)
-cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)"
-else
-cpu_ucode_cbfs_offset = "-b"
-endif
-
 # In case we have more than one "source" (cough) files containing microcode, we
 # link them together in one large blob, so that we get all the microcode updates
 # in one file. This makes it easier for objcopy in the final step.
@@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
 	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
 
-ifeq ($(cbfs_include_ucode),y)
-# Add CPU microcode to specified rom image $(1)
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset)
+cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
+cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
+cpu_microcode_blob.bin-type := microcode
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
+cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
 else
-add-cpu-microcode-to-cbfs = true
+cpu_microcode_blob.bin-align := 16
 endif
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
index da25b8b..3497328 100644
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ b/src/soc/intel/braswell/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-y += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
index a5e8981..ba308f6 100644
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ b/src/soc/intel/skylake/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-


From gerrit at coreboot.org  Mon Sep  7 19:18:23 2015
From: gerrit at coreboot.org (Mono Moosbart (mono-for-coreboot@donderklumpen.de))
Date: Mon, 7 Sep 2015 19:18:23 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: intel i945: Fix
	native VGA initialization
References: <I0663f3b423624c67c2388a9cc44ec41f370f4a17+0@gerrit.coreboot.org>
Message-ID: <I0663f3b423624c67c2388a9cc44ec41f370f4a17+1@gerrit.coreboot.org>

Mono Moosbart (mono-for-coreboot at donderklumpen.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11585

-gerrit

commit 84f873c4497b91bca845849dc8dc35f3add142b3
Author: Mono <mono-for-coreboot at donderklumpen.de>
Date:   Mon Sep 7 21:15:26 2015 +0200

    intel i945: Fix native VGA initialization
    
    Native VGA init no longer compiles  from commit:
    * 7dbf9c6 edid: Use edid_mode struct to reduce redundancy
    
    Tested on a single X60 machine.
    
    This patch basically copies 11491 which does
    the same for north/intel/sandybridge.
    
    Change-Id: I0663f3b423624c67c2388a9cc44ec41f370f4a17
    Signed-off-by: Axel Holewa <mono-for-coreboot at donderklumpen.de>
---
 src/northbridge/intel/i945/gma.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 437b6ce..8b70e55 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -85,6 +85,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
 			  void *pmmio, unsigned int pgfx)
 {
 	struct edid edid;
+	struct edid_mode *mode;
 	u8 edid_data[128];
 	unsigned long temp;
 	int hpolarity, vpolarity;
@@ -107,19 +108,20 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
 
 	intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128);
 	decode_edid(edid_data, sizeof(edid_data), &edid);
+	mode = &edid.mode;
 
-	hpolarity = (edid.phsync == '-');
-	vpolarity = (edid.pvsync == '-');
+	hpolarity = (mode->phsync == '-');
+	vpolarity = (mode->pvsync == '-');
 	hactive = edid.x_resolution;
 	vactive = edid.y_resolution;
-	right_border = edid.hborder;
-	bottom_border = edid.vborder;
-	vblank = edid.vbl;
-	hblank = edid.hbl;
-	vsync = edid.vspw;
-	hsync = edid.hspw;
-	hfront_porch = edid.hso;
-	vfront_porch = edid.vso;
+	right_border = mode->hborder;
+	bottom_border = mode->vborder;
+	vblank = mode->vbl;
+	hblank = mode->hbl;
+	vsync = mode->vspw;
+	hsync = mode->hspw;
+	hfront_porch = mode->hso;
+	vfront_porch = mode->vso;
 
 	for (i = 0; i < 2; i++)
 		for (j = 0; j < 0x100; j++)
@@ -160,8 +162,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
 	write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
 	write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
 
-	target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock
-		: (2 * edid.pixel_clock);
+	target_frequency = conf->gpu_lvds_is_dual_channel ? mode->pixel_clock
+		: (2 * mode->pixel_clock);
 
 	/* Find suitable divisors.  */
 	for (candp1 = 1; candp1 <= 8; candp1++) {


From gerrit at coreboot.org  Mon Sep  7 19:43:25 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 7 Sep 2015 19:43:25 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	north/intel/sandybridge: Fix native VGA initialization
References: <I51a4f4874ce77178cab96651eb7caf2edd862aa2+0@gerrit.coreboot.org>
Message-ID: <E1ZZ2K5-0002C5-47@mail.coreboot.org>

the following patch was just integrated into master:
commit c2418552407fee39965ecd6dbad52cb39c76b656
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 2 09:00:45 2015 -0700

    north/intel/sandybridge: Fix native VGA initialization
    
    Native VGA init no longer compiles  from commit:
    * 7dbf9c6 edid: Use edid_mode struct to reduce redundancy
    
    Change-Id: I51a4f4874ce77178cab96651eb7caf2edd862aa2
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11491
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11491 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep  7 20:41:53 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 20:41:53 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	intel/sandybridge: Do not guard native VGA init by #ifdefs
References: <I334cdee214872f967ae090170d61a0e4951c6b35+0@gerrit.coreboot.org>
Message-ID: <I334cdee214872f967ae090170d61a0e4951c6b35+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11586

-gerrit

commit 0aa297ad9b7f26963ead3a107edb9af27fc5f5dc
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 03:06:31 2015 -0700

    intel/sandybridge: Do not guard native VGA init by #ifdefs
    
    We don't build-test with native VGA init, so if the code is broken by
    a commit, we won't see it when it's guarded by #ifdefs. This has
    already happened in the past. Instead of gurading entire files, use
    the IS_ENABLED() macro, and return early. This at least enables us to
    build-test the code to some extent, while linker garbage collection
    will removed unused parts.
    
    BONUS: Indenting some blocks also makes the difference between
    framebuffer init and textmode init clearer.
    
    Change-Id: I334cdee214872f967ae090170d61a0e4951c6b35
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/northbridge/intel/sandybridge/gma.c            |  38 +++----
 .../intel/sandybridge/gma_ivybridge_lvds.c         | 119 +++++++++++----------
 .../intel/sandybridge/gma_sandybridge_lvds.c       | 119 +++++++++++----------
 3 files changed, 140 insertions(+), 136 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index c465694..d1779db 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -577,29 +577,29 @@ static void gma_func0_init(struct device *dev)
 	/* Init graphics power management */
 	gma_pm_init_pre_vbios(dev);
 
-#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
-	/* PCI Init, will run VBIOS */
-	pci_dev_init(dev);
-#endif
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		/* PCI Init, will run VBIOS */
+		pci_dev_init(dev);
 
 	/* Post VBIOS init */
 	gma_pm_init_post_vbios(dev);
 
-#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
-	/* This should probably run before post VBIOS init. */
-	printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
-	u8 *mmiobase;
-	u32 iobase, physbase, graphics_base;
-	struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
-	iobase = dev->resource_list[2].base;
-	mmiobase = res2mmio(&dev->resource_list[0], 0, 0);
-	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
-	graphics_base = dev->resource_list[1].base;
-
-	int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base);
-	if (lightup_ok)
-		gfx_set_init_done(1);
-#endif
+	if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+		/* This should probably run before post VBIOS init. */
+		printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
+		u8 *mmiobase;
+		u32 iobase, physbase, graphics_base;
+		struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
+		iobase = dev->resource_list[2].base;
+		mmiobase = res2mmio(&dev->resource_list[0], 0, 0);
+		physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+		graphics_base = dev->resource_list[1].base;
+
+		int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase,
+						   mmiobase, graphics_base);
+		if (lightup_ok)
+			gfx_set_init_done(1);
+	}
 }
 
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 65719d1..098f423 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -34,8 +34,6 @@
 #include <device/pci_def.h>
 #include <device/pci_rom.h>
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-
 static void link_train(u8 *mmio)
 {
 	write32(mmio+0xf000c,0x40);
@@ -166,6 +164,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	u8 edid_data[128];
 	struct edid edid;
 
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return 0;
+
 	write32(mmio + 0x00070080, 0x00000000);
 	write32(mmio + DSPCNTR(0), 0x00000000);
 	write32(mmio + 0x00071180, 0x00000000);
@@ -238,31 +239,31 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	u32 pixel_m2 = 1;
 
 	vga_textmode_init();
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	vga_sr_write(1, 1);
-	vga_sr_write(0x2, 0xf);
-	vga_sr_write(0x3, 0x0);
-	vga_sr_write(0x4, 0xe);
-	vga_gr_write(0, 0x0);
-	vga_gr_write(1, 0x0);
-	vga_gr_write(2, 0x0);
-	vga_gr_write(3, 0x0);
-	vga_gr_write(4, 0x0);
-	vga_gr_write(5, 0x0);
-	vga_gr_write(6, 0x5);
-	vga_gr_write(7, 0xf);
-	vga_gr_write(0x10, 0x1);
-	vga_gr_write(0x11, 0);
-
-	edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
-
-	write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
-	write32(mmio + DSPADDR(0), 0);
-	write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
-	write32(mmio + DSPSURF(0), 0);
-	for (i = 0; i < 0x100; i++)
-		write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) {
+		vga_sr_write(1, 1);
+		vga_sr_write(0x2, 0xf);
+		vga_sr_write(0x3, 0x0);
+		vga_sr_write(0x4, 0xe);
+		vga_gr_write(0, 0x0);
+		vga_gr_write(1, 0x0);
+		vga_gr_write(2, 0x0);
+		vga_gr_write(3, 0x0);
+		vga_gr_write(4, 0x0);
+		vga_gr_write(5, 0x0);
+		vga_gr_write(6, 0x5);
+		vga_gr_write(7, 0xf);
+		vga_gr_write(0x10, 0x1);
+		vga_gr_write(0x11, 0);
+
+		edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
+
+		write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
+		write32(mmio + DSPADDR(0), 0);
+		write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
+		write32(mmio + DSPSURF(0), 0);
+		for (i = 0; i < 0x100; i++)
+			write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+	}
 
 	/* Find suitable divisors.  */
 	for (candp1 = 1; candp1 <= 8; candp1++) {
@@ -408,17 +409,17 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	write32(mmio + 0xf0008, 0);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
-	write32(mmio + PF_CTL(0),0);
-	write32(mmio + PF_WIN_SZ(0), 0);
-	write32(mmio + PF_WIN_POS(0), 0);
-#else
-	write32(mmio + PIPESRC(0), (719 << 16) | 399);
-	write32(mmio + PF_WIN_POS(0), 0);
-	write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
-	write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
+		write32(mmio + PF_CTL(0),0);
+		write32(mmio + PF_WIN_SZ(0), 0);
+		write32(mmio + PF_WIN_POS(0), 0);
+	} else {
+		write32(mmio + PIPESRC(0), (719 << 16) | 399);
+		write32(mmio + PF_WIN_POS(0), 0);
+		write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+		write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+	}
 
 	mdelay(1);
 
@@ -428,21 +429,23 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + PIPE_LINK_N1(0), link_n1);
 
 	link_train(mmio);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
-#else
-	write32(mmio+CPU_VGACNTRL,0x298e);
-#endif
+
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+		write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
+	else
+		write32(mmio+CPU_VGACNTRL,0x298e);
+
 	write32(mmio+0x60100,0x44300);
 	write32(mmio+0x60100,0x80044f00);
 
 	mdelay(1);
 	read32(mmio + 0x000f0014); // = 0x00000600
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-	mdelay(1);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
+					| DISPPLANE_BGRX888);
+		mdelay(1);
+	}
 
 	write32(mmio + TRANS_HTOTAL(0),
 		((hactive + right_border + hblank - 1) << 16)
@@ -470,11 +473,12 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	mdelay(1);
 
-	write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-		| TRANS_STATE_MASK
-#endif
-		);
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+		write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+						| TRANS_STATE_MASK);
+	else
+		write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC);
+
 	write32(mmio + PCH_LVDS,
 		LVDS_PORT_ENABLE
 		| (hpolarity << 20) | (vpolarity << 21)
@@ -508,10 +512,11 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + DEIIR, 0xffffffff);
 	write32(mmio + SDEIIR, 0xffffffff);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
-	set_vbe_mode_info_valid(&edid, lfb);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		memset ((void *) lfb, 0, edid.x_resolution
+					* edid.y_resolution * 4);
+		set_vbe_mode_info_valid(&edid, lfb);
+	}
 
 	/* Doesn't change any hw behaviour but vga oprom expects it there. */
 	write32(mmio + 0x0004f040, 0x01000008);
@@ -526,5 +531,3 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	return 1;
 }
-
-#endif
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 266883e..758a41d 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -33,8 +33,6 @@
 #include <device/pci_def.h>
 #include <device/pci_rom.h>
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-
 static void train_link(u8 *mmio)
 {
 	/* Clear interrupts. */
@@ -145,6 +143,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	u32 link_m1;
 	u32 link_n1 = 0x00080000;
 
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return 0;
+
 	write32(mmio + 0x00070080, 0x00000000);
 	write32(mmio + DSPCNTR(0), 0x00000000);
 	write32(mmio + 0x00071180, 0x00000000);
@@ -206,34 +207,34 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	target_frequency = info->lvds_dual_channel ? mode->pixel_clock
 		: (2 * mode->pixel_clock);
-#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	vga_textmode_init();
-#else
-	vga_sr_write(1, 1);
-	vga_sr_write(0x2, 0xf);
-	vga_sr_write(0x3, 0x0);
-	vga_sr_write(0x4, 0xe);
-	vga_gr_write(0, 0x0);
-	vga_gr_write(1, 0x0);
-	vga_gr_write(2, 0x0);
-	vga_gr_write(3, 0x0);
-	vga_gr_write(4, 0x0);
-	vga_gr_write(5, 0x0);
-	vga_gr_write(6, 0x5);
-	vga_gr_write(7, 0xf);
-	vga_gr_write(0x10, 0x1);
-	vga_gr_write(0x11, 0);
-
-
-	edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
-
-	write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
-	write32(mmio + DSPADDR(0), 0);
-	write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
-	write32(mmio + DSPSURF(0), 0);
-	for (i = 0; i < 0x100; i++)
-		write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
-#endif
+
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		vga_sr_write(1, 1);
+		vga_sr_write(0x2, 0xf);
+		vga_sr_write(0x3, 0x0);
+		vga_sr_write(0x4, 0xe);
+		vga_gr_write(0, 0x0);
+		vga_gr_write(1, 0x0);
+		vga_gr_write(2, 0x0);
+		vga_gr_write(3, 0x0);
+		vga_gr_write(4, 0x0);
+		vga_gr_write(5, 0x0);
+		vga_gr_write(6, 0x5);
+		vga_gr_write(7, 0xf);
+		vga_gr_write(0x10, 0x1);
+		vga_gr_write(0x11, 0);
+
+		edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
+
+		write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
+		write32(mmio + DSPADDR(0), 0);
+		write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
+		write32(mmio + DSPSURF(0), 0);
+		for (i = 0; i < 0x100; i++)
+			write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+	} else {
+		vga_textmode_init();
+	}
 
 	/* Find suitable divisors.  */
 	for (candp1 = 1; candp1 <= 8; candp1++) {
@@ -368,15 +369,15 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
 
 	write32(mmio + PF_WIN_POS(0), 0);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
-	write32(mmio + PF_CTL(0),0);
-	write32(mmio + PF_WIN_SZ(0), 0);
-#else
-	write32(mmio + PIPESRC(0), (639 << 16) | 399);
-	write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
-	write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
+		write32(mmio + PF_CTL(0),0);
+		write32(mmio + PF_WIN_SZ(0), 0);
+	} else {
+		write32(mmio + PIPESRC(0), (639 << 16) | 399);
+		write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+		write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+	}
 
 	mdelay(1);
 
@@ -395,17 +396,17 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 	write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
-#else
-	write32(mmio + CPU_VGACNTRL, 0x20298e);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+		write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
+	else
+		write32(mmio + CPU_VGACNTRL, 0x20298e);
+
 	train_link(mmio);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-	mdelay(1);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+		mdelay(1);
+	}
 
 	write32(mmio + TRANS_HTOTAL(0),
 		((hactive + right_border + hblank - 1) << 16)
@@ -430,11 +431,12 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + 0x00060100, 0xb01c4000);
 	write32(mmio + 0x000f000c, 0x801a2350);
 	mdelay(1);
-	write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-		| TRANS_STATE_MASK
-#endif
-		);
+
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+		write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+					   | TRANS_STATE_MASK);
+	else
+		write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC);
 
 	write32(mmio + PCH_LVDS,
 		LVDS_PORT_ENABLE
@@ -468,10 +470,11 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + DEIIR, 0xffffffff);
 	write32(mmio + SDEIIR, 0xffffffff);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
-	set_vbe_mode_info_valid(&edid, lfb);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		memset ((void *) lfb, 0, edid.x_resolution
+					* edid.y_resolution * 4);
+		set_vbe_mode_info_valid(&edid, lfb);
+	}
 
 	/* Linux relies on VBT for panel info.  */
 	generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
@@ -479,5 +482,3 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	return 1;
 }
-
-#endif


From gerrit at coreboot.org  Mon Sep  7 20:56:08 2015
From: gerrit at coreboot.org (Timothy Pearson (tpearson@raptorengineeringinc.com))
Date: Mon, 7 Sep 2015 20:56:08 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	northbridge/amd/amdfam10: Use adequate size for HT speed limit field
References: <Ib7ca49ffd53b0ae98a592b9fe8949dee2d9ae100+0@gerrit.coreboot.org>
Message-ID: <Ib7ca49ffd53b0ae98a592b9fe8949dee2d9ae100+1@gerrit.coreboot.org>

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11587

-gerrit

commit 815f6001074d46e8099f781836dd131cf3a57055
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Mon Sep 7 15:55:50 2015 -0500

    northbridge/amd/amdfam10: Use adequate size for HT speed limit field
    
    Change-Id: Ib7ca49ffd53b0ae98a592b9fe8949dee2d9ae100
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdfam10/amdfam10.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 9461385..a1e08a0 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1005,7 +1005,7 @@ struct nodes_info_t {
 } __attribute__((packed));
 
 struct ht_link_config {
-	uint8_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default)
+	uint32_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default)
 };
 
 /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/


From gerrit at coreboot.org  Mon Sep  7 21:05:02 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 7 Sep 2015 21:05:02 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel i945:
	Fix native VGA initialization
References: <I0663f3b423624c67c2388a9cc44ec41f370f4a17+0@gerrit.coreboot.org>
Message-ID: <E1ZZ3b4-0005FA-Qf@mail.coreboot.org>

the following patch was just integrated into master:
commit 2e4f83b164d2013e0ed856d8771a00993d1c403e
Author: Mono <mono-for-coreboot at donderklumpen.de>
Date:   Mon Sep 7 21:15:26 2015 +0200

    intel i945: Fix native VGA initialization
    
    Native VGA init no longer compiles  from commit:
    * 7dbf9c6 edid: Use edid_mode struct to reduce redundancy
    
    Tested on a single X60 machine.
    
    This patch basically copies 11491 which does
    the same for north/intel/sandybridge.
    
    Change-Id: I0663f3b423624c67c2388a9cc44ec41f370f4a17
    Signed-off-by: Axel Holewa <mono-for-coreboot at donderklumpen.de>
    Reviewed-on: http://review.coreboot.org/11585
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11585 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep  7 21:12:17 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 21:12:17 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	intel/sandybridge: Do not guard native VGA init by #ifdefs
References: <I334cdee214872f967ae090170d61a0e4951c6b35+0@gerrit.coreboot.org>
Message-ID: <I334cdee214872f967ae090170d61a0e4951c6b35+2@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11586

-gerrit

commit d596f16c4010a718b11b7fa4f799658664debe10
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 03:06:31 2015 -0700

    intel/sandybridge: Do not guard native VGA init by #ifdefs
    
    We don't build-test with native VGA init, so if the code is broken by
    a commit, we won't see it when it's guarded by #ifdefs. This has
    already happened in the past. Instead of gurading entire files, use
    the IS_ENABLED() macro, and return early. This at least enables us to
    build-test the code to some extent, while linker garbage collection
    will removed unused parts.
    
    BONUS: Indenting some blocks also makes the difference between
    framebuffer init and textmode init clearer.
    
    Change-Id: I334cdee214872f967ae090170d61a0e4951c6b35
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/northbridge/intel/sandybridge/gma.c            |  38 +++----
 .../intel/sandybridge/gma_ivybridge_lvds.c         | 119 +++++++++++----------
 .../intel/sandybridge/gma_sandybridge_lvds.c       | 119 +++++++++++----------
 3 files changed, 140 insertions(+), 136 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index c465694..d1779db 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -577,29 +577,29 @@ static void gma_func0_init(struct device *dev)
 	/* Init graphics power management */
 	gma_pm_init_pre_vbios(dev);
 
-#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
-	/* PCI Init, will run VBIOS */
-	pci_dev_init(dev);
-#endif
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		/* PCI Init, will run VBIOS */
+		pci_dev_init(dev);
 
 	/* Post VBIOS init */
 	gma_pm_init_post_vbios(dev);
 
-#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
-	/* This should probably run before post VBIOS init. */
-	printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
-	u8 *mmiobase;
-	u32 iobase, physbase, graphics_base;
-	struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
-	iobase = dev->resource_list[2].base;
-	mmiobase = res2mmio(&dev->resource_list[0], 0, 0);
-	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
-	graphics_base = dev->resource_list[1].base;
-
-	int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base);
-	if (lightup_ok)
-		gfx_set_init_done(1);
-#endif
+	if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+		/* This should probably run before post VBIOS init. */
+		printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
+		u8 *mmiobase;
+		u32 iobase, physbase, graphics_base;
+		struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
+		iobase = dev->resource_list[2].base;
+		mmiobase = res2mmio(&dev->resource_list[0], 0, 0);
+		physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+		graphics_base = dev->resource_list[1].base;
+
+		int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase,
+						   mmiobase, graphics_base);
+		if (lightup_ok)
+			gfx_set_init_done(1);
+	}
 }
 
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 65719d1..101a3c1 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -34,8 +34,6 @@
 #include <device/pci_def.h>
 #include <device/pci_rom.h>
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-
 static void link_train(u8 *mmio)
 {
 	write32(mmio+0xf000c,0x40);
@@ -166,6 +164,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	u8 edid_data[128];
 	struct edid edid;
 
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return 0;
+
 	write32(mmio + 0x00070080, 0x00000000);
 	write32(mmio + DSPCNTR(0), 0x00000000);
 	write32(mmio + 0x00071180, 0x00000000);
@@ -238,31 +239,31 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	u32 pixel_m2 = 1;
 
 	vga_textmode_init();
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	vga_sr_write(1, 1);
-	vga_sr_write(0x2, 0xf);
-	vga_sr_write(0x3, 0x0);
-	vga_sr_write(0x4, 0xe);
-	vga_gr_write(0, 0x0);
-	vga_gr_write(1, 0x0);
-	vga_gr_write(2, 0x0);
-	vga_gr_write(3, 0x0);
-	vga_gr_write(4, 0x0);
-	vga_gr_write(5, 0x0);
-	vga_gr_write(6, 0x5);
-	vga_gr_write(7, 0xf);
-	vga_gr_write(0x10, 0x1);
-	vga_gr_write(0x11, 0);
-
-	edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
-
-	write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
-	write32(mmio + DSPADDR(0), 0);
-	write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
-	write32(mmio + DSPSURF(0), 0);
-	for (i = 0; i < 0x100; i++)
-		write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		vga_sr_write(1, 1);
+		vga_sr_write(0x2, 0xf);
+		vga_sr_write(0x3, 0x0);
+		vga_sr_write(0x4, 0xe);
+		vga_gr_write(0, 0x0);
+		vga_gr_write(1, 0x0);
+		vga_gr_write(2, 0x0);
+		vga_gr_write(3, 0x0);
+		vga_gr_write(4, 0x0);
+		vga_gr_write(5, 0x0);
+		vga_gr_write(6, 0x5);
+		vga_gr_write(7, 0xf);
+		vga_gr_write(0x10, 0x1);
+		vga_gr_write(0x11, 0);
+
+		edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
+
+		write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
+		write32(mmio + DSPADDR(0), 0);
+		write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
+		write32(mmio + DSPSURF(0), 0);
+		for (i = 0; i < 0x100; i++)
+			write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+	}
 
 	/* Find suitable divisors.  */
 	for (candp1 = 1; candp1 <= 8; candp1++) {
@@ -408,17 +409,17 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	write32(mmio + 0xf0008, 0);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
-	write32(mmio + PF_CTL(0),0);
-	write32(mmio + PF_WIN_SZ(0), 0);
-	write32(mmio + PF_WIN_POS(0), 0);
-#else
-	write32(mmio + PIPESRC(0), (719 << 16) | 399);
-	write32(mmio + PF_WIN_POS(0), 0);
-	write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
-	write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
+		write32(mmio + PF_CTL(0),0);
+		write32(mmio + PF_WIN_SZ(0), 0);
+		write32(mmio + PF_WIN_POS(0), 0);
+	} else {
+		write32(mmio + PIPESRC(0), (719 << 16) | 399);
+		write32(mmio + PF_WIN_POS(0), 0);
+		write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+		write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+	}
 
 	mdelay(1);
 
@@ -428,21 +429,23 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + PIPE_LINK_N1(0), link_n1);
 
 	link_train(mmio);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
-#else
-	write32(mmio+CPU_VGACNTRL,0x298e);
-#endif
+
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+		write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
+	else
+		write32(mmio+CPU_VGACNTRL,0x298e);
+
 	write32(mmio+0x60100,0x44300);
 	write32(mmio+0x60100,0x80044f00);
 
 	mdelay(1);
 	read32(mmio + 0x000f0014); // = 0x00000600
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-	mdelay(1);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
+					| DISPPLANE_BGRX888);
+		mdelay(1);
+	}
 
 	write32(mmio + TRANS_HTOTAL(0),
 		((hactive + right_border + hblank - 1) << 16)
@@ -470,11 +473,12 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	mdelay(1);
 
-	write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-		| TRANS_STATE_MASK
-#endif
-		);
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+		write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+						| TRANS_STATE_MASK);
+	else
+		write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC);
+
 	write32(mmio + PCH_LVDS,
 		LVDS_PORT_ENABLE
 		| (hpolarity << 20) | (vpolarity << 21)
@@ -508,10 +512,11 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + DEIIR, 0xffffffff);
 	write32(mmio + SDEIIR, 0xffffffff);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
-	set_vbe_mode_info_valid(&edid, lfb);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		memset ((void *) lfb, 0, edid.x_resolution
+					* edid.y_resolution * 4);
+		set_vbe_mode_info_valid(&edid, lfb);
+	}
 
 	/* Doesn't change any hw behaviour but vga oprom expects it there. */
 	write32(mmio + 0x0004f040, 0x01000008);
@@ -526,5 +531,3 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	return 1;
 }
-
-#endif
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 266883e..758a41d 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -33,8 +33,6 @@
 #include <device/pci_def.h>
 #include <device/pci_rom.h>
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-
 static void train_link(u8 *mmio)
 {
 	/* Clear interrupts. */
@@ -145,6 +143,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	u32 link_m1;
 	u32 link_n1 = 0x00080000;
 
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+		return 0;
+
 	write32(mmio + 0x00070080, 0x00000000);
 	write32(mmio + DSPCNTR(0), 0x00000000);
 	write32(mmio + 0x00071180, 0x00000000);
@@ -206,34 +207,34 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	target_frequency = info->lvds_dual_channel ? mode->pixel_clock
 		: (2 * mode->pixel_clock);
-#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	vga_textmode_init();
-#else
-	vga_sr_write(1, 1);
-	vga_sr_write(0x2, 0xf);
-	vga_sr_write(0x3, 0x0);
-	vga_sr_write(0x4, 0xe);
-	vga_gr_write(0, 0x0);
-	vga_gr_write(1, 0x0);
-	vga_gr_write(2, 0x0);
-	vga_gr_write(3, 0x0);
-	vga_gr_write(4, 0x0);
-	vga_gr_write(5, 0x0);
-	vga_gr_write(6, 0x5);
-	vga_gr_write(7, 0xf);
-	vga_gr_write(0x10, 0x1);
-	vga_gr_write(0x11, 0);
-
-
-	edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
-
-	write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
-	write32(mmio + DSPADDR(0), 0);
-	write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
-	write32(mmio + DSPSURF(0), 0);
-	for (i = 0; i < 0x100; i++)
-		write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
-#endif
+
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		vga_sr_write(1, 1);
+		vga_sr_write(0x2, 0xf);
+		vga_sr_write(0x3, 0x0);
+		vga_sr_write(0x4, 0xe);
+		vga_gr_write(0, 0x0);
+		vga_gr_write(1, 0x0);
+		vga_gr_write(2, 0x0);
+		vga_gr_write(3, 0x0);
+		vga_gr_write(4, 0x0);
+		vga_gr_write(5, 0x0);
+		vga_gr_write(6, 0x5);
+		vga_gr_write(7, 0xf);
+		vga_gr_write(0x10, 0x1);
+		vga_gr_write(0x11, 0);
+
+		edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
+
+		write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
+		write32(mmio + DSPADDR(0), 0);
+		write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
+		write32(mmio + DSPSURF(0), 0);
+		for (i = 0; i < 0x100; i++)
+			write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+	} else {
+		vga_textmode_init();
+	}
 
 	/* Find suitable divisors.  */
 	for (candp1 = 1; candp1 <= 8; candp1++) {
@@ -368,15 +369,15 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
 
 	write32(mmio + PF_WIN_POS(0), 0);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
-	write32(mmio + PF_CTL(0),0);
-	write32(mmio + PF_WIN_SZ(0), 0);
-#else
-	write32(mmio + PIPESRC(0), (639 << 16) | 399);
-	write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
-	write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
+		write32(mmio + PF_CTL(0),0);
+		write32(mmio + PF_WIN_SZ(0), 0);
+	} else {
+		write32(mmio + PIPESRC(0), (639 << 16) | 399);
+		write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+		write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+	}
 
 	mdelay(1);
 
@@ -395,17 +396,17 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 	write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
-#else
-	write32(mmio + CPU_VGACNTRL, 0x20298e);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+		write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
+	else
+		write32(mmio + CPU_VGACNTRL, 0x20298e);
+
 	train_link(mmio);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-	mdelay(1);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+		mdelay(1);
+	}
 
 	write32(mmio + TRANS_HTOTAL(0),
 		((hactive + right_border + hblank - 1) << 16)
@@ -430,11 +431,12 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + 0x00060100, 0xb01c4000);
 	write32(mmio + 0x000f000c, 0x801a2350);
 	mdelay(1);
-	write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-		| TRANS_STATE_MASK
-#endif
-		);
+
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+		write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+					   | TRANS_STATE_MASK);
+	else
+		write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC);
 
 	write32(mmio + PCH_LVDS,
 		LVDS_PORT_ENABLE
@@ -468,10 +470,11 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	write32(mmio + DEIIR, 0xffffffff);
 	write32(mmio + SDEIIR, 0xffffffff);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
-	set_vbe_mode_info_valid(&edid, lfb);
-#endif
+	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+		memset ((void *) lfb, 0, edid.x_resolution
+					* edid.y_resolution * 4);
+		set_vbe_mode_info_valid(&edid, lfb);
+	}
 
 	/* Linux relies on VBT for panel info.  */
 	generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
@@ -479,5 +482,3 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 
 	return 1;
 }
-
-#endif


From gerrit at coreboot.org  Mon Sep  7 21:55:05 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 7 Sep 2015 21:55:05 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: microcode: Unify
	rules to add microcode to CBFS once again
References: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+0@gerrit.coreboot.org>
Message-ID: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+6@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526

-gerrit

commit 62faaccc16dcdbd3fe752de82aef9beecb47ea58
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:35:55 2015 -0700

    microcode: Unify rules to add microcode to CBFS once again
    
    Now that cbfstool supports file alignment, we can use the conveniently
    available <filename>-align handler, and remove the need to have a
    separate rule in src/Makefile.inc just for adding the microcode.
    
    We can also get rid of the layering violation of having the
    CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
    Note that we still have a layering violation by the use of the
    CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
    for the time being.
    
    Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 Makefile.inc                                  |  1 -
 src/cpu/Makefile.inc                          | 20 +++++++-------------
 src/soc/intel/braswell/microcode/Makefile.inc | 11 -----------
 src/soc/intel/skylake/microcode/Makefile.inc  | 11 -----------
 4 files changed, 7 insertions(+), 36 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..be6021b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(
 	-B $(objcbfs)/bootblock.bin \
 	$(CBFSTOOL_PRE1_OPTS)
 	$(prebuild-files) true
-	$(call add-cpu-microcode-to-cbfs,$@.tmp)
 	mv $@.tmp $@
 else
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index cdd353f..d757c79 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64))
 ## Rules for building the microcode blob in CBFS
 ################################################################################
 
-cpu_ucode_cbfs_name = cpu_microcode_blob.bin
-
 # External microcode file, or are we generating one ?
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
 cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
@@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y)
-cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)"
-else
-cpu_ucode_cbfs_offset = "-b"
-endif
-
 # In case we have more than one "source" (cough) files containing microcode, we
 # link them together in one large blob, so that we get all the microcode updates
 # in one file. This makes it easier for objcopy in the final step.
@@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
 	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
 
-ifeq ($(cbfs_include_ucode),y)
-# Add CPU microcode to specified rom image $(1)
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset)
+cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
+cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
+cpu_microcode_blob.bin-type := microcode
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
+cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
 else
-add-cpu-microcode-to-cbfs = true
+cpu_microcode_blob.bin-align := 16
 endif
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
index da25b8b..3497328 100644
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ b/src/soc/intel/braswell/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-y += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
index a5e8981..ba308f6 100644
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ b/src/soc/intel/skylake/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-


From gerrit at coreboot.org  Mon Sep  7 23:07:47 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 7 Sep 2015 23:07:47 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	northbridge/amd/amdfam10: Use adequate size for HT speed limit field
References: <Ib7ca49ffd53b0ae98a592b9fe8949dee2d9ae100+0@gerrit.coreboot.org>
Message-ID: <E1ZZ5Vr-0003to-Lh@mail.coreboot.org>

the following patch was just integrated into master:
commit 8ac492999a57aa112fbcc063c6e0689d2c5d4776
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Mon Sep 7 15:55:50 2015 -0500

    northbridge/amd/amdfam10: Use adequate size for HT speed limit field
    
    Change-Id: Ib7ca49ffd53b0ae98a592b9fe8949dee2d9ae100
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
    Reviewed-on: http://review.coreboot.org/11587
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>


See http://review.coreboot.org/11587 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep  7 23:51:28 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 7 Sep 2015 23:51:28 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	intel/sandybridge: Do not guard native VGA init by #ifdefs
References: <I334cdee214872f967ae090170d61a0e4951c6b35+0@gerrit.coreboot.org>
Message-ID: <E1ZZ6C8-0000YP-Kx@mail.coreboot.org>

the following patch was just integrated into master:
commit 9647094672eb2ea31c6192de92028614164b9d9c
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 03:06:31 2015 -0700

    intel/sandybridge: Do not guard native VGA init by #ifdefs
    
    We don't build-test with native VGA init, so if the code is broken by
    a commit, we won't see it when it's guarded by #ifdefs. This has
    already happened in the past. Instead of gurading entire files, use
    the IS_ENABLED() macro, and return early. This at least enables us to
    build-test the code to some extent, while linker garbage collection
    will removed unused parts.
    
    BONUS: Indenting some blocks also makes the difference between
    framebuffer init and textmode init clearer.
    
    Change-Id: I334cdee214872f967ae090170d61a0e4951c6b35
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11586
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11586 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep  7 23:51:35 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 7 Sep 2015 23:51:35 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: microcode:
	Unify rules to add microcode to CBFS once again
References: <Id2f8c15d250a0c75300d0a870284cac0c68a311b+0@gerrit.coreboot.org>
Message-ID: <E1ZZ6CF-0000aj-Up@mail.coreboot.org>

the following patch was just integrated into master:
commit f55e6680b94a12bdbe8bf4860b3323dac41a9a11
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 7 00:35:55 2015 -0700

    microcode: Unify rules to add microcode to CBFS once again
    
    Now that cbfstool supports file alignment, we can use the conveniently
    available <filename>-align handler, and remove the need to have a
    separate rule in src/Makefile.inc just for adding the microcode.
    
    We can also get rid of the layering violation of having the
    CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
    Note that we still have a layering violation by the use of the
    CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
    for the time being.
    
    Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11526
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11526 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 01:39:04 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 8 Sep 2015 01:39:04 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	romstage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+8@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit 2f28e43694c7a552b910bd002c6be8414fbfdbfa
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add romstage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 00d8d27..fe974ef 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..b19b954
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Tue Sep  8 02:25:22 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 02:25:22 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	drivers/intel/fsp1_1: Take platform ID as a string, not integers
References: <I76da85fab59fe4891fbc3b5edf430f2791b70ffb+0@gerrit.coreboot.org>
Message-ID: <E1ZZ8b4-0000w3-Dm@mail.coreboot.org>

the following patch was just integrated into master:
commit 5c261229aebe4a8bdc67c80be06e17795fc34c1b
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sat Aug 29 18:53:43 2015 -0700

    drivers/intel/fsp1_1: Take platform ID as a string, not integers
    
    The platform ID is an 8 character ASCII string, so our config should
    take it in as a string, rather than a set of two 32-bit integers.
    
    Change-Id: I76da85fab59fe4891fbc3b5edf430f2791b70ffb
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11465
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at gmail.com>


See http://review.coreboot.org/11465 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 04:10:23 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:10:23 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+14@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 9cea85e7edd9c54555f1f5bd5976a61bfa333dc0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Tue Sep  8 04:10:50 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:10:50 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+15@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit 9456d2288027b4b0e58c1ae063c7d714ddf9d39d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3963339..5f9c3c1 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Tue Sep  8 04:11:13 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:11:13 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+16@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit a524617267a3302075ab83b44daecd52d09aff03
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3c1871e..0315798 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..4bb7250 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Tue Sep  8 04:11:16 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:11:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	romstage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit 12fbc843eb56434f28eeaaea09b569a834bbea6a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add romstage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 00d8d27..fe974ef 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..b19b954
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Tue Sep  8 04:11:29 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:11:29 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit 570f48653cf290e48a4dd647b54299968e5ffaff
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Tue Sep  8 04:11:48 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:11:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+14@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 6de6d370d250a60a13c4fe050b4413534e1472f9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               |  42 +++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    | 130 ++++++++++++++++++++++++++++++++++
 src/lib/ramstage.ld                   | 115 ------------------------------
 7 files changed, 197 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 10a94c3..3c1871e 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -295,7 +295,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3963339 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,12 +127,12 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..02d017a
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+.text : {
+	SYMBOL_CURRENT_LOC(program)
+	SYMBOL_CURRENT_LOC(text)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
+	KEEP(*(.rodata.cbmem_init_hooks));
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#endif
+
+#if ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(pci_drivers)
+	KEEP(*(.rodata.pci_driver));
+	SYMBOL_CURRENT_LOC(epci_drivers)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cpu_drivers)
+	KEEP(*(.rodata.cpu_driver));
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	*(.rodata);
+	*(.rodata.*);
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(etext)
+} : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+.ctors : {
+	ALIGN_COUNTER(0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+}
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+#if ARCH_STAGE_HAS_DATA_SECTION
+.data : {
+	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(data)
+	*(.data);
+	*(.data.*);
+
+#ifdef __PRE_RAM__
+	PROVIDE(_preram_cbmem_console = .);
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bs_init_begin)
+	KEEP(*(.bs_init));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(edata)
+}
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+.bss : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bss)
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(ebss)
+}
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+.heap : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(heap)
+	. += CONFIG_HEAP_SIZE;
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(eheap)
+}
+#endif
+
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Tue Sep  8 04:11:59 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:11:59 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit 761606da50621f8f4f6986475cbbcf4c38829403
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 5f9c3c1..d4be3f8 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,4 +139,31 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Tue Sep  8 04:12:08 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:12:08 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit 021835809390d080b2b1705adbdfef56f79a1f00
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0315798..788d7c7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -294,11 +294,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..6793ca1
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 4bb7250..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Tue Sep  8 04:12:16 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:12:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit 92e7d841d543a4fb9f1419f06ec7be33980a87f9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |   4 +-
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/program.ld                    |  15 +++--
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 14 files changed, 64 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index be6021b..4add195 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..b3112e3 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBTLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index d4be3f8..a25e018 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index d147d3c..1563f2d 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /*
@@ -84,6 +99,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 02d017a..43b1fea 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -74,13 +74,20 @@
 .data : {
 	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(data)
+
+#if ENV_RMODULE
+	SYMBOL_CURRENT_LOC(rmodule_params)
+	KEEP(*(.module_parameters));
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#endif
+
 	*(.data);
 	*(.data.*);
 
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
@@ -111,7 +118,7 @@
 .heap : {
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(heap)
-	. += CONFIG_HEAP_SIZE;
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(eheap)
 }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Tue Sep  8 04:12:26 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:12:26 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit cc798117d18ae90d614f18db4f84c2352ffbf5b4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 788d7c7..3d1d214 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -298,7 +298,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Tue Sep  8 04:12:39 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:12:39 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit 3bd63ea79c710f45d38276020654aacbce3f88ba
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Tue Sep  8 04:12:50 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:12:50 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit 334288a66db8515d6c383e4c469c71972d9ca92f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/lib/Makefile.inc      |  9 ++++++---
 src/lib/program.ld        |  6 +++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3d1d214..68ed810 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -282,17 +282,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -300,8 +294,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 43b1fea..794dcf8 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -87,7 +87,7 @@
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));


From gerrit at coreboot.org  Tue Sep  8 04:13:03 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:13:03 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit 65dfd724951f79165d81027172993723ed360783
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..d147d3c 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,27 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/*
+ * Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. Also AGES
+ * apparently builds compeletely separate from our build infrastructure
+ * hardcoding its own rules.
+ */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Tue Sep  8 04:13:16 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:13:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit 2b050b4d3b241484505c8430a71a26d8a32e15c5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 54 +++++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++
 src/arch/x86/bootblock.ld                      | 29 ++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 32 files changed, 155 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..b0546f5 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
 bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+	touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock.ld, $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..7276c7a
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generated by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions at the beginning of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
new file mode 100644
index 0000000..6835430
--- /dev/null
+++ b/src/arch/x86/bootblock.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/x86/failover.ld>
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
+
+/* Include generated .ld files. */
+#include <generated/bootblock.ld>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Tue Sep  8 04:13:27 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:13:27 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: don't create
	MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit 54745a585088a115140940efe89c423005a74ddf
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b0546f5..00d8d27 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -125,13 +125,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Tue Sep  8 04:13:28 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 04:13:28 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: provide
	minimum alignment for romstage
References: <Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15+0@gerrit.coreboot.org>
Message-ID: <Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11588

-gerrit

commit 5f5ce994edfba1d7d072dc6afb759df991a4b19e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Sep 7 23:05:28 2015 -0500

    x86: provide minimum alignment for romstage
    
    The current way the XIP address of romstage is calculated is by
    doing a 'cbfstool locate' using a bin file of romstage linked
    at address 0. That address is then used for re-linking romstage at
    the address spit out by cbfstool. Currently, the linker actually
    sets minimum alignment on the text sections as 32 bytes, but it
    doesn't actually honor that value. Instead, provide a minimum
    alignment for romstage so as not to fight the linker.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built asus/kfsn4-dre. Confirmed ROMSTAGE_BASE == gdtptr.
    
    Change-Id: Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index fe974ef..10a94c3 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -207,9 +207,15 @@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xi
 	sed -e '/^ROMSTAGE_BASE/d' $(objgenerated)/romstage_null.ld >> $@.tmp
 	mv $@.tmp $@
 
+# Use a '-a 64' option to cbfstool locate to provide a minimum alignment
+# requirement for the overall romstage. While the first object within
+# romstage could have a 4 byte minimum alignment that doesn't mean the linker
+# won't decide the entire section should be aligned to a larger value. In the
+# future cbfstool should add XIP files proper and honor the alignment
+# requirements of the program segment.
 $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	rm -f $@
-	$(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \
+	$(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) -a 64 > $@.tmp \
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 


From gerrit at coreboot.org  Tue Sep  8 11:16:16 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:16:16 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Update
	4GB DIMM SPD for 1866
References: <Ibb84f77565d46894afe2153f5951e17a450413fc+0@gerrit.coreboot.org>
Message-ID: <E1ZZGsp-0000Ny-Tt@mail.coreboot.org>

the following patch was just integrated into master:
commit 1bfbe7e72a3bb0562e190136a77f889d2cdb81f4
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 21 13:09:10 2015 -0700

    glados: Update 4GB DIMM SPD for 1866
    
    Enable 1866 timings in the 4GB Hynix SPD.
    
    BUG=chrome-os-partner:44394
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423
    Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295174
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11528
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11528 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:16:32 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:16:32 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Fix and clean up PCIE _PRT entries
References: <I76ff07d2bf7001aed504558d55cca9e19c692d7e+0@gerrit.coreboot.org>
Message-ID: <E1ZZGt6-0000R1-9X@mail.coreboot.org>

the following patch was just integrated into master:
commit 08112303065bf4d8ebd009c2b5bd1364d4d872ac
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 15:49:12 2015 -0700

    skylake: ACPI: Fix and clean up PCIE _PRT entries
    
    Fix the code for PCIE _PRT entries to use an actual root
    port number from the device instead of NVS that was never
    initialized from zero.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=build and boot on glados with pci=nomsi to ensure interrupts work
    
    Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
    Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295902
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11529
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11529 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:16:48 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:16:48 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Clean up pch.asl
References: <I51b1c5286fc344df6942a24c1dea71abf10ab561+0@gerrit.coreboot.org>
Message-ID: <E1ZZGtM-0000TL-Tc@mail.coreboot.org>

the following patch was just integrated into master:
commit 86d937fb46bfb3b4d5c850b28e79ff25cb56faa4
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:01:08 2015 -0700

    skylake: ACPI: Clean up pch.asl
    
    Clean up the code in pch.asl:
    - move all the C header includes into here instead of duplicated
    in various ASL files included from here
    - move the trap field definition into platform.asl with the method
    - alphebetize the includes
    - move gpio.asl include into pch.asl
    - remove duplicate irqlinks.asl include from lpc.asl
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I51b1c5286fc344df6942a24c1dea71abf10ab561
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3ee9c4afa031191d275f0d3d40b2b15b85369b2f
    Original-Change-Id: I3bae434ad227273885d8436db23e17e593739f77
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295903
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11530
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11530 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:17:08 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:17:08 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Add functions for PCR access
References: <Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d+0@gerrit.coreboot.org>
Message-ID: <E1ZZGtg-0000XJ-1b@mail.coreboot.org>

the following patch was just integrated into master:
commit bf9df75eac002296b570620f824d7bf7011de1e4
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:03:45 2015 -0700

    skylake: ACPI: Add functions for PCR access
    
    There are a few places in ACPI that touch PCR registers,
    either to read a value or to set some magic bits.
    
    Expose some functions for this that will keep all the PCR
    access in one location instead of spread throughout the code.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e78b2801fbc5c00ba452ae5e4ecb07c3e23bf6c1
    Original-Change-Id: I2e4d491157f7ac6d2ebc231b11661c059b4a7fa0
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295904
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11531
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11531 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:17:21 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:17:21 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: PCR:
	Add Port ID for SCS
References: <I0f0144ef79d3691fa120dafc9a31d2a681bf2a28+0@gerrit.coreboot.org>
Message-ID: <E1ZZGtt-0000Zy-EH@mail.coreboot.org>

the following patch was just integrated into master:
commit fe85ae3f41912ce021c0ffe9a0cfcf4798da5da1
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:35:06 2015 -0700

    skylake: PCR: Add Port ID for SCS
    
    Add the PCR Port ID for the storage controllers and
    reformat to put the PCR PIDs in increasing order.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9
    Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295905
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11532
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11532 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:17:56 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:17:56 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake:
	iomap: Remove unused RCBA region
References: <If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48+0@gerrit.coreboot.org>
Message-ID: <E1ZZGuS-0000ex-VG@mail.coreboot.org>

the following patch was just integrated into master:
commit fbd5367b1c8d5d95063fc03930effb8f54c96831
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:39:31 2015 -0700

    skylake: iomap: Remove unused RCBA region
    
    Remove the now unused RCBA base and size from iomap.h
    and fix a trivial typo that doesn't seem to get used
    anywhere.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emege-glados coreboot
    
    Change-Id: If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: ee7b1a8a75a9e9dc191c16ddc32b6a38acec398c
    Original-Change-Id: I0c49803d47105c3c55121caedaffaa249c4f0189
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295906
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11533
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11533 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:18:10 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:18:10 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Remove itss.asl and cleanup irqlinks.asl
References: <I1af7d730542fd0e79b9f3db9f0796e7c701c59e6+0@gerrit.coreboot.org>
Message-ID: <E1ZZGug-0000hY-9n@mail.coreboot.org>

the following patch was just integrated into master:
commit 9171f1ab8d9164f909f794a8a308a944ddefc74d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:48:11 2015 -0700

    skylake: ACPI: Remove itss.asl and cleanup irqlinks.asl
    
    Move the itss.asl code that was exporting PIRQ routing
    control registers into irqlinks.asl and use the PCR access
    methods to find the appropriate address.  At the same time
    clean up the code in irqlinks.asl to follow formatting rules.
    
    Also now that the GPIO code in itss.asl is unused the file
    can be removed.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I1af7d730542fd0e79b9f3db9f0796e7c701c59e6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 39a96063d01d00ab768db1c723f78b5af9ed6513
    Original-Change-Id: Iafa03c276cb276ec8c00c24ed2dba48d0dc9612b
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295907
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11534
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11534 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:18:36 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:18:36 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Move storage controllers to separate file
References: <I43081e661b7220bfa635c2d166c3675a0ff910d6+0@gerrit.coreboot.org>
Message-ID: <E1ZZGv6-0000k2-Ke@mail.coreboot.org>

the following patch was just integrated into master:
commit 86f23acee5e9945efe1aaf99dd6dc9deb6554b11
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:53:45 2015 -0700

    skylake: ACPI: Move storage controllers to separate file
    
    Move the storage controller devices out of serialio.asl
    and into a new scs.asl file and implement the power
    gating workarounds for D0 and D3 transitions.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529
    Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295908
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11535
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11535 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:18:54 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:18:54 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Remove SerialIO ACPI mode code
References: <Id0112830211707ba3d67d4dda29dd93397b5b180+0@gerrit.coreboot.org>
Message-ID: <E1ZZGvO-0000mh-Fu@mail.coreboot.org>

the following patch was just integrated into master:
commit bf31983836e7546ce03061280a7c612d86c70fc9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:58:23 2015 -0700

    skylake: ACPI: Remove SerialIO ACPI mode code
    
    Skylake moves back to having SerialIO devices be enumerated
    as PCI devices instead of putting them all in ACPI mode.
    
    There is currently no code that populates the device_nvs
    fields so all the ACPI code to support that is dead.
    
    Additionally because it contains _PS0/_PS3 methods that
    causes the kernel to not use the standard PCIe PME handlers
    and results in confusing messages at boot about not being
    able to transition to a non-D0 state from D3.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=build and boot on glados and ensure I2C devices work
    
    Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b
    Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295909
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11536
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11536 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:19:22 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:19:22 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Clean up and fix XHCI ACPI Device
References: <I535c9d22308c45a3b9bf7e4045c3d01481acc19c+0@gerrit.coreboot.org>
Message-ID: <E1ZZGvq-0000qX-Ol@mail.coreboot.org>

the following patch was just integrated into master:
commit e32da955b3a4e9674c6c5012e895c79c2696032e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 17:09:02 2015 -0700

    skylake: ACPI: Clean up and fix XHCI ACPI Device
    
    - Remove the old workarounds for XHCI from broadwell
    - Add PMC device to expose bits needed for XHCI workarounds
    - Implement the new workarounds for XHCI, the first will set
    a bit in the XHCI MMIO and the second will send a message
    to the PMC if a bit is set indicating the workaround is available.
    - Clean up the HS/SS port defines and remove unnecessary
    methods to determine the port count since we only support SPT-LP.
    
    BUG=chrome-os-partner:44622,chrome-os-partner:44518
    BRANCH=none
    TEST=build and boot on glados, verify that D0 and D3 can be
    made to work (by disabling unused USB and the misbehaving camera)
    
    Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88
    Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295950
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11537
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11537 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:19:44 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:19:44 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Clean up GPIO controller
References: <Ic82fcb00285aeb2515e24001ef69a882c3df1417+0@gerrit.coreboot.org>
Message-ID: <E1ZZGwD-0000sU-60@mail.coreboot.org>

the following patch was just integrated into master:
commit c97106fd48daf34bf89cf8422455e2b6e0878dd2
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 17:15:00 2015 -0700

    skylake: ACPI: Clean up GPIO controller
    
    Switch the GPIO controller to use the PCR functions that are
    defined in pcr.asl.
    
    Have the default memory regions declare a size of zero and
    be fixed up in the _CRS in order to fix compile issues on
    some versions of iasl.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ic82fcb00285aeb2515e24001ef69a882c3df1417
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: be24d9ccd9db62ca694f3a67436af25a73f59c5a
    Original-Change-Id: I13acd891427f467e289d5671add5617befef4380
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295951
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11538
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11538 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:22:29 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:22:29 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: allow
	timer_monotonic_get() in all stages
References: <I8294c74abe09947fb4438bf5c1d0fc5265491694+0@gerrit.coreboot.org>
Message-ID: <E1ZZGyr-0001Cp-UJ@mail.coreboot.org>

the following patch was just integrated into master:
commit bdc1c878992076da145b3c1d775f86adaa37ecde
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Aug 28 01:58:18 2015 -0500

    skylake: allow timer_monotonic_get() in all stages
    
    The timer_monotonic_get() function wasn't being compiled for
    romstage. To simplify the implementation don't keep track of
    partial microsecond ticks and just return the MSR value divided
    by 24 (24MHz clock).
    
    BUG=chrome-os-partner:42115
    BRANCH=None
    TEST=Build and booted glados. Used monotonic timers in romstage
         in subsequent patches.
    
    Change-Id: I8294c74abe09947fb4438bf5c1d0fc5265491694
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6d60ef204fc92c26748ab57d4ff37830cd8dc664
    Original-Change-Id: Ibdb6b9e20b9f2d48ff0f8a8c782f5c1f7ddde4f7
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295237
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11540
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11540 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:22:42 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:22:42 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: fix
	eventlog on resume path
References: <I187baa940bb45ef90ab82e67c02f13d8855d364e+0@gerrit.coreboot.org>
Message-ID: <E1ZZGz4-0001Ea-Kv@mail.coreboot.org>

the following patch was just integrated into master:
commit 394d6993b90d73d4fca7b7500b753e1d18452cd7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Aug 28 02:14:48 2015 -0500

    skylake: fix eventlog on resume path
    
    The spi_init() routine needs to be called in all boot paths to allow
    writes to the SPI part. The reason is that the write enable is done
    in spi_init(). Moreover, this is also required for a writing a firmware
    update after a resume.
    
    BUG=chrome-os-partner:42115
    BRANCH=None
    TEST=Built and booted glados. Suspended and resumed. Eventlogs show
         up in resume path.
    
    Change-Id: I187baa940bb45ef90ab82e67c02f13d8855d364e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8813ab227395cfcba46ad4109730a1eb5897e538
    Original-Change-Id: Ida726fc29e6d49cd9af02c4e57125e09f2599c36
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295238
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11541
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11541 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:29:57 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:29:57 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: move
	flash_controller.h to the proper place
References: <Ia018c20f97f267b8f7592b2459d10eafe5ec7159+0@gerrit.coreboot.org>
Message-ID: <E1ZZH66-0001z0-Ad@mail.coreboot.org>

the following patch was just integrated into master:
commit ce03aaf08c98ce8bc4cb679418f0b82ca50c9a94
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Aug 27 14:28:35 2015 -0500

    skylake: move flash_controller.h to the proper place
    
    I missed this in code review. This should be under the soc
    directory.
    
    BUG=chrome-os-partner:43522
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: Ia018c20f97f267b8f7592b2459d10eafe5ec7159
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9c081ed6de46605b7d0a72962ac2a041c470b12c
    Original-Change-Id: Ic3938fe5d71bd24a395304cfabe40eff48bc4a40
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295239
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11542
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11542 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:30:17 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:30:17 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake:
	refactor flash_controller code
References: <I0ddd42f0744cf8f88da832d7d715663238209a71+0@gerrit.coreboot.org>
Message-ID: <E1ZZH6P-00023K-1h@mail.coreboot.org>

the following patch was just integrated into master:
commit 11f356c3904321838d69e31f6de3a7fad9d8f42d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Aug 27 14:30:22 2015 -0500

    skylake: refactor flash_controller code
    
    There's no need to add any typedefs nor guard code with
    ENV_ROMSTAGE. The linker will garbage collect unused functions.
    Additionally there were a few errors in the code including
    the operation mask wasn't wide enough to clear out old operations
    as well as component size decoding was incorrect.
    
    The big difference in the code flow is that the operation
    setup is now in one place. The stopwatch API is also used in
    order to not open code time calculations.
    
    BUG=chrome-os-partner:42115
    BUG=chrome-os-partner:43522
    BRANCH=None
    TEST=Built and booted. Suspended and resumed. event log is populated
         for all.
    
    Change-Id: I0ddd42f0744cf8f88da832d7d715663238209a71
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9893fe309104c05edfb158afda6bb029801c0489
    Original-Change-Id: I6468f5b9b4a73885b69ebd916861dd2e8e3746b6
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295980
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11543
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11543 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:30:35 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:30:35 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake:
	Remove dead code
References: <I3d457a196d12d03340bceb444d1d6c95afef13df+0@gerrit.coreboot.org>
Message-ID: <E1ZZH6h-00025m-SL@mail.coreboot.org>

the following patch was just integrated into master:
commit 15c220dc3918755b72ac7eb1e128fc65c6b64cf7
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Thu Aug 20 19:04:31 2015 -0700

    skylake: Remove dead code
    
    Remove dead code not called by any part of coreboot.
    
    BRANCH=none
    BUG=None
    TEST=Build and run on skylake
    
    Change-Id: I3d457a196d12d03340bceb444d1d6c95afef13df
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 58ea135813afeef773f37023fda58f36d544beef
    Original-Change-Id: Id8f4591f20d41f875348c6583618bbcaaf9d9a3a
    Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/294953
    Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Tested-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11544
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11544 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:31:20 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:31:20 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: Apply
	USB2 and USB3 port enable/disable settings
References: <I13d4eb901215308de4b59083339832d29ce0049f+0@gerrit.coreboot.org>
Message-ID: <E1ZZH7Q-0002C2-Tc@mail.coreboot.org>

the following patch was just integrated into master:
commit 3745c65c832ab0abb557cf68e92a6ad2c09f0faf
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 28 17:21:07 2015 -0700

    skylake: Apply USB2 and USB3 port enable/disable settings
    
    The USB port enable/disable settings were never getting applied to
    the UPD configuration and so were not getting used by FSP.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=build and boot on glados
    
    Change-Id: I13d4eb901215308de4b59083339832d29ce0049f
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4
    Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296034
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11547
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11547 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:31:33 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:31:33 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados:
	Disable unused USB ports
References: <I8c999e3b17478effc39cf078f8420f63413d091b+0@gerrit.coreboot.org>
Message-ID: <E1ZZH7d-0002EO-SX@mail.coreboot.org>

the following patch was just integrated into master:
commit 5c44d2e23ec90eac5996aebbae214d3fe84b53ce
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 28 17:22:04 2015 -0700

    glados: Disable unused USB ports
    
    Enable only the USB ports that are connected on-board or to an
    external port, all others will be disabled.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=build and boot on glados, ensure expected USB ports still work
    
    Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163
    Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296035
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11548
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11548 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:32:04 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:32:04 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Disable unused USB ports
References: <I909a6fab553bba829349dd08fa9cc3f26e5adeb2+0@gerrit.coreboot.org>
Message-ID: <E1ZZH88-0002JG-Rj@mail.coreboot.org>

the following patch was just integrated into master:
commit 2b9595a8722a92ea19d1ca51d975c4ba9a5fa11f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 28 17:48:11 2015 -0700

    kunimitsu: Disable unused USB ports
    
    Enable only the USB ports that are connected on-board or to an
    external port, all others will be disabled.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=emerge-kunimitsu coreboot, change verified in schematic but not tested
    
    Change-Id: I909a6fab553bba829349dd08fa9cc3f26e5adeb2
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 1b0ce28d093e3b12273d7e0f56b47fb5b13d712f
    Original-Change-Id: I0c4b7de6e559595efa97d756e43f8398feccdffd
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296036
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11549
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11549 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:32:24 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:32:24 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Fix
	incorrect comment format in devicetree.cb
References: <I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b+0@gerrit.coreboot.org>
Message-ID: <E1ZZH8S-0002MB-PF@mail.coreboot.org>

the following patch was just integrated into master:
commit 0d65df93f0d20da3cb78a88907f860062fe77a2a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 31 09:49:08 2015 -0700

    glados: Fix incorrect comment format in devicetree.cb
    
    The devicetree.cb compiler can't handle C style /**/ comments,
    they need to be shell-style #.  Due to a last minute formatting
    change in my commit to enable USB ports this broke the glados
    build.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2
    Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296301
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11553
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11553 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:32:54 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:32:54 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: sklrvp: Clean
	up devicetree.cb
References: <I232bd62853685bdcda771e3cbaba2d8ee7437b81+0@gerrit.coreboot.org>
Message-ID: <E1ZZH8v-0002Qn-Fu@mail.coreboot.org>

the following patch was just integrated into master:
commit e031ec3ca33f1a1487c62a984cfd699e09123a34
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:03:09 2015 -0700

    sklrvp: Clean up devicetree.cb
    
    Remove devicetree.cb settings that do not apply to skylake so
    they can be removed from chip.h and clean up the pci device
    comments and add missing devices.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-sklrvp coreboot
    
    Change-Id: I232bd62853685bdcda771e3cbaba2d8ee7437b81
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a22e1fa56c68b06192acbeeb5c76862d84b8f509
    Original-Change-Id: I61f0581069d87ab974b0fffa6478b44a71bdd69b
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297337
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11560
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11560 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:33:49 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:33:49 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Clean up devicetree.cb
References: <Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a+0@gerrit.coreboot.org>
Message-ID: <E1ZZH9p-0002Vf-5S@mail.coreboot.org>

the following patch was just integrated into master:
commit 1c2de9fc3df6c5994db7bf2ee613aeb020b9b9db
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:05:00 2015 -0700

    kunimitsu: Clean up devicetree.cb
    
    Fix the PCI device list comments to be consistent between
    mainboards and remove unused and incorrect register settings.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8
    Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297339
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11562
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11562 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:34:02 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:34:02 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: Clean
	up chip.h
References: <Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3+0@gerrit.coreboot.org>
Message-ID: <E1ZZHA2-0002Xf-Gj@mail.coreboot.org>

the following patch was just integrated into master:
commit 0c66e866c95758c0e5557581a3af2cef4743c4ff
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:05:59 2015 -0700

    skylake: Clean up chip.h
    
    Remove config options that do not apply and are unused on skylake.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3224b89e310909c2836ef2c669c6b2ee826b1b28
    Original-Change-Id: I2b4fe85f78480eac5635e78ce4e848f73967bd27
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297740
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11563
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11563 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:35:43 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:35:43 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: Skylake:Set
	DISB inside romstage after mrc init
References: <I230ff76287f90c5d3655a77bbaca666af37c4aae+0@gerrit.coreboot.org>
Message-ID: <E1ZZHBf-0002hU-KS@mail.coreboot.org>

the following patch was just integrated into master:
commit 9ae6cd4280f0ff02711726393b74ca119fb1fc92
Author: Dhaval Sharma <dhaval.v.sharma at intel.com>
Date:   Thu Aug 27 17:13:19 2015 +0530

    Skylake:Set DISB inside romstage after mrc init
    
    Set DISB inside romstage right after successful mrc init such that
    any reset events afterwards can take fast boot path and in turn
    achieve better boot performance
    
    BRANCH=NONE
    BUG=chrome-os-partner:43637
    TEST=Built for kunimitsu and tested DISB is set correctly and fast
    boot path is taken.
    
    Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61
    Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00
    Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295509
    Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma at intel.com>
    Original-Tested-by: dhaval v sharma <dhaval.v.sharma at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11550
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11550 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:35:55 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:35:55 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Modify DQ/DQS mapping
References: <I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb+0@gerrit.coreboot.org>
Message-ID: <E1ZZHBr-0002jy-CG@mail.coreboot.org>

the following patch was just integrated into master:
commit 736a4a2a1728ea0e28f96c1a19d6be9544b58f94
Author: Mike M Hsieh <mike.m.hsieh at intel.com>
Date:   Fri Aug 28 09:27:22 2015 +0800

    kunimitsu: Modify DQ/DQS mapping
    
    Modify DQ Byte Map and DQS Byte Swizzling to match up with design
    
    BUG=chrome-os-partner:44647
    BRANCH=none
    TEST=System boot up and pass memory initialization
    Signed-off-by: Mike Hsieh <mike.m.hsieh at intel.com>
    
    Change-Id: I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7d0a30d4b12bf4dc588d525399a8d223ff35e3de
    Original-Change-Id: I6001c853e4c5540717acf813e039c5c5dbe14c78
    Original-Reviewed-on: https://chromium-review.googlesource.com/295518
    Original-Commit-Ready: Wenkai Du <wenkai.du at intel.com>
    Original-Tested-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Reviewed-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11551
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11551 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:36:53 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:36:53 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: veyron: Unify
	identical mainboards
References: <I4bd590429b9539a91f837459a804888904cd6f2d+0@gerrit.coreboot.org>
Message-ID: <E1ZZHCn-0002tQ-CC@mail.coreboot.org>

the following patch was just integrated into master:
commit dd07ef2acd65df0f64a34545c6dd85060de4659f
Author: Julius Werner <jwerner at chromium.org>
Date:   Fri Aug 28 14:34:09 2015 -0700

    veyron: Unify identical mainboards
    
    This patch removes a lot of code duplication between the virtually
    identical Veyron Chromebook variants by merging the code into a single
    directory and handling the different names solely within Kconfig. This
    also allows us to easily add all the other Chromebook variants that have
    only been kept in Google's firmware branch to avoid cluttering coreboot
    too much, making it possible to build these boards with upstream
    coreboot out of the box.
    
    The only effective change this will have on the affected boards is
    removing quirks for early board revisions (since revision numbers differ
    between variants). Since all those quirks concerned early pre-MP
    revisions, I doubt this will bother anyone (and the old code is still
    available through the Google firmware branch if anyone needs it). It
    will also expand a recent fix in Jerry that increased an LCD power-on
    delay to make it compatible with another kind of panel to all boards,
    which is probably not a bad idea anyway.
    
    Leaving all non-Chromebook boards as they are for now since they often
    contain more extensive differences.
    
    BRANCH=None
    BUG=None
    TEST=Booted Jerry.
    
    Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9
    Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296053
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11555
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11555 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:38:42 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:38:42 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO level
References: <I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d+0@gerrit.coreboot.org>
Message-ID: <E1ZZHEY-00031k-U6@mail.coreboot.org>

the following patch was just integrated into master:
commit 17ba9445e5268d1005103966f968b5c2255f51b1
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:00:49 2015 -0700

    drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO level
    
    Having no supplied printk level makes this info message
    printed at all levels and so it shows up when booting with
    DEFAULT_CONSOLE_LOGLEVEL=3.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST="USE=quiet-cb emerge-glados coreboot"
    
    Change-Id: I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e6cffc6d5a9fcda60a04f8a31f2b2ffe4b620c77
    Original-Change-Id: Ie6715d15f950d184805149619bebe328d528e55a
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297336
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11559
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11559 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:32:36 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:32:36 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu: Fix
	incorrect comment format in devicetree.cb
References: <I7a77f0f51345f779fcae43338cdc078bc91bb51c+0@gerrit.coreboot.org>
Message-ID: <E1ZZH8e-0002Q3-EG@mail.coreboot.org>

the following patch was just integrated into master:
commit cae067f136408ff2ab4972ea677a3f04e5892912
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 31 10:01:03 2015 -0700

    kunimitsu: Fix incorrect comment format in devicetree.cb
    
    The devicetree.cb compiler can't handle C style /**/ comments,
    they need to be shell-style #.  Due to a last minute formatting
    change in my commit to enable USB ports this broke the kunimitsu
    build.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5
    Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296302
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11554
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11554 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:33:27 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:33:27 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Clean
	up devicetree.cb
References: <I0080ab21db006365f34995db06480dae68ac547d+0@gerrit.coreboot.org>
Message-ID: <E1ZZH9T-0002TY-7c@mail.coreboot.org>

the following patch was just integrated into master:
commit d96f8307865eb7b8d05dd8c010c214d223ea6b79
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:04:09 2015 -0700

    glados: Clean up devicetree.cb
    
    Clean up the PCI device list comments to be consistent between
    the skylake mainboards.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I0080ab21db006365f34995db06480dae68ac547d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d
    Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297338
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11561 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:48:13 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:48:13 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: braswell:
	Tristate CFIO 139 and CFIO 140
References: <I6d78d2ccc08167b2cd6fc3405cfcb5c69a77d4b8+0@gerrit.coreboot.org>
Message-ID: <E1ZZHNm-0004cB-3L@mail.coreboot.org>

the following patch was just integrated into master:
commit a5d98889bd5c3da0fec73dee0070338abf9b8dea
Author: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Date:   Tue Aug 11 14:06:15 2015 -0700

    braswell: Tristate CFIO 139 and CFIO 140
    
    CFIO 139 and CFIO 140 are consuming ~5 during stanndby. The reason
    for this leakage is internally it is configured to 1K PU. So there
    is leakage of ~2mW in standby. Total impact ~2.5 mw in Srandby.
    
    Configure these CFIOs as tristate for ~5mW power saving at platform
    level.
    
    BRANCH=none
    TEST=PnP Team to verify that the CFIO's are tri-stated.
    
    Change-Id: I6d78d2ccc08167b2cd6fc3405cfcb5c69a77d4b8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f11eb98cb36c504dfebe6f0fa53e9af120d21f24
    Original-Change-Id: Ib309ad0c6abffa4515fdf2a2f2d9174fad7f8e8d
    Original-Signed-off-by: Hannah Williams <hannah.williams at intel.com>
    Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/292863
    Original-Commit-Ready: Rajmohan Mani <rajmohan.mani at intel.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11556
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11556 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:48:26 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:48:26 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: igd:
	clean up igd.c
References: <I2d041f61605e0fc96483a1e825ab082668a0fa44+0@gerrit.coreboot.org>
Message-ID: <E1ZZHNz-0004dk-2K@mail.coreboot.org>

the following patch was just integrated into master:
commit 68957b33ed4f9261bd74217aa58e9e1e08ac2aea
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:07:35 2015 -0700

    skylake: igd: clean up igd.c
    
    Remove unused constants, remove unused headers, and fix the
    use of acpi_slp_type variable.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I2d041f61605e0fc96483a1e825ab082668a0fa44
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: bc57147cb7fa3c38169fcdd62cc9e35d8058414a
    Original-Change-Id: If411ad50650e6705da7de50f5be8b1d414766a8c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297741
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11564
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11564 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:50:58 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:50:58 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: rk3288: Allow
	board-specific APLL (CPU clock) settings
References: <I28b332e1d484bd009599944cd9f5cf633ea468dd+0@gerrit.coreboot.org>
Message-ID: <E1ZZHQQ-0004ts-9K@mail.coreboot.org>

the following patch was just integrated into master:
commit 4bd65e1c0cd53802abd3598c03d28b82a11be46d
Author: David Hendricks <dhendrix at chromium.org>
Date:   Wed Sep 2 18:10:14 2015 -0700

    rk3288: Allow board-specific APLL (CPU clock) settings
    
    This changes the API to rkclk_configure_cpu() such that we can pass
    in the desired APLL frequency in each veyron board's bootblock.c.
    
    Devices with a constrainted form facter (rialto and possibly mickey)
    will use this to run firmware at a slower speed to mitigate risk
    of thermal issues (due to the RK808, not the RK3288).
    
    BUG=chrome-os-partner:42054
    BRANCH=none
    TEST=amstan says rialto is noticably cooler (and slower)
    
    Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb
    Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631
    Original-Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297190
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: http://review.coreboot.org/11582
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11582 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:51:31 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:51:31 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: video: add
	video_printf
References: <I619625f7d4c5bc19cd9de64a0ba07899cf9ba289+0@gerrit.coreboot.org>
Message-ID: <E1ZZHQx-000511-Is@mail.coreboot.org>

the following patch was just integrated into master:
commit abe03d25e2890eec96df5b8e8372a9b5a1ffd1d0
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Fri Jul 31 15:22:58 2015 -0700

    video: add video_printf
    
    video_printf prints strings on the screen with specified foreground and
    background color.
    
    BUG=none
    BRANCH=smaug
    TEST=verified messages printed on Smaug
    
    Change-Id: I619625f7d4c5bc19cd9de64a0ba07899cf9ba289
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: e0ac4cb4c0d43b40f5c8f8f5a90eac45b0263b77
    Original-Reviewed-on: https://chromium-review.googlesource.com/290130
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-(cherry picked from commit 75ea2c025d629c8fabc0cb859c4e8ab8ba6ce6e3)
    Original-Change-Id: Ief6d1fc820330b54f37ad9260cf3119853460b70
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/290373
    Reviewed-on: http://review.coreboot.org/11407
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11407 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 11:52:00 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 11:52:00 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: video_printf:
	align text
References: <If1d50b7d8ddaa86eddc1618946756184cb87bfe1+0@gerrit.coreboot.org>
Message-ID: <E1ZZHRQ-00057A-Ub@mail.coreboot.org>

the following patch was just integrated into master:
commit ccda446e5204c99a98867f93113eea2a71b1c4c4
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Aug 12 18:49:50 2015 -0700

    video_printf: align text
    
    This change allows video_printf to left/center/right-align text depending on
    the enum value provided by the caller. This is useful especially because usually
    the length of formatted string is unknown before calling video_printf.
    
    BUG=none
    BRANCH=smaug
    TEST=drew fastboot screens on Smaug
    CQ-DEPEND=CL:296460
    
    Reviewed-on: https://chromium-review.googlesource.com/292929
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit 436f05f60c1b88626740a35913e3ad37b5c777a3)
    Change-Id: If1d50b7d8ddaa86eddc1618946756184cb87bfe1
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/295413
    Reviewed-on: http://review.coreboot.org/11583
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11583 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 13:57:53 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 13:57:53 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+15@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit e7948ebf624c25b8aa4b321e6ecec90ecbe24ac0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Tue Sep  8 13:58:19 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 13:58:19 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+16@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit c66dc843129bad9a7f644b86e94d4648f27d88ef
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3963339..5f9c3c1 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Tue Sep  8 13:58:44 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 13:58:44 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+17@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit f2d61c1bf0b06618e8f5a413c77300ca5124fc30
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3c1871e..0315798 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..4bb7250 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Tue Sep  8 13:59:06 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 13:59:06 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+15@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit b99e479ae66866872d15f31e60460a4b94216f07
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               |  42 +++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    | 130 ++++++++++++++++++++++++++++++++++
 src/lib/ramstage.ld                   | 115 ------------------------------
 7 files changed, 197 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 10a94c3..3c1871e 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -295,7 +295,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3963339 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,12 +127,12 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..02d017a
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+.text : {
+	SYMBOL_CURRENT_LOC(program)
+	SYMBOL_CURRENT_LOC(text)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
+	KEEP(*(.rodata.cbmem_init_hooks));
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#endif
+
+#if ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(pci_drivers)
+	KEEP(*(.rodata.pci_driver));
+	SYMBOL_CURRENT_LOC(epci_drivers)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cpu_drivers)
+	KEEP(*(.rodata.cpu_driver));
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	*(.rodata);
+	*(.rodata.*);
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(etext)
+} : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+.ctors : {
+	ALIGN_COUNTER(0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+}
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+#if ARCH_STAGE_HAS_DATA_SECTION
+.data : {
+	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(data)
+	*(.data);
+	*(.data.*);
+
+#ifdef __PRE_RAM__
+	PROVIDE(_preram_cbmem_console = .);
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bs_init_begin)
+	KEEP(*(.bs_init));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(edata)
+}
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+.bss : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bss)
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(ebss)
+}
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+.heap : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(heap)
+	. += CONFIG_HEAP_SIZE;
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(eheap)
+}
+#endif
+
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Tue Sep  8 13:59:20 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 13:59:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit 557ea1c1fa993645ba6490caa389a88573cc5564
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 5f9c3c1..d4be3f8 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,4 +139,31 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Tue Sep  8 13:59:24 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 13:59:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: provide
	minimum alignment for romstage
References: <Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15+0@gerrit.coreboot.org>
Message-ID: <Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11588

-gerrit

commit b95c817ae785e3ba6472ec06841f8b606a726d3e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Sep 7 23:05:28 2015 -0500

    x86: provide minimum alignment for romstage
    
    The current way the XIP address of romstage is calculated is by
    doing a 'cbfstool locate' using a bin file of romstage linked
    at address 0. That address is then used for re-linking romstage at
    the address spit out by cbfstool. Currently, the linker actually
    sets minimum alignment on the text sections as 32 bytes, but it
    doesn't actually honor that value. Instead, provide a minimum
    alignment for romstage so as not to fight the linker.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built asus/kfsn4-dre. Confirmed ROMSTAGE_BASE == gdtptr.
    
    Change-Id: Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index fe974ef..10a94c3 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -207,9 +207,15 @@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xi
 	sed -e '/^ROMSTAGE_BASE/d' $(objgenerated)/romstage_null.ld >> $@.tmp
 	mv $@.tmp $@
 
+# Use a '-a 64' option to cbfstool locate to provide a minimum alignment
+# requirement for the overall romstage. While the first object within
+# romstage could have a 4 byte minimum alignment that doesn't mean the linker
+# won't decide the entire section should be aligned to a larger value. In the
+# future cbfstool should add XIP files proper and honor the alignment
+# requirements of the program segment.
 $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	rm -f $@
-	$(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \
+	$(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) -a 64 > $@.tmp \
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 


From gerrit at coreboot.org  Tue Sep  8 13:59:34 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 13:59:34 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit ee5a5279e53ff9c5229ce56651be1e39cc131b04
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |   4 +-
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/program.ld                    |  15 +++--
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 14 files changed, 64 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index be6021b..4add195 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..55b4cb7 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index d4be3f8..a25e018 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index 607d7fc..7523347 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /*
@@ -84,6 +99,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 02d017a..43b1fea 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -74,13 +74,20 @@
 .data : {
 	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(data)
+
+#if ENV_RMODULE
+	SYMBOL_CURRENT_LOC(rmodule_params)
+	KEEP(*(.module_parameters));
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#endif
+
 	*(.data);
 	*(.data.*);
 
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
@@ -111,7 +118,7 @@
 .heap : {
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(heap)
-	. += CONFIG_HEAP_SIZE;
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(eheap)
 }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Tue Sep  8 13:59:48 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 13:59:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit bea9e288128f84bf895fffbec8bfa592a37f6aa0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0315798..788d7c7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -294,11 +294,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..6793ca1
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 4bb7250..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Tue Sep  8 14:00:04 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 14:00:04 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit 1be2d2f305a8c3b60c51cf927643256459c9774e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 788d7c7..3d1d214 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -298,7 +298,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Tue Sep  8 14:00:19 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 14:00:19 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit daffcb5b6e0d9c275caaab848ed6e81456759a55
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Tue Sep  8 14:00:35 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 14:00:35 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit a0e7f51fd61406475f9c798769ff5699c5082777
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/lib/Makefile.inc      |  9 ++++++---
 src/lib/program.ld        |  6 +++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3d1d214..68ed810 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -282,17 +282,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -300,8 +294,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 43b1fea..794dcf8 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -87,7 +87,7 @@
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));


From gerrit at coreboot.org  Tue Sep  8 14:00:52 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 14:00:52 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit fc51f8d7c73e62e795dd85770ec20c54395937ef
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..607d7fc 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,27 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/*
+ * Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. Also AGESA
+ * apparently builds things compeletely separate from coreboot's
+ * build infrastructure -- hardcoding its own rules.
+ */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Tue Sep  8 14:40:37 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Tue, 8 Sep 2015 14:40:37 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: crossgcc: Add
	option to build gcc for specific languages
References: <I6a74ab2c75871ea8d03a499cca33d88938b59c8d+0@gerrit.coreboot.org>
Message-ID: <I6a74ab2c75871ea8d03a499cca33d88938b59c8d+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11589

-gerrit

commit c71944add3b3881fa52416eb476182e94213862a
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Sep 8 12:30:27 2015 +0200

    crossgcc: Add option to build gcc for specific languages
    
    Add an option `--languages` which takes a list of target languages to
    buildgcc. That list gets passed through to the configure step for
    building gcc.
    
    Also alter the Makefile to pass $(BUILD_LANGUAGES) to that option, if
    this variable is set.
    
    Change-Id: I6a74ab2c75871ea8d03a499cca33d88938b59c8d
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 util/crossgcc/Makefile |  3 ++-
 util/crossgcc/buildgcc | 10 +++++++---
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile
index b1fba4a..262f4d2 100644
--- a/util/crossgcc/Makefile
+++ b/util/crossgcc/Makefile
@@ -19,7 +19,8 @@ build_tools_without_gdb: build_gcc build_iasl
 ### targets to do buildgcc builds
 
 build_gcc:
-	bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(BUILDJOBS),-j $(BUILDJOBS)) $(BUILDGCC_OPTIONS)
+	bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(BUILDJOBS),-j $(BUILDJOBS)) $(BUILDGCC_OPTIONS) \
+			$(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES))
 
 build_gdb:
 	bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(BUILDJOBS),-j $(BUILDJOBS)) $(BUILDGCC_OPTIONS)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 49e41e5..049ace4 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -29,6 +29,7 @@ CROSSGCC_VERSION="1.32"
 PACKAGE=GCC
 TARGETDIR=$(pwd)/xgcc
 TARGETARCH=i386-elf
+LANGUAGES=c
 DESTDIR=
 SAVETEMPS=0
 SKIPPYTHON=1
@@ -310,6 +311,8 @@ myhelp()
 	printf "GCC specific options:\n"
 	printf "    [-p|--platform <platform>]    target platform to build cross compiler for\n"
 	printf "                                  (defaults to $TARGETARCH)\n"
+	printf "    [-l|--languages <languages>]  comma separated list of target languages\n"
+	printf "                                  (defaults to $LANGUAGES)\n"
 	printf "GDB specific options:\n"
 	printf "    [-p|--platform <platform>]    target platform to build cross compiler for\n"
 	printf "                                  (defaults to $TARGETARCH)\n"
@@ -416,7 +419,7 @@ build_GCC() {
 		--enable-lto --enable-plugins --enable-gold --enable-ld=default \
 		--disable-libssp --disable-bootstrap --disable-nls \
 		--disable-libquadmath --without-headers \
-		${GCC_OPTIONS} --enable-languages="c" \
+		${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \
 		--with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \
 		--with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \
 		--with-pkgversion="coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE" \
@@ -508,11 +511,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c
 getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^\(......\).*,\1,')"
 if [ "${getoptbrand}" = "getopt" ]; then
 	# Detected GNU getopt that supports long options.
-	args=$(getopt -l version,help,clean,directory:,platform:,package:,jobs:,destdir:,savetemps,scripting,ccache Vhcd:p:P:j:D:tSy -- "$@")
+	args=$(getopt -l version,help,clean,directory:,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache Vhcd:p:l:P:j:D:tSy -- "$@")
 	eval set "$args"
 else
 	# Detected non-GNU getopt
-	args=$(getopt Vhcd:p:P:j:D:tSy $*)
+	args=$(getopt Vhcd:p:l:P:j:D:tSy $*)
 	set -- $args
 fi
 
@@ -529,6 +532,7 @@ while true ; do
 		-t|--savetemps)	shift; SAVETEMPS=1;;
 		-d|--directory)	shift; TARGETDIR="$1"; shift;;
 		-p|--platform)	shift; TARGETARCH="$1"; shift;;
+		-l|--languages)	shift; LANGUAGES="$1"; shift;;
 		-D|--destdir)	shift; DESTDIR="$1"; shift;;
 		-j|--jobs)	shift; JOBS="-j $1"; shift;;
 		-P|--package)   shift; PACKAGE="$1"; shift;;


From gerrit at coreboot.org  Tue Sep  8 14:40:38 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Tue, 8 Sep 2015 14:40:38 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: crossgcc:
	Preparations for building Ada frontend
References: <Ia78c29d1aba2943de5238421a324cfff8eb08875+0@gerrit.coreboot.org>
Message-ID: <Ia78c29d1aba2943de5238421a324cfff8eb08875+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11590

-gerrit

commit 9b650129703ac287d0c38568dc416cbfa64d2bdb
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Sep 8 12:38:57 2015 +0200

    crossgcc: Preparations for building Ada frontend
    
    As with most other languages, a pre-installed Ada toolchain is needed
    to build gcc's Ada frontend. To support building with older host tool-
    chains, the patch `gcc-5.2.0_gnat.patch` disables warnings for unknown
    pragmas. Building has been tested with host gcc-4.9 and hopefully works
    with newer versions, too.
    
    For convenience, the gnattools (e.g. gnatmake etc.) will be build if
    'ada' is specified as a target language.
    
    Change-Id: Ia78c29d1aba2943de5238421a324cfff8eb08875
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 util/crossgcc/buildgcc                     |  5 +++++
 util/crossgcc/patches/gcc-5.2.0_gnat.patch | 11 +++++++++++
 2 files changed, 16 insertions(+)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 049ace4..4bd89a2 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -425,6 +425,11 @@ build_GCC() {
 		--with-pkgversion="coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE" \
 		|| touch .failed
 	$MAKE $JOBS CFLAGS_FOR_BUILD="$HOSTCFLAGS" all-gcc || touch .failed
+
+	if [ "$(echo ${LANGUAGES} | grep -c '\<ada\>')" -gt 0 ]; then
+		$MAKE $JOBS CFLAGS_FOR_BUILD="$HOSTCFLAGS" -Cgcc/ cross-gnattools || touch .failed
+	fi
+
 	$MAKE install-gcc DESTDIR=$DESTDIR || touch .failed
 
 	if [ "$(echo $TARGETARCH | grep -c -- -mingw32)" -eq 0 ]; then
diff --git a/util/crossgcc/patches/gcc-5.2.0_gnat.patch b/util/crossgcc/patches/gcc-5.2.0_gnat.patch
new file mode 100644
index 0000000..1e0a5bb
--- /dev/null
+++ b/util/crossgcc/patches/gcc-5.2.0_gnat.patch
@@ -0,0 +1,11 @@
+--- gcc-5.2.0/gcc/ada/gcc-interface/Make-lang.in.bak	2015-08-24 16:23:25.004493665 +0200
++++ gcc-5.2.0/gcc/ada/gcc-interface/Make-lang.in	2015-08-24 17:53:52.496636113 +0200
+@@ -45,7 +45,7 @@
+ 

+ 
+ # Extra flags to pass to recursive makes.
+-COMMON_ADAFLAGS= -gnatpg
++COMMON_ADAFLAGS= -gnatpg -gnatwG
+ ifeq ($(TREECHECKING),)
+ CHECKING_ADAFLAGS=
+ else


From gerrit at coreboot.org  Tue Sep  8 15:28:37 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Tue, 8 Sep 2015 15:28:37 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Partially
	revert "lib: Unify log2() and related functions"
References: <I4e3fc15816b778e640bceea0d89cd9624d271c2e+0@gerrit.coreboot.org>
Message-ID: <I4e3fc15816b778e640bceea0d89cd9624d271c2e+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11591

-gerrit

commit 029e3c431c520ec6a51c9141802e905457bcb3f7
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Sep 8 17:14:08 2015 +0200

    Partially revert "lib: Unify log2() and related functions"
    
    This partially reverts
    
    commit 7a8a4ab1d88a411ee0dad23318f98b4f29fd2f60
    Author: Julius Werner <jwerner at chromium.org>
    Date:   Fri May 22 16:26:40 2015 -0700
    
        lib: Unify log2() and related functions
    
    as it silently dropped ffs() from libpayload (for whatever reason),
    breaking an interface that had been stable for over four years.
    
    Change-Id: I4e3fc15816b778e640bceea0d89cd9624d271c2e
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 payloads/libpayload/include/strings.h | 35 +++++++++++++++++++++++++++++
 payloads/libpayload/libc/Makefile.inc |  2 +-
 payloads/libpayload/libc/strings.c    | 42 +++++++++++++++++++++++++++++++++++
 3 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/include/strings.h b/payloads/libpayload/include/strings.h
new file mode 100644
index 0000000..5beddc6
--- /dev/null
+++ b/payloads/libpayload/include/strings.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _STRINGS_H
+#define _STRINGS_H
+
+int ffs(int i);
+
+#endif
diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc
index edef62c..2cf7445 100644
--- a/payloads/libpayload/libc/Makefile.inc
+++ b/payloads/libpayload/libc/Makefile.inc
@@ -32,7 +32,7 @@ libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c
 libc-$(CONFIG_LP_LIBC) += memory.c ctype.c ipchecksum.c lib.c libgcc.c
 libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c
 libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c
-libc-$(CONFIG_LP_LIBC) += args.c
+libc-$(CONFIG_LP_LIBC) += args.c strings.c
 libc-$(CONFIG_LP_LIBC) += strlcpy.c
 libc-$(CONFIG_LP_LIBC) += qsort.c
 libc-$(CONFIG_LP_LIBC) += hexdump.c
diff --git a/payloads/libpayload/libc/strings.c b/payloads/libpayload/libc/strings.c
new file mode 100644
index 0000000..465ae4f
--- /dev/null
+++ b/payloads/libpayload/libc/strings.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <strings.h>
+
+int ffs(int i)
+{
+	int count = 1;
+	if (i == 0) return 0;
+
+	while ((i & 1) != 1) {
+		i>>=1;
+		count++;
+	}
+	return count;
+}


From gerrit at coreboot.org  Tue Sep  8 18:41:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 18:41:41 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: RFC: Introduce
	commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 7229507ce598d4498ac0ca1a47e04046a856c8a8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    RFC: Introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                             |   4 +-
 src/commonlib/Makefile.inc               |  10 ++
 src/commonlib/include/cbmem_id.h         | 113 ++++++++++++++++++
 src/commonlib/include/console/loglevel.h | 178 ++++++++++++++++++++++++++++
 src/commonlib/include/helpers.h          |  40 +++++++
 src/commonlib/include/mem_pool.h         |  73 ++++++++++++
 src/commonlib/include/region.h           | 157 +++++++++++++++++++++++++
 src/commonlib/mem_pool.c                 |  51 ++++++++
 src/commonlib/ramstage.a                 | Bin 0 -> 516 bytes
 src/commonlib/region.c                   | 196 +++++++++++++++++++++++++++++++
 src/include/cbmem_id.h                   | 113 ------------------
 src/include/console/loglevel.h           | 178 ----------------------------
 src/include/mem_pool.h                   |  73 ------------
 src/include/region.h                     | 157 -------------------------
 src/include/stddef.h                     |  34 +-----
 src/lib/Makefile.inc                     |   9 --
 src/lib/mem_pool.c                       |  51 --------
 src/lib/region.c                         | 196 -------------------------------
 util/cbmem/Makefile                      |   2 +-
 util/cbmem/cbmem.c                       |   2 +-
 20 files changed, 824 insertions(+), 813 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 4add195..250fe91 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/cbmem_id.h b/src/commonlib/include/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/console/loglevel.h b/src/commonlib/include/console/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/console/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/helpers.h b/src/commonlib/include/helpers.h
new file mode 100644
index 0000000..d6caca6
--- /dev/null
+++ b/src/commonlib/include/helpers.h
@@ -0,0 +1,40 @@
+
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/mem_pool.h b/src/commonlib/include/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/region.h b/src/commonlib/include/region.h
new file mode 100644
index 0000000..82db854
--- /dev/null
+++ b/src/commonlib/include/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..4bd0668
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/ramstage.a b/src/commonlib/ramstage.a
new file mode 100644
index 0000000..f42b83f
Binary files /dev/null and b/src/commonlib/ramstage.a differ
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..d5d3762
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..035a53c 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..1d8ad6d 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86 -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..33d6493 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -51,7 +51,7 @@ typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
+#include <cbmem_id.h>
 #include "timestamp.h"
 
 #define CBMEM_VERSION "1.1"


From gerrit at coreboot.org  Tue Sep  8 20:05:03 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 20:05:03 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: RFC: Introduce
	commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 66c2ac3ee3d690ba16159f685a03d275f117f55e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    RFC: Introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                             |   4 +-
 src/commonlib/Makefile.inc               |  10 ++
 src/commonlib/include/cbmem_id.h         | 113 ++++++++++++++++++
 src/commonlib/include/console/loglevel.h | 178 ++++++++++++++++++++++++++++
 src/commonlib/include/helpers.h          |  40 +++++++
 src/commonlib/include/mem_pool.h         |  73 ++++++++++++
 src/commonlib/include/region.h           | 157 +++++++++++++++++++++++++
 src/commonlib/include/rmodule-defs.h     |  63 ++++++++++
 src/commonlib/mem_pool.c                 |  51 ++++++++
 src/commonlib/region.c                   | 196 +++++++++++++++++++++++++++++++
 src/include/cbmem_id.h                   | 113 ------------------
 src/include/console/loglevel.h           | 178 ----------------------------
 src/include/mem_pool.h                   |  73 ------------
 src/include/region.h                     | 157 -------------------------
 src/include/rmodule-defs.h               |  63 ----------
 src/include/stddef.h                     |  34 +-----
 src/lib/Makefile.inc                     |   9 --
 src/lib/mem_pool.c                       |  51 --------
 src/lib/region.c                         | 196 -------------------------------
 util/cbfstool/Makefile                   |   1 +
 util/cbfstool/rmodule.c                  |   2 +-
 util/cbmem/Makefile                      |   2 +-
 util/cbmem/cbmem.c                       |   2 +-
 23 files changed, 889 insertions(+), 877 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 4add195..250fe91 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/cbmem_id.h b/src/commonlib/include/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/console/loglevel.h b/src/commonlib/include/console/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/console/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/helpers.h b/src/commonlib/include/helpers.h
new file mode 100644
index 0000000..d6caca6
--- /dev/null
+++ b/src/commonlib/include/helpers.h
@@ -0,0 +1,40 @@
+
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/mem_pool.h b/src/commonlib/include/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/region.h b/src/commonlib/include/region.h
new file mode 100644
index 0000000..82db854
--- /dev/null
+++ b/src/commonlib/include/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/rmodule-defs.h b/src/commonlib/include/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..4bd0668
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..d5d3762
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..035a53c 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 1f41d17..5b193d9 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <rmodule-defs.h>
 
 struct rmod_context;
 
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..1d8ad6d 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86 -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..33d6493 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -51,7 +51,7 @@ typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
+#include <cbmem_id.h>
 #include "timestamp.h"
 
 #define CBMEM_VERSION "1.1"


From gerrit at coreboot.org  Tue Sep  8 21:05:14 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 21:05:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: RFC: Introduce
	commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 42091dd2b9156445557bf5badafc6115a8113928
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    RFC: Introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                             |   4 +-
 src/commonlib/Makefile.inc               |  10 ++
 src/commonlib/include/cbmem_id.h         | 113 ++++++++++++++++++
 src/commonlib/include/console/loglevel.h | 178 ++++++++++++++++++++++++++++
 src/commonlib/include/helpers.h          |  40 +++++++
 src/commonlib/include/mem_pool.h         |  73 ++++++++++++
 src/commonlib/include/region.h           | 157 +++++++++++++++++++++++++
 src/commonlib/include/rmodule-defs.h     |  63 ++++++++++
 src/commonlib/mem_pool.c                 |  51 ++++++++
 src/commonlib/region.c                   | 196 +++++++++++++++++++++++++++++++
 src/include/cbmem_id.h                   | 113 ------------------
 src/include/console/loglevel.h           | 178 ----------------------------
 src/include/mem_pool.h                   |  73 ------------
 src/include/region.h                     | 157 -------------------------
 src/include/rmodule-defs.h               |  63 ----------
 src/include/stddef.h                     |  34 +-----
 src/lib/Makefile.inc                     |   9 --
 src/lib/mem_pool.c                       |  51 --------
 src/lib/region.c                         | 196 -------------------------------
 util/cbfstool/Makefile                   |   1 +
 util/cbfstool/Makefile.inc               |   1 +
 util/cbfstool/rmodule.c                  |   2 +-
 util/cbmem/Makefile                      |   2 +-
 util/cbmem/cbmem.c                       |   2 +-
 24 files changed, 890 insertions(+), 877 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 4add195..250fe91 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/cbmem_id.h b/src/commonlib/include/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/console/loglevel.h b/src/commonlib/include/console/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/console/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/helpers.h b/src/commonlib/include/helpers.h
new file mode 100644
index 0000000..d6caca6
--- /dev/null
+++ b/src/commonlib/include/helpers.h
@@ -0,0 +1,40 @@
+
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/mem_pool.h b/src/commonlib/include/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/region.h b/src/commonlib/include/region.h
new file mode 100644
index 0000000..82db854
--- /dev/null
+++ b/src/commonlib/include/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/rmodule-defs.h b/src/commonlib/include/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..4bd0668
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..d5d3762
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..035a53c 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 1f41d17..5b193d9 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <rmodule-defs.h>
 
 struct rmod_context;
 
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..1d8ad6d 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86 -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..33d6493 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -51,7 +51,7 @@ typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
+#include <cbmem_id.h>
 #include "timestamp.h"
 
 #define CBMEM_VERSION "1.1"


From gerrit at coreboot.org  Tue Sep  8 21:05:15 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 21:05:15 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	prepare for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <I176d0ae0ae1933cdf6adac67d393ba676198861a+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11595

-gerrit

commit 132005e279b60dacde6b8ffbf9657c2aa7adb4bd
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 70 +++++++++++++++++++++++++++----------------------
 1 file changed, 38 insertions(+), 32 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 5b193d9..5c3927d 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,14 +50,11 @@ struct rmod_context {
 	Elf64_Xword nrelocs;
 	Elf64_Addr *emitted_relocs;
 
-	/* The following fields are addresses within the linked program. */
-	Elf64_Addr link_addr;
-	Elf64_Addr entry;
+	/* The following fields are addresses within the linked program.  */
 	Elf64_Addr parameters_begin;
 	Elf64_Addr parameters_end;
 	Elf64_Addr bss_begin;
 	Elf64_Addr bss_end;
-	Elf64_Xword size;
 };
 
 /*
@@ -371,7 +368,7 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 	return -1;
 }
 
-static int populate_program_info(struct rmod_context *ctx)
+static int populate_rmodule_info(struct rmod_context *ctx)
 {
 	int i;
 	const char *strtab;
@@ -423,15 +420,6 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
-	/* Honor the entry point within the ELF header. */
-	ctx->entry = ehdr->e_entry;
-
-	/* Link address is the virtual address of the program segment. */
-	ctx->link_addr = ctx->phdr->p_vaddr;
-
-	/* The program size is the memsz of the program segment. */
-	ctx->size = ctx->phdr->p_memsz;
-
 	return 0;
 }
 
@@ -516,7 +504,6 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 
 	/* Create ELF writer with modified entry point. */
 	memcpy(&ehdr, &ctx->pelf.ehdr, sizeof(ehdr));
-	ehdr.e_entry = ctx->entry;
 	ew = elf_writer_init(&ehdr);
 
 	if (ew == NULL) {
@@ -543,12 +530,13 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 	else
 		loc += ctx->nrelocs * sizeof(Elf32_Addr);
 	ctx->xdr->put32(&rmod_header, loc);
+
 	/* module_link_start_address */
-	ctx->xdr->put32(&rmod_header, ctx->link_addr);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_vaddr);
 	/* module_program_size */
-	ctx->xdr->put32(&rmod_header, ctx->size);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_memsz);
 	/* module_entry_point */
-	ctx->xdr->put32(&rmod_header, ctx->entry);
+	ctx->xdr->put32(&rmod_header, ctx->pelf.ehdr.e_entry);
 	/* parameters_begin */
 	ctx->xdr->put32(&rmod_header, ctx->parameters_begin);
 	/* parameters_end */
@@ -631,16 +619,15 @@ out:
 	return ret;
 }
 
-int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
-	struct rmod_context ctx;
 	struct parsed_elf *pelf;
 	int i;
 	int ret;
 
 	ret = -1;
-	memset(&ctx, 0, sizeof(ctx));
-	pelf = &ctx.pelf;
+	memset(ctx, 0, sizeof(*ctx));
+	pelf = &ctx->pelf;
 
 	if (parse_elf(elfin, pelf, ELF_PARSE_ALL)) {
 		ERROR("Couldn't parse ELF!\n");
@@ -656,32 +643,52 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	/* Determine if architecture is supported. */
 	for (i = 0; i < ARRAY_SIZE(reloc_ops); i++) {
 		if (reloc_ops[i].arch == pelf->ehdr.e_machine) {
-			ctx.ops = &reloc_ops[i];
+			ctx->ops = &reloc_ops[i];
 			break;
 		}
 	}
 
-	if (ctx.ops == NULL) {
+	if (ctx->ops == NULL) {
 		ERROR("ELF is unsupported arch: %u.\n", pelf->ehdr.e_machine);
 		goto out;
 	}
 
 	/* Set the endian ops. */
-	if (ctx.pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
-		ctx.xdr = &xdr_be;
+	if (ctx->pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
+		ctx->xdr = &xdr_be;
 	else
-		ctx.xdr = &xdr_le;
+		ctx->xdr = &xdr_le;
+
+	if (find_program_segment(ctx))
+		goto out;
 
-	if (find_program_segment(&ctx))
+	if (filter_relocation_sections(ctx))
 		goto out;
 
-	if (filter_relocation_sections(&ctx))
+	ret = 0;
+
+out:
+	return ret;
+}
+
+static void rmodule_cleanup(struct rmod_context *ctx)
+{
+	free(ctx->emitted_relocs);
+	parsed_elf_destroy(&ctx->pelf);
+}
+
+int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+{
+	struct rmod_context ctx;
+	int ret = -1;
+
+	if (rmodule_init(&ctx, elfin))
 		goto out;
 
 	if (collect_relocations(&ctx))
 		goto out;
 
-	if (populate_program_info(&ctx))
+	if (populate_rmodule_info(&ctx))
 		goto out;
 
 	if (write_elf(&ctx, elfin, elfout))
@@ -690,7 +697,6 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	ret = 0;
 
 out:
-	free(ctx.emitted_relocs);
-	parsed_elf_destroy(pelf);
+	rmodule_cleanup(&ctx);
 	return ret;
 }


From gerrit at coreboot.org  Tue Sep  8 21:06:12 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 21:06:12 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prepare
	for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <I176d0ae0ae1933cdf6adac67d393ba676198861a+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11595

-gerrit

commit 6a48a83152e6376c21f47a8ce21cdde3ad8df7d7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 69 ++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 5b193d9..bfa3426 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,14 +50,11 @@ struct rmod_context {
 	Elf64_Xword nrelocs;
 	Elf64_Addr *emitted_relocs;
 
-	/* The following fields are addresses within the linked program. */
-	Elf64_Addr link_addr;
-	Elf64_Addr entry;
+	/* The following fields are addresses within the linked program.  */
 	Elf64_Addr parameters_begin;
 	Elf64_Addr parameters_end;
 	Elf64_Addr bss_begin;
 	Elf64_Addr bss_end;
-	Elf64_Xword size;
 };
 
 /*
@@ -371,7 +368,7 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 	return -1;
 }
 
-static int populate_program_info(struct rmod_context *ctx)
+static int populate_rmodule_info(struct rmod_context *ctx)
 {
 	int i;
 	const char *strtab;
@@ -423,15 +420,6 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
-	/* Honor the entry point within the ELF header. */
-	ctx->entry = ehdr->e_entry;
-
-	/* Link address is the virtual address of the program segment. */
-	ctx->link_addr = ctx->phdr->p_vaddr;
-
-	/* The program size is the memsz of the program segment. */
-	ctx->size = ctx->phdr->p_memsz;
-
 	return 0;
 }
 
@@ -516,7 +504,6 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 
 	/* Create ELF writer with modified entry point. */
 	memcpy(&ehdr, &ctx->pelf.ehdr, sizeof(ehdr));
-	ehdr.e_entry = ctx->entry;
 	ew = elf_writer_init(&ehdr);
 
 	if (ew == NULL) {
@@ -544,11 +531,11 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 		loc += ctx->nrelocs * sizeof(Elf32_Addr);
 	ctx->xdr->put32(&rmod_header, loc);
 	/* module_link_start_address */
-	ctx->xdr->put32(&rmod_header, ctx->link_addr);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_vaddr);
 	/* module_program_size */
-	ctx->xdr->put32(&rmod_header, ctx->size);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_memsz);
 	/* module_entry_point */
-	ctx->xdr->put32(&rmod_header, ctx->entry);
+	ctx->xdr->put32(&rmod_header, ctx->pelf.ehdr.e_entry);
 	/* parameters_begin */
 	ctx->xdr->put32(&rmod_header, ctx->parameters_begin);
 	/* parameters_end */
@@ -631,16 +618,15 @@ out:
 	return ret;
 }
 
-int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
-	struct rmod_context ctx;
 	struct parsed_elf *pelf;
 	int i;
 	int ret;
 
 	ret = -1;
-	memset(&ctx, 0, sizeof(ctx));
-	pelf = &ctx.pelf;
+	memset(ctx, 0, sizeof(*ctx));
+	pelf = &ctx->pelf;
 
 	if (parse_elf(elfin, pelf, ELF_PARSE_ALL)) {
 		ERROR("Couldn't parse ELF!\n");
@@ -656,32 +642,52 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	/* Determine if architecture is supported. */
 	for (i = 0; i < ARRAY_SIZE(reloc_ops); i++) {
 		if (reloc_ops[i].arch == pelf->ehdr.e_machine) {
-			ctx.ops = &reloc_ops[i];
+			ctx->ops = &reloc_ops[i];
 			break;
 		}
 	}
 
-	if (ctx.ops == NULL) {
+	if (ctx->ops == NULL) {
 		ERROR("ELF is unsupported arch: %u.\n", pelf->ehdr.e_machine);
 		goto out;
 	}
 
 	/* Set the endian ops. */
-	if (ctx.pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
-		ctx.xdr = &xdr_be;
+	if (ctx->pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
+		ctx->xdr = &xdr_be;
 	else
-		ctx.xdr = &xdr_le;
+		ctx->xdr = &xdr_le;
 
-	if (find_program_segment(&ctx))
+	if (find_program_segment(ctx))
 		goto out;
 
-	if (filter_relocation_sections(&ctx))
+	if (filter_relocation_sections(ctx))
+		goto out;
+
+	ret = 0;
+
+out:
+	return ret;
+}
+
+static void rmodule_cleanup(struct rmod_context *ctx)
+{
+	free(ctx->emitted_relocs);
+	parsed_elf_destroy(&ctx->pelf);
+}
+
+int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+{
+	struct rmod_context ctx;
+	int ret = -1;
+
+	if (rmodule_init(&ctx, elfin))
 		goto out;
 
 	if (collect_relocations(&ctx))
 		goto out;
 
-	if (populate_program_info(&ctx))
+	if (populate_rmodule_info(&ctx))
 		goto out;
 
 	if (write_elf(&ctx, elfin, elfout))
@@ -690,7 +696,6 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	ret = 0;
 
 out:
-	free(ctx.emitted_relocs);
-	parsed_elf_destroy(pelf);
+	rmodule_cleanup(&ctx);
 	return ret;
 }


From gerrit at coreboot.org  Tue Sep  8 21:12:37 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Tue, 8 Sep 2015 21:12:37 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload:
	Revive ffs()
References: <I4e3fc15816b778e640bceea0d89cd9624d271c2e+0@gerrit.coreboot.org>
Message-ID: <I4e3fc15816b778e640bceea0d89cd9624d271c2e+2@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11591

-gerrit

commit 0e22d8d93327377b3621daab85f95fe27e1b13c7
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Sep 8 17:14:08 2015 +0200

    libpayload: Revive ffs()
    
    Revive ffs() in a more fancy way (that is more likely to be accepted).
    We dropped it in
      7a8a4ab lib: Unify log2() and related functions
    but there is at least one user: flashrom.
    
    Change-Id: I4e3fc15816b778e640bceea0d89cd9624d271c2e
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 payloads/libpayload/include/strings.h | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/payloads/libpayload/include/strings.h b/payloads/libpayload/include/strings.h
new file mode 100644
index 0000000..bde95f3
--- /dev/null
+++ b/payloads/libpayload/include/strings.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _STRINGS_H
+#define _STRINGS_H
+
+static inline int ffs(int i) { return __builtin_ffs(i); }
+
+#endif


From gerrit at coreboot.org  Tue Sep  8 21:33:07 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 21:33:07 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cpu: fix
	cpu_microcode class
References: <Icb47d509832e7433092a814bad020f8d66f2a299+0@gerrit.coreboot.org>
Message-ID: <Icb47d509832e7433092a814bad020f8d66f2a299+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11596

-gerrit

commit 8685eab15751b6701559c45697dc4a41f0dff1d8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 16:30:05 2015 -0500

    cpu: fix cpu_microcode class
    
    The cpu_micrcode was never being added as a class proper.
    Also, there's no reason defining another class compiler
    which overrides the first one. The microcode files are just
    built into a binary and added to cbfs. There's no reason to
    change compilers.
    
    Change-Id: Icb47d509832e7433092a814bad020f8d66f2a299
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index d757c79..c203c72 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -12,8 +12,8 @@ subdirs-y += via
 subdirs-y += x86
 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
 
+$(call add-class,cpu_microcode)
 $(eval $(call create_class_compiler,cpu_microcode,x86_32))
-$(eval $(call create_class_compiler,cpu_microcode,x86_64))
 ################################################################################
 ## Rules for building the microcode blob in CBFS
 ################################################################################


From gerrit at coreboot.org  Tue Sep  8 21:37:31 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 21:37:31 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: fix
	cpu_microcode class
References: <Icb47d509832e7433092a814bad020f8d66f2a299+0@gerrit.coreboot.org>
Message-ID: <Icb47d509832e7433092a814bad020f8d66f2a299+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11596

-gerrit

commit a4195ba08ef54c61dffa6d4b10d84f83aa331eaf
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 16:30:05 2015 -0500

    cpu: fix cpu_microcode class
    
    There's no reason defining another class compiler which
    overrides the first one. The microcode files are just
    built into a binary and added to cbfs. There's no reason to
    change compilers.
    
    Change-Id: Icb47d509832e7433092a814bad020f8d66f2a299
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/Makefile.inc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index d757c79..3ea42e5 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -13,7 +13,6 @@ subdirs-y += x86
 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
 
 $(eval $(call create_class_compiler,cpu_microcode,x86_32))
-$(eval $(call create_class_compiler,cpu_microcode,x86_64))
 ################################################################################
 ## Rules for building the microcode blob in CBFS
 ################################################################################


From gerrit at coreboot.org  Tue Sep  8 21:42:34 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 21:42:34 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: RFC: Introduce
	commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 781fe382d5499de37a6f5aa3d870e2a7b244919e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    RFC: Introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                             |   4 +-
 src/commonlib/Makefile.inc               |  10 ++
 src/commonlib/include/cbmem_id.h         | 113 ++++++++++++++++++
 src/commonlib/include/console/loglevel.h | 178 ++++++++++++++++++++++++++++
 src/commonlib/include/helpers.h          |  40 +++++++
 src/commonlib/include/mem_pool.h         |  73 ++++++++++++
 src/commonlib/include/region.h           | 157 +++++++++++++++++++++++++
 src/commonlib/include/rmodule-defs.h     |  63 ++++++++++
 src/commonlib/mem_pool.c                 |  51 ++++++++
 src/commonlib/region.c                   | 196 +++++++++++++++++++++++++++++++
 src/include/cbmem_id.h                   | 113 ------------------
 src/include/console/loglevel.h           | 178 ----------------------------
 src/include/mem_pool.h                   |  73 ------------
 src/include/region.h                     | 157 -------------------------
 src/include/rmodule-defs.h               |  63 ----------
 src/include/stddef.h                     |  34 +-----
 src/lib/Makefile.inc                     |   9 --
 src/lib/mem_pool.c                       |  51 --------
 src/lib/region.c                         | 196 -------------------------------
 src/vendorcode/amd/pi/Makefile.inc       |   1 +
 util/cbfstool/Makefile                   |   1 +
 util/cbfstool/Makefile.inc               |   1 +
 util/cbfstool/rmodule.c                  |   2 +-
 util/cbmem/Makefile                      |   2 +-
 util/cbmem/cbmem.c                       |   2 +-
 25 files changed, 891 insertions(+), 877 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 4add195..250fe91 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/cbmem_id.h b/src/commonlib/include/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/console/loglevel.h b/src/commonlib/include/console/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/console/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/helpers.h b/src/commonlib/include/helpers.h
new file mode 100644
index 0000000..d6caca6
--- /dev/null
+++ b/src/commonlib/include/helpers.h
@@ -0,0 +1,40 @@
+
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/mem_pool.h b/src/commonlib/include/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/region.h b/src/commonlib/include/region.h
new file mode 100644
index 0000000..82db854
--- /dev/null
+++ b/src/commonlib/include/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/rmodule-defs.h b/src/commonlib/include/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..4bd0668
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..d5d3762
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..035a53c 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 1f41d17..5b193d9 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <rmodule-defs.h>
 
 struct rmod_context;
 
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..1d8ad6d 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86 -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..33d6493 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -51,7 +51,7 @@ typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
+#include <cbmem_id.h>
 #include "timestamp.h"
 
 #define CBMEM_VERSION "1.1"


From gerrit at coreboot.org  Tue Sep  8 21:42:36 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 21:42:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prepare
	for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <I176d0ae0ae1933cdf6adac67d393ba676198861a+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11595

-gerrit

commit fd79a0be5a23ba618a2a0eaff37fd8abc907201a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 69 ++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 5b193d9..bfa3426 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,14 +50,11 @@ struct rmod_context {
 	Elf64_Xword nrelocs;
 	Elf64_Addr *emitted_relocs;
 
-	/* The following fields are addresses within the linked program. */
-	Elf64_Addr link_addr;
-	Elf64_Addr entry;
+	/* The following fields are addresses within the linked program.  */
 	Elf64_Addr parameters_begin;
 	Elf64_Addr parameters_end;
 	Elf64_Addr bss_begin;
 	Elf64_Addr bss_end;
-	Elf64_Xword size;
 };
 
 /*
@@ -371,7 +368,7 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 	return -1;
 }
 
-static int populate_program_info(struct rmod_context *ctx)
+static int populate_rmodule_info(struct rmod_context *ctx)
 {
 	int i;
 	const char *strtab;
@@ -423,15 +420,6 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
-	/* Honor the entry point within the ELF header. */
-	ctx->entry = ehdr->e_entry;
-
-	/* Link address is the virtual address of the program segment. */
-	ctx->link_addr = ctx->phdr->p_vaddr;
-
-	/* The program size is the memsz of the program segment. */
-	ctx->size = ctx->phdr->p_memsz;
-
 	return 0;
 }
 
@@ -516,7 +504,6 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 
 	/* Create ELF writer with modified entry point. */
 	memcpy(&ehdr, &ctx->pelf.ehdr, sizeof(ehdr));
-	ehdr.e_entry = ctx->entry;
 	ew = elf_writer_init(&ehdr);
 
 	if (ew == NULL) {
@@ -544,11 +531,11 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 		loc += ctx->nrelocs * sizeof(Elf32_Addr);
 	ctx->xdr->put32(&rmod_header, loc);
 	/* module_link_start_address */
-	ctx->xdr->put32(&rmod_header, ctx->link_addr);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_vaddr);
 	/* module_program_size */
-	ctx->xdr->put32(&rmod_header, ctx->size);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_memsz);
 	/* module_entry_point */
-	ctx->xdr->put32(&rmod_header, ctx->entry);
+	ctx->xdr->put32(&rmod_header, ctx->pelf.ehdr.e_entry);
 	/* parameters_begin */
 	ctx->xdr->put32(&rmod_header, ctx->parameters_begin);
 	/* parameters_end */
@@ -631,16 +618,15 @@ out:
 	return ret;
 }
 
-int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
-	struct rmod_context ctx;
 	struct parsed_elf *pelf;
 	int i;
 	int ret;
 
 	ret = -1;
-	memset(&ctx, 0, sizeof(ctx));
-	pelf = &ctx.pelf;
+	memset(ctx, 0, sizeof(*ctx));
+	pelf = &ctx->pelf;
 
 	if (parse_elf(elfin, pelf, ELF_PARSE_ALL)) {
 		ERROR("Couldn't parse ELF!\n");
@@ -656,32 +642,52 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	/* Determine if architecture is supported. */
 	for (i = 0; i < ARRAY_SIZE(reloc_ops); i++) {
 		if (reloc_ops[i].arch == pelf->ehdr.e_machine) {
-			ctx.ops = &reloc_ops[i];
+			ctx->ops = &reloc_ops[i];
 			break;
 		}
 	}
 
-	if (ctx.ops == NULL) {
+	if (ctx->ops == NULL) {
 		ERROR("ELF is unsupported arch: %u.\n", pelf->ehdr.e_machine);
 		goto out;
 	}
 
 	/* Set the endian ops. */
-	if (ctx.pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
-		ctx.xdr = &xdr_be;
+	if (ctx->pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
+		ctx->xdr = &xdr_be;
 	else
-		ctx.xdr = &xdr_le;
+		ctx->xdr = &xdr_le;
 
-	if (find_program_segment(&ctx))
+	if (find_program_segment(ctx))
 		goto out;
 
-	if (filter_relocation_sections(&ctx))
+	if (filter_relocation_sections(ctx))
+		goto out;
+
+	ret = 0;
+
+out:
+	return ret;
+}
+
+static void rmodule_cleanup(struct rmod_context *ctx)
+{
+	free(ctx->emitted_relocs);
+	parsed_elf_destroy(&ctx->pelf);
+}
+
+int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+{
+	struct rmod_context ctx;
+	int ret = -1;
+
+	if (rmodule_init(&ctx, elfin))
 		goto out;
 
 	if (collect_relocations(&ctx))
 		goto out;
 
-	if (populate_program_info(&ctx))
+	if (populate_rmodule_info(&ctx))
 		goto out;
 
 	if (write_elf(&ctx, elfin, elfout))
@@ -690,7 +696,6 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	ret = 0;
 
 out:
-	free(ctx.emitted_relocs);
-	parsed_elf_destroy(pelf);
+	rmodule_cleanup(&ctx);
 	return ret;
 }


From gerrit at coreboot.org  Tue Sep  8 22:23:59 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 8 Sep 2015 22:23:59 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cpu: fix
	cpu_microcode class
References: <Icb47d509832e7433092a814bad020f8d66f2a299+0@gerrit.coreboot.org>
Message-ID: <E1ZZRJ1-00040l-Tr@mail.coreboot.org>

the following patch was just integrated into master:
commit 6c950da54ce2dff7b2874d774147572b95ae82f6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 16:30:05 2015 -0500

    cpu: fix cpu_microcode class
    
    There's no reason defining another class compiler which
    overrides the first one. The microcode files are just
    built into a binary and added to cbfs. There's no reason to
    change compilers.
    
    Change-Id: Icb47d509832e7433092a814bad020f8d66f2a299
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11596
    Reviewed-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11596 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep  8 22:31:56 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:31:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+16@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit a1e11154378d01ba9824d4ca9557b928ff40a21f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Tue Sep  8 22:32:23 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:32:23 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+17@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit c085c9607359e6ee781c3325cf9b234c4b31930b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3963339..5f9c3c1 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Tue Sep  8 22:32:50 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:32:50 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+18@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit ef98e45c61f9a1a12aac96f9f3a41a0e3d83a6c5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++--
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h | 13 ++++++++-
 src/arch/x86/romstage.ld              | 50 +++++++++--------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 6 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3c1871e..0315798 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..abaa8c7 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,17 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* Ensure the binding for .rom sections comes prior to all other text. */
+#define ARCH_FIRST_TEXT \
+	*(.rom.text); \
+	*(.rom.data);
+
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..4bb7250 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
-		_car_data_start = .;
+		SYMBOL_CURRENT_LOC(car_data_start)
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
-		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)


From gerrit at coreboot.org  Tue Sep  8 22:32:58 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:32:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: RFC: Introduce
	commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 74ae166274a21cffcde57d7d9b40cb05a86eb1a8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    RFC: Introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                             |   4 +-
 src/commonlib/Makefile.inc               |  10 ++
 src/commonlib/include/cbmem_id.h         | 113 ++++++++++++++++++
 src/commonlib/include/console/loglevel.h | 178 ++++++++++++++++++++++++++++
 src/commonlib/include/helpers.h          |  40 +++++++
 src/commonlib/include/mem_pool.h         |  73 ++++++++++++
 src/commonlib/include/region.h           | 157 +++++++++++++++++++++++++
 src/commonlib/include/rmodule-defs.h     |  63 ++++++++++
 src/commonlib/mem_pool.c                 |  51 ++++++++
 src/commonlib/region.c                   | 196 +++++++++++++++++++++++++++++++
 src/include/cbmem_id.h                   | 113 ------------------
 src/include/console/loglevel.h           | 178 ----------------------------
 src/include/mem_pool.h                   |  73 ------------
 src/include/region.h                     | 157 -------------------------
 src/include/rmodule-defs.h               |  63 ----------
 src/include/stddef.h                     |  34 +-----
 src/lib/Makefile.inc                     |   9 --
 src/lib/mem_pool.c                       |  51 --------
 src/lib/region.c                         | 196 -------------------------------
 src/vendorcode/amd/pi/Makefile.inc       |   1 +
 util/cbfstool/Makefile                   |   1 +
 util/cbfstool/Makefile.inc               |   1 +
 util/cbfstool/rmodule.c                  |   2 +-
 util/cbmem/Makefile                      |   2 +-
 util/cbmem/cbmem.c                       |   2 +-
 25 files changed, 891 insertions(+), 877 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 4add195..250fe91 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/cbmem_id.h b/src/commonlib/include/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/console/loglevel.h b/src/commonlib/include/console/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/console/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/helpers.h b/src/commonlib/include/helpers.h
new file mode 100644
index 0000000..d6caca6
--- /dev/null
+++ b/src/commonlib/include/helpers.h
@@ -0,0 +1,40 @@
+
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/mem_pool.h b/src/commonlib/include/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/region.h b/src/commonlib/include/region.h
new file mode 100644
index 0000000..82db854
--- /dev/null
+++ b/src/commonlib/include/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/rmodule-defs.h b/src/commonlib/include/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..4bd0668
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..d5d3762
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..035a53c 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 1f41d17..5b193d9 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <rmodule-defs.h>
 
 struct rmod_context;
 
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..1d8ad6d 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86 -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..33d6493 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -51,7 +51,7 @@ typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
+#include <cbmem_id.h>
 #include "timestamp.h"
 
 #define CBMEM_VERSION "1.1"


From gerrit at coreboot.org  Tue Sep  8 22:33:02 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:33:02 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: add
	romstage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504

-gerrit

commit 32329960f22357ea9129cb6f06d4c36227f15269
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add romstage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
 src/arch/x86/romstage.S   | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 00d8d27..fe974ef 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-crt0s = $(src)/arch/x86/prologue.inc
 romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
 romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
 
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
 
 endif
 
-romstage-srcs += $(objgenerated)/crt0.S
-
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 
-$(objgenerated)/crt0.S: $$(crt0s)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..b19b954
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>


From gerrit at coreboot.org  Tue Sep  8 22:33:18 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:33:18 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <Id17cf95c943103de006c5f3f21a625838ab49929+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505

-gerrit

commit 6876c5f98bc33243a2ba80b5c3e675119933d08a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/romstage.ld | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
-		*(.rom.text.*);
+		*(.rom.data);
 		*(.text);
 		*(.text.*);
-		*(.rom.data);
 		. = ALIGN(4);
 		_cbmem_init_hooks = .;
 		KEEP(*(.rodata.cbmem_init_hooks));
 		_ecbmem_init_hooks = .;
 		*(.rodata);
 		*(.rodata.*);
-		*(.rom.data.*);
 		. = ALIGN(16);
 		_erom = .;
 	}


From gerrit at coreboot.org  Tue Sep  8 22:33:27 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:33:27 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prepare
	for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <I176d0ae0ae1933cdf6adac67d393ba676198861a+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11595

-gerrit

commit 889658679cc9aa74493b7793da6a66bda8ab45e3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 69 ++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 5b193d9..bfa3426 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,14 +50,11 @@ struct rmod_context {
 	Elf64_Xword nrelocs;
 	Elf64_Addr *emitted_relocs;
 
-	/* The following fields are addresses within the linked program. */
-	Elf64_Addr link_addr;
-	Elf64_Addr entry;
+	/* The following fields are addresses within the linked program.  */
 	Elf64_Addr parameters_begin;
 	Elf64_Addr parameters_end;
 	Elf64_Addr bss_begin;
 	Elf64_Addr bss_end;
-	Elf64_Xword size;
 };
 
 /*
@@ -371,7 +368,7 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 	return -1;
 }
 
-static int populate_program_info(struct rmod_context *ctx)
+static int populate_rmodule_info(struct rmod_context *ctx)
 {
 	int i;
 	const char *strtab;
@@ -423,15 +420,6 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
-	/* Honor the entry point within the ELF header. */
-	ctx->entry = ehdr->e_entry;
-
-	/* Link address is the virtual address of the program segment. */
-	ctx->link_addr = ctx->phdr->p_vaddr;
-
-	/* The program size is the memsz of the program segment. */
-	ctx->size = ctx->phdr->p_memsz;
-
 	return 0;
 }
 
@@ -516,7 +504,6 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 
 	/* Create ELF writer with modified entry point. */
 	memcpy(&ehdr, &ctx->pelf.ehdr, sizeof(ehdr));
-	ehdr.e_entry = ctx->entry;
 	ew = elf_writer_init(&ehdr);
 
 	if (ew == NULL) {
@@ -544,11 +531,11 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 		loc += ctx->nrelocs * sizeof(Elf32_Addr);
 	ctx->xdr->put32(&rmod_header, loc);
 	/* module_link_start_address */
-	ctx->xdr->put32(&rmod_header, ctx->link_addr);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_vaddr);
 	/* module_program_size */
-	ctx->xdr->put32(&rmod_header, ctx->size);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_memsz);
 	/* module_entry_point */
-	ctx->xdr->put32(&rmod_header, ctx->entry);
+	ctx->xdr->put32(&rmod_header, ctx->pelf.ehdr.e_entry);
 	/* parameters_begin */
 	ctx->xdr->put32(&rmod_header, ctx->parameters_begin);
 	/* parameters_end */
@@ -631,16 +618,15 @@ out:
 	return ret;
 }
 
-int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
-	struct rmod_context ctx;
 	struct parsed_elf *pelf;
 	int i;
 	int ret;
 
 	ret = -1;
-	memset(&ctx, 0, sizeof(ctx));
-	pelf = &ctx.pelf;
+	memset(ctx, 0, sizeof(*ctx));
+	pelf = &ctx->pelf;
 
 	if (parse_elf(elfin, pelf, ELF_PARSE_ALL)) {
 		ERROR("Couldn't parse ELF!\n");
@@ -656,32 +642,52 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	/* Determine if architecture is supported. */
 	for (i = 0; i < ARRAY_SIZE(reloc_ops); i++) {
 		if (reloc_ops[i].arch == pelf->ehdr.e_machine) {
-			ctx.ops = &reloc_ops[i];
+			ctx->ops = &reloc_ops[i];
 			break;
 		}
 	}
 
-	if (ctx.ops == NULL) {
+	if (ctx->ops == NULL) {
 		ERROR("ELF is unsupported arch: %u.\n", pelf->ehdr.e_machine);
 		goto out;
 	}
 
 	/* Set the endian ops. */
-	if (ctx.pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
-		ctx.xdr = &xdr_be;
+	if (ctx->pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
+		ctx->xdr = &xdr_be;
 	else
-		ctx.xdr = &xdr_le;
+		ctx->xdr = &xdr_le;
 
-	if (find_program_segment(&ctx))
+	if (find_program_segment(ctx))
 		goto out;
 
-	if (filter_relocation_sections(&ctx))
+	if (filter_relocation_sections(ctx))
+		goto out;
+
+	ret = 0;
+
+out:
+	return ret;
+}
+
+static void rmodule_cleanup(struct rmod_context *ctx)
+{
+	free(ctx->emitted_relocs);
+	parsed_elf_destroy(&ctx->pelf);
+}
+
+int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+{
+	struct rmod_context ctx;
+	int ret = -1;
+
+	if (rmodule_init(&ctx, elfin))
 		goto out;
 
 	if (collect_relocations(&ctx))
 		goto out;
 
-	if (populate_program_info(&ctx))
+	if (populate_rmodule_info(&ctx))
 		goto out;
 
 	if (write_elf(&ctx, elfin, elfout))
@@ -690,7 +696,6 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	ret = 0;
 
 out:
-	free(ctx.emitted_relocs);
-	parsed_elf_destroy(pelf);
+	rmodule_cleanup(&ctx);
 	return ret;
 }


From gerrit at coreboot.org  Tue Sep  8 22:33:55 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:33:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+16@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit bfb7e67ade9b4d009e7f2c49cfee64ab65b6483a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               |  42 +++++++++--
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    | 130 ++++++++++++++++++++++++++++++++++
 src/lib/ramstage.ld                   | 115 ------------------------------
 7 files changed, 197 insertions(+), 122 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 10a94c3..3c1871e 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -295,7 +295,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3963339 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -34,6 +65,9 @@
 	SET_COUNTER(name, addr) \
 	_##name = .;
 
+#define SYMBOL_CURRENT_LOC(name) \
+	_##name = .;
+
 #define REGION(name, addr, size, expected_align) \
 	SYMBOL(name, addr) \
 	_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,12 +127,12 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..02d017a
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+.text : {
+	SYMBOL_CURRENT_LOC(program)
+	SYMBOL_CURRENT_LOC(text)
+	ARCH_FIRST_TEXT
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
+	KEEP(*(.rodata.cbmem_init_hooks));
+	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#endif
+
+#if ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(pci_drivers)
+	KEEP(*(.rodata.pci_driver));
+	SYMBOL_CURRENT_LOC(epci_drivers)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(cpu_drivers)
+	KEEP(*(.rodata.cpu_driver));
+	SYMBOL_CURRENT_LOC(ecpu_drivers)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	*(.rodata);
+	*(.rodata.*);
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(etext)
+} : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+.ctors : {
+	ALIGN_COUNTER(0x100)
+	SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(__CTOR_END__)
+}
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+#if ARCH_STAGE_HAS_DATA_SECTION
+.data : {
+	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(data)
+	*(.data);
+	*(.data.*);
+
+#ifdef __PRE_RAM__
+	PROVIDE(_preram_cbmem_console = .);
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bs_init_begin)
+	KEEP(*(.bs_init));
+	LONG(0);
+	LONG(0);
+	SYMBOL_CURRENT_LOC(ebs_init_begin)
+#endif
+
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(edata)
+}
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+.bss : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(bss)
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(ebss)
+}
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+.heap : {
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(heap)
+	. += CONFIG_HEAP_SIZE;
+	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+	SYMBOL_CURRENT_LOC(eheap)
+}
+#endif
+
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Tue Sep  8 22:34:00 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:34:00 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: provide
	minimum alignment for romstage
References: <Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15+0@gerrit.coreboot.org>
Message-ID: <Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11588

-gerrit

commit f9fe848c5e7a466b2b29490c2baae1cb062aa8f7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Sep 7 23:05:28 2015 -0500

    x86: provide minimum alignment for romstage
    
    The current way the XIP address of romstage is calculated is by
    doing a 'cbfstool locate' using a bin file of romstage linked
    at address 0. That address is then used for re-linking romstage at
    the address spit out by cbfstool. Currently, the linker actually
    sets minimum alignment on the text sections as 32 bytes, but it
    doesn't actually honor that value. Instead, provide a minimum
    alignment for romstage so as not to fight the linker.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built asus/kfsn4-dre. Confirmed ROMSTAGE_BASE == gdtptr.
    
    Change-Id: Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index fe974ef..10a94c3 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -207,9 +207,15 @@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xi
 	sed -e '/^ROMSTAGE_BASE/d' $(objgenerated)/romstage_null.ld >> $@.tmp
 	mv $@.tmp $@
 
+# Use a '-a 64' option to cbfstool locate to provide a minimum alignment
+# requirement for the overall romstage. While the first object within
+# romstage could have a 4 byte minimum alignment that doesn't mean the linker
+# won't decide the entire section should be aligned to a larger value. In the
+# future cbfstool should add XIP files proper and honor the alignment
+# requirements of the program segment.
 $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
 	rm -f $@
-	$(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \
+	$(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) -a 64 > $@.tmp \
 	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	mv $@.tmp $@
 


From gerrit at coreboot.org  Tue Sep  8 22:34:14 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:34:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit c73f8d6feac1c111161a0fcbdbf753142864cbea
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 5f9c3c1..d4be3f8 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,4 +139,31 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Tue Sep  8 22:34:25 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:34:25 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit f85646b752fe14d5ddcf6857e56144766db66247
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |   4 +-
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/program.ld                    |  15 +++--
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 14 files changed, 64 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index be6021b..4add195 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..55b4cb7 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index d4be3f8..a25e018 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -47,9 +47,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index 607d7fc..7523347 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /*
@@ -84,6 +99,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 02d017a..43b1fea 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -74,13 +74,20 @@
 .data : {
 	ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(data)
+
+#if ENV_RMODULE
+	SYMBOL_CURRENT_LOC(rmodule_params)
+	KEEP(*(.module_parameters));
+	SYMBOL_CURRENT_LOC(ermodule_params)
+#endif
+
 	*(.data);
 	*(.data.*);
 
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));
@@ -111,7 +118,7 @@
 .heap : {
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(heap)
-	. += CONFIG_HEAP_SIZE;
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(eheap)
 }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Tue Sep  8 22:34:38 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:34:38 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit 5ccb80b0ef12558dd0e4dd7788d43363fdd06822
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 50 +++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 97 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0315798..788d7c7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -294,11 +294,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..6793ca1
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		SYMBOL_CURRENT_LOC(car_data_start)
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+		TIMESTAMP(., 0x100)
+#endif
+		*(.car.global_data);
+		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+		SYMBOL_CURRENT_LOC(car_data_end)
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+	}
+
+	/* Global variables are not allowed in romstage
+	 * This section is checked during stage creation to ensure
+	 * that there are no global variables present
+	 */
+
+	. = 0xffffff00;
+	.illegal_globals . : {
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+		*(.bss)
+		*(.bss.*)
+		*(.sbss)
+		*(.sbss.*)
+	}
+
+	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index 4bb7250..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		SYMBOL_CURRENT_LOC(car_data_start)
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
-		SYMBOL_CURRENT_LOC(car_data_end)
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Tue Sep  8 22:34:56 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:34:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit 8c26087d44171eb97a7579c73bd603df06669409
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 6 ++++++
 8 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 788d7c7..3d1d214 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -298,7 +298,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..d143dd7 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,11 @@ CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 
+# Set the LDFLAGS for each arch.
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+$(foreach arch,$(ARCH_SUPPORTED), \
+	$(eval LDFLAGS_$(arch):=$(LDFLAGS_common)))
+
 # Some boards only provide 2K stacks, so storing lots of data there leads to
 # problems. Since C rules don't allow us to statically determine the maximum
 # stack use, we use 1.5K as heuristic, assuming that we typically have lots
@@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Tue Sep  8 22:35:14 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:35:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit 88d916f3eb5f4f649455b60c786135a4ef2d08b6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Tue Sep  8 22:35:29 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:35:29 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit 93a63fb6dd6bf45165b5f633050fc0e185713b34
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/lib/Makefile.inc      |  9 ++++++---
 src/lib/program.ld        |  6 +++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3d1d214..68ed810 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -282,17 +282,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -300,8 +294,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 43b1fea..794dcf8 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -33,14 +33,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(cbmem_init_hooks)
 	KEEP(*(.rodata.cbmem_init_hooks));
 	SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(pci_drivers)
 	KEEP(*(.rodata.pci_driver));
@@ -87,7 +87,7 @@
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 	ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
 	SYMBOL_CURRENT_LOC(bs_init_begin)
 	KEEP(*(.bs_init));


From gerrit at coreboot.org  Tue Sep  8 22:35:46 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:35:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rules.h: add fall
	through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <Ia9688886d445c961f4a448fc7bfcb28f691609db+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513

-gerrit

commit 4459bd9e40f1e42393b0dac1758559cbcbb234eb
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/rules.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a..607d7fc 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,27 @@
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
 
-#else
+#elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 1
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+
+#else
+/*
+ * Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. Also AGESA
+ * apparently builds things compeletely separate from coreboot's
+ * build infrastructure -- hardcoding its own rules.
+ */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.


From gerrit at coreboot.org  Tue Sep  8 22:36:02 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:36:02 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: bootblock:
	remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495

-gerrit

commit e85f3375cabb7d9ed6579d9a9e8bef66bba9c064
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc                      | 54 +++++++-------------------
 src/arch/x86/bootblock.S                       | 51 ++++++++++++++++++++++++
 src/arch/x86/bootblock.ld                      | 29 ++++++++++++++
 src/arch/x86/id.inc                            |  2 +
 src/cpu/dmp/vortex86ex/Kconfig                 |  4 ++
 src/cpu/dmp/vortex86ex/Makefile.inc            |  2 -
 src/cpu/dmp/vortex86ex/biosdata.inc            |  2 +-
 src/cpu/dmp/vortex86ex/chipset_bootblock.inc   |  2 +
 src/northbridge/via/vx800/Kconfig              |  8 ++++
 src/northbridge/via/vx800/Makefile.inc         |  1 -
 src/northbridge/via/vx900/Kconfig              |  4 ++
 src/northbridge/via/vx900/Makefile.inc         |  1 -
 src/soc/intel/baytrail/Kconfig                 |  4 ++
 src/soc/intel/baytrail/Makefile.inc            |  1 -
 src/soc/intel/baytrail/bootblock/Makefile.inc  |  1 -
 src/soc/intel/braswell/Kconfig                 |  4 ++
 src/soc/intel/braswell/Makefile.inc            |  1 -
 src/soc/intel/braswell/bootblock/Makefile.inc  |  1 -
 src/soc/intel/broadwell/Kconfig                |  4 ++
 src/soc/intel/broadwell/Makefile.inc           |  1 -
 src/soc/intel/broadwell/bootblock/Makefile.inc |  1 -
 src/soc/intel/skylake/Kconfig                  |  4 ++
 src/soc/intel/skylake/Makefile.inc             |  1 -
 src/soc/intel/skylake/bootblock/Makefile.inc   |  1 -
 src/southbridge/nvidia/ck804/Kconfig           |  5 +++
 src/southbridge/nvidia/ck804/Makefile.inc      |  1 -
 src/southbridge/nvidia/mcp55/Kconfig           |  4 ++
 src/southbridge/nvidia/mcp55/Makefile.inc      |  1 -
 src/southbridge/sis/sis966/Kconfig             | 12 +++++-
 src/southbridge/sis/sis966/Makefile.inc        |  1 -
 src/southbridge/via/k8t890/Kconfig             |  4 ++
 src/southbridge/via/k8t890/Makefile.inc        |  1 -
 32 files changed, 155 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..b0546f5 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
 
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
 
 bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
 bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+	touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock.ld, $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	cat $^ >> $@.tmp
 	mv $@.tmp $@
 
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $<  > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 else
-	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+	$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
 endif
 
 
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..7276c7a
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generated by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions at the beginning of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
new file mode 100644
index 0000000..6835430
--- /dev/null
+++ b/src/arch/x86/bootblock.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/x86/failover.ld>
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
+
+/* Include generated .ld files. */
+#include <generated/bootblock.ld>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
 	.section ".id", "a", @progbits
 
 	.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
 
 endchoice
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
 endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
 bootblock-y += biosdata.ld
 bootblock-y += biosdata_ex.ld
 
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
 
 	.section ".dmp_kbd_fw_part1", "a", @progbits
 
-	#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+	#include "dmp_kbd_fw_part1.inc"
 
 .previous
 
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
 ramstage-y += lpc.c
 ramstage-y += ide.c
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
 	string
 	default "1106,7122"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "northbridge/via/vx900/romstrap.inc"
+
 endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
 ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
 
 
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/baytrail/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/braswell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/broadwell/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
 	select DRIVERS_UART_8250MEM
 	select DRIVERS_UART_8250MEM_32
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "soc/intel/skylake/bootblock/timestamp.inc"
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 3bd9823..32ecb5d 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
 config HPET_MIN_TICKS
 	hex
 	default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/ck804/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
 	int
 	default 4
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/nvidia/mcp55/romstrap.inc"
+
 endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 endif
 
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
 
+if SOUTHBRIDGE_SIS_SIS966
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+	default "southbridge/sis/sis966/bootblock.c"
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+	default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
+config CHIPSET_BOOTBLOCK_INCLUDE
+	string
+	default "southbridge/via/k8t890/romstrap.inc"
+
 endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
 ramstage-y += error.c
 ramstage-y += chrome.c
 
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
 
 endif


From gerrit at coreboot.org  Tue Sep  8 22:36:15 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:36:15 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: don't create
	MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503

-gerrit

commit 93e06d2c24d4632514ca8f7e3929a6918657210d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b0546f5..00d8d27 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -125,13 +125,19 @@ endif
 
 crt0s += $(cpu_incs-y)
 
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+ifneq ($(CONFIG_ROMCC),y)
+
+romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
 
-ifeq ($(CONFIG_ROMCC),y)
+else # CONFIG_ROMCC == y
+
+# This order matters. The mainboards requiring ROMCC need their mainboard
+# code to follow the prior crt0s files for program flow control. The
+# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
+# because of the instruction sequen fall-through.
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
-endif
 
-ifeq ($(CONFIG_ROMCC),y)
 ifeq ($(CONFIG_MMX),y)
 	ifeq ($(CONFIG_SSE),y)
 		ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
@@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	printf "    ROMCC      romstage.inc\n"
 	$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
-else
 
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
-	@printf "    CC         romstage.inc\n"
-	$(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
-	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
-		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
-	mv $@.tmp $@
 endif
 
 romstage-srcs += $(objgenerated)/crt0.S


From gerrit at coreboot.org  Tue Sep  8 22:36:17 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 8 Sep 2015 22:36:17 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	expose rmodule logic
References: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+0@gerrit.coreboot.org>
Message-ID: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11598

-gerrit

commit 46cba4eb3e14a202ac0aac2bdfdb0500d6da9f83
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 17:24:04 2015 -0500

    cbfstool: expose rmodule logic
    
    In order to allow cbfstool to add XIP romstage on x86 without
    doing the 'cbfstool locate', relink, then 'cbfstool add' dance
    expose the core logic and of rmodule including proving an optional
    filter. The filter will be used for ignoring relocations to the
    .car.global region.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 62 ++++++++++++++++---------------------------------
 util/cbfstool/rmodule.h | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+), 42 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index bfa3426..90d7845 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -24,39 +24,6 @@
 #include "rmodule.h"
 #include <rmodule-defs.h>
 
-struct rmod_context;
-
-struct arch_ops {
-	int arch;
-	/* Determine if relocation is a valid type for the architecture. */
-	int (*valid_type)(Elf64_Rela *rel);
-	/* Determine if relocation should be emitted. */
-	int (*should_emit)(Elf64_Rela *rel);
-};
-
-struct rmod_context {
-	/* Ops to process relocations. */
-	struct arch_ops *ops;
-
-	/* endian conversion ops */
-	struct xdr *xdr;
-
-	/* Parsed ELF sturcture. */
-	struct parsed_elf pelf;
-	/* Program segment. */
-	Elf64_Phdr *phdr;
-
-	/* Collection of relocation addresses fixup in the module. */
-	Elf64_Xword nrelocs;
-	Elf64_Addr *emitted_relocs;
-
-	/* The following fields are addresses within the linked program.  */
-	Elf64_Addr parameters_begin;
-	Elf64_Addr parameters_end;
-	Elf64_Addr bss_begin;
-	Elf64_Addr bss_end;
-};
-
 /*
  * Architecture specific support operations.
  */
@@ -130,7 +97,7 @@ static int should_emit_aarch64(Elf64_Rela *rel)
 	return (type == R_AARCH64_ABS64);
 }
 
-static struct arch_ops reloc_ops[] = {
+static const struct arch_ops reloc_ops[] = {
 	{
 		.arch = EM_386,
 		.valid_type = valid_reloc_386,
@@ -152,7 +119,8 @@ static struct arch_ops reloc_ops[] = {
  * Relocation processing loops.
  */
 
-static int for_each_reloc(struct rmod_context *ctx, int do_emit)
+static int for_each_reloc(struct rmod_context *ctx, struct reloc_filter *f,
+				int do_emit)
 {
 	Elf64_Half i;
 	struct parsed_elf *pelf = &ctx->pelf;
@@ -173,6 +141,7 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 		nrelocs = shdr->sh_size / shdr->sh_entsize;
 
 		for (j = 0; j < nrelocs; j++) {
+			int filter_emit = 1;
 			Elf64_Rela *r = &relocs[j];
 
 			if (!ctx->ops->valid_type(r)) {
@@ -181,7 +150,15 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 				return -1;
 			}
 
-			if (ctx->ops->should_emit(r)) {
+			/* Allow the provided filter to have precedence. */
+			if (f != NULL) {
+				filter_emit = f->filter(f, r);
+
+				if (filter_emit < 0)
+					return filter_emit;
+			}
+
+			if (filter_emit && ctx->ops->should_emit(r)) {
 				int n = ctx->nrelocs;
 				if (do_emit)
 					ctx->emitted_relocs[n] = r->r_offset;
@@ -303,7 +280,8 @@ static int vaddr_cmp(const void *a, const void *b)
 	return 0;
 }
 
-static int collect_relocations(struct rmod_context *ctx)
+int rmodule_collect_relocations(struct rmod_context *ctx,
+				struct reloc_filter *f)
 {
 	Elf64_Xword nrelocs;
 
@@ -312,7 +290,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	 * apply to the program. Count the number relocations. Then collect
 	 * them into the allocated buffer.
 	 */
-	if (for_each_reloc(ctx, 0))
+	if (for_each_reloc(ctx, f, 0))
 		return -1;
 
 	nrelocs = ctx->nrelocs;
@@ -324,7 +302,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	ctx->nrelocs = 0;
 	ctx->emitted_relocs = calloc(nrelocs, sizeof(Elf64_Addr));
 	/* Write out the relocations into the emitted_relocs array. */
-	if (for_each_reloc(ctx, 1))
+	if (for_each_reloc(ctx, f, 1))
 		return -1;
 
 	if (ctx->nrelocs != nrelocs) {
@@ -618,7 +596,7 @@ out:
 	return ret;
 }
 
-static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
 	struct parsed_elf *pelf;
 	int i;
@@ -670,7 +648,7 @@ out:
 	return ret;
 }
 
-static void rmodule_cleanup(struct rmod_context *ctx)
+void rmodule_cleanup(struct rmod_context *ctx)
 {
 	free(ctx->emitted_relocs);
 	parsed_elf_destroy(&ctx->pelf);
@@ -684,7 +662,7 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	if (rmodule_init(&ctx, elfin))
 		goto out;
 
-	if (collect_relocations(&ctx))
+	if (rmodule_collect_relocations(&ctx, NULL))
 		goto out;
 
 	if (populate_rmodule_info(&ctx))
diff --git a/util/cbfstool/rmodule.h b/util/cbfstool/rmodule.h
index 4531f8d..f3d750d 100644
--- a/util/cbfstool/rmodule.h
+++ b/util/cbfstool/rmodule.h
@@ -21,10 +21,71 @@
 #include "elf.h"
 #include "common.h"
 
+struct arch_ops {
+	int arch;
+	/* Determine if relocation is a valid type for the architecture. */
+	int (*valid_type)(Elf64_Rela *rel);
+	/* Determine if relocation should be emitted. */
+	int (*should_emit)(Elf64_Rela *rel);
+};
+
+/*
+ * The fields in rmod_context are read-only to the user. These are
+ * exposed for easy shareability.
+ */
+struct rmod_context {
+	/* Ops to process relocations. */
+	const struct arch_ops *ops;
+
+	/* endian conversion ops */
+	struct xdr *xdr;
+
+	/* Parsed ELF sturcture. */
+	struct parsed_elf pelf;
+	/* Program segment. */
+	Elf64_Phdr *phdr;
+
+	/* Collection of relocation addresses fixup in the module. */
+	Elf64_Xword nrelocs;
+	Elf64_Addr *emitted_relocs;
+
+	/* The following fields are addresses within the linked program.  */
+	Elf64_Addr parameters_begin;
+	Elf64_Addr parameters_end;
+	Elf64_Addr bss_begin;
+	Elf64_Addr bss_end;
+};
+
+struct reloc_filter {
+	/* Return < 0 on error. 0 to ignore relocation and 1 to include
+	 * relocation. */
+	int (*filter)(struct reloc_filter *f, const Elf64_Rela *r);
+	/* Pointer for filter provides */
+	void *context;
+};
+
 /*
  * Parse an ELF file within the elfin buffer and fill in the elfout buffer
  * with a created rmodule in ELF format. Return 0 on success, < 0 on error.
  */
 int rmodule_create(const struct buffer *elfin, struct buffer *elfout);
 
+/*
+ * Initialize an rmodule context from an ELF buffer. Returns 0 on scucess, < 0
+ * on error.
+ */
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin);
+
+/*
+ * Collect all the relocations that apply to the program in
+ * nrelocs/emitted_relocs. One can optionally provide a reloc_filter object
+ * to help in relocation filtering. The filter function will be called twice:
+ * once for counting and once for emitting. The same response should be
+ * provided for each call. Returns 0 on success, < 0 on error.
+ */
+int rmodule_collect_relocations(struct rmod_context *c, struct reloc_filter *f);
+
+/* Clean up the memory consumed by the rmdoule context. */
+void rmodule_cleanup(struct rmod_context *ctx);
+
 #endif /* TOOL_RMODULE_H */


From gerrit at coreboot.org  Wed Sep  9 03:04:56 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:04:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <I012c9b88c178b43bf6a6dde0bab821e066728139+17@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 9c7f1d039e4bb65d501d4ea580517b76c2ba8f6b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }


From gerrit at coreboot.org  Wed Sep  9 03:05:28 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:05:28 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <I4c3e3671d696caa2c7601065a85fab803e86f971+18@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509

-gerrit

commit c64e7500571afe9f408ab95a9592e76206b29bc9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h | 12 +++++-----
 src/lib/Makefile.inc    |  4 ++--
 src/lib/bootblock.ld    | 51 ---------------------------------------
 src/lib/romstage.ld     | 64 -------------------------------------------------
 4 files changed, 8 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index f0ee3d3..aa22be9 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -96,24 +96,24 @@
 #endif
 
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
-		_ = ASSERT(_ebootblock - _bootblock <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Bootblock exceeded its allotted size! (sz))); \
-		INCLUDE "lib/bootblock.bootblock.ld"
+		INCLUDE "lib/program.bootblock.ld"
 #else
 	#define BOOTBLOCK(addr, sz) \
 		SET_COUNTER(bootblock, addr) \
 		. += sz;
 #endif
 
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
-		_ = ASSERT(_eromstage - _romstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Romstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/romstage.romstage.ld"
+		INCLUDE "lib/program.romstage.ld"
 #else
 	#define ROMSTAGE(addr, sz) \
 		SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
 ifneq ($(CONFIG_ARCH_X86),y)
 # X86 bootblock and romstage use custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
 endif
 
 ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
-	_program = .;
-	_bootblock = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	KEEP(*(.id));
-	*(.text);
-	*(.text.*);
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	*(.bss);
-	*(.bss.*);
-	*(.sbss);
-	*(.sbss.*);
-	_preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
-	_epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
-	_ebootblock = .;
-	_eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.ARM.*)
-	*(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_romstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	. = ALIGN(8);
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	PROVIDE(_preram_cbmem_console = .);
-	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_eromstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Wed Sep  9 03:05:30 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:05:30 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: expose
	rmodule logic
References: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+0@gerrit.coreboot.org>
Message-ID: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11598

-gerrit

commit 2af9a2b643b5f2e58e6bf0e571153375341547c2
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 17:24:04 2015 -0500

    cbfstool: expose rmodule logic
    
    In order to allow cbfstool to add XIP romstage on x86 without
    doing the 'cbfstool locate', relink, then 'cbfstool add' dance
    expose the core logic and of rmodule including proving an optional
    filter. The filter will be used for ignoring relocations to the
    .car.global region.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 62 ++++++++++++++++---------------------------------
 util/cbfstool/rmodule.h | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+), 42 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index bfa3426..90d7845 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -24,39 +24,6 @@
 #include "rmodule.h"
 #include <rmodule-defs.h>
 
-struct rmod_context;
-
-struct arch_ops {
-	int arch;
-	/* Determine if relocation is a valid type for the architecture. */
-	int (*valid_type)(Elf64_Rela *rel);
-	/* Determine if relocation should be emitted. */
-	int (*should_emit)(Elf64_Rela *rel);
-};
-
-struct rmod_context {
-	/* Ops to process relocations. */
-	struct arch_ops *ops;
-
-	/* endian conversion ops */
-	struct xdr *xdr;
-
-	/* Parsed ELF sturcture. */
-	struct parsed_elf pelf;
-	/* Program segment. */
-	Elf64_Phdr *phdr;
-
-	/* Collection of relocation addresses fixup in the module. */
-	Elf64_Xword nrelocs;
-	Elf64_Addr *emitted_relocs;
-
-	/* The following fields are addresses within the linked program.  */
-	Elf64_Addr parameters_begin;
-	Elf64_Addr parameters_end;
-	Elf64_Addr bss_begin;
-	Elf64_Addr bss_end;
-};
-
 /*
  * Architecture specific support operations.
  */
@@ -130,7 +97,7 @@ static int should_emit_aarch64(Elf64_Rela *rel)
 	return (type == R_AARCH64_ABS64);
 }
 
-static struct arch_ops reloc_ops[] = {
+static const struct arch_ops reloc_ops[] = {
 	{
 		.arch = EM_386,
 		.valid_type = valid_reloc_386,
@@ -152,7 +119,8 @@ static struct arch_ops reloc_ops[] = {
  * Relocation processing loops.
  */
 
-static int for_each_reloc(struct rmod_context *ctx, int do_emit)
+static int for_each_reloc(struct rmod_context *ctx, struct reloc_filter *f,
+				int do_emit)
 {
 	Elf64_Half i;
 	struct parsed_elf *pelf = &ctx->pelf;
@@ -173,6 +141,7 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 		nrelocs = shdr->sh_size / shdr->sh_entsize;
 
 		for (j = 0; j < nrelocs; j++) {
+			int filter_emit = 1;
 			Elf64_Rela *r = &relocs[j];
 
 			if (!ctx->ops->valid_type(r)) {
@@ -181,7 +150,15 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 				return -1;
 			}
 
-			if (ctx->ops->should_emit(r)) {
+			/* Allow the provided filter to have precedence. */
+			if (f != NULL) {
+				filter_emit = f->filter(f, r);
+
+				if (filter_emit < 0)
+					return filter_emit;
+			}
+
+			if (filter_emit && ctx->ops->should_emit(r)) {
 				int n = ctx->nrelocs;
 				if (do_emit)
 					ctx->emitted_relocs[n] = r->r_offset;
@@ -303,7 +280,8 @@ static int vaddr_cmp(const void *a, const void *b)
 	return 0;
 }
 
-static int collect_relocations(struct rmod_context *ctx)
+int rmodule_collect_relocations(struct rmod_context *ctx,
+				struct reloc_filter *f)
 {
 	Elf64_Xword nrelocs;
 
@@ -312,7 +290,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	 * apply to the program. Count the number relocations. Then collect
 	 * them into the allocated buffer.
 	 */
-	if (for_each_reloc(ctx, 0))
+	if (for_each_reloc(ctx, f, 0))
 		return -1;
 
 	nrelocs = ctx->nrelocs;
@@ -324,7 +302,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	ctx->nrelocs = 0;
 	ctx->emitted_relocs = calloc(nrelocs, sizeof(Elf64_Addr));
 	/* Write out the relocations into the emitted_relocs array. */
-	if (for_each_reloc(ctx, 1))
+	if (for_each_reloc(ctx, f, 1))
 		return -1;
 
 	if (ctx->nrelocs != nrelocs) {
@@ -618,7 +596,7 @@ out:
 	return ret;
 }
 
-static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
 	struct parsed_elf *pelf;
 	int i;
@@ -670,7 +648,7 @@ out:
 	return ret;
 }
 
-static void rmodule_cleanup(struct rmod_context *ctx)
+void rmodule_cleanup(struct rmod_context *ctx)
 {
 	free(ctx->emitted_relocs);
 	parsed_elf_destroy(&ctx->pelf);
@@ -684,7 +662,7 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	if (rmodule_init(&ctx, elfin))
 		goto out;
 
-	if (collect_relocations(&ctx))
+	if (rmodule_collect_relocations(&ctx, NULL))
 		goto out;
 
 	if (populate_rmodule_info(&ctx))
diff --git a/util/cbfstool/rmodule.h b/util/cbfstool/rmodule.h
index 4531f8d..f3d750d 100644
--- a/util/cbfstool/rmodule.h
+++ b/util/cbfstool/rmodule.h
@@ -21,10 +21,71 @@
 #include "elf.h"
 #include "common.h"
 
+struct arch_ops {
+	int arch;
+	/* Determine if relocation is a valid type for the architecture. */
+	int (*valid_type)(Elf64_Rela *rel);
+	/* Determine if relocation should be emitted. */
+	int (*should_emit)(Elf64_Rela *rel);
+};
+
+/*
+ * The fields in rmod_context are read-only to the user. These are
+ * exposed for easy shareability.
+ */
+struct rmod_context {
+	/* Ops to process relocations. */
+	const struct arch_ops *ops;
+
+	/* endian conversion ops */
+	struct xdr *xdr;
+
+	/* Parsed ELF sturcture. */
+	struct parsed_elf pelf;
+	/* Program segment. */
+	Elf64_Phdr *phdr;
+
+	/* Collection of relocation addresses fixup in the module. */
+	Elf64_Xword nrelocs;
+	Elf64_Addr *emitted_relocs;
+
+	/* The following fields are addresses within the linked program.  */
+	Elf64_Addr parameters_begin;
+	Elf64_Addr parameters_end;
+	Elf64_Addr bss_begin;
+	Elf64_Addr bss_end;
+};
+
+struct reloc_filter {
+	/* Return < 0 on error. 0 to ignore relocation and 1 to include
+	 * relocation. */
+	int (*filter)(struct reloc_filter *f, const Elf64_Rela *r);
+	/* Pointer for filter provides */
+	void *context;
+};
+
 /*
  * Parse an ELF file within the elfin buffer and fill in the elfout buffer
  * with a created rmodule in ELF format. Return 0 on success, < 0 on error.
  */
 int rmodule_create(const struct buffer *elfin, struct buffer *elfout);
 
+/*
+ * Initialize an rmodule context from an ELF buffer. Returns 0 on scucess, < 0
+ * on error.
+ */
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin);
+
+/*
+ * Collect all the relocations that apply to the program in
+ * nrelocs/emitted_relocs. One can optionally provide a reloc_filter object
+ * to help in relocation filtering. The filter function will be called twice:
+ * once for counting and once for emitting. The same response should be
+ * provided for each call. Returns 0 on success, < 0 on error.
+ */
+int rmodule_collect_relocations(struct rmod_context *c, struct reloc_filter *f);
+
+/* Clean up the memory consumed by the rmdoule context. */
+void rmodule_cleanup(struct rmod_context *ctx);
+
 #endif /* TOOL_RMODULE_H */


From gerrit at coreboot.org  Wed Sep  9 03:06:04 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:06:04 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <I016666c4b01410df112e588c2949e3fc64540c2e+19@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510

-gerrit

commit 38a59949d89bedb7d82f96cdaf78964697bdf2d4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |  7 +++---
 src/arch/x86/include/arch/header.ld   |  6 +++++
 src/arch/x86/include/arch/memlayout.h |  8 +++++-
 src/arch/x86/romstage.ld              | 46 ++++++++---------------------------
 src/cpu/x86/32bit/entry32.ld          |  1 -
 src/lib/Makefile.inc                  |  4 +--
 src/lib/program.ld                    |  6 +++++
 7 files changed, 34 insertions(+), 44 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3c1871e..0315798 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb27..55547ad 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a..91cfc8e 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,12 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142e..d6d1b9c 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
 		_car_data_start = .;
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
+		. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.ld
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4aa6bf8..464d631 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -192,12 +192,12 @@ smm-y += halt.c
 secmon-y += halt.c
 
 ifneq ($(CONFIG_ARCH_X86),y)
-# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# X86 bootblock uses custom ldscripts that are all glued together,
 # so we need to exclude it here or it would pick these up as well
 bootblock-y += program.ld
-romstage-y += program.ld
 endif
 
+romstage-y += program.ld
 ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 1346eaf..cf011e9 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -27,6 +27,12 @@
 .text : {
 	_program = .;
 	_text = .;
+	/*
+	 * The .rom.* sections are to acommodate x86 romstage. romcc as well
+	 * as the assembly files put their text and data in these sections.
+	 */
+	*(.rom.text);
+	*(.rom.data);
 	*(.text._start);
 	*(.text.stage_entry);
 	*(.text);


From gerrit at coreboot.org  Wed Sep  9 03:06:16 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:06:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: RFC: Introduce
	commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit b08087aa35917211992305f8518aea54e1b63a0c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    RFC: Introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                             |   4 +-
 src/commonlib/Makefile.inc               |  10 ++
 src/commonlib/include/cbmem_id.h         | 113 ++++++++++++++++++
 src/commonlib/include/console/loglevel.h | 178 ++++++++++++++++++++++++++++
 src/commonlib/include/helpers.h          |  40 +++++++
 src/commonlib/include/mem_pool.h         |  73 ++++++++++++
 src/commonlib/include/region.h           | 157 +++++++++++++++++++++++++
 src/commonlib/include/rmodule-defs.h     |  63 ++++++++++
 src/commonlib/mem_pool.c                 |  51 ++++++++
 src/commonlib/region.c                   | 196 +++++++++++++++++++++++++++++++
 src/include/cbmem_id.h                   | 113 ------------------
 src/include/console/loglevel.h           | 178 ----------------------------
 src/include/mem_pool.h                   |  73 ------------
 src/include/region.h                     | 157 -------------------------
 src/include/rmodule-defs.h               |  63 ----------
 src/include/stddef.h                     |  34 +-----
 src/lib/Makefile.inc                     |   9 --
 src/lib/mem_pool.c                       |  51 --------
 src/lib/region.c                         | 196 -------------------------------
 src/vendorcode/amd/pi/Makefile.inc       |   1 +
 util/cbfstool/Makefile                   |   1 +
 util/cbfstool/Makefile.inc               |   1 +
 util/cbfstool/rmodule.c                  |   2 +-
 util/cbmem/Makefile                      |   2 +-
 util/cbmem/cbmem.c                       |   2 +-
 25 files changed, 891 insertions(+), 877 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..34f3411 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/cbmem_id.h b/src/commonlib/include/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/console/loglevel.h b/src/commonlib/include/console/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/console/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/helpers.h b/src/commonlib/include/helpers.h
new file mode 100644
index 0000000..d6caca6
--- /dev/null
+++ b/src/commonlib/include/helpers.h
@@ -0,0 +1,40 @@
+
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/mem_pool.h b/src/commonlib/include/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/region.h b/src/commonlib/include/region.h
new file mode 100644
index 0000000..82db854
--- /dev/null
+++ b/src/commonlib/include/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/rmodule-defs.h b/src/commonlib/include/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..4bd0668
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..d5d3762
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..035a53c 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 1f41d17..5b193d9 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <rmodule-defs.h>
 
 struct rmod_context;
 
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..1d8ad6d 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86 -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..33d6493 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -51,7 +51,7 @@ typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
+#include <cbmem_id.h>
 #include "timestamp.h"
 
 #define CBMEM_VERSION "1.1"


From gerrit at coreboot.org  Wed Sep  9 03:06:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:06:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: lay the
	groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+17@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507

-gerrit

commit 18e7ced54a517fbcfbf3ba2c9f50c0118b7924a4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc             |   2 +-
 src/arch/x86/include/arch/memlayout.h |  25 +++++++
 src/arch/x86/ramstage.ld              |   2 +-
 src/include/memlayout.h               |  35 +++++++--
 src/include/symbols.h                 |  15 +---
 src/lib/Makefile.inc                  |   3 +-
 src/lib/program.ld                    | 129 ++++++++++++++++++++++++++++++++++
 src/lib/ramstage.ld                   | 115 ------------------------------
 8 files changed, 190 insertions(+), 136 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 10a94c3..3c1871e 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -295,7 +295,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
 {
 	. = CONFIG_RAMBASE;
 
-	INCLUDE "lib/ramstage.ramstage.ld"
+	INCLUDE "lib/program.ramstage.ld"
 
 	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..f0ee3d3 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,37 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
+#include <rules.h>
 #include <arch/memlayout.h>
 
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
 #define STR(x) #x
 
+#define ALIGN_COUNTER(align) \
+	. = ALIGN(align);
+
 #define SET_COUNTER(name, addr) \
 	_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
 	. = addr;
@@ -58,7 +85,7 @@
 
 /* TODO: This only works if you never access CBFS in romstage before RAM is up!
  * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,12 +120,12 @@
 		. += sz;
 #endif
 
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
-		_ = ASSERT(_eramstage - _ramstage <= sz, \
+		_ = ASSERT(_eprogram - _program <= sz, \
 			STR(Ramstage exceeded its allotted size! (sz))); \
-		INCLUDE "lib/ramstage.ramstage.ld"
+		INCLUDE "lib/program.ramstage.ld"
 #else
 	#define RAMSTAGE(addr, sz) \
 		SET_COUNTER(ramstage, addr) \
diff --git a/src/include/symbols.h b/src/include/symbols.h
index 3fbf819..22cd575 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -53,20 +53,7 @@ extern u8 _payload[];
 extern u8 _epayload[];
 #define _payload_size (_epayload - _payload)
 
-/* Careful: _e<stage> and _<stage>_size only defined for the current stage! */
-extern u8 _bootblock[];
-extern u8 _ebootblock[];
-#define _bootblock_size (_ebootblock - _bootblock)
-
-extern u8 _romstage[];
-extern u8 _eromstage[];
-#define _romstage_size (_eromstage - _romstage)
-
-extern u8 _ramstage[];
-extern u8 _eramstage[];
-#define _ramstage_size (_eramstage - _ramstage)
-
-/* "program" always refers to the current execution unit, except for x86 ROM. */
+/* "program" always refers to the current execution unit. */
 extern u8 _program[];
 extern u8 _eprogram[];
 #define _program_size (_eprogram - _program)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
 bootblock-y += bootblock.ld
 romstage-y += romstage.ld
 endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..1346eaf
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+.text : {
+	_program = .;
+	_text = .;
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_cbmem_init_hooks = .;
+	KEEP(*(.rodata.cbmem_init_hooks));
+	_ecbmem_init_hooks = .;
+#endif
+
+#if ENV_RAMSTAGE
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_pci_drivers = .;
+	KEEP(*(.rodata.pci_driver));
+	_epci_drivers = .;
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_cpu_drivers = .;
+	KEEP(*(.rodata.cpu_driver));
+	_ecpu_drivers = .;
+#endif
+
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	*(.rodata);
+	*(.rodata.*);
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_etext = .;
+} : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+.ctors : {
+	. = ALIGN(0x100)
+	__CTOR_LIST__ = .;
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	__CTOR_END__ = .;
+}
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+#if ARCH_STAGE_HAS_DATA_SECTION
+.data : {
+	. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
+	_data = .;
+	*(.data);
+	*(.data.*);
+
+#ifdef __PRE_RAM__
+	PROVIDE(_preram_cbmem_console = .);
+	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_bs_init_begin = .;
+	KEEP(*(.bs_init));
+	LONG(0);
+	LONG(0);
+	_ebs_init_begin = .;
+#endif
+
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_edata = .;
+}
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+.bss : {
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_bss = .;
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_ebss = .;
+}
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+.heap : {
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_heap = .;
+	. += CONFIG_HEAP_SIZE;
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_eheap = .;
+}
+#endif
+
+_eprogram = .;
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.comment.*)
+	*(.note)
+	*(.note.*)
+	*(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index b224827..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
-	_program = .;
-	_ramstage = .;
-	_text = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-	. = ALIGN(16);
-	_etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
-	. = ALIGN(0x100);
-	__CTOR_LIST__ = .;
-	KEEP(*(.ctors));
-	LONG(0);
-	LONG(0);
-	__CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
-	_rodata = .;
-	. = ALIGN(8);
-
-	/* If any changes are made to the driver start/symbols or the
-	 * section names the equivalent changes need to made to
-	 * rmodule.ld. */
-	_pci_drivers = . ;
-	KEEP(*(.rodata.pci_driver));
-	_epci_drivers = . ;
-	_cpu_drivers = . ;
-	KEEP(*(.rodata.cpu_driver));
-	_ecpu_drivers = . ;
-	_bs_init_begin = .;
-	KEEP(*(.bs_init));
-	LONG(0);
-	LONG(0);
-	_bs_init_end = .;
-	_cbmem_init_hooks = .;
-	KEEP(*(.rodata.cbmem_init_hooks));
-	_ecbmem_init_hooks = .;
-
-	*(.rodata)
-	*(.rodata.*)
-	/* kevinh/Ispiri - Added an align, because the objcopy tool
-	 * incorrectly converts sections that are not long word aligned.
-	 */
-	 . = ALIGN(8);
-
-	_erodata = .;
-}
-
-.data : {
-	/* Move to different cache line to avoid false sharing with .rodata. */
-	. = ALIGN(64);	/* May not be actual line size, not that important. */
-	_data = .;
-	*(.data)
-	*(.data.*)
-	_edata = .;
-}
-
-.bss . : {
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-}
-
-.heap . : {
-	_heap = .;
-	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
-	_eheap = .;
-	_eramstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.note.*)
-}


From gerrit at coreboot.org  Wed Sep  9 03:06:48 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:06:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prepare
	for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <I176d0ae0ae1933cdf6adac67d393ba676198861a+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11595

-gerrit

commit 5fc50faeddbf7ae864edd388ba8415b9e0400c17
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 69 ++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 5b193d9..bfa3426 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,14 +50,11 @@ struct rmod_context {
 	Elf64_Xword nrelocs;
 	Elf64_Addr *emitted_relocs;
 
-	/* The following fields are addresses within the linked program. */
-	Elf64_Addr link_addr;
-	Elf64_Addr entry;
+	/* The following fields are addresses within the linked program.  */
 	Elf64_Addr parameters_begin;
 	Elf64_Addr parameters_end;
 	Elf64_Addr bss_begin;
 	Elf64_Addr bss_end;
-	Elf64_Xword size;
 };
 
 /*
@@ -371,7 +368,7 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 	return -1;
 }
 
-static int populate_program_info(struct rmod_context *ctx)
+static int populate_rmodule_info(struct rmod_context *ctx)
 {
 	int i;
 	const char *strtab;
@@ -423,15 +420,6 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
-	/* Honor the entry point within the ELF header. */
-	ctx->entry = ehdr->e_entry;
-
-	/* Link address is the virtual address of the program segment. */
-	ctx->link_addr = ctx->phdr->p_vaddr;
-
-	/* The program size is the memsz of the program segment. */
-	ctx->size = ctx->phdr->p_memsz;
-
 	return 0;
 }
 
@@ -516,7 +504,6 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 
 	/* Create ELF writer with modified entry point. */
 	memcpy(&ehdr, &ctx->pelf.ehdr, sizeof(ehdr));
-	ehdr.e_entry = ctx->entry;
 	ew = elf_writer_init(&ehdr);
 
 	if (ew == NULL) {
@@ -544,11 +531,11 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 		loc += ctx->nrelocs * sizeof(Elf32_Addr);
 	ctx->xdr->put32(&rmod_header, loc);
 	/* module_link_start_address */
-	ctx->xdr->put32(&rmod_header, ctx->link_addr);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_vaddr);
 	/* module_program_size */
-	ctx->xdr->put32(&rmod_header, ctx->size);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_memsz);
 	/* module_entry_point */
-	ctx->xdr->put32(&rmod_header, ctx->entry);
+	ctx->xdr->put32(&rmod_header, ctx->pelf.ehdr.e_entry);
 	/* parameters_begin */
 	ctx->xdr->put32(&rmod_header, ctx->parameters_begin);
 	/* parameters_end */
@@ -631,16 +618,15 @@ out:
 	return ret;
 }
 
-int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
-	struct rmod_context ctx;
 	struct parsed_elf *pelf;
 	int i;
 	int ret;
 
 	ret = -1;
-	memset(&ctx, 0, sizeof(ctx));
-	pelf = &ctx.pelf;
+	memset(ctx, 0, sizeof(*ctx));
+	pelf = &ctx->pelf;
 
 	if (parse_elf(elfin, pelf, ELF_PARSE_ALL)) {
 		ERROR("Couldn't parse ELF!\n");
@@ -656,32 +642,52 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	/* Determine if architecture is supported. */
 	for (i = 0; i < ARRAY_SIZE(reloc_ops); i++) {
 		if (reloc_ops[i].arch == pelf->ehdr.e_machine) {
-			ctx.ops = &reloc_ops[i];
+			ctx->ops = &reloc_ops[i];
 			break;
 		}
 	}
 
-	if (ctx.ops == NULL) {
+	if (ctx->ops == NULL) {
 		ERROR("ELF is unsupported arch: %u.\n", pelf->ehdr.e_machine);
 		goto out;
 	}
 
 	/* Set the endian ops. */
-	if (ctx.pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
-		ctx.xdr = &xdr_be;
+	if (ctx->pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
+		ctx->xdr = &xdr_be;
 	else
-		ctx.xdr = &xdr_le;
+		ctx->xdr = &xdr_le;
 
-	if (find_program_segment(&ctx))
+	if (find_program_segment(ctx))
 		goto out;
 
-	if (filter_relocation_sections(&ctx))
+	if (filter_relocation_sections(ctx))
+		goto out;
+
+	ret = 0;
+
+out:
+	return ret;
+}
+
+static void rmodule_cleanup(struct rmod_context *ctx)
+{
+	free(ctx->emitted_relocs);
+	parsed_elf_destroy(&ctx->pelf);
+}
+
+int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+{
+	struct rmod_context ctx;
+	int ret = -1;
+
+	if (rmodule_init(&ctx, elfin))
 		goto out;
 
 	if (collect_relocations(&ctx))
 		goto out;
 
-	if (populate_program_info(&ctx))
+	if (populate_rmodule_info(&ctx))
 		goto out;
 
 	if (write_elf(&ctx, elfin, elfout))
@@ -690,7 +696,6 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	ret = 0;
 
 out:
-	free(ctx.emitted_relocs);
-	parsed_elf_destroy(pelf);
+	rmodule_cleanup(&ctx);
 	return ret;
 }


From gerrit at coreboot.org  Wed Sep  9 03:07:02 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:07:02 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <I1195e06e06c1f81a758f68a026167689c19589dd+12@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516

-gerrit

commit 612f795042c510edf7503b6e159dea13676df706
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/include/memlayout.h                            | 27 ++++++++++
 src/lib/Makefile.inc                               |  1 +
 src/soc/broadcom/cygnus/include/soc/memlayout.ld   |  1 -
 src/soc/imgtec/pistachio/include/soc/memlayout.ld  |  1 -
 src/soc/marvell/bg4cd/include/soc/memlayout.ld     |  1 -
 src/soc/nvidia/tegra124/include/soc/memlayout.ld   |  1 -
 .../tegra132/include/soc/memlayout_vboot2.ld       |  1 -
 .../tegra210/include/soc/memlayout_vboot2.ld       |  1 -
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld  |  1 -
 src/soc/rockchip/rk3288/include/soc/memlayout.ld   |  1 -
 .../samsung/exynos5250/include/soc/memlayout.ld    |  1 -
 src/vendorcode/google/chromeos/memlayout.h         | 54 --------------------
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |  2 -
 src/vendorcode/google/chromeos/vboot2/verstage.ld  | 58 ----------------------
 14 files changed, 28 insertions(+), 123 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index aa22be9..f67753c 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -132,4 +132,31 @@
 		. += sz;
 #endif
 
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+	REGION(vboot2_work, addr, size, 16) \
+	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		_ = ASSERT(_eprogram - _program <= sz, \
+			STR(Verstage exceeded its allotted size! (sz))); \
+		INCLUDE "lib/program.verstage.ld"
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+	#define VERSTAGE(addr, sz) \
+		SET_COUNTER(verstage, addr) \
+		. += sz;
+
+	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+	REGION(watchdog_tombstone, addr, size, 4) \
+	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
 #endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
 
 romstage-y += program.ld
 ramstage-y += program.ld
+verstage-y += program.ld
 
 ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
  */
 
 #include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index 29434bd..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
-	REGION(vboot2_work, addr, size, 16) \
-	_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		_ = ASSERT(_everstage - _verstage <= sz, \
-			STR(Verstage exceeded its allotted size! (sz))); \
-		INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
-	#define VERSTAGE(addr, sz) \
-		SET_COUNTER(VERSTAGE, addr) \
-		. += sz;
-#endif
-
-#ifdef __VERSTAGE__
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
-	#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
-	REGION(watchdog_tombstone, addr, size, 4) \
-	_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
 
 ramstage-y += common.c
 
-verstage-y += verstage.ld
-
 ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
 VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
-	_program = .;
-	_verstage = .;
-	*(.text._start);
-	*(.text.stage_entry);
-	*(.text);
-	*(.text.*);
-} : to_load
-
-.data . : {
-	*(.rodata);
-	*(.rodata.*);
-	*(.data);
-	*(.data.*);
-	. = ALIGN(8);
-}
-
-.bss . : {
-	. = ALIGN(8);
-	_bss = .;
-	*(.bss)
-	*(.bss.*)
-	*(.sbss)
-	*(.sbss.*)
-	_ebss = .;
-	_everstage = .;
-	_eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
-	*(.comment)
-	*(.note)
-	*(.comment.*)
-	*(.note.*)
-	*(.eh_frame);
-}


From gerrit at coreboot.org  Wed Sep  9 03:07:13 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:07:13 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521

-gerrit

commit 19fcda4d13070dbe6af69c3083f0321439bb4b27
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 ++++----
 src/arch/x86/car.ld       | 51 ++++++++++++++++++++++++++++++++++++++++
 src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++
 src/arch/x86/ramstage.ld  |  7 ------
 src/arch/x86/romstage.ld  | 59 -----------------------------------------------
 5 files changed, 98 insertions(+), 71 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 0315798..788d7c7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -294,11 +294,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
new file mode 100644
index 0000000..c30c802
--- /dev/null
+++ b/src/arch/x86/car.ld
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file is included inside a SECTIONS block */
+. = CONFIG_DCACHE_RAM_BASE;
+.car.data . (NOLOAD) : {
+	_car_data_start = .;
+#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
+	TIMESTAMP(., 0x100)
+#endif
+	*(.car.global_data);
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_car_data_end = .;
+
+	PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
+}
+
+/* Global variables are not allowed in romstage
+ * This section is checked during stage creation to ensure
+ * that there are no global variables present
+ */
+
+. = 0xffffff00;
+.illegal_globals . : {
+	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+}
+
+_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
new file mode 100644
index 0000000..43c5229
--- /dev/null
+++ b/src/arch/x86/memlayout.ld
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
deleted file mode 100644
index 0d329db..0000000
--- a/src/arch/x86/ramstage.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
deleted file mode 100644
index d6d1b9c..0000000
--- a/src/arch/x86/romstage.ld
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		_car_data_start = .;
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		TIMESTAMP(., 0x100)
-#endif
-		*(.car.global_data);
-		. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
-		_car_data_end = .;
-
-		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
-	}
-
-	/* Global variables are not allowed in romstage
-	 * This section is checked during stage creation to ensure
-	 * that there are no global variables present
-	 */
-
-	. = 0xffffff00;
-	.illegal_globals . : {
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-	}
-
-	_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}


From gerrit at coreboot.org  Wed Sep  9 03:07:23 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:07:23 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517

-gerrit

commit 95666734303e254edc530b917d69c989a6240d5a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                          |   3 +
 src/arch/arm64/include/arch/header.ld |  10 +++-
 src/arch/arm64/stage_entry.S          |   4 +-
 src/arch/x86/c_start.S                |   2 -
 src/arch/x86/include/arch/header.ld   |   2 +-
 src/cpu/x86/Makefile.inc              |   4 +-
 src/cpu/x86/sipi_vector.S             |  10 ++--
 src/cpu/x86/smm/smm_stub.S            |   6 +-
 src/include/memlayout.h               |   4 +-
 src/include/rmodule.h                 |   4 +-
 src/include/rules.h                   |  16 ++++++
 src/lib/program.ld                    |  15 +++--
 src/lib/rmodule.ld                    | 101 ++--------------------------------
 util/cbfstool/rmodule.c               |   8 +--
 14 files changed, 64 insertions(+), 125 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index be6021b..4add195 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v
 # Add dynamic classes for rmodules
 $(foreach supported_arch,$(ARCH_SUPPORTED), \
 	    $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch))))
+# Provide a macro to determine environment for free standing rmodules.
+$(foreach supported_arch,$(ARCH_SUPPORTED), \
+	$(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__))
 
 #######################################################################
 # Helper functions for math and various file placement matters.
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index fa8fdfa..55b4cb7 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 /* We use ELF as output format. So that we can debug the code in some form. */
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
@@ -26,7 +28,13 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 TARGET(binary)
 #endif
+
+/* secmon uses rmodules */
+#if ENV_RMODULE
+ENTRY(_start)
+#else
 ENTRY(stage_entry)
+#endif
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index 4e15dbb..dbc6cad 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment)
 	2002:
 .endm
 
-ENTRY(__rmodule_entry)
+ENTRY(_start)
 	split_bsp_path
 	/* Save the arguments to secmon in x25 */
 	mov	x25, x0
 	b	arm64_c_environment
-ENDPROC(__rmodule_entry)
+ENDPROC(_start)
 
 /*
  * Setup SCTLR so that:
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 582966b..ad4589a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,8 +23,6 @@ thread_stacks:
 	.code32
 #endif
 	.globl _start
-	.globl __rmodule_entry
-__rmodule_entry:
 _start:
 	cli
 	lgdt	%cs:gdtaddr
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 55547ad..0262c92 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,7 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 ENTRY(_start)
 #elif ENV_ROMSTAGE
 ENTRY(protected_start)
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9ec0768..e9394b2 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o
 	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64))
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
 endif
 
 $(SIPI_BIN): $(SIPI_RMOD)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c7b1097..0887b0a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -56,10 +56,8 @@ ap_count:
 
 .text
 .code16
-.global ap_start
-.global __rmodule_entry
-__rmodule_entry:
-ap_start:
+.global _start
+_start:
 	cli
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
@@ -74,9 +72,9 @@ ap_start:
 
 	/* The gdtaddr needs to be releative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
-	 * rmodule so ap_start can be used as a proxy for the load address. */
+	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
-	sub	$(ap_start), %ebx
+	sub	$(_start), %ebx
 
 	data32 lgdt (%ebx)
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 5fbec28..ead597c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -59,10 +59,8 @@ fallback_stack_top:
 
 .text
 .code16
-.global smm_handler_start
-.global __rmodule_entry
-__rmodule_entry:
-smm_handler_start:
+.global _start
+_start:
 	movl	$(smm_relocate_gdt), %ebx
 	data32	lgdt (%ebx)
 
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index f67753c..09be615 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -43,9 +43,9 @@
 #define ARCH_STAGE_HAS_BSS_SECTION 1
 #endif
 
-/* Default is that currently ramstage and smm only has a heap. */
+/* Default is that currently ramstage, smm, and rmodules have a heap. */
 #ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
 #endif
 
 #define STR(x) #x
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 719c6a6..03cdf76 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -73,9 +73,9 @@ struct rmodule {
 };
 
 #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
-/* Rmodules have an entry point of named __rmodule_entry. */
+/* Rmodules have an entry point of named _start. */
 #define RMODULE_ENTRY(entry_) \
-	void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_))))
+	void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
 #else
 #define RMODULE_ENTRY(entry_)
 #endif
diff --git a/src/include/rules.h b/src/include/rules.h
index 607d7fc..7523347 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -30,6 +30,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__ROMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -38,6 +39,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SMM__)
 #define ENV_BOOTBLOCK 0
@@ -46,6 +48,7 @@
 #define ENV_SMM 1
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__SECMON__)
 #define ENV_BOOTBLOCK 0
@@ -54,6 +57,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 1
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 
 #elif defined(__VERSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -62,6 +66,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 1
+#define ENV_RMODULE 0
 
 #elif defined(__RAMSTAGE__)
 #define ENV_BOOTBLOCK 0
@@ -70,6 +75,16 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+
+#elif defined(__RMODULE__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 1
 
 #else
 /*
@@ -84,6 +99,7 @@
 #define ENV_SMM 0
 #define ENV_SECMON 0
 #define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
 #endif
 
 /* For romstage and ramstage always build with simple device model, ie.
diff --git a/src/lib/program.ld b/src/lib/program.ld
index cf011e9..d6e3e54 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -38,14 +38,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_cbmem_init_hooks = .;
 	KEEP(*(.rodata.cbmem_init_hooks));
 	_ecbmem_init_hooks = .;
 #endif
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE || ENV_RMODULE
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_pci_drivers = .;
 	KEEP(*(.rodata.pci_driver));
@@ -79,13 +79,20 @@
 .data : {
 	. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
 	_data = .;
+
+#if ENV_RMODULE
+	_rmodule_params = .;
+	KEEP(*(.module_parameters));
+	_ermodule_params = .;
+#endif
+
 	*(.data);
 	*(.data.*);
 
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE
+#elif ENV_RAMSTAGE || ENV_RMODULE
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bs_init_begin = .;
 	KEEP(*(.bs_init));
@@ -116,7 +123,7 @@
 .heap : {
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_heap = .;
-	. += CONFIG_HEAP_SIZE;
+	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_eheap = .;
 }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index f5d5f06..340fe7a 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -12,103 +12,14 @@
  * won't be a consistent mapping between the flat blob and the loaded program.
  */
 
-BASE_ADDRESS = 0x00000;
-
-ENTRY(__rmodule_entry);
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = BASE_ADDRESS;
-
-	.payload :  {
-		/* C code of the module. */
-		_program = .;
-		*(.text._start);
-		*(.text.stage_entry);
-		*(.text);
-		*(.text.*);
-		/* C read-only data. */
-		. = ALIGN(16);
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-		__CTOR_LIST__ = .;
-		*(.ctors);
-		LONG(0);
-		LONG(0);
-		__CTOR_END__ = .;
-#endif
-
-		/* The driver sections are to allow linking coreboot's
-		 * ramstage with the rmodule linker. Any changes made in
-		 * ramstage.ld should be made here as well. */
-		. = ALIGN(8);
-		_pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		_epci_drivers = . ;
-		. = ALIGN(8);
-		_cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		_ecpu_drivers = . ;
-		. = ALIGN(8);
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		LONG(0);
-		_bs_init_end = .;
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-
-		. = ALIGN(8);
-
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(8);
-
-		/* The parameters section can be used to pass parameters
-		 * to a module, however there has to be an prior agreement
-		 * on how to interpret the parameters. */
-		_module_params_begin = .;
-		KEEP(*(.module_parameters));
-		_module_params_end = .;
-		. = ALIGN(8);
-
-		/* Data section. */
-		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
-		_sdata = .;
-		*(.data);
-		*(.data.*);
-		. = ALIGN(8);
-		_edata = .;
-
-		. = ALIGN(8);
-	}
-
-	.bss (NOLOAD) : {
-		/* C uninitialized data of the module. */
-		_bss = .;
-		*(.bss);
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON);
-		. = ALIGN(8);
-		_ebss = .;
-
-		/*
-		 * Place the heap after BSS. The heap size is passed in by
-		 * by way of ld --defsym=__heap_size=<>
-		 */
-		_heap = .;
-		. = . + __heap_size;
-		_eheap = .;
-		_eprogram = .;
-	}
+	SET_COUNTER(rmodule, 0x00000000)
 
-	/DISCARD/ : {
-		/* Drop unnecessary sections. */
-		*(.eh_frame);
-		*(.note);
-		*(.note.*);
-	}
+	/* program.ld is directly included because there's no one particular
+	 * class that rmodule is used on. */
+	#include <lib/program.ld>
 }
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index f93f4f6..c35eff7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx)
 		break;
 	}
 
-	if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin,
+	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
 	                 nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end,
+	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
 	                 nsyms, strtab))
 		return -1;
 
@@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
 		return -1;
 
-	if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab))
-		return -1;
+	/* Honor the entry point within the ELF header. */
+	ctx->entry = ehdr->e_entry;
 
 	/* Link address is the virtual address of the program segment. */
 	ctx->link_addr = ctx->phdr->p_vaddr;


From gerrit at coreboot.org  Wed Sep  9 03:07:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:07:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: add and
	use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <I41fbded54055455889b297b9e8738db4dda0aad0+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522

-gerrit

commit ddc627566aa31af5a8fd6ec8e5272d6ce5cb68de
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 Makefile.inc                 | 2 ++
 src/arch/arm/Makefile.inc    | 8 ++++----
 src/arch/arm64/Makefile.inc  | 8 ++++----
 src/arch/mips/Makefile.inc   | 6 +++---
 src/arch/riscv/Makefile.inc  | 6 +++---
 src/arch/x86/Makefile.inc    | 6 +++---
 src/cpu/x86/smm/Makefile.inc | 2 +-
 src/lib/Makefile.inc         | 4 ++--
 toolchain.inc                | 1 +
 9 files changed, 23 insertions(+), 20 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 4add195..c0bedda 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -278,6 +278,8 @@ CFLAGS_common += -Wstrict-aliasing -Wshadow
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -ffunction-sections -fdata-sections
 
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
+
 ifeq ($(CONFIG_COMPILER_GCC),y)
 # cf. commit f69a99db (coreboot: x86: enable gc-sections)
 CFLAGS_common += -Wno-unused-but-set-variable
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 7a4409e..82ce8b3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -63,7 +63,7 @@ bootblock-y += clock.c
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM
 
@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM
 
@@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index a625c7a..e1c84a9 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -73,7 +73,7 @@ bootblock-y += memmove.S
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
 
 endif # CONFIG_ARCH_BOOTBLOCK_ARM64
 
@@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
 
 $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+	$(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
 
 verstage-y += boot.c
 verstage-y += div0.c
@@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
 
 endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
@@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
 
 # Build ARM Trusted Firmware (BL31)
 
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index e3aff0c..fab8a05 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
 
 endif # CONFIG_ARCH_BOOTBLOCK_MIPS
 
@@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
 
 endif # CONFIG_ARCH_ROMSTAGE_MIPS
 
@@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
 
 endif # CONFIG_ARCH_RAMSTAGE_MIPS
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0f3eb0f..5233faa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,7 +40,7 @@ bootblock-y += \
 
 $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
+	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
 		-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
 		$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
 
@@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
 
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
@@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
 
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 788d7c7..3d1d214 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -180,7 +180,7 @@ endif
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 
 $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
 $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
@@ -298,7 +298,7 @@ ramstage-y += memlayout.ld
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 239689e..7b4ad59 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
 else # CONFIG_SMM_TSEG
 
 $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
-	$(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
 	$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index d8cd1d8..a89f7d4 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
 ramstage-y += rmodule.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
 
-RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
+RMODULE_LDFLAGS  := -z defs -Bsymbolic
 
 # rmodule_link_rules is a function that should be called with:
 # (1) the object name to link
@@ -216,7 +216,7 @@ RMODULE_LDFLAGS  := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
 # rmdoule is named $(1).rmod
 define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
-	$$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
+	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
 
 $(strip $(1)).rmod: $(strip $(1))
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..5fd5a77 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -122,6 +122,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
 CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
 COMPILER_RT_$(1) := $$(COMPILER_RT_$(2))
 COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2))
+LDFLAGS_$(1) = $$(LDFLAGS_common) $$(LDFLAGS_$(2))
 endef
 
 # define_class: Allows defining any program as dynamic class and compiler tool


From gerrit at coreboot.org  Wed Sep  9 03:07:58 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:07:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523

-gerrit

commit 183e19a00601e6838dbb66b3087d1778ed56cee3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 util/cbfstool/rmodule.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index c35eff7..1f41d17 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx)
 
 static int
 populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
-             int nsyms, const char *strtab)
+             int nsyms, const char *strtab, int optional)
 {
 	int i;
 	Elf64_Sym *syms;
@@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 		*addr = syms[i].st_value;
 		return 0;
 	}
+
+	if (optional) {
+		DEBUG("optional symbol '%s' not found.\n", sym_name);
+		*addr = 0;
+		return 0;
+	}
+
 	ERROR("symbol '%s' not found.\n", sym_name);
 	return -1;
 }
@@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx)
 	}
 
 	if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
 	if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end,
-	                 nsyms, strtab))
+	                 nsyms, strtab, 1))
 		return -1;
 
-	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab))
+	if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0))
 		return -1;
 
-	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab))
+	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
 	/* Honor the entry point within the ELF header. */


From gerrit at coreboot.org  Wed Sep  9 03:08:13 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 03:08:13 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524

-gerrit

commit c2c61e6ac524a6ec51eb3e1923e1875d25cd536b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/Makefile.inc | 10 +---------
 src/lib/Makefile.inc      |  9 ++++++---
 src/lib/program.ld        |  6 +++---
 3 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3d1d214..68ed810 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -282,17 +282,11 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32))
-else
-$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64))
-endif
-
 # The rmodule_link defintion creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
-else
+endif
 
 ramstage-y += memlayout.ld
 
@@ -300,8 +294,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
-endif
-
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index a89f7d4..f4d8c2c 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -218,9 +218,12 @@ define rmodule_link
 $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
 	$$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group
 	$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
-
-$(strip $(1)).rmod: $(strip $(1))
-	$$(RMODTOOL) -i $$^ -o $$@
 endef
 
 endif
+
+$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
+
+$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
+	$(RMODTOOL) -i $< -o $@
diff --git a/src/lib/program.ld b/src/lib/program.ld
index d6e3e54..9f28d65 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -38,14 +38,14 @@
 	*(.text);
 	*(.text.*);
 
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_cbmem_init_hooks = .;
 	KEEP(*(.rodata.cbmem_init_hooks));
 	_ecbmem_init_hooks = .;
 #endif
 
-#if ENV_RAMSTAGE || ENV_RMODULE
+#if ENV_RAMSTAGE
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_pci_drivers = .;
 	KEEP(*(.rodata.pci_driver));
@@ -92,7 +92,7 @@
 #ifdef __PRE_RAM__
 	PROVIDE(_preram_cbmem_console = .);
 	PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
-#elif ENV_RAMSTAGE || ENV_RMODULE
+#elif ENV_RAMSTAGE
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bs_init_begin = .;
 	KEEP(*(.bs_init));


From gerrit at coreboot.org  Wed Sep  9 03:23:01 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 03:23:01 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86:
	bootblock: remove linking and program flow from build system
References: <Ida4571cbe6eed65e77ade98b8d9ad056353c53f9+0@gerrit.coreboot.org>
Message-ID: <E1ZZVyP-0005oW-Je@mail.coreboot.org>

the following patch was just integrated into master:
commit 3953e3947d375c0552abc45d47a120aaee67d763
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 00:41:29 2015 -0500

    x86: bootblock: remove linking and program flow from build system
    
    The build system was previously determining the flow
    and linking scripts bootblock code by the order of files
    added to the bootblock_inc bootblock-y variables.Those
    files were then concatenated together and built by a myriad of
    make rules.
    
    Now bootblock.S and bootblock.ld is added so that bootblock
    can be built and linked using the default build rules.
    CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
    chipset code to place include files in the path of the bootblock
    program -- a replacement for the chipset_bootblock_inc
    make variable.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards.
    
    Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11495
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11495 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 03:23:13 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 03:23:13 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: don't
	create MAINBOARDDIR/romstage.inc for !ROMCC boards
References: <I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7+0@gerrit.coreboot.org>
Message-ID: <E1ZZVyb-0005qj-UY@mail.coreboot.org>

the following patch was just integrated into master:
commit 85982cd4a2ed31a441eb96b247ae4d19091b1c1c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:01:17 2015 -0500

    x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
    
    Previously, the x86 romstage build process was unconditionally
    creating a romstage.inc and adding it to crt0s. This step is
    inherently not necessary in the !ROMCC case becaue the romstage.inc
    was created by the compiler outputting assembler. That means
    MAINBOARDDIR/romstage.c is truly a C environment that requires
    some sort of assembler stub to call into (cache_as_ram.inc from
    the chipset dirs). Therefore, remove this processing. The result
    is that MAINBOARDDIR/romstage.c can use the normal build steps
    in creating an object and linking. The layout of romstage.elf
    will change but that's only from a symbol perspective.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built multitude of boards. Compared readelf -e output.
    
    Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11503
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11503 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 03:23:36 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 03:23:36 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: add
	romstage.S to bind program flow and ordering
References: <Ib1168f9541eaf96651c52d03dc0f60e2489a77bd+0@gerrit.coreboot.org>
Message-ID: <E1ZZVyy-0005tD-9w@mail.coreboot.org>

the following patch was just integrated into master:
commit e581b067ca968ce4dae818d8bf09081c1eb6e11a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 11:29:28 2015 -0500

    x86: add romstage.S to bind program flow and ordering
    
    The build system was previously determining the flow
    of the romstage code by the order of files added to
    the crt0s make variable. Those files were then
    concatenated together, and the resulting file was added
    to the build dependencies for romstage proper.
    
    Now romstage.S is added that can be built using
    the default object file rules. The generated
    romstage.inc is pulled in by way of an #include in the
    newly added romstage.S.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built vortex, rambi, and some asus boards. compared
         readelf -e output.
    
    Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11504
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11504 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 03:23:58 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 03:23:58 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: remove
	unused sections from romstage.ld
References: <Id17cf95c943103de006c5f3f21a625838ab49929+0@gerrit.coreboot.org>
Message-ID: <E1ZZVzL-0005vn-70@mail.coreboot.org>

the following patch was just integrated into master:
commit d2cd7f6c6a5f45f3a731c45fe7553bf166bd9ae3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 14:39:39 2015 -0500

    x86: remove unused sections from romstage.ld
    
    Now that the only source of ELF sections for romstage are
    from directly included .inc files or ROMCC generated inc
    files the subsection globs can be removed. i.e. Remove
    .rom.data.* and .rom.text.* listings. Lastly, put the
    .rom.data section directly after the .rom.text. They
    are by definition read-only and they are generated from
    the same place.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
         only .rom.text .rom.data sections exist.
    
    Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11505
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11505 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 09:17:28 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 9 Sep 2015 09:17:28 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: genbuild_h: Add
	Mac OS to case of "data -r"
References: <I2a43a1b1749da207b7a23b8eb252c13605121533+0@gerrit.coreboot.org>
Message-ID: <I2a43a1b1749da207b7a23b8eb252c13605121533+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11599

-gerrit

commit 25e7c1bbbb77f47ae20fd32c253e3992259f74e0
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Sep 9 05:16:40 2015 -0400

    genbuild_h: Add Mac OS to case of "data -r"
    
    Change-Id: I2a43a1b1749da207b7a23b8eb252c13605121533
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/genbuild_h/genbuild_h.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh
index a3e4453..2a009c1 100755
--- a/util/genbuild_h/genbuild_h.sh
+++ b/util/genbuild_h/genbuild_h.sh
@@ -40,7 +40,7 @@ fi
 
 our_date() {
 case $(uname) in
-NetBSD|OpenBSD|DragonFly|FreeBSD)
+NetBSD|OpenBSD|DragonFly|FreeBSD|Darwin)
 	date -r $1 $2
 	;;
 *)


From gerrit at coreboot.org  Wed Sep  9 09:53:05 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 9 Sep 2015 09:53:05 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Makefile:
	Replace the way to test if a string is empty
References: <Ie4b8fe1fb26df092e2985937251a49feadc61eb0+0@gerrit.coreboot.org>
Message-ID: <Ie4b8fe1fb26df092e2985937251a49feadc61eb0+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11600

-gerrit

commit 7d9a5b2e34a59c836690037b68a90a940005dec5
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Sep 9 05:27:53 2015 -0400

    Makefile: Replace the way to test if a string is empty
    
    The output of command below,
    has different result on MacOS, which output 0.
    
    It is misleading to search an empty string in a empty string.
    We just test if the string is empty.
    
    Change-Id: Ie4b8fe1fb26df092e2985937251a49feadc61eb0
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/arch/x86/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3a8d8d5..f7fa387 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -209,7 +209,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
-	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
+	if [ -n "`$(NM_romstage) $(objcbfs)/romstage_null.offenders 2>/dev/null`" ]; then \
 		echo "Forbidden global variables in romstage:"; \
 		$(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \
 		else true; fi


From gerrit at coreboot.org  Wed Sep  9 09:53:07 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 9 Sep 2015 09:53:07 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: pi/Makefile:
	Remove cp option '-u'
References: <I60cf57991275db0e075278f77a95ca5b8b941c7f+0@gerrit.coreboot.org>
Message-ID: <I60cf57991275db0e075278f77a95ca5b8b941c7f+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11601

-gerrit

commit 299cb08773e8e18f441172eeb9861956392b6879
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Sep 9 05:42:52 2015 -0400

    pi/Makefile: Remove cp option '-u'
    
    Most of the revision of cp don't take -u.
    
    Change-Id: I60cf57991275db0e075278f77a95ca5b8b941c7f
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/vendorcode/amd/pi/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..a296c75 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -83,7 +83,7 @@ define create_agesa_cp_template
 $(agesa_src_path)/$(notdir $2): $2 $(agesa_src_path)
 	@printf "    AGESA      Copying $$(notdir $2) => $$(@D)\n"
 	if [ ! -r $(agesa_src_path)/$(notdir $2) ]; then                   \
-		cp -uf $2 $$(@D);                                                     \
+		cp -f $2 $$(@D);                                                     \
 	fi
 
 $(agesa_obj_path)/$1.libagesa.o: $(agesa_src_path)/$(notdir $2) $(obj)/config.h $(src)/include/kconfig.h $(agesa_obj_path)


From gerrit at coreboot.org  Wed Sep  9 09:53:09 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 9 Sep 2015 09:53:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Dot gitignore:
	Fix some names of ignore files
References: <I6c752f08aa545d8878fddd373e5acbfade317ad5+0@gerrit.coreboot.org>
Message-ID: <I6c752f08aa545d8878fddd373e5acbfade317ad5+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11602

-gerrit

commit 321a09c13e7ba7e68f6034cd9ddbd1649a5aa390
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Sep 9 05:52:20 2015 -0400

    Dot gitignore: Fix some names of ignore files
    
    Change-Id: I6c752f08aa545d8878fddd373e5acbfade317ad5
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 .gitignore | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/.gitignore b/.gitignore
index 770a62d..4eaf426 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,15 +10,17 @@ payloads/external/GRUB2/grub2/
 payloads/external/SeaBIOS/seabios/
 util/crossgcc/acpica-unix-*/
 util/crossgcc/binutils-*/
-util/crossgcc/build-*binutils/
-util/crossgcc/build-*expat/
-util/crossgcc/build-*gcc/
-util/crossgcc/build-*gdb/
-util/crossgcc/build-*gmp/
-util/crossgcc/build-*libelf/
-util/crossgcc/build-*mpc/
-util/crossgcc/build-*mpfr/
-util/crossgcc/build-*python/
+util/crossgcc/build-*BINUTILS/
+util/crossgcc/build-*EXPAT/
+util/crossgcc/build-*GCC/
+util/crossgcc/build-*GDB/
+util/crossgcc/build-*GMP/
+util/crossgcc/build-*LIBELF/
+util/crossgcc/build-*MPC/
+util/crossgcc/build-*MPFR/
+util/crossgcc/build-*PYTHON/
+util/crossgcc/build-*LVM/
+util/crossgcc/build-*IASL/
 util/crossgcc/expat-*/
 util/crossgcc/gcc-*/
 util/crossgcc/gdb-*/
@@ -28,6 +30,7 @@ util/crossgcc/mingwrt-*/
 util/crossgcc/mpc-*/
 util/crossgcc/mpfr-*/
 util/crossgcc/Python-*/
+util/crossgcc/*.src/
 util/crossgcc/tarballs/
 util/crossgcc/w32api-*/
 util/crossgcc/xgcc/


From gerrit at coreboot.org  Wed Sep  9 11:08:05 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Wed, 9 Sep 2015 11:08:05 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: libpayload: Add
	missing autoconf dependency
References: <I9f0dd8adbc3aa434a18cb4815b1ccbd1f6e7847b+0@gerrit.coreboot.org>
Message-ID: <I9f0dd8adbc3aa434a18cb4815b1ccbd1f6e7847b+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11603

-gerrit

commit 731aa6bfc05bcd975b1a2948da8daac1bdbc5829
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed Sep 9 13:02:51 2015 +0200

    libpayload: Add missing autoconf dependency
    
    With new version of kconfig we have to trigger [silent]oldconfig each
    time .config changed. We missed that, because config.h had no dependen-
    cies.
    
    Change-Id: I9f0dd8adbc3aa434a18cb4815b1ccbd1f6e7847b
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 payloads/libpayload/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
index ba883cc..1b42e29 100644
--- a/payloads/libpayload/Makefile
+++ b/payloads/libpayload/Makefile
@@ -196,7 +196,7 @@ endif
 # must come rather early
 .SECONDEXPANSION:
 
-$(obj)/config.h:
+$(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG)
 	$(MAKE) oldconfig
 
 # Add a new class of source/object files to the build system


From gerrit at coreboot.org  Wed Sep  9 11:36:35 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Wed, 9 Sep 2015 11:36:35 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: libpayload: Fix
	merge of PL011 UART support
References: <Ifea8113fbc59e0463eaedb86b976f54ec11113a9+0@gerrit.coreboot.org>
Message-ID: <Ifea8113fbc59e0463eaedb86b976f54ec11113a9+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11604

-gerrit

commit 594ac89684b63b3b2591fc558746d14c8557c535
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed Sep 9 13:27:09 2015 +0200

    libpayload: Fix merge of PL011 UART support
    
    Wished I haven't seen that. Git saw the conflict (file was gone), both
    committer and reviewer thought it would be a good idea to re-add it as
    dead code (see 558e9b5).
    
    Change-Id: Ifea8113fbc59e0463eaedb86b976f54ec11113a9
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 payloads/libpayload/drivers/serial.c      | 250 ------------------------------
 payloads/libpayload/drivers/serial/8250.c |   4 +
 2 files changed, 4 insertions(+), 250 deletions(-)

diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c
deleted file mode 100644
index a239ecd..0000000
--- a/payloads/libpayload/drivers/serial.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * This file is part of the libpayload project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2008 Ulf Jordan <jordan at chalmers.se>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload-config.h>
-#include <libpayload.h>
-
-#define IOBASE lib_sysinfo.serial->baseaddr
-#define MEMBASE (phys_to_virt(IOBASE))
-
-static int serial_hardware_is_present = 0;
-static int serial_is_mem_mapped = 0;
-
-static uint8_t serial_read_reg(int offset)
-{
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
-	if (!serial_is_mem_mapped)
-		return inb(IOBASE + offset);
-	else
-#endif
-		return readb(MEMBASE + offset);
-}
-
-static void serial_write_reg(uint8_t val, int offset)
-{
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
-	if (!serial_is_mem_mapped)
-		outb(val, IOBASE + offset);
-	else
-#endif
-		writeb(val, MEMBASE + offset);
-}
-
-#if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED)
-static void serial_hardware_init(int speed, int word_bits,
-				 int parity, int stop_bits)
-{
-	unsigned char reg;
-
-#ifndef PL011_SERIAL_CONSOLE
-	/* Disable interrupts. */
-	serial_write_reg(0, 0x01);
-
-	/* Assert RTS and DTR. */
-	serial_write_reg(3, 0x04);
-
-	/* Set the divisor latch. */
-	reg = serial_read_reg(0x03);
-	serial_write_reg(reg | 0x80, 0x03);
-
-	/* Write the divisor. */
-	uint16_t divisor = 115200 / speed;
-	serial_write_reg(divisor & 0xFF, 0x00);
-	serial_write_reg(divisor >> 8, 0x01);
-
-	/* Restore the previous value of the divisor.
-	 * And set 8 bits per character */
-	serial_write_reg((reg & ~0x80) | 3, 0x03);
-#endif
-}
-#endif
-
-static struct console_input_driver consin = {
-	.havekey = &serial_havechar,
-	.getchar = &serial_getchar
-};
-
-static struct console_output_driver consout = {
-	.putchar = &serial_putchar
-};
-
-void serial_init(void)
-{
-	if (!lib_sysinfo.serial)
-		return;
-
-	serial_is_mem_mapped =
-		(lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED);
-
-	if (!serial_is_mem_mapped) {
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
-		if ((inb(IOBASE + 0x05) == 0xFF) &&
-				(inb(IOBASE + 0x06) == 0xFF)) {
-			return;
-		}
-#else
-		printf("IO space mapped serial not supported.");
-		return;
-#endif
-	}
-
-
-	serial_hardware_is_present = 1;
-
-#if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED)
-	serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1);
-#endif
-}
-
-void serial_console_init(void)
-{
-	if (!lib_sysinfo.serial)
-		return;
-
-	serial_init();
-
-	console_add_input_driver(&consin);
-	console_add_output_driver(&consout);
-}
-
-void serial_putchar(unsigned int c)
-{
-	if (!serial_hardware_is_present)
-		return;
-#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE)
-	while ((serial_read_reg(0x05) & 0x20) == 0) ;
-#endif
-	serial_write_reg(c, 0x00);
-}
-
-int serial_havechar(void)
-{
-	if (!serial_hardware_is_present)
-		return 0;
-	return serial_read_reg(0x05) & 0x01;
-}
-
-int serial_getchar(void)
-{
-	if (!serial_hardware_is_present)
-		return -1;
-	while (!serial_havechar()) ;
-	return serial_read_reg(0x00);
-}
-
-/*  These are thinly veiled vt100 functions used by curses */
-
-#define VT100_CLEAR       "\e[H\e[J"
-/* These defines will fail if you use bold and reverse at the same time.
- * Switching off one of them will switch off both. tinycurses knows about
- * this and does the right thing.
- */
-#define VT100_SBOLD       "\e[1m"
-#define VT100_EBOLD       "\e[m"
-#define VT100_SREVERSE    "\e[7m"
-#define VT100_EREVERSE    "\e[m"
-#define VT100_CURSOR_ADDR "\e[%d;%dH"
-#define VT100_CURSOR_ON   "\e[?25h"
-#define VT100_CURSOR_OFF  "\e[?25l"
-/* The following smacs/rmacs are actually for xterm; a real vt100 has
-   enacs=\E(B\E)0, smacs=^N, rmacs=^O.  */
-#define VT100_SMACS       "\e(0"
-#define VT100_RMACS       "\e(B"
-/* A vt100 doesn't do color, setaf/setab below are from xterm-color. */
-#define VT100_SET_COLOR   "\e[3%d;4%dm"
-
-static void serial_putcmd(const char *str)
-{
-	while (*str)
-		serial_putchar(*(str++));
-}
-
-void serial_clear(void)
-{
-	serial_putcmd(VT100_CLEAR);
-}
-
-void serial_start_bold(void)
-{
-	serial_putcmd(VT100_SBOLD);
-}
-
-void serial_end_bold(void)
-{
-	serial_putcmd(VT100_EBOLD);
-}
-
-void serial_start_reverse(void)
-{
-	serial_putcmd(VT100_SREVERSE);
-}
-
-void serial_end_reverse(void)
-{
-	serial_putcmd(VT100_EREVERSE);
-}
-
-void serial_start_altcharset(void)
-{
-	serial_putcmd(VT100_SMACS);
-}
-
-void serial_end_altcharset(void)
-{
-	serial_putcmd(VT100_RMACS);
-}
-
-/**
- * Set the foreground and background colors on the serial console.
- *
- * @param fg Foreground color number.
- * @param bg Background color number.
- */
-void serial_set_color(short fg, short bg)
-{
-	char buffer[32];
-	snprintf(buffer, sizeof(buffer), VT100_SET_COLOR, fg, bg);
-	serial_putcmd(buffer);
-}
-
-void serial_set_cursor(int y, int x)
-{
-	char buffer[32];
-	snprintf(buffer, sizeof(buffer), VT100_CURSOR_ADDR, y + 1, x + 1);
-	serial_putcmd(buffer);
-}
-
-void serial_cursor_enable(int state)
-{
-	if (state)
-		serial_putcmd(VT100_CURSOR_ON);
-	else
-		serial_putcmd(VT100_CURSOR_OFF);
-}
diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c
index e9550f3..7fe9920 100644
--- a/payloads/libpayload/drivers/serial/8250.c
+++ b/payloads/libpayload/drivers/serial/8250.c
@@ -67,6 +67,7 @@ static void serial_hardware_init(int speed, int word_bits,
 {
 	unsigned char reg;
 
+#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE)
 	/* Disable interrupts. */
 	serial_write_reg(0, 0x01);
 
@@ -85,6 +86,7 @@ static void serial_hardware_init(int speed, int word_bits,
 	/* Restore the previous value of the divisor.
 	 * And set 8 bits per character */
 	serial_write_reg((reg & ~0x80) | 3, 0x03);
+#endif
 }
 #endif
 
@@ -139,7 +141,9 @@ void serial_putchar(unsigned int c)
 {
 	if (!serial_hardware_is_present)
 		return;
+#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE)
 	while ((serial_read_reg(0x05) & 0x20) == 0) ;
+#endif
 	serial_write_reg(c, 0x00);
 	if (c == '\n')
 		serial_putchar('\r');


From gerrit at coreboot.org  Wed Sep  9 13:21:37 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Wed, 9 Sep 2015 13:21:37 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload: Fix
	merge of PL011 UART support
References: <Ifea8113fbc59e0463eaedb86b976f54ec11113a9+0@gerrit.coreboot.org>
Message-ID: <Ifea8113fbc59e0463eaedb86b976f54ec11113a9+2@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11604

-gerrit

commit c31fd165e902137c4599169d3fc86303cd8919d1
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed Sep 9 13:27:09 2015 +0200

    libpayload: Fix merge of PL011 UART support
    
    Wished I hadn't seen that. Git saw the conflict (file was gone), both
    committer and reviewer thought it would be a good idea to re-add it as
    dead code (see 558e9b5: libpayload: Add minimal support for PL011 UART).
    
    Change-Id: Ifea8113fbc59e0463eaedb86b976f54ec11113a9
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 payloads/libpayload/drivers/serial.c      | 250 ------------------------------
 payloads/libpayload/drivers/serial/8250.c |   4 +
 2 files changed, 4 insertions(+), 250 deletions(-)

diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c
deleted file mode 100644
index a239ecd..0000000
--- a/payloads/libpayload/drivers/serial.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * This file is part of the libpayload project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2008 Ulf Jordan <jordan at chalmers.se>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload-config.h>
-#include <libpayload.h>
-
-#define IOBASE lib_sysinfo.serial->baseaddr
-#define MEMBASE (phys_to_virt(IOBASE))
-
-static int serial_hardware_is_present = 0;
-static int serial_is_mem_mapped = 0;
-
-static uint8_t serial_read_reg(int offset)
-{
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
-	if (!serial_is_mem_mapped)
-		return inb(IOBASE + offset);
-	else
-#endif
-		return readb(MEMBASE + offset);
-}
-
-static void serial_write_reg(uint8_t val, int offset)
-{
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
-	if (!serial_is_mem_mapped)
-		outb(val, IOBASE + offset);
-	else
-#endif
-		writeb(val, MEMBASE + offset);
-}
-
-#if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED)
-static void serial_hardware_init(int speed, int word_bits,
-				 int parity, int stop_bits)
-{
-	unsigned char reg;
-
-#ifndef PL011_SERIAL_CONSOLE
-	/* Disable interrupts. */
-	serial_write_reg(0, 0x01);
-
-	/* Assert RTS and DTR. */
-	serial_write_reg(3, 0x04);
-
-	/* Set the divisor latch. */
-	reg = serial_read_reg(0x03);
-	serial_write_reg(reg | 0x80, 0x03);
-
-	/* Write the divisor. */
-	uint16_t divisor = 115200 / speed;
-	serial_write_reg(divisor & 0xFF, 0x00);
-	serial_write_reg(divisor >> 8, 0x01);
-
-	/* Restore the previous value of the divisor.
-	 * And set 8 bits per character */
-	serial_write_reg((reg & ~0x80) | 3, 0x03);
-#endif
-}
-#endif
-
-static struct console_input_driver consin = {
-	.havekey = &serial_havechar,
-	.getchar = &serial_getchar
-};
-
-static struct console_output_driver consout = {
-	.putchar = &serial_putchar
-};
-
-void serial_init(void)
-{
-	if (!lib_sysinfo.serial)
-		return;
-
-	serial_is_mem_mapped =
-		(lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED);
-
-	if (!serial_is_mem_mapped) {
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
-		if ((inb(IOBASE + 0x05) == 0xFF) &&
-				(inb(IOBASE + 0x06) == 0xFF)) {
-			return;
-		}
-#else
-		printf("IO space mapped serial not supported.");
-		return;
-#endif
-	}
-
-
-	serial_hardware_is_present = 1;
-
-#if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED)
-	serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1);
-#endif
-}
-
-void serial_console_init(void)
-{
-	if (!lib_sysinfo.serial)
-		return;
-
-	serial_init();
-
-	console_add_input_driver(&consin);
-	console_add_output_driver(&consout);
-}
-
-void serial_putchar(unsigned int c)
-{
-	if (!serial_hardware_is_present)
-		return;
-#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE)
-	while ((serial_read_reg(0x05) & 0x20) == 0) ;
-#endif
-	serial_write_reg(c, 0x00);
-}
-
-int serial_havechar(void)
-{
-	if (!serial_hardware_is_present)
-		return 0;
-	return serial_read_reg(0x05) & 0x01;
-}
-
-int serial_getchar(void)
-{
-	if (!serial_hardware_is_present)
-		return -1;
-	while (!serial_havechar()) ;
-	return serial_read_reg(0x00);
-}
-
-/*  These are thinly veiled vt100 functions used by curses */
-
-#define VT100_CLEAR       "\e[H\e[J"
-/* These defines will fail if you use bold and reverse at the same time.
- * Switching off one of them will switch off both. tinycurses knows about
- * this and does the right thing.
- */
-#define VT100_SBOLD       "\e[1m"
-#define VT100_EBOLD       "\e[m"
-#define VT100_SREVERSE    "\e[7m"
-#define VT100_EREVERSE    "\e[m"
-#define VT100_CURSOR_ADDR "\e[%d;%dH"
-#define VT100_CURSOR_ON   "\e[?25h"
-#define VT100_CURSOR_OFF  "\e[?25l"
-/* The following smacs/rmacs are actually for xterm; a real vt100 has
-   enacs=\E(B\E)0, smacs=^N, rmacs=^O.  */
-#define VT100_SMACS       "\e(0"
-#define VT100_RMACS       "\e(B"
-/* A vt100 doesn't do color, setaf/setab below are from xterm-color. */
-#define VT100_SET_COLOR   "\e[3%d;4%dm"
-
-static void serial_putcmd(const char *str)
-{
-	while (*str)
-		serial_putchar(*(str++));
-}
-
-void serial_clear(void)
-{
-	serial_putcmd(VT100_CLEAR);
-}
-
-void serial_start_bold(void)
-{
-	serial_putcmd(VT100_SBOLD);
-}
-
-void serial_end_bold(void)
-{
-	serial_putcmd(VT100_EBOLD);
-}
-
-void serial_start_reverse(void)
-{
-	serial_putcmd(VT100_SREVERSE);
-}
-
-void serial_end_reverse(void)
-{
-	serial_putcmd(VT100_EREVERSE);
-}
-
-void serial_start_altcharset(void)
-{
-	serial_putcmd(VT100_SMACS);
-}
-
-void serial_end_altcharset(void)
-{
-	serial_putcmd(VT100_RMACS);
-}
-
-/**
- * Set the foreground and background colors on the serial console.
- *
- * @param fg Foreground color number.
- * @param bg Background color number.
- */
-void serial_set_color(short fg, short bg)
-{
-	char buffer[32];
-	snprintf(buffer, sizeof(buffer), VT100_SET_COLOR, fg, bg);
-	serial_putcmd(buffer);
-}
-
-void serial_set_cursor(int y, int x)
-{
-	char buffer[32];
-	snprintf(buffer, sizeof(buffer), VT100_CURSOR_ADDR, y + 1, x + 1);
-	serial_putcmd(buffer);
-}
-
-void serial_cursor_enable(int state)
-{
-	if (state)
-		serial_putcmd(VT100_CURSOR_ON);
-	else
-		serial_putcmd(VT100_CURSOR_OFF);
-}
diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c
index e9550f3..7fe9920 100644
--- a/payloads/libpayload/drivers/serial/8250.c
+++ b/payloads/libpayload/drivers/serial/8250.c
@@ -67,6 +67,7 @@ static void serial_hardware_init(int speed, int word_bits,
 {
 	unsigned char reg;
 
+#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE)
 	/* Disable interrupts. */
 	serial_write_reg(0, 0x01);
 
@@ -85,6 +86,7 @@ static void serial_hardware_init(int speed, int word_bits,
 	/* Restore the previous value of the divisor.
 	 * And set 8 bits per character */
 	serial_write_reg((reg & ~0x80) | 3, 0x03);
+#endif
 }
 #endif
 
@@ -139,7 +141,9 @@ void serial_putchar(unsigned int c)
 {
 	if (!serial_hardware_is_present)
 		return;
+#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE)
 	while ((serial_read_reg(0x05) & 0x20) == 0) ;
+#endif
 	serial_write_reg(c, 0x00);
 	if (c == '\n')
 		serial_putchar('\r');


From gerrit at coreboot.org  Wed Sep  9 15:16:30 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 15:16:30 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMER
References: <I5caa60ca7ab9a24d25c184c85184f9492b453706+0@gerrit.coreboot.org>
Message-ID: <E1ZZh6s-0003qM-Sw@mail.coreboot.org>

the following patch was just integrated into master:
commit 0f045a69b806b9998523ffd799f69bf70bf716a5
Author: Martin Roth <martinroth at google.com>
Date:   Tue Aug 25 14:47:39 2015 -0600

    intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMER
    
    The LAPIC_MONOTONIC_TIMER symbol doesn't do anything in the code
    unless UDELAY_LAPIC is selected.  Since this chip uses UDELAY_TSC,
    LAPIC_MONOTONIC_TIMER generates a Kconfig warning and should be
    removed.
    
    Change-Id: I5caa60ca7ab9a24d25c184c85184f9492b453706
    Signed-off-by: Martin Roth <martinroth at google.com>
    Reviewed-on: http://review.coreboot.org/11342
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexander Couzens <lynxis at fe80.eu>


See http://review.coreboot.org/11342 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 16:47:51 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 16:47:51 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: drivers/pc80:
	Do not initialize PS2 keyboard by default
References: <I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4+0@gerrit.coreboot.org>
Message-ID: <E1ZZiXH-0002si-KP@mail.coreboot.org>

the following patch was just integrated into master:
commit 6aa8c5bc5850e0c3e0037742ea990d0ff74ea303
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Tue Mar 3 22:37:44 2015 -0600

    drivers/pc80: Do not initialize PS2 keyboard by default
    
    The most common payloads do not need this set, so optimize for the
    common case.
    
    Change-Id: I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/8599
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones at se-eng.com>


See http://review.coreboot.org/8599 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 18:45:23 2015
From: gerrit at coreboot.org (Julius Werner (jwerner@chromium.org))
Date: Wed, 9 Sep 2015 18:45:23 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload:
	Revive ffs()
References: <I4e3fc15816b778e640bceea0d89cd9624d271c2e+0@gerrit.coreboot.org>
Message-ID: <I4e3fc15816b778e640bceea0d89cd9624d271c2e+3@gerrit.coreboot.org>

Julius Werner (jwerner at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11591

-gerrit

commit 88c1be0ae8509c55ce490d08dcafdf4b7c4c2f0b
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Sep 8 17:14:08 2015 +0200

    libpayload: Revive ffs()
    
    Revive ffs() in a more fancy way (that is more likely to be accepted).
    We dropped it in
      7a8a4ab lib: Unify log2() and related functions
    but there is at least one user: flashrom.
    
    Change-Id: I4e3fc15816b778e640bceea0d89cd9624d271c2e
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
    Signed-off-by: Julius Werner <jwerner at chromium.org>
---
 payloads/libpayload/include/strings.h | 37 +++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/payloads/libpayload/include/strings.h b/payloads/libpayload/include/strings.h
new file mode 100644
index 0000000..e25a823
--- /dev/null
+++ b/payloads/libpayload/include/strings.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _STRINGS_H
+#define _STRINGS_H
+
+#include <libpayload.h>
+
+static inline int ffs(int i) { return __ffs(i) + 1; }
+
+#endif


From gerrit at coreboot.org  Wed Sep  9 19:34:18 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:34:18 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: rules.h: add
	fall through where no ENV_<STAGE> is set
References: <Ia9688886d445c961f4a448fc7bfcb28f691609db+0@gerrit.coreboot.org>
Message-ID: <E1ZZl8M-0003Zc-7h@mail.coreboot.org>

the following patch was just integrated into master:
commit cd96c5cf95e68280f0ff19831555930bbb705dca
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 16:28:15 2015 -0500

    rules.h: add fall through where no ENV_<STAGE> is set
    
    There are cases where rules.h can be pulled in, but the
    usage is not associated with a particular stage. For
    example, the cpu/ti/am335x build creates an opmap header.
    That is a case where there is no stage associated with
    the process. Therefore, provide a case of no ENV_>STAGE>
    being set.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11513
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11513 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:34:37 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:34:37 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: provide
	minimum alignment for romstage
References: <Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15+0@gerrit.coreboot.org>
Message-ID: <E1ZZl8f-0003dQ-Sb@mail.coreboot.org>

the following patch was just integrated into master:
commit 4b34909d099e395161b90c5528382450dc9937fc
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Sep 7 23:05:28 2015 -0500

    x86: provide minimum alignment for romstage
    
    The current way the XIP address of romstage is calculated is by
    doing a 'cbfstool locate' using a bin file of romstage linked
    at address 0. That address is then used for re-linking romstage at
    the address spit out by cbfstool. Currently, the linker actually
    sets minimum alignment on the text sections as 32 bytes, but it
    doesn't actually honor that value. Instead, provide a minimum
    alignment for romstage so as not to fight the linker.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built asus/kfsn4-dre. Confirmed ROMSTAGE_BASE == gdtptr.
    
    Change-Id: Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11588
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11588 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:34:46 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:34:46 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: linking: lay
	the groundwork for a unified linking approach
References: <I5d689bfa7e0e9aff3a148178515ef241b5f70661+0@gerrit.coreboot.org>
Message-ID: <E1ZZl8o-0003fO-BT@mail.coreboot.org>

the following patch was just integrated into master:
commit 4de29d48edb2c760332def9004989d6cdf002f02
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 3 22:49:36 2015 -0500

    linking: lay the groundwork for a unified linking approach
    
    Though coreboot started as x86 only, the current approach to x86
    linking is out of the norm with respect to other architectures.
    To start alleviating that the way ramstage is linked is partially
    unified. A new file, program.ld, was added to provide a common way
    to link stages by deferring to per-stage architectural overrides.
    The previous ramstage.ld is no longer required.
    
    Note that this change doesn't handle RELOCATABLE_RAMSTAGE
    because that is handled by rmodule.ld. Future convergence
    can be achieved, but for the time being that's being left out.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards.
    
    Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11507
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
    Reviewed-by: Julius Werner <jwerner at chromium.org>


See http://review.coreboot.org/11507 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:35:01 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:35:01 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: link
	ramstage like the other architectures
References: <I012c9b88c178b43bf6a6dde0bab821e066728139+0@gerrit.coreboot.org>
Message-ID: <E1ZZl93-0003ih-LP@mail.coreboot.org>

the following patch was just integrated into master:
commit cce557b7934c2560ac2ae33e06b6039acd4e6fb9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11508
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11508 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:35:12 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:35:12 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: linking: move
	romstage and bootblock to use program.ld
References: <I4c3e3671d696caa2c7601065a85fab803e86f971+0@gerrit.coreboot.org>
Message-ID: <E1ZZl9E-0003rs-5r@mail.coreboot.org>

the following patch was just integrated into master:
commit b2a62622ba030162784c31865a4fcba0c03408c7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:09:49 2015 -0500

    linking: move romstage and bootblock to use program.ld
    
    Instead of having separate <stage>.ld files in src/lib
    one file can be used: program.ld. There's now only one
    touch point for stage layout.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11509
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11509 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:35:20 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:35:20 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: link
	romstage like the other architectures
References: <I016666c4b01410df112e588c2949e3fc64540c2e+0@gerrit.coreboot.org>
Message-ID: <E1ZZl9M-0003xa-0f@mail.coreboot.org>

the following patch was just integrated into master:
commit 14714e1303a420f9e0bf0bb5bba2efaae2c52efb
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 12:06:05 2015 -0500

    x86: link romstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking romstage. Use that same method on x86
    as well for consistency.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11510
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11510 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:35:30 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:35:30 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: verstage: use
	common program.ld for linking
References: <I1195e06e06c1f81a758f68a026167689c19589dd+0@gerrit.coreboot.org>
Message-ID: <E1ZZl9W-0003zl-Cl@mail.coreboot.org>

the following patch was just integrated into master:
commit e5bad5cd3d828eba06f1db66f43948f966e7b0e0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 10:27:12 2015 -0500

    verstage: use common program.ld for linking
    
    There's no reason to have a separate verstage.ld now
    that there is a unified stage linking strategy. Moreover
    verstage support is throughout the code base as it is
    so bring in those link script macros into the common
    memlayout.h as that removes one more specific thing a
    board/chipset needs to do in order to turn on verstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=None
    
    Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11516
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11516 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:35:52 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:35:52 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: rmodule: use
	program.ld for linking
References: <Iaa499eb229d8171272add9ee6d27cff75e7534ac+0@gerrit.coreboot.org>
Message-ID: <E1ZZl9s-00042F-A7@mail.coreboot.org>

the following patch was just integrated into master:
commit dde7629e9cccf7b3a9b2e468ac8439f91d13cf97
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 12:59:26 2015 -0500

    rmodule: use program.ld for linking
    
    Bring rmodule linking into the common linking method.
    The __rmodule_entry symbol was removed while using
    a more common _start symbol. The rmodtool will honor
    the entry point found within the ELF header. Add
    ENV_RMODULE so that one can distinguish the environment
    when generating linker scripts for rmodules. Lastly,
    directly use program.ld for the rmodule.ld linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage,
         sipi_vector, and smm rmodules.
    
    Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11517
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11517 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:35:54 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:35:54 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: link
	romstage and ramstage with 1 file
References: <I1e8982a6a28027566ddd42a71b7e24e2397e68d2+0@gerrit.coreboot.org>
Message-ID: <E1ZZl9u-00042v-IO@mail.coreboot.org>

the following patch was just integrated into master:
commit 956c4f2d4cfa2b43085b493e0c5fed2f61cf5363
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Sep 5 13:31:14 2015 -0500

    x86: link romstage and ramstage with 1 file
    
    To reduce file clutter merge romstage.ld and ramstage.ld
    into a single memlayout.ld. The naming is consistent with
    other architectures and chipsets for their linker script
    names. The cache-as-ram linking rules are put into a separate
    file such that other rules can be applied for future verstage
    support.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and dmp/vortex86ex.
    
    Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11521
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11521 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:36:18 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:36:18 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: link
	ramstage the same way regardless of RELOCATABLE_RAMSTAGE
References: <I98d249036c27cb4847512ab8bca5ea7b02ce04bd+0@gerrit.coreboot.org>
Message-ID: <E1ZZlAI-00046Y-A6@mail.coreboot.org>

the following patch was just integrated into master:
commit 83bc0db777ef4906b0e0d2b588bfb14e1b82c84e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:45:18 2015 -0500

    x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
    
    Previously there were 2 paths in linking ramstage. One was used for
    RELOCATABLE_RAMSTAGE while the other was fixed location. Now that
    rmodtool can handle multiple secitons for a single proram segment
    there's no need for linking ramstage using lib/rmodule.ld.  That
    also means true rmodules don't have symbols required for ramstage
    purposes so fix memlayout.h. Lastly add default rules for creating
    rmod files from the known file names and locations.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Inspected ramstage.debug as well as rmodules
         created during the build.
    
    Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11524
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11524 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:36:20 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:36:20 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: rmodtool: make
	rmodule parameter section optional
References: <I5f8a415e86510be9409a28068e3d3a4d0ba8733e+0@gerrit.coreboot.org>
Message-ID: <E1ZZlAK-00047O-M4@mail.coreboot.org>

the following patch was just integrated into master:
commit c9b053d07d1edbd2b0016d19cb6730597ee0a21e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:39:10 2015 -0500

    rmodtool: make rmodule parameter section optional
    
    There are currently 2 uses for rmodule programs: stand alone
    programs that are separate from the coreboot stages and a
    relocatable ramstage. For the ramstage usage there's no reason
    to require a rmodule parameter section. Therefore make this
    optional.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built ramstage w/ normal linking (w/o a rmodule parameter
         section). No error.
    
    Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11523
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11523 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 19:36:23 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 19:36:23 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: linking: add
	and use LDFLAGS_common
References: <I41fbded54055455889b297b9e8738db4dda0aad0+0@gerrit.coreboot.org>
Message-ID: <E1ZZlAN-000483-5D@mail.coreboot.org>

the following patch was just integrated into master:
commit d4dd44cc2b75c13f5e99e8c293307199fe5e7e93
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sun Sep 6 10:15:17 2015 -0500

    linking: add and use LDFLAGS_common
    
    Add an LDFLAGS_common variable and use that for each stage
    during linking within all the architectures. All the architectures
    support gc-sections, and as such they should be linking in the
    same way.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi and analyzed the relocatable ramstage.
    
    Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11522
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-by: Julius Werner <jwerner at chromium.org>


See http://review.coreboot.org/11522 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 20:17:07 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 9 Sep 2015 20:17:07 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/skylake:
	ACPI: Clean up formatting in and fix ASL code
References: <I9726fb337bf53fa7dce72c5f30524b58abb4cab6+0@gerrit.coreboot.org>
Message-ID: <I9726fb337bf53fa7dce72c5f30524b58abb4cab6+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11539

-gerrit

commit 16fcaea1db3afd302616f06e2c0c20eb2ec71fff
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 17:19:24 2015 -0700

    intel/skylake: ACPI: Clean up formatting in and fix ASL code
    
    Clean up the formatting in various ASL files and remove
    unused and/or incorrect field definitions.
    
    Add back the methods to set the USB power in S3 field
    in NVS as it is called by the chromium kernel at boot and
    is currently complaining that the method is not found.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I9726fb337bf53fa7dce72c5f30524b58abb4cab6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3a47eeba2792c3abed07be175034c709dbf60879
    Original-Change-Id: I8e8388c9b834fd060990f8e069929ba829e29ab6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295952
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/globalnvs.asl   |  11 ++
 src/soc/intel/skylake/acpi/lpc.asl         |  99 +++++--------
 src/soc/intel/skylake/acpi/pci_irqs.asl    | 230 ++++++++++++++---------------
 src/soc/intel/skylake/acpi/systemagent.asl | 172 +++++++--------------
 4 files changed, 216 insertions(+), 296 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 0208198..31711d1 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -68,7 +68,18 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+}
 
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+	Store (One, \S3U0)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+	Store (Zero, \S3U0)
 }
 
 /* Set flag to enable USB charging in S5 */
diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl
index 877be99..c841311 100644
--- a/src/soc/intel/skylake/acpi/lpc.asl
+++ b/src/soc/intel/skylake/acpi/lpc.asl
@@ -19,33 +19,16 @@
  * Foundation, Inc.
  */
 
-
-// Intel LPC Bus Device  - 0:1f.0
-
 Device (LPCB)
 {
 	Name (_ADR, 0x001f0000)
+	Name (_DDN, "LPC Bus Device")
 
-	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
-	Field (LPC0, AnyAcc, NoLock, Preserve)
-	{
-		Offset (0x02),
-		PDID,	16,	// Device ID
-		Offset (0x40),
-		PMBS,	16,	// PMBASE
-		Offset (0x48),
-		GPBS,	16,	// GPIOBASE
-
-
-		Offset (0x80),	// IO Decode Ranges
-		IOD0,	8,
-		IOD1,	8,
-	}
-
-	Device (DMAC)	// DMA Controller
+	Device (DMAC)
 	{
-		Name (_HID, EISAID("PNP0200"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0200"))
+		Name (_DDN, "DMA Controller")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
 			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
@@ -55,40 +38,34 @@ Device (LPCB)
 		})
 	}
 
-	Device (FWH)	// Firmware Hub
+	Device (FWH)
 	{
-		Name (_HID, EISAID("INT0800"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("INT0800"))
+		Name (_DDN, "Firmware Hub")
+		Name (_CRS, ResourceTemplate ()
 		{
-			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+			Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
 		})
 	}
 
 	Device (HPET)
 	{
-		Name (_HID, EISAID("PNP0103"))
-		Name (BUF0, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0103"))
+		Name (_DDN, "High Precision Event Timer")
+		Name (_CRS, ResourceTemplate ()
 		{
-			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
+			Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
 		})
-
-		Method (_STA, 0)	// Device Status
+		Method (_STA, 0)
 		{
 			Return (0xf)
 		}
-		Method (_CRS, 0, Serialized) // Current resources
-		{
-			CreateDWordField (BUF0, ^FED0._BAS, HPT0)
-			/* TODO: Base address configured need to pass as GNVS */
-			Store(HPET_BASE_ADDRESS, HPT0)
-
-			Return(BUF0)
-		}
 	}
 
-	Device(PIC)	// 8259 Interrupt Controller
+	Device (PIC)
 	{
-		Name (_HID,EISAID("PNP0000"))
+		Name (_HID, EISAID ("PNP0000"))
+		Name (_DDN, "8259 Interrupt Controller")
 		Name (_CRS, ResourceTemplate()
 		{
 			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
@@ -112,22 +89,23 @@ Device (LPCB)
 		})
 	}
 
-	Device(MATH)	// FPU
+	Device (MATH)
 	{
-		Name (_HID, EISAID("PNP0C04"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0C04"))
+		Name (_DDN, "Floating Point Unit")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
-			IRQNoFlags() { 13 }
+			IRQNoFlags () { 13 }
 		})
 	}
 
-	Device(LDRC)	// LPC device: Resource consumption
+	Device (LDRC)
 	{
-		Name (_HID, EISAID("PNP0C02"))
+		Name (_HID, EISAID ("PNP0C02"))
 		Name (_UID, 2)
-
-		Name (RBUF, ResourceTemplate()
+		Name (_DDN, "Legacy Device Resources")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
 			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
@@ -141,30 +119,27 @@ Device (LPCB)
 			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
 			    0x1, 0xff)
 		})
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Return (RBUF)
-		}
 	}
 
-	Device (RTC)	// Real Time Clock
+	Device (RTC)
 	{
-		Name (_HID, EISAID("PNP0B00"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0B00"))
+		Name (_DDN, "Real Time Clock")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x70, 0x70, 1, 8)
-			//IRQNoFlags() { 8 }
 		})
 	}
 
-	Device (TIMR)	// Intel 8254 timer
+	Device (TIMR)
 	{
-		Name (_HID, EISAID("PNP0100"))
-		Name (_CRS, ResourceTemplate() {
+		Name (_HID, EISAID ("PNP0100"))
+		Name (_DDN, "8254 Timer")
+		Name (_CRS, ResourceTemplate ()
+		{
 			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
 			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
-			IRQNoFlags() {0}
+			IRQNoFlags () {0}
 		})
 	}
 
diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl
index c43e42d..3bf5f3e 100644
--- a/src/soc/intel/skylake/acpi/pci_irqs.asl
+++ b/src/soc/intel/skylake/acpi/pci_irqs.asl
@@ -19,125 +19,121 @@
  * Foundation, Inc.
  */
 
-Method(_PRT)
+Name (PICP, Package () {
+	/* D31: cAVS, SMBus, GbE, Nothpeak */
+	Package () { 0x001FFFFF, 0, 0, 16 },
+	Package () { 0x001FFFFF, 1, 0, 17 },
+	Package () { 0x001FFFFF, 2, 0, 18 },
+	Package () { 0x001FFFFF, 3, 0, 19 },
+	/* D30: SerialIo and SCS */
+	Package () { 0x001EFFFF, 0, 0, 20 },
+	Package () { 0x001EFFFF, 1, 0, 21 },
+	Package () { 0x001EFFFF, 2, 0, 22 },
+	Package () { 0x001EFFFF, 3, 0, 23 },
+	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001DFFFF, 0, 0, 16 },
+	Package () { 0x001DFFFF, 1, 0, 17 },
+	Package () { 0x001DFFFF, 2, 0, 18 },
+	Package () { 0x001DFFFF, 3, 0, 19 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, 0, 16 },
+	Package () { 0x001CFFFF, 1, 0, 17 },
+	Package () { 0x001CFFFF, 2, 0, 18 },
+	Package () { 0x001CFFFF, 3, 0, 19 },
+	/* D27: PCI Express Port 17-20 */
+	Package () { 0x001BFFFF, 0, 0, 16 },
+	Package () { 0x001BFFFF, 1, 0, 17 },
+	Package () { 0x001BFFFF, 2, 0, 18 },
+	Package () { 0x001BFFFF, 3, 0, 19 },
+	/* D25: SerialIo */
+	Package () { 0x0019FFFF, 0, 0, 32 },
+	Package () { 0x0019FFFF, 1, 0, 33 },
+	Package () { 0x0019FFFF, 2, 0, 34 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, 0, 16 },
+	Package () { 0x0016FFFF, 1, 0, 17 },
+	Package () { 0x0016FFFF, 2, 0, 18 },
+	Package () { 0x0016FFFF, 3, 0, 19 },
+	/* D21: SerialIo */
+	Package () { 0x0015FFFF, 0, 0, 16 },
+	Package () { 0x0015FFFF, 1, 0, 17 },
+	Package () { 0x0015FFFF, 2, 0, 18 },
+	Package () { 0x0015FFFF, 3, 0, 19 },
+	/* D20: xHCI, OTG, Thermal, Camera */
+	Package () { 0x0014FFFF, 0, 0, 16 },
+	Package () { 0x0014FFFF, 1, 0, 17 },
+	Package () { 0x0014FFFF, 2, 0, 18 },
+	Package () { 0x0014FFFF, 3, 0, 19 },
+	/* D19: Integrated Sensor Hub */
+	Package () { 0x0013FFFF, 0, 0, 20 },
+	/* P.E.G. Root Port D1F0 */
+	Package () { 0x0001FFFF, 0, 0, 16 },
+	Package () { 0x0001FFFF, 1, 0, 17 },
+	Package () { 0x0001FFFF, 2, 0, 18 },
+	Package () { 0x0001FFFF, 3, 0, 19 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, 0, 16 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, 0, 16 },
+	/* SA SkyCam Device */
+	Package () { 0x0005FFFF, 0, 0, 16 },
+	/* SA GMM Device */
+	Package () { 0x0008FFFF, 0, 0, 16 },
+})
+
+Name (PICN, Package () {
+	/* D31: cAVS, SMBus, GbE, Nothpeak */
+	Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D27: PCI Express Port 17-20 */
+	Package () { 0x001BFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001BFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001BFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001BFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D23 */
+	Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D20: xHCI, OTG, Thermal, Camera */
+	Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* P.E.G. Root Port D1F0 */
+	Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA Skycam Device */
+	Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA GMM Device */
+	Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
+})
+
+Method (_PRT)
 {
 	If (PICM) {
-		Return (Package() {
-		/* PCI Bridge */
-		/* D31: cAVS, SMBus, GbE, Nothpeak */
-			Package(){0x001FFFFF, 0, 0, 16 },
-			Package(){0x001FFFFF, 1, 0, 17 },
-			Package(){0x001FFFFF, 2, 0, 18 },
-			Package(){0x001FFFFF, 3, 0, 19 },
-		/* D30: SerialIo and SCS */
-			Package(){0x001EFFFF, 0, 0, 20 },
-			Package(){0x001EFFFF, 1, 0, 21 },
-			Package(){0x001EFFFF, 2, 0, 22 },
-			Package(){0x001EFFFF, 3, 0, 23 },
-		/* D29: PCI Express Port 9-16 */
-			Package(){0x001DFFFF, 0, 0, 16 },
-			Package(){0x001DFFFF, 1, 0, 17 },
-			Package(){0x001DFFFF, 2, 0, 18 },
-			Package(){0x001DFFFF, 3, 0, 19 },
-		/* D28: PCI Express Port 1-8 */
-			Package(){0x001CFFFF, 0, 0, 16 },
-			Package(){0x001CFFFF, 1, 0, 17 },
-			Package(){0x001CFFFF, 2, 0, 18 },
-			Package(){0x001CFFFF, 3, 0, 19 },
-		/* D27: PCI Express Port 17-20 */
-			Package(){0x001BFFFF, 0, 0, 16 },
-			Package(){0x001BFFFF, 1, 0, 17 },
-			Package(){0x001BFFFF, 2, 0, 18 },
-			Package(){0x001BFFFF, 3, 0, 19 },
-		/* D25: SerialIo */
-			Package(){0x0019FFFF, 0, 0, 32 },
-			Package(){0x0019FFFF, 1, 0, 33 },
-			Package(){0x0019FFFF, 2, 0, 34 },
-		/* D22: CSME (HECI, IDE-R, Keyboard and Text redirection */
-			Package(){0x0016FFFF, 0, 0, 16 },
-			Package(){0x0016FFFF, 1, 0, 17 },
-			Package(){0x0016FFFF, 2, 0, 18 },
-			Package(){0x0016FFFF, 3, 0, 19 },
-		/* D21: SerialIo */
-			Package(){0x0015FFFF, 0, 0, 16 },
-			Package(){0x0015FFFF, 1, 0, 17 },
-			Package(){0x0015FFFF, 2, 0, 18 },
-			Package(){0x0015FFFF, 3, 0, 19 },
-		/* D20: xHCI, OTG,
-		 * Thermal Subsystem, Camera IO Host Controller
-		 */
-			Package(){0x0014FFFF, 0, 0, 16 },
-			Package(){0x0014FFFF, 1, 0, 17 },
-			Package(){0x0014FFFF, 2, 0, 18 },
-			Package(){0x0014FFFF, 3, 0, 19 },
-		/* D19: Integrated Sensor Hub */
-			Package(){0x0013FFFF, 0, 0, 20 },
-
-		/* Host Bridge */
-		/* P.E.G. Root Port D1F0 */
-			Package(){0x0001FFFF, 0, 0, 16 },
-			Package(){0x0001FFFF, 1, 0, 17 },
-			Package(){0x0001FFFF, 2, 0, 18 },
-			Package(){0x0001FFFF, 3, 0, 19 },
-		/* P.E.G. Root Port D1F1 */
-		/* P.E.G. Root Port D1F2 */
-		/* SA IGFX Device */
-			Package(){0x0002FFFF, 0, 0, 16 },
-		/* SA Thermal Device */
-			Package(){0x0004FFFF, 0, 0, 16 },
-		/* SA SkyCam Device */
-			Package(){0x0005FFFF, 0, 0, 16 },
-		/* SA GMM Device */
-			Package(){0x0008FFFF, 0, 0, 16 },
-		})
+		Return (^PICP)
 	} Else {
-		Return (Package() {
-		/* D31 */
-		Package() { 0x001fffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001fffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001fffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001fffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D29 */
-		Package() { 0x001dffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001dffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001dffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001dffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D28 */
-		Package() { 0x001cffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001cffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001cffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001cffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D27 */
-		Package() { 0x001bffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001bffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001bffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001bffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D23 */
-		Package() { 0x0017ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* D22 */
-		Package() { 0x0016ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0016ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0016ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0016ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D20 */
-		Package() { 0x0014ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0014ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0014ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0014ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* Host bridge */
-		Package() { 0x0001ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0001ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0001ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0001ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* SA IGFX Device */
-		Package() { 0x0002ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA Thermal Device */
-		Package() { 0x0004ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA Skycam Device */
-		Package() { 0x0005ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA GMM Device */
-		Package() { 0x0008ffff, 0, \_SB.PCI0.LNKA, 0 },
-		})
+		Return (^PICN)
 	}
 }
-
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index b8fec94..9c9fc17 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -24,121 +24,73 @@
 #define BASE_32GB	0x800000000
 #define SIZE_16GB	0x400000000
 
-Name (_HID, EISAID ("PNP0A08"))	// PCIe
-Name (_CID, EISAID ("PNP0A03"))	// PCI
+Name (_HID, EISAID ("PNP0A08"))	/* PCIe */
+Name (_CID, EISAID ("PNP0A03"))	/* PCI */
 
 Name (_ADR, 0)
 Name (_BBN, 0)
 
 Device (MCHC)
 {
-	Name (_ADR, 0x00000000)	// 0:0.0
+	Name (_ADR, 0x00000000)
 
 	OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
 	Field (MCHP, DWordAcc, NoLock, Preserve)
 	{
-		Offset(0x40),	// EPBAR (0:0:0:40)
-		EPEN, 1,		// Enable
-			, 11,
-		EPBR, 20,		// EPBAR [31:12]
-
-		Offset(0x48),	// MCHBAR (0:0:0:48)
-		MHEN, 1,		// Enable
-			, 14,
-		MHBR, 17,	// MCHBAR [31:15]
-
-		Offset(0x54),	// DEVEN (0:0:0:54)
-		D0EN, 1,		// DEV0 Enable
-		D1F2, 1,		// DEV1 FUN2 Enable
-		D1F1, 1,		// DEV1 FUN1 Enable
-		D1F0, 1,		// DEV1 FUN0 Enable
-
-		Offset(0x60),	// PCIEXBAR (0:0:0:60)
-		PXEN, 1,		// Enable
-		PXSZ, 2,		// PCI Express Size
-			, 23,
-		PXBR, 6,		// PCI Express BAR [31:26]
-
-		Offset(0x68),	// DMIBAR (0:0:0:68)
-		DIEN, 1,		// Enable
-			, 11,
-		DIBR, 20,		// DMIBAR [31:12]
-
-		Offset (0x70),	// ME Base Address
+		Offset(0x40),	/* EPBAR (0:0:0:40) */
+		EPEN, 1,	/* Enable */
+		, 11,
+		EPBR, 20,	/* EPBAR [31:12] */
+
+		Offset(0x48),	/* MCHBAR (0:0:0:48) */
+		MHEN, 1,	/* Enable */
+		, 14,
+		MHBR, 17,	/* MCHBAR [31:15] */
+
+		Offset(0x60),	/* PCIEXBAR (0:0:0:60) */
+		PXEN, 1,	/* Enable */
+		PXSZ, 2,	/* PCI Express Size */
+		, 23,
+		PXBR, 6,	/* PCI Express BAR [31:26] */
+
+		Offset(0x68),	/* DMIBAR (0:0:0:68) */
+		DIEN, 1,	/* Enable */
+		, 11,
+		DIBR, 20,	/* DMIBAR [31:12] */
+
+		Offset (0x70),	/* ME Base Address */
 		MEBA, 64,
 
-		Offset(0x80),	// PAM0 Register (0:0:0:80)
-		PMLK, 1,		// PAM Lock bit.
-			, 3,
-		PM0H, 2,		// PAM 0, High Nibble
-			, 2,
-
-		Offset(0x81),	// PAM1 Register (0:0:0:81)
-		PM1L, 2,		// PAM1, Low  Nibble
-			, 2,
-		PM1H, 2,		// PAM1, High Nibble
-			, 2,
-
-		Offset(0x82),	// PAM2 Register (0:0:0:82)
-		PM2L, 2,		// PAM2, Low  Nibble
-			, 2,
-		PM2H, 2,		// PAM2, High Nibble
-			, 2,
-
-		Offset(0x83),	// PAM3 Register (0:0:0:83)
-		PM3L, 2,		// PAM3, Low  Nibble
-			, 2,
-		PM3H, 2,		// PAM3, High Nibble
-			, 2,
-
-		Offset(0x84),	// PAM4 Register (0:0:0:84)
-		PM4L, 2,		// PAM4, Low  Nibble
-			, 2,
-		PM4H, 2,		// PAM4, High Nibble
-			, 2,
-
-		Offset(0x85),	// PAM5 Register (0:0:0:85)
-		PM5L, 2,		// PAM5, Low  Nibble
-			, 2,
-		PM5H, 2,		// PAM5, High Nibble
-			, 2,
-
-		Offset(0x86),	// PAM6 Register (0:0:0:86)
-		PM6L, 2,		// PAM6, Low  Nibble
-			, 2,
-		PM6H, 2,		// PAM6, High Nibble
-			, 2,
-
-		Offset (0xa0),	// Top of Used Memory
+		Offset (0xa0),	/* Top of Used Memory */
 		TOM, 64,
 
-		Offset (0xa8),	// Top of Upper Used Memory
+		Offset (0xa8),	/* Top of Upper Used Memory */
 		TUUD, 64,
 
-		Offset (0xbc),	// Top of Low Used Memory
+		Offset (0xbc),	/* Top of Low Used Memory */
 		TLUD, 32,
 	}
 }
 
-// Current Resource Settings
-
 Method (_CRS, 0, Serialized)
 {
-	Name (MCRS, ResourceTemplate()
+	Name (MCRS, ResourceTemplate ()
 	{
 		/* Bus Numbers */
 		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
 				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
 
 		/* IO Region 0 */
-		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				EntireRange,
 				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
 
 		/* PCI Config Space */
 		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
 
 		/* IO Region 1 */
-		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				EntireRange,
 				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
 
 		/* VGA memory (0xa0000-0xbffff) */
@@ -278,13 +230,10 @@ Method (_CRS, 0, Serialized)
 
 	Store (^MCHC.TUUD, Local0)
 
-	If (LLessEqual (Local0, BASE_32GB))
-	{
+	If (LLessEqual (Local0, BASE_32GB)) {
 		Store (BASE_32GB, MMIN)
 		Store (SIZE_16GB, MLEN)
-	}
-	else
-	{
+	} Else {
 		Store (0, MMIN)
 		Store (0, MLEN)
 	}
@@ -300,50 +249,45 @@ Name (PC_L, 0) /* to store PCIe BAR Length */
 Name (DM_B, 0) /* to store DMI BAR */
 
 /* Get MCH BAR */
-Method (GMHB,0,Serialized)
+Method (GMHB, 0, Serialized)
 {
-	if (LEqual (MH_B,0))
-	{
+	If (LEqual (MH_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
 	}
 	Return (MH_B)
 }
 
 /* Get EP BAR */
-Method (GEPB,0,Serialized)
+Method (GEPB, 0, Serialized)
 {
-	if (LEqual (EP_B,0))
-	{
+	If (LEqual (EP_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
 	}
 	Return (EP_B)
 }
 
 /* Get PCIe BAR */
-Method (GPCB,0,Serialized)
+Method (GPCB, 0, Serialized)
 {
-	if (LEqual (PC_B,0))
-	{
+	If (LEqual (PC_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
 	}
 	Return (PC_B)
 }
 
 /* Get PCIe Length */
-Method (GPCL,0,Serialized)
+Method (GPCL, 0, Serialized)
 {
-	if (LEqual (PC_L,0))
-	{
+	If (LEqual (PC_L, 0)) {
 		ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
 	}
 	Return (PC_L)
 }
 
 /* Get DMI BAR */
-Method (GDMB,0,Serialized)
+Method (GDMB, 0, Serialized)
 {
-	if (LEqual (DM_B,0))
-	{
+	If (LEqual (DM_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
 	}
 	Return (DM_B)
@@ -352,10 +296,10 @@ Method (GDMB,0,Serialized)
 /* PCI Device Resource Consumption */
 Device (PDRC)
 {
-	Name (_HID, EISAID("PNP0C02"))
+	Name (_HID, EISAID ("PNP0C02"))
 	Name (_UID, 1)
 
-	Name (BUF0,ResourceTemplate()
+	Name (BUF0, ResourceTemplate ()
 	{
 		/* MCH BAR _BAS will be updated in _CRS below according to
 		 * B0:D0:F0:Reg.48h
@@ -398,8 +342,8 @@ Device (PDRC)
 		/* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
 		Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
 
-		/* Reserve HPET address decode range */
-		Memory32Fixed (ReadWrite, 0, 0, HPET)
+		/* HPET address decode range */
+		Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
 
 		/* Debug Base Address
 		 * Base Address for ACPI debug output memory buffer
@@ -407,28 +351,22 @@ Device (PDRC)
 		Memory32Fixed (ReadWrite, 0, 0, DBAD)
 	})
 
-	// Current Resource Settings
 	Method (_CRS, 0, Serialized)
 	{
 		CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
-		Store (\_SB.PCI0.GMHB(), MBR0)
+		Store (\_SB.PCI0.GMHB (), MBR0)
 
 		CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
-		Store (\_SB.PCI0.GDMB(), DBR0)
+		Store (\_SB.PCI0.GDMB (), DBR0)
 
 		CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
-		Store (\_SB.PCI0.GEPB(), EBR0)
+		Store (\_SB.PCI0.GEPB (), EBR0)
 
 		CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
-		Store (\_SB.PCI0.GPCB(), XBR0)
+		Store (\_SB.PCI0.GPCB (), XBR0)
 
 		CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
-		Store (\_SB.PCI0.GPCL(),  XSZ0)
-
-		CreateDwordField (BUF0, ^HPET._BAS, HBAS)
-		CreateDwordField (BUF0, ^HPET._LEN, HLEN)
-		Store (0xfed00000, HBAS)
-		Store (0x400, HLEN)
+		Store (\_SB.PCI0.GPCL (), XSZ0)
 
 		Return (BUF0)
 	}


From gerrit at coreboot.org  Wed Sep  9 20:17:15 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 20:17:15 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel/skylake:
	ACPI: Clean up formatting in and fix ASL code
References: <I9726fb337bf53fa7dce72c5f30524b58abb4cab6+0@gerrit.coreboot.org>
Message-ID: <E1ZZlnv-0005t7-Md@mail.coreboot.org>

the following patch was just integrated into master:
commit f966d3b3ae7c52691cfc5697c784c7e99f7d2fff
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 17:19:24 2015 -0700

    intel/skylake: ACPI: Clean up formatting in and fix ASL code
    
    Clean up the formatting in various ASL files and remove
    unused and/or incorrect field definitions.
    
    Add back the methods to set the USB power in S3 field
    in NVS as it is called by the chromium kernel at boot and
    is currently complaining that the method is not found.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I9726fb337bf53fa7dce72c5f30524b58abb4cab6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3a47eeba2792c3abed07be175034c709dbf60879
    Original-Change-Id: I8e8388c9b834fd060990f8e069929ba829e29ab6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295952
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11539
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11539 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 20:18:31 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 20:18:31 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: braswell:
	acpi: Allow DPTF thresholds to be defined at board-level
References: <Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0+0@gerrit.coreboot.org>
Message-ID: <E1ZZlp9-00060p-Kw@mail.coreboot.org>

the following patch was just integrated into master:
commit 3bad4cb086276a0fef715a3e661b489c59e27e08
Author: Shawn Nematbakhsh <shawnn at chromium.org>
Date:   Tue Aug 25 18:03:31 2015 -0700

    braswell: acpi: Allow DPTF thresholds to be defined at board-level
    
    Similar to Skylake, allow braswell mainboards to override the default
    DPTF thresholds.
    
    BUG=chrome-os-partner:43884
    TEST=Build for Strago
    BRANCH=Strago
    
    Change-Id: Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 799a7006e8fcacfea8e8e0de5c99c3ce3c4ac34f
    Original-Signed-off-by: Shawn Nematbakhsh <shawnn at chromium.org>
    Original-Change-Id: If69627163237674a28fb8a26b4ce1886e5dbfc17
    Original-Reviewed-on: https://chromium-review.googlesource.com/296033
    Original-Commit-Ready: Shawn N <shawnn at chromium.org>
    Original-Tested-by: Shawn N <shawnn at chromium.org>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11546
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11546 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 20:19:16 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 20:19:16 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: dptf:
	Add TSR3 thermal sensor and CPU code cleanup
References: <I1afe7013a24ee1215f5e968e25594f746bbdd17c+0@gerrit.coreboot.org>
Message-ID: <E1ZZlps-00068A-SU@mail.coreboot.org>

the following patch was just integrated into master:
commit 372b67e22b61a38fea3549b6658cdfe127459aab
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 15:57:56 2015 -0700

    skylake: dptf: Add TSR3 thermal sensor and CPU code cleanup
    
    - glados has more thermal sensors that could be used so add
    another entry in the DTPF thermal sensor ACPI code.
    - fix indentation block in cpu.asl.
    - declare \_SB.MPDL as external (it is already CondRefOf)
    so it does not need to be present in mainboard config if
    the mainboard does not want to override the default.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I1afe7013a24ee1215f5e968e25594f746bbdd17c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8d357437d06349039a94869b088c3c50b32933c0
    Original-Change-Id: Ie87d52e735bf930a003e525cf1918789920922a5
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297335
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11558
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11558 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 20:23:12 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 20:23:12 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: chromeec: Add
	kconfig entry for EC PD support
References: <I170271de9b929fcb73d6b0e09171385a6d23f153+0@gerrit.coreboot.org>
Message-ID: <E1ZZltg-0006gT-UM@mail.coreboot.org>

the following patch was just integrated into master:
commit ab40b9196977de2c37e37fc28e98bea4596460a7
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:14:18 2015 -0700

    chromeec: Add kconfig entry for EC PD support
    
    Add a kconfig entry to indicate that a board has a PD chip and
    try to put it in RO mode before the EC during early init.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c
    Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297747
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11571
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11571 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 20:23:28 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 20:23:28 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: samus: Use EC
	PD kconfig instead of manual PD reboot
References: <I9e7baffec500a83af1fcf9b1e43d418489172918+0@gerrit.coreboot.org>
Message-ID: <E1ZZltx-0006jC-02@mail.coreboot.org>

the following patch was just integrated into master:
commit 779caddec3c621f8bea667877b14cdfd339945e0
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:15:42 2015 -0700

    samus: Use EC PD kconfig instead of manual PD reboot
    
    Use the new kconfig entry to select the EC PD chip and have it
    be rebooted before the EC automatically insetad of being done
    manually by the board.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-samus coreboot
    
    Change-Id: I9e7baffec500a83af1fcf9b1e43d418489172918
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 53b086725d9d595e8eff7e1e35b9ba8db17ca199
    Original-Change-Id: I9c9a7dd2ba2b78d681b448839f2c5d15ba9dfe60
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297748
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11572
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11572 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 20:23:45 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 9 Sep 2015 20:23:45 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Select
	EC PD and call early EC init
References: <Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4+0@gerrit.coreboot.org>
Message-ID: <E1ZZluD-0006mG-Is@mail.coreboot.org>

the following patch was just integrated into master:
commit 5243b79053b1eed86a2adc126bef94083016d715
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:17:13 2015 -0700

    glados: Select EC PD and call early EC init
    
    Select the EC PD support in kconfig and call the EC early init
    code that will reboot into RO for recovery mode.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=boot on glados in recovery mode
    
    Change-Id: Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 135ef6e0e2c4864be1c25a9761e04cfe17aec51e
    Original-Change-Id: Iac8c092453bfbd94210462be0b377fb77410941d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297749
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11573
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11573 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep  9 22:26:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 9 Sep 2015 22:26:41 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: fsp1_1: provide
	binding to UEFI version
References: <I894165942cfe36936e186af5221efa810be8bb29+0@gerrit.coreboot.org>
Message-ID: <I894165942cfe36936e186af5221efa810be8bb29+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11606

-gerrit

commit 359c7aa79514aebf972f8fdd07bfe312d4cc0de1
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 9 17:05:06 2015 -0500

    fsp1_1: provide binding to UEFI version
    
    FSP has some unique attributes which makes integration
    cumbersome:
    
    1. FSP header files do not include the types they need. Like
       EDKII development it's expected types are provided by the
       build system. Therefore, one needs to include the proper
       files to avoid compilation issues.
    2. An implementation of FSP for a chipset may use different
       versions of the UEFI PI spec implementation. EDKII is a
       proxy for all of UEFI specifications. In order to provide
       flexibility one needs to binding a set of types and
       structures from an UEFI PI implementation.
    3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
       file which defines it's own types. Commonality between
       FSP chipset implementations are only named typedef
       structs. The fields within are not consistent. And
       because of FSP's insistence on typedefs it makes it
       near impossible to forward declare structs.
    
    The above 3 means one needs to include the correct UEFI
    type bindings when working with FSP. The current
    implementation had the SoC picking include paths in the
    edk2 directory and using a bare <uefi_types.h> include.
    Also, with the prior fsp_util.h implementation the SoC's
    FSP FspUpdVpd.h header file was required since for providing
    all the types at once (Generic FSP 1.1 and SoC types).
    
    The binding has been changed in the following manner:
    1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
       selects. No other bindings are currently available,
       but this provides the policy.
    2. Based on CONFIG_UEFI_2_4_BINDING the proper include
       paths are added to the CPPFLAGS_common.
    3. SoC Makefile.inc does not bind UEFI types nor does
       it adjust CPPFLAGS_common in any way.
    4. Provide a include/fsp directory under fsp1_1 and
       expose src/drivers/intel/fsp1_1/include in the
       include path. This split can allow a version 2,
       for example, FSP to provide its own include files.
       Yes, that means there needs to be consistency in
       APIs, however that's not this patch.
    5. Provide a way for code to differentiate the FSP spec
       types (fsp/api.h) from the chipset FSP types
       (fsp/soc_binding.h). This allows for code re-use that
       doesn't need the chipset types to be defined such as
       the FSP relocation code.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted on glados.
    
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    
    Change-Id: I894165942cfe36936e186af5221efa810be8bb29
---
 src/drivers/intel/fsp1_1/Kconfig                   |   1 +
 src/drivers/intel/fsp1_1/Makefile.inc              |   4 +-
 src/drivers/intel/fsp1_1/fsp_gop.c                 |   2 +-
 src/drivers/intel/fsp1_1/fsp_gop.h                 |  33 -------
 src/drivers/intel/fsp1_1/fsp_relocate.c            |   3 +-
 src/drivers/intel/fsp1_1/fsp_util.c                |   2 +-
 src/drivers/intel/fsp1_1/fsp_util.h                | 104 ---------------------
 src/drivers/intel/fsp1_1/hob.c                     |   2 +-
 src/drivers/intel/fsp1_1/include/fsp/api.h         |  41 ++++++++
 src/drivers/intel/fsp1_1/include/fsp/gop.h         |  33 +++++++
 src/drivers/intel/fsp1_1/include/fsp/soc_binding.h |  43 +++++++++
 .../intel/fsp1_1/include/fsp/uefi_binding.h        |  39 ++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |  96 +++++++++++++++++++
 src/soc/intel/braswell/Makefile.inc                |   8 --
 src/soc/intel/braswell/acpi.c                      |   2 +-
 src/soc/intel/braswell/chip.c                      |   2 +-
 src/soc/intel/braswell/chip.h                      |   2 +-
 .../intel/braswell/include/soc/chipset_fsp_util.h  |  41 --------
 src/soc/intel/braswell/include/soc/romstage.h      |   2 +-
 src/soc/intel/braswell/northcluster.c              |   2 +-
 src/soc/intel/braswell/ramstage.c                  |   2 +-
 src/soc/intel/braswell/romstage/romstage.c         |   2 +-
 src/soc/intel/common/fsp_ramstage.c                |   2 +-
 src/soc/intel/common/raminit.c                     |   2 +-
 src/soc/intel/common/ramstage.h                    |   2 +-
 src/soc/intel/common/romstage.h                    |   2 +-
 src/soc/intel/common/vbt.c                         |   2 +-
 src/soc/intel/skylake/Makefile.inc                 |   9 +-
 src/soc/intel/skylake/chip.c                       |   2 +-
 .../intel/skylake/include/soc/chipset_fsp_util.h   |  41 --------
 src/soc/intel/skylake/ramstage.c                   |   3 -
 src/vendorcode/intel/Kconfig                       |   3 +
 src/vendorcode/intel/Makefile.inc                  |  10 ++
 src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h    |  18 ++--
 34 files changed, 296 insertions(+), 266 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 2ffa323..d23d966 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -19,6 +19,7 @@
 
 config PLATFORM_USES_FSP1_1
 	bool
+	select UEFI_2_4_BINDING
 	help
 	  Does the code require the Intel Firmware Support Package?
 
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index f831f9d..bab68e1 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -26,7 +26,9 @@ ramstage-y += fsp_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
+# Where FspUpdVpd.h can be picked up from.
+CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
 
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
 
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c
index ed1f1b4..c5b515c 100644
--- a/src/drivers/intel/fsp1_1/fsp_gop.c
+++ b/src/drivers/intel/fsp1_1/fsp_gop.c
@@ -19,7 +19,7 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <lib.h>
 
 /* Reading VBT table from flash */
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.h b/src/drivers/intel/fsp1_1/fsp_gop.h
deleted file mode 100644
index 2999369..0000000
--- a/src/drivers/intel/fsp1_1/fsp_gop.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _FSP_GOP_H_
-#define _FSP_GOP_H_
-
-/* GOP support */
-#if IS_ENABLED(CONFIG_GOP_SUPPORT)
-
-#include <boot/coreboot_tables.h>
-#include <soc/intel/common/gma.h>
-
-const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
-void fsp_gop_framebuffer(struct lb_header *header);
-
-#endif /* CONFIG_GOP_SUPPORT */
-#endif /* _FSP_GOP_H_ */
diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
index 3e52608..2cc2560 100644
--- a/src/drivers/intel/fsp1_1/fsp_relocate.c
+++ b/src/drivers/intel/fsp1_1/fsp_relocate.c
@@ -19,11 +19,10 @@
 
 #include <console/console.h>
 #include <cbmem.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <stdlib.h>
 #include <stdint.h>
 #include <string.h>
-#include <uefi_types.h>
 
 #define FSP_DBG_LVL BIOS_NEVER
 
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 1d67e78..455c736 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -21,7 +21,7 @@
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <timestamp.h>
 
 /* Locate the FSP binary in the coreboot filesystem */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h
deleted file mode 100644
index 8f6f77a..0000000
--- a/src/drivers/intel/fsp1_1/fsp_util.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef FSP_UTIL_H
-#define FSP_UTIL_H
-
-#include <types.h>
-#include <arch/cpu.h>
-#include <fsp_gop.h>
-#include <program_loading.h>
-#include <region.h>
-
-/*
- * The following are functions with prototypes defined in the EDK2 headers. The
- * EDK2 headers are included with chipset_fsp_util.h.  Define the following
- * names to reduce the use of CamelCase in the other source files.
- */
-#define GetHobList	get_hob_list
-#define GetNextHob	get_next_hob
-#define GetFirstHob	get_first_hob
-#define GetNextGuidHob	get_next_guid_hob
-#define GetFirstGuidHob	get_first_guid_hob
-
-/* Include the EDK2 headers */
-#include <soc/chipset_fsp_util.h>
-
-/* find_fsp() should only be called from assembly code. */
-FSP_INFO_HEADER *find_fsp(void);
-/* Set FSP's runtime information. */
-void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
-/* Use a new FSP_INFO_HEADER at runtime. */
-void fsp_update_fih(FSP_INFO_HEADER *fih);
-/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
-FSP_INFO_HEADER *fsp_get_fih(void);
-/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
-void *fsp_get_hob_list(void);
-void fsp_early_init(FSP_INFO_HEADER *fsp_info);
-void fsp_notify(u32 phase);
-void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
-void print_fsp_info(FSP_INFO_HEADER *fsp_header);
-void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
-	const void *hob_start);
-void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
-void *get_first_resource_hob(const EFI_GUID *guid);
-/*
- * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
- * The FSP source is pointed to by region_device and the relocation information
- * is encoded in a struct prog with its entry point set to the FSP info header.
- */
-int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
-
-/* Additional HOB types not included in the FSP:
- * #define EFI_HOB_TYPE_HANDOFF 0x0001
- * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
- * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
- * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
- * #define EFI_HOB_TYPE_FV 0x0005
- * #define EFI_HOB_TYPE_CPU 0x0006
- * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
- * #define EFI_HOB_TYPE_CV 0x0008
- * #define EFI_HOB_TYPE_UNUSED 0xFFFE
- * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
- */
-#define EFI_HOB_TYPE_HANDOFF		0x0001
-#define EFI_HOB_TYPE_MEMORY_POOL	0x0007
-
-/* The offset in bytes from the start of the info structure */
-#define FSP_IMAGE_SIG_LOC			0
-#define FSP_IMAGE_ID_LOC			16
-#define FSP_IMAGE_BASE_LOC			28
-#define FSP_IMAGE_ATTRIBUTE_LOC			32
-#define  GRAPHICS_SUPPORT_BIT			(1 << 0)
-
-#define FSP_SIG					0x48505346	/* 'FSPH' */
-
-#define ERROR_NO_FV_SIG				1
-#define ERROR_NO_FFS_GUID			2
-#define ERROR_NO_INFO_HEADER			3
-#define ERROR_IMAGEBASE_MISMATCH		4
-#define ERROR_INFO_HEAD_SIG_MISMATCH		5
-#define ERROR_FSP_SIG_MISMATCH			6
-
-#if ENV_RAMSTAGE
-extern void *FspHobListPtr;
-#endif
-
-#endif	/* FSP_UTIL_H */
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
index 05044cb..467d4af 100644
--- a/src/drivers/intel/fsp1_1/hob.c
+++ b/src/drivers/intel/fsp1_1/hob.c
@@ -23,7 +23,7 @@
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <ip_checksum.h>
 #include <lib.h> // hexdump
 #include <string.h>
diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h
new file mode 100644
index 0000000..414532c
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/api.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_API_H_
+#define _FSP1_1_API_H_
+
+#define FSP_SIG		0x48505346	/* 'FSPH' */
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h>
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h
new file mode 100644
index 0000000..14bada6
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_GOP_H_
+#define _FSP1_1_GOP_H_
+
+/* GOP support */
+#if IS_ENABLED(CONFIG_GOP_SUPPORT)
+
+#include <boot/coreboot_tables.h>
+#include <soc/intel/common/gma.h>
+
+const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
+void fsp_gop_framebuffer(struct lb_header *header);
+
+#endif /* CONFIG_GOP_SUPPORT */
+#endif /* _FSP_GOP_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
new file mode 100644
index 0000000..1625040
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_SOC_BINDING_H_
+#define _FSP1_1_SOC_BINDING_H_
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * This file is found by way of the Kconfig FSP_INCLUDE_PATH option. It is
+ * a per implementation specific header. i.e. different FSP implementations
+ * for different chipsets.
+ */
+#include <FspUpdVpd.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
new file mode 100644
index 0000000..73a8a4a
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_UEFI_BINDING_H_
+#define _FSP1_1_UEFI_BINDING_H_
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * Pull in the UEFI types from 2.4. Smarter decisions can be made on what
+ * version to bind to, but for now 2.4 is standard for FSP 1.1.
+ */
+#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
new file mode 100644
index 0000000..8e61ae8
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef FSP1_1_UTIL_H
+#define FSP1_1_UTIL_H
+
+#include <fsp/api.h>
+/* Current users expect to get the SoC's FSP definitions by including util.h. */
+#include <fsp/soc_binding.h>
+#include <fsp/gop.h>
+#include <program_loading.h>
+#include <region.h>
+
+/* find_fsp() should only be called from assembly code. */
+FSP_INFO_HEADER *find_fsp(void);
+/* Set FSP's runtime information. */
+void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
+/* Use a new FSP_INFO_HEADER at runtime. */
+void fsp_update_fih(FSP_INFO_HEADER *fih);
+/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
+FSP_INFO_HEADER *fsp_get_fih(void);
+/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
+void *fsp_get_hob_list(void);
+void fsp_early_init(FSP_INFO_HEADER *fsp_info);
+void fsp_notify(u32 phase);
+void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
+void print_fsp_info(FSP_INFO_HEADER *fsp_header);
+void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
+	const void *hob_start);
+void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
+void *get_first_resource_hob(const EFI_GUID *guid);
+/*
+ * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
+ * The FSP source is pointed to by region_device and the relocation information
+ * is encoded in a struct prog with its entry point set to the FSP info header.
+ */
+int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
+
+/* Additional HOB types not included in the FSP:
+ * #define EFI_HOB_TYPE_HANDOFF 0x0001
+ * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
+ * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
+ * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
+ * #define EFI_HOB_TYPE_FV 0x0005
+ * #define EFI_HOB_TYPE_CPU 0x0006
+ * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+ * #define EFI_HOB_TYPE_CV 0x0008
+ * #define EFI_HOB_TYPE_UNUSED 0xFFFE
+ * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
+ */
+#define EFI_HOB_TYPE_HANDOFF		0x0001
+#define EFI_HOB_TYPE_MEMORY_POOL	0x0007
+
+/* The offset in bytes from the start of the info structure */
+#define FSP_IMAGE_SIG_LOC			0
+#define FSP_IMAGE_ID_LOC			16
+#define FSP_IMAGE_BASE_LOC			28
+#define FSP_IMAGE_ATTRIBUTE_LOC			32
+#define  GRAPHICS_SUPPORT_BIT			(1 << 0)
+
+#define ERROR_NO_FV_SIG				1
+#define ERROR_NO_FFS_GUID			2
+#define ERROR_NO_INFO_HEADER			3
+#define ERROR_IMAGEBASE_MISMATCH		4
+#define ERROR_INFO_HEAD_SIG_MISMATCH		5
+#define ERROR_FSP_SIG_MISMATCH			6
+
+#if ENV_RAMSTAGE
+extern void *FspHobListPtr;
+#endif
+
+/* TODO: Remove the EFI types and decorations from coreboot implementations. */
+VOID * EFIAPI get_hob_list(VOID);
+VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
+VOID * EFIAPI get_first_hob(UINT16 type);
+VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
+VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
+
+#endif	/* FSP1_1_UTIL_H */
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 755c15a..fae97b8 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -51,19 +51,11 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
-CPPFLAGS_common += -I$(src)/arch/x86/include/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index e1065e2..b8be3c6 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -35,7 +35,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <ec/google/chromeec/ec.h>
-#include <fsp_gop.h>
+#include <fsp/gop.h>
 #include <rules.h>
 #include <soc/acpi.h>
 #include <soc/gfx.h>
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index c986507..6f22740 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -22,7 +22,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 191fc01..ff68014 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -27,7 +27,7 @@
 #define _SOC_CHIP_H_
 
 #include <stdint.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 
 #define SVID_CONFIG1		1
diff --git a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
deleted file mode 100644
index c269a61..0000000
--- a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef CHIPSET_FSP_UTIL_H
-#define CHIPSET_FSP_UTIL_H
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h>				/* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h>		/* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h>	/* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h>	/* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>	/* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>	/* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>	/* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h>		/* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h>	/* HOB routine declarations */
-#include <FspUpdVpd.h>		/* Vital/updatable product data definitions */
-
-#endif	/* CHIPSET_FSP_UTIL_H */
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 770a39d..a735c04 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -23,7 +23,7 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>
 #include <soc/intel/common/romstage.h>
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 7821a2a..390e050 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -25,7 +25,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/memmap.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 3e1e02f..26c23bc 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -29,7 +29,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <romstage_handoff.h>
 #include <soc/gpio.h>
 #include <soc/lpc.h>
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 1dbff54..2286cd4 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -40,7 +40,7 @@
 #include <timestamp.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index 41c0b1c..d1f2e49 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -22,7 +22,7 @@
 #include <cbmem.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h>
 #include <soc/intel/common/memmap.h>
 #include <soc/intel/common/ramstage.h>
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
index ddf5675..bdb23e2 100644
--- a/src/soc/intel/common/raminit.c
+++ b/src/soc/intel/common/raminit.c
@@ -19,7 +19,7 @@
 
 #include <cbmem.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h> /* hexdump */
 #include <reset.h>
 #include <soc/intel/common/memmap.h>
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h
index 414142a..d6cb895 100644
--- a/src/soc/intel/common/ramstage.h
+++ b/src/soc/intel/common/ramstage.h
@@ -21,7 +21,7 @@
 #ifndef _INTEL_COMMON_RAMSTAGE_H_
 #define _INTEL_COMMON_RAMSTAGE_H_
 
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <stdint.h>
 
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index 440cad7..b35ff66 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -24,7 +24,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <memory_info.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>		/* chip_power_state */
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index 0e46b70..b12ec04 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -20,7 +20,7 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h>
 #include <soc/intel/common/ramstage.h>
 #include <string.h>
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 32ecb5d..38668da 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -61,19 +61,12 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
-CPPFLAGS_common += -I$(src)/arch/x86/include/
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
+# Currently used for microcode path.
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 2c49883..afb0ff6 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -23,7 +23,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <string.h>
diff --git a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h b/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
deleted file mode 100644
index 2c05f01..0000000
--- a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CHIPSET_FSP_UTIL_H_
-#define _CHIPSET_FSP_UTIL_H_
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h>				/* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h>		/* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h>	/* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h>	/* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>	/* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>	/* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>	/* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h>		/* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h>	/* HOB routine declarations */
-#include <FspUpdVpd.h>		/* Vital/updatable product data definitions */
-
-#endif	/* _CHIPSET_FSP_UTIL_H_ */
diff --git a/src/soc/intel/skylake/ramstage.c b/src/soc/intel/skylake/ramstage.c
index 51e9b31..3646843 100644
--- a/src/soc/intel/skylake/ramstage.c
+++ b/src/soc/intel/skylake/ramstage.c
@@ -18,9 +18,6 @@
  * Foundation, Inc.
  */
 
-#include <bootstate.h>
-#include <console/console.h>
-#include <fsp_util.h>
 #include <soc/ramstage.h>
 #include <soc/intel/common/ramstage.h>
 
diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig
index 0da26f0..754c487 100644
--- a/src/vendorcode/intel/Kconfig
+++ b/src/vendorcode/intel/Kconfig
@@ -22,3 +22,6 @@ config FSP_VENDORCODE_HEADER_PATH
 	default "fsp1_0/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
 	default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL
 	default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX
+
+config UEFI_2_4_BINDING
+	def_bool n
diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc
index 2cb486b..b95d4f9 100644
--- a/src/vendorcode/intel/Makefile.inc
+++ b/src/vendorcode/intel/Makefile.inc
@@ -25,3 +25,13 @@ ramstage-y += $(FSP_C_INPUTS)
 
 CFLAGS_x86_32 += -Isrc/vendorcode/intel/$(FSP_PATH)/include
 endif
+
+ifeq ($(CONFIG_UEFI_2_4_BINDING),y)
+# ProccessorBind.h provided in Ia32 directory. Types are derived from ia32.
+# It's possible to provide our own ProcessorBind.h using posix types. However,
+# ProcessorBind.h isn't just about types. There's compiler definitions as well
+# as ABI enforcement. Luckily long is not used in Ia32/ProcessorBind.h for
+# a fixed width type.
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+endif
diff --git a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
index e17361e..e68f8c9 100644
--- a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
+++ b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
@@ -37,15 +37,15 @@ are permitted provided that the following conditions are met:
 #define __APPLE__ 0
 #include <stdlib.h>
 #include <Uefi/UefiBaseType.h>
-#include <MdePkg/Include/Pi/PiBootMode.h>
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>
-#include <MdePkg/Include/Pi/PiHob.h>
-#include <MdePkg/Include/Protocol/GraphicsOutput.h>
-#include <MdePkg/Include/Library/HobLib.h>
-#include <MdePkg/Include/Guid/FirmwareFileSystem2.h>
-#include <MdePkg/Include/IndustryStandard/PeImage.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiFirmwareVolume.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiHob.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Library/HobLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <IndustryStandard/PeImage.h>
 
 ///
 /// For GNU assembly code, .global or .globl can declare global symbols.


From gerrit at coreboot.org  Thu Sep 10 02:14:08 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 02:14:08 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: genbuild_h:
	Add Mac OS to case of "data -r"
References: <I2a43a1b1749da207b7a23b8eb252c13605121533+0@gerrit.coreboot.org>
Message-ID: <E1ZZrNI-0005Ns-CX@mail.coreboot.org>

the following patch was just integrated into master:
commit 5e1fb2d0748c49e064e1ed2cc68db36eff3bc00c
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Sep 9 05:16:40 2015 -0400

    genbuild_h: Add Mac OS to case of "data -r"
    
    Change-Id: I2a43a1b1749da207b7a23b8eb252c13605121533
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
    Reviewed-on: http://review.coreboot.org/11599
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11599 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 05:51:29 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Thu, 10 Sep 2015 05:51:29 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: WIP: cpu:
	microcode: Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit 2dc8f5d6402c1af1dbd907f734b7160a6f2aced3
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    WIP: cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan made converted most microcode in blobs to
    binary, use the binary version. Save the poor compiler the wild goose
    hunt.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                       | 23 ++++++++++-------------
 src/cpu/intel/model_1067x/Makefile.inc     |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c |  3 ---
 src/cpu/intel/model_106cx/Makefile.inc     |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c |  3 ---
 src/cpu/intel/model_2065x/Makefile.inc     |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c | 22 ----------------------
 src/cpu/intel/model_206ax/Makefile.inc     |  3 +++
 src/cpu/intel/model_206ax/microcode_blob.c | 23 -----------------------
 src/cpu/intel/model_65x/Makefile.inc       |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c   |  3 ---
 src/cpu/intel/model_67x/Makefile.inc       |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c   |  3 ---
 src/cpu/intel/model_68x/Makefile.inc       |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c   |  3 ---
 src/cpu/intel/model_69x/Makefile.inc       |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c   |  3 ---
 src/cpu/intel/model_6bx/Makefile.inc       |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c   |  3 ---
 src/cpu/intel/model_6dx/Makefile.inc       |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c   |  3 ---
 src/cpu/intel/model_6ex/Makefile.inc       |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c   |  3 ---
 src/cpu/intel/model_6fx/Makefile.inc       |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c   |  3 ---
 src/cpu/intel/model_6xx/Makefile.inc       |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c   |  3 ---
 src/cpu/intel/model_f0x/Makefile.inc       |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c   |  4 ----
 src/cpu/intel/model_f1x/Makefile.inc       |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c   |  4 ----
 src/cpu/intel/model_f2x/Makefile.inc       |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c   |  4 ----
 src/cpu/intel/model_f3x/Makefile.inc       |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c   |  3 ---
 src/cpu/intel/model_f4x/Makefile.inc       |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c   |  3 ---
 src/cpu/via/nano/Makefile.inc              |  4 +++-
 38 files changed, 33 insertions(+), 127 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..4b74ce2 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -8,4 +8,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
+
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..ffedcb8 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..999b8fa 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -28,6 +28,8 @@ ramstage-y += update_ucode.c
 
 # This microcode is included as a separate CBFS file. It is never linked in to
 # the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc


From gerrit at coreboot.org  Thu Sep 10 09:05:35 2015
From: gerrit at coreboot.org (Gerd Hoffmann (kraxel@redhat.com))
Date: Thu, 10 Sep 2015 09:05:35 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: qemu:
	initialize lapic
References: <I022f3742475d3f3477fc838b1e2bce69287b6b8e+0@gerrit.coreboot.org>
Message-ID: <I022f3742475d3f3477fc838b1e2bce69287b6b8e+1@gerrit.coreboot.org>

Gerd Hoffmann (kraxel at redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11611

-gerrit

commit 07929cad329a628b03b98b139a5ded4716c9afe6
Author: Gerd Hoffmann <kraxel at redhat.com>
Date:   Thu Sep 10 10:58:52 2015 +0200

    qemu: initialize lapic
    
    Recently qemu stopped doing a basic lapic setup and expects the
    firmware to handle this properly (like on real hardware).  So
    lets do that so coreboot works properly on qemu 2.4+.
    
    Here is the qemu commit message for the change:
    
    <quote>
      commit b8eb5512fd8a115f164edbbe897cdf8884920ccb
      Author: Nadav Amit <namit at cs.technion.ac.il>
      Date:   Mon Apr 13 02:32:08 2015 +0300
    
      target-i386: disable LINT0 after reset
    
      Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone
      and therefore this hack is no longer needed.  Since it violates the
      specifications, it is removed.
    
      Signed-off-by: Nadav Amit <namit at cs.technion.ac.il>
      Message-Id: <1428881529-29459-2-git-send-email-namit at cs.technion.ac.il>
      Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
    </quote>
    
    Change-Id: I022f3742475d3f3477fc838b1e2bce69287b6b8e
    Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
 src/cpu/qemu-x86/qemu.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c
index 4704bb8..b6f0ad5 100644
--- a/src/cpu/qemu-x86/qemu.c
+++ b/src/cpu/qemu-x86/qemu.c
@@ -18,8 +18,15 @@
 
 #include <cpu/cpu.h>
 #include <device/device.h>
+#include <cpu/x86/lapic.h>
+
+static void qemu_cpu_init(struct device *dev)
+{
+	setup_lapic();
+}
 
 static struct device_operations cpu_dev_ops = {
+	.init = qemu_cpu_init,
 };
 
 static struct cpu_device_id cpu_table[] = {


From gerrit at coreboot.org  Thu Sep 10 09:12:03 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:12:03 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: crossgcc: Add
	option to build gcc for specific languages
References: <I6a74ab2c75871ea8d03a499cca33d88938b59c8d+0@gerrit.coreboot.org>
Message-ID: <E1ZZxtj-0004sn-GV@mail.coreboot.org>

the following patch was just integrated into master:
commit bb313bf2219da1c483b2205f301b95db06eac760
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Sep 8 12:30:27 2015 +0200

    crossgcc: Add option to build gcc for specific languages
    
    Add an option `--languages` which takes a list of target languages to
    buildgcc. That list gets passed through to the configure step for
    building gcc.
    
    Also alter the Makefile to pass $(BUILD_LANGUAGES) to that option, if
    this variable is set.
    
    Change-Id: I6a74ab2c75871ea8d03a499cca33d88938b59c8d
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
    Reviewed-on: http://review.coreboot.org/11589
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11589 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:17:12 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:17:12 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: crossgcc:
	Preparations for building Ada frontend
References: <Ia78c29d1aba2943de5238421a324cfff8eb08875+0@gerrit.coreboot.org>
Message-ID: <E1ZZxyj-0005ai-0h@mail.coreboot.org>

the following patch was just integrated into master:
commit 135ca51314a437cbb50bafb8ed24b48b2d7c5127
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Sep 8 12:38:57 2015 +0200

    crossgcc: Preparations for building Ada frontend
    
    As with most other languages, a pre-installed Ada toolchain is needed
    to build gcc's Ada frontend. To support building with older host tool-
    chains, the patch `gcc-5.2.0_gnat.patch` disables warnings for unknown
    pragmas. Building has been tested with host gcc-4.9 and hopefully works
    with newer versions, too.
    
    For convenience, the gnattools (e.g. gnatmake etc.) will be build if
    'ada' is specified as a target language.
    
    Change-Id: Ia78c29d1aba2943de5238421a324cfff8eb08875
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
    Reviewed-on: http://review.coreboot.org/11590
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11590 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:18:17 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:18:17 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	Add missing autoconf dependency
References: <I9f0dd8adbc3aa434a18cb4815b1ccbd1f6e7847b+0@gerrit.coreboot.org>
Message-ID: <E1ZZxzl-0005gI-Hz@mail.coreboot.org>

the following patch was just integrated into master:
commit 602a82af7cb9ad0c41d4470f82a725a9caec46d4
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed Sep 9 13:02:51 2015 +0200

    libpayload: Add missing autoconf dependency
    
    With new version of kconfig we have to trigger [silent]oldconfig each
    time .config changed. We missed that, because config.h had no dependen-
    cies.
    
    Change-Id: I9f0dd8adbc3aa434a18cb4815b1ccbd1f6e7847b
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
    Reviewed-on: http://review.coreboot.org/11603
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11603 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:19:18 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:19:18 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	Fix merge of PL011 UART support
References: <Ifea8113fbc59e0463eaedb86b976f54ec11113a9+0@gerrit.coreboot.org>
Message-ID: <E1ZZy0k-0005o9-Py@mail.coreboot.org>

the following patch was just integrated into master:
commit a7c609c262d5beba968519903fed297dc4b601c1
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed Sep 9 13:27:09 2015 +0200

    libpayload: Fix merge of PL011 UART support
    
    Wished I hadn't seen that. Git saw the conflict (file was gone), both
    committer and reviewer thought it would be a good idea to re-add it as
    dead code (see 558e9b5: libpayload: Add minimal support for PL011 UART).
    
    Change-Id: Ifea8113fbc59e0463eaedb86b976f54ec11113a9
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
    Reviewed-on: http://review.coreboot.org/11604
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11604 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:43:16 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:43:16 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: FSP: Pass FSP
	image base address to find_fsp
References: <Iac43c8aac8491390479af551765b514ca919928a+0@gerrit.coreboot.org>
Message-ID: <E1ZZyNw-0000KX-TV@mail.coreboot.org>

the following patch was just integrated into master:
commit a887492e1e51849b75c7bb0d67430be4b1074493
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Wed Aug 26 14:58:29 2015 -0700

    FSP: Pass FSP image base address to find_fsp
    
    Add a parameter to find_fsp which is the image base address.  Adjust the
    fake stack in cache_as_ram.inc to pass in the read-only FSP image base
    address.  In fsp_notify, pass in the read-only FSP image base address
    when the FSP header pointer is NULL.  In find_fsp, validate the FSP
    binary image starting from the specified image base address.
    
    BRANCH=none
    BUG=None
    TEST=Build and run on Skylake
    
    Change-Id: Iac43c8aac8491390479af551765b514ca919928a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95
    Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e
    Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295593
    Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Tested-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11545
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11545 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:43:45 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:43:45 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: Skylake: Print
	GPIO MMIO base and pad config using gpio_debug token
References: <I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42+0@gerrit.coreboot.org>
Message-ID: <E1ZZyOP-0000PG-Pv@mail.coreboot.org>

the following patch was just integrated into master:
commit c1bc8171e65bb9100c4e9cb0efe8e5aa9771d4d3
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Mon Aug 31 17:10:35 2015 +0530

    Skylake: Print GPIO MMIO base and pad config using gpio_debug token
    
    This will help development activity. Default GPIO print settings is
    disable, need to set gpio_debug = 1 to get GPIO MMIO dump.
    
    BUG=None
    BRANCH=None
    TEST=build coreboot and boot on Kunimitsu.
    
    Change-Id: I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 19102612ea40184307ecb0ce8b165b5b989f6911
    Original-Change-Id: I4ea6349866c108382de9787bb9ed09fc78d9c770
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296280
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11552
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11552 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:48:01 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:48:01 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake:
	Enable DPTF based on devicetree setting
References: <I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51+0@gerrit.coreboot.org>
Message-ID: <E1ZZySX-00012u-FB@mail.coreboot.org>

the following patch was just integrated into master:
commit 7fce30c2a5dd748ab3efa79fb24e3c85cef11628
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 13:53:14 2015 -0700

    skylake: Enable DPTF based on devicetree setting
    
    Enable DPTF flag in ACPI NVS based on devicetree setting
    for the mainboard.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glaods coreboot
    
    Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5
    Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297755
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11565
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11565 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:48:20 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:48:20 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Change
	include headers to relative path
References: <I6d184adab5b6b2df970ddd3998d3413f1330c12e+0@gerrit.coreboot.org>
Message-ID: <E1ZZySq-00016J-2G@mail.coreboot.org>

the following patch was just integrated into master:
commit 241f8fcf1a496746200736f49ae9f8d067c00624
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:10:48 2015 -0700

    glados: Change include headers to relative path
    
    To make it easier to port glados to a new board name change
    the include headers to use relative path name instead of
    including the mainboard name.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90
    Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297742
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11566
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11566 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:48:33 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:48:33 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Remove
	thermal.h
References: <Idb716b47875b20e2110741ae9c154cc52307fbcf+0@gerrit.coreboot.org>
Message-ID: <E1ZZyT3-000182-4B@mail.coreboot.org>

the following patch was just integrated into master:
commit e067083d08b391882c7a773d0a70073d28dc17b4
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:13:36 2015 -0700

    glados: Remove thermal.h
    
    The constants defined in thermal.h are never used since there
    is no defined thermal zone.  Remove it to result in less code
    to worry about in board ports.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10
    Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297743
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11567
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11567 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:48:56 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:48:56 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Misc
	code cleanups
References: <I0f76a560dc2c4197e66999752c52573ff0278430+0@gerrit.coreboot.org>
Message-ID: <E1ZZyTQ-0001CA-OY@mail.coreboot.org>

the following patch was just integrated into master:
commit 44b01fdcd7bbd7e619f496530d3bfbea69f7fce9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:19:42 2015 -0700

    glados: Misc code cleanups
    
    - romstage.c is using gpio_configure_pads so it should really
    include soc/gpio.h instead of relying on it to come from "gpio.h"
    - consistent formatting of array initializers in pei_data.c
    - remove pei_data->ec_present flag as this is unused in skylake
    - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR
    - clean up acpi_slp_type usage in ec.c, remove unnecessary post
    codes, and cleaner console output message.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b
    Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297744
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11568
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11568 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:50:27 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:50:27 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Enable
	DPTF
References: <I8cd2e0ea9c322ea92c101995e8e706f063428a45+0@gerrit.coreboot.org>
Message-ID: <E1ZZyUt-0001Xk-3J@mail.coreboot.org>

the following patch was just integrated into master:
commit 0678bea4b6dcd6c3e90ca400fbb5d5ec65f694f4
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:22:49 2015 -0700

    glados: Enable DPTF
    
    - Add ACPI code for DPTF support with placeholder thresholds
    - Do not have custom PDL for mainboard
    - Do not have enable charger control for DPTF as there is
    already a complicated charge profile in the EC.  We may still
    want to enable this but it would need to be tuned to work
    well with the EC profile.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a
    Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297745
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11569
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11569 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:50:45 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:50:45 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Add
	Board ID support
References: <Iba93a913b67e3b3230aded289c2e25585dec1195+0@gerrit.coreboot.org>
Message-ID: <E1ZZyVB-0001aK-4H@mail.coreboot.org>

the following patch was just integrated into master:
commit 1a50d08fc7671cea527299df5b80c0bbfa450f91
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:12:59 2015 -0700

    glados: Add Board ID support
    
    Add support for reading board id and populating it in the
    coreboot tables so it is exposed to payloads.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=boot on glados and look for reported board ID
    
    Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004
    Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297746
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11570
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11570 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:51:41 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:51:41 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Select BOARD_ID_AUTO and clean up boardid code
References: <I90bd85ef14543717287cbeaaab77e6c54b94df97+0@gerrit.coreboot.org>
Message-ID: <E1ZZyW5-0001hD-Uf@mail.coreboot.org>

the following patch was just integrated into master:
commit 88b21f31e61c2527b05623a2ebbbd150531d7657
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:24:40 2015 -0700

    kunimitsu: Select BOARD_ID_AUTO and clean up boardid code
    
    Select the BOARD_ID_AUTO kconfig option to have the coreboot
    tables populated with the board ID and print it early in
    romstage as well.  Also clean up the code for it.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I90bd85ef14543717287cbeaaab77e6c54b94df97
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 1fed7de4a0650a497a240b091fd2eb99d59e1433
    Original-Change-Id: I82e9d17ab618b1aae1fd874d9247b7d52b42334d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297750
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11574
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11574 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:51:55 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:51:55 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Select EC PD and software sync and do early init
References: <I48316df99b796c568c2481c72588b41f7147bec0+0@gerrit.coreboot.org>
Message-ID: <E1ZZyWJ-0001iw-EN@mail.coreboot.org>

the following patch was just integrated into master:
commit 963bfa7a0f36d25b22ff221ddc3f1a537bb655a2
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:29:58 2015 -0700

    kunimitsu: Select EC PD and software sync and do early init
    
    Select the EC PD and software sync kconfig options so they are
    supported by the mainboard and call the EC early init function
    to reboot into RO in recovery mode.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I48316df99b796c568c2481c72588b41f7147bec0
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c7507470f82848062bc98da809d3c5fe1ca31998
    Original-Change-Id: I822aac9c24718f226819e5d3fcc82a4024b7c5a7
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297751
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11575
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11575 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:52:14 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:52:14 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Clean up mainboard code to match glados
References: <I64a053bcec0e0ff25a57f65659f391ab64d9a11a+0@gerrit.coreboot.org>
Message-ID: <E1ZZyWc-0001m5-R2@mail.coreboot.org>

the following patch was just integrated into master:
commit 74b964ec4ace463d0b221a369a754bc86776e594
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 10:41:02 2015 -0700

    kunimitsu: Clean up mainboard code to match glados
    
    Clean up the intel/kunimitsu mainboard code to match the code
    and cleanups in glados.  Many of these are trivial changes that
    do not impact things in a meaningful way but will make it easier
    to diff the code and keep the mainboards in sync.
    
    - use relative path for mainboard includes to make porting easier
    - fix trivial style issues to match glados so diffs are clean
    - pull GPIO configuration into gpio.h and use from there
    - remove thermal.h as it is not used on this board
    - make info message BIOS_INFO instead of BIOS_ERR
    - add support for SPD manufacturer and part number in SMBIOS
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be
    Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297752
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11576
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11576 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:52:33 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:52:33 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel/common:
	Print board ID if enabled
References: <I9d50089242b3a2f461dff2b1039adc8f0347179e+0@gerrit.coreboot.org>
Message-ID: <E1ZZyWv-0001oL-Pi@mail.coreboot.org>

the following patch was just integrated into master:
commit 91da91f5d1ac3a1c2671771f18495fc3b703fae5
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 13:47:34 2015 -0700

    intel/common: Print board ID if enabled
    
    Read and print the board ID if it is enabled in the mainboard.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f
    Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297756
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11577
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11577 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:54:28 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:54:28 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: sklrvp: Remove
	thermal.h and functions from acpi_tables.c
References: <I934fcc451a722f853034c0970074ee3259cc704f+0@gerrit.coreboot.org>
Message-ID: <E1ZZyYm-0001wh-V8@mail.coreboot.org>

the following patch was just integrated into master:
commit 4bf410aa291ba4e6ea133f7c80d92af0ed59a476
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 14:21:14 2015 -0700

    sklrvp: Remove thermal.h and functions from acpi_tables.c
    
    Remove thermal.h as it is not used by this board.
    Remove functions from acpi_tables.c so they can move to SOC.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-sklrvp coreboot (does not compile due to GPIO changes)
    
    Change-Id: I934fcc451a722f853034c0970074ee3259cc704f
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7e3b5c0ed8295091d3d5761b8456f3c13c6bd8bc
    Original-Change-Id: If855f598e895e38c58657af17130158b2f73de81
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297757
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11578
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11578 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:54:44 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:54:44 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Remove
	functions from acpi_tables.c
References: <I18e6a0be5eac053598b613b30b622c4963417919+0@gerrit.coreboot.org>
Message-ID: <E1ZZyZ2-0001zJ-F1@mail.coreboot.org>

the following patch was just integrated into master:
commit cdcadfef07e0a4c64eef324e83984e3c0e03b0a2
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 14:15:36 2015 -0700

    glados: Remove functions from acpi_tables.c
    
    Remove the acpi_tables.c functions so these functions can move to
    SOC init code.  The file itself is included by x86/arch code and
    must exist for the build to succeed.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I18e6a0be5eac053598b613b30b622c4963417919
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2
    Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297758
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11579
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11579 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:55:08 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:55:08 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Remove functions from acpi_tables.c
References: <Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911+0@gerrit.coreboot.org>
Message-ID: <E1ZZyZQ-000296-VP@mail.coreboot.org>

the following patch was just integrated into master:
commit 5f3ea3b77ed733e59a83c0c77d36b8b9e7a322a1
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 14:16:49 2015 -0700

    kunimitsu: Remove functions from acpi_tables.c
    
    Remove the acpi_tables.c functions so these functions can move to
    SOC init code.  The file itself is included by x86/arch code and
    must exist for the build to succeed.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 93ae87f2429af5cb9d497f8b5ef8b8dffe370df4
    Original-Change-Id: Ifc2f64dc1693e7bd3f5a43144d84ff033b2cfe8b
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297759
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11580
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11580 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 09:55:26 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 09:55:26 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: Move
	ACPI init to SOC instead of mainboard
References: <I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52+0@gerrit.coreboot.org>
Message-ID: <E1ZZyZi-0002Hs-Bp@mail.coreboot.org>

the following patch was just integrated into master:
commit db54a67b769d2734c3e79a35c8909e2b16001ac1
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 14:19:35 2015 -0700

    skylake: Move ACPI init to SOC instead of mainboard
    
    Move some remaining ACPI init code to the SOC instead of being
    done in each mainboard:
    
    - acpi_create_gnvs is now a local function
    - add a weak acpi_mainboard_gnvs() that can be used for mainboards
    to override or set additional NVS
    - add acpi_fill_madt() function for skylake
    - remove acpi_create_serialio_ssdt() function as it is unused
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c717bb418a0cb6002582572632e42b44b473f718
    Original-Change-Id: I0910ac8ef25de265ae1fde16b68f6cbacedb4462
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297800
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11581
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11581 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 14:05:19 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 10 Sep 2015 14:05:19 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: intel/skylake:
	HAVE_UART_MEMORY_MAPPED doesn't exist anymore
References: <Ie5481d23cd3ac3561958fd100bd05c0e4b03ce00+0@gerrit.coreboot.org>
Message-ID: <Ie5481d23cd3ac3561958fd100bd05c0e4b03ce00+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11612

-gerrit

commit a1c2906632df49064c63d1e60923a4f759f55dac
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 9 21:53:52 2015 +0200

    intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymore
    
    ... the configuration is handled further below in the file by virtue of
    select DRIVERS_UART_8250MEM
    
    Change-Id: Ie5481d23cd3ac3561958fd100bd05c0e4b03ce00
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/soc/intel/skylake/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 843cb8a..07c1d41 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -24,7 +24,6 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_HARD_RESET
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
-	select HAVE_UART_MEMORY_MAPPED
 	select IOAPIC
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT


From gerrit at coreboot.org  Thu Sep 10 14:54:33 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 14:54:33 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel/skylake:
	HAVE_UART_MEMORY_MAPPED doesn't exist anymore
References: <Ie5481d23cd3ac3561958fd100bd05c0e4b03ce00+0@gerrit.coreboot.org>
Message-ID: <E1Za3FB-00057x-Ru@mail.coreboot.org>

the following patch was just integrated into master:
commit 87582d1cf2ff09c5ef7f48f41469eaf124e9ffde
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 9 21:53:52 2015 +0200

    intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymore
    
    ... the configuration is handled further below in the file by virtue of
    select DRIVERS_UART_8250MEM
    
    Change-Id: Ie5481d23cd3ac3561958fd100bd05c0e4b03ce00
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11612
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11612 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 15:38:08 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Thu, 10 Sep 2015 15:38:08 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: ifdtool: Enable
	warnings as errors, and fix any issues
References: <Id462a10c2affac54ec48a1cc2a5b2ca66112848e+0@gerrit.coreboot.org>
Message-ID: <Id462a10c2affac54ec48a1cc2a5b2ca66112848e+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11613

-gerrit

commit f5a63d730d50e8bb48f333da457c695f1fffe9c8
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Thu Sep 10 08:37:42 2015 -0700

    ifdtool: Enable warnings as errors, and fix any issues
    
    Change-Id: Id462a10c2affac54ec48a1cc2a5b2ca66112848e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/ifdtool/Makefile  | 2 +-
 util/ifdtool/ifdtool.c | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
index a234ded..02a02c4 100644
--- a/util/ifdtool/Makefile
+++ b/util/ifdtool/Makefile
@@ -22,7 +22,7 @@ PROGRAM = ifdtool
 CC      = gcc
 INSTALL = /usr/bin/install
 PREFIX  = /usr/local
-CFLAGS  = -O2 -g -Wall -W
+CFLAGS  = -O2 -g -Wall -W -Werror
 LDFLAGS =
 
 OBJS = ifdtool.o
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 214998c..9277e7c 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -42,7 +42,7 @@ static const struct region_name region_names[MAX_REGIONS] = {
 	{ "Reserved", "res1" },
 	{ "Reserved", "res2" },
 	{ "Reserved", "res3" },
-	{ "EC" "ec" },
+	{ "EC", "ec" },
 };
 
 static fdbar_t *find_fd(char *image, int size)
@@ -729,6 +729,9 @@ static void set_em100_mode(char *filename, char *image, int size)
 	case IFD_VERSION_2:
 		freq = SPI_FREQUENCY_17MHZ;
 		break;
+	default:
+		SPI_FREQUENCY_17MHZ;
+		break;
 	}
 
 	fcba->flcomp &= ~(1 << 30);


From gerrit at coreboot.org  Thu Sep 10 16:00:18 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Thu, 10 Sep 2015 16:00:18 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: ifdtool: Enable
	warnings as errors, and fix any issues
References: <Id462a10c2affac54ec48a1cc2a5b2ca66112848e+0@gerrit.coreboot.org>
Message-ID: <Id462a10c2affac54ec48a1cc2a5b2ca66112848e+2@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11613

-gerrit

commit 5b2078ab9dfd17086e62db1a311f92781dbdc9ea
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Thu Sep 10 08:37:42 2015 -0700

    ifdtool: Enable warnings as errors, and fix any issues
    
    Change-Id: Id462a10c2affac54ec48a1cc2a5b2ca66112848e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/ifdtool/Makefile  | 2 +-
 util/ifdtool/ifdtool.c | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
index a234ded..02a02c4 100644
--- a/util/ifdtool/Makefile
+++ b/util/ifdtool/Makefile
@@ -22,7 +22,7 @@ PROGRAM = ifdtool
 CC      = gcc
 INSTALL = /usr/bin/install
 PREFIX  = /usr/local
-CFLAGS  = -O2 -g -Wall -W
+CFLAGS  = -O2 -g -Wall -W -Werror
 LDFLAGS =
 
 OBJS = ifdtool.o
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 214998c..e6ed110 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -42,7 +42,7 @@ static const struct region_name region_names[MAX_REGIONS] = {
 	{ "Reserved", "res1" },
 	{ "Reserved", "res2" },
 	{ "Reserved", "res3" },
-	{ "EC" "ec" },
+	{ "EC", "ec" },
 };
 
 static fdbar_t *find_fd(char *image, int size)
@@ -729,6 +729,9 @@ static void set_em100_mode(char *filename, char *image, int size)
 	case IFD_VERSION_2:
 		freq = SPI_FREQUENCY_17MHZ;
 		break;
+	default:
+		freq = SPI_FREQUENCY_17MHZ;
+		break;
 	}
 
 	fcba->flcomp &= ~(1 << 30);


From gerrit at coreboot.org  Thu Sep 10 16:43:24 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 10 Sep 2015 16:43:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: fsp1_1: provide
	binding to UEFI version
References: <I894165942cfe36936e186af5221efa810be8bb29+0@gerrit.coreboot.org>
Message-ID: <I894165942cfe36936e186af5221efa810be8bb29+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11606

-gerrit

commit ce7842cd7a44e7ff36a17bb1bcf9d88afac2138c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 9 17:05:06 2015 -0500

    fsp1_1: provide binding to UEFI version
    
    FSP has some unique attributes which makes integration
    cumbersome:
    
    1. FSP header files do not include the types they need. Like
       EDKII development it's expected types are provided by the
       build system. Therefore, one needs to include the proper
       files to avoid compilation issues.
    2. An implementation of FSP for a chipset may use different
       versions of the UEFI PI spec implementation. EDKII is a
       proxy for all of UEFI specifications. In order to provide
       flexibility one needs to binding a set of types and
       structures from an UEFI PI implementation.
    3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
       file which defines it's own types. Commonality between
       FSP chipset implementations are only named typedef
       structs. The fields within are not consistent. And
       because of FSP's insistence on typedefs it makes it
       near impossible to forward declare structs.
    
    The above 3 means one needs to include the correct UEFI
    type bindings when working with FSP. The current
    implementation had the SoC picking include paths in the
    edk2 directory and using a bare <uefi_types.h> include.
    Also, with the prior fsp_util.h implementation the SoC's
    FSP FspUpdVpd.h header file was required since for providing
    all the types at once (Generic FSP 1.1 and SoC types).
    
    The binding has been changed in the following manner:
    1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
       selects. No other bindings are currently available,
       but this provides the policy.
    2. Based on CONFIG_UEFI_2_4_BINDING the proper include
       paths are added to the CPPFLAGS_common.
    3. SoC Makefile.inc does not bind UEFI types nor does
       it adjust CPPFLAGS_common in any way.
    4. Provide a include/fsp directory under fsp1_1 and
       expose src/drivers/intel/fsp1_1/include in the
       include path. This split can allow a version 2,
       for example, FSP to provide its own include files.
       Yes, that means there needs to be consistency in
       APIs, however that's not this patch.
    5. Provide a way for code to differentiate the FSP spec
       types (fsp/api.h) from the chipset FSP types
       (fsp/soc_binding.h). This allows for code re-use that
       doesn't need the chipset types to be defined such as
       the FSP relocation code.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted on glados.
    
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    
    Change-Id: I894165942cfe36936e186af5221efa810be8bb29
---
 src/drivers/intel/fsp1_1/Kconfig                   |   1 +
 src/drivers/intel/fsp1_1/Makefile.inc              |   4 +-
 src/drivers/intel/fsp1_1/fsp_gop.c                 |   2 +-
 src/drivers/intel/fsp1_1/fsp_gop.h                 |  33 -------
 src/drivers/intel/fsp1_1/fsp_relocate.c            |   3 +-
 src/drivers/intel/fsp1_1/fsp_util.c                |   2 +-
 src/drivers/intel/fsp1_1/fsp_util.h                | 104 ---------------------
 src/drivers/intel/fsp1_1/hob.c                     |   2 +-
 src/drivers/intel/fsp1_1/include/fsp/api.h         |  41 ++++++++
 src/drivers/intel/fsp1_1/include/fsp/gop.h         |  33 +++++++
 src/drivers/intel/fsp1_1/include/fsp/soc_binding.h |  43 +++++++++
 .../intel/fsp1_1/include/fsp/uefi_binding.h        |  39 ++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |  96 +++++++++++++++++++
 src/soc/intel/braswell/Makefile.inc                |   8 --
 src/soc/intel/braswell/acpi.c                      |   2 +-
 src/soc/intel/braswell/chip.c                      |   2 +-
 src/soc/intel/braswell/chip.h                      |   2 +-
 .../intel/braswell/include/soc/chipset_fsp_util.h  |  41 --------
 src/soc/intel/braswell/include/soc/romstage.h      |   2 +-
 src/soc/intel/braswell/northcluster.c              |   2 +-
 src/soc/intel/braswell/ramstage.c                  |   2 +-
 src/soc/intel/braswell/romstage/romstage.c         |   2 +-
 src/soc/intel/common/fsp_ramstage.c                |   2 +-
 src/soc/intel/common/raminit.c                     |   2 +-
 src/soc/intel/common/ramstage.h                    |   2 +-
 src/soc/intel/common/romstage.h                    |   2 +-
 src/soc/intel/common/vbt.c                         |   2 +-
 src/soc/intel/skylake/Makefile.inc                 |   9 +-
 src/soc/intel/skylake/chip.c                       |   2 +-
 .../intel/skylake/include/soc/chipset_fsp_util.h   |  41 --------
 src/soc/intel/skylake/ramstage.c                   |   3 -
 src/vendorcode/intel/Kconfig                       |   3 +
 src/vendorcode/intel/Makefile.inc                  |  10 ++
 src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h    |  18 ++--
 34 files changed, 296 insertions(+), 266 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 2ffa323..d23d966 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -19,6 +19,7 @@
 
 config PLATFORM_USES_FSP1_1
 	bool
+	select UEFI_2_4_BINDING
 	help
 	  Does the code require the Intel Firmware Support Package?
 
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index f831f9d..bab68e1 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -26,7 +26,9 @@ ramstage-y += fsp_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
+# Where FspUpdVpd.h can be picked up from.
+CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
 
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
 
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c
index ed1f1b4..c5b515c 100644
--- a/src/drivers/intel/fsp1_1/fsp_gop.c
+++ b/src/drivers/intel/fsp1_1/fsp_gop.c
@@ -19,7 +19,7 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <lib.h>
 
 /* Reading VBT table from flash */
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.h b/src/drivers/intel/fsp1_1/fsp_gop.h
deleted file mode 100644
index 2999369..0000000
--- a/src/drivers/intel/fsp1_1/fsp_gop.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _FSP_GOP_H_
-#define _FSP_GOP_H_
-
-/* GOP support */
-#if IS_ENABLED(CONFIG_GOP_SUPPORT)
-
-#include <boot/coreboot_tables.h>
-#include <soc/intel/common/gma.h>
-
-const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
-void fsp_gop_framebuffer(struct lb_header *header);
-
-#endif /* CONFIG_GOP_SUPPORT */
-#endif /* _FSP_GOP_H_ */
diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
index 3e52608..2cc2560 100644
--- a/src/drivers/intel/fsp1_1/fsp_relocate.c
+++ b/src/drivers/intel/fsp1_1/fsp_relocate.c
@@ -19,11 +19,10 @@
 
 #include <console/console.h>
 #include <cbmem.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <stdlib.h>
 #include <stdint.h>
 #include <string.h>
-#include <uefi_types.h>
 
 #define FSP_DBG_LVL BIOS_NEVER
 
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index e6e3889..d44f0f0 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -21,7 +21,7 @@
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <timestamp.h>
 
 /* Locate the FSP binary in the coreboot filesystem */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h
deleted file mode 100644
index 51ecb98..0000000
--- a/src/drivers/intel/fsp1_1/fsp_util.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef FSP_UTIL_H
-#define FSP_UTIL_H
-
-#include <types.h>
-#include <arch/cpu.h>
-#include <fsp_gop.h>
-#include <program_loading.h>
-#include <region.h>
-
-/*
- * The following are functions with prototypes defined in the EDK2 headers. The
- * EDK2 headers are included with chipset_fsp_util.h.  Define the following
- * names to reduce the use of CamelCase in the other source files.
- */
-#define GetHobList	get_hob_list
-#define GetNextHob	get_next_hob
-#define GetFirstHob	get_first_hob
-#define GetNextGuidHob	get_next_guid_hob
-#define GetFirstGuidHob	get_first_guid_hob
-
-/* Include the EDK2 headers */
-#include <soc/chipset_fsp_util.h>
-
-/* find_fsp() should only be called from assembly code. */
-FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
-/* Set FSP's runtime information. */
-void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
-/* Use a new FSP_INFO_HEADER at runtime. */
-void fsp_update_fih(FSP_INFO_HEADER *fih);
-/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
-FSP_INFO_HEADER *fsp_get_fih(void);
-/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
-void *fsp_get_hob_list(void);
-void fsp_early_init(FSP_INFO_HEADER *fsp_info);
-void fsp_notify(u32 phase);
-void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
-void print_fsp_info(FSP_INFO_HEADER *fsp_header);
-void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
-	const void *hob_start);
-void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
-void *get_first_resource_hob(const EFI_GUID *guid);
-/*
- * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
- * The FSP source is pointed to by region_device and the relocation information
- * is encoded in a struct prog with its entry point set to the FSP info header.
- */
-int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
-
-/* Additional HOB types not included in the FSP:
- * #define EFI_HOB_TYPE_HANDOFF 0x0001
- * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
- * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
- * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
- * #define EFI_HOB_TYPE_FV 0x0005
- * #define EFI_HOB_TYPE_CPU 0x0006
- * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
- * #define EFI_HOB_TYPE_CV 0x0008
- * #define EFI_HOB_TYPE_UNUSED 0xFFFE
- * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
- */
-#define EFI_HOB_TYPE_HANDOFF		0x0001
-#define EFI_HOB_TYPE_MEMORY_POOL	0x0007
-
-/* The offset in bytes from the start of the info structure */
-#define FSP_IMAGE_SIG_LOC			0
-#define FSP_IMAGE_ID_LOC			16
-#define FSP_IMAGE_BASE_LOC			28
-#define FSP_IMAGE_ATTRIBUTE_LOC			32
-#define  GRAPHICS_SUPPORT_BIT			(1 << 0)
-
-#define FSP_SIG					0x48505346	/* 'FSPH' */
-
-#define ERROR_NO_FV_SIG				1
-#define ERROR_NO_FFS_GUID			2
-#define ERROR_NO_INFO_HEADER			3
-#define ERROR_IMAGEBASE_MISMATCH		4
-#define ERROR_INFO_HEAD_SIG_MISMATCH		5
-#define ERROR_FSP_SIG_MISMATCH			6
-
-#if ENV_RAMSTAGE
-extern void *FspHobListPtr;
-#endif
-
-#endif	/* FSP_UTIL_H */
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
index 05044cb..467d4af 100644
--- a/src/drivers/intel/fsp1_1/hob.c
+++ b/src/drivers/intel/fsp1_1/hob.c
@@ -23,7 +23,7 @@
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <ip_checksum.h>
 #include <lib.h> // hexdump
 #include <string.h>
diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h
new file mode 100644
index 0000000..414532c
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/api.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_API_H_
+#define _FSP1_1_API_H_
+
+#define FSP_SIG		0x48505346	/* 'FSPH' */
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h>
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h
new file mode 100644
index 0000000..14bada6
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_GOP_H_
+#define _FSP1_1_GOP_H_
+
+/* GOP support */
+#if IS_ENABLED(CONFIG_GOP_SUPPORT)
+
+#include <boot/coreboot_tables.h>
+#include <soc/intel/common/gma.h>
+
+const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
+void fsp_gop_framebuffer(struct lb_header *header);
+
+#endif /* CONFIG_GOP_SUPPORT */
+#endif /* _FSP_GOP_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
new file mode 100644
index 0000000..1625040
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_SOC_BINDING_H_
+#define _FSP1_1_SOC_BINDING_H_
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * This file is found by way of the Kconfig FSP_INCLUDE_PATH option. It is
+ * a per implementation specific header. i.e. different FSP implementations
+ * for different chipsets.
+ */
+#include <FspUpdVpd.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
new file mode 100644
index 0000000..73a8a4a
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_UEFI_BINDING_H_
+#define _FSP1_1_UEFI_BINDING_H_
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * Pull in the UEFI types from 2.4. Smarter decisions can be made on what
+ * version to bind to, but for now 2.4 is standard for FSP 1.1.
+ */
+#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
new file mode 100644
index 0000000..9695b3b
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef FSP1_1_UTIL_H
+#define FSP1_1_UTIL_H
+
+#include <fsp/api.h>
+/* Current users expect to get the SoC's FSP definitions by including util.h. */
+#include <fsp/soc_binding.h>
+#include <fsp/gop.h>
+#include <program_loading.h>
+#include <region.h>
+
+/* find_fsp() should only be called from assembly code. */
+FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
+/* Set FSP's runtime information. */
+void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
+/* Use a new FSP_INFO_HEADER at runtime. */
+void fsp_update_fih(FSP_INFO_HEADER *fih);
+/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
+FSP_INFO_HEADER *fsp_get_fih(void);
+/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
+void *fsp_get_hob_list(void);
+void fsp_early_init(FSP_INFO_HEADER *fsp_info);
+void fsp_notify(u32 phase);
+void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
+void print_fsp_info(FSP_INFO_HEADER *fsp_header);
+void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
+	const void *hob_start);
+void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
+void *get_first_resource_hob(const EFI_GUID *guid);
+/*
+ * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
+ * The FSP source is pointed to by region_device and the relocation information
+ * is encoded in a struct prog with its entry point set to the FSP info header.
+ */
+int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
+
+/* Additional HOB types not included in the FSP:
+ * #define EFI_HOB_TYPE_HANDOFF 0x0001
+ * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
+ * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
+ * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
+ * #define EFI_HOB_TYPE_FV 0x0005
+ * #define EFI_HOB_TYPE_CPU 0x0006
+ * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+ * #define EFI_HOB_TYPE_CV 0x0008
+ * #define EFI_HOB_TYPE_UNUSED 0xFFFE
+ * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
+ */
+#define EFI_HOB_TYPE_HANDOFF		0x0001
+#define EFI_HOB_TYPE_MEMORY_POOL	0x0007
+
+/* The offset in bytes from the start of the info structure */
+#define FSP_IMAGE_SIG_LOC			0
+#define FSP_IMAGE_ID_LOC			16
+#define FSP_IMAGE_BASE_LOC			28
+#define FSP_IMAGE_ATTRIBUTE_LOC			32
+#define  GRAPHICS_SUPPORT_BIT			(1 << 0)
+
+#define ERROR_NO_FV_SIG				1
+#define ERROR_NO_FFS_GUID			2
+#define ERROR_NO_INFO_HEADER			3
+#define ERROR_IMAGEBASE_MISMATCH		4
+#define ERROR_INFO_HEAD_SIG_MISMATCH		5
+#define ERROR_FSP_SIG_MISMATCH			6
+
+#if ENV_RAMSTAGE
+extern void *FspHobListPtr;
+#endif
+
+/* TODO: Remove the EFI types and decorations from coreboot implementations. */
+VOID * EFIAPI get_hob_list(VOID);
+VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
+VOID * EFIAPI get_first_hob(UINT16 type);
+VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
+VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
+
+#endif	/* FSP1_1_UTIL_H */
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 755c15a..fae97b8 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -51,19 +51,11 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
-CPPFLAGS_common += -I$(src)/arch/x86/include/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index e1065e2..b8be3c6 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -35,7 +35,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <ec/google/chromeec/ec.h>
-#include <fsp_gop.h>
+#include <fsp/gop.h>
 #include <rules.h>
 #include <soc/acpi.h>
 #include <soc/gfx.h>
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index c986507..6f22740 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -22,7 +22,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 191fc01..ff68014 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -27,7 +27,7 @@
 #define _SOC_CHIP_H_
 
 #include <stdint.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 
 #define SVID_CONFIG1		1
diff --git a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
deleted file mode 100644
index c269a61..0000000
--- a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef CHIPSET_FSP_UTIL_H
-#define CHIPSET_FSP_UTIL_H
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h>				/* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h>		/* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h>	/* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h>	/* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>	/* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>	/* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>	/* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h>		/* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h>	/* HOB routine declarations */
-#include <FspUpdVpd.h>		/* Vital/updatable product data definitions */
-
-#endif	/* CHIPSET_FSP_UTIL_H */
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 770a39d..a735c04 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -23,7 +23,7 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>
 #include <soc/intel/common/romstage.h>
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 7821a2a..390e050 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -25,7 +25,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/memmap.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 3e1e02f..26c23bc 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -29,7 +29,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <romstage_handoff.h>
 #include <soc/gpio.h>
 #include <soc/lpc.h>
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 1dbff54..2286cd4 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -40,7 +40,7 @@
 #include <timestamp.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index 41c0b1c..d1f2e49 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -22,7 +22,7 @@
 #include <cbmem.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h>
 #include <soc/intel/common/memmap.h>
 #include <soc/intel/common/ramstage.h>
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
index ddf5675..bdb23e2 100644
--- a/src/soc/intel/common/raminit.c
+++ b/src/soc/intel/common/raminit.c
@@ -19,7 +19,7 @@
 
 #include <cbmem.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h> /* hexdump */
 #include <reset.h>
 #include <soc/intel/common/memmap.h>
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h
index 414142a..d6cb895 100644
--- a/src/soc/intel/common/ramstage.h
+++ b/src/soc/intel/common/ramstage.h
@@ -21,7 +21,7 @@
 #ifndef _INTEL_COMMON_RAMSTAGE_H_
 #define _INTEL_COMMON_RAMSTAGE_H_
 
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <stdint.h>
 
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index 440cad7..b35ff66 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -24,7 +24,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <memory_info.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>		/* chip_power_state */
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index 0e46b70..b12ec04 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -20,7 +20,7 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h>
 #include <soc/intel/common/ramstage.h>
 #include <string.h>
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 32ecb5d..38668da 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -61,19 +61,12 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
-CPPFLAGS_common += -I$(src)/arch/x86/include/
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
+# Currently used for microcode path.
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 2c49883..afb0ff6 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -23,7 +23,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <string.h>
diff --git a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h b/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
deleted file mode 100644
index 2c05f01..0000000
--- a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CHIPSET_FSP_UTIL_H_
-#define _CHIPSET_FSP_UTIL_H_
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h>				/* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h>		/* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h>	/* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h>	/* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>	/* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>	/* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>	/* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h>		/* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h>	/* HOB routine declarations */
-#include <FspUpdVpd.h>		/* Vital/updatable product data definitions */
-
-#endif	/* _CHIPSET_FSP_UTIL_H_ */
diff --git a/src/soc/intel/skylake/ramstage.c b/src/soc/intel/skylake/ramstage.c
index 51e9b31..3646843 100644
--- a/src/soc/intel/skylake/ramstage.c
+++ b/src/soc/intel/skylake/ramstage.c
@@ -18,9 +18,6 @@
  * Foundation, Inc.
  */
 
-#include <bootstate.h>
-#include <console/console.h>
-#include <fsp_util.h>
 #include <soc/ramstage.h>
 #include <soc/intel/common/ramstage.h>
 
diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig
index 0da26f0..754c487 100644
--- a/src/vendorcode/intel/Kconfig
+++ b/src/vendorcode/intel/Kconfig
@@ -22,3 +22,6 @@ config FSP_VENDORCODE_HEADER_PATH
 	default "fsp1_0/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
 	default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL
 	default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX
+
+config UEFI_2_4_BINDING
+	def_bool n
diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc
index 2cb486b..b95d4f9 100644
--- a/src/vendorcode/intel/Makefile.inc
+++ b/src/vendorcode/intel/Makefile.inc
@@ -25,3 +25,13 @@ ramstage-y += $(FSP_C_INPUTS)
 
 CFLAGS_x86_32 += -Isrc/vendorcode/intel/$(FSP_PATH)/include
 endif
+
+ifeq ($(CONFIG_UEFI_2_4_BINDING),y)
+# ProccessorBind.h provided in Ia32 directory. Types are derived from ia32.
+# It's possible to provide our own ProcessorBind.h using posix types. However,
+# ProcessorBind.h isn't just about types. There's compiler definitions as well
+# as ABI enforcement. Luckily long is not used in Ia32/ProcessorBind.h for
+# a fixed width type.
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+endif
diff --git a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
index e17361e..e68f8c9 100644
--- a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
+++ b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
@@ -37,15 +37,15 @@ are permitted provided that the following conditions are met:
 #define __APPLE__ 0
 #include <stdlib.h>
 #include <Uefi/UefiBaseType.h>
-#include <MdePkg/Include/Pi/PiBootMode.h>
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>
-#include <MdePkg/Include/Pi/PiHob.h>
-#include <MdePkg/Include/Protocol/GraphicsOutput.h>
-#include <MdePkg/Include/Library/HobLib.h>
-#include <MdePkg/Include/Guid/FirmwareFileSystem2.h>
-#include <MdePkg/Include/IndustryStandard/PeImage.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiFirmwareVolume.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiHob.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Library/HobLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <IndustryStandard/PeImage.h>
 
 ///
 /// For GNU assembly code, .global or .globl can declare global symbols.


From gerrit at coreboot.org  Thu Sep 10 17:21:18 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 10 Sep 2015 17:21:18 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: endian: add
	portable endian functions
References: <I737facab0c849cb4b95756eefbf3ffd69e558b32+0@gerrit.coreboot.org>
Message-ID: <I737facab0c849cb4b95756eefbf3ffd69e558b32+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11618

-gerrit

commit fba1469a3416abc5fe83fcc0c550a3db2f0eaa4a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 12:08:34 2015 -0500

    endian: add portable endian functions
    
    The current endian API support in coreboot doesn't follow
    any known API that can be shared in userland as well coreboot
    proper. To that end provide big and little endian helper functions
    that can be used in code that can be shared within coreboot proper
    and userland tools.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi
    
    Change-Id: I737facab0c849cb4b95756eefbf3ffd69e558b32
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/endian.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/src/include/endian.h b/src/include/endian.h
index d9199b4..297ffd7 100644
--- a/src/include/endian.h
+++ b/src/include/endian.h
@@ -88,4 +88,70 @@
 #define clrbits_8(addr, clear) clrsetbits_8(addr, clear, 0)
 #define setbits_8(addr, set) setbits_8(addr, 0, set)
 
+#ifndef __ROMCC__
+/*
+ * Portable (API) endian support that can be used in code that is shared
+ * with userspace (man 3 endian) tools.
+ */
+static inline uint16_t htobe16(uint16_t host_16bits)
+{
+	return cpu_to_be16(host_16bits);
+}
+
+static inline uint16_t htole16(uint16_t host_16bits)
+{
+	return cpu_to_le16(host_16bits);
+}
+
+static inline uint16_t be16toh(uint16_t big_endian_16bits)
+{
+	return be16_to_cpu(big_endian_16bits);
+}
+
+static inline uint16_t le16toh(uint16_t little_endian_16bits)
+{
+	return le16_to_cpu(little_endian_16bits);
+}
+
+static inline uint32_t htobe32(uint32_t host_32bits)
+{
+	return cpu_to_be32(host_32bits);
+}
+
+static inline uint32_t htole32(uint32_t host_32bits)
+{
+	return cpu_to_le32(host_32bits);
+}
+
+static inline uint32_t be32toh(uint32_t big_endian_32bits)
+{
+	return be32_to_cpu(big_endian_32bits);
+}
+
+static inline uint32_t le32toh(uint32_t little_endian_32bits)
+{
+	return le32_to_cpu(little_endian_32bits);
+}
+
+static inline uint64_t htobe64(uint64_t host_64bits)
+{
+	return cpu_to_be64(host_64bits);
+}
+
+static inline uint64_t htole64(uint64_t host_64bits)
+{
+	return cpu_to_le64(host_64bits);
+}
+
+static inline uint64_t be64toh(uint64_t big_endian_64bits)
+{
+	return be64_to_cpu(big_endian_64bits);
+}
+
+static inline uint64_t le64toh(uint64_t little_endian_64bits)
+{
+	return le16_to_cpu(little_endian_64bits);
+}
+#endif
+
 #endif


From gerrit at coreboot.org  Thu Sep 10 17:23:49 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 17:23:49 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	riscv-virtual-memory: Add virtual memory setup
References: <I46e080e0ee8dc13277d567dcd4bf0f61a4507b76+0@gerrit.coreboot.org>
Message-ID: <E1Za5Zd-0004vm-S3@mail.coreboot.org>

the following patch was just integrated into master:
commit b094583c6fd9d330be28ed6feb1c1140de07ff37
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Wed Aug 26 15:28:04 2015 -0700

    riscv-virtual-memory: Add virtual memory setup
    
    Execution in supervisor level code in RISCV requires early setup of
    virtual memory. Add initialization calls in
    src/arch/riscv/virtual_memory.c to implement the required page table
    setup, and helper functions to use when jumping to the payload correctly
    in riscv.
    
    Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
    Reviewed-on: http://review.coreboot.org/11369
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See http://review.coreboot.org/11369 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 17:26:45 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 17:26:45 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	riscv-trap-handling: Add implementation for trap calls in riscv
References: <Ie1d5f361595e48fa6cc1fac25485ad623ecdc717+0@gerrit.coreboot.org>
Message-ID: <E1Za5cT-0005QL-Fm@mail.coreboot.org>

the following patch was just integrated into master:
commit 95ba4c87f5f4802e2afaeae38003db5e7235864a
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Wed Aug 26 14:54:31 2015 -0700

    riscv-trap-handling: Add implementation for trap calls in riscv
    
    RISCV requires the bios/bootloader to set up an interface by which it
    can get information about memory, talk to host devices, etc. Put
    implementation for spike in
    src/mainboard/emulation/spike-riscv/spike_util.c, and
    src/arch/riscv/trap_handler.c
    
    Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
    Reviewed-on: http://review.coreboot.org/11368
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See http://review.coreboot.org/11368 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 17:27:35 2015
From: gerrit at coreboot.org (Ronald G. Minnich (rminnich@gmail.com))
Date: Thu, 10 Sep 2015 17:27:35 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: riscv-memlayout:
	fix existing memlayout issues, add sbi interface
References: <Id97fe75e45ac1361005bec6d421756ee3f98a508+0@gerrit.coreboot.org>
Message-ID: <Id97fe75e45ac1361005bec6d421756ee3f98a508+9@gerrit.coreboot.org>

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11370

-gerrit

commit 949e74f23463c552d2533fe320ec6801a31d8a23
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Wed Aug 26 15:39:16 2015 -0700

    riscv-memlayout: fix existing memlayout issues, add sbi interface
    
    Existing memlayout code placed sections in overlapping areas, and would
    overwrite the payload if it was large enough. Update memlayout.ld in
    src/mainboard/emulation/spike-riscv to represent the spike emulator, and
    add sbi interface which now has room into src/arch/riscv/bootblock.S.
    Update Makefile to include all the files necessary for sbi interface.
    
    Clean up unused include in src/arch/riscv/include/atomic.h and
    whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld
    
    Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
---
 src/arch/riscv/Makefile.inc                      |   3 +
 src/arch/riscv/bootblock.S                       | 108 ++++++++++++++++++++---
 src/arch/riscv/include/atomic.h                  |   1 -
 src/mainboard/emulation/spike-riscv/memlayout.ld |  10 +--
 4 files changed, 102 insertions(+), 20 deletions(-)

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 6fac99c..de6eb91 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -31,6 +31,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
 bootblock-y = bootblock.S stages.c
 bootblock-y += trap_util.S
 bootblock-y += trap_handler.c
+bootblock-y += virtual_memory.c
 bootblock-y += boot.c
 bootblock-y += rom_media.c
 bootblock-y += \
@@ -85,6 +86,8 @@ endif
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 
 ramstage-y =
+ramstage-y += trap_handler.c
+ramstage-y += virtual_memory.c
 ramstage-y += rom_media.c
 ramstage-y += stages.c
 ramstage-y += misc.c
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index a26b144..4caeea6 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -1,7 +1,7 @@
 /*
  * Early initialization code for aarch64 (a.k.a. armv8)
  *
- * Copyright 2013Google Inc.
+ * Copyright 2013 Google Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -22,34 +22,112 @@
 
 .section ".text._start", "ax", %progbits
 // Maybe there's a better way.
-.space 0x200
+# machine mode handler when in supervisor mode
+.space 0x140
+supervisor_machine_handler:
+  j supervisor_trap_entry
+
+# handler for when
+.space 0x7c
+.globl machine_handler
+machine_handler:
+#  call trap_handler
+  j trap_entry
+
+.space 0x3c
 .globl _start
 _start:
 
 	// pending figuring out this f-ing toolchain. Hardcode what we know works.
-//  la sp, 0x4ef0 // .stacktop
-//  la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv
-  la sp, 0x7FF00 // stack start + stack size
+  la sp, 0x80FFF0 // stack start + stack size
 
-  // make room for HLS
+  # make room for HLS and initialize it
   addi sp, sp, -64 // MENTRY_FRAME_SIZE
-
+  csrr a0, mhartid
+  call hls_init
 
   //poison the stack
-  la t1, 0x40000
+  la t1, 0x800000
   li t0, 0xdeadbeef
   sd t0, 0(t1)
 
-//  la gp, _gp
+  la t0, exception_handler
+  csrw stvec, t0
 
   # clear any pending interrupts
-#if __GNUC__ < 5
-  csrwi clear_ipi, 0
-#else
   csrwi sip, 0
-#endif
 
+  # set up the mstatus register for VM
+  call mstatus_init
   call main
+.=0x2000
+    .space 0x800
+# sbi interface lives here
+
+# hart_id
+.align 5
+li a7, 0
+ecall
+ret
+
+# num_harts
+.align 4
+li a0, 1
+ret
+
+# query_memory
+.align 4
+li a7, 8
+ecall
+ret
+
+# console_putchar
+.align 4
+li a7, 1
+ecall
+ret
+
+# send_device_request
+.align 4
+li a7, 2
+ecall
+ret
+
+# receive_device_response
+.align 4
+li a7, 3
+ecall
+ret
+
+# send ipi
+.align 4
+li a7, 4
+ecall
+ret
+
+# clear ipi
+.align 4
+li a7, 5
+ecall
+ret
+
+# timebase
+.align 4
+li a0, 10000000 # temporary, we should provide the correct answer
+ret
+
+# shutdown
+.align 4
+li a7, 6
+ecall
+
+# set_timer
+.align 4
+li a7, 7
+ecall
+ret
+
+# end of SBI trampolines
 .=0x4000
 .stack:
 .align 8
@@ -59,7 +137,9 @@ _start:
 .align 3
 .stack_size:
 	.quad 0xf00
-
+.globl test_trap
+exception_handler:
+        call trap_handler
 reset:
 init_stack_loop:
 
diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h
index 8d7295d..f63f6e1 100644
--- a/src/arch/riscv/include/atomic.h
+++ b/src/arch/riscv/include/atomic.h
@@ -3,7 +3,6 @@
 #ifndef _RISCV_ATOMIC_H
 #define _RISCV_ATOMIC_H
 
-//#include "config.h"
 #include <arch/encoding.h>
 
 #define disable_irqsave() clear_csr(sstatus, SSTATUS_IE)
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index 8801f35..8e2e7ee 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -23,10 +23,10 @@
 
 SECTIONS
 {
-	DRAM_START(0x0)
+        DRAM_START(0x0)
 	BOOTBLOCK(0x0, 64K)
-	ROMSTAGE(0x20000, 128K)
-	STACK(0x40000, 0x3ff00)
-	PRERAM_CBMEM_CONSOLE(0x80000, 8K)
-	RAMSTAGE(0x100000, 16M)
+        STACK(8M, 64K)
+	ROMSTAGE(8M + 64K, 128K)
+	PRERAM_CBMEM_CONSOLE(8M + 192k, 8K)
+	RAMSTAGE(8M + 200K, 256K)
 }


From gerrit at coreboot.org  Thu Sep 10 17:50:09 2015
From: gerrit at coreboot.org (Thaminda Edirisooriya (thaminda@google.com))
Date: Thu, 10 Sep 2015 17:50:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	riscv-trap-handling: add functionality and prevent stack corruption
References: <I1a7d3d4ae4bb3cbccaad39b5b3c4fbc01b6b4336+0@gerrit.coreboot.org>
Message-ID: <I1a7d3d4ae4bb3cbccaad39b5b3c4fbc01b6b4336+1@gerrit.coreboot.org>

Thaminda Edirisooriya (thaminda at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11619

-gerrit

commit 688d96c1358ece8cf4d3acca0e04718f698f3a95
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Thu Sep 10 10:46:20 2015 -0700

    riscv-trap-handling: add functionality and prevent stack corruption
    
    Trap handling code was bugged in that it loaded in the wrong stack
    pointer, overwriting the space the processor uses to talk to it's host
    for doing device requests. Fix this issue, as well as add misaligned
    load handling to match misaligned store.
    
    Change-Id: I1a7d3d4ae4bb3cbccaad39b5b3c4fbc01b6b4336
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
---
 src/arch/riscv/include/arch/exception.h |  2 +-
 src/arch/riscv/trap_handler.c           | 29 +++++++++++++++++++++++++++++
 src/arch/riscv/trap_util.S              |  2 +-
 src/arch/riscv/virtual_memory.c         |  2 +-
 4 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h
index 4318cba..28b9279 100644
--- a/src/arch/riscv/include/arch/exception.h
+++ b/src/arch/riscv/include/arch/exception.h
@@ -55,7 +55,7 @@ static inline void exception_init(void)
 
 void trap_handler(trapframe* tf);
 void handle_supervisor_call(trapframe* tf);
-//void handleMisalignedLoad(trapframe *tf);
+void handleMisalignedLoad(trapframe *tf);
 void handle_misaligned_store(trapframe *tf);
 
 #endif
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index d4c9b87..6148037 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -162,6 +162,35 @@ void trap_handler(trapframe *tf) {
 	while(1);
 }
 
+void handleMisalignedLoad(trapframe *tf) {
+	printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
+	printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
+	insn_t faultingInstruction = 0;
+	uintptr_t faultingInstructionAddr = tf->epc;
+	asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr));
+	asm("lw t0, 0(t0)");
+	asm("move %0, t0" : "=r"(faultingInstruction));
+	printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
+	insn_t widthMask = 0x7000;
+	insn_t memWidth = (faultingInstruction & widthMask) >> 12;
+	insn_t destMask = 0xF80;
+	insn_t destRegister = (faultingInstruction & destMask) >> 7;
+	printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth);
+	if (memWidth == 3) {
+		// load double, handle the issue
+		void* badAddress = (void*) tf->badvaddr;
+		memcpy(&(tf->gpr[destRegister]), badAddress, 8);
+	} else {
+		// panic, this should not have happened
+		printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n");
+		while(1);
+	}
+
+	// return to where we came from
+	write_csr(mepc, read_csr(mepc) + 4);
+	asm volatile("j machine_call_return");
+}
+
 void handle_misaligned_store(trapframe *tf) {
 	printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
 	printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 9701aaf..274dca6 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -112,7 +112,7 @@
 supervisor_trap_entry:
     csrw mscratch, sp
     # load in the top of the machine stack
-    la sp, 0x80FFF0
+    la sp, 0x80FFF0 - 64
     1:addi sp,sp,-320
     save_tf
     move  a0,sp
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 2095bfa..0163a45 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -107,7 +107,7 @@ void initVirtualMemory(void) {
 	printk(BIOS_DEBUG, "Initializing virtual memory...\n");
 	uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs
 	uintptr_t virtualStart = 0xffffffff81000000;
-	uintptr_t pageTableStart = 0x1f0000;
+	uintptr_t pageTableStart = 0x1400000;
 	init_vm(virtualStart, physicalStart, pageTableStart);
 	mb();
 	printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n");


From gerrit at coreboot.org  Thu Sep 10 17:52:22 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 10 Sep 2015 17:52:22 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: endian: add
	portable endian functions
References: <I737facab0c849cb4b95756eefbf3ffd69e558b32+0@gerrit.coreboot.org>
Message-ID: <I737facab0c849cb4b95756eefbf3ffd69e558b32+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11618

-gerrit

commit 8df2de044a494146c5bdd062ac69659927d5b0a5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 12:08:34 2015 -0500

    endian: add portable endian functions
    
    The current endian API support in coreboot doesn't follow
    any known API that can be shared in userland as well as coreboot
    proper. To that end provide big and little endian helper functions
    that can be used in code that can be shared within coreboot proper
    and userland tools.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi
    
    Change-Id: I737facab0c849cb4b95756eefbf3ffd69e558b32
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/endian.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/src/include/endian.h b/src/include/endian.h
index d9199b4..297ffd7 100644
--- a/src/include/endian.h
+++ b/src/include/endian.h
@@ -88,4 +88,70 @@
 #define clrbits_8(addr, clear) clrsetbits_8(addr, clear, 0)
 #define setbits_8(addr, set) setbits_8(addr, 0, set)
 
+#ifndef __ROMCC__
+/*
+ * Portable (API) endian support that can be used in code that is shared
+ * with userspace (man 3 endian) tools.
+ */
+static inline uint16_t htobe16(uint16_t host_16bits)
+{
+	return cpu_to_be16(host_16bits);
+}
+
+static inline uint16_t htole16(uint16_t host_16bits)
+{
+	return cpu_to_le16(host_16bits);
+}
+
+static inline uint16_t be16toh(uint16_t big_endian_16bits)
+{
+	return be16_to_cpu(big_endian_16bits);
+}
+
+static inline uint16_t le16toh(uint16_t little_endian_16bits)
+{
+	return le16_to_cpu(little_endian_16bits);
+}
+
+static inline uint32_t htobe32(uint32_t host_32bits)
+{
+	return cpu_to_be32(host_32bits);
+}
+
+static inline uint32_t htole32(uint32_t host_32bits)
+{
+	return cpu_to_le32(host_32bits);
+}
+
+static inline uint32_t be32toh(uint32_t big_endian_32bits)
+{
+	return be32_to_cpu(big_endian_32bits);
+}
+
+static inline uint32_t le32toh(uint32_t little_endian_32bits)
+{
+	return le32_to_cpu(little_endian_32bits);
+}
+
+static inline uint64_t htobe64(uint64_t host_64bits)
+{
+	return cpu_to_be64(host_64bits);
+}
+
+static inline uint64_t htole64(uint64_t host_64bits)
+{
+	return cpu_to_le64(host_64bits);
+}
+
+static inline uint64_t be64toh(uint64_t big_endian_64bits)
+{
+	return be64_to_cpu(big_endian_64bits);
+}
+
+static inline uint64_t le64toh(uint64_t little_endian_64bits)
+{
+	return le16_to_cpu(little_endian_64bits);
+}
+#endif
+
 #endif


From gerrit at coreboot.org  Thu Sep 10 17:52:32 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 17:52:32 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: fsp1_1:
	provide binding to UEFI version
References: <I894165942cfe36936e186af5221efa810be8bb29+0@gerrit.coreboot.org>
Message-ID: <E1Za61Q-0000GH-55@mail.coreboot.org>

the following patch was just integrated into master:
commit 789f2b6c435c7f31591e2c5e969ba96df21a191d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 9 17:05:06 2015 -0500

    fsp1_1: provide binding to UEFI version
    
    FSP has some unique attributes which makes integration
    cumbersome:
    
    1. FSP header files do not include the types they need. Like
       EDKII development it's expected types are provided by the
       build system. Therefore, one needs to include the proper
       files to avoid compilation issues.
    2. An implementation of FSP for a chipset may use different
       versions of the UEFI PI spec implementation. EDKII is a
       proxy for all of UEFI specifications. In order to provide
       flexibility one needs to binding a set of types and
       structures from an UEFI PI implementation.
    3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
       file which defines it's own types. Commonality between
       FSP chipset implementations are only named typedef
       structs. The fields within are not consistent. And
       because of FSP's insistence on typedefs it makes it
       near impossible to forward declare structs.
    
    The above 3 means one needs to include the correct UEFI
    type bindings when working with FSP. The current
    implementation had the SoC picking include paths in the
    edk2 directory and using a bare <uefi_types.h> include.
    Also, with the prior fsp_util.h implementation the SoC's
    FSP FspUpdVpd.h header file was required since for providing
    all the types at once (Generic FSP 1.1 and SoC types).
    
    The binding has been changed in the following manner:
    1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
       selects. No other bindings are currently available,
       but this provides the policy.
    2. Based on CONFIG_UEFI_2_4_BINDING the proper include
       paths are added to the CPPFLAGS_common.
    3. SoC Makefile.inc does not bind UEFI types nor does
       it adjust CPPFLAGS_common in any way.
    4. Provide a include/fsp directory under fsp1_1 and
       expose src/drivers/intel/fsp1_1/include in the
       include path. This split can allow a version 2,
       for example, FSP to provide its own include files.
       Yes, that means there needs to be consistency in
       APIs, however that's not this patch.
    5. Provide a way for code to differentiate the FSP spec
       types (fsp/api.h) from the chipset FSP types
       (fsp/soc_binding.h). This allows for code re-use that
       doesn't need the chipset types to be defined such as
       the FSP relocation code.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted on glados.
    
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
    
    Change-Id: I894165942cfe36936e186af5221efa810be8bb29
    Reviewed-on: http://review.coreboot.org/11606
    Reviewed-by: Duncan Laurie <dlaurie at google.com>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11606 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 17:52:50 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 17:52:50 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: endian: add
	portable endian functions
References: <I737facab0c849cb4b95756eefbf3ffd69e558b32+0@gerrit.coreboot.org>
Message-ID: <E1Za61i-0000Jq-3T@mail.coreboot.org>

the following patch was just integrated into master:
commit 94a74998c08fd485656175faf0cba6583f615070
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 12:08:34 2015 -0500

    endian: add portable endian functions
    
    The current endian API support in coreboot doesn't follow
    any known API that can be shared in userland as well as coreboot
    proper. To that end provide big and little endian helper functions
    that can be used in code that can be shared within coreboot proper
    and userland tools.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi
    
    Change-Id: I737facab0c849cb4b95756eefbf3ffd69e558b32
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11618
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.h at gmx.de>


See http://review.coreboot.org/11618 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 10 17:58:32 2015
From: gerrit at coreboot.org (Thaminda Edirisooriya (thaminda@google.com))
Date: Thu, 10 Sep 2015 17:58:32 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	riscv-trap-handling: Add functionality, prevent stack corruption
References: <I68ba3a114b7167b3212bb0bed181a7595f0b97d8+0@gerrit.coreboot.org>
Message-ID: <I68ba3a114b7167b3212bb0bed181a7595f0b97d8+1@gerrit.coreboot.org>

Thaminda Edirisooriya (thaminda at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11620

-gerrit

commit f0191cdb5d60905939f70fec4a36c38cdfb627d8
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Thu Sep 10 10:55:17 2015 -0700

    riscv-trap-handling: Add functionality, prevent stack corruption
    
    Trap handling code was bugged in that it loaded in the wrong stack
    pointer, overwriting the space the processor uses to talk to its host
    for doing device requests. Fix this issue, as well as add support for
    handling misaligned loads the same way we handle misaligned stores.
    
    Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
---
 src/arch/riscv/include/arch/exception.h |  2 +-
 src/arch/riscv/trap_handler.c           | 29 +++++++++++++++++++++++++++++
 src/arch/riscv/trap_util.S              |  2 +-
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h
index 4318cba..28b9279 100644
--- a/src/arch/riscv/include/arch/exception.h
+++ b/src/arch/riscv/include/arch/exception.h
@@ -55,7 +55,7 @@ static inline void exception_init(void)
 
 void trap_handler(trapframe* tf);
 void handle_supervisor_call(trapframe* tf);
-//void handleMisalignedLoad(trapframe *tf);
+void handleMisalignedLoad(trapframe *tf);
 void handle_misaligned_store(trapframe *tf);
 
 #endif
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index d4c9b87..6148037 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -162,6 +162,35 @@ void trap_handler(trapframe *tf) {
 	while(1);
 }
 
+void handleMisalignedLoad(trapframe *tf) {
+	printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
+	printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
+	insn_t faultingInstruction = 0;
+	uintptr_t faultingInstructionAddr = tf->epc;
+	asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr));
+	asm("lw t0, 0(t0)");
+	asm("move %0, t0" : "=r"(faultingInstruction));
+	printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
+	insn_t widthMask = 0x7000;
+	insn_t memWidth = (faultingInstruction & widthMask) >> 12;
+	insn_t destMask = 0xF80;
+	insn_t destRegister = (faultingInstruction & destMask) >> 7;
+	printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth);
+	if (memWidth == 3) {
+		// load double, handle the issue
+		void* badAddress = (void*) tf->badvaddr;
+		memcpy(&(tf->gpr[destRegister]), badAddress, 8);
+	} else {
+		// panic, this should not have happened
+		printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n");
+		while(1);
+	}
+
+	// return to where we came from
+	write_csr(mepc, read_csr(mepc) + 4);
+	asm volatile("j machine_call_return");
+}
+
 void handle_misaligned_store(trapframe *tf) {
 	printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
 	printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 9701aaf..274dca6 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -112,7 +112,7 @@
 supervisor_trap_entry:
     csrw mscratch, sp
     # load in the top of the machine stack
-    la sp, 0x80FFF0
+    la sp, 0x80FFF0 - 64
     1:addi sp,sp,-320
     save_tf
     move  a0,sp


From gerrit at coreboot.org  Thu Sep 10 18:02:01 2015
From: gerrit at coreboot.org (Thaminda Edirisooriya (thaminda@google.com))
Date: Thu, 10 Sep 2015 18:02:01 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	riscv-virtual-memory: move page tables into virtual address space
References: <I1d99e46f38a38a163fb1c7c517b1abca80cde0dc+0@gerrit.coreboot.org>
Message-ID: <I1d99e46f38a38a163fb1c7c517b1abca80cde0dc+1@gerrit.coreboot.org>

Thaminda Edirisooriya (thaminda at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11621

-gerrit

commit 7128feece369b2b8a7e59b73b049ad5a55d8817b
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Thu Sep 10 10:58:58 2015 -0700

    riscv-virtual-memory: move page tables into virtual address space
    
    If we use a linux payload/any payload that wants to manage virtual
    memory, and the payload is a supervisor (thus requiring virtual
    addressing before being started), we need to make sure that the page
    table is mapped into the virtual address space. Move the start address
    of the tables so the payload can manage virtual memory.
    
    Change-Id: I1d99e46f38a38a163fb1c7c517b1abca80cde0dc
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
---
 src/arch/riscv/virtual_memory.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 2095bfa..0163a45 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -107,7 +107,7 @@ void initVirtualMemory(void) {
 	printk(BIOS_DEBUG, "Initializing virtual memory...\n");
 	uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs
 	uintptr_t virtualStart = 0xffffffff81000000;
-	uintptr_t pageTableStart = 0x1f0000;
+	uintptr_t pageTableStart = 0x1400000;
 	init_vm(virtualStart, physicalStart, pageTableStart);
 	mb();
 	printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n");


From gerrit at coreboot.org  Thu Sep 10 20:11:37 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 10 Sep 2015 20:11:37 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	Revive ffs()
References: <I4e3fc15816b778e640bceea0d89cd9624d271c2e+0@gerrit.coreboot.org>
Message-ID: <E1Za8C1-0007JF-1R@mail.coreboot.org>

the following patch was just integrated into master:
commit 66cc843f3d70a38c44f49077bcc7663ad685aef4
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue Sep 8 17:14:08 2015 +0200

    libpayload: Revive ffs()
    
    Revive ffs() in a more fancy way (that is more likely to be accepted).
    We dropped it in
      7a8a4ab lib: Unify log2() and related functions
    but there is at least one user: flashrom.
    
    Change-Id: I4e3fc15816b778e640bceea0d89cd9624d271c2e
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
    Signed-off-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: http://review.coreboot.org/11591
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.h at gmx.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11591 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep 11 02:02:13 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 11 Sep 2015 02:02:13 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: ifdtool:
	Enable warnings as errors, and fix any issues
References: <Id462a10c2affac54ec48a1cc2a5b2ca66112848e+0@gerrit.coreboot.org>
Message-ID: <E1ZaDfJ-0002WB-Nm@mail.coreboot.org>

the following patch was just integrated into master:
commit 71a7ba2e5d84198e63464287c8543d23c5d75e48
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Thu Sep 10 08:37:42 2015 -0700

    ifdtool: Enable warnings as errors, and fix any issues
    
    Change-Id: Id462a10c2affac54ec48a1cc2a5b2ca66112848e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11613
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11613 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep 11 03:30:52 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 03:30:52 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: endian: fix
	le64toh()
References: <If6f49c3c2b7908f93a99c23a80536ad5937959c7+0@gerrit.coreboot.org>
Message-ID: <If6f49c3c2b7908f93a99c23a80536ad5937959c7+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11622

-gerrit

commit c9bdc8a1c31f1200908bab1a283737a0635b1b40
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 22:27:55 2015 -0500

    endian: fix le64toh()
    
    This change was sitting in my git index, and I
    failed to push it in the original patch.
    
    Change-Id: If6f49c3c2b7908f93a99c23a80536ad5937959c7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/endian.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/include/endian.h b/src/include/endian.h
index 297ffd7..b9f1dee 100644
--- a/src/include/endian.h
+++ b/src/include/endian.h
@@ -150,7 +150,7 @@ static inline uint64_t be64toh(uint64_t big_endian_64bits)
 
 static inline uint64_t le64toh(uint64_t little_endian_64bits)
 {
-	return le16_to_cpu(little_endian_64bits);
+	return le64_to_cpu(little_endian_64bits);
 }
 #endif
 


From gerrit at coreboot.org  Fri Sep 11 05:19:42 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 05:19:42 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: expose
	rmodule logic
References: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+0@gerrit.coreboot.org>
Message-ID: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11598

-gerrit

commit 8123d9eb968ca53ea11298b98444c6c892678eda
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 17:24:04 2015 -0500

    cbfstool: expose rmodule logic
    
    In order to allow cbfstool to add XIP romstage on x86 without
    doing the 'cbfstool locate', relink, then 'cbfstool add' dance
    expose the core logic and of rmodule including proving an optional
    filter. The filter will be used for ignoring relocations to the
    .car.global region.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 62 ++++++++++++++++---------------------------------
 util/cbfstool/rmodule.h | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+), 42 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 03828f7..46c9384 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -24,39 +24,6 @@
 #include "rmodule.h"
 #include "../../src/include/rmodule-defs.h"
 
-struct rmod_context;
-
-struct arch_ops {
-	int arch;
-	/* Determine if relocation is a valid type for the architecture. */
-	int (*valid_type)(Elf64_Rela *rel);
-	/* Determine if relocation should be emitted. */
-	int (*should_emit)(Elf64_Rela *rel);
-};
-
-struct rmod_context {
-	/* Ops to process relocations. */
-	struct arch_ops *ops;
-
-	/* endian conversion ops */
-	struct xdr *xdr;
-
-	/* Parsed ELF sturcture. */
-	struct parsed_elf pelf;
-	/* Program segment. */
-	Elf64_Phdr *phdr;
-
-	/* Collection of relocation addresses fixup in the module. */
-	Elf64_Xword nrelocs;
-	Elf64_Addr *emitted_relocs;
-
-	/* The following fields are addresses within the linked program.  */
-	Elf64_Addr parameters_begin;
-	Elf64_Addr parameters_end;
-	Elf64_Addr bss_begin;
-	Elf64_Addr bss_end;
-};
-
 /*
  * Architecture specific support operations.
  */
@@ -130,7 +97,7 @@ static int should_emit_aarch64(Elf64_Rela *rel)
 	return (type == R_AARCH64_ABS64);
 }
 
-static struct arch_ops reloc_ops[] = {
+static const struct arch_ops reloc_ops[] = {
 	{
 		.arch = EM_386,
 		.valid_type = valid_reloc_386,
@@ -152,7 +119,8 @@ static struct arch_ops reloc_ops[] = {
  * Relocation processing loops.
  */
 
-static int for_each_reloc(struct rmod_context *ctx, int do_emit)
+static int for_each_reloc(struct rmod_context *ctx, struct reloc_filter *f,
+				int do_emit)
 {
 	Elf64_Half i;
 	struct parsed_elf *pelf = &ctx->pelf;
@@ -173,6 +141,7 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 		nrelocs = shdr->sh_size / shdr->sh_entsize;
 
 		for (j = 0; j < nrelocs; j++) {
+			int filter_emit = 1;
 			Elf64_Rela *r = &relocs[j];
 
 			if (!ctx->ops->valid_type(r)) {
@@ -181,7 +150,15 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 				return -1;
 			}
 
-			if (ctx->ops->should_emit(r)) {
+			/* Allow the provided filter to have precedence. */
+			if (f != NULL) {
+				filter_emit = f->filter(f, r);
+
+				if (filter_emit < 0)
+					return filter_emit;
+			}
+
+			if (filter_emit && ctx->ops->should_emit(r)) {
 				int n = ctx->nrelocs;
 				if (do_emit)
 					ctx->emitted_relocs[n] = r->r_offset;
@@ -303,7 +280,8 @@ static int vaddr_cmp(const void *a, const void *b)
 	return 0;
 }
 
-static int collect_relocations(struct rmod_context *ctx)
+int rmodule_collect_relocations(struct rmod_context *ctx,
+				struct reloc_filter *f)
 {
 	Elf64_Xword nrelocs;
 
@@ -312,7 +290,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	 * apply to the program. Count the number relocations. Then collect
 	 * them into the allocated buffer.
 	 */
-	if (for_each_reloc(ctx, 0))
+	if (for_each_reloc(ctx, f, 0))
 		return -1;
 
 	nrelocs = ctx->nrelocs;
@@ -324,7 +302,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	ctx->nrelocs = 0;
 	ctx->emitted_relocs = calloc(nrelocs, sizeof(Elf64_Addr));
 	/* Write out the relocations into the emitted_relocs array. */
-	if (for_each_reloc(ctx, 1))
+	if (for_each_reloc(ctx, f, 1))
 		return -1;
 
 	if (ctx->nrelocs != nrelocs) {
@@ -618,7 +596,7 @@ out:
 	return ret;
 }
 
-static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
 	struct parsed_elf *pelf;
 	int i;
@@ -670,7 +648,7 @@ out:
 	return ret;
 }
 
-static void rmodule_cleanup(struct rmod_context *ctx)
+void rmodule_cleanup(struct rmod_context *ctx)
 {
 	free(ctx->emitted_relocs);
 	parsed_elf_destroy(&ctx->pelf);
@@ -684,7 +662,7 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	if (rmodule_init(&ctx, elfin))
 		goto out;
 
-	if (collect_relocations(&ctx))
+	if (rmodule_collect_relocations(&ctx, NULL))
 		goto out;
 
 	if (populate_rmodule_info(&ctx))
diff --git a/util/cbfstool/rmodule.h b/util/cbfstool/rmodule.h
index 4531f8d..f3d750d 100644
--- a/util/cbfstool/rmodule.h
+++ b/util/cbfstool/rmodule.h
@@ -21,10 +21,71 @@
 #include "elf.h"
 #include "common.h"
 
+struct arch_ops {
+	int arch;
+	/* Determine if relocation is a valid type for the architecture. */
+	int (*valid_type)(Elf64_Rela *rel);
+	/* Determine if relocation should be emitted. */
+	int (*should_emit)(Elf64_Rela *rel);
+};
+
+/*
+ * The fields in rmod_context are read-only to the user. These are
+ * exposed for easy shareability.
+ */
+struct rmod_context {
+	/* Ops to process relocations. */
+	const struct arch_ops *ops;
+
+	/* endian conversion ops */
+	struct xdr *xdr;
+
+	/* Parsed ELF sturcture. */
+	struct parsed_elf pelf;
+	/* Program segment. */
+	Elf64_Phdr *phdr;
+
+	/* Collection of relocation addresses fixup in the module. */
+	Elf64_Xword nrelocs;
+	Elf64_Addr *emitted_relocs;
+
+	/* The following fields are addresses within the linked program.  */
+	Elf64_Addr parameters_begin;
+	Elf64_Addr parameters_end;
+	Elf64_Addr bss_begin;
+	Elf64_Addr bss_end;
+};
+
+struct reloc_filter {
+	/* Return < 0 on error. 0 to ignore relocation and 1 to include
+	 * relocation. */
+	int (*filter)(struct reloc_filter *f, const Elf64_Rela *r);
+	/* Pointer for filter provides */
+	void *context;
+};
+
 /*
  * Parse an ELF file within the elfin buffer and fill in the elfout buffer
  * with a created rmodule in ELF format. Return 0 on success, < 0 on error.
  */
 int rmodule_create(const struct buffer *elfin, struct buffer *elfout);
 
+/*
+ * Initialize an rmodule context from an ELF buffer. Returns 0 on scucess, < 0
+ * on error.
+ */
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin);
+
+/*
+ * Collect all the relocations that apply to the program in
+ * nrelocs/emitted_relocs. One can optionally provide a reloc_filter object
+ * to help in relocation filtering. The filter function will be called twice:
+ * once for counting and once for emitting. The same response should be
+ * provided for each call. Returns 0 on success, < 0 on error.
+ */
+int rmodule_collect_relocations(struct rmod_context *c, struct reloc_filter *f);
+
+/* Clean up the memory consumed by the rmdoule context. */
+void rmodule_cleanup(struct rmod_context *ctx);
+
 #endif /* TOOL_RMODULE_H */


From gerrit at coreboot.org  Fri Sep 11 05:19:46 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 05:19:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: corebot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 082d54d4c644663f75b9fb8e24d269122734bee8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    corebot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                                       |   4 +-
 src/arch/x86/include/arch/cbfs.h                   |   2 +-
 src/arch/x86/romcc_console.c                       |   2 +-
 src/commonlib/Makefile.inc                         |  10 ++
 src/commonlib/include/commonlib/cbfs_serialized.h  | 190 ++++++++++++++++++++
 src/commonlib/include/commonlib/cbmem_id.h         | 113 ++++++++++++
 src/commonlib/include/commonlib/fmap_serialized.h  |  73 ++++++++
 src/commonlib/include/commonlib/helpers.h          |  51 ++++++
 src/commonlib/include/commonlib/loglevel.h         | 178 +++++++++++++++++++
 src/commonlib/include/commonlib/mem_pool.h         |  73 ++++++++
 src/commonlib/include/commonlib/region.h           | 157 +++++++++++++++++
 src/commonlib/include/commonlib/rmodule-defs.h     |  63 +++++++
 src/commonlib/mem_pool.c                           |  51 ++++++
 src/commonlib/region.c                             | 196 +++++++++++++++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |   2 +-
 src/include/assets.h                               |   2 +-
 src/include/boot_device.h                          |   2 +-
 src/include/cbfs.h                                 |   4 +-
 src/include/cbfs_serialized.h                      | 190 --------------------
 src/include/cbmem.h                                |   2 +-
 src/include/cbmem_id.h                             | 113 ------------
 src/include/console/console.h                      |   2 +-
 src/include/console/early_print.h                  |   2 +-
 src/include/console/loglevel.h                     | 178 -------------------
 src/include/fmap.h                                 |   4 +-
 src/include/fmap_serialized.h                      |  73 --------
 src/include/mem_pool.h                             |  73 --------
 src/include/region.h                               | 157 -----------------
 src/include/rmodule-defs.h                         |  63 -------
 src/include/rmodule.h                              |   2 +-
 src/include/stddef.h                               |  34 +---
 src/include/stdlib.h                               |  14 --
 src/lib/Makefile.inc                               |   9 -
 src/lib/cbfs_boot_props.c                          |   2 +-
 src/lib/fmap.c                                     |   2 +-
 src/lib/mem_pool.c                                 |  51 ------
 src/lib/region.c                                   | 196 ---------------------
 src/mainboard/advansus/a785e-i/romstage.c          |   2 +-
 src/mainboard/amd/bimini_fam10/romstage.c          |   2 +-
 src/mainboard/amd/dinar/romstage.c                 |   2 +-
 src/mainboard/amd/inagua/romstage.c                |   2 +-
 src/mainboard/amd/lamar/romstage.c                 |   2 +-
 src/mainboard/amd/mahogany_fam10/romstage.c        |   2 +-
 src/mainboard/amd/olivehill/romstage.c             |   2 +-
 src/mainboard/amd/olivehillplus/romstage.c         |   2 +-
 src/mainboard/amd/parmer/romstage.c                |   2 +-
 src/mainboard/amd/persimmon/romstage.c             |   2 +-
 .../amd/serengeti_cheetah_fam10/romstage.c         |   2 +-
 src/mainboard/amd/south_station/romstage.c         |   2 +-
 src/mainboard/amd/thatcher/romstage.c              |   2 +-
 src/mainboard/amd/tilapia_fam10/romstage.c         |   2 +-
 src/mainboard/amd/torpedo/romstage.c               |   2 +-
 src/mainboard/amd/union_station/romstage.c         |   2 +-
 src/mainboard/asrock/e350m1/romstage.c             |   2 +-
 src/mainboard/asrock/imb-a180/romstage.c           |   2 +-
 src/mainboard/asus/m4a78-em/romstage.c             |   2 +-
 src/mainboard/asus/m4a785-m/romstage.c             |   2 +-
 src/mainboard/asus/m5a88-v/romstage.c              |   2 +-
 src/mainboard/avalue/eax-785e/romstage.c           |   2 +-
 src/mainboard/bap/ode_e20XX/romstage.c             |   2 +-
 src/mainboard/biostar/am1ml/romstage.c             |   2 +-
 src/mainboard/gigabyte/ma785gm/romstage.c          |   2 +-
 src/mainboard/gigabyte/ma785gmt/romstage.c         |   2 +-
 src/mainboard/gigabyte/ma78gm/romstage.c           |   2 +-
 src/mainboard/gizmosphere/gizmo/romstage.c         |   2 +-
 src/mainboard/gizmosphere/gizmo2/romstage.c        |   2 +-
 src/mainboard/google/peach_pit/romstage.c          |   2 +-
 src/mainboard/hp/abm/romstage.c                    |   2 +-
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |   2 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |   2 +-
 src/mainboard/jetway/pa78vm5/romstage.c            |   2 +-
 src/mainboard/lippert/frontrunner-af/romstage.c    |   2 +-
 src/mainboard/lippert/toucan-af/romstage.c         |   2 +-
 src/mainboard/pcengines/apu1/romstage.c            |   2 +-
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |   2 +-
 src/soc/intel/broadwell/include/soc/me.h           |   2 +-
 src/southbridge/amd/cimx/sb700/Platform.h          |   2 +-
 src/southbridge/amd/cimx/sb700/early.c             |   2 +-
 src/southbridge/amd/cimx/sb900/early.c             |   2 +-
 src/vendorcode/amd/agesa/common/Porting.h          |   2 +-
 src/vendorcode/amd/pi/00630F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c    |   2 +-
 src/vendorcode/amd/pi/00730F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/Makefile.inc                 |   1 +
 src/vendorcode/google/chromeos/vboot_common.h      |   2 +-
 util/cbfstool/Makefile                             |   1 +
 util/cbfstool/Makefile.inc                         |   1 +
 util/cbfstool/rmodule.c                            |   2 +-
 util/cbmem/Makefile                                |   2 +-
 util/cbmem/cbmem.c                                 |   2 +-
 91 files changed, 1228 insertions(+), 1217 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..34f3411 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
 #ifndef __INCLUDE_ARCH_CBFS__
 #define __INCLUDE_ARCH_CBFS__
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
 #include <endian.h>
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
 #include <build.h>
 #include <console/streams.h>
 #include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* Include the sources. */
 #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_PAYLOAD    0x20
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+	uint32_t compression;  /** Compression type */
+	uint64_t entry;  /** entry point */
+	uint64_t load;   /** Where to load in memory */
+	uint32_t len;          /** length of data to load */
+	uint32_t memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __attribute__((packed));
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 9695b3b..b3772a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
 #include <fsp/soc_binding.h>
 #include <fsp/gop.h>
 #include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
 #ifndef ASSETS_H
 #define ASSETS_H
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* An asset represents data used to boot the system. It can be found within
  * CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
 #ifndef _BOOT_DEVICE_H_
 #define _BOOT_DEVICE_H_
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* Return the region_device for the read-only boot device. */
 const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
 #include <program_loading.h>
-#include <region.h>
 
 /*
  * CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
-    algorithms that coreboot knows about for stages and
-    payloads.  Of course, other CBFS users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE      0x10
-#define CBFS_TYPE_PAYLOAD    0x20
-#define CBFS_TYPE_OPTIONROM  0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW        0x50
-#define CBFS_TYPE_VSA        0x51
-#define CBFS_TYPE_MBI        0x52
-#define CBFS_TYPE_MICROCODE  0x53
-#define CBFS_TYPE_FSP        0x60
-#define CBFS_TYPE_MRC        0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD          0xab
-#define CBFS_TYPE_MRC_CACHE    0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
-	uint32_t magic;
-	uint32_t version;
-	uint32_t romsize;
-	uint32_t bootblocksize;
-	uint32_t align; /* fixed to 64 bytes */
-	uint32_t offset;
-	uint32_t architecture;
-	uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARM      0x00000010
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	uint32_t len;
-	uint32_t type;
-	uint32_t checksum;
-	uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	uint32_t compression;  /** Compression type */
-	uint64_t entry;  /** entry point */
-	uint64_t load;   /** Where to load in memory */
-	uint32_t len;          /** length of data to load */
-	uint32_t memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	uint32_t type;
-	uint32_t compression;
-	uint32_t offset;
-	uint64_t load_addr;
-	uint32_t len;
-	uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	uint32_t compression;
-	uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
 #include <rules.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <rules.h>
 #include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef __ROMCC__
 struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
 
 #include <console/console.h>
 #include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* While in romstage, console loglevel is built-time constant.
  * With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
 #ifndef _FMAP_H_
 #define _FMAP_H_
 
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
 
 /* Locate the fmap directory. Return 0 on success, < 0 on error. */
 int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *    * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE		"__FMAP__"
-#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
-#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
-#define FMAP_STRLEN		32	/* maximum length for strings, */
-					/* including null-terminator */
-
-enum fmap_flags {
-	FMAP_AREA_STATIC	= 1 << 0,
-	FMAP_AREA_COMPRESSED	= 1 << 1,
-	FMAP_AREA_RO		= 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
-	uint32_t offset;                /* offset relative to base */
-	uint32_t size;                  /* size in bytes */
-	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
-	uint16_t flags;                 /* flags for this area */
-}  __attribute__((packed));
-
-struct fmap {
-	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
-	uint8_t  ver_major;		/* major version */
-	uint8_t  ver_minor;		/* minor version */
-	uint64_t base;			/* address of the firmware binary */
-	uint32_t size;			/* size of firmware binary in bytes */
-	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
-	uint16_t nareas;		/* number of areas described by
-					   fmap_areas[] below */
-	struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
 
 enum {
 	RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <commonlib/helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
 
 #include <stddef.h>
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a)           ALIGN((x),(a))
-#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-
 #define min(a,b) MIN((a),(b))
 #define max(a,b) MAX((a),(b))
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* This function is marked as weak to allow a particular platform to
  * override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
 #include <stddef.h>
 #include <string.h>
 
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
 #include <spd.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <commonlib/region.h>
 #include <console/console.h>
 #include <device/i2c.h>
 #include <drivers/maxim/max77802/max77802.h>
 #include <program_loading.h>
-#include <region.h>
 #include <soc/clk.h>
 #include <soc/cpu.h>
 #include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
 #define ME_DELAY		10	/* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
 
 #include <cpu/amd/common/cbtypes.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #ifdef NULL
 #undef NULL
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
 #include "sb_cimx.h"
 #include "sb700_cfg.h"                /*sb700_cimx_config*/
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
 #include "SbPlatform.h"
 #include "sb_cimx.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
 #include "amdlib.h"
 #include "cbfs.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 // TODO Add a kconfig option to name the AGESA ROM file in CBFS
 #define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
 #include <assert.h>
 #include <config.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
 #define VBOOT_COMMON_H
 
 #include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* The FW areas consist of multiple components. At the beginning of
  * each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
 
 /*
  * Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..1d8ad6d 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86 -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..33d6493 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -51,7 +51,7 @@ typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
+#include <cbmem_id.h>
 #include "timestamp.h"
 
 #define CBMEM_VERSION "1.1"


From gerrit at coreboot.org  Fri Sep 11 05:19:53 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 05:19:53 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prepare
	for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <I176d0ae0ae1933cdf6adac67d393ba676198861a+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11595

-gerrit

commit c1fe67fdded0f4feb46e181e90ce05ba1cff89a7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 69 ++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 1f41d17..03828f7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,14 +50,11 @@ struct rmod_context {
 	Elf64_Xword nrelocs;
 	Elf64_Addr *emitted_relocs;
 
-	/* The following fields are addresses within the linked program. */
-	Elf64_Addr link_addr;
-	Elf64_Addr entry;
+	/* The following fields are addresses within the linked program.  */
 	Elf64_Addr parameters_begin;
 	Elf64_Addr parameters_end;
 	Elf64_Addr bss_begin;
 	Elf64_Addr bss_end;
-	Elf64_Xword size;
 };
 
 /*
@@ -371,7 +368,7 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 	return -1;
 }
 
-static int populate_program_info(struct rmod_context *ctx)
+static int populate_rmodule_info(struct rmod_context *ctx)
 {
 	int i;
 	const char *strtab;
@@ -423,15 +420,6 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
-	/* Honor the entry point within the ELF header. */
-	ctx->entry = ehdr->e_entry;
-
-	/* Link address is the virtual address of the program segment. */
-	ctx->link_addr = ctx->phdr->p_vaddr;
-
-	/* The program size is the memsz of the program segment. */
-	ctx->size = ctx->phdr->p_memsz;
-
 	return 0;
 }
 
@@ -516,7 +504,6 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 
 	/* Create ELF writer with modified entry point. */
 	memcpy(&ehdr, &ctx->pelf.ehdr, sizeof(ehdr));
-	ehdr.e_entry = ctx->entry;
 	ew = elf_writer_init(&ehdr);
 
 	if (ew == NULL) {
@@ -544,11 +531,11 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 		loc += ctx->nrelocs * sizeof(Elf32_Addr);
 	ctx->xdr->put32(&rmod_header, loc);
 	/* module_link_start_address */
-	ctx->xdr->put32(&rmod_header, ctx->link_addr);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_vaddr);
 	/* module_program_size */
-	ctx->xdr->put32(&rmod_header, ctx->size);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_memsz);
 	/* module_entry_point */
-	ctx->xdr->put32(&rmod_header, ctx->entry);
+	ctx->xdr->put32(&rmod_header, ctx->pelf.ehdr.e_entry);
 	/* parameters_begin */
 	ctx->xdr->put32(&rmod_header, ctx->parameters_begin);
 	/* parameters_end */
@@ -631,16 +618,15 @@ out:
 	return ret;
 }
 
-int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
-	struct rmod_context ctx;
 	struct parsed_elf *pelf;
 	int i;
 	int ret;
 
 	ret = -1;
-	memset(&ctx, 0, sizeof(ctx));
-	pelf = &ctx.pelf;
+	memset(ctx, 0, sizeof(*ctx));
+	pelf = &ctx->pelf;
 
 	if (parse_elf(elfin, pelf, ELF_PARSE_ALL)) {
 		ERROR("Couldn't parse ELF!\n");
@@ -656,32 +642,52 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	/* Determine if architecture is supported. */
 	for (i = 0; i < ARRAY_SIZE(reloc_ops); i++) {
 		if (reloc_ops[i].arch == pelf->ehdr.e_machine) {
-			ctx.ops = &reloc_ops[i];
+			ctx->ops = &reloc_ops[i];
 			break;
 		}
 	}
 
-	if (ctx.ops == NULL) {
+	if (ctx->ops == NULL) {
 		ERROR("ELF is unsupported arch: %u.\n", pelf->ehdr.e_machine);
 		goto out;
 	}
 
 	/* Set the endian ops. */
-	if (ctx.pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
-		ctx.xdr = &xdr_be;
+	if (ctx->pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
+		ctx->xdr = &xdr_be;
 	else
-		ctx.xdr = &xdr_le;
+		ctx->xdr = &xdr_le;
 
-	if (find_program_segment(&ctx))
+	if (find_program_segment(ctx))
 		goto out;
 
-	if (filter_relocation_sections(&ctx))
+	if (filter_relocation_sections(ctx))
+		goto out;
+
+	ret = 0;
+
+out:
+	return ret;
+}
+
+static void rmodule_cleanup(struct rmod_context *ctx)
+{
+	free(ctx->emitted_relocs);
+	parsed_elf_destroy(&ctx->pelf);
+}
+
+int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+{
+	struct rmod_context ctx;
+	int ret = -1;
+
+	if (rmodule_init(&ctx, elfin))
 		goto out;
 
 	if (collect_relocations(&ctx))
 		goto out;
 
-	if (populate_program_info(&ctx))
+	if (populate_rmodule_info(&ctx))
 		goto out;
 
 	if (write_elf(&ctx, elfin, elfout))
@@ -690,7 +696,6 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	ret = 0;
 
 out:
-	free(ctx.emitted_relocs);
-	parsed_elf_destroy(pelf);
+	rmodule_cleanup(&ctx);
 	return ret;
 }


From gerrit at coreboot.org  Fri Sep 11 05:20:07 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 11 Sep 2015 05:20:07 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: endian: fix
	le64toh()
References: <If6f49c3c2b7908f93a99c23a80536ad5937959c7+0@gerrit.coreboot.org>
Message-ID: <E1ZaGkp-0007Ac-5r@mail.coreboot.org>

the following patch was just integrated into master:
commit 113d821696c25f508e2b98c3ecd749e3c92ac118
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 22:27:55 2015 -0500

    endian: fix le64toh()
    
    This change was sitting in my git index, and I
    failed to push it in the original patch.
    
    Change-Id: If6f49c3c2b7908f93a99c23a80536ad5937959c7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11622
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>
    Tested-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11622 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep 11 05:40:01 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 05:40:01 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: expose
	rmodule logic
References: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+0@gerrit.coreboot.org>
Message-ID: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11598

-gerrit

commit 560fbcd2db67dc37d0bb78fcb501703367909800
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 17:24:04 2015 -0500

    cbfstool: expose rmodule logic
    
    In order to allow cbfstool to add XIP romstage on x86 without
    doing the 'cbfstool locate', relink, then 'cbfstool add' dance
    expose the core logic and of rmodule including proving an optional
    filter. The filter will be used for ignoring relocations to the
    .car.global region.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 62 ++++++++++++++++---------------------------------
 util/cbfstool/rmodule.h | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+), 42 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 03828f7..46c9384 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -24,39 +24,6 @@
 #include "rmodule.h"
 #include "../../src/include/rmodule-defs.h"
 
-struct rmod_context;
-
-struct arch_ops {
-	int arch;
-	/* Determine if relocation is a valid type for the architecture. */
-	int (*valid_type)(Elf64_Rela *rel);
-	/* Determine if relocation should be emitted. */
-	int (*should_emit)(Elf64_Rela *rel);
-};
-
-struct rmod_context {
-	/* Ops to process relocations. */
-	struct arch_ops *ops;
-
-	/* endian conversion ops */
-	struct xdr *xdr;
-
-	/* Parsed ELF sturcture. */
-	struct parsed_elf pelf;
-	/* Program segment. */
-	Elf64_Phdr *phdr;
-
-	/* Collection of relocation addresses fixup in the module. */
-	Elf64_Xword nrelocs;
-	Elf64_Addr *emitted_relocs;
-
-	/* The following fields are addresses within the linked program.  */
-	Elf64_Addr parameters_begin;
-	Elf64_Addr parameters_end;
-	Elf64_Addr bss_begin;
-	Elf64_Addr bss_end;
-};
-
 /*
  * Architecture specific support operations.
  */
@@ -130,7 +97,7 @@ static int should_emit_aarch64(Elf64_Rela *rel)
 	return (type == R_AARCH64_ABS64);
 }
 
-static struct arch_ops reloc_ops[] = {
+static const struct arch_ops reloc_ops[] = {
 	{
 		.arch = EM_386,
 		.valid_type = valid_reloc_386,
@@ -152,7 +119,8 @@ static struct arch_ops reloc_ops[] = {
  * Relocation processing loops.
  */
 
-static int for_each_reloc(struct rmod_context *ctx, int do_emit)
+static int for_each_reloc(struct rmod_context *ctx, struct reloc_filter *f,
+				int do_emit)
 {
 	Elf64_Half i;
 	struct parsed_elf *pelf = &ctx->pelf;
@@ -173,6 +141,7 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 		nrelocs = shdr->sh_size / shdr->sh_entsize;
 
 		for (j = 0; j < nrelocs; j++) {
+			int filter_emit = 1;
 			Elf64_Rela *r = &relocs[j];
 
 			if (!ctx->ops->valid_type(r)) {
@@ -181,7 +150,15 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 				return -1;
 			}
 
-			if (ctx->ops->should_emit(r)) {
+			/* Allow the provided filter to have precedence. */
+			if (f != NULL) {
+				filter_emit = f->filter(f, r);
+
+				if (filter_emit < 0)
+					return filter_emit;
+			}
+
+			if (filter_emit && ctx->ops->should_emit(r)) {
 				int n = ctx->nrelocs;
 				if (do_emit)
 					ctx->emitted_relocs[n] = r->r_offset;
@@ -303,7 +280,8 @@ static int vaddr_cmp(const void *a, const void *b)
 	return 0;
 }
 
-static int collect_relocations(struct rmod_context *ctx)
+int rmodule_collect_relocations(struct rmod_context *ctx,
+				struct reloc_filter *f)
 {
 	Elf64_Xword nrelocs;
 
@@ -312,7 +290,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	 * apply to the program. Count the number relocations. Then collect
 	 * them into the allocated buffer.
 	 */
-	if (for_each_reloc(ctx, 0))
+	if (for_each_reloc(ctx, f, 0))
 		return -1;
 
 	nrelocs = ctx->nrelocs;
@@ -324,7 +302,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	ctx->nrelocs = 0;
 	ctx->emitted_relocs = calloc(nrelocs, sizeof(Elf64_Addr));
 	/* Write out the relocations into the emitted_relocs array. */
-	if (for_each_reloc(ctx, 1))
+	if (for_each_reloc(ctx, f, 1))
 		return -1;
 
 	if (ctx->nrelocs != nrelocs) {
@@ -618,7 +596,7 @@ out:
 	return ret;
 }
 
-static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
 	struct parsed_elf *pelf;
 	int i;
@@ -670,7 +648,7 @@ out:
 	return ret;
 }
 
-static void rmodule_cleanup(struct rmod_context *ctx)
+void rmodule_cleanup(struct rmod_context *ctx)
 {
 	free(ctx->emitted_relocs);
 	parsed_elf_destroy(&ctx->pelf);
@@ -684,7 +662,7 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	if (rmodule_init(&ctx, elfin))
 		goto out;
 
-	if (collect_relocations(&ctx))
+	if (rmodule_collect_relocations(&ctx, NULL))
 		goto out;
 
 	if (populate_rmodule_info(&ctx))
diff --git a/util/cbfstool/rmodule.h b/util/cbfstool/rmodule.h
index 4531f8d..f3d750d 100644
--- a/util/cbfstool/rmodule.h
+++ b/util/cbfstool/rmodule.h
@@ -21,10 +21,71 @@
 #include "elf.h"
 #include "common.h"
 
+struct arch_ops {
+	int arch;
+	/* Determine if relocation is a valid type for the architecture. */
+	int (*valid_type)(Elf64_Rela *rel);
+	/* Determine if relocation should be emitted. */
+	int (*should_emit)(Elf64_Rela *rel);
+};
+
+/*
+ * The fields in rmod_context are read-only to the user. These are
+ * exposed for easy shareability.
+ */
+struct rmod_context {
+	/* Ops to process relocations. */
+	const struct arch_ops *ops;
+
+	/* endian conversion ops */
+	struct xdr *xdr;
+
+	/* Parsed ELF sturcture. */
+	struct parsed_elf pelf;
+	/* Program segment. */
+	Elf64_Phdr *phdr;
+
+	/* Collection of relocation addresses fixup in the module. */
+	Elf64_Xword nrelocs;
+	Elf64_Addr *emitted_relocs;
+
+	/* The following fields are addresses within the linked program.  */
+	Elf64_Addr parameters_begin;
+	Elf64_Addr parameters_end;
+	Elf64_Addr bss_begin;
+	Elf64_Addr bss_end;
+};
+
+struct reloc_filter {
+	/* Return < 0 on error. 0 to ignore relocation and 1 to include
+	 * relocation. */
+	int (*filter)(struct reloc_filter *f, const Elf64_Rela *r);
+	/* Pointer for filter provides */
+	void *context;
+};
+
 /*
  * Parse an ELF file within the elfin buffer and fill in the elfout buffer
  * with a created rmodule in ELF format. Return 0 on success, < 0 on error.
  */
 int rmodule_create(const struct buffer *elfin, struct buffer *elfout);
 
+/*
+ * Initialize an rmodule context from an ELF buffer. Returns 0 on scucess, < 0
+ * on error.
+ */
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin);
+
+/*
+ * Collect all the relocations that apply to the program in
+ * nrelocs/emitted_relocs. One can optionally provide a reloc_filter object
+ * to help in relocation filtering. The filter function will be called twice:
+ * once for counting and once for emitting. The same response should be
+ * provided for each call. Returns 0 on success, < 0 on error.
+ */
+int rmodule_collect_relocations(struct rmod_context *c, struct reloc_filter *f);
+
+/* Clean up the memory consumed by the rmdoule context. */
+void rmodule_cleanup(struct rmod_context *ctx);
+
 #endif /* TOOL_RMODULE_H */


From gerrit at coreboot.org  Fri Sep 11 05:40:08 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 05:40:08 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: corebot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 6e0f1ed6134dc85fe3a611d669878fc129d48888
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    corebot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                                       |    4 +-
 src/arch/x86/include/arch/cbfs.h                   |    2 +-
 src/arch/x86/romcc_console.c                       |    2 +-
 src/commonlib/Makefile.inc                         |   10 +
 src/commonlib/include/commonlib/cbfs_serialized.h  |  190 ++
 src/commonlib/include/commonlib/cbmem_id.h         |  113 ++
 src/commonlib/include/commonlib/coreboot_tables.h  |  387 ++++
 src/commonlib/include/commonlib/fmap_serialized.h  |   73 +
 src/commonlib/include/commonlib/helpers.h          |   51 +
 src/commonlib/include/commonlib/loglevel.h         |  178 ++
 src/commonlib/include/commonlib/mem_pool.h         |   73 +
 src/commonlib/include/commonlib/region.h           |  157 ++
 src/commonlib/include/commonlib/rmodule-defs.h     |   63 +
 .../include/commonlib/timestamp_serialized.h       |   92 +
 src/commonlib/mem_pool.c                           |   51 +
 src/commonlib/region.c                             |  196 +++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |    2 +-
 src/include/assets.h                               |    2 +-
 src/include/boot/coreboot_tables.h                 |  384 +---
 src/include/boot_device.h                          |    2 +-
 src/include/cbfs.h                                 |    4 +-
 src/include/cbfs_serialized.h                      |  190 --
 src/include/cbmem.h                                |    2 +-
 src/include/cbmem_id.h                             |  113 --
 src/include/console/console.h                      |    2 +-
 src/include/console/early_print.h                  |    2 +-
 src/include/console/loglevel.h                     |  178 --
 src/include/fmap.h                                 |    4 +-
 src/include/fmap_serialized.h                      |   73 -
 src/include/mem_pool.h                             |   73 -
 src/include/region.h                               |  157 --
 src/include/rmodule-defs.h                         |   63 -
 src/include/rmodule.h                              |    2 +-
 src/include/stddef.h                               |   34 +-
 src/include/stdlib.h                               |   14 -
 src/include/timestamp.h                            |   69 +-
 src/lib/Makefile.inc                               |    9 -
 src/lib/cbfs_boot_props.c                          |    2 +-
 src/lib/fmap.c                                     |    2 +-
 src/lib/mem_pool.c                                 |   51 -
 src/lib/region.c                                   |  196 ---
 src/mainboard/advansus/a785e-i/romstage.c          |    2 +-
 src/mainboard/amd/bimini_fam10/romstage.c          |    2 +-
 src/mainboard/amd/dinar/romstage.c                 |    2 +-
 src/mainboard/amd/inagua/romstage.c                |    2 +-
 src/mainboard/amd/lamar/romstage.c                 |    2 +-
 src/mainboard/amd/mahogany_fam10/romstage.c        |    2 +-
 src/mainboard/amd/olivehill/romstage.c             |    2 +-
 src/mainboard/amd/olivehillplus/romstage.c         |    2 +-
 src/mainboard/amd/parmer/romstage.c                |    2 +-
 src/mainboard/amd/persimmon/romstage.c             |    2 +-
 .../amd/serengeti_cheetah_fam10/romstage.c         |    2 +-
 src/mainboard/amd/south_station/romstage.c         |    2 +-
 src/mainboard/amd/thatcher/romstage.c              |    2 +-
 src/mainboard/amd/tilapia_fam10/romstage.c         |    2 +-
 src/mainboard/amd/torpedo/romstage.c               |    2 +-
 src/mainboard/amd/union_station/romstage.c         |    2 +-
 src/mainboard/asrock/e350m1/romstage.c             |    2 +-
 src/mainboard/asrock/imb-a180/romstage.c           |    2 +-
 src/mainboard/asus/m4a78-em/romstage.c             |    2 +-
 src/mainboard/asus/m4a785-m/romstage.c             |    2 +-
 src/mainboard/asus/m5a88-v/romstage.c              |    2 +-
 src/mainboard/avalue/eax-785e/romstage.c           |    2 +-
 src/mainboard/bap/ode_e20XX/romstage.c             |    2 +-
 src/mainboard/biostar/am1ml/romstage.c             |    2 +-
 src/mainboard/gigabyte/ma785gm/romstage.c          |    2 +-
 src/mainboard/gigabyte/ma785gmt/romstage.c         |    2 +-
 src/mainboard/gigabyte/ma78gm/romstage.c           |    2 +-
 src/mainboard/gizmosphere/gizmo/romstage.c         |    2 +-
 src/mainboard/gizmosphere/gizmo2/romstage.c        |    2 +-
 src/mainboard/google/peach_pit/romstage.c          |    2 +-
 src/mainboard/hp/abm/romstage.c                    |    2 +-
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |    2 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |    2 +-
 src/mainboard/jetway/pa78vm5/romstage.c            |    2 +-
 src/mainboard/lippert/frontrunner-af/romstage.c    |    2 +-
 src/mainboard/lippert/toucan-af/romstage.c         |    2 +-
 src/mainboard/pcengines/apu1/romstage.c            |    2 +-
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |    2 +-
 src/soc/intel/broadwell/include/soc/me.h           |    2 +-
 src/southbridge/amd/cimx/sb700/Platform.h          |    2 +-
 src/southbridge/amd/cimx/sb700/early.c             |    2 +-
 src/southbridge/amd/cimx/sb900/early.c             |    2 +-
 src/vendorcode/amd/agesa/common/Porting.h          |    2 +-
 src/vendorcode/amd/pi/00630F01/Porting.h           |    2 +-
 src/vendorcode/amd/pi/00660F01/Porting.h           |    2 +-
 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c    |    2 +-
 src/vendorcode/amd/pi/00730F01/Porting.h           |    2 +-
 src/vendorcode/amd/pi/Makefile.inc                 |    1 +
 src/vendorcode/google/chromeos/vboot_common.h      |    2 +-
 util/cbfstool/Makefile                             |    1 +
 util/cbfstool/Makefile.inc                         |    1 +
 util/cbfstool/fmd_parser.c                         | 1648 +++++++++++++++++
 util/cbfstool/fmd_parser.h                         |  109 ++
 util/cbfstool/fmd_scanner.c                        | 1853 ++++++++++++++++++++
 util/cbfstool/fmd_scanner.h                        |  333 ++++
 util/cbfstool/rmodule.c                            |    2 +-
 util/cbmem/Makefile                                |    2 +-
 util/cbmem/cbmem.c                                 |    9 +-
 99 files changed, 5654 insertions(+), 1673 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..34f3411 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
 #ifndef __INCLUDE_ARCH_CBFS__
 #define __INCLUDE_ARCH_CBFS__
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
 #include <endian.h>
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
 #include <build.h>
 #include <console/streams.h>
 #include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* Include the sources. */
 #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_PAYLOAD    0x20
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+	uint32_t compression;  /** Compression type */
+	uint64_t entry;  /** entry point */
+	uint64_t load;   /** Where to load in memory */
+	uint32_t len;          /** length of data to load */
+	uint32_t memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image.  Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing.   For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed.  This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ *   a particular motherboard is constructed? (Assuming the kernel
+ *   has drivers for all of the hardware but it does not have
+ *   assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not.  This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped.  Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+	uint64_t result;
+	result = value.hi;
+	result = (result << 32) + value.lo;
+	return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+	struct lb_uint64 result;
+	result.lo = (value >> 0) & 0xffffffff;
+	result.hi = (value >> 32) & 0xffffffff;
+	return result;
+}
+
+struct lb_header
+{
+	uint8_t  signature[4]; /* LBIO */
+	uint32_t header_bytes;
+	uint32_t header_checksum;
+	uint32_t table_bytes;
+	uint32_t table_checksum;
+	uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record.  Encoding both type and size.  The type is obviously
+ * so you can tell what it is.  The size allows you to skip that
+ * boot environment record if you don't know what it is.  This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+	uint32_t tag;		/* tag ID */
+	uint32_t size;		/* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED		0x0000
+
+#define LB_TAG_MEMORY		0x0001
+
+struct lb_memory_range {
+	struct lb_uint64 start;
+	struct lb_uint64 size;
+	uint32_t type;
+#define LB_MEM_RAM		 1	/* Memory anyone can use */
+#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
+#define LB_MEM_ACPI		 3	/* ACPI Tables */
+#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
+#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
+#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+	uint32_t tag;
+	uint32_t size;
+	struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB		0x0002
+struct lb_hwrpb {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
+#define LB_TAG_VERSION		0x0004
+#define LB_TAG_EXTRA_VERSION	0x0005
+#define LB_TAG_BUILD		0x0006
+#define LB_TAG_COMPILE_TIME	0x0007
+#define LB_TAG_COMPILE_BY	0x0008
+#define LB_TAG_COMPILE_HOST	0x0009
+#define LB_TAG_COMPILE_DOMAIN	0x000a
+#define LB_TAG_COMPILER		0x000b
+#define LB_TAG_LINKER		0x000c
+#define LB_TAG_ASSEMBLER	0x000d
+struct lb_string {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP	0x0026
+struct lb_timestamp {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL		0x000f
+struct lb_serial {
+	uint32_t tag;
+	uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
+	uint32_t baud;
+	uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE		0x0010
+struct lb_console {
+	uint32_t tag;
+	uint32_t size;
+	uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250	0
+#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI		5
+#define LB_TAG_CONSOLE_SERIAL8250MEM	6
+
+#define LB_TAG_FORWARD		0x0011
+struct lb_forward {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER	0x0012
+struct lb_framebuffer {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t physical_address;
+	uint32_t x_resolution;
+	uint32_t y_resolution;
+	uint32_t bytes_per_line;
+	uint8_t bits_per_pixel;
+	uint8_t red_mask_pos;
+	uint8_t red_mask_size;
+	uint8_t green_mask_pos;
+	uint8_t green_mask_size;
+	uint8_t blue_mask_pos;
+	uint8_t blue_mask_size;
+	uint8_t reserved_mask_pos;
+	uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT		0x0015
+#define LB_TAG_VBNV		0x0019
+#define LB_TAB_VBOOT_HANDOFF	0x0020
+#define LB_TAB_DMA		0x0022
+#define LB_TAG_RAM_OOPS		0x0023
+#define LB_TAG_MTC		0x002b
+struct lb_range {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t range_start;
+	uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+#define LB_TAG_ACPI_GNVS	0x0024
+#define LB_TAG_WIFI_CALIBRATION	0x0027
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR	0x0021
+struct lb_x86_rom_mtrr {
+	uint32_t tag;
+	uint32_t size;
+	/* The variable range MTRR index covering the ROM. */
+	uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID		0x0025
+struct lb_board_id {
+	uint32_t tag;
+	uint32_t size;
+	/* Board ID as retrieved from the board revision GPIOs. */
+	uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS	0x0026
+struct mac_address {
+	uint8_t mac_addr[6];
+	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t count;
+	struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE		0x0028
+struct lb_ram_code {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH	0x0029
+struct lb_spi_flash {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t flash_size;
+	uint32_t sector_size;
+	uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+	uint32_t tag;
+	uint32_t size;
+	/* offsets are relative to start of boot media */
+	uint64_t fmap_offset;
+	uint64_t cbfs_offset;
+	uint64_t cbfs_size;
+	uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO		0x002a
+#define MAX_SERIALNO_LENGTH	32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+	uint32_t tag;               /* CMOS definitions table type */
+	uint32_t size;               /* size of the entire table */
+	uint32_t header_length;      /* length of header */
+};
+
+/* cmos entry record
+        This record is variable length.  The name field may be
+        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+        anywhere in the byte, but can not span bytes unless it
+        starts at the beginning of the byte and the length is
+        fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+	uint32_t tag;                /* entry type */
+	uint32_t size;               /* length of this record */
+	uint32_t bit;                /* starting bit from start of image */
+	uint32_t length;             /* length of field in bits */
+	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
+	uint32_t config_id;          /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+					       variable length int aligned */
+};
+
+
+/* cmos enumerations record
+        This record is variable length.  The text field may be
+        shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+	uint32_t tag;		     /* enumeration type */
+	uint32_t size; 		     /* length of this record */
+	uint32_t config_id;          /* a number identifying the config id */
+	uint32_t value;              /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+						variable length int aligned */
+};
+
+/* cmos defaults record
+        This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+	uint32_t tag;                /* default type */
+	uint32_t size;               /* length of this record */
+	uint32_t name_length;        /* length of the following name field */
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct	cmos_checksum {
+	uint32_t tag;
+	uint32_t size;
+	/* In practice everything is byte aligned, but things are measured
+	 * in bits to be consistent.
+	 */
+	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
+	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
+	uint32_t location;	/* First bit of the checksum (byte aligned) */
+	uint32_t type;		/* Checksum algorithm that is used */
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __attribute__((packed));
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint16_t	max_entries;
+	uint16_t	tick_freq_mhz;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_VBOOT = 5,
+	TS_END_VBOOT = 6,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_START_BOOTBLOCK = 11,
+	TS_END_BOOTBLOCK = 12,
+	TS_START_COPYROM = 13,
+	TS_END_COPYROM = 14,
+	TS_START_ULZMA = 15,
+	TS_END_ULZMA = 16,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+
+	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+	TS_START_COPYVER = 501,
+	TS_END_COPYVER = 502,
+	TS_START_TPMINIT = 503,
+	TS_END_TPMINIT = 504,
+	TS_START_VERIFY_SLOT = 505,
+	TS_END_VERIFY_SLOT = 506,
+	TS_START_HASH_BODY = 507,
+	TS_DONE_LOADING = 508,
+	TS_DONE_HASHING = 509,
+	TS_END_HASH_BODY = 510,
+
+	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+	TS_FSP_MEMORY_INIT_START = 950,
+	TS_FSP_MEMORY_INIT_END = 951,
+	TS_FSP_TEMP_RAM_EXIT_START = 952,
+	TS_FSP_TEMP_RAM_EXIT_END = 953,
+	TS_FSP_SILICON_INIT_START = 954,
+	TS_FSP_SILICON_INIT_END = 955,
+	TS_FSP_BEFORE_ENUMERATE = 956,
+	TS_FSP_AFTER_ENUMERATE = 957,
+	TS_FSP_BEFORE_FINALIZE = 958,
+	TS_FSP_AFTER_FINALIZE = 959,
+
+	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 9695b3b..b3772a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
 #include <fsp/soc_binding.h>
 #include <fsp/gop.h>
 #include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
 #ifndef ASSETS_H
 #define ASSETS_H
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* An asset represents data used to boot the system. It can be found within
  * CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
 #ifndef COREBOOT_TABLES_H
 #define COREBOOT_TABLES_H
 
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image.  Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing.   For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed.  This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- *   a particular motherboard is constructed? (Assuming the kernel
- *   has drivers for all of the hardware but it does not have
- *   assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not.  This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped.  Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
-	uint32_t lo;
-	uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
-	uint64_t result;
-	result = value.hi;
-	result = (result << 32) + value.lo;
-	return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
-	struct lb_uint64 result;
-	result.lo = (value >> 0) & 0xffffffff;
-	result.hi = (value >> 32) & 0xffffffff;
-	return result;
-}
-
-struct lb_header
-{
-	uint8_t  signature[4]; /* LBIO */
-	uint32_t header_bytes;
-	uint32_t header_checksum;
-	uint32_t table_bytes;
-	uint32_t table_checksum;
-	uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record.  Encoding both type and size.  The type is obviously
- * so you can tell what it is.  The size allows you to skip that
- * boot environment record if you don't know what it is.  This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
-	uint32_t tag;		/* tag ID */
-	uint32_t size;		/* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED		0x0000
-
-#define LB_TAG_MEMORY		0x0001
-
-struct lb_memory_range {
-	struct lb_uint64 start;
-	struct lb_uint64 size;
-	uint32_t type;
-#define LB_MEM_RAM		 1	/* Memory anyone can use */
-#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
-#define LB_MEM_ACPI		 3	/* ACPI Tables */
-#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
-#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
-#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
-	uint32_t tag;
-	uint32_t size;
-	struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB		0x0002
-struct lb_hwrpb {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD	0x0003
-struct lb_mainboard {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  vendor_idx;
-	uint8_t  part_number_idx;
-	uint8_t  strings[0];
-};
-
-#define LB_TAG_VERSION		0x0004
-#define LB_TAG_EXTRA_VERSION	0x0005
-#define LB_TAG_BUILD		0x0006
-#define LB_TAG_COMPILE_TIME	0x0007
-#define LB_TAG_COMPILE_BY	0x0008
-#define LB_TAG_COMPILE_HOST	0x0009
-#define LB_TAG_COMPILE_DOMAIN	0x000a
-#define LB_TAG_COMPILER		0x000b
-#define LB_TAG_LINKER		0x000c
-#define LB_TAG_ASSEMBLER	0x000d
-struct lb_string {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP	0x0026
-struct lb_timestamp {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL		0x000f
-struct lb_serial {
-	uint32_t tag;
-	uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED     1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
-	uint32_t type;
-	uint32_t baseaddr;
-	uint32_t baud;
-	uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE		0x0010
-struct lb_console {
-	uint32_t tag;
-	uint32_t size;
-	uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250	0
-#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI		5
-#define LB_TAG_CONSOLE_SERIAL8250MEM	6
-
-#define LB_TAG_FORWARD		0x0011
-struct lb_forward {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER	0x0012
-struct lb_framebuffer {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t physical_address;
-	uint32_t x_resolution;
-	uint32_t y_resolution;
-	uint32_t bytes_per_line;
-	uint8_t bits_per_pixel;
-	uint8_t red_mask_pos;
-	uint8_t red_mask_size;
-	uint8_t green_mask_pos;
-	uint8_t green_mask_size;
-	uint8_t blue_mask_pos;
-	uint8_t blue_mask_size;
-	uint8_t reserved_mask_pos;
-	uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO	0x0013
-
-struct lb_gpio {
-	uint32_t port;
-	uint32_t polarity;
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-	uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
-        uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
-	uint32_t tag;
-	uint32_t size;
-
-	uint32_t count;
-	struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT		0x0015
-#define LB_TAG_VBNV		0x0019
-#define LB_TAB_VBOOT_HANDOFF	0x0020
-#define LB_TAB_DMA		0x0022
-#define LB_TAG_RAM_OOPS		0x0023
-#define LB_TAG_MTC		0x002b
-struct lb_range {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t range_start;
-	uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS	0x0016
-#define LB_TAG_CBMEM_CONSOLE	0x0017
-#define LB_TAG_MRC_CACHE	0x0018
-#define LB_TAG_ACPI_GNVS	0x0024
-#define LB_TAG_WIFI_CALIBRATION	0x0027
-struct lb_cbmem_ref {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR	0x0021
-struct lb_x86_rom_mtrr {
-	uint32_t tag;
-	uint32_t size;
-	/* The variable range MTRR index covering the ROM. */
-	uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID		0x0025
-struct lb_board_id {
-	uint32_t tag;
-	uint32_t size;
-	/* Board ID as retrieved from the board revision GPIOs. */
-	uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS	0x0026
-struct mac_address {
-	uint8_t mac_addr[6];
-	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t count;
-	struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE		0x0028
-struct lb_ram_code {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH	0x0029
-struct lb_spi_flash {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t flash_size;
-	uint32_t sector_size;
-	uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
-	uint32_t tag;
-	uint32_t size;
-	/* offsets are relative to start of boot media */
-	uint64_t fmap_offset;
-	uint64_t cbfs_offset;
-	uint64_t cbfs_size;
-	uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO		0x002a
-#define MAX_SERIALNO_LENGTH	32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
-	uint32_t tag;               /* CMOS definitions table type */
-	uint32_t size;               /* size of the entire table */
-	uint32_t header_length;      /* length of header */
-};
-
-/* cmos entry record
-        This record is variable length.  The name field may be
-        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
-        anywhere in the byte, but can not span bytes unless it
-        starts at the beginning of the byte and the length is
-        fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
-	uint32_t tag;                /* entry type */
-	uint32_t size;               /* length of this record */
-	uint32_t bit;                /* starting bit from start of image */
-	uint32_t length;             /* length of field in bits */
-	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
-	uint32_t config_id;          /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
-					       variable length int aligned */
-};
-
-
-/* cmos enumerations record
-        This record is variable length.  The text field may be
-        shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
-	uint32_t tag;		     /* enumeration type */
-	uint32_t size; 		     /* length of this record */
-	uint32_t config_id;          /* a number identifying the config id */
-	uint32_t value;              /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
-	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
-						variable length int aligned */
-};
-
-/* cmos defaults record
-        This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
-	uint32_t tag;                /* default type */
-	uint32_t size;               /* length of this record */
-	uint32_t name_length;        /* length of the following name field */
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
-	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct	cmos_checksum {
-	uint32_t tag;
-	uint32_t size;
-	/* In practice everything is byte aligned, but things are measured
-	 * in bits to be consistent.
-	 */
-	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
-	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
-	uint32_t location;	/* First bit of the checksum (byte aligned) */
-	uint32_t type;		/* Checksum algorithm that is used */
-#define CHECKSUM_NONE	0
-#define CHECKSUM_PCBIOS	1
-};
-
+#include <commonlib/coreboot_tables.h>
 /* function prototypes for building the coreboot table */
 
 unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
 #ifndef _BOOT_DEVICE_H_
 #define _BOOT_DEVICE_H_
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* Return the region_device for the read-only boot device. */
 const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
 #include <program_loading.h>
-#include <region.h>
 
 /*
  * CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
-    algorithms that coreboot knows about for stages and
-    payloads.  Of course, other CBFS users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE      0x10
-#define CBFS_TYPE_PAYLOAD    0x20
-#define CBFS_TYPE_OPTIONROM  0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW        0x50
-#define CBFS_TYPE_VSA        0x51
-#define CBFS_TYPE_MBI        0x52
-#define CBFS_TYPE_MICROCODE  0x53
-#define CBFS_TYPE_FSP        0x60
-#define CBFS_TYPE_MRC        0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD          0xab
-#define CBFS_TYPE_MRC_CACHE    0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
-	uint32_t magic;
-	uint32_t version;
-	uint32_t romsize;
-	uint32_t bootblocksize;
-	uint32_t align; /* fixed to 64 bytes */
-	uint32_t offset;
-	uint32_t architecture;
-	uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARM      0x00000010
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	uint32_t len;
-	uint32_t type;
-	uint32_t checksum;
-	uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	uint32_t compression;  /** Compression type */
-	uint64_t entry;  /** entry point */
-	uint64_t load;   /** Where to load in memory */
-	uint32_t len;          /** length of data to load */
-	uint32_t memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	uint32_t type;
-	uint32_t compression;
-	uint32_t offset;
-	uint64_t load_addr;
-	uint32_t len;
-	uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	uint32_t compression;
-	uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
 #include <rules.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <rules.h>
 #include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef __ROMCC__
 struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
 
 #include <console/console.h>
 #include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* While in romstage, console loglevel is built-time constant.
  * With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
 #ifndef _FMAP_H_
 #define _FMAP_H_
 
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
 
 /* Locate the fmap directory. Return 0 on success, < 0 on error. */
 int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *    * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE		"__FMAP__"
-#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
-#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
-#define FMAP_STRLEN		32	/* maximum length for strings, */
-					/* including null-terminator */
-
-enum fmap_flags {
-	FMAP_AREA_STATIC	= 1 << 0,
-	FMAP_AREA_COMPRESSED	= 1 << 1,
-	FMAP_AREA_RO		= 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
-	uint32_t offset;                /* offset relative to base */
-	uint32_t size;                  /* size in bytes */
-	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
-	uint16_t flags;                 /* flags for this area */
-}  __attribute__((packed));
-
-struct fmap {
-	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
-	uint8_t  ver_major;		/* major version */
-	uint8_t  ver_minor;		/* minor version */
-	uint64_t base;			/* address of the firmware binary */
-	uint32_t size;			/* size of firmware binary in bytes */
-	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
-	uint16_t nareas;		/* number of areas described by
-					   fmap_areas[] below */
-	struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
 
 enum {
 	RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <commonlib/helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
 
 #include <stddef.h>
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a)           ALIGN((x),(a))
-#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-
 #define min(a,b) MIN((a),(b))
 #define max(a,b) MAX((a),(b))
 
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
 #ifndef __TIMESTAMP_H__
 #define __TIMESTAMP_H__
 
-#include <stdint.h>
-
-struct timestamp_entry {
-	uint32_t	entry_id;
-	uint64_t	entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
-	uint64_t	base_time;
-	uint16_t	max_entries;
-	uint16_t	tick_freq_mhz;
-	uint32_t	num_entries;
-	struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
-	TS_START_ROMSTAGE = 1,
-	TS_BEFORE_INITRAM = 2,
-	TS_AFTER_INITRAM = 3,
-	TS_END_ROMSTAGE = 4,
-	TS_START_VBOOT = 5,
-	TS_END_VBOOT = 6,
-	TS_START_COPYRAM = 8,
-	TS_END_COPYRAM = 9,
-	TS_START_RAMSTAGE = 10,
-	TS_START_BOOTBLOCK = 11,
-	TS_END_BOOTBLOCK = 12,
-	TS_START_COPYROM = 13,
-	TS_END_COPYROM = 14,
-	TS_START_ULZMA = 15,
-	TS_END_ULZMA = 16,
-	TS_DEVICE_ENUMERATE = 30,
-	TS_DEVICE_CONFIGURE = 40,
-	TS_DEVICE_ENABLE = 50,
-	TS_DEVICE_INITIALIZE = 60,
-	TS_DEVICE_DONE = 70,
-	TS_CBMEM_POST = 75,
-	TS_WRITE_TABLES = 80,
-	TS_LOAD_PAYLOAD = 90,
-	TS_ACPI_WAKE_JUMP = 98,
-	TS_SELFBOOT_JUMP = 99,
-
-	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
-	TS_START_COPYVER = 501,
-	TS_END_COPYVER = 502,
-	TS_START_TPMINIT = 503,
-	TS_END_TPMINIT = 504,
-	TS_START_VERIFY_SLOT = 505,
-	TS_END_VERIFY_SLOT = 506,
-	TS_START_HASH_BODY = 507,
-	TS_DONE_LOADING = 508,
-	TS_DONE_HASHING = 509,
-	TS_END_HASH_BODY = 510,
-
-	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
-	TS_FSP_MEMORY_INIT_START = 950,
-	TS_FSP_MEMORY_INIT_END = 951,
-	TS_FSP_TEMP_RAM_EXIT_START = 952,
-	TS_FSP_TEMP_RAM_EXIT_END = 953,
-	TS_FSP_SILICON_INIT_START = 954,
-	TS_FSP_SILICON_INIT_END = 955,
-	TS_FSP_BEFORE_ENUMERATE = 956,
-	TS_FSP_AFTER_ENUMERATE = 957,
-	TS_FSP_BEFORE_FINALIZE = 958,
-	TS_FSP_AFTER_FINALIZE = 959,
-
-	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
 
 #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
 /*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* This function is marked as weak to allow a particular platform to
  * override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
 #include <stddef.h>
 #include <string.h>
 
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
 #include <spd.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <commonlib/region.h>
 #include <console/console.h>
 #include <device/i2c.h>
 #include <drivers/maxim/max77802/max77802.h>
 #include <program_loading.h>
-#include <region.h>
 #include <soc/clk.h>
 #include <soc/cpu.h>
 #include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
 #define ME_DELAY		10	/* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
 
 #include <cpu/amd/common/cbtypes.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #ifdef NULL
 #undef NULL
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
 #include "sb_cimx.h"
 #include "sb700_cfg.h"                /*sb700_cimx_config*/
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
 #include "SbPlatform.h"
 #include "sb_cimx.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
 #include "amdlib.h"
 #include "cbfs.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 // TODO Add a kconfig option to name the AGESA ROM file in CBFS
 #define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
 #include <assert.h>
 #include <config.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
 #define VBOOT_COMMON_H
 
 #include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* The FW areas consist of multiple components. At the beginning of
  * each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/fmd_parser.c b/util/cbfstool/fmd_parser.c
new file mode 100644
index 0000000..d463393
--- /dev/null
+++ b/util/cbfstool/fmd_parser.c
@@ -0,0 +1,1648 @@
+/* A Bison parser, made by GNU Bison 3.0.2.  */
+
+/* Bison implementation for Yacc-like parsers in C
+
+   Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+   This program is free software: you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation, either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* As a special exception, you may create a larger work that contains
+   part or all of the Bison parser skeleton and distribute that work
+   under terms of your choice, so long as that work isn't itself a
+   parser generator using the skeleton or a modified version thereof
+   as a parser skeleton.  Alternatively, if you modify or redistribute
+   the parser skeleton itself, you may (at your option) remove this
+   special exception, which will cause the skeleton and the resulting
+   Bison output files to be licensed under the GNU General Public
+   License without this special exception.
+
+   This special exception was added by the Free Software Foundation in
+   version 2.2 of Bison.  */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+   simplifying the original so-called "semantic" parser.  */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+   infringing on user name space.  This should be done even for local
+   variables, as they might otherwise be expanded by user macros.
+   There are some unavoidable exceptions within include files to
+   define necessary library symbols; they are noted "INFRINGES ON
+   USER NAME SPACE" below.  */
+
+/* Identify Bison output.  */
+#define YYBISON 1
+
+/* Bison version.  */
+#define YYBISON_VERSION "3.0.2"
+
+/* Skeleton name.  */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers.  */
+#define YYPURE 0
+
+/* Push parsers.  */
+#define YYPUSH 0
+
+/* Pull parsers.  */
+#define YYPULL 1
+
+
+
+
+/* Copy the first part of user declarations.  */
+#line 20 "fmd_parser.y" /* yacc.c:339  */
+
+#include "fmd_scanner.h"
+#include "common.h"
+
+#include <stdlib.h>
+
+struct flashmap_descriptor *res = NULL;
+
+#line 75 "y.tab.c" /* yacc.c:339  */
+
+# ifndef YY_NULLPTR
+#  if defined __cplusplus && 201103L <= __cplusplus
+#   define YY_NULLPTR nullptr
+#  else
+#   define YY_NULLPTR 0
+#  endif
+# endif
+
+/* Enabling verbose error messages.  */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* In a future release of Bison, this section will be replaced
+   by #include "y.tab.h".  */
+#ifndef YY_YY_Y_TAB_H_INCLUDED
+# define YY_YY_Y_TAB_H_INCLUDED
+/* Debug traces.  */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int yydebug;
+#endif
+/* "%code requires" blocks.  */
+#line 37 "fmd_parser.y" /* yacc.c:355  */
+
+#include "fmd.h"
+#include "option.h"
+
+#include <stdbool.h>
+
+struct descriptor_node {
+	struct flashmap_descriptor *val;
+	struct descriptor_node *next;
+};
+
+struct descriptor_list {
+	size_t len;
+	struct descriptor_node *head;
+	struct descriptor_node *tail;
+};
+
+extern struct flashmap_descriptor *res;
+
+struct flashmap_descriptor *parse_descriptor(char *name,
+	struct unsigned_option offset, struct unsigned_option size,
+					struct descriptor_list children);
+void yyerror(const char *s);
+
+#line 130 "y.tab.c" /* yacc.c:355  */
+
+/* Token type.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+  enum yytokentype
+  {
+    INTEGER = 258,
+    OCTAL = 259,
+    STRING = 260
+  };
+#endif
+/* Tokens.  */
+#define INTEGER 258
+#define OCTAL 259
+#define STRING 260
+
+/* Value type.  */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 29 "fmd_parser.y" /* yacc.c:355  */
+
+	unsigned intval;
+	char *strval;
+	struct unsigned_option maybe_intval;
+	struct flashmap_descriptor *region_ptr;
+	struct descriptor_list region_listhdr;
+
+#line 160 "y.tab.c" /* yacc.c:355  */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE yylval;
+
+int yyparse (void);
+
+#endif /* !YY_YY_Y_TAB_H_INCLUDED  */
+
+/* Copy the second part of user declarations.  */
+
+#line 175 "y.tab.c" /* yacc.c:358  */
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#else
+typedef signed char yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+#  define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+#  define YYSIZE_T size_t
+# elif ! defined YYSIZE_T
+#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYSIZE_T size_t
+# else
+#  define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if defined YYENABLE_NLS && YYENABLE_NLS
+#  if ENABLE_NLS
+#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+#   define YY_(Msgid) dgettext ("bison-runtime", Msgid)
+#  endif
+# endif
+# ifndef YY_
+#  define YY_(Msgid) Msgid
+# endif
+#endif
+
+#ifndef YY_ATTRIBUTE
+# if (defined __GNUC__                                               \
+      && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__)))  \
+     || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C
+#  define YY_ATTRIBUTE(Spec) __attribute__(Spec)
+# else
+#  define YY_ATTRIBUTE(Spec) /* empty */
+# endif
+#endif
+
+#ifndef YY_ATTRIBUTE_PURE
+# define YY_ATTRIBUTE_PURE   YY_ATTRIBUTE ((__pure__))
+#endif
+
+#ifndef YY_ATTRIBUTE_UNUSED
+# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__))
+#endif
+
+#if !defined _Noreturn \
+     && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112)
+# if defined _MSC_VER && 1200 <= _MSC_VER
+#  define _Noreturn __declspec (noreturn)
+# else
+#  define _Noreturn YY_ATTRIBUTE ((__noreturn__))
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E.  */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(E) ((void) (E))
+#else
+# define YYUSE(E) /* empty */
+#endif
+
+#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
+/* Suppress an incorrect diagnostic about yylval being uninitialized.  */
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
+    _Pragma ("GCC diagnostic push") \
+    _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
+    _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
+    _Pragma ("GCC diagnostic pop")
+#else
+# define YY_INITIAL_VALUE(Value) Value
+#endif
+#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END
+#endif
+#ifndef YY_INITIAL_VALUE
+# define YY_INITIAL_VALUE(Value) /* Nothing. */
+#endif
+
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols.  */
+
+# ifdef YYSTACK_USE_ALLOCA
+#  if YYSTACK_USE_ALLOCA
+#   ifdef __GNUC__
+#    define YYSTACK_ALLOC __builtin_alloca
+#   elif defined __BUILTIN_VA_ARG_INCR
+#    include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+#   elif defined _AIX
+#    define YYSTACK_ALLOC __alloca
+#   elif defined _MSC_VER
+#    include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+#    define alloca _alloca
+#   else
+#    define YYSTACK_ALLOC alloca
+#    if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
+#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+      /* Use EXIT_SUCCESS as a witness for stdlib.h.  */
+#     ifndef EXIT_SUCCESS
+#      define EXIT_SUCCESS 0
+#     endif
+#    endif
+#   endif
+#  endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+   /* Pacify GCC's 'empty if-body' warning.  */
+#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+    /* The OS might guarantee only one guard page at the bottom of the stack,
+       and a page size can be as small as 4096 bytes.  So we cannot safely
+       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
+       to allow for a few compiler-allocated temporary stack slots.  */
+#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+#  endif
+# else
+#  define YYSTACK_ALLOC YYMALLOC
+#  define YYSTACK_FREE YYFREE
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+#   define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+#  endif
+#  if (defined __cplusplus && ! defined EXIT_SUCCESS \
+       && ! ((defined YYMALLOC || defined malloc) \
+             && (defined YYFREE || defined free)))
+#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#   ifndef EXIT_SUCCESS
+#    define EXIT_SUCCESS 0
+#   endif
+#  endif
+#  ifndef YYMALLOC
+#   define YYMALLOC malloc
+#   if ! defined malloc && ! defined EXIT_SUCCESS
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifndef YYFREE
+#   define YYFREE free
+#   if ! defined free && ! defined EXIT_SUCCESS
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+     && (! defined __cplusplus \
+         || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member.  */
+union yyalloc
+{
+  yytype_int16 yyss_alloc;
+  YYSTYPE yyvs_alloc;
+};
+
+/* The size of the maximum gap between one aligned stack and the next.  */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+   N elements.  */
+# define YYSTACK_BYTES(N) \
+     ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+      + YYSTACK_GAP_MAXIMUM)
+
+# define YYCOPY_NEEDED 1
+
+/* Relocate STACK from its old location to the new one.  The
+   local variables YYSIZE and YYSTACKSIZE give the old and new number of
+   elements in the stack, and YYPTR gives the new location of the
+   stack.  Advance YYPTR to a properly aligned location for the next
+   stack.  */
+# define YYSTACK_RELOCATE(Stack_alloc, Stack)                           \
+    do                                                                  \
+      {                                                                 \
+        YYSIZE_T yynewbytes;                                            \
+        YYCOPY (&yyptr->Stack_alloc, Stack, yysize);                    \
+        Stack = &yyptr->Stack_alloc;                                    \
+        yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+        yyptr += yynewbytes / sizeof (*yyptr);                          \
+      }                                                                 \
+    while (0)
+
+#endif
+
+#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
+/* Copy COUNT objects from SRC to DST.  The source and destination do
+   not overlap.  */
+# ifndef YYCOPY
+#  if defined __GNUC__ && 1 < __GNUC__
+#   define YYCOPY(Dst, Src, Count) \
+      __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src)))
+#  else
+#   define YYCOPY(Dst, Src, Count)              \
+      do                                        \
+        {                                       \
+          YYSIZE_T yyi;                         \
+          for (yyi = 0; yyi < (Count); yyi++)   \
+            (Dst)[yyi] = (Src)[yyi];            \
+        }                                       \
+      while (0)
+#  endif
+# endif
+#endif /* !YYCOPY_NEEDED */
+
+/* YYFINAL -- State number of the termination state.  */
+#define YYFINAL  4
+/* YYLAST -- Last index in YYTABLE.  */
+#define YYLAST   17
+
+/* YYNTOKENS -- Number of terminals.  */
+#define YYNTOKENS  11
+/* YYNNTS -- Number of nonterminals.  */
+#define YYNNTS  13
+/* YYNRULES -- Number of rules.  */
+#define YYNRULES  18
+/* YYNSTATES -- Number of states.  */
+#define YYNSTATES  28
+
+/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
+   by yylex, with out-of-bounds checking.  */
+#define YYUNDEFTOK  2
+#define YYMAXUTOK   260
+
+#define YYTRANSLATE(YYX)                                                \
+  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
+   as returned by yylex, without out-of-bounds checking.  */
+static const yytype_uint8 yytranslate[] =
+{
+       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       6,     7,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     8,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     9,     2,    10,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
+       5
+};
+
+#if YYDEBUG
+  /* YYRLINE[YYN] -- Source line where rule number YYN was defined.  */
+static const yytype_uint8 yyrline[] =
+{
+       0,    80,    80,    85,   102,   109,   110,   111,   112,   113,
+     114,   115,   116,   117,   119,   123,   124,   125,   136
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || 0
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+   First, the terminals, then, starting at YYNTOKENS, nonterminals.  */
+static const char *const yytname[] =
+{
+  "$end", "error", "$undefined", "INTEGER", "OCTAL", "STRING", "'('",
+  "')'", "'@'", "'{'", "'}'", "$accept", "flash_chip", "flash_region",
+  "region_name", "region_annotation_opt", "region_annotation",
+  "region_offset_opt", "region_offset", "region_size_opt", "region_size",
+  "region_list_opt", "region_list", "region_list_entries", YY_NULLPTR
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[NUM] -- (External) token number corresponding to the
+   (internal) symbol number NUM (which must be that of a token).  */
+static const yytype_uint16 yytoknum[] =
+{
+       0,   256,   257,   258,   259,   260,    40,    41,    64,   123,
+     125
+};
+# endif
+
+#define YYPACT_NINF -10
+
+#define yypact_value_is_default(Yystate) \
+  (!!((Yystate) == (-10)))
+
+#define YYTABLE_NINF -1
+
+#define yytable_value_is_error(Yytable_value) \
+  0
+
+  /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+     STATE-NUM.  */
+static const yytype_int8 yypact[] =
+{
+      -4,   -10,     2,    -2,   -10,     0,     1,   -10,   -10,   -10,
+      -1,    -4,   -10,   -10,     3,    -5,     5,    -2,   -10,   -10,
+     -10,     4,     1,   -10,    -1,   -10,   -10,   -10
+};
+
+  /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
+     Performed when YYTABLE does not specify something else to do.  Zero
+     means the default is an error.  */
+static const yytype_uint8 yydefact[] =
+{
+       0,     4,     0,     8,     1,     0,     0,     9,    10,    13,
+       0,     0,     2,    17,     5,     0,     0,     8,     6,    16,
+      18,     0,    11,     7,    14,    12,     3,    15
+};
+
+  /* YYPGOTO[NTERM-NUM].  */
+static const yytype_int8 yypgoto[] =
+{
+     -10,   -10,    -8,    12,   -10,   -10,    -3,   -10,   -10,    -9,
+     -10,    -7,   -10
+};
+
+  /* YYDEFGOTO[NTERM-NUM].  */
+static const yytype_int8 yydefgoto[] =
+{
+      -1,     2,    13,    14,    17,    18,     6,     7,    24,    10,
+      26,    12,    15
+};
+
+  /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM.  If
+     positive, shift that token.  If negative, reduce the rule whose
+     number is the opposite.  If YYTABLE_NINF, syntax error.  */
+static const yytype_uint8 yytable[] =
+{
+       1,     1,     4,     8,     9,    19,     5,    20,    11,    16,
+      21,    23,     3,    25,    22,     0,     0,    27
+};
+
+static const yytype_int8 yycheck[] =
+{
+       5,     5,     0,     3,     3,    10,     8,    15,     9,     6,
+       5,     7,     0,    22,    17,    -1,    -1,    24
+};
+
+  /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+     symbol of state STATE-NUM.  */
+static const yytype_uint8 yystos[] =
+{
+       0,     5,    12,    14,     0,     8,    17,    18,     3,     3,
+      20,     9,    22,    13,    14,    23,     6,    15,    16,    10,
+      13,     5,    17,     7,    19,    20,    21,    22
+};
+
+  /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
+static const yytype_uint8 yyr1[] =
+{
+       0,    11,    12,    13,    14,    15,    15,    16,    17,    17,
+      18,    19,    19,    20,    21,    21,    22,    23,    23
+};
+
+  /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN.  */
+static const yytype_uint8 yyr2[] =
+{
+       0,     2,     4,     5,     1,     0,     1,     3,     0,     1,
+       2,     0,     1,     1,     0,     1,     3,     1,     2
+};
+
+
+#define yyerrok         (yyerrstatus = 0)
+#define yyclearin       (yychar = YYEMPTY)
+#define YYEMPTY         (-2)
+#define YYEOF           0
+
+#define YYACCEPT        goto yyacceptlab
+#define YYABORT         goto yyabortlab
+#define YYERROR         goto yyerrorlab
+
+
+#define YYRECOVERING()  (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value)                                  \
+do                                                              \
+  if (yychar == YYEMPTY)                                        \
+    {                                                           \
+      yychar = (Token);                                         \
+      yylval = (Value);                                         \
+      YYPOPSTACK (yylen);                                       \
+      yystate = *yyssp;                                         \
+      goto yybackup;                                            \
+    }                                                           \
+  else                                                          \
+    {                                                           \
+      yyerror (YY_("syntax error: cannot back up")); \
+      YYERROR;                                                  \
+    }                                                           \
+while (0)
+
+/* Error token number */
+#define YYTERROR        1
+#define YYERRCODE       256
+
+
+
+/* Enable debugging if requested.  */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args)                        \
+do {                                            \
+  if (yydebug)                                  \
+    YYFPRINTF Args;                             \
+} while (0)
+
+/* This macro is provided for backward compatibility. */
+#ifndef YY_LOCATION_PRINT
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+#endif
+
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)                    \
+do {                                                                      \
+  if (yydebug)                                                            \
+    {                                                                     \
+      YYFPRINTF (stderr, "%s ", Title);                                   \
+      yy_symbol_print (stderr,                                            \
+                  Type, Value); \
+      YYFPRINTF (stderr, "\n");                                           \
+    }                                                                     \
+} while (0)
+
+
+/*----------------------------------------.
+| Print this symbol's value on YYOUTPUT.  |
+`----------------------------------------*/
+
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+  FILE *yyo = yyoutput;
+  YYUSE (yyo);
+  if (!yyvaluep)
+    return;
+# ifdef YYPRINT
+  if (yytype < YYNTOKENS)
+    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+  YYUSE (yytype);
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+  YYFPRINTF (yyoutput, "%s %s (",
+             yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
+
+  yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+  YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included).                                                   |
+`------------------------------------------------------------------*/
+
+static void
+yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
+{
+  YYFPRINTF (stderr, "Stack now");
+  for (; yybottom <= yytop; yybottom++)
+    {
+      int yybot = *yybottom;
+      YYFPRINTF (stderr, " %d", yybot);
+    }
+  YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top)                            \
+do {                                                            \
+  if (yydebug)                                                  \
+    yy_stack_print ((Bottom), (Top));                           \
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced.  |
+`------------------------------------------------*/
+
+static void
+yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule)
+{
+  unsigned long int yylno = yyrline[yyrule];
+  int yynrhs = yyr2[yyrule];
+  int yyi;
+  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+             yyrule - 1, yylno);
+  /* The symbols being reduced.  */
+  for (yyi = 0; yyi < yynrhs; yyi++)
+    {
+      YYFPRINTF (stderr, "   $%d = ", yyi + 1);
+      yy_symbol_print (stderr,
+                       yystos[yyssp[yyi + 1 - yynrhs]],
+                       &(yyvsp[(yyi + 1) - (yynrhs)])
+                                              );
+      YYFPRINTF (stderr, "\n");
+    }
+}
+
+# define YY_REDUCE_PRINT(Rule)          \
+do {                                    \
+  if (yydebug)                          \
+    yy_reduce_print (yyssp, yyvsp, Rule); \
+} while (0)
+
+/* Nonzero means print parse trace.  It is left uninitialized so that
+   multiple parsers can coexist.  */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks.  */
+#ifndef YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+   if the built-in stack extension method is used).
+
+   Do not make this value too large; the results are undefined if
+   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+   evaluated with infinite-precision integer arithmetic.  */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+#  if defined __GLIBC__ && defined _STRING_H
+#   define yystrlen strlen
+#  else
+/* Return the length of YYSTR.  */
+static YYSIZE_T
+yystrlen (const char *yystr)
+{
+  YYSIZE_T yylen;
+  for (yylen = 0; yystr[yylen]; yylen++)
+    continue;
+  return yylen;
+}
+#  endif
+# endif
+
+# ifndef yystpcpy
+#  if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+#   define yystpcpy stpcpy
+#  else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+   YYDEST.  */
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+{
+  char *yyd = yydest;
+  const char *yys = yysrc;
+
+  while ((*yyd++ = *yys++) != '\0')
+    continue;
+
+  return yyd - 1;
+}
+#  endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+   quotes and backslashes, so that it's suitable for yyerror.  The
+   heuristic is that double-quoting is unnecessary unless the string
+   contains an apostrophe, a comma, or backslash (other than
+   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
+   null, do not copy; instead, return the length of what the result
+   would have been.  */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+  if (*yystr == '"')
+    {
+      YYSIZE_T yyn = 0;
+      char const *yyp = yystr;
+
+      for (;;)
+        switch (*++yyp)
+          {
+          case '\'':
+          case ',':
+            goto do_not_strip_quotes;
+
+          case '\\':
+            if (*++yyp != '\\')
+              goto do_not_strip_quotes;
+            /* Fall through.  */
+          default:
+            if (yyres)
+              yyres[yyn] = *yyp;
+            yyn++;
+            break;
+
+          case '"':
+            if (yyres)
+              yyres[yyn] = '\0';
+            return yyn;
+          }
+    do_not_strip_quotes: ;
+    }
+
+  if (! yyres)
+    return yystrlen (yystr);
+
+  return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
+   about the unexpected token YYTOKEN for the state stack whose top is
+   YYSSP.
+
+   Return 0 if *YYMSG was successfully written.  Return 1 if *YYMSG is
+   not large enough to hold the message.  In that case, also set
+   *YYMSG_ALLOC to the required number of bytes.  Return 2 if the
+   required number of bytes is too large to store.  */
+static int
+yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+                yytype_int16 *yyssp, int yytoken)
+{
+  YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]);
+  YYSIZE_T yysize = yysize0;
+  enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+  /* Internationalized format string. */
+  const char *yyformat = YY_NULLPTR;
+  /* Arguments of yyformat. */
+  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+  /* Number of reported tokens (one for the "unexpected", one per
+     "expected"). */
+  int yycount = 0;
+
+  /* There are many possibilities here to consider:
+     - If this state is a consistent state with a default action, then
+       the only way this function was invoked is if the default action
+       is an error action.  In that case, don't check for expected
+       tokens because there are none.
+     - The only way there can be no lookahead present (in yychar) is if
+       this state is a consistent state with a default action.  Thus,
+       detecting the absence of a lookahead is sufficient to determine
+       that there is no unexpected or expected token to report.  In that
+       case, just report a simple "syntax error".
+     - Don't assume there isn't a lookahead just because this state is a
+       consistent state with a default action.  There might have been a
+       previous inconsistent state, consistent state with a non-default
+       action, or user semantic action that manipulated yychar.
+     - Of course, the expected token list depends on states to have
+       correct lookahead information, and it depends on the parser not
+       to perform extra reductions after fetching a lookahead from the
+       scanner and before detecting a syntax error.  Thus, state merging
+       (from LALR or IELR) and default reductions corrupt the expected
+       token list.  However, the list is correct for canonical LR with
+       one exception: it will still contain any token that will not be
+       accepted due to an error action in a later state.
+  */
+  if (yytoken != YYEMPTY)
+    {
+      int yyn = yypact[*yyssp];
+      yyarg[yycount++] = yytname[yytoken];
+      if (!yypact_value_is_default (yyn))
+        {
+          /* Start YYX at -YYN if negative to avoid negative indexes in
+             YYCHECK.  In other words, skip the first -YYN actions for
+             this state because they are default actions.  */
+          int yyxbegin = yyn < 0 ? -yyn : 0;
+          /* Stay within bounds of both yycheck and yytname.  */
+          int yychecklim = YYLAST - yyn + 1;
+          int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+          int yyx;
+
+          for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+            if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
+                && !yytable_value_is_error (yytable[yyx + yyn]))
+              {
+                if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+                  {
+                    yycount = 1;
+                    yysize = yysize0;
+                    break;
+                  }
+                yyarg[yycount++] = yytname[yyx];
+                {
+                  YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]);
+                  if (! (yysize <= yysize1
+                         && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+                    return 2;
+                  yysize = yysize1;
+                }
+              }
+        }
+    }
+
+  switch (yycount)
+    {
+# define YYCASE_(N, S)                      \
+      case N:                               \
+        yyformat = S;                       \
+      break
+      YYCASE_(0, YY_("syntax error"));
+      YYCASE_(1, YY_("syntax error, unexpected %s"));
+      YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
+      YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
+      YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
+      YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
+# undef YYCASE_
+    }
+
+  {
+    YYSIZE_T yysize1 = yysize + yystrlen (yyformat);
+    if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+      return 2;
+    yysize = yysize1;
+  }
+
+  if (*yymsg_alloc < yysize)
+    {
+      *yymsg_alloc = 2 * yysize;
+      if (! (yysize <= *yymsg_alloc
+             && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
+        *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
+      return 1;
+    }
+
+  /* Avoid sprintf, as that infringes on the user's name space.
+     Don't have undefined behavior even if the translation
+     produced a string with the wrong number of "%s"s.  */
+  {
+    char *yyp = *yymsg;
+    int yyi = 0;
+    while ((*yyp = *yyformat) != '\0')
+      if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
+        {
+          yyp += yytnamerr (yyp, yyarg[yyi++]);
+          yyformat += 2;
+        }
+      else
+        {
+          yyp++;
+          yyformat++;
+        }
+  }
+  return 0;
+}
+#endif /* YYERROR_VERBOSE */
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol.  |
+`-----------------------------------------------*/
+
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+{
+  YYUSE (yyvaluep);
+  if (!yymsg)
+    yymsg = "Deleting";
+  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+  YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+  YYUSE (yytype);
+  YY_IGNORE_MAYBE_UNINITIALIZED_END
+}
+
+
+
+
+/* The lookahead symbol.  */
+int yychar;
+
+/* The semantic value of the lookahead symbol.  */
+YYSTYPE yylval;
+/* Number of syntax errors so far.  */
+int yynerrs;
+
+
+/*----------.
+| yyparse.  |
+`----------*/
+
+int
+yyparse (void)
+{
+    int yystate;
+    /* Number of tokens to shift before error messages enabled.  */
+    int yyerrstatus;
+
+    /* The stacks and their tools:
+       'yyss': related to states.
+       'yyvs': related to semantic values.
+
+       Refer to the stacks through separate pointers, to allow yyoverflow
+       to reallocate them elsewhere.  */
+
+    /* The state stack.  */
+    yytype_int16 yyssa[YYINITDEPTH];
+    yytype_int16 *yyss;
+    yytype_int16 *yyssp;
+
+    /* The semantic value stack.  */
+    YYSTYPE yyvsa[YYINITDEPTH];
+    YYSTYPE *yyvs;
+    YYSTYPE *yyvsp;
+
+    YYSIZE_T yystacksize;
+
+  int yyn;
+  int yyresult;
+  /* Lookahead token as an internal (translated) token number.  */
+  int yytoken = 0;
+  /* The variables used to return semantic value and location from the
+     action routines.  */
+  YYSTYPE yyval;
+
+#if YYERROR_VERBOSE
+  /* Buffer for error messages, and its allocated size.  */
+  char yymsgbuf[128];
+  char *yymsg = yymsgbuf;
+  YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+#define YYPOPSTACK(N)   (yyvsp -= (N), yyssp -= (N))
+
+  /* The number of symbols on the RHS of the reduced rule.
+     Keep to zero when no symbol should be popped.  */
+  int yylen = 0;
+
+  yyssp = yyss = yyssa;
+  yyvsp = yyvs = yyvsa;
+  yystacksize = YYINITDEPTH;
+
+  YYDPRINTF ((stderr, "Starting parse\n"));
+
+  yystate = 0;
+  yyerrstatus = 0;
+  yynerrs = 0;
+  yychar = YYEMPTY; /* Cause a token to be read.  */
+  goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate.  |
+`------------------------------------------------------------*/
+ yynewstate:
+  /* In all cases, when you get here, the value and location stacks
+     have just been pushed.  So pushing a state here evens the stacks.  */
+  yyssp++;
+
+ yysetstate:
+  *yyssp = yystate;
+
+  if (yyss + yystacksize - 1 <= yyssp)
+    {
+      /* Get the current used size of the three stacks, in elements.  */
+      YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+      {
+        /* Give user a chance to reallocate the stack.  Use copies of
+           these so that the &'s don't force the real ones into
+           memory.  */
+        YYSTYPE *yyvs1 = yyvs;
+        yytype_int16 *yyss1 = yyss;
+
+        /* Each stack pointer address is followed by the size of the
+           data in use in that stack, in bytes.  This used to be a
+           conditional around just the two extra args, but that might
+           be undefined if yyoverflow is a macro.  */
+        yyoverflow (YY_("memory exhausted"),
+                    &yyss1, yysize * sizeof (*yyssp),
+                    &yyvs1, yysize * sizeof (*yyvsp),
+                    &yystacksize);
+
+        yyss = yyss1;
+        yyvs = yyvs1;
+      }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+      goto yyexhaustedlab;
+# else
+      /* Extend the stack our own way.  */
+      if (YYMAXDEPTH <= yystacksize)
+        goto yyexhaustedlab;
+      yystacksize *= 2;
+      if (YYMAXDEPTH < yystacksize)
+        yystacksize = YYMAXDEPTH;
+
+      {
+        yytype_int16 *yyss1 = yyss;
+        union yyalloc *yyptr =
+          (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+        if (! yyptr)
+          goto yyexhaustedlab;
+        YYSTACK_RELOCATE (yyss_alloc, yyss);
+        YYSTACK_RELOCATE (yyvs_alloc, yyvs);
+#  undef YYSTACK_RELOCATE
+        if (yyss1 != yyssa)
+          YYSTACK_FREE (yyss1);
+      }
+# endif
+#endif /* no yyoverflow */
+
+      yyssp = yyss + yysize - 1;
+      yyvsp = yyvs + yysize - 1;
+
+      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+                  (unsigned long int) yystacksize));
+
+      if (yyss + yystacksize - 1 <= yyssp)
+        YYABORT;
+    }
+
+  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+  if (yystate == YYFINAL)
+    YYACCEPT;
+
+  goto yybackup;
+
+/*-----------.
+| yybackup.  |
+`-----------*/
+yybackup:
+
+  /* Do appropriate processing given the current state.  Read a
+     lookahead token if we need one and don't already have one.  */
+
+  /* First try to decide what to do without reference to lookahead token.  */
+  yyn = yypact[yystate];
+  if (yypact_value_is_default (yyn))
+    goto yydefault;
+
+  /* Not known => get a lookahead token if don't already have one.  */
+
+  /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol.  */
+  if (yychar == YYEMPTY)
+    {
+      YYDPRINTF ((stderr, "Reading a token: "));
+      yychar = yylex ();
+    }
+
+  if (yychar <= YYEOF)
+    {
+      yychar = yytoken = YYEOF;
+      YYDPRINTF ((stderr, "Now at end of input.\n"));
+    }
+  else
+    {
+      yytoken = YYTRANSLATE (yychar);
+      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+    }
+
+  /* If the proper action on seeing token YYTOKEN is to reduce or to
+     detect an error, take that action.  */
+  yyn += yytoken;
+  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+    goto yydefault;
+  yyn = yytable[yyn];
+  if (yyn <= 0)
+    {
+      if (yytable_value_is_error (yyn))
+        goto yyerrlab;
+      yyn = -yyn;
+      goto yyreduce;
+    }
+
+  /* Count tokens shifted since error; after three, turn off error
+     status.  */
+  if (yyerrstatus)
+    yyerrstatus--;
+
+  /* Shift the lookahead token.  */
+  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+  /* Discard the shifted token.  */
+  yychar = YYEMPTY;
+
+  yystate = yyn;
+  YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+  *++yyvsp = yylval;
+  YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+  goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state.  |
+`-----------------------------------------------------------*/
+yydefault:
+  yyn = yydefact[yystate];
+  if (yyn == 0)
+    goto yyerrlab;
+  goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction.  |
+`-----------------------------*/
+yyreduce:
+  /* yyn is the number of a rule to reduce with.  */
+  yylen = yyr2[yyn];
+
+  /* If YYLEN is nonzero, implement the default value of the action:
+     '$$ = $1'.
+
+     Otherwise, the following line sets YYVAL to garbage.
+     This behavior is undocumented and Bison
+     users should not rely upon it.  Assigning to YYVAL
+     unconditionally makes the parser a bit smaller, and it avoids a
+     GCC warning that YYVAL may be used uninitialized.  */
+  yyval = yyvsp[1-yylen];
+
+
+  YY_REDUCE_PRINT (yyn);
+  switch (yyn)
+    {
+        case 2:
+#line 81 "fmd_parser.y" /* yacc.c:1646  */
+    {
+	if (!(res = parse_descriptor((yyvsp[-3].strval), (yyvsp[-2].maybe_intval), (yyvsp[-1].maybe_intval), (yyvsp[0].region_listhdr))))
+		YYABORT;
+}
+#line 1261 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 3:
+#line 87 "fmd_parser.y" /* yacc.c:1646  */
+    {
+	struct flashmap_descriptor *node = parse_descriptor((yyvsp[-4].strval), (yyvsp[-2].maybe_intval), (yyvsp[-1].maybe_intval), (yyvsp[0].region_listhdr));
+	if (!node)
+		YYABORT;
+
+	char *annotation = (yyvsp[-3].strval);
+	if (annotation && !fmd_process_annotation_impl(node, annotation)) {
+		ERROR("Section '%s' has unexpected annotation '(%s)'\n",
+							node->name, annotation);
+		YYABORT;
+	}
+	free(annotation);
+
+	(yyval.region_ptr) = node;
+}
+#line 1281 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 4:
+#line 103 "fmd_parser.y" /* yacc.c:1646  */
+    {
+	if (!(yyvsp[0].strval)) {
+		perror("E: While allocating section name");
+		YYABORT;
+	}
+}
+#line 1292 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 5:
+#line 109 "fmd_parser.y" /* yacc.c:1646  */
+    { (yyval.strval) = NULL; }
+#line 1298 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 7:
+#line 111 "fmd_parser.y" /* yacc.c:1646  */
+    { (yyval.strval) = (yyvsp[-1].strval); }
+#line 1304 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 8:
+#line 112 "fmd_parser.y" /* yacc.c:1646  */
+    { (yyval.maybe_intval) = (struct unsigned_option){false, 0}; }
+#line 1310 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 10:
+#line 114 "fmd_parser.y" /* yacc.c:1646  */
+    { (yyval.maybe_intval) = (struct unsigned_option){true, (yyvsp[0].intval)}; }
+#line 1316 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 11:
+#line 115 "fmd_parser.y" /* yacc.c:1646  */
+    { (yyval.maybe_intval) = (struct unsigned_option){false, 0}; }
+#line 1322 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 13:
+#line 117 "fmd_parser.y" /* yacc.c:1646  */
+    { (yyval.maybe_intval) = (struct unsigned_option){true, (yyvsp[0].intval)}; }
+#line 1328 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 14:
+#line 119 "fmd_parser.y" /* yacc.c:1646  */
+    {
+	(yyval.region_listhdr) = (struct descriptor_list)
+					{.len = 0, .head = NULL, .tail = NULL};
+}
+#line 1337 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 16:
+#line 124 "fmd_parser.y" /* yacc.c:1646  */
+    { (yyval.region_listhdr) = (yyvsp[-1].region_listhdr); }
+#line 1343 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 17:
+#line 126 "fmd_parser.y" /* yacc.c:1646  */
+    {
+	struct descriptor_node *node = malloc(sizeof(*node));
+	if (!node) {
+		perror("E: While allocating linked list node");
+		YYABORT;
+	}
+	node->val = (yyvsp[0].region_ptr);
+	node->next = NULL;
+	(yyval.region_listhdr) = (struct descriptor_list){.len = 1, .head = node, .tail = node};
+}
+#line 1358 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+  case 18:
+#line 137 "fmd_parser.y" /* yacc.c:1646  */
+    {
+	struct descriptor_node *node = malloc(sizeof(*node));
+	if (!node) {
+		perror("E: While allocating linked list node");
+		YYABORT;
+	}
+	node->val = (yyvsp[0].region_ptr);
+	node->next = NULL;
+
+	(yyvsp[-1].region_listhdr).tail->next = node;
+	(yyval.region_listhdr) = (struct descriptor_list)
+			{.len = (yyvsp[-1].region_listhdr).len + 1, .head = (yyvsp[-1].region_listhdr).head, .tail = node};
+}
+#line 1376 "y.tab.c" /* yacc.c:1646  */
+    break;
+
+
+#line 1380 "y.tab.c" /* yacc.c:1646  */
+      default: break;
+    }
+  /* User semantic actions sometimes alter yychar, and that requires
+     that yytoken be updated with the new translation.  We take the
+     approach of translating immediately before every use of yytoken.
+     One alternative is translating here after every semantic action,
+     but that translation would be missed if the semantic action invokes
+     YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
+     if it invokes YYBACKUP.  In the case of YYABORT or YYACCEPT, an
+     incorrect destructor might then be invoked immediately.  In the
+     case of YYERROR or YYBACKUP, subsequent parser actions might lead
+     to an incorrect destructor call or verbose syntax error message
+     before the lookahead is translated.  */
+  YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+  YYPOPSTACK (yylen);
+  yylen = 0;
+  YY_STACK_PRINT (yyss, yyssp);
+
+  *++yyvsp = yyval;
+
+  /* Now 'shift' the result of the reduction.  Determine what state
+     that goes to, based on the state we popped back to and the rule
+     number reduced by.  */
+
+  yyn = yyr1[yyn];
+
+  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+    yystate = yytable[yystate];
+  else
+    yystate = yydefgoto[yyn - YYNTOKENS];
+
+  goto yynewstate;
+
+
+/*--------------------------------------.
+| yyerrlab -- here on detecting error.  |
+`--------------------------------------*/
+yyerrlab:
+  /* Make sure we have latest lookahead translation.  See comments at
+     user semantic actions for why this is necessary.  */
+  yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
+
+  /* If not already recovering from an error, report this error.  */
+  if (!yyerrstatus)
+    {
+      ++yynerrs;
+#if ! YYERROR_VERBOSE
+      yyerror (YY_("syntax error"));
+#else
+# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
+                                        yyssp, yytoken)
+      {
+        char const *yymsgp = YY_("syntax error");
+        int yysyntax_error_status;
+        yysyntax_error_status = YYSYNTAX_ERROR;
+        if (yysyntax_error_status == 0)
+          yymsgp = yymsg;
+        else if (yysyntax_error_status == 1)
+          {
+            if (yymsg != yymsgbuf)
+              YYSTACK_FREE (yymsg);
+            yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
+            if (!yymsg)
+              {
+                yymsg = yymsgbuf;
+                yymsg_alloc = sizeof yymsgbuf;
+                yysyntax_error_status = 2;
+              }
+            else
+              {
+                yysyntax_error_status = YYSYNTAX_ERROR;
+                yymsgp = yymsg;
+              }
+          }
+        yyerror (yymsgp);
+        if (yysyntax_error_status == 2)
+          goto yyexhaustedlab;
+      }
+# undef YYSYNTAX_ERROR
+#endif
+    }
+
+
+
+  if (yyerrstatus == 3)
+    {
+      /* If just tried and failed to reuse lookahead token after an
+         error, discard it.  */
+
+      if (yychar <= YYEOF)
+        {
+          /* Return failure if at end of input.  */
+          if (yychar == YYEOF)
+            YYABORT;
+        }
+      else
+        {
+          yydestruct ("Error: discarding",
+                      yytoken, &yylval);
+          yychar = YYEMPTY;
+        }
+    }
+
+  /* Else will try to reuse lookahead token after shifting the error
+     token.  */
+  goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR.  |
+`---------------------------------------------------*/
+yyerrorlab:
+
+  /* Pacify compilers like GCC when the user code never invokes
+     YYERROR and the label yyerrorlab therefore never appears in user
+     code.  */
+  if (/*CONSTCOND*/ 0)
+     goto yyerrorlab;
+
+  /* Do not reclaim the symbols of the rule whose action triggered
+     this YYERROR.  */
+  YYPOPSTACK (yylen);
+  yylen = 0;
+  YY_STACK_PRINT (yyss, yyssp);
+  yystate = *yyssp;
+  goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR.  |
+`-------------------------------------------------------------*/
+yyerrlab1:
+  yyerrstatus = 3;      /* Each real token shifted decrements this.  */
+
+  for (;;)
+    {
+      yyn = yypact[yystate];
+      if (!yypact_value_is_default (yyn))
+        {
+          yyn += YYTERROR;
+          if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+            {
+              yyn = yytable[yyn];
+              if (0 < yyn)
+                break;
+            }
+        }
+
+      /* Pop the current state because it cannot handle the error token.  */
+      if (yyssp == yyss)
+        YYABORT;
+
+
+      yydestruct ("Error: popping",
+                  yystos[yystate], yyvsp);
+      YYPOPSTACK (1);
+      yystate = *yyssp;
+      YY_STACK_PRINT (yyss, yyssp);
+    }
+
+  YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+  *++yyvsp = yylval;
+  YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+
+  /* Shift the error token.  */
+  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+  yystate = yyn;
+  goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here.  |
+`-------------------------------------*/
+yyacceptlab:
+  yyresult = 0;
+  goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here.  |
+`-----------------------------------*/
+yyabortlab:
+  yyresult = 1;
+  goto yyreturn;
+
+#if !defined yyoverflow || YYERROR_VERBOSE
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here.  |
+`-------------------------------------------------*/
+yyexhaustedlab:
+  yyerror (YY_("memory exhausted"));
+  yyresult = 2;
+  /* Fall through.  */
+#endif
+
+yyreturn:
+  if (yychar != YYEMPTY)
+    {
+      /* Make sure we have latest lookahead translation.  See comments at
+         user semantic actions for why this is necessary.  */
+      yytoken = YYTRANSLATE (yychar);
+      yydestruct ("Cleanup: discarding lookahead",
+                  yytoken, &yylval);
+    }
+  /* Do not reclaim the symbols of the rule whose action triggered
+     this YYABORT or YYACCEPT.  */
+  YYPOPSTACK (yylen);
+  YY_STACK_PRINT (yyss, yyssp);
+  while (yyssp != yyss)
+    {
+      yydestruct ("Cleanup: popping",
+                  yystos[*yyssp], yyvsp);
+      YYPOPSTACK (1);
+    }
+#ifndef yyoverflow
+  if (yyss != yyssa)
+    YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+  if (yymsg != yymsgbuf)
+    YYSTACK_FREE (yymsg);
+#endif
+  return yyresult;
+}
+#line 151 "fmd_parser.y" /* yacc.c:1906  */
+
+
+struct flashmap_descriptor *parse_descriptor(char *name,
+	struct unsigned_option offset, struct unsigned_option size,
+					struct descriptor_list children)
+{
+	struct flashmap_descriptor *region = malloc(sizeof(*region));
+	if (!region) {
+		perror("E: While allocating descriptor section");
+		return NULL;
+	}
+	region->name = name;
+	region->offset_known = offset.val_known;
+	region->offset = offset.val;
+	region->size_known = size.val_known;
+	region->size = size.val;
+	region->list_len = children.len;
+	if (region->list_len) {
+		region->list = malloc(region->list_len * sizeof(*region->list));
+		if (!region->list) {
+			perror("E: While allocating node children array");
+			return NULL;
+		}
+		struct descriptor_node *cur_node = children.head;
+		for (unsigned idx = 0; idx < region->list_len; ++idx) {
+			region->list[idx] = cur_node->val;
+
+			struct descriptor_node *next_node = cur_node->next;
+			free(cur_node);
+			cur_node = next_node;
+		}
+	} else {
+		region->list = NULL;
+	}
+	return region;
+}
+
+void yyerror(const char *s)
+{
+	fprintf(stderr, "%s\n", s);
+}
diff --git a/util/cbfstool/fmd_parser.h b/util/cbfstool/fmd_parser.h
new file mode 100644
index 0000000..dc6301d
--- /dev/null
+++ b/util/cbfstool/fmd_parser.h
@@ -0,0 +1,109 @@
+/* A Bison parser, made by GNU Bison 3.0.2.  */
+
+/* Bison interface for Yacc-like parsers in C
+
+   Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+   This program is free software: you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation, either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* As a special exception, you may create a larger work that contains
+   part or all of the Bison parser skeleton and distribute that work
+   under terms of your choice, so long as that work isn't itself a
+   parser generator using the skeleton or a modified version thereof
+   as a parser skeleton.  Alternatively, if you modify or redistribute
+   the parser skeleton itself, you may (at your option) remove this
+   special exception, which will cause the skeleton and the resulting
+   Bison output files to be licensed under the GNU General Public
+   License without this special exception.
+
+   This special exception was added by the Free Software Foundation in
+   version 2.2 of Bison.  */
+
+#ifndef YY_YY_Y_TAB_H_INCLUDED
+# define YY_YY_Y_TAB_H_INCLUDED
+/* Debug traces.  */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int yydebug;
+#endif
+/* "%code requires" blocks.  */
+#line 37 "fmd_parser.y" /* yacc.c:1909  */
+
+#include "fmd.h"
+#include "option.h"
+
+#include <stdbool.h>
+
+struct descriptor_node {
+	struct flashmap_descriptor *val;
+	struct descriptor_node *next;
+};
+
+struct descriptor_list {
+	size_t len;
+	struct descriptor_node *head;
+	struct descriptor_node *tail;
+};
+
+extern struct flashmap_descriptor *res;
+
+struct flashmap_descriptor *parse_descriptor(char *name,
+	struct unsigned_option offset, struct unsigned_option size,
+					struct descriptor_list children);
+void yyerror(const char *s);
+
+#line 69 "y.tab.h" /* yacc.c:1909  */
+
+/* Token type.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+  enum yytokentype
+  {
+    INTEGER = 258,
+    OCTAL = 259,
+    STRING = 260
+  };
+#endif
+/* Tokens.  */
+#define INTEGER 258
+#define OCTAL 259
+#define STRING 260
+
+/* Value type.  */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 29 "fmd_parser.y" /* yacc.c:1909  */
+
+	unsigned intval;
+	char *strval;
+	struct unsigned_option maybe_intval;
+	struct flashmap_descriptor *region_ptr;
+	struct descriptor_list region_listhdr;
+
+#line 99 "y.tab.h" /* yacc.c:1909  */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE yylval;
+
+int yyparse (void);
+
+#endif /* !YY_YY_Y_TAB_H_INCLUDED  */
diff --git a/util/cbfstool/fmd_scanner.c b/util/cbfstool/fmd_scanner.c
new file mode 100644
index 0000000..6628e7d
--- /dev/null
+++ b/util/cbfstool/fmd_scanner.c
@@ -0,0 +1,1853 @@
+
+#line 3 "<stdout>"
+
+#define  YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 35
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* First, we deal with  platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types. 
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t; 
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN               (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN              (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN              (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX               (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX              (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX              (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX              (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX             (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX             (4294967295U)
+#endif
+
+#endif /* ! C99 */
+
+#endif /* ! FLEXINT_H */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else	/* ! __cplusplus */
+
+/* C99 requires __STDC__ to be defined as 1. */
+#if defined (__STDC__)
+
+#define YY_USE_CONST
+
+#endif	/* defined (__STDC__) */
+#endif	/* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index.  If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition.  This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state.  The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE yyrestart(yyin  )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#ifdef __ia64__
+/* On IA-64, the buffer size is 16k, not 8k.
+ * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case.
+ * Ditto for the __ia64__ case accordingly.
+ */
+#define YY_BUF_SIZE 32768
+#else
+#define YY_BUF_SIZE 16384
+#endif /* __ia64__ */
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE   ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+extern int yyleng;
+
+extern FILE *yyin, *yyout;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+    #define YY_LESS_LINENO(n)
+    
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up yytext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		*yy_cp = (yy_hold_char); \
+		YY_RESTORE_YY_MORE_OFFSET \
+		(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+		YY_DO_BEFORE_ACTION; /* set up yytext again */ \
+		} \
+	while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr)  )
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef size_t yy_size_t;
+#endif
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+	{
+	FILE *yy_input_file;
+
+	char *yy_ch_buf;		/* input buffer */
+	char *yy_buf_pos;		/* current position in input buffer */
+
+	/* Size of input buffer in bytes, not including room for EOB
+	 * characters.
+	 */
+	yy_size_t yy_buf_size;
+
+	/* Number of characters read into yy_ch_buf, not including EOB
+	 * characters.
+	 */
+	int yy_n_chars;
+
+	/* Whether we "own" the buffer - i.e., we know we created it,
+	 * and can realloc() it to grow it, and should free() it to
+	 * delete it.
+	 */
+	int yy_is_our_buffer;
+
+	/* Whether this is an "interactive" input source; if so, and
+	 * if we're using stdio for input, then we want to use getc()
+	 * instead of fread(), to make sure we stop fetching input after
+	 * each newline.
+	 */
+	int yy_is_interactive;
+
+	/* Whether we're considered to be at the beginning of a line.
+	 * If so, '^' rules will be active on the next match, otherwise
+	 * not.
+	 */
+	int yy_at_bol;
+
+    int yy_bs_lineno; /**< The line count. */
+    int yy_bs_column; /**< The column count. */
+    
+	/* Whether to try to fill the input buffer when we reach the
+	 * end of it.
+	 */
+	int yy_fill_buffer;
+
+	int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+	/* When an EOF's been seen but there's still some text to process
+	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+	 * shouldn't try reading from the input source any more.  We might
+	 * still have a bunch of tokens to match, though, because of
+	 * possible backing-up.
+	 *
+	 * When we actually see the EOF, we change the status to "new"
+	 * (via yyrestart()), so that the user can continue scanning by
+	 * just pointing yyin at a new input file.
+	 */
+#define YY_BUFFER_EOF_PENDING 2
+
+	};
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* Stack of input buffers. */
+static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
+static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
+static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+                          ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+                          : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+/* yy_hold_char holds the character lost when yytext is formed. */
+static char yy_hold_char;
+static int yy_n_chars;		/* number of characters read into yy_ch_buf */
+int yyleng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 0;		/* whether we need to initialize */
+static int yy_start = 0;	/* start state number */
+
+/* Flag which is used to allow yywrap()'s to do buffer switches
+ * instead of setting up a fresh yyin.  A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+
+void yyrestart (FILE *input_file  );
+void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer  );
+YY_BUFFER_STATE yy_create_buffer (FILE *file,int size  );
+void yy_delete_buffer (YY_BUFFER_STATE b  );
+void yy_flush_buffer (YY_BUFFER_STATE b  );
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer  );
+void yypop_buffer_state (void );
+
+static void yyensure_buffer_stack (void );
+static void yy_load_buffer_state (void );
+static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file  );
+
+#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER )
+
+YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size  );
+YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str  );
+YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len  );
+
+void *yyalloc (yy_size_t  );
+void *yyrealloc (void *,yy_size_t  );
+void yyfree (void *  );
+
+#define yy_new_buffer yy_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){ \
+        yyensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            yy_create_buffer(yyin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+	}
+
+#define yy_set_bol(at_bol) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){\
+        yyensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            yy_create_buffer(yyin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+	}
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* Begin user sect3 */
+
+#define yywrap(n) 1
+#define YY_SKIP_YYWRAP
+
+typedef unsigned char YY_CHAR;
+
+FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
+
+typedef int yy_state_type;
+
+extern int yylineno;
+
+int yylineno = 1;
+
+extern char *yytext;
+#define yytext_ptr yytext
+
+static yy_state_type yy_get_previous_state (void );
+static yy_state_type yy_try_NUL_trans (yy_state_type current_state  );
+static int yy_get_next_buffer (void );
+static void yy_fatal_error (yyconst char msg[]  );
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up yytext.
+ */
+#define YY_DO_BEFORE_ACTION \
+	(yytext_ptr) = yy_bp; \
+	yyleng = (size_t) (yy_cp - yy_bp); \
+	(yy_hold_char) = *yy_cp; \
+	*yy_cp = '\0'; \
+	(yy_c_buf_p) = yy_cp;
+
+#define YY_NUM_RULES 9
+#define YY_END_OF_BUFFER 10
+/* This struct is not used in this scanner,
+   but its presence is necessary. */
+struct yy_trans_info
+	{
+	flex_int32_t yy_verify;
+	flex_int32_t yy_nxt;
+	};
+static yyconst flex_int16_t yy_accept[24] =
+    {   0,
+        7,    7,   10,    7,    1,    1,    8,    8,    3,    4,
+        7,    1,    0,    2,    5,    3,    7,    4,    4,    5,
+        6,    6,    0
+    } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
+        2,    2,    2,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    2,    1,    1,    4,    1,    1,    1,    1,    5,
+        5,    1,    1,    1,    1,    1,    1,    6,    7,    7,
+        7,    7,    7,    7,    7,    7,    7,    1,    1,    1,
+        1,    1,    1,    5,    1,    1,    1,    1,    1,    1,
+        8,    1,    1,    1,    8,    1,    8,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    9,    1,    1,
+        1,    1,    1,    1,    1,    1,   10,   10,   10,   10,
+
+       10,   10,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    9,
+        1,    1,    5,    1,    5,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1
+    } ;
+
+static yyconst flex_int32_t yy_meta[11] =
+    {   0,
+        1,    2,    2,    3,    3,    1,    1,    1,    1,    1
+    } ;
+
+static yyconst flex_int16_t yy_base[27] =
+    {   0,
+        0,    0,   29,    0,    0,    0,   25,   34,   10,   15,
+        0,    0,   12,   34,   16,    0,   20,    0,    0,    0,
+        6,    0,   34,   12,   10,   30
+    } ;
+
+static yyconst flex_int16_t yy_def[27] =
+    {   0,
+       23,    1,   23,   24,   25,   25,   26,   23,   23,   24,
+       24,   25,   26,   23,    9,   24,   24,   10,   24,   24,
+       17,   24,    0,   23,   23,   23
+    } ;
+
+static yyconst flex_int16_t yy_nxt[45] =
+    {   0,
+        4,    5,    6,    7,    8,    9,   10,    4,    4,    4,
+       11,   12,   11,   22,   14,   15,   15,   16,   17,   11,
+       18,   18,   19,   20,   11,   21,   21,   14,   23,   21,
+       13,   13,   13,    3,   23,   23,   23,   23,   23,   23,
+       23,   23,   23,   23
+    } ;
+
+static yyconst flex_int16_t yy_chk[45] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        9,   25,   24,   21,   13,    9,    9,    9,    9,    9,
+       10,   10,   10,   15,   15,   17,   17,    7,    3,   17,
+       26,   26,   26,   23,   23,   23,   23,   23,   23,   23,
+       23,   23,   23,   23
+    } ;
+
+static yy_state_type yy_last_accepting_state;
+static char *yy_last_accepting_cpos;
+
+extern int yy_flex_debug;
+int yy_flex_debug = 0;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *yytext;
+#line 1 "fmd_scanner.l"
+/*
+ * fmd_scanner.l, scanner generator for flashmap descriptor language
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#line 21 "fmd_scanner.l"
+#include "fmd_parser.h"
+
+#include <assert.h>
+#include <string.h>
+
+int parse_integer(char *src, int base);
+int copy_string(const char *src);
+#line 501 "<stdout>"
+
+#define INITIAL 0
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+static int yy_init_globals (void );
+
+/* Accessor methods to globals.
+   These are made visible to non-reentrant scanners for convenience. */
+
+int yylex_destroy (void );
+
+int yyget_debug (void );
+
+void yyset_debug (int debug_flag  );
+
+YY_EXTRA_TYPE yyget_extra (void );
+
+void yyset_extra (YY_EXTRA_TYPE user_defined  );
+
+FILE *yyget_in (void );
+
+void yyset_in  (FILE * in_str  );
+
+FILE *yyget_out (void );
+
+void yyset_out  (FILE * out_str  );
+
+int yyget_leng (void );
+
+char *yyget_text (void );
+
+int yyget_lineno (void );
+
+void yyset_lineno (int line_number  );
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int yywrap (void );
+#else
+extern int yywrap (void );
+#endif
+#endif
+
+    static void yyunput (int c,char *buf_ptr  );
+    
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#ifdef __cplusplus
+static int yyinput (void );
+#else
+static int input (void );
+#endif
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#ifdef __ia64__
+/* On IA-64, the buffer size is 16k, not 8k */
+#define YY_READ_BUF_SIZE 16384
+#else
+#define YY_READ_BUF_SIZE 8192
+#endif /* __ia64__ */
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0)
+#endif
+
+/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
+		{ \
+		int c = '*'; \
+		size_t n; \
+		for ( n = 0; n < max_size && \
+			     (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
+			buf[n] = (char) c; \
+		if ( c == '\n' ) \
+			buf[n++] = (char) c; \
+		if ( c == EOF && ferror( yyin ) ) \
+			YY_FATAL_ERROR( "input in flex scanner failed" ); \
+		result = n; \
+		} \
+	else \
+		{ \
+		errno=0; \
+		while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
+			{ \
+			if( errno != EINTR) \
+				{ \
+				YY_FATAL_ERROR( "input in flex scanner failed" ); \
+				break; \
+				} \
+			errno=0; \
+			clearerr(yyin); \
+			} \
+		}\
+\
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+#endif
+
+/* end tables serialization structures and prototypes */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+
+extern int yylex (void);
+
+#define YY_DECL int yylex (void)
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after yytext and yyleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+	YY_USER_ACTION
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp, *yy_bp;
+	register int yy_act;
+    
+#line 34 "fmd_scanner.l"
+
+
+#line 691 "<stdout>"
+
+	if ( !(yy_init) )
+		{
+		(yy_init) = 1;
+
+#ifdef YY_USER_INIT
+		YY_USER_INIT;
+#endif
+
+		if ( ! (yy_start) )
+			(yy_start) = 1;	/* first start state */
+
+		if ( ! yyin )
+			yyin = stdin;
+
+		if ( ! yyout )
+			yyout = stdout;
+
+		if ( ! YY_CURRENT_BUFFER ) {
+			yyensure_buffer_stack ();
+			YY_CURRENT_BUFFER_LVALUE =
+				yy_create_buffer(yyin,YY_BUF_SIZE );
+		}
+
+		yy_load_buffer_state( );
+		}
+
+	while ( 1 )		/* loops until end-of-file is reached */
+		{
+		yy_cp = (yy_c_buf_p);
+
+		/* Support of yytext. */
+		*yy_cp = (yy_hold_char);
+
+		/* yy_bp points to the position in yy_ch_buf of the start of
+		 * the current run.
+		 */
+		yy_bp = yy_cp;
+
+		yy_current_state = (yy_start);
+yy_match:
+		do
+			{
+			register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
+			if ( yy_accept[yy_current_state] )
+				{
+				(yy_last_accepting_state) = yy_current_state;
+				(yy_last_accepting_cpos) = yy_cp;
+				}
+			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+				{
+				yy_current_state = (int) yy_def[yy_current_state];
+				if ( yy_current_state >= 24 )
+					yy_c = yy_meta[(unsigned int) yy_c];
+				}
+			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+			++yy_cp;
+			}
+		while ( yy_base[yy_current_state] != 34 );
+
+yy_find_action:
+		yy_act = yy_accept[yy_current_state];
+		if ( yy_act == 0 )
+			{ /* have to back up */
+			yy_cp = (yy_last_accepting_cpos);
+			yy_current_state = (yy_last_accepting_state);
+			yy_act = yy_accept[yy_current_state];
+			}
+
+		YY_DO_BEFORE_ACTION;
+
+do_action:	/* This label is used only to access EOF actions. */
+
+		switch ( yy_act )
+	{ /* beginning of action switch */
+			case 0: /* must back up */
+			/* undo the effects of YY_DO_BEFORE_ACTION */
+			*yy_cp = (yy_hold_char);
+			yy_cp = (yy_last_accepting_cpos);
+			yy_current_state = (yy_last_accepting_state);
+			goto yy_find_action;
+
+case 1:
+/* rule 1 can match eol */
+YY_RULE_SETUP
+#line 36 "fmd_scanner.l"
+/* Eat whitespace. */
+	YY_BREAK
+case 2:
+*yy_cp = (yy_hold_char); /* undo effects of setting up yytext */
+(yy_c_buf_p) = yy_cp -= 1;
+YY_DO_BEFORE_ACTION; /* set up yytext again */
+YY_RULE_SETUP
+#line 37 "fmd_scanner.l"
+/* Eat comments. */
+	YY_BREAK
+case 3:
+#line 39 "fmd_scanner.l"
+case 4:
+YY_RULE_SETUP
+#line 39 "fmd_scanner.l"
+return parse_integer(yytext, 10);
+	YY_BREAK
+case 5:
+YY_RULE_SETUP
+#line 40 "fmd_scanner.l"
+return OCTAL;
+	YY_BREAK
+case 6:
+YY_RULE_SETUP
+#line 41 "fmd_scanner.l"
+return parse_integer(yytext + 2, 16);
+	YY_BREAK
+case 7:
+YY_RULE_SETUP
+#line 42 "fmd_scanner.l"
+return copy_string(yytext);
+	YY_BREAK
+case 8:
+YY_RULE_SETUP
+#line 43 "fmd_scanner.l"
+return *yytext;
+	YY_BREAK
+case 9:
+YY_RULE_SETUP
+#line 45 "fmd_scanner.l"
+ECHO;
+	YY_BREAK
+#line 820 "<stdout>"
+case YY_STATE_EOF(INITIAL):
+	yyterminate();
+
+	case YY_END_OF_BUFFER:
+		{
+		/* Amount of text matched not including the EOB char. */
+		int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+		/* Undo the effects of YY_DO_BEFORE_ACTION. */
+		*yy_cp = (yy_hold_char);
+		YY_RESTORE_YY_MORE_OFFSET
+
+		if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+			{
+			/* We're scanning a new file or input source.  It's
+			 * possible that this happened because the user
+			 * just pointed yyin at a new source and called
+			 * yylex().  If so, then we have to assure
+			 * consistency between YY_CURRENT_BUFFER and our
+			 * globals.  Here is the right place to do so, because
+			 * this is the first action (other than possibly a
+			 * back-up) that will match for the new input source.
+			 */
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+			YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+			}
+
+		/* Note that here we test for yy_c_buf_p "<=" to the position
+		 * of the first EOB in the buffer, since yy_c_buf_p will
+		 * already have been incremented past the NUL character
+		 * (since all states make transitions on EOB to the
+		 * end-of-buffer state).  Contrast this with the test
+		 * in input().
+		 */
+		if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			{ /* This was really a NUL. */
+			yy_state_type yy_next_state;
+
+			(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+			yy_current_state = yy_get_previous_state(  );
+
+			/* Okay, we're now positioned to make the NUL
+			 * transition.  We couldn't have
+			 * yy_get_previous_state() go ahead and do it
+			 * for us because it doesn't know how to deal
+			 * with the possibility of jamming (and we don't
+			 * want to build jamming into it because then it
+			 * will run more slowly).
+			 */
+
+			yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+			yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+			if ( yy_next_state )
+				{
+				/* Consume the NUL. */
+				yy_cp = ++(yy_c_buf_p);
+				yy_current_state = yy_next_state;
+				goto yy_match;
+				}
+
+			else
+				{
+				yy_cp = (yy_c_buf_p);
+				goto yy_find_action;
+				}
+			}
+
+		else switch ( yy_get_next_buffer(  ) )
+			{
+			case EOB_ACT_END_OF_FILE:
+				{
+				(yy_did_buffer_switch_on_eof) = 0;
+
+				if ( yywrap( ) )
+					{
+					/* Note: because we've taken care in
+					 * yy_get_next_buffer() to have set up
+					 * yytext, we can now set up
+					 * yy_c_buf_p so that if some total
+					 * hoser (like flex itself) wants to
+					 * call the scanner after we return the
+					 * YY_NULL, it'll still work - another
+					 * YY_NULL will get returned.
+					 */
+					(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+					yy_act = YY_STATE_EOF(YY_START);
+					goto do_action;
+					}
+
+				else
+					{
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+					}
+				break;
+				}
+
+			case EOB_ACT_CONTINUE_SCAN:
+				(yy_c_buf_p) =
+					(yytext_ptr) + yy_amount_of_matched_text;
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_match;
+
+			case EOB_ACT_LAST_MATCH:
+				(yy_c_buf_p) =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_find_action;
+			}
+		break;
+		}
+
+	default:
+		YY_FATAL_ERROR(
+			"fatal flex scanner internal error--no action found" );
+	} /* end of action switch */
+		} /* end of scanning one token */
+} /* end of yylex */
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ *	EOB_ACT_LAST_MATCH -
+ *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ *	EOB_ACT_END_OF_FILE - end of file
+ */
+static int yy_get_next_buffer (void)
+{
+    	register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+	register char *source = (yytext_ptr);
+	register int number_to_move, i;
+	int ret_val;
+
+	if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+		YY_FATAL_ERROR(
+		"fatal flex scanner internal error--end of buffer missed" );
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+		{ /* Don't try to fill the buffer, so this is an EOF. */
+		if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+			{
+			/* We matched a single character, the EOB, so
+			 * treat this as a final EOF.
+			 */
+			return EOB_ACT_END_OF_FILE;
+			}
+
+		else
+			{
+			/* We matched some text prior to the EOB, first
+			 * process it.
+			 */
+			return EOB_ACT_LAST_MATCH;
+			}
+		}
+
+	/* Try to read more data. */
+
+	/* First move last chars to start of buffer. */
+	number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+	for ( i = 0; i < number_to_move; ++i )
+		*(dest++) = *(source++);
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+		/* don't do the read, it's not guaranteed to return an EOF,
+		 * just force an EOF
+		 */
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+	else
+		{
+			int num_to_read =
+			YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+		while ( num_to_read <= 0 )
+			{ /* Not enough room in the buffer - grow it. */
+
+			/* just a shorter name for the current buffer */
+			YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+			int yy_c_buf_p_offset =
+				(int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+			if ( b->yy_is_our_buffer )
+				{
+				int new_size = b->yy_buf_size * 2;
+
+				if ( new_size <= 0 )
+					b->yy_buf_size += b->yy_buf_size / 8;
+				else
+					b->yy_buf_size *= 2;
+
+				b->yy_ch_buf = (char *)
+					/* Include room in for 2 EOB chars. */
+					yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2  );
+				}
+			else
+				/* Can't grow it, we don't own it. */
+				b->yy_ch_buf = 0;
+
+			if ( ! b->yy_ch_buf )
+				YY_FATAL_ERROR(
+				"fatal error - scanner input buffer overflow" );
+
+			(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+			num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+						number_to_move - 1;
+
+			}
+
+		if ( num_to_read > YY_READ_BUF_SIZE )
+			num_to_read = YY_READ_BUF_SIZE;
+
+		/* Read in more data. */
+		YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+			(yy_n_chars), (size_t) num_to_read );
+
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	if ( (yy_n_chars) == 0 )
+		{
+		if ( number_to_move == YY_MORE_ADJ )
+			{
+			ret_val = EOB_ACT_END_OF_FILE;
+			yyrestart(yyin  );
+			}
+
+		else
+			{
+			ret_val = EOB_ACT_LAST_MATCH;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+				YY_BUFFER_EOF_PENDING;
+			}
+		}
+
+	else
+		ret_val = EOB_ACT_CONTINUE_SCAN;
+
+	if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
+		/* Extend the array by 50%, plus the number we really need. */
+		yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
+		YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size  );
+		if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
+	}
+
+	(yy_n_chars) += number_to_move;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+	(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+	return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+    static yy_state_type yy_get_previous_state (void)
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp;
+    
+	yy_current_state = (yy_start);
+
+	for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+		{
+		register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+		if ( yy_accept[yy_current_state] )
+			{
+			(yy_last_accepting_state) = yy_current_state;
+			(yy_last_accepting_cpos) = yy_cp;
+			}
+		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+			{
+			yy_current_state = (int) yy_def[yy_current_state];
+			if ( yy_current_state >= 24 )
+				yy_c = yy_meta[(unsigned int) yy_c];
+			}
+		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+		}
+
+	return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ *	next_state = yy_try_NUL_trans( current_state );
+ */
+    static yy_state_type yy_try_NUL_trans  (yy_state_type yy_current_state )
+{
+	register int yy_is_jam;
+    	register char *yy_cp = (yy_c_buf_p);
+
+	register YY_CHAR yy_c = 1;
+	if ( yy_accept[yy_current_state] )
+		{
+		(yy_last_accepting_state) = yy_current_state;
+		(yy_last_accepting_cpos) = yy_cp;
+		}
+	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+		{
+		yy_current_state = (int) yy_def[yy_current_state];
+		if ( yy_current_state >= 24 )
+			yy_c = yy_meta[(unsigned int) yy_c];
+		}
+	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+	yy_is_jam = (yy_current_state == 23);
+
+	return yy_is_jam ? 0 : yy_current_state;
+}
+
+    static void yyunput (int c, register char * yy_bp )
+{
+	register char *yy_cp;
+    
+    yy_cp = (yy_c_buf_p);
+
+	/* undo effects of setting up yytext */
+	*yy_cp = (yy_hold_char);
+
+	if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+		{ /* need to shift things up to make room */
+		/* +2 for EOB chars. */
+		register int number_to_move = (yy_n_chars) + 2;
+		register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+					YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+		register char *source =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+		while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			*--dest = *--source;
+
+		yy_cp += (int) (dest - source);
+		yy_bp += (int) (dest - source);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+		if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+			YY_FATAL_ERROR( "flex scanner push-back overflow" );
+		}
+
+	*--yy_cp = (char) c;
+
+	(yytext_ptr) = yy_bp;
+	(yy_hold_char) = *yy_cp;
+	(yy_c_buf_p) = yy_cp;
+}
+
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+    static int yyinput (void)
+#else
+    static int input  (void)
+#endif
+
+{
+	int c;
+    
+	*(yy_c_buf_p) = (yy_hold_char);
+
+	if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+		{
+		/* yy_c_buf_p now points to the character we want to return.
+		 * If this occurs *before* the EOB characters, then it's a
+		 * valid NUL; if not, then we've hit the end of the buffer.
+		 */
+		if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			/* This was really a NUL. */
+			*(yy_c_buf_p) = '\0';
+
+		else
+			{ /* need more input */
+			int offset = (yy_c_buf_p) - (yytext_ptr);
+			++(yy_c_buf_p);
+
+			switch ( yy_get_next_buffer(  ) )
+				{
+				case EOB_ACT_LAST_MATCH:
+					/* This happens because yy_g_n_b()
+					 * sees that we've accumulated a
+					 * token and flags that we need to
+					 * try matching the token before
+					 * proceeding.  But for input(),
+					 * there's no matching to consider.
+					 * So convert the EOB_ACT_LAST_MATCH
+					 * to EOB_ACT_END_OF_FILE.
+					 */
+
+					/* Reset buffer status. */
+					yyrestart(yyin );
+
+					/*FALLTHROUGH*/
+
+				case EOB_ACT_END_OF_FILE:
+					{
+					if ( yywrap( ) )
+						return EOF;
+
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+#ifdef __cplusplus
+					return yyinput();
+#else
+					return input();
+#endif
+					}
+
+				case EOB_ACT_CONTINUE_SCAN:
+					(yy_c_buf_p) = (yytext_ptr) + offset;
+					break;
+				}
+			}
+		}
+
+	c = *(unsigned char *) (yy_c_buf_p);	/* cast for 8-bit char's */
+	*(yy_c_buf_p) = '\0';	/* preserve yytext */
+	(yy_hold_char) = *++(yy_c_buf_p);
+
+	return c;
+}
+#endif	/* ifndef YY_NO_INPUT */
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ * 
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+    void yyrestart  (FILE * input_file )
+{
+    
+	if ( ! YY_CURRENT_BUFFER ){
+        yyensure_buffer_stack ();
+		YY_CURRENT_BUFFER_LVALUE =
+            yy_create_buffer(yyin,YY_BUF_SIZE );
+	}
+
+	yy_init_buffer(YY_CURRENT_BUFFER,input_file );
+	yy_load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ * 
+ */
+    void yy_switch_to_buffer  (YY_BUFFER_STATE  new_buffer )
+{
+    
+	/* TODO. We should be able to replace this entire function body
+	 * with
+	 *		yypop_buffer_state();
+	 *		yypush_buffer_state(new_buffer);
+     */
+	yyensure_buffer_stack ();
+	if ( YY_CURRENT_BUFFER == new_buffer )
+		return;
+
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+	yy_load_buffer_state( );
+
+	/* We don't actually know whether we did this switch during
+	 * EOF (yywrap()) processing, but the only time this flag
+	 * is looked at is after yywrap() is called, so it's safe
+	 * to go ahead and always set it.
+	 */
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+static void yy_load_buffer_state  (void)
+{
+    	(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+	(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+	yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+	(yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ * 
+ * @return the allocated buffer state.
+ */
+    YY_BUFFER_STATE yy_create_buffer  (FILE * file, int  size )
+{
+	YY_BUFFER_STATE b;
+    
+	b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+	b->yy_buf_size = size;
+
+	/* yy_ch_buf has to be 2 characters longer than the size given because
+	 * we need to put in 2 end-of-buffer characters.
+	 */
+	b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2  );
+	if ( ! b->yy_ch_buf )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+	b->yy_is_our_buffer = 1;
+
+	yy_init_buffer(b,file );
+
+	return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with yy_create_buffer()
+ * 
+ */
+    void yy_delete_buffer (YY_BUFFER_STATE  b )
+{
+    
+	if ( ! b )
+		return;
+
+	if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+		YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+	if ( b->yy_is_our_buffer )
+		yyfree((void *) b->yy_ch_buf  );
+
+	yyfree((void *) b  );
+}
+
+#ifndef __cplusplus
+extern int isatty (int );
+#endif /* __cplusplus */
+    
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a yyrestart() or at EOF.
+ */
+    static void yy_init_buffer  (YY_BUFFER_STATE  b, FILE * file )
+
+{
+	int oerrno = errno;
+    
+	yy_flush_buffer(b );
+
+	b->yy_input_file = file;
+	b->yy_fill_buffer = 1;
+
+    /* If b is the current buffer, then yy_init_buffer was _probably_
+     * called from yyrestart() or through yy_get_next_buffer.
+     * In that case, we don't want to reset the lineno or column.
+     */
+    if (b != YY_CURRENT_BUFFER){
+        b->yy_bs_lineno = 1;
+        b->yy_bs_column = 0;
+    }
+
+        b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
+    
+	errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ * 
+ */
+    void yy_flush_buffer (YY_BUFFER_STATE  b )
+{
+    	if ( ! b )
+		return;
+
+	b->yy_n_chars = 0;
+
+	/* We always need two end-of-buffer characters.  The first causes
+	 * a transition to the end-of-buffer state.  The second causes
+	 * a jam in that state.
+	 */
+	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+	b->yy_buf_pos = &b->yy_ch_buf[0];
+
+	b->yy_at_bol = 1;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	if ( b == YY_CURRENT_BUFFER )
+		yy_load_buffer_state( );
+}
+
+/** Pushes the new state onto the stack. The new state becomes
+ *  the current state. This function will allocate the stack
+ *  if necessary.
+ *  @param new_buffer The new state.
+ *  
+ */
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer )
+{
+    	if (new_buffer == NULL)
+		return;
+
+	yyensure_buffer_stack();
+
+	/* This block is copied from yy_switch_to_buffer. */
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	/* Only push if top exists. Otherwise, replace top. */
+	if (YY_CURRENT_BUFFER)
+		(yy_buffer_stack_top)++;
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+	/* copied from yy_switch_to_buffer. */
+	yy_load_buffer_state( );
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+/** Removes and deletes the top of the stack, if present.
+ *  The next element becomes the new top.
+ *  
+ */
+void yypop_buffer_state (void)
+{
+    	if (!YY_CURRENT_BUFFER)
+		return;
+
+	yy_delete_buffer(YY_CURRENT_BUFFER );
+	YY_CURRENT_BUFFER_LVALUE = NULL;
+	if ((yy_buffer_stack_top) > 0)
+		--(yy_buffer_stack_top);
+
+	if (YY_CURRENT_BUFFER) {
+		yy_load_buffer_state( );
+		(yy_did_buffer_switch_on_eof) = 1;
+	}
+}
+
+/* Allocates the stack if it does not exist.
+ *  Guarantees space for at least one push.
+ */
+static void yyensure_buffer_stack (void)
+{
+	int num_to_alloc;
+    
+	if (!(yy_buffer_stack)) {
+
+		/* First allocation is just for 2 elements, since we don't know if this
+		 * scanner will even need a stack. We use 2 instead of 1 to avoid an
+		 * immediate realloc on the next call.
+         */
+		num_to_alloc = 1;
+		(yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
+								(num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		if ( ! (yy_buffer_stack) )
+			YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+								  
+		memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+				
+		(yy_buffer_stack_max) = num_to_alloc;
+		(yy_buffer_stack_top) = 0;
+		return;
+	}
+
+	if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+		/* Increase the buffer to prepare for a possible push. */
+		int grow_size = 8 /* arbitrary grow size */;
+
+		num_to_alloc = (yy_buffer_stack_max) + grow_size;
+		(yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
+								((yy_buffer_stack),
+								num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		if ( ! (yy_buffer_stack) )
+			YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+		/* zero only the new slots.*/
+		memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+		(yy_buffer_stack_max) = num_to_alloc;
+	}
+}
+
+/** Setup the input buffer state to scan directly from a user-specified character buffer.
+ * @param base the character buffer
+ * @param size the size in bytes of the character buffer
+ * 
+ * @return the newly allocated buffer state object. 
+ */
+YY_BUFFER_STATE yy_scan_buffer  (char * base, yy_size_t  size )
+{
+	YY_BUFFER_STATE b;
+    
+	if ( size < 2 ||
+	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
+	     base[size-1] != YY_END_OF_BUFFER_CHAR )
+		/* They forgot to leave room for the EOB's. */
+		return 0;
+
+	b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
+
+	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
+	b->yy_buf_pos = b->yy_ch_buf = base;
+	b->yy_is_our_buffer = 0;
+	b->yy_input_file = 0;
+	b->yy_n_chars = b->yy_buf_size;
+	b->yy_is_interactive = 0;
+	b->yy_at_bol = 1;
+	b->yy_fill_buffer = 0;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	yy_switch_to_buffer(b  );
+
+	return b;
+}
+
+/** Setup the input buffer state to scan a string. The next call to yylex() will
+ * scan from a @e copy of @a str.
+ * @param yystr a NUL-terminated string to scan
+ * 
+ * @return the newly allocated buffer state object.
+ * @note If you want to scan bytes that may contain NUL values, then use
+ *       yy_scan_bytes() instead.
+ */
+YY_BUFFER_STATE yy_scan_string (yyconst char * yystr )
+{
+    
+	return yy_scan_bytes(yystr,strlen(yystr) );
+}
+
+/** Setup the input buffer state to scan the given bytes. The next call to yylex() will
+ * scan from a @e copy of @a bytes.
+ * @param yybytes the byte buffer to scan
+ * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes.
+ * 
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE yy_scan_bytes  (yyconst char * yybytes, int  _yybytes_len )
+{
+	YY_BUFFER_STATE b;
+	char *buf;
+	yy_size_t n;
+	int i;
+    
+	/* Get memory for full buffer, including space for trailing EOB's. */
+	n = _yybytes_len + 2;
+	buf = (char *) yyalloc(n  );
+	if ( ! buf )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
+
+	for ( i = 0; i < _yybytes_len; ++i )
+		buf[i] = yybytes[i];
+
+	buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
+
+	b = yy_scan_buffer(buf,n );
+	if ( ! b )
+		YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
+
+	/* It's okay to grow etc. this buffer, and we should throw it
+	 * away when we're done.
+	 */
+	b->yy_is_our_buffer = 1;
+
+	return b;
+}
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+static void yy_fatal_error (yyconst char* msg )
+{
+    	(void) fprintf( stderr, "%s\n", msg );
+	exit( YY_EXIT_FAILURE );
+}
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up yytext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		yytext[yyleng] = (yy_hold_char); \
+		(yy_c_buf_p) = yytext + yyless_macro_arg; \
+		(yy_hold_char) = *(yy_c_buf_p); \
+		*(yy_c_buf_p) = '\0'; \
+		yyleng = yyless_macro_arg; \
+		} \
+	while ( 0 )
+
+/* Accessor  methods (get/set functions) to struct members. */
+
+/** Get the current line number.
+ * 
+ */
+int yyget_lineno  (void)
+{
+        
+    return yylineno;
+}
+
+/** Get the input stream.
+ * 
+ */
+FILE *yyget_in  (void)
+{
+        return yyin;
+}
+
+/** Get the output stream.
+ * 
+ */
+FILE *yyget_out  (void)
+{
+        return yyout;
+}
+
+/** Get the length of the current token.
+ * 
+ */
+int yyget_leng  (void)
+{
+        return yyleng;
+}
+
+/** Get the current token.
+ * 
+ */
+
+char *yyget_text  (void)
+{
+        return yytext;
+}
+
+/** Set the current line number.
+ * @param line_number
+ * 
+ */
+void yyset_lineno (int  line_number )
+{
+    
+    yylineno = line_number;
+}
+
+/** Set the input stream. This does not discard the current
+ * input buffer.
+ * @param in_str A readable stream.
+ * 
+ * @see yy_switch_to_buffer
+ */
+void yyset_in (FILE *  in_str )
+{
+        yyin = in_str ;
+}
+
+void yyset_out (FILE *  out_str )
+{
+        yyout = out_str ;
+}
+
+int yyget_debug  (void)
+{
+        return yy_flex_debug;
+}
+
+void yyset_debug (int  bdebug )
+{
+        yy_flex_debug = bdebug ;
+}
+
+static int yy_init_globals (void)
+{
+        /* Initialization is the same as for the non-reentrant scanner.
+     * This function is called from yylex_destroy(), so don't allocate here.
+     */
+
+    (yy_buffer_stack) = 0;
+    (yy_buffer_stack_top) = 0;
+    (yy_buffer_stack_max) = 0;
+    (yy_c_buf_p) = (char *) 0;
+    (yy_init) = 0;
+    (yy_start) = 0;
+
+/* Defined in main.c */
+#ifdef YY_STDINIT
+    yyin = stdin;
+    yyout = stdout;
+#else
+    yyin = (FILE *) 0;
+    yyout = (FILE *) 0;
+#endif
+
+    /* For future reference: Set errno on error, since we are called by
+     * yylex_init()
+     */
+    return 0;
+}
+
+/* yylex_destroy is for both reentrant and non-reentrant scanners. */
+int yylex_destroy  (void)
+{
+    
+    /* Pop the buffer stack, destroying each element. */
+	while(YY_CURRENT_BUFFER){
+		yy_delete_buffer(YY_CURRENT_BUFFER  );
+		YY_CURRENT_BUFFER_LVALUE = NULL;
+		yypop_buffer_state();
+	}
+
+	/* Destroy the stack itself. */
+	yyfree((yy_buffer_stack) );
+	(yy_buffer_stack) = NULL;
+
+    /* Reset the globals. This is important in a non-reentrant scanner so the next time
+     * yylex() is called, initialization will occur. */
+    yy_init_globals( );
+
+    return 0;
+}
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+	register int i;
+	for ( i = 0; i < n; ++i )
+		s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+	register int n;
+	for ( n = 0; s[n]; ++n )
+		;
+
+	return n;
+}
+#endif
+
+void *yyalloc (yy_size_t  size )
+{
+	return (void *) malloc( size );
+}
+
+void *yyrealloc  (void * ptr, yy_size_t  size )
+{
+	/* The cast to (char *) in the following accommodates both
+	 * implementations that use char* generic pointers, and those
+	 * that use void* generic pointers.  It works with the latter
+	 * because both ANSI C and C++ allow castless assignment from
+	 * any pointer type to void*, and deal with argument conversions
+	 * as though doing an assignment.
+	 */
+	return (void *) realloc( (char *) ptr, size );
+}
+
+void yyfree (void * ptr )
+{
+	free( (char *) ptr );	/* see yyrealloc() for (char *) cast */
+}
+
+#define YYTABLES_NAME "yytables"
+
+#line 45 "fmd_scanner.l"
+
+
+
+int parse_integer(char *src, int base)
+{
+	char *multiplier = NULL;
+	unsigned val = strtoul(src, &multiplier, base);
+
+	if (*multiplier) {
+		switch(*multiplier) {
+		case 'K':
+			val *= 1024;
+			break;
+		case 'M':
+			val *= 1024*1024;
+			break;
+		case 'G':
+			val *= 1024*1024*1024;
+			break;
+		default:
+			// If we ever get here, the MULTIPLIER regex is allowing
+			// multiplier suffixes not handled by this code.
+			assert(false);
+		}
+	}
+
+	yylval.intval = val;
+	return INTEGER;
+}
+
+int copy_string(const char *src)
+{
+	yylval.strval = strdup(src);
+	return STRING;
+}
+
diff --git a/util/cbfstool/fmd_scanner.h b/util/cbfstool/fmd_scanner.h
new file mode 100644
index 0000000..6a56c5f
--- /dev/null
+++ b/util/cbfstool/fmd_scanner.h
@@ -0,0 +1,333 @@
+#ifndef yyHEADER_H
+#define yyHEADER_H 1
+#define yyIN_HEADER 1
+
+#line 6 "fmd_scanner.h"
+
+#define  YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 35
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* First, we deal with  platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types. 
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t; 
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN               (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN              (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN              (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX               (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX              (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX              (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX              (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX             (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX             (4294967295U)
+#endif
+
+#endif /* ! C99 */
+
+#endif /* ! FLEXINT_H */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else	/* ! __cplusplus */
+
+/* C99 requires __STDC__ to be defined as 1. */
+#if defined (__STDC__)
+
+#define YY_USE_CONST
+
+#endif	/* defined (__STDC__) */
+#endif	/* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#ifdef __ia64__
+/* On IA-64, the buffer size is 16k, not 8k.
+ * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case.
+ * Ditto for the __ia64__ case accordingly.
+ */
+#define YY_BUF_SIZE 32768
+#else
+#define YY_BUF_SIZE 16384
+#endif /* __ia64__ */
+#endif
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+extern int yyleng;
+
+extern FILE *yyin, *yyout;
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef size_t yy_size_t;
+#endif
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+	{
+	FILE *yy_input_file;
+
+	char *yy_ch_buf;		/* input buffer */
+	char *yy_buf_pos;		/* current position in input buffer */
+
+	/* Size of input buffer in bytes, not including room for EOB
+	 * characters.
+	 */
+	yy_size_t yy_buf_size;
+
+	/* Number of characters read into yy_ch_buf, not including EOB
+	 * characters.
+	 */
+	int yy_n_chars;
+
+	/* Whether we "own" the buffer - i.e., we know we created it,
+	 * and can realloc() it to grow it, and should free() it to
+	 * delete it.
+	 */
+	int yy_is_our_buffer;
+
+	/* Whether this is an "interactive" input source; if so, and
+	 * if we're using stdio for input, then we want to use getc()
+	 * instead of fread(), to make sure we stop fetching input after
+	 * each newline.
+	 */
+	int yy_is_interactive;
+
+	/* Whether we're considered to be at the beginning of a line.
+	 * If so, '^' rules will be active on the next match, otherwise
+	 * not.
+	 */
+	int yy_at_bol;
+
+    int yy_bs_lineno; /**< The line count. */
+    int yy_bs_column; /**< The column count. */
+    
+	/* Whether to try to fill the input buffer when we reach the
+	 * end of it.
+	 */
+	int yy_fill_buffer;
+
+	int yy_buffer_status;
+
+	};
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+void yyrestart (FILE *input_file  );
+void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer  );
+YY_BUFFER_STATE yy_create_buffer (FILE *file,int size  );
+void yy_delete_buffer (YY_BUFFER_STATE b  );
+void yy_flush_buffer (YY_BUFFER_STATE b  );
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer  );
+void yypop_buffer_state (void );
+
+YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size  );
+YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str  );
+YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len  );
+
+void *yyalloc (yy_size_t  );
+void *yyrealloc (void *,yy_size_t  );
+void yyfree (void *  );
+
+/* Begin user sect3 */
+
+#define yywrap(n) 1
+#define YY_SKIP_YYWRAP
+
+extern int yylineno;
+
+extern char *yytext;
+#define yytext_ptr yytext
+
+#ifdef YY_HEADER_EXPORT_START_CONDITIONS
+#define INITIAL 0
+
+#endif
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+/* Accessor methods to globals.
+   These are made visible to non-reentrant scanners for convenience. */
+
+int yylex_destroy (void );
+
+int yyget_debug (void );
+
+void yyset_debug (int debug_flag  );
+
+YY_EXTRA_TYPE yyget_extra (void );
+
+void yyset_extra (YY_EXTRA_TYPE user_defined  );
+
+FILE *yyget_in (void );
+
+void yyset_in  (FILE * in_str  );
+
+FILE *yyget_out (void );
+
+void yyset_out  (FILE * out_str  );
+
+int yyget_leng (void );
+
+char *yyget_text (void );
+
+int yyget_lineno (void );
+
+void yyset_lineno (int line_number  );
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int yywrap (void );
+#else
+extern int yywrap (void );
+#endif
+#endif
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#ifdef __ia64__
+/* On IA-64, the buffer size is 16k, not 8k */
+#define YY_READ_BUF_SIZE 16384
+#else
+#define YY_READ_BUF_SIZE 8192
+#endif /* __ia64__ */
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+
+extern int yylex (void);
+
+#define YY_DECL int yylex (void)
+#endif /* !YY_DECL */
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+#undef YY_NEW_FILE
+#undef YY_FLUSH_BUFFER
+#undef yy_set_bol
+#undef yy_new_buffer
+#undef yy_set_interactive
+#undef YY_DO_BEFORE_ACTION
+
+#ifdef YY_DECL_IS_OURS
+#undef YY_DECL_IS_OURS
+#undef YY_DECL
+#endif
+
+#line 45 "fmd_scanner.l"
+
+
+#line 332 "fmd_scanner.h"
+#undef yyIN_HEADER
+#endif /* yyHEADER_H */
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
 
 /*
  * Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
 #include <sys/mman.h>
 #include <libgen.h>
 #include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
 
 #ifdef __OpenBSD__
 #include <sys/param.h>
@@ -42,18 +45,12 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
 
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
-#include "timestamp.h"
-
 #define CBMEM_VERSION "1.1"
 
 /* verbose output? */


From gerrit at coreboot.org  Fri Sep 11 05:40:15 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 05:40:15 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prepare
	for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <I176d0ae0ae1933cdf6adac67d393ba676198861a+7@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11595

-gerrit

commit b0fb4246bcabbc80444ede6b3a552215a40fe163
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 69 ++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 1f41d17..03828f7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,14 +50,11 @@ struct rmod_context {
 	Elf64_Xword nrelocs;
 	Elf64_Addr *emitted_relocs;
 
-	/* The following fields are addresses within the linked program. */
-	Elf64_Addr link_addr;
-	Elf64_Addr entry;
+	/* The following fields are addresses within the linked program.  */
 	Elf64_Addr parameters_begin;
 	Elf64_Addr parameters_end;
 	Elf64_Addr bss_begin;
 	Elf64_Addr bss_end;
-	Elf64_Xword size;
 };
 
 /*
@@ -371,7 +368,7 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 	return -1;
 }
 
-static int populate_program_info(struct rmod_context *ctx)
+static int populate_rmodule_info(struct rmod_context *ctx)
 {
 	int i;
 	const char *strtab;
@@ -423,15 +420,6 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
-	/* Honor the entry point within the ELF header. */
-	ctx->entry = ehdr->e_entry;
-
-	/* Link address is the virtual address of the program segment. */
-	ctx->link_addr = ctx->phdr->p_vaddr;
-
-	/* The program size is the memsz of the program segment. */
-	ctx->size = ctx->phdr->p_memsz;
-
 	return 0;
 }
 
@@ -516,7 +504,6 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 
 	/* Create ELF writer with modified entry point. */
 	memcpy(&ehdr, &ctx->pelf.ehdr, sizeof(ehdr));
-	ehdr.e_entry = ctx->entry;
 	ew = elf_writer_init(&ehdr);
 
 	if (ew == NULL) {
@@ -544,11 +531,11 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 		loc += ctx->nrelocs * sizeof(Elf32_Addr);
 	ctx->xdr->put32(&rmod_header, loc);
 	/* module_link_start_address */
-	ctx->xdr->put32(&rmod_header, ctx->link_addr);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_vaddr);
 	/* module_program_size */
-	ctx->xdr->put32(&rmod_header, ctx->size);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_memsz);
 	/* module_entry_point */
-	ctx->xdr->put32(&rmod_header, ctx->entry);
+	ctx->xdr->put32(&rmod_header, ctx->pelf.ehdr.e_entry);
 	/* parameters_begin */
 	ctx->xdr->put32(&rmod_header, ctx->parameters_begin);
 	/* parameters_end */
@@ -631,16 +618,15 @@ out:
 	return ret;
 }
 
-int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
-	struct rmod_context ctx;
 	struct parsed_elf *pelf;
 	int i;
 	int ret;
 
 	ret = -1;
-	memset(&ctx, 0, sizeof(ctx));
-	pelf = &ctx.pelf;
+	memset(ctx, 0, sizeof(*ctx));
+	pelf = &ctx->pelf;
 
 	if (parse_elf(elfin, pelf, ELF_PARSE_ALL)) {
 		ERROR("Couldn't parse ELF!\n");
@@ -656,32 +642,52 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	/* Determine if architecture is supported. */
 	for (i = 0; i < ARRAY_SIZE(reloc_ops); i++) {
 		if (reloc_ops[i].arch == pelf->ehdr.e_machine) {
-			ctx.ops = &reloc_ops[i];
+			ctx->ops = &reloc_ops[i];
 			break;
 		}
 	}
 
-	if (ctx.ops == NULL) {
+	if (ctx->ops == NULL) {
 		ERROR("ELF is unsupported arch: %u.\n", pelf->ehdr.e_machine);
 		goto out;
 	}
 
 	/* Set the endian ops. */
-	if (ctx.pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
-		ctx.xdr = &xdr_be;
+	if (ctx->pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
+		ctx->xdr = &xdr_be;
 	else
-		ctx.xdr = &xdr_le;
+		ctx->xdr = &xdr_le;
 
-	if (find_program_segment(&ctx))
+	if (find_program_segment(ctx))
 		goto out;
 
-	if (filter_relocation_sections(&ctx))
+	if (filter_relocation_sections(ctx))
+		goto out;
+
+	ret = 0;
+
+out:
+	return ret;
+}
+
+static void rmodule_cleanup(struct rmod_context *ctx)
+{
+	free(ctx->emitted_relocs);
+	parsed_elf_destroy(&ctx->pelf);
+}
+
+int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+{
+	struct rmod_context ctx;
+	int ret = -1;
+
+	if (rmodule_init(&ctx, elfin))
 		goto out;
 
 	if (collect_relocations(&ctx))
 		goto out;
 
-	if (populate_program_info(&ctx))
+	if (populate_rmodule_info(&ctx))
 		goto out;
 
 	if (write_elf(&ctx, elfin, elfout))
@@ -690,7 +696,6 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	ret = 0;
 
 out:
-	free(ctx.emitted_relocs);
-	parsed_elf_destroy(pelf);
+	rmodule_cleanup(&ctx);
 	return ret;
 }


From gerrit at coreboot.org  Fri Sep 11 05:44:01 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 05:44:01 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: corebot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+9@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 57f9722922cda2c3596bfe5c4bc41332b9c59611
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    corebot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                                       |   4 +-
 src/arch/x86/include/arch/cbfs.h                   |   2 +-
 src/arch/x86/romcc_console.c                       |   2 +-
 src/commonlib/Makefile.inc                         |  10 +
 src/commonlib/include/commonlib/cbfs_serialized.h  | 190 ++++++++++
 src/commonlib/include/commonlib/cbmem_id.h         | 113 ++++++
 src/commonlib/include/commonlib/coreboot_tables.h  | 387 +++++++++++++++++++++
 src/commonlib/include/commonlib/fmap_serialized.h  |  73 ++++
 src/commonlib/include/commonlib/helpers.h          |  51 +++
 src/commonlib/include/commonlib/loglevel.h         | 178 ++++++++++
 src/commonlib/include/commonlib/mem_pool.h         |  73 ++++
 src/commonlib/include/commonlib/region.h           | 157 +++++++++
 src/commonlib/include/commonlib/rmodule-defs.h     |  63 ++++
 .../include/commonlib/timestamp_serialized.h       |  92 +++++
 src/commonlib/mem_pool.c                           |  51 +++
 src/commonlib/region.c                             | 196 +++++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |   2 +-
 src/include/assets.h                               |   2 +-
 src/include/boot/coreboot_tables.h                 | 384 +-------------------
 src/include/boot_device.h                          |   2 +-
 src/include/cbfs.h                                 |   4 +-
 src/include/cbfs_serialized.h                      | 190 ----------
 src/include/cbmem.h                                |   2 +-
 src/include/cbmem_id.h                             | 113 ------
 src/include/console/console.h                      |   2 +-
 src/include/console/early_print.h                  |   2 +-
 src/include/console/loglevel.h                     | 178 ----------
 src/include/fmap.h                                 |   4 +-
 src/include/fmap_serialized.h                      |  73 ----
 src/include/mem_pool.h                             |  73 ----
 src/include/region.h                               | 157 ---------
 src/include/rmodule-defs.h                         |  63 ----
 src/include/rmodule.h                              |   2 +-
 src/include/stddef.h                               |  34 +-
 src/include/stdlib.h                               |  14 -
 src/include/timestamp.h                            |  69 +---
 src/lib/Makefile.inc                               |   9 -
 src/lib/cbfs_boot_props.c                          |   2 +-
 src/lib/fmap.c                                     |   2 +-
 src/lib/mem_pool.c                                 |  51 ---
 src/lib/region.c                                   | 196 -----------
 src/mainboard/advansus/a785e-i/romstage.c          |   2 +-
 src/mainboard/amd/bimini_fam10/romstage.c          |   2 +-
 src/mainboard/amd/dinar/romstage.c                 |   2 +-
 src/mainboard/amd/inagua/romstage.c                |   2 +-
 src/mainboard/amd/lamar/romstage.c                 |   2 +-
 src/mainboard/amd/mahogany_fam10/romstage.c        |   2 +-
 src/mainboard/amd/olivehill/romstage.c             |   2 +-
 src/mainboard/amd/olivehillplus/romstage.c         |   2 +-
 src/mainboard/amd/parmer/romstage.c                |   2 +-
 src/mainboard/amd/persimmon/romstage.c             |   2 +-
 .../amd/serengeti_cheetah_fam10/romstage.c         |   2 +-
 src/mainboard/amd/south_station/romstage.c         |   2 +-
 src/mainboard/amd/thatcher/romstage.c              |   2 +-
 src/mainboard/amd/tilapia_fam10/romstage.c         |   2 +-
 src/mainboard/amd/torpedo/romstage.c               |   2 +-
 src/mainboard/amd/union_station/romstage.c         |   2 +-
 src/mainboard/asrock/e350m1/romstage.c             |   2 +-
 src/mainboard/asrock/imb-a180/romstage.c           |   2 +-
 src/mainboard/asus/m4a78-em/romstage.c             |   2 +-
 src/mainboard/asus/m4a785-m/romstage.c             |   2 +-
 src/mainboard/asus/m5a88-v/romstage.c              |   2 +-
 src/mainboard/avalue/eax-785e/romstage.c           |   2 +-
 src/mainboard/bap/ode_e20XX/romstage.c             |   2 +-
 src/mainboard/biostar/am1ml/romstage.c             |   2 +-
 src/mainboard/gigabyte/ma785gm/romstage.c          |   2 +-
 src/mainboard/gigabyte/ma785gmt/romstage.c         |   2 +-
 src/mainboard/gigabyte/ma78gm/romstage.c           |   2 +-
 src/mainboard/gizmosphere/gizmo/romstage.c         |   2 +-
 src/mainboard/gizmosphere/gizmo2/romstage.c        |   2 +-
 src/mainboard/google/peach_pit/romstage.c          |   2 +-
 src/mainboard/hp/abm/romstage.c                    |   2 +-
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |   2 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |   2 +-
 src/mainboard/jetway/pa78vm5/romstage.c            |   2 +-
 src/mainboard/lippert/frontrunner-af/romstage.c    |   2 +-
 src/mainboard/lippert/toucan-af/romstage.c         |   2 +-
 src/mainboard/pcengines/apu1/romstage.c            |   2 +-
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |   2 +-
 src/soc/intel/broadwell/include/soc/me.h           |   2 +-
 src/southbridge/amd/cimx/sb700/Platform.h          |   2 +-
 src/southbridge/amd/cimx/sb700/early.c             |   2 +-
 src/southbridge/amd/cimx/sb900/early.c             |   2 +-
 src/vendorcode/amd/agesa/common/Porting.h          |   2 +-
 src/vendorcode/amd/pi/00630F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c    |   2 +-
 src/vendorcode/amd/pi/00730F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/Makefile.inc                 |   1 +
 src/vendorcode/google/chromeos/vboot_common.h      |   2 +-
 util/cbfstool/Makefile                             |   1 +
 util/cbfstool/Makefile.inc                         |   1 +
 util/cbfstool/rmodule.c                            |   2 +-
 util/cbmem/Makefile                                |   2 +-
 util/cbmem/cbmem.c                                 |   9 +-
 95 files changed, 1711 insertions(+), 1673 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..34f3411 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
 #ifndef __INCLUDE_ARCH_CBFS__
 #define __INCLUDE_ARCH_CBFS__
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
 #include <endian.h>
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
 #include <build.h>
 #include <console/streams.h>
 #include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* Include the sources. */
 #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_PAYLOAD    0x20
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+	uint32_t compression;  /** Compression type */
+	uint64_t entry;  /** entry point */
+	uint64_t load;   /** Where to load in memory */
+	uint32_t len;          /** length of data to load */
+	uint32_t memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image.  Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing.   For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed.  This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ *   a particular motherboard is constructed? (Assuming the kernel
+ *   has drivers for all of the hardware but it does not have
+ *   assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not.  This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped.  Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+	uint64_t result;
+	result = value.hi;
+	result = (result << 32) + value.lo;
+	return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+	struct lb_uint64 result;
+	result.lo = (value >> 0) & 0xffffffff;
+	result.hi = (value >> 32) & 0xffffffff;
+	return result;
+}
+
+struct lb_header
+{
+	uint8_t  signature[4]; /* LBIO */
+	uint32_t header_bytes;
+	uint32_t header_checksum;
+	uint32_t table_bytes;
+	uint32_t table_checksum;
+	uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record.  Encoding both type and size.  The type is obviously
+ * so you can tell what it is.  The size allows you to skip that
+ * boot environment record if you don't know what it is.  This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+	uint32_t tag;		/* tag ID */
+	uint32_t size;		/* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED		0x0000
+
+#define LB_TAG_MEMORY		0x0001
+
+struct lb_memory_range {
+	struct lb_uint64 start;
+	struct lb_uint64 size;
+	uint32_t type;
+#define LB_MEM_RAM		 1	/* Memory anyone can use */
+#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
+#define LB_MEM_ACPI		 3	/* ACPI Tables */
+#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
+#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
+#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+	uint32_t tag;
+	uint32_t size;
+	struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB		0x0002
+struct lb_hwrpb {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
+#define LB_TAG_VERSION		0x0004
+#define LB_TAG_EXTRA_VERSION	0x0005
+#define LB_TAG_BUILD		0x0006
+#define LB_TAG_COMPILE_TIME	0x0007
+#define LB_TAG_COMPILE_BY	0x0008
+#define LB_TAG_COMPILE_HOST	0x0009
+#define LB_TAG_COMPILE_DOMAIN	0x000a
+#define LB_TAG_COMPILER		0x000b
+#define LB_TAG_LINKER		0x000c
+#define LB_TAG_ASSEMBLER	0x000d
+struct lb_string {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP	0x0026
+struct lb_timestamp {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL		0x000f
+struct lb_serial {
+	uint32_t tag;
+	uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
+	uint32_t baud;
+	uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE		0x0010
+struct lb_console {
+	uint32_t tag;
+	uint32_t size;
+	uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250	0
+#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI		5
+#define LB_TAG_CONSOLE_SERIAL8250MEM	6
+
+#define LB_TAG_FORWARD		0x0011
+struct lb_forward {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER	0x0012
+struct lb_framebuffer {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t physical_address;
+	uint32_t x_resolution;
+	uint32_t y_resolution;
+	uint32_t bytes_per_line;
+	uint8_t bits_per_pixel;
+	uint8_t red_mask_pos;
+	uint8_t red_mask_size;
+	uint8_t green_mask_pos;
+	uint8_t green_mask_size;
+	uint8_t blue_mask_pos;
+	uint8_t blue_mask_size;
+	uint8_t reserved_mask_pos;
+	uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT		0x0015
+#define LB_TAG_VBNV		0x0019
+#define LB_TAB_VBOOT_HANDOFF	0x0020
+#define LB_TAB_DMA		0x0022
+#define LB_TAG_RAM_OOPS		0x0023
+#define LB_TAG_MTC		0x002b
+struct lb_range {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t range_start;
+	uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+#define LB_TAG_ACPI_GNVS	0x0024
+#define LB_TAG_WIFI_CALIBRATION	0x0027
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR	0x0021
+struct lb_x86_rom_mtrr {
+	uint32_t tag;
+	uint32_t size;
+	/* The variable range MTRR index covering the ROM. */
+	uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID		0x0025
+struct lb_board_id {
+	uint32_t tag;
+	uint32_t size;
+	/* Board ID as retrieved from the board revision GPIOs. */
+	uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS	0x0026
+struct mac_address {
+	uint8_t mac_addr[6];
+	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t count;
+	struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE		0x0028
+struct lb_ram_code {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH	0x0029
+struct lb_spi_flash {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t flash_size;
+	uint32_t sector_size;
+	uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+	uint32_t tag;
+	uint32_t size;
+	/* offsets are relative to start of boot media */
+	uint64_t fmap_offset;
+	uint64_t cbfs_offset;
+	uint64_t cbfs_size;
+	uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO		0x002a
+#define MAX_SERIALNO_LENGTH	32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+	uint32_t tag;               /* CMOS definitions table type */
+	uint32_t size;               /* size of the entire table */
+	uint32_t header_length;      /* length of header */
+};
+
+/* cmos entry record
+        This record is variable length.  The name field may be
+        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+        anywhere in the byte, but can not span bytes unless it
+        starts at the beginning of the byte and the length is
+        fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+	uint32_t tag;                /* entry type */
+	uint32_t size;               /* length of this record */
+	uint32_t bit;                /* starting bit from start of image */
+	uint32_t length;             /* length of field in bits */
+	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
+	uint32_t config_id;          /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+					       variable length int aligned */
+};
+
+
+/* cmos enumerations record
+        This record is variable length.  The text field may be
+        shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+	uint32_t tag;		     /* enumeration type */
+	uint32_t size; 		     /* length of this record */
+	uint32_t config_id;          /* a number identifying the config id */
+	uint32_t value;              /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+						variable length int aligned */
+};
+
+/* cmos defaults record
+        This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+	uint32_t tag;                /* default type */
+	uint32_t size;               /* length of this record */
+	uint32_t name_length;        /* length of the following name field */
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct	cmos_checksum {
+	uint32_t tag;
+	uint32_t size;
+	/* In practice everything is byte aligned, but things are measured
+	 * in bits to be consistent.
+	 */
+	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
+	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
+	uint32_t location;	/* First bit of the checksum (byte aligned) */
+	uint32_t type;		/* Checksum algorithm that is used */
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __attribute__((packed));
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint16_t	max_entries;
+	uint16_t	tick_freq_mhz;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_VBOOT = 5,
+	TS_END_VBOOT = 6,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_START_BOOTBLOCK = 11,
+	TS_END_BOOTBLOCK = 12,
+	TS_START_COPYROM = 13,
+	TS_END_COPYROM = 14,
+	TS_START_ULZMA = 15,
+	TS_END_ULZMA = 16,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+
+	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+	TS_START_COPYVER = 501,
+	TS_END_COPYVER = 502,
+	TS_START_TPMINIT = 503,
+	TS_END_TPMINIT = 504,
+	TS_START_VERIFY_SLOT = 505,
+	TS_END_VERIFY_SLOT = 506,
+	TS_START_HASH_BODY = 507,
+	TS_DONE_LOADING = 508,
+	TS_DONE_HASHING = 509,
+	TS_END_HASH_BODY = 510,
+
+	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+	TS_FSP_MEMORY_INIT_START = 950,
+	TS_FSP_MEMORY_INIT_END = 951,
+	TS_FSP_TEMP_RAM_EXIT_START = 952,
+	TS_FSP_TEMP_RAM_EXIT_END = 953,
+	TS_FSP_SILICON_INIT_START = 954,
+	TS_FSP_SILICON_INIT_END = 955,
+	TS_FSP_BEFORE_ENUMERATE = 956,
+	TS_FSP_AFTER_ENUMERATE = 957,
+	TS_FSP_BEFORE_FINALIZE = 958,
+	TS_FSP_AFTER_FINALIZE = 959,
+
+	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 9695b3b..b3772a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
 #include <fsp/soc_binding.h>
 #include <fsp/gop.h>
 #include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
 #ifndef ASSETS_H
 #define ASSETS_H
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* An asset represents data used to boot the system. It can be found within
  * CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
 #ifndef COREBOOT_TABLES_H
 #define COREBOOT_TABLES_H
 
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image.  Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing.   For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed.  This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- *   a particular motherboard is constructed? (Assuming the kernel
- *   has drivers for all of the hardware but it does not have
- *   assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not.  This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped.  Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
-	uint32_t lo;
-	uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
-	uint64_t result;
-	result = value.hi;
-	result = (result << 32) + value.lo;
-	return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
-	struct lb_uint64 result;
-	result.lo = (value >> 0) & 0xffffffff;
-	result.hi = (value >> 32) & 0xffffffff;
-	return result;
-}
-
-struct lb_header
-{
-	uint8_t  signature[4]; /* LBIO */
-	uint32_t header_bytes;
-	uint32_t header_checksum;
-	uint32_t table_bytes;
-	uint32_t table_checksum;
-	uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record.  Encoding both type and size.  The type is obviously
- * so you can tell what it is.  The size allows you to skip that
- * boot environment record if you don't know what it is.  This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
-	uint32_t tag;		/* tag ID */
-	uint32_t size;		/* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED		0x0000
-
-#define LB_TAG_MEMORY		0x0001
-
-struct lb_memory_range {
-	struct lb_uint64 start;
-	struct lb_uint64 size;
-	uint32_t type;
-#define LB_MEM_RAM		 1	/* Memory anyone can use */
-#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
-#define LB_MEM_ACPI		 3	/* ACPI Tables */
-#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
-#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
-#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
-	uint32_t tag;
-	uint32_t size;
-	struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB		0x0002
-struct lb_hwrpb {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD	0x0003
-struct lb_mainboard {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  vendor_idx;
-	uint8_t  part_number_idx;
-	uint8_t  strings[0];
-};
-
-#define LB_TAG_VERSION		0x0004
-#define LB_TAG_EXTRA_VERSION	0x0005
-#define LB_TAG_BUILD		0x0006
-#define LB_TAG_COMPILE_TIME	0x0007
-#define LB_TAG_COMPILE_BY	0x0008
-#define LB_TAG_COMPILE_HOST	0x0009
-#define LB_TAG_COMPILE_DOMAIN	0x000a
-#define LB_TAG_COMPILER		0x000b
-#define LB_TAG_LINKER		0x000c
-#define LB_TAG_ASSEMBLER	0x000d
-struct lb_string {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP	0x0026
-struct lb_timestamp {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL		0x000f
-struct lb_serial {
-	uint32_t tag;
-	uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED     1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
-	uint32_t type;
-	uint32_t baseaddr;
-	uint32_t baud;
-	uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE		0x0010
-struct lb_console {
-	uint32_t tag;
-	uint32_t size;
-	uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250	0
-#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI		5
-#define LB_TAG_CONSOLE_SERIAL8250MEM	6
-
-#define LB_TAG_FORWARD		0x0011
-struct lb_forward {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER	0x0012
-struct lb_framebuffer {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t physical_address;
-	uint32_t x_resolution;
-	uint32_t y_resolution;
-	uint32_t bytes_per_line;
-	uint8_t bits_per_pixel;
-	uint8_t red_mask_pos;
-	uint8_t red_mask_size;
-	uint8_t green_mask_pos;
-	uint8_t green_mask_size;
-	uint8_t blue_mask_pos;
-	uint8_t blue_mask_size;
-	uint8_t reserved_mask_pos;
-	uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO	0x0013
-
-struct lb_gpio {
-	uint32_t port;
-	uint32_t polarity;
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-	uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
-        uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
-	uint32_t tag;
-	uint32_t size;
-
-	uint32_t count;
-	struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT		0x0015
-#define LB_TAG_VBNV		0x0019
-#define LB_TAB_VBOOT_HANDOFF	0x0020
-#define LB_TAB_DMA		0x0022
-#define LB_TAG_RAM_OOPS		0x0023
-#define LB_TAG_MTC		0x002b
-struct lb_range {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t range_start;
-	uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS	0x0016
-#define LB_TAG_CBMEM_CONSOLE	0x0017
-#define LB_TAG_MRC_CACHE	0x0018
-#define LB_TAG_ACPI_GNVS	0x0024
-#define LB_TAG_WIFI_CALIBRATION	0x0027
-struct lb_cbmem_ref {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR	0x0021
-struct lb_x86_rom_mtrr {
-	uint32_t tag;
-	uint32_t size;
-	/* The variable range MTRR index covering the ROM. */
-	uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID		0x0025
-struct lb_board_id {
-	uint32_t tag;
-	uint32_t size;
-	/* Board ID as retrieved from the board revision GPIOs. */
-	uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS	0x0026
-struct mac_address {
-	uint8_t mac_addr[6];
-	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t count;
-	struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE		0x0028
-struct lb_ram_code {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH	0x0029
-struct lb_spi_flash {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t flash_size;
-	uint32_t sector_size;
-	uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
-	uint32_t tag;
-	uint32_t size;
-	/* offsets are relative to start of boot media */
-	uint64_t fmap_offset;
-	uint64_t cbfs_offset;
-	uint64_t cbfs_size;
-	uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO		0x002a
-#define MAX_SERIALNO_LENGTH	32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
-	uint32_t tag;               /* CMOS definitions table type */
-	uint32_t size;               /* size of the entire table */
-	uint32_t header_length;      /* length of header */
-};
-
-/* cmos entry record
-        This record is variable length.  The name field may be
-        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
-        anywhere in the byte, but can not span bytes unless it
-        starts at the beginning of the byte and the length is
-        fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
-	uint32_t tag;                /* entry type */
-	uint32_t size;               /* length of this record */
-	uint32_t bit;                /* starting bit from start of image */
-	uint32_t length;             /* length of field in bits */
-	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
-	uint32_t config_id;          /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
-					       variable length int aligned */
-};
-
-
-/* cmos enumerations record
-        This record is variable length.  The text field may be
-        shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
-	uint32_t tag;		     /* enumeration type */
-	uint32_t size; 		     /* length of this record */
-	uint32_t config_id;          /* a number identifying the config id */
-	uint32_t value;              /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
-	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
-						variable length int aligned */
-};
-
-/* cmos defaults record
-        This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
-	uint32_t tag;                /* default type */
-	uint32_t size;               /* length of this record */
-	uint32_t name_length;        /* length of the following name field */
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
-	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct	cmos_checksum {
-	uint32_t tag;
-	uint32_t size;
-	/* In practice everything is byte aligned, but things are measured
-	 * in bits to be consistent.
-	 */
-	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
-	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
-	uint32_t location;	/* First bit of the checksum (byte aligned) */
-	uint32_t type;		/* Checksum algorithm that is used */
-#define CHECKSUM_NONE	0
-#define CHECKSUM_PCBIOS	1
-};
-
+#include <commonlib/coreboot_tables.h>
 /* function prototypes for building the coreboot table */
 
 unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
 #ifndef _BOOT_DEVICE_H_
 #define _BOOT_DEVICE_H_
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* Return the region_device for the read-only boot device. */
 const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
 #include <program_loading.h>
-#include <region.h>
 
 /*
  * CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
-    algorithms that coreboot knows about for stages and
-    payloads.  Of course, other CBFS users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE      0x10
-#define CBFS_TYPE_PAYLOAD    0x20
-#define CBFS_TYPE_OPTIONROM  0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW        0x50
-#define CBFS_TYPE_VSA        0x51
-#define CBFS_TYPE_MBI        0x52
-#define CBFS_TYPE_MICROCODE  0x53
-#define CBFS_TYPE_FSP        0x60
-#define CBFS_TYPE_MRC        0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD          0xab
-#define CBFS_TYPE_MRC_CACHE    0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
-	uint32_t magic;
-	uint32_t version;
-	uint32_t romsize;
-	uint32_t bootblocksize;
-	uint32_t align; /* fixed to 64 bytes */
-	uint32_t offset;
-	uint32_t architecture;
-	uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARM      0x00000010
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	uint32_t len;
-	uint32_t type;
-	uint32_t checksum;
-	uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	uint32_t compression;  /** Compression type */
-	uint64_t entry;  /** entry point */
-	uint64_t load;   /** Where to load in memory */
-	uint32_t len;          /** length of data to load */
-	uint32_t memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	uint32_t type;
-	uint32_t compression;
-	uint32_t offset;
-	uint64_t load_addr;
-	uint32_t len;
-	uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	uint32_t compression;
-	uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
 #include <rules.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <rules.h>
 #include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef __ROMCC__
 struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
 
 #include <console/console.h>
 #include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* While in romstage, console loglevel is built-time constant.
  * With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
 #ifndef _FMAP_H_
 #define _FMAP_H_
 
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
 
 /* Locate the fmap directory. Return 0 on success, < 0 on error. */
 int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *    * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE		"__FMAP__"
-#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
-#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
-#define FMAP_STRLEN		32	/* maximum length for strings, */
-					/* including null-terminator */
-
-enum fmap_flags {
-	FMAP_AREA_STATIC	= 1 << 0,
-	FMAP_AREA_COMPRESSED	= 1 << 1,
-	FMAP_AREA_RO		= 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
-	uint32_t offset;                /* offset relative to base */
-	uint32_t size;                  /* size in bytes */
-	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
-	uint16_t flags;                 /* flags for this area */
-}  __attribute__((packed));
-
-struct fmap {
-	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
-	uint8_t  ver_major;		/* major version */
-	uint8_t  ver_minor;		/* minor version */
-	uint64_t base;			/* address of the firmware binary */
-	uint32_t size;			/* size of firmware binary in bytes */
-	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
-	uint16_t nareas;		/* number of areas described by
-					   fmap_areas[] below */
-	struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
 
 enum {
 	RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <commonlib/helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
 
 #include <stddef.h>
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a)           ALIGN((x),(a))
-#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-
 #define min(a,b) MIN((a),(b))
 #define max(a,b) MAX((a),(b))
 
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
 #ifndef __TIMESTAMP_H__
 #define __TIMESTAMP_H__
 
-#include <stdint.h>
-
-struct timestamp_entry {
-	uint32_t	entry_id;
-	uint64_t	entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
-	uint64_t	base_time;
-	uint16_t	max_entries;
-	uint16_t	tick_freq_mhz;
-	uint32_t	num_entries;
-	struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
-	TS_START_ROMSTAGE = 1,
-	TS_BEFORE_INITRAM = 2,
-	TS_AFTER_INITRAM = 3,
-	TS_END_ROMSTAGE = 4,
-	TS_START_VBOOT = 5,
-	TS_END_VBOOT = 6,
-	TS_START_COPYRAM = 8,
-	TS_END_COPYRAM = 9,
-	TS_START_RAMSTAGE = 10,
-	TS_START_BOOTBLOCK = 11,
-	TS_END_BOOTBLOCK = 12,
-	TS_START_COPYROM = 13,
-	TS_END_COPYROM = 14,
-	TS_START_ULZMA = 15,
-	TS_END_ULZMA = 16,
-	TS_DEVICE_ENUMERATE = 30,
-	TS_DEVICE_CONFIGURE = 40,
-	TS_DEVICE_ENABLE = 50,
-	TS_DEVICE_INITIALIZE = 60,
-	TS_DEVICE_DONE = 70,
-	TS_CBMEM_POST = 75,
-	TS_WRITE_TABLES = 80,
-	TS_LOAD_PAYLOAD = 90,
-	TS_ACPI_WAKE_JUMP = 98,
-	TS_SELFBOOT_JUMP = 99,
-
-	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
-	TS_START_COPYVER = 501,
-	TS_END_COPYVER = 502,
-	TS_START_TPMINIT = 503,
-	TS_END_TPMINIT = 504,
-	TS_START_VERIFY_SLOT = 505,
-	TS_END_VERIFY_SLOT = 506,
-	TS_START_HASH_BODY = 507,
-	TS_DONE_LOADING = 508,
-	TS_DONE_HASHING = 509,
-	TS_END_HASH_BODY = 510,
-
-	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
-	TS_FSP_MEMORY_INIT_START = 950,
-	TS_FSP_MEMORY_INIT_END = 951,
-	TS_FSP_TEMP_RAM_EXIT_START = 952,
-	TS_FSP_TEMP_RAM_EXIT_END = 953,
-	TS_FSP_SILICON_INIT_START = 954,
-	TS_FSP_SILICON_INIT_END = 955,
-	TS_FSP_BEFORE_ENUMERATE = 956,
-	TS_FSP_AFTER_ENUMERATE = 957,
-	TS_FSP_BEFORE_FINALIZE = 958,
-	TS_FSP_AFTER_FINALIZE = 959,
-
-	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
 
 #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
 /*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* This function is marked as weak to allow a particular platform to
  * override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
 #include <stddef.h>
 #include <string.h>
 
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
 #include <spd.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <commonlib/region.h>
 #include <console/console.h>
 #include <device/i2c.h>
 #include <drivers/maxim/max77802/max77802.h>
 #include <program_loading.h>
-#include <region.h>
 #include <soc/clk.h>
 #include <soc/cpu.h>
 #include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
 #define ME_DELAY		10	/* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
 
 #include <cpu/amd/common/cbtypes.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #ifdef NULL
 #undef NULL
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
 #include "sb_cimx.h"
 #include "sb700_cfg.h"                /*sb700_cimx_config*/
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
 #include "SbPlatform.h"
 #include "sb_cimx.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
 #include "amdlib.h"
 #include "cbfs.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 // TODO Add a kconfig option to name the AGESA ROM file in CBFS
 #define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
 #include <assert.h>
 #include <config.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
 #define VBOOT_COMMON_H
 
 #include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* The FW areas consist of multiple components. At the beginning of
  * each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
 
 /*
  * Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
 #include <sys/mman.h>
 #include <libgen.h>
 #include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
 
 #ifdef __OpenBSD__
 #include <sys/param.h>
@@ -42,18 +45,12 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
 
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
-#include "timestamp.h"
-
 #define CBMEM_VERSION "1.1"
 
 /* verbose output? */


From gerrit at coreboot.org  Fri Sep 11 10:18:07 2015
From: gerrit at coreboot.org (Gerd Hoffmann (kraxel@redhat.com))
Date: Fri, 11 Sep 2015 10:18:07 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: qemu: initialize
	lapic
References: <I022f3742475d3f3477fc838b1e2bce69287b6b8e+0@gerrit.coreboot.org>
Message-ID: <I022f3742475d3f3477fc838b1e2bce69287b6b8e+2@gerrit.coreboot.org>

Gerd Hoffmann (kraxel at redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11611

-gerrit

commit c403665b070878ff23ad200179f3323f73da5c83
Author: Gerd Hoffmann <kraxel at redhat.com>
Date:   Thu Sep 10 10:58:52 2015 +0200

    qemu: initialize lapic
    
    Recently qemu stopped doing a basic lapic setup and expects the
    firmware to handle this properly (like on real hardware).  So
    let's do that so coreboot works properly on qemu 2.4+.
    
    Here is the qemu commit message for the change:
    
    <quote>
      commit b8eb5512fd8a115f164edbbe897cdf8884920ccb
      Author: Nadav Amit <namit at cs.technion.ac.il>
      Date:   Mon Apr 13 02:32:08 2015 +0300
    
      target-i386: disable LINT0 after reset
    
      Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone
      and therefore this hack is no longer needed.  Since it violates the
      specifications, it is removed.
    
      Signed-off-by: Nadav Amit <namit at cs.technion.ac.il>
      Message-Id: <1428881529-29459-2-git-send-email-namit at cs.technion.ac.il>
      Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
    </quote>
    
    Change-Id: I022f3742475d3f3477fc838b1e2bce69287b6b8e
    Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
 src/cpu/qemu-x86/qemu.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c
index 4704bb8..b6f0ad5 100644
--- a/src/cpu/qemu-x86/qemu.c
+++ b/src/cpu/qemu-x86/qemu.c
@@ -18,8 +18,15 @@
 
 #include <cpu/cpu.h>
 #include <device/device.h>
+#include <cpu/x86/lapic.h>
+
+static void qemu_cpu_init(struct device *dev)
+{
+	setup_lapic();
+}
 
 static struct device_operations cpu_dev_ops = {
+	.init = qemu_cpu_init,
 };
 
 static struct cpu_device_id cpu_table[] = {


From gerrit at coreboot.org  Fri Sep 11 11:52:20 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 11 Sep 2015 11:52:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Move final Intel
	chipsets with ME to intel/common/firmware
References: <Id3bec6dbe2e1a8a90f51d9378150dbb44258b596+0@gerrit.coreboot.org>
Message-ID: <Id3bec6dbe2e1a8a90f51d9378150dbb44258b596+3@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10876

-gerrit

commit 155c6477134f7577bf97cc9583a8d44c5ed474c9
Author: Martin Roth <gaumless at gmail.com>
Date:   Thu Jul 9 21:02:26 2015 -0600

    Move final Intel chipsets with ME to intel/common/firmware
    
    This switches the final 4 Intel platforms that use ME firmware from
    using code specific to the platform to the common IFD Kconfig and
    Makefile.
    
    braswell, broadwell, bd82x6x(cougar point & panther point) and ibexpeak
    
    Change-Id: Id3bec6dbe2e1a8a90f51d9378150dbb44258b596
    Signed-off-by: Martin Roth <gaumless at gmail.com>
---
 src/soc/intel/braswell/Kconfig              | 68 ++--------------------
 src/soc/intel/braswell/Makefile.inc         | 51 +----------------
 src/soc/intel/broadwell/Kconfig             | 69 +---------------------
 src/soc/intel/broadwell/Makefile.inc        | 46 +--------------
 src/southbridge/intel/bd82x6x/Kconfig       | 88 +----------------------------
 src/southbridge/intel/bd82x6x/Makefile.inc  | 53 +----------------
 src/southbridge/intel/ibexpeak/Kconfig      | 63 +--------------------
 src/southbridge/intel/ibexpeak/Makefile.inc | 51 +----------------
 8 files changed, 16 insertions(+), 473 deletions(-)

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index ab99a08..043dc1a 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
 	select USE_GENERIC_FSP_CAR_INC
+	select HAVE_INTEL_FIRMWARE
 
 config BOOTBLOCK_CPU_INIT
 	string
@@ -116,19 +117,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
 	  the system will reset otherwise the ramstage will be reloaded from
 	  cbfs.
 
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
-
 config ENABLE_BUILTIN_COM1
 	bool "Enable builtin COM1 Serial Port"
 	default n
@@ -138,66 +126,18 @@ config ENABLE_BUILTIN_COM1
 	  the debug console.
 
 config HAVE_IFD_BIN
-	bool
-	default y
+	def_bool y
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-		   was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+	def_bool !HAVE_IFD_BIN
 
 config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
+	def_bool y
 
 config IED_REGION_SIZE
 	hex
 	default 0x400000
 
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
-
 config CHIPSET_BOOTBLOCK_INCLUDE
 	string
 	default "soc/intel/braswell/bootblock/timestamp.inc"
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index fae97b8..eda9f76 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../southbridge/intel/common/firmware
 
 romstage-y += gpio_support.c
 romstage-y += iosf.c
@@ -56,54 +57,4 @@ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE := pch_add_me
-
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	printf "CONFIG_IFD_BIN_PATH: $(CONFIG_IFD_BIN_PATH)\n"
-	printf "IFD_BIN_PATH: $(IFD_BIN_PATH)\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-	printf "CONFIG_HAVE_ME_BIN: $(CONFIG_HAVE_ME_BIN)\n"
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	printf "CONFIG_ME_BIN_PATH: $(CONFIG_ME_BIN_PATH)\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += pch_add_me
-
 endif
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index c2db2a1..e01d559 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
 	select SOC_INTEL_COMMON
+	select HAVE_INTEL_FIRMWARE
 
 config BOOTBLOCK_CPU_INIT
 	string
@@ -203,74 +204,10 @@ config REFCODE_BLOB_FILE
 endif # HAVE_REFCODE_BLOB
 
 config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
-
-config HAVE_IFD_BIN
-	bool "Use Intel Firmware Descriptor from existing binary"
-	default n
+	def_bool y
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-		   was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
+	def_bool !HAVE_IFD_BIN
 
 config CHIPSET_BOOTBLOCK_INCLUDE
 	string
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index ca295fc..183c40f 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += acpi.c
 ramstage-y += adsp.c
@@ -75,51 +76,6 @@ endif
 
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE := broadwell_add_me
-
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-broadwell_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-endif
-
-PHONY += broadwell_add_me
-
 # If an MRC file is an ELF file determine the entry address and first loadable
 # section offset in the file. Subtract the offset from the entry address to
 # determine the final location.
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 3a68fec..9bdeefa 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -38,6 +38,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select SPI_FLASH
 	select COMMON_FADT
 	select ACPI_SATA_GENERATOR
+	select HAVE_INTEL_FIRMWARE
 
 config EHCI_BAR
 	hex
@@ -63,93 +64,10 @@ config HPET_MIN_TICKS
 	default 0x80
 
 config HAVE_IFD_BIN
-	bool
-	default y
+	def_bool y
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-	           was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_GBE_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config HAVE_GBE_BIN
-	bool "Add gigabit ethernet firmware"
-	default n
-	help
-	  The integrated gigabit ethernet controller needs a firmware file.
-	  Select this if you are going to use the PCH integrated controller
-	  and have the firmware.
-
-config GBE_BIN_PATH
-	string "Path to gigabit ethernet firmware"
-	depends on HAVE_GBE_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
-
-config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
-
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	depends on !BUILD_WITH_FAKE_IFD
-	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
+	def_bool !HAVE_IFD_BIN
 
 endif
 
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index a7b509c..9214450 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -19,10 +19,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE+=bd82x6x_add_me
+subdirs-y += ../common/firmware
 
 ramstage-y += pch.c
 ramstage-y += azalia.c
@@ -62,52 +59,4 @@ romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early
 
 ramstage-y += madt.c
 
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-ifeq ($(CONFIG_HAVE_GBE_BIN),y)
-	printf "    IFDTOOL    gbe.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i GbE:$(CONFIG_GBE_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += bd82x6x_add_me
-
 endif
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index f31f83c..a2c5153 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -36,6 +36,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select HAVE_USBDEBUG_OPTIONS
 	select COMMON_FADT
 	select ACPI_SATA_GENERATOR
+	select HAVE_INTEL_FIRMWARE
 
 config EHCI_BAR
 	hex
@@ -57,70 +58,10 @@ config SERIRQ_CONTINUOUS_MODE
 	  operated in continuous mode.
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-	           was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-
-config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default n
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
+	def_bool !HAVE_IFD_BIN
 
 config HPET_MIN_TICKS
 	hex
 	default 0x80
 
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
-
 endif
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 06c5853..57c498d 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -19,10 +19,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE+=bd82x6x_add_me
+subdirs-y += ../common/firmware
 
 ramstage-y += ../bd82x6x/pch.c
 ramstage-y += azalia.c
@@ -57,50 +54,4 @@ romstage-y += ../bd82x6x/early_rcba.c
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c
 
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built without Management Engine firmware.\n"
-	printf "Never write a complete coreboot.rom without ME to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-endif
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += bd82x6x_add_me
-
 endif


From gerrit at coreboot.org  Fri Sep 11 11:52:21 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 11 Sep 2015 11:52:21 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: ifdfake: allow
	"base+size" description of regions
References: <Iecf8250e84d6eb267711ded446909b21147f1a9c+0@gerrit.coreboot.org>
Message-ID: <Iecf8250e84d6eb267711ded446909b21147f1a9c+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11623

-gerrit

commit 6dd36c65f77e428c9641cdf76b080f644fc8325f
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 13:48:24 2015 +0200

    ifdfake: allow "base+size" description of regions
    
    This is more in line with how fmd/fmap specify ranges.
    
    Change-Id: Iecf8250e84d6eb267711ded446909b21147f1a9c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/ifdfake/ifdfake.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/util/ifdfake/ifdfake.c b/util/ifdfake/ifdfake.c
index b70b6ae..7b268df 100644
--- a/util/ifdfake/ifdfake.c
+++ b/util/ifdfake/ifdfake.c
@@ -91,24 +91,39 @@ static void write_image(const region_t regions[], const char *const image)
 static int parse_region(const char *_arg, region_t *const region)
 {
 	char *const start = strdup(_arg);
+	int size_spec = 0;
+	unsigned long first, second;
 	if (!start) {
 		fprintf(stderr, "Out of memory.\n");
 		exit(EXIT_FAILURE);
 	}
 
-	char *const colon = strchr(start, ':');
+	char *colon = strchr(start, ':');
 	if (!colon) {
-		free(start);
-		return -1;
+		colon = strchr(start, '+');
+		if (!colon) {
+			free(start);
+			return -1;
+		}
+		size_spec = 1;
 	}
 	*colon = '\0';
 
 	char *const end = colon + 1;
 
 	errno = 0;
-	region->base = strtoul(start, NULL, 0);
-	region->limit = strtoul(end, NULL, 0);
-	region->size = region->limit - region->base + 1;
+	first = strtoul(start, NULL, 0);
+	second = strtoul(end, NULL, 0);
+
+	if (size_spec) {
+		region->base = first;
+		region->size = second;
+		region->limit = region->base + region->size - 1;
+	} else {
+		region->base = first;
+		region->limit = second;
+		region->size = region->limit - region->base + 1;
+	}
 
 	free(start);
 	if (errno) {


From gerrit at coreboot.org  Fri Sep 11 13:16:08 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Fri, 11 Sep 2015 13:16:08 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: pi/Makefile:
	Remove cp option '-u'
References: <I60cf57991275db0e075278f77a95ca5b8b941c7f+0@gerrit.coreboot.org>
Message-ID: <I60cf57991275db0e075278f77a95ca5b8b941c7f+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11601

-gerrit

commit 2b6d19b85eee7d2b1d764709103387a9183e9638
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 11 09:11:49 2015 -0400

    pi/Makefile: Remove cp option '-u'
    
    "-u" is only for GNU cp. Cp of BSD and Solaris don't
    take this option.
    
    It is not necessary to compare the files before copying.
    
    Change-Id: I60cf57991275db0e075278f77a95ca5b8b941c7f
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/vendorcode/amd/pi/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..b95fc5c 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -83,7 +83,7 @@ define create_agesa_cp_template
 $(agesa_src_path)/$(notdir $2): $2 $(agesa_src_path)
 	@printf "    AGESA      Copying $$(notdir $2) => $$(@D)\n"
 	if [ ! -r $(agesa_src_path)/$(notdir $2) ]; then                   \
-		cp -uf $2 $$(@D);                                                     \
+		cp -f $2 $$(@D);                                           \
 	fi
 
 $(agesa_obj_path)/$1.libagesa.o: $(agesa_src_path)/$(notdir $2) $(obj)/config.h $(src)/include/kconfig.h $(agesa_obj_path)


From gerrit at coreboot.org  Fri Sep 11 13:16:10 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Fri, 11 Sep 2015 13:16:10 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Makefile: Replace
	the way to test if a string is empty
References: <Ie4b8fe1fb26df092e2985937251a49feadc61eb0+0@gerrit.coreboot.org>
Message-ID: <Ie4b8fe1fb26df092e2985937251a49feadc61eb0+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11600

-gerrit

commit df9dc6bfcc5be4ff373969bec9922c5184f6327c
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 11 08:49:38 2015 -0400

    Makefile: Replace the way to test if a string is empty
    
    The output of command below,
    # i386-elf-nm build/cbfs/fallback/romstage_null.offenders | \
                         grep -q "" ; echo $?
    has different result on MacOS, OS X Mavericks, which outputs 0.
    On linux, it outputs 1.
    
    I assume it is misleading to search an empty string in a empty
    string. Change it to testing if the string is empty.
    
    Change-Id: Ie4b8fe1fb26df092e2985937251a49feadc61eb0
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/arch/x86/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 68ed810..8bef5e6 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -183,7 +183,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
-	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
+	if [ -n "`$(NM_romstage) $(objcbfs)/romstage_null.offenders 2>/dev/null`" ]; then \
 		echo "Forbidden global variables in romstage:"; \
 		$(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \
 		else true; fi


From gerrit at coreboot.org  Fri Sep 11 13:16:11 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Fri, 11 Sep 2015 13:16:11 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: .gitignore: adapt
	to new buildgcc version
References: <I6c752f08aa545d8878fddd373e5acbfade317ad5+0@gerrit.coreboot.org>
Message-ID: <I6c752f08aa545d8878fddd373e5acbfade317ad5+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11602

-gerrit

commit 87876d5479fd0a971d0808b72d2982cfb01de680
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 11 09:15:40 2015 -0400

    .gitignore: adapt to new buildgcc version
    
    1. The build folders are capitalized.
    2. Add folders for build LLVM and IASL.
    
    Change-Id: I6c752f08aa545d8878fddd373e5acbfade317ad5
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 .gitignore | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/.gitignore b/.gitignore
index 770a62d..4eaf426 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,15 +10,17 @@ payloads/external/GRUB2/grub2/
 payloads/external/SeaBIOS/seabios/
 util/crossgcc/acpica-unix-*/
 util/crossgcc/binutils-*/
-util/crossgcc/build-*binutils/
-util/crossgcc/build-*expat/
-util/crossgcc/build-*gcc/
-util/crossgcc/build-*gdb/
-util/crossgcc/build-*gmp/
-util/crossgcc/build-*libelf/
-util/crossgcc/build-*mpc/
-util/crossgcc/build-*mpfr/
-util/crossgcc/build-*python/
+util/crossgcc/build-*BINUTILS/
+util/crossgcc/build-*EXPAT/
+util/crossgcc/build-*GCC/
+util/crossgcc/build-*GDB/
+util/crossgcc/build-*GMP/
+util/crossgcc/build-*LIBELF/
+util/crossgcc/build-*MPC/
+util/crossgcc/build-*MPFR/
+util/crossgcc/build-*PYTHON/
+util/crossgcc/build-*LVM/
+util/crossgcc/build-*IASL/
 util/crossgcc/expat-*/
 util/crossgcc/gcc-*/
 util/crossgcc/gdb-*/
@@ -28,6 +30,7 @@ util/crossgcc/mingwrt-*/
 util/crossgcc/mpc-*/
 util/crossgcc/mpfr-*/
 util/crossgcc/Python-*/
+util/crossgcc/*.src/
 util/crossgcc/tarballs/
 util/crossgcc/w32api-*/
 util/crossgcc/xgcc/


From gerrit at coreboot.org  Fri Sep 11 15:34:19 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 15:34:19 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: coreboot: add
	rdevbs (region device byte stream)
References: <I60feb24ae1b2abadb23b23201f38c85ade5bcfbd+0@gerrit.coreboot.org>
Message-ID: <I60feb24ae1b2abadb23b23201f38c85ade5bcfbd+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11624

-gerrit

commit 991d8f8029b9a04414f9c03cbccf932dc3a389d0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 11 09:49:12 2015 -0500

    coreboot: add rdevbs (region device byte stream)
    
    Add a region device byte stream object, rdevbs, which
    will perform designated endian operations for reading
    serialized objects out of a region device. The cbfs
    walking code was updated to show usage of the library.
    
    The implementation uses memory region device after
    performing a mapping on the original parent. The reason
    is absorb the communication costs of dealing with a
    controller and its external media.
    
    TEST=Booted glados.
    
    Change-Id: I60feb24ae1b2abadb23b23201f38c85ade5bcfbd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/region.h | 28 ++++++++++++++++++
 src/lib/cbfs.c       | 51 +++++++++++++++++++++-----------
 src/lib/region.c     | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 144 insertions(+), 17 deletions(-)

diff --git a/src/include/region.h b/src/include/region.h
index 82db854..1c9cb6d 100644
--- a/src/include/region.h
+++ b/src/include/region.h
@@ -154,4 +154,32 @@ void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
 void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
 int mmap_helper_rdev_munmap(const struct region_device *, void *);
 
+/* Interpret region_device as byte stream operations with endian conversions. */
+struct rdevbs;
+
+enum {
+	BE_BS, /* Big Endian */
+	LE_BS, /* Little Endian */
+};
+/*
+ * Initialize an rdev byte stream from parent for reading stream_size bytes
+ * using the providded endianness interpretation. Returns 0 on success, < 0
+ * on error.
+ */
+int rdevbs_init(struct rdevbs *bs, const struct region_device *parent,
+		size_t stream_offset, size_t stream_size, int endianness);
+
+/* Return 0 on success, < 0 on error. */
+int rdevbs_read(struct rdevbs *bs, void *dest, size_t size);
+
+/* Indicate that the bytream is complete and any resources can be freed. */
+void rdevbs_complete(struct rdevbs *bs);
+
+struct rdevbs {
+	const struct region_device *parent;
+	struct mem_region_device memdev;
+	size_t current_offset;
+	int endianness;
+};
+
 #endif /* _REGION_H_ */
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index abc4077..4075b7f 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -90,30 +90,47 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 	/* Try to scan the entire cbfs region looking for file name. */
 	while (1) {
-		struct cbfs_file file;
-		const size_t fsz = sizeof(file);
+		uint8_t magic[8];
+		uint32_t flen;
+		uint32_t ftype;
+		uint32_t fchecksum;
+		uint32_t foffset;
+		const size_t fsz = sizeof(struct cbfs_file);
 		char *fname;
 		int name_match;
 		size_t datasz;
+		struct rdevbs bs;
+		size_t i;
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		/* Can't read file. Nothing else to do but bail out. */
-		if (rdev_readat(rd, &file, offset, fsz) != fsz)
+		if (rdevbs_init(&bs, rd, offset, fsz, BE_BS))
 			break;
 
-		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
+		/* Joy. magic is a byte array w/o an endian encoding. */
+		for (i = 0; i < sizeof(magic); i++)
+			if (rdevbs_read(&bs, &magic[i], sizeof(magic[i])))
+				break;
+
+		if (rdevbs_read(&bs, &flen, sizeof(flen)))
+			break;
+		if (rdevbs_read(&bs, &ftype, sizeof(ftype)))
+			break;
+		if (rdevbs_read(&bs, &fchecksum, sizeof(fchecksum)))
+			break;
+		if (rdevbs_read(&bs, &foffset, sizeof(foffset)))
+			break;
+
+		rdevbs_complete(&bs);
+
+		if (memcmp(magic, CBFS_FILE_MAGIC, sizeof(magic))) {
 			offset++;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		file.len = ntohl(file.len);
-		file.type = ntohl(file.type);
-		file.offset = ntohl(file.offset);
-
 		/* See if names match. */
-		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
+		fname = rdev_mmap(rd, offset + fsz, foffset - fsz);
 
 		if (fname == NULL)
 			break;
@@ -123,23 +140,23 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 		if (!name_match) {
 			DEBUG(" Unmatched '%s' at %zx\n", fname, offset);
-			offset += file.offset + file.len;
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		if (type != NULL && *type != file.type) {
-			DEBUG(" Unmatched type %x at %zx\n", file.type, offset);
-			offset += file.offset + file.len;
+		if (type != NULL && *type != ftype) {
+			DEBUG(" Unmatched type %x at %zx\n", ftype, offset);
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		LOG("Found @ offset %zx size %x\n", offset, file.len);
+		LOG("Found @ offset %zx size %x\n", offset, flen);
 		/* File and type match. Create a chained region_device to
 		 * represent the cbfs file. */
-		offset += file.offset;
-		datasz = file.len;
+		offset += foffset;
+		datasz = flen;
 		if (rdev_chain(fh, rd, offset, datasz))
 			break;
 
diff --git a/src/lib/region.c b/src/lib/region.c
index d5d3762..4dd4adc 100644
--- a/src/lib/region.c
+++ b/src/lib/region.c
@@ -17,6 +17,7 @@
  * Foundation, Inc.
  */
 
+#include <endian.h>
 #include <region.h>
 #include <string.h>
 
@@ -194,3 +195,84 @@ int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
 
 	return 0;
 }
+
+int rdevbs_init(struct rdevbs *bs, const struct region_device *parent,
+		size_t stream_offset, size_t stream_size, int endianness)
+{
+	void *mapping;
+
+	bs->parent = parent;
+	bs->current_offset = 0;
+	bs->endianness = endianness;
+	if (endianness != LE_BS && endianness != BE_BS)
+		return -1;
+
+	/*
+	 * One needs the object storage in order to read from the stream
+	 * efficiently. Otherwise there would be many small round trip
+	 * operations to the backing controller. Instead use a mapping of
+	 * the size to be consumed.
+	 */
+	mapping = rdev_mmap(parent, stream_offset, stream_size);
+
+	if (mapping == NULL)
+		return -1;
+
+	mem_region_device_init(&bs->memdev, mapping, stream_size);
+
+	return 0;
+}
+
+int rdevbs_read(struct rdevbs *bs, void *dest, size_t size)
+{
+	union {
+		uint64_t bits64;
+		uint32_t bits32;
+		uint16_t bits16;
+		uint8_t bits8;
+	} b;
+
+	if (size != sizeof(b.bits64) && size != sizeof(b.bits32) &&
+			size != sizeof(b.bits16) && size != sizeof(b.bits8))
+		return -1;
+
+	if (rdev_readat(&bs->memdev.rdev, &b, bs->current_offset, size) != size)
+		return -1;
+
+	if (bs->endianness == LE_BS) {
+		switch (size) {
+		case sizeof(b.bits64):
+			b.bits64 = le64toh(b.bits64);
+			break;
+		case sizeof(b.bits32):
+			b.bits32 = le32toh(b.bits32);
+			break;
+		case sizeof(b.bits16):
+			b.bits16 = le16toh(b.bits16);
+			break;
+		}
+	} else {
+		switch (size) {
+		case sizeof(b.bits64):
+			b.bits64 = be64toh(b.bits64);
+			break;
+		case sizeof(b.bits32):
+			b.bits32 = be32toh(b.bits32);
+			break;
+		case sizeof(b.bits16):
+			b.bits16 = be16toh(b.bits16);
+			break;
+		}
+	}
+
+	memcpy(dest, &b, size);
+	bs->current_offset += size;
+
+	return 0;
+}
+
+void rdevbs_complete(struct rdevbs *bs)
+{
+	rdev_munmap(bs->parent, bs->memdev.base);
+	bs->parent = NULL;
+}


From gerrit at coreboot.org  Fri Sep 11 16:34:53 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 11 Sep 2015 16:34:53 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: corebot: add
	bytestream helpfer functions
References: <I59a44704e9bff9bf11e779970ad4667e2e6b2bdd+0@gerrit.coreboot.org>
Message-ID: <I59a44704e9bff9bf11e779970ad4667e2e6b2bdd+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11625

-gerrit

commit 78cbc9ed83bc9e9c3fc18cde32c6ba57cac19892
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 11 11:26:37 2015 -0500

    corebot: add bytestream helpfer functions
    
    Allow one to operate on a buffer to interpret values
    based on an endianness encoding. The cbfs walking code
    was update to use the API. It requires one to open code
    the tracking field offset and sizes while also not providing
    any bounds checking.
    
    TEST=Built and booted on glados.
    
    Change-Id: I59a44704e9bff9bf11e779970ad4667e2e6b2bdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bytestream.h | 83 ++++++++++++++++++++++++++++++++++++++++++++++++
 src/lib/cbfs.c           | 51 +++++++++++++++++++----------
 2 files changed, 117 insertions(+), 17 deletions(-)

diff --git a/src/include/bytestream.h b/src/include/bytestream.h
new file mode 100644
index 0000000..9f19107
--- /dev/null
+++ b/src/include/bytestream.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _BYTESTREAM_H_
+#define _BYTESTREAM_H_
+
+#include <endian.h>
+#include <stdint.h>
+#include <string.h>
+
+static inline uint64_t read_be64(void *src, size_t offset)
+{
+	uint64_t val;
+	memcpy(&val, offset + (uint8_t *)src, sizeof(val));
+	return be64toh(val);
+}
+
+static inline uint32_t read_be32(void *src, size_t offset)
+{
+	uint32_t val;
+	memcpy(&val, offset + (uint8_t *)src, sizeof(val));
+	return be32toh(val);
+}
+
+static inline uint16_t read_be16(void *src, size_t offset)
+{
+	uint16_t val;
+	memcpy(&val, offset + (uint8_t *)src, sizeof(val));
+	return be16toh(val);
+}
+
+static inline uint8_t read_be8(void *src, size_t offset)
+{
+	uint8_t val;
+	memcpy(&val, offset + (uint8_t *)src, sizeof(val));
+	return val;
+}
+
+static inline uint64_t read_le64(void *src, size_t offset)
+{
+	uint64_t val;
+	memcpy(&val, offset + (uint8_t *)src, sizeof(val));
+	return le64toh(val);
+}
+
+static inline uint32_t read_le32(void *src, size_t offset)
+{
+	uint32_t val;
+	memcpy(&val, offset + (uint8_t *)src, sizeof(val));
+	return le32toh(val);
+}
+
+static inline uint16_t read_le16(void *src, size_t offset)
+{
+	uint16_t val;
+	memcpy(&val, offset + (uint8_t *)src, sizeof(val));
+	return le16toh(val);
+}
+
+static inline uint8_t read_le8(void *src, size_t offset)
+{
+	uint8_t val;
+	memcpy(&val, offset + (uint8_t *)src, sizeof(val));
+	return val;
+}
+
+#endif
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index abc4077..83cd247 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <stdlib.h>
 #include <boot_device.h>
+#include <bytestream.h>
 #include <cbfs.h>
 #include <endian.h>
 #include <lib.h>
@@ -90,30 +91,46 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 	/* Try to scan the entire cbfs region looking for file name. */
 	while (1) {
-		struct cbfs_file file;
-		const size_t fsz = sizeof(file);
+		uint8_t magic[8];
+		uint32_t flen;
+		uint32_t ftype;
+		uint32_t foffset;
+		size_t strmoff;
+		const size_t fsz = sizeof(struct cbfs_file);
+		void *file_mapping;
 		char *fname;
 		int name_match;
 		size_t datasz;
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		/* Can't read file. Nothing else to do but bail out. */
-		if (rdev_readat(rd, &file, offset, fsz) != fsz)
+		file_mapping = rdev_mmap(rd, offset, fsz);
+
+		if (file_mapping == NULL)
 			break;
 
-		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
+		/* Magic is a byte string w/ no endian encoding. */
+		memcpy(magic, file_mapping, sizeof(magic));
+		strmoff = sizeof(magic);
+
+		flen = read_be32(file_mapping, strmoff);
+		strmoff += sizeof(flen);
+		ftype = read_be32(file_mapping, strmoff);
+		strmoff += sizeof(ftype);
+		/* Skip the checksum field. */
+		strmoff += sizeof(ftype);
+		foffset = read_be32(file_mapping, strmoff);
+
+		rdev_munmap(rd, file_mapping);
+
+		if (memcmp(magic, CBFS_FILE_MAGIC, sizeof(magic))) {
 			offset++;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		file.len = ntohl(file.len);
-		file.type = ntohl(file.type);
-		file.offset = ntohl(file.offset);
-
 		/* See if names match. */
-		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
+		fname = rdev_mmap(rd, offset + fsz, foffset - fsz);
 
 		if (fname == NULL)
 			break;
@@ -123,23 +140,23 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 		if (!name_match) {
 			DEBUG(" Unmatched '%s' at %zx\n", fname, offset);
-			offset += file.offset + file.len;
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		if (type != NULL && *type != file.type) {
-			DEBUG(" Unmatched type %x at %zx\n", file.type, offset);
-			offset += file.offset + file.len;
+		if (type != NULL && *type != ftype) {
+			DEBUG(" Unmatched type %x at %zx\n", ftype, offset);
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		LOG("Found @ offset %zx size %x\n", offset, file.len);
+		LOG("Found @ offset %zx size %x\n", offset, flen);
 		/* File and type match. Create a chained region_device to
 		 * represent the cbfs file. */
-		offset += file.offset;
-		datasz = file.len;
+		offset += foffset;
+		datasz = flen;
 		if (rdev_chain(fh, rd, offset, datasz))
 			break;
 


From gerrit at coreboot.org  Fri Sep 11 16:42:20 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 11 Sep 2015 16:42:20 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: drop
	extra copy of filetype->string map
References: <I08e478b92f3316139f14294e50ede657c7d5fb01+0@gerrit.coreboot.org>
Message-ID: <I08e478b92f3316139f14294e50ede657c7d5fb01+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11626

-gerrit

commit c02a13b4f90f5545a8c58921d503ffdf201f8d9d
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 9 16:46:00 2015 +0200

    cbfstool: drop extra copy of filetype->string map
    
    We had two mappings of filetype IDs to strings. We shouldn't.
    
    Change-Id: I08e478b92f3316139f14294e50ede657c7d5fb01
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfs.h       | 24 ++++++++++++++++++++++++
 util/cbfstool/cbfs_image.c | 27 +--------------------------
 util/cbfstool/common.c     | 24 +-----------------------
 3 files changed, 26 insertions(+), 49 deletions(-)

diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index f738c60..70f806b 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -175,6 +175,30 @@ struct cbfs_payload {
  */
 #define CBFS_COMPONENT_NULL 0xFFFFFFFF
 
+struct typedesc_t {
+	uint32_t type;
+	const char *name;
+};
+
+static struct typedesc_t filetypes[] unused = {
+	{CBFS_COMPONENT_STAGE, "stage"},
+	{CBFS_COMPONENT_PAYLOAD, "payload"},
+	{CBFS_COMPONENT_OPTIONROM, "optionrom"},
+	{CBFS_COMPONENT_BOOTSPLASH, "bootsplash"},
+	{CBFS_COMPONENT_RAW, "raw"},
+	{CBFS_COMPONENT_VSA, "vsa"},
+	{CBFS_COMPONENT_MBI, "mbi"},
+	{CBFS_COMPONENT_MICROCODE, "microcode"},
+	{CBFS_COMPONENT_FSP, "fsp"},
+	{CBFS_COMPONENT_MRC, "mrc"},
+	{CBFS_COMPONENT_CMOS_DEFAULT, "cmos_default"},
+	{CBFS_COMPONENT_CMOS_LAYOUT, "cmos_layout"},
+	{CBFS_COMPONENT_SPD, "spd"},
+	{CBFS_COMPONENT_MRC_CACHE, "mrc_cache"},
+	{CBFS_COMPONENT_DELETED, "deleted"},
+	{CBFS_COMPONENT_NULL, "null"}
+};
+
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
 
 /* cbfs_image.c */
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index c40bd66..c2f0b37 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -52,31 +52,6 @@
 
 /* Type and format */
 
-struct typedesc_t {
-	uint32_t type;
-	const char *name;
-};
-
-static const struct typedesc_t types_cbfs_entry[] = {
-	{CBFS_COMPONENT_STAGE, "stage"},
-	{CBFS_COMPONENT_PAYLOAD, "payload"},
-	{CBFS_COMPONENT_OPTIONROM, "optionrom"},
-	{CBFS_COMPONENT_BOOTSPLASH, "bootsplash"},
-	{CBFS_COMPONENT_RAW, "raw"},
-	{CBFS_COMPONENT_VSA, "vsa"},
-	{CBFS_COMPONENT_MBI, "mbi"},
-	{CBFS_COMPONENT_MICROCODE, "microcode"},
-	{CBFS_COMPONENT_FSP, "fsp"},
-	{CBFS_COMPONENT_MRC, "mrc"},
-	{CBFS_COMPONENT_CMOS_DEFAULT, "cmos_default"},
-	{CBFS_COMPONENT_CMOS_LAYOUT, "cmos_layout"},
-	{CBFS_COMPONENT_SPD, "spd"},
-	{CBFS_COMPONENT_MRC_CACHE, "mrc_cache"},
-	{CBFS_COMPONENT_DELETED, "deleted"},
-	{CBFS_COMPONENT_NULL, "null"},
-	{0, NULL}
-};
-
 static const struct typedesc_t types_cbfs_compression[] = {
 	{CBFS_COMPRESS_NONE, "none"},
 	{CBFS_COMPRESS_LZMA, "LZMA"},
@@ -102,7 +77,7 @@ static int lookup_type_by_name(const struct typedesc_t *desc, const char *name)
 
 static const char *get_cbfs_entry_type_name(uint32_t type)
 {
-	return lookup_name_by_type(types_cbfs_entry, type, "(unknown)");
+	return lookup_name_by_type(filetypes, type, "(unknown)");
 }
 
 int cbfs_parse_comp_algo(const char *name)
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index d72db38..f8ce2f9 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -177,28 +177,6 @@ const char *arch_to_string(uint32_t a)
 	return ret;
 }
 
-static struct filetypes_t {
-	uint32_t type;
-	const char *name;
-} filetypes[] = {
-	{CBFS_COMPONENT_STAGE, "stage"},
-	{CBFS_COMPONENT_PAYLOAD, "payload"},
-	{CBFS_COMPONENT_OPTIONROM, "optionrom"},
-	{CBFS_COMPONENT_BOOTSPLASH, "bootsplash"},
-	{CBFS_COMPONENT_RAW, "raw"},
-	{CBFS_COMPONENT_VSA, "vsa"},
-	{CBFS_COMPONENT_MBI, "mbi"},
-	{CBFS_COMPONENT_MICROCODE, "microcode"},
-	{CBFS_COMPONENT_FSP, "fsp"},
-	{CBFS_COMPONENT_MRC, "mrc"},
-	{CBFS_COMPONENT_CMOS_DEFAULT, "cmos default"},
-	{CBFS_COMPONENT_CMOS_LAYOUT, "cmos layout"},
-	{CBFS_COMPONENT_SPD, "spd"},
-	{CBFS_COMPONENT_MRC_CACHE, "mrc_cache"},
-	{CBFS_COMPONENT_DELETED, "deleted"},
-	{CBFS_COMPONENT_NULL, "null"}
-};
-
 void print_supported_filetypes(void)
 {
 	int i, number = ARRAY_SIZE(filetypes);
@@ -213,7 +191,7 @@ void print_supported_filetypes(void)
 uint64_t intfiletype(const char *name)
 {
 	size_t i;
-	for (i = 0; i < (sizeof(filetypes) / sizeof(struct filetypes_t)); i++)
+	for (i = 0; i < (sizeof(filetypes) / sizeof(struct typedesc_t)); i++)
 		if (strcmp(filetypes[i].name, name) == 0)
 			return filetypes[i].type;
 	return -1;


From gerrit at coreboot.org  Fri Sep 11 16:42:22 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 11 Sep 2015 16:42:22 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	introduce new file types
References: <I1b4149c7f3b8564ee358a2c18ba91e6a7a6797da+0@gerrit.coreboot.org>
Message-ID: <I1b4149c7f3b8564ee358a2c18ba91e6a7a6797da+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11627

-gerrit

commit 1c9a628834fe1f4fdc8c8ade222d70aa6a89fb94
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 9 20:11:26 2015 +0200

    cbfstool: introduce new file types
    
    Let's move x86 style bootblocks (and later the others) and the master header
    into the CBFS structure. Prepare for this by adding file types.
    
    Change-Id: I1b4149c7f3b8564ee358a2c18ba91e6a7a6797da
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfs.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index 70f806b..579afa6 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -148,6 +148,8 @@ struct cbfs_payload {
     Users are welcome to use any other value for their
     components */
 
+#define CBFS_COMPONENT_BOOTBLOCK  0x01
+#define CBFS_COMPONENT_CBFSHEADER 0x02
 #define CBFS_COMPONENT_STAGE      0x10
 #define CBFS_COMPONENT_PAYLOAD    0x20
 #define CBFS_COMPONENT_OPTIONROM  0x30
@@ -181,6 +183,8 @@ struct typedesc_t {
 };
 
 static struct typedesc_t filetypes[] unused = {
+	{CBFS_COMPONENT_BOOTBLOCK, "bootblock"},
+	{CBFS_COMPONENT_CBFSHEADER, "cbfs header"},
 	{CBFS_COMPONENT_STAGE, "stage"},
 	{CBFS_COMPONENT_PAYLOAD, "payload"},
 	{CBFS_COMPONENT_OPTIONROM, "optionrom"},


From gerrit at coreboot.org  Fri Sep 11 16:42:24 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 11 Sep 2015 16:42:24 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: add
	new add-master-header command
References: <I5bc7fbcb5962b35a95261f30f0c93008e760680d+0@gerrit.coreboot.org>
Message-ID: <I5bc7fbcb5962b35a95261f30f0c93008e760680d+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11628

-gerrit

commit 677a6c9571fc1921aa9ea892e501bd01947715a5
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Thu Sep 10 15:28:27 2015 +0200

    cbfstool: add new add-master-header command
    
    The command adds a new cbfs file, fills in the CBFS meta data in cbfs
    master header format, then points the master header pointer (which
    resides at the last 4 bytes of the CBFS region) to the data area of the
    new file.
    
    This can leak some space in CBFS if an old-style CBFS with native master
    header gets the treatment, because a new header is created at pointed
    at. flashmap based images have no such header, and the attempt to create
    a second file with the (hardcoded) name will fail.
    
    Change-Id: I5bc7fbcb5962b35a95261f30f0c93008e760680d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfstool.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 65 insertions(+), 1 deletion(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index d6c116a..47cf876 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -168,6 +168,66 @@ done:
 	return ret;
 }
 
+static int cbfs_add_master_header(void)
+{
+	const char * const name = "cbfs master header";
+	struct cbfs_image image;
+	struct cbfs_file *header = NULL;
+	struct buffer buffer;
+	int ret = 1;
+
+	if (cbfs_image_from_buffer(&image, param.image_region,
+		param.headeroffset)) {
+		ERROR("Selected image region is not a CBFS.\n");
+		return 1;
+	}
+
+	if (cbfs_get_entry(&image, name)) {
+		ERROR("'%s' already in ROM image.\n", name);
+		return 1;
+	}
+
+	if (buffer_create(&buffer, sizeof(struct cbfs_header), name) != 0)
+		return 1;
+
+	struct cbfs_header *h = (struct cbfs_header *)buffer.data;
+	h->magic = htonl(CBFS_HEADER_MAGIC);
+	h->version = htonl(CBFS_HEADER_VERSION);
+	h->romsize = htonl(param.image_region->size);
+	h->bootblocksize = htonl(4);
+	h->align = htonl(64);
+	h->offset = htonl(param.image_region->offset);
+	h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN);
+
+	header = cbfs_create_file_header(CBFS_COMPONENT_CBFSHEADER,
+		buffer.size, name);
+	if (cbfs_add_entry(&image, &buffer, 0, header) != 0) {
+		ERROR("Failed to add cbfs master header into ROM image.\n");
+		goto done;
+	}
+
+	struct cbfs_file *entry;
+	if ((entry = cbfs_get_entry(&image, name)) == NULL) {
+		ERROR("'%s' not in ROM image?!?\n", name);
+		goto done;
+	}
+
+	uint32_t header_offset = CBFS_SUBHEADER(entry) -
+		(void *)image.buffer.data;
+	header_offset = 0xffffffff - image.buffer.size + 1 + header_offset;
+
+	// TODO: when we have a BE target, we'll need to store this as BE
+	*(uint32_t *)(image.buffer.data + image.buffer.size - 4) =
+		swab32(htonl(header_offset));
+
+	ret = 0;
+
+done:
+	free(header);
+	buffer_delete(&buffer);
+	return ret;
+}
+
 static int cbfs_add_component(const char *filename,
 			      const char *name,
 			      uint32_t type,
@@ -191,7 +251,7 @@ static int cbfs_add_component(const char *filename,
 	}
 
 	struct cbfs_image image;
-	if (cbfs_image_from_buffer(&image, param.image_region, headeroffset))
+		if (cbfs_image_from_buffer(&image, param.image_region, headeroffset))
 		return 1;
 
 	if (cbfs_get_entry(&image, name)) {
@@ -811,6 +871,8 @@ static const struct command commands[] = {
 	{"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true},
 	{"add-stage", "H:r:f:n:t:c:b:S:vh?", cbfs_add_stage, true, true},
 	{"add-int", "H:r:i:n:b:vh?", cbfs_add_integer, true, true},
+	{"add-master-header", "H:r:vh?", cbfs_add_master_header, true,
+		true},
 	{"copy", "H:D:s:h?", cbfs_copy, true, true},
 	{"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true},
 	{"extract", "H:r:n:f:vh?", cbfs_extract, true, false},
@@ -935,6 +997,8 @@ static void usage(char *name)
 			"Add a 32bit flat mode binary\n"
 	     " add-int [-r image,regions] -i INTEGER -n NAME [-b base]     "
 			"Add a raw 64-bit integer value\n"
+	     " add-master-header [-r image,regions]                        "
+			"Add a legacy CBFS master header\n"
 	     " remove [-r image,regions] -n NAME                           "
 			"Remove a component\n"
 	     " copy -D new_header_offset -s region size \\\n"


From gerrit at coreboot.org  Fri Sep 11 16:42:27 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 11 Sep 2015 16:42:27 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cfstool: prefer
	fmap data over cbfs master header if it exists
References: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+0@gerrit.coreboot.org>
Message-ID: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11629

-gerrit

commit 8220bdad9ddef0617aad8b31c15c2ccdd448ff1c
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 18:34:39 2015 +0200

    cfstool: prefer fmap data over cbfs master header if it exists
    
    Up to now, if both fmap and a master header existed, the master header
    was used. Now, use the master header only if no fmap is found.
    
    Change-Id: Iafbf2c9dc325597e23a9780b495549b5d912e9ad
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfs_image.c       | 12 +++++++-----
 util/cbfstool/cbfstool.c         |  9 +--------
 util/cbfstool/partitioned_file.c | 15 +--------------
 util/cbfstool/partitioned_file.h | 24 +++++-------------------
 4 files changed, 14 insertions(+), 46 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index c2f0b37..cdaf33b 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -343,20 +343,22 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in,
 	buffer_clone(&out->buffer, in);
 	out->has_header = false;
 
+	if (cbfs_is_valid_cbfs(out)) {
+		return 0;
+	}
+
 	void *header_loc = cbfs_find_header(in->data, in->size, offset);
 	if (header_loc) {
 		cbfs_get_header(&out->header, header_loc);
 		out->has_header = true;
 		cbfs_fix_legacy_size(out, header_loc);
+		return 0;
 	} else if (offset != ~0u) {
 		ERROR("The -H switch is only valid on legacy images having CBFS master headers.\n");
 		return 1;
-	} else if (!cbfs_is_valid_cbfs(out)) {
-		ERROR("Selected image region is not a valid CBFS.\n");
-		return 1;
 	}
-
-	return 0;
+	ERROR("Selected image region is not a valid CBFS.\n");
+	return 1;
 }
 
 int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset,
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 47cf876..d847e2c 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -858,12 +858,6 @@ static int cbfs_copy(void)
 	return cbfs_copy_instance(&image, param.copyoffset, param.size);
 }
 
-static bool cbfs_is_legacy_format(struct buffer *buffer)
-{
-	// Legacy CBFSes are those containing the deprecated CBFS master header.
-	return cbfs_find_header(buffer->data, buffer->size, -1);
-}
-
 static const struct command commands[] = {
 	{"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true},
 	{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
@@ -1227,8 +1221,7 @@ int main(int argc, char **argv)
 			}
 		} else {
 			param.image_file =
-				partitioned_file_reopen(image_name,
-							cbfs_is_legacy_format);
+				partitioned_file_reopen(image_name);
 		}
 		if (!param.image_file)
 			return 1;
diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c
index 9d67832..041ef11 100644
--- a/util/cbfstool/partitioned_file.c
+++ b/util/cbfstool/partitioned_file.c
@@ -165,8 +165,7 @@ partitioned_file_t *partitioned_file_create(const char *filename,
 	return file;
 }
 
-partitioned_file_t *partitioned_file_reopen(const char *filename,
-				partitioned_file_flat_decider_t flat_override)
+partitioned_file_t *partitioned_file_reopen(const char *filename)
 {
 	assert(filename);
 
@@ -174,11 +173,6 @@ partitioned_file_t *partitioned_file_reopen(const char *filename,
 	if (!file)
 		return NULL;
 
-	if (flat_override && flat_override(&file->buffer)) {
-		INFO("Opening image as a flat file in response to explicit request\n");
-		return file;
-	}
-
 	long fmap_region_offset = fmap_find((const uint8_t *)file->buffer.data,
 							file->buffer.size);
 	if (fmap_region_offset < 0) {
@@ -365,10 +359,3 @@ static bool select_parents_of(const struct fmap_area *parent, const void *arg)
 }
 const partitioned_file_fmap_selector_t partitioned_file_fmap_select_parents_of =
 							select_parents_of;
-
-static bool open_as_flat(unused struct buffer *buffer)
-{
-	return true;
-}
-const partitioned_file_flat_decider_t partitioned_file_open_as_flat =
-								open_as_flat;
diff --git a/util/cbfstool/partitioned_file.h b/util/cbfstool/partitioned_file.h
index 4583316..3698a19 100644
--- a/util/cbfstool/partitioned_file.h
+++ b/util/cbfstool/partitioned_file.h
@@ -28,15 +28,6 @@
 
 typedef struct partitioned_file partitioned_file_t;
 
-/** @return Whether the specific existing file should be opened in flat mode. */
-typedef bool (*partitioned_file_flat_decider_t)(struct buffer *buffer);
-
-/** Pass to partitioned_file_reopen() to force opening as a partitioned file. */
-#define partitioned_file_open_as_partitioned NULL
-
-/** Pass to partitioned_file_reopen() to force opening as a flat file. */
-extern const partitioned_file_flat_decider_t partitioned_file_open_as_flat;
-
 /**
  * Create a new filesystem-backed flat buffer.
  * This backwards-compatibility function creates a new in-memory buffer and
@@ -76,22 +67,17 @@ partitioned_file_t *partitioned_file_create(const char *filename,
 
 /**
  * Read a file back in from the disk.
- * An in-memory buffer is created and populated with the file's contents. If
- * flat_override is NULL and the image contains an FMAP, it will be opened as a
- * full partitioned file; otherwise, it will be opened as a flat file as if it
- * had been created by partitioned_file_create_flat(). This selection behavior
- * is extensible: if a flat_override function is provided, it is invoked before
- * searching for an FMAP, and has the option of explicitly instructing the
- * module to open the image as a flat file based on its contents.
+ * An in-memory buffer is created and populated with the file's
+ * contents. If the image contains an FMAP, it will be opened as a
+ * full partitioned file; otherwise, it will be opened as a flat file as
+ * if it had been created by partitioned_file_create_flat().
  * The partitioned_file_t returned from this function is separately owned by the
  * caller, and must later be passed to partitioned_file_close();
  *
  * @param filename      Name of the file to read in
- * @param flat_override Callback that can decide to open it as flat, or NULL
  * @return              Caller-owned partitioned file, or NULL on error
  */
-partitioned_file_t *partitioned_file_reopen(const char *filename,
-				partitioned_file_flat_decider_t flat_override);
+partitioned_file_t *partitioned_file_reopen(const char *filename);
 
 /**
  * Write a buffer's contents to its original region within a segmented file.


From gerrit at coreboot.org  Fri Sep 11 16:42:30 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 11 Sep 2015 16:42:30 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Kconfig: Add
	ROM_START variable
References: <Icc747eccf4263875f15806fcb38ec29e4665cf11+0@gerrit.coreboot.org>
Message-ID: <Icc747eccf4263875f15806fcb38ec29e4665cf11+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11630

-gerrit

commit d9d74288a575d06b993b41e035f5e67aa9e858d2
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 15:29:42 2015 +0200

    Kconfig: Add ROM_START variable
    
    It's automatically derived from ROM_SIZE and specifies the offset of
    flash in memory. On non-x86 that's 0, on x86 it's 4GB-ROM_SIZE.
    
    Change-Id: Icc747eccf4263875f15806fcb38ec29e4665cf11
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/mainboard/Kconfig | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index ab8ee26..3098803 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -128,6 +128,20 @@ config ROM_SIZE
 	default 0xc00000 if COREBOOT_ROMSIZE_KB_12288
 	default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
 
+config ROM_START
+	hex
+	default 0 if !ARCH_X86
+	default 0xffff0000 if COREBOOT_ROMSIZE_KB_64
+	default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+	default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+	default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+	default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+	default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+	default 0xffc00000 if COREBOOT_ROMSIZE_KB_4096
+	default 0xff800000 if COREBOOT_ROMSIZE_KB_8192
+	default 0xff400000 if COREBOOT_ROMSIZE_KB_12288
+	default 0xff000000 if COREBOOT_ROMSIZE_KB_16384
+
 config ENABLE_POWER_BUTTON
 	bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
 	default y if POWER_BUTTON_DEFAULT_ENABLE


From gerrit at coreboot.org  Fri Sep 11 21:42:45 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Fri, 11 Sep 2015 21:42:45 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	cbfstool/cbfs_image.c: Just use one space before `=`
References: <Id31c889d1e83e7ddfb0f0f98b78601f37b71cfa2+0@gerrit.coreboot.org>
Message-ID: <Id31c889d1e83e7ddfb0f0f98b78601f37b71cfa2+1@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11631

-gerrit

commit e6bab340930bf80c9f02793a878d4ddb122b64b6
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Sat Aug 8 20:20:57 2015 +0200

    cbfstool/cbfs_image.c: Just use one space before `=`
    
    Change-Id: Id31c889d1e83e7ddfb0f0f98b78601f37b71cfa2
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 util/cbfstool/cbfs_image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index c40bd66..50b97ef 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -852,7 +852,7 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry,
 			break;
 
 		case CBFS_COMPONENT_PAYLOAD:
-			payload  = (struct cbfs_payload_segment *)
+			payload = (struct cbfs_payload_segment *)
 					CBFS_SUBHEADER(entry);
 			while (payload) {
 				struct cbfs_payload_segment seg;


From gerrit at coreboot.org  Fri Sep 11 21:42:47 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Fri, 11 Sep 2015 21:42:47 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: Fix
	removing and adding file with same name
References: <I033456ab10e3e1b402ac2374f3a887cefd3e5abf+0@gerrit.coreboot.org>
Message-ID: <I033456ab10e3e1b402ac2374f3a887cefd3e5abf+1@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11632

-gerrit

commit 5694ec710caf22e43fc8544333542f5954ed4809
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Aug 8 20:25:17 2015 +0200

    cbfstool: Fix removing and adding file with same name
    
    Currently, cbfstool regressed that removing a file from CBFS the space
    is marked as empty but the filename is still shown, preventing adding a
    file with the same name again. [1]
    
    ```
    $ echo a > a
    $ echo b > b
    $ ./util/cbfstool/cbfstool  test.rom create -m x86 -s 1024
    Created CBFS (capacity = 920 bytes)
    $ ./util/cbfstool/cbfstool test.rom add -f a -n a -t raw
    $ ./util/cbfstool/cbfstool test.rom add -f b -n b -t raw
    $ cp test.rom test.rom.original
    $ ./util/cbfstool/cbfstool test.rom remove  -n
    $ diff -up <(hexdump -C test.rom.original) <(hexdump -C test.rom)
    --- /dev/fd/63  2015-08-07 08:43:42.118430961 -0500
    +++ /dev/fd/62  2015-08-07 08:43:42.114430961 -0500
    @@ -1,4 +1,4 @@
    -00000000  4c 41 52 43 48 49 56 45  00 00 00 02 00 00 00 50  |LARCHIVE.......P|
    +00000000  4c 41 52 43 48 49 56 45  00 00 00 02 ff ff ff ff  |LARCHIVE........|
     00000010  00 00 00 00 00 00 00 28  61 00 00 00 00 00 00 00  |.......(a.......|
     00000020  00 00 00 00 00 00 00 00  61 0a ff ff ff ff ff ff  |........a.......|
     00000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
    $ ./util/cbfstool/cbfstool test.rom add -f c -n c -t raw
    
    $ ./util/cbfstool/cbfstool test.rom print
    test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
    alignment: 64 bytes, architecture: x86
    
    Name                           Offset     Type         Size
    c                              0x0        raw          2
    b                              0x40       raw          2
    (empty)                        0x80       null         792
    ```
    
    So it is ?deteled? as the type changed. But the name was not changed to
    match the *(empty)* heuristic.
    
    So also adapt the name when removing a file by writing a null byte to
    the beginning of the name, so that the heuristic works. (Though remove
    doesn't really clear contents.)
    
    ```
    $ ./util/cbfstool/cbfstool test.rom remove  -n c
    $ ./util/cbfstool/cbfstool test.rom print
    test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
    alignment: 64 bytes, architecture: x86
    
    Name                           Offset     Type         Size
    (empty)                        0x0        null         2
    b                              0x40       raw          2
    (empty)                        0x80       null         792
    ```
    
    [1] http://www.coreboot.org/pipermail/coreboot/2015-August/080201.html
    
    Change-Id: I033456ab10e3e1b402ac2374f3a887cefd3e5abf
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 util/cbfstool/cbfs_image.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 50b97ef..c47069c 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -884,6 +884,7 @@ int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry,
 			   unused void *arg)
 {
 	struct cbfs_file *next;
+	uint8_t *name;
 	uint32_t type, addr, last_addr;
 
 	type = ntohl(entry->type);
@@ -891,6 +892,9 @@ int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry,
 		// Ready to be recycled.
 		type = CBFS_COMPONENT_NULL;
 		entry->type = htonl(type);
+		// Place NUL byte as first byte of name to be viewed as "empty".
+		*name = (void *)&entry[1];
+		*name = '\0';
 	}
 	if (type != CBFS_COMPONENT_NULL)
 		return 0;


From gerrit at coreboot.org  Fri Sep 11 21:44:21 2015
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Fri, 11 Sep 2015 21:44:21 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: AGESA S3
	support: Fix excessive stack usage
References: <I993df6abc04436fb135822729c4931c5c7496e5a+0@gerrit.coreboot.org>
Message-ID: <I993df6abc04436fb135822729c4931c5c7496e5a+1@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11633

-gerrit

commit 63dcce1b58ae33c3ce6b9cd96fb343fe72e9d54b
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Sat Sep 12 00:20:25 2015 +0300

    AGESA S3 support: Fix excessive stack usage
    
    Commit 300caced9 introduced stack overflow when HAVE_ACPI_RESUME
    is selected as the temporary storage for MTRRs is 4KiB.
    
    Change-Id: I993df6abc04436fb135822729c4931c5c7496e5a
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/northbridge/amd/agesa/oem_s3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index 5f02815..f9ce4a7 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -115,6 +115,8 @@ static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
 #endif
 }
 
+static u8 MTRRStorage[S3_DATA_MTRR_SIZE];
+
 AGESA_STATUS OemS3Save(void *vS3SaveParams)
 {
 #if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01)
@@ -124,7 +126,6 @@ AGESA_STATUS OemS3Save(void *vS3SaveParams)
 	AMD_S3SAVE_PARAMS *S3SaveParams = (AMD_S3SAVE_PARAMS *)vS3SaveParams;
 	AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock;
 #endif
-	u8 MTRRStorage[S3_DATA_MTRR_SIZE];
 	u32 MTRRStorageSize = 0;
 	uintptr_t pos, size;
 


From gerrit at coreboot.org  Sat Sep 12 08:39:15 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Sat, 12 Sep 2015 08:39:15 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: Fix
	removing and adding file with same name
References: <I033456ab10e3e1b402ac2374f3a887cefd3e5abf+0@gerrit.coreboot.org>
Message-ID: <I033456ab10e3e1b402ac2374f3a887cefd3e5abf+2@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11632

-gerrit

commit 297ca027972e7b2e28f6f6903a40a13f1324b0ad
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Sat Aug 8 20:25:17 2015 +0200

    cbfstool: Fix removing and adding file with same name
    
    Currently, cbfstool regressed that removing a file from CBFS the space
    is marked as empty but the filename is still shown, preventing adding a
    file with the same name again. [1]
    
    ```
    $ echo a > a
    $ echo b > b
    $ ./util/cbfstool/cbfstool  test.rom create -m x86 -s 1024
    Created CBFS (capacity = 920 bytes)
    $ ./util/cbfstool/cbfstool test.rom add -f a -n a -t raw
    $ ./util/cbfstool/cbfstool test.rom add -f b -n b -t raw
    $ cp test.rom test.rom.original
    $ ./util/cbfstool/cbfstool test.rom remove  -n
    $ diff -up <(hexdump -C test.rom.original) <(hexdump -C test.rom)
    --- /dev/fd/63  2015-08-07 08:43:42.118430961 -0500
    +++ /dev/fd/62  2015-08-07 08:43:42.114430961 -0500
    @@ -1,4 +1,4 @@
    -00000000  4c 41 52 43 48 49 56 45  00 00 00 02 00 00 00 50  |LARCHIVE.......P|
    +00000000  4c 41 52 43 48 49 56 45  00 00 00 02 ff ff ff ff  |LARCHIVE........|
     00000010  00 00 00 00 00 00 00 28  61 00 00 00 00 00 00 00  |.......(a.......|
     00000020  00 00 00 00 00 00 00 00  61 0a ff ff ff ff ff ff  |........a.......|
     00000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
    $ ./util/cbfstool/cbfstool test.rom add -f c -n c -t raw
    
    $ ./util/cbfstool/cbfstool test.rom print
    test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
    alignment: 64 bytes, architecture: x86
    
    Name                           Offset     Type         Size
    c                              0x0        raw          2
    b                              0x40       raw          2
    (empty)                        0x80       null         792
    ```
    
    So it is ?deteled? as the type changed. But the name was not changed to
    match the *(empty)* heuristic.
    
    So also adapt the name when removing a file by writing a null byte to
    the beginning of the name, so that the heuristic works. (Though remove
    doesn't really clear contents.)
    
    ```
    $ ./util/cbfstool/cbfstool test.rom remove  -n c
    $ ./util/cbfstool/cbfstool test.rom print
    test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
    alignment: 64 bytes, architecture: x86
    
    Name                           Offset     Type         Size
    (empty)                        0x0        null         2
    b                              0x40       raw          2
    (empty)                        0x80       null         792
    ```
    
    [1] http://www.coreboot.org/pipermail/coreboot/2015-August/080201.html
    
    Change-Id: I033456ab10e3e1b402ac2374f3a887cefd3e5abf
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 util/cbfstool/cbfs_image.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 50b97ef..97b349a 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -884,6 +884,7 @@ int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry,
 			   unused void *arg)
 {
 	struct cbfs_file *next;
+	uint8_t *name;
 	uint32_t type, addr, last_addr;
 
 	type = ntohl(entry->type);
@@ -891,6 +892,9 @@ int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry,
 		// Ready to be recycled.
 		type = CBFS_COMPONENT_NULL;
 		entry->type = htonl(type);
+		// Place NUL byte as first byte of name to be viewed as "empty".
+		name = (void *)&entry[1];
+		*name = '\0';
 	}
 	if (type != CBFS_COMPONENT_NULL)
 		return 0;


From gerrit at coreboot.org  Sun Sep 13 11:55:12 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Sun, 13 Sep 2015 11:55:12 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: [NOTFORMERGE]
	Build with -Wstack-usage=1024
References: <Ide3a8f2f0740678ed68f07716157b99707c866f5+0@gerrit.coreboot.org>
Message-ID: <Ide3a8f2f0740678ed68f07716157b99707c866f5+1@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11634

-gerrit

commit f44c635e40d7825759aa74a87c3f32dffc5dafee
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Sun Sep 13 13:51:47 2015 +0200

    [NOTFORMERGE] Build with -Wstack-usage=1024
    
    http://www.coreboot.org/pipermail/coreboot/2015-September/080353.html
    
    Change-Id: Ide3a8f2f0740678ed68f07716157b99707c866f5
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 Makefile.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..696dbda 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -693,3 +693,5 @@ what-jenkins-does:
 	util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD)
 	(cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml)
 	$(MAKE) V=$(V) Q=$(Q) -C util/cbmem junit.xml
+
+CFLAGS_ramstage += -Wstack-usage=1024


From gerrit at coreboot.org  Mon Sep 14 02:28:17 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 14 Sep 2015 02:28:17 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: corebot: add
	bytestream helpfer functions
References: <I59a44704e9bff9bf11e779970ad4667e2e6b2bdd+0@gerrit.coreboot.org>
Message-ID: <I59a44704e9bff9bf11e779970ad4667e2e6b2bdd+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11625

-gerrit

commit 662fa13f8f8b48bfb3c6d038692dd0d646be4f6a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 11 11:26:37 2015 -0500

    corebot: add bytestream helpfer functions
    
    Allow one to operate on a buffer to interpret values
    based on an endianness encoding. Endian functions are
    open coded. The cbfs walking code was update to use the
    API. It requires one to open code the tracking field
    offset and sizes while also not providing any bounds
    checking.
    
    TEST=Built and booted on glados.
    
    Change-Id: I59a44704e9bff9bf11e779970ad4667e2e6b2bdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bytestream.h | 93 ++++++++++++++++++++++++++++++++++++++++++++++++
 src/lib/cbfs.c           | 51 +++++++++++++++++---------
 2 files changed, 127 insertions(+), 17 deletions(-)

diff --git a/src/include/bytestream.h b/src/include/bytestream.h
new file mode 100644
index 0000000..badc5a5
--- /dev/null
+++ b/src/include/bytestream.h
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _BYTESTREAM_H_
+#define _BYTESTREAM_H_
+
+#include <stdint.h>
+
+static inline uint8_t read_be8(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return *s;
+}
+
+static inline uint16_t read_be16(const void *src, size_t offset)
+{
+	uint16_t val;
+	val = read_be8(src, offset);
+	val <<= 8;
+	val |= read_be8(src, offset + sizeof(uint8_t));
+	return val;
+}
+
+static inline uint32_t read_be32(const void *src, size_t offset)
+{
+	uint32_t val;
+	val = read_be16(src, offset);
+	val <<= 16;
+	val |= read_be16(src, offset + sizeof(uint16_t));
+	return val;
+}
+
+static inline uint64_t read_be64(const void *src, size_t offset)
+{
+	uint64_t val;
+	val = read_be32(src, offset);
+	val <<= 32;
+	val |= read_be32(src, offset + sizeof(uint32_t));
+	return val;
+}
+
+static inline uint8_t read_le8(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return *s;
+}
+
+static inline uint16_t read_le16(const void *src, size_t offset)
+{
+	uint16_t val;
+	val = read_le8(src, offset + sizeof(uint8_t));
+	val <<= 8;
+	val |= read_le8(src, offset);
+	return val;
+}
+
+static inline uint32_t read_le32(const void *src, size_t offset)
+{
+	uint32_t val;
+	val = read_le16(src, offset + sizeof(uint16_t));
+	val <<= 16;
+	val = read_le16(src, offset);
+	return val;
+}
+
+static inline uint64_t read_le64(const void *src, size_t offset)
+{
+	uint64_t val;
+	val = read_le32(src, offset + sizeof(uint32_t));
+	val <<= 32;
+	val |= read_le32(src, offset);
+	return val;
+}
+
+#endif
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index abc4077..83cd247 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <stdlib.h>
 #include <boot_device.h>
+#include <bytestream.h>
 #include <cbfs.h>
 #include <endian.h>
 #include <lib.h>
@@ -90,30 +91,46 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 	/* Try to scan the entire cbfs region looking for file name. */
 	while (1) {
-		struct cbfs_file file;
-		const size_t fsz = sizeof(file);
+		uint8_t magic[8];
+		uint32_t flen;
+		uint32_t ftype;
+		uint32_t foffset;
+		size_t strmoff;
+		const size_t fsz = sizeof(struct cbfs_file);
+		void *file_mapping;
 		char *fname;
 		int name_match;
 		size_t datasz;
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		/* Can't read file. Nothing else to do but bail out. */
-		if (rdev_readat(rd, &file, offset, fsz) != fsz)
+		file_mapping = rdev_mmap(rd, offset, fsz);
+
+		if (file_mapping == NULL)
 			break;
 
-		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
+		/* Magic is a byte string w/ no endian encoding. */
+		memcpy(magic, file_mapping, sizeof(magic));
+		strmoff = sizeof(magic);
+
+		flen = read_be32(file_mapping, strmoff);
+		strmoff += sizeof(flen);
+		ftype = read_be32(file_mapping, strmoff);
+		strmoff += sizeof(ftype);
+		/* Skip the checksum field. */
+		strmoff += sizeof(ftype);
+		foffset = read_be32(file_mapping, strmoff);
+
+		rdev_munmap(rd, file_mapping);
+
+		if (memcmp(magic, CBFS_FILE_MAGIC, sizeof(magic))) {
 			offset++;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		file.len = ntohl(file.len);
-		file.type = ntohl(file.type);
-		file.offset = ntohl(file.offset);
-
 		/* See if names match. */
-		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
+		fname = rdev_mmap(rd, offset + fsz, foffset - fsz);
 
 		if (fname == NULL)
 			break;
@@ -123,23 +140,23 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 		if (!name_match) {
 			DEBUG(" Unmatched '%s' at %zx\n", fname, offset);
-			offset += file.offset + file.len;
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		if (type != NULL && *type != file.type) {
-			DEBUG(" Unmatched type %x at %zx\n", file.type, offset);
-			offset += file.offset + file.len;
+		if (type != NULL && *type != ftype) {
+			DEBUG(" Unmatched type %x at %zx\n", ftype, offset);
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		LOG("Found @ offset %zx size %x\n", offset, file.len);
+		LOG("Found @ offset %zx size %x\n", offset, flen);
 		/* File and type match. Create a chained region_device to
 		 * represent the cbfs file. */
-		offset += file.offset;
-		datasz = file.len;
+		offset += foffset;
+		datasz = flen;
 		if (rdev_chain(fh, rd, offset, datasz))
 			break;
 


From gerrit at coreboot.org  Mon Sep 14 02:36:32 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 14 Sep 2015 02:36:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: corebot: add
	bytestream helpfer functions
References: <I59a44704e9bff9bf11e779970ad4667e2e6b2bdd+0@gerrit.coreboot.org>
Message-ID: <I59a44704e9bff9bf11e779970ad4667e2e6b2bdd+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11625

-gerrit

commit fb0353c275d06ba0f77cd6858b4290c7c2112278
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 11 11:26:37 2015 -0500

    corebot: add bytestream helpfer functions
    
    Allow one to operate on a buffer to interpret values
    based on an endianness encoding. Endian functions are
    open coded and unrolled. The cbfs walking code was
    update to use the API. It requires one to open code
    the tracking field offset and sizes while also not
    providing any bounds checking.
    
    TEST=Built and booted on glados.
    
    Change-Id: I59a44704e9bff9bf11e779970ad4667e2e6b2bdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bytestream.h | 121 +++++++++++++++++++++++++++++++++++++++++++++++
 src/lib/cbfs.c           |  51 +++++++++++++-------
 2 files changed, 155 insertions(+), 17 deletions(-)

diff --git a/src/include/bytestream.h b/src/include/bytestream.h
new file mode 100644
index 0000000..0b8d794
--- /dev/null
+++ b/src/include/bytestream.h
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _BYTESTREAM_H_
+#define _BYTESTREAM_H_
+
+#include <stdint.h>
+
+static inline uint8_t read_be8(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return *s;
+}
+
+static inline uint16_t read_be16(const void *src, size_t offset)
+{
+	uint16_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint16_t)s[0]) << 8;
+	val |= ((uint16_t)s[1]) << 0;
+	return val;
+}
+
+static inline uint32_t read_be32(const void *src, size_t offset)
+{
+	uint32_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint32_t)s[0]) << 24;
+	val |= ((uint32_t)s[1]) << 16;
+	val |= ((uint32_t)s[2]) << 8;
+	val |= ((uint32_t)s[3]) << 0;
+	return val;
+}
+
+static inline uint64_t read_be64(const void *src, size_t offset)
+{
+	uint64_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint64_t)s[0]) << (24 + 32);
+	val |= ((uint64_t)s[1]) << (16 + 32);
+	val |= ((uint64_t)s[2]) << (8 + 32);
+	val |= ((uint64_t)s[3]) << (0 + 32);
+	val |= ((uint64_t)s[4]) << 24;
+	val |= ((uint64_t)s[5]) << 16;
+	val |= ((uint64_t)s[6]) << 8;
+	val |= ((uint64_t)s[7]) << 0;
+	return val;
+}
+
+static inline uint8_t read_le8(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return *s;
+}
+
+static inline uint16_t read_le16(const void *src, size_t offset)
+{
+	uint16_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint16_t)s[0]) << 0;
+	val |= ((uint16_t)s[1]) << 8;
+	return val;
+}
+
+static inline uint32_t read_le32(const void *src, size_t offset)
+{
+	uint32_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint32_t)s[0]) << 0;
+	val |= ((uint32_t)s[1]) << 8;
+	val |= ((uint32_t)s[2]) << 16;
+	val |= ((uint32_t)s[3]) << 24;
+	return val;
+}
+
+static inline uint64_t read_le64(const void *src, size_t offset)
+{
+	uint64_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint64_t)s[0]) << 0;
+	val |= ((uint64_t)s[1]) << 8;
+	val |= ((uint64_t)s[2]) << 16;
+	val |= ((uint64_t)s[3]) << 24;
+	val |= ((uint64_t)s[4]) << (0 + 32);
+	val |= ((uint64_t)s[5]) << (8 + 32);
+	val |= ((uint64_t)s[6]) << (16 + 32);
+	val |= ((uint64_t)s[7]) << (24 + 32);
+	return val;
+}
+
+#endif
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index abc4077..83cd247 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <stdlib.h>
 #include <boot_device.h>
+#include <bytestream.h>
 #include <cbfs.h>
 #include <endian.h>
 #include <lib.h>
@@ -90,30 +91,46 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 	/* Try to scan the entire cbfs region looking for file name. */
 	while (1) {
-		struct cbfs_file file;
-		const size_t fsz = sizeof(file);
+		uint8_t magic[8];
+		uint32_t flen;
+		uint32_t ftype;
+		uint32_t foffset;
+		size_t strmoff;
+		const size_t fsz = sizeof(struct cbfs_file);
+		void *file_mapping;
 		char *fname;
 		int name_match;
 		size_t datasz;
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		/* Can't read file. Nothing else to do but bail out. */
-		if (rdev_readat(rd, &file, offset, fsz) != fsz)
+		file_mapping = rdev_mmap(rd, offset, fsz);
+
+		if (file_mapping == NULL)
 			break;
 
-		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
+		/* Magic is a byte string w/ no endian encoding. */
+		memcpy(magic, file_mapping, sizeof(magic));
+		strmoff = sizeof(magic);
+
+		flen = read_be32(file_mapping, strmoff);
+		strmoff += sizeof(flen);
+		ftype = read_be32(file_mapping, strmoff);
+		strmoff += sizeof(ftype);
+		/* Skip the checksum field. */
+		strmoff += sizeof(ftype);
+		foffset = read_be32(file_mapping, strmoff);
+
+		rdev_munmap(rd, file_mapping);
+
+		if (memcmp(magic, CBFS_FILE_MAGIC, sizeof(magic))) {
 			offset++;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		file.len = ntohl(file.len);
-		file.type = ntohl(file.type);
-		file.offset = ntohl(file.offset);
-
 		/* See if names match. */
-		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
+		fname = rdev_mmap(rd, offset + fsz, foffset - fsz);
 
 		if (fname == NULL)
 			break;
@@ -123,23 +140,23 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 		if (!name_match) {
 			DEBUG(" Unmatched '%s' at %zx\n", fname, offset);
-			offset += file.offset + file.len;
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		if (type != NULL && *type != file.type) {
-			DEBUG(" Unmatched type %x at %zx\n", file.type, offset);
-			offset += file.offset + file.len;
+		if (type != NULL && *type != ftype) {
+			DEBUG(" Unmatched type %x at %zx\n", ftype, offset);
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		LOG("Found @ offset %zx size %x\n", offset, file.len);
+		LOG("Found @ offset %zx size %x\n", offset, flen);
 		/* File and type match. Create a chained region_device to
 		 * represent the cbfs file. */
-		offset += file.offset;
-		datasz = file.len;
+		offset += foffset;
+		datasz = flen;
 		if (rdev_chain(fh, rd, offset, datasz))
 			break;
 


From gerrit at coreboot.org  Mon Sep 14 03:31:02 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 14 Sep 2015 03:31:02 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: coreboot: add
	rdevbs (region device byte stream)
References: <I60feb24ae1b2abadb23b23201f38c85ade5bcfbd+0@gerrit.coreboot.org>
Message-ID: <I60feb24ae1b2abadb23b23201f38c85ade5bcfbd+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11624

-gerrit

commit 916f4ae336a9bac07a035b9cfae6f6903fdf9ec2
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 11 09:49:12 2015 -0500

    coreboot: add rdevbs (region device byte stream)
    
    Add a region device byte stream object, rdevbs, which
    will perform designated endian operations for reading
    serialized objects out of a region device. The cbfs
    walking code was updated to show usage of the library.
    
    The implementation uses memory region device after
    performing a mapping on the original parent. The reason
    is absorb the communication costs of dealing with a
    controller and its external media.
    
    TEST=Booted glados.
    
    Change-Id: I60feb24ae1b2abadb23b23201f38c85ade5bcfbd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/region.h |  28 ++++++++++++
 src/lib/cbfs.c       |  32 +++++++-------
 src/lib/region.c     | 120 +++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 164 insertions(+), 16 deletions(-)

diff --git a/src/include/region.h b/src/include/region.h
index 82db854..b1f9789 100644
--- a/src/include/region.h
+++ b/src/include/region.h
@@ -154,4 +154,32 @@ void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
 void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
 int mmap_helper_rdev_munmap(const struct region_device *, void *);
 
+/* Interpret region_device as byte stream operations with endian conversions. */
+struct rdevbs {
+	const struct region_device *parent;
+	size_t current_offset;
+	void *mapping;
+	void (*read)(struct rdevbs *bs, void *dest, size_t size);
+};
+
+/*
+ * Initialize an rdev byte stream from parent for reading stream_size bytes
+ * for the endianness interpretation. Returns 0 on success, < 0 on error.
+ */
+int rdevbs_init_le(struct rdevbs *bs, const struct region_device *parent,
+		size_t stream_offset, size_t stream_size);
+int rdevbs_init_be(struct rdevbs *bs, const struct region_device *parent,
+		size_t stream_offset, size_t stream_size);
+
+/* Return 0 on success, < 0 on error. */
+int rdevbs_read(struct rdevbs *bs, void *dest, size_t size);
+
+/* Indicate that the bytream is complete and any resources can be freed. */
+void rdevbs_complete(struct rdevbs *bs);
+
+static inline void rdevbs_skip(struct rdevbs *bs, size_t bytes)
+{
+	bs->current_offset += bytes;
+}
+
 #endif /* _REGION_H_ */
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 83cd247..40146ee 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -95,33 +95,33 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 		uint32_t flen;
 		uint32_t ftype;
 		uint32_t foffset;
-		size_t strmoff;
 		const size_t fsz = sizeof(struct cbfs_file);
-		void *file_mapping;
 		char *fname;
 		int name_match;
 		size_t datasz;
+		struct rdevbs bs;
+		size_t i;
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		file_mapping = rdev_mmap(rd, offset, fsz);
-
-		if (file_mapping == NULL)
+		if (rdevbs_init_be(&bs, rd, offset, fsz))
 			break;
 
-		/* Magic is a byte string w/ no endian encoding. */
-		memcpy(magic, file_mapping, sizeof(magic));
-		strmoff = sizeof(magic);
+		/* Joy. magic is a byte array w/o an endian encoding. */
+		for (i = 0; i < sizeof(magic); i++)
+			if (rdevbs_read(&bs, &magic[i], sizeof(magic[i])))
+				break;
 
-		flen = read_be32(file_mapping, strmoff);
-		strmoff += sizeof(flen);
-		ftype = read_be32(file_mapping, strmoff);
-		strmoff += sizeof(ftype);
-		/* Skip the checksum field. */
-		strmoff += sizeof(ftype);
-		foffset = read_be32(file_mapping, strmoff);
+		if (rdevbs_read(&bs, &flen, sizeof(flen)))
+			break;
+		if (rdevbs_read(&bs, &ftype, sizeof(ftype)))
+			break;
+		/* Skip checksum field. */
+		rdevbs_skip(&bs, sizeof(uint32_t));
+		if (rdevbs_read(&bs, &foffset, sizeof(foffset)))
+			break;
 
-		rdev_munmap(rd, file_mapping);
+		rdevbs_complete(&bs);
 
 		if (memcmp(magic, CBFS_FILE_MAGIC, sizeof(magic))) {
 			offset++;
diff --git a/src/lib/region.c b/src/lib/region.c
index d5d3762..1a34533 100644
--- a/src/lib/region.c
+++ b/src/lib/region.c
@@ -17,6 +17,7 @@
  * Foundation, Inc.
  */
 
+#include <bytestream.h>
 #include <region.h>
 #include <string.h>
 
@@ -194,3 +195,122 @@ int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
 
 	return 0;
 }
+
+static void rdevbs_read_le(struct rdevbs *bs, void *dest, size_t size)
+{
+	uint64_t *ptr64;
+	uint32_t *ptr32;
+	uint16_t *ptr16;
+	uint8_t *ptr8;
+
+	switch (size) {
+	case sizeof(uint64_t):
+		ptr64 = dest;
+		*ptr64 = read_le64(bs->mapping, bs->current_offset);
+		break;
+	case sizeof(uint32_t):
+		ptr32 = dest;
+		*ptr32 = read_le32(bs->mapping, bs->current_offset);
+		break;
+	case sizeof(uint16_t):
+		ptr16 = dest;
+		*ptr16 = read_le16(bs->mapping, bs->current_offset);
+		break;
+	case sizeof(uint8_t):
+		ptr8 = dest;
+		*ptr8 = read_be8(bs->mapping, bs->current_offset);
+		break;
+	}
+}
+
+static void rdevbs_read_be(struct rdevbs *bs, void *dest, size_t size)
+{
+	uint64_t *ptr64;
+	uint32_t *ptr32;
+	uint16_t *ptr16;
+	uint8_t *ptr8;
+
+	switch (size) {
+	case sizeof(uint64_t):
+		ptr64 = dest;
+		*ptr64 = read_be64(bs->mapping, bs->current_offset);
+		break;
+	case sizeof(uint32_t):
+		ptr32 = dest;
+		*ptr32 = read_be32(bs->mapping, bs->current_offset);
+		break;
+	case sizeof(uint16_t):
+		ptr16 = dest;
+		*ptr16 = read_be16(bs->mapping, bs->current_offset);
+		break;
+	case sizeof(uint8_t):
+		ptr8 = dest;
+		*ptr8 = read_be8(bs->mapping, bs->current_offset);
+		break;
+	}
+}
+
+static int rdevbs_init(struct rdevbs *bs, const struct region_device *parent,
+			size_t stream_offset, size_t stream_size)
+{
+	void *mapping;
+
+	bs->parent = parent;
+	bs->current_offset = 0;
+
+	/*
+	 * One needs the object storage in order to read from the stream
+	 * efficiently. Otherwise there would be many small round trip
+	 * operations to the backing controller. Instead use a mapping of
+	 * the size to be consumed.
+	 */
+	mapping = rdev_mmap(parent, stream_offset, stream_size);
+
+	if (mapping == NULL)
+		return -1;
+
+	bs->mapping = mapping;
+
+	return 0;
+}
+
+int rdevbs_init_le(struct rdevbs *bs, const struct region_device *parent,
+		size_t stream_offset, size_t stream_size)
+{
+	bs->read = rdevbs_read_le;
+	return rdevbs_init(bs, parent, stream_offset, stream_size);
+}
+
+int rdevbs_init_be(struct rdevbs *bs, const struct region_device *parent,
+		size_t stream_offset, size_t stream_size)
+{
+	bs->read = rdevbs_read_be;
+	return rdevbs_init(bs, parent, stream_offset, stream_size);
+}
+
+int rdevbs_read(struct rdevbs *bs, void *dest, size_t size)
+{
+	struct region r = {
+		.offset = bs->current_offset,
+		.size = size,
+	};
+
+	if (size != sizeof(uint64_t) && size != sizeof(uint32_t) &&
+			size != sizeof(uint16_t) && size != sizeof(uint8_t))
+		return -1;
+
+	if (!normalize_and_ok(&bs->parent->region, &r))
+		return -1;
+
+	bs->read(bs, dest, size);
+
+	bs->current_offset += size;
+
+	return 0;
+}
+
+void rdevbs_complete(struct rdevbs *bs)
+{
+	rdev_munmap(bs->parent, bs->mapping);
+	bs->parent = NULL;
+}


From gerrit at coreboot.org  Mon Sep 14 03:31:06 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 14 Sep 2015 03:31:06 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: corebot: add
	bytestream helpfer functions
References: <I59a44704e9bff9bf11e779970ad4667e2e6b2bdd+0@gerrit.coreboot.org>
Message-ID: <I59a44704e9bff9bf11e779970ad4667e2e6b2bdd+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11625

-gerrit

commit 99aea7f7870728362799e8898cb0597b40b5d525
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 11 11:26:37 2015 -0500

    corebot: add bytestream helpfer functions
    
    Allow one to operate on a buffer to interpret values
    based on an endianness encoding. Endian functions are
    open coded and unrolled. The cbfs walking code was
    update to use the API. It requires one to open code
    the tracking field offset and sizes while also not
    providing any bounds checking.
    
    TEST=Built and booted on glados.
    
    Change-Id: I59a44704e9bff9bf11e779970ad4667e2e6b2bdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/bytestream.h | 122 +++++++++++++++++++++++++++++++++++++++++++++++
 src/lib/cbfs.c           |  51 +++++++++++++-------
 2 files changed, 156 insertions(+), 17 deletions(-)

diff --git a/src/include/bytestream.h b/src/include/bytestream.h
new file mode 100644
index 0000000..2cbf579
--- /dev/null
+++ b/src/include/bytestream.h
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _BYTESTREAM_H_
+#define _BYTESTREAM_H_
+
+#include <stdint.h>
+#include <stddef.h>
+
+static inline uint8_t read_be8(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return *s;
+}
+
+static inline uint16_t read_be16(const void *src, size_t offset)
+{
+	uint16_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint16_t)s[0]) << 8;
+	val |= ((uint16_t)s[1]) << 0;
+	return val;
+}
+
+static inline uint32_t read_be32(const void *src, size_t offset)
+{
+	uint32_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint32_t)s[0]) << 24;
+	val |= ((uint32_t)s[1]) << 16;
+	val |= ((uint32_t)s[2]) << 8;
+	val |= ((uint32_t)s[3]) << 0;
+	return val;
+}
+
+static inline uint64_t read_be64(const void *src, size_t offset)
+{
+	uint64_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint64_t)s[0]) << (24 + 32);
+	val |= ((uint64_t)s[1]) << (16 + 32);
+	val |= ((uint64_t)s[2]) << (8 + 32);
+	val |= ((uint64_t)s[3]) << (0 + 32);
+	val |= ((uint64_t)s[4]) << 24;
+	val |= ((uint64_t)s[5]) << 16;
+	val |= ((uint64_t)s[6]) << 8;
+	val |= ((uint64_t)s[7]) << 0;
+	return val;
+}
+
+static inline uint8_t read_le8(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return *s;
+}
+
+static inline uint16_t read_le16(const void *src, size_t offset)
+{
+	uint16_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint16_t)s[0]) << 0;
+	val |= ((uint16_t)s[1]) << 8;
+	return val;
+}
+
+static inline uint32_t read_le32(const void *src, size_t offset)
+{
+	uint32_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint32_t)s[0]) << 0;
+	val |= ((uint32_t)s[1]) << 8;
+	val |= ((uint32_t)s[2]) << 16;
+	val |= ((uint32_t)s[3]) << 24;
+	return val;
+}
+
+static inline uint64_t read_le64(const void *src, size_t offset)
+{
+	uint64_t val;
+	const uint8_t *s = src;
+	s += offset;
+	val = 0;
+	val |= ((uint64_t)s[0]) << 0;
+	val |= ((uint64_t)s[1]) << 8;
+	val |= ((uint64_t)s[2]) << 16;
+	val |= ((uint64_t)s[3]) << 24;
+	val |= ((uint64_t)s[4]) << (0 + 32);
+	val |= ((uint64_t)s[5]) << (8 + 32);
+	val |= ((uint64_t)s[6]) << (16 + 32);
+	val |= ((uint64_t)s[7]) << (24 + 32);
+	return val;
+}
+
+#endif
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index abc4077..83cd247 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <stdlib.h>
 #include <boot_device.h>
+#include <bytestream.h>
 #include <cbfs.h>
 #include <endian.h>
 #include <lib.h>
@@ -90,30 +91,46 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 	/* Try to scan the entire cbfs region looking for file name. */
 	while (1) {
-		struct cbfs_file file;
-		const size_t fsz = sizeof(file);
+		uint8_t magic[8];
+		uint32_t flen;
+		uint32_t ftype;
+		uint32_t foffset;
+		size_t strmoff;
+		const size_t fsz = sizeof(struct cbfs_file);
+		void *file_mapping;
 		char *fname;
 		int name_match;
 		size_t datasz;
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		/* Can't read file. Nothing else to do but bail out. */
-		if (rdev_readat(rd, &file, offset, fsz) != fsz)
+		file_mapping = rdev_mmap(rd, offset, fsz);
+
+		if (file_mapping == NULL)
 			break;
 
-		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
+		/* Magic is a byte string w/ no endian encoding. */
+		memcpy(magic, file_mapping, sizeof(magic));
+		strmoff = sizeof(magic);
+
+		flen = read_be32(file_mapping, strmoff);
+		strmoff += sizeof(flen);
+		ftype = read_be32(file_mapping, strmoff);
+		strmoff += sizeof(ftype);
+		/* Skip the checksum field. */
+		strmoff += sizeof(ftype);
+		foffset = read_be32(file_mapping, strmoff);
+
+		rdev_munmap(rd, file_mapping);
+
+		if (memcmp(magic, CBFS_FILE_MAGIC, sizeof(magic))) {
 			offset++;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		file.len = ntohl(file.len);
-		file.type = ntohl(file.type);
-		file.offset = ntohl(file.offset);
-
 		/* See if names match. */
-		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
+		fname = rdev_mmap(rd, offset + fsz, foffset - fsz);
 
 		if (fname == NULL)
 			break;
@@ -123,23 +140,23 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 		if (!name_match) {
 			DEBUG(" Unmatched '%s' at %zx\n", fname, offset);
-			offset += file.offset + file.len;
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		if (type != NULL && *type != file.type) {
-			DEBUG(" Unmatched type %x at %zx\n", file.type, offset);
-			offset += file.offset + file.len;
+		if (type != NULL && *type != ftype) {
+			DEBUG(" Unmatched type %x at %zx\n", ftype, offset);
+			offset += foffset + flen;
 			offset = ALIGN_UP(offset, CBFS_ALIGNMENT);
 			continue;
 		}
 
-		LOG("Found @ offset %zx size %x\n", offset, file.len);
+		LOG("Found @ offset %zx size %x\n", offset, flen);
 		/* File and type match. Create a chained region_device to
 		 * represent the cbfs file. */
-		offset += file.offset;
-		datasz = file.len;
+		offset += foffset;
+		datasz = flen;
 		if (rdev_chain(fh, rd, offset, datasz))
 			break;
 


From gerrit at coreboot.org  Mon Sep 14 10:01:01 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 14 Sep 2015 10:01:01 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: AGESA S3
	support: Fix excessive stack usage
References: <I993df6abc04436fb135822729c4931c5c7496e5a+0@gerrit.coreboot.org>
Message-ID: <E1ZbQZJ-000684-Ev@mail.coreboot.org>

the following patch was just integrated into master:
commit 98e0ac00b9cd5a1ba87b2e965584a37078c58e42
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Sat Sep 12 00:20:25 2015 +0300

    AGESA S3 support: Fix excessive stack usage
    
    Commit 300caced9 introduced stack overflow when HAVE_ACPI_RESUME
    is selected as the temporary storage for MTRRs is 4KiB.
    
    Change-Id: I993df6abc04436fb135822729c4931c5c7496e5a
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
    Reviewed-on: http://review.coreboot.org/11633
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11633 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 14 16:06:46 2015
From: gerrit at coreboot.org (Thaminda Edirisooriya (thaminda@google.com))
Date: Mon, 14 Sep 2015 16:06:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: riscv-memlayout:
	fix existing memlayout issues, add sbi interface
References: <Id97fe75e45ac1361005bec6d421756ee3f98a508+0@gerrit.coreboot.org>
Message-ID: <Id97fe75e45ac1361005bec6d421756ee3f98a508+10@gerrit.coreboot.org>

Thaminda Edirisooriya (thaminda at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11370

-gerrit

commit 2a818f38d7cb4529fa19b40976768d04920cb9fe
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Wed Aug 26 15:39:16 2015 -0700

    riscv-memlayout: fix existing memlayout issues, add sbi interface
    
    Existing memlayout code placed sections in overlapping areas, and would
    overwrite the payload if it was large enough. Update memlayout.ld in
    src/mainboard/emulation/spike-riscv to represent the spike emulator, and
    add sbi interface which now has room into src/arch/riscv/bootblock.S.
    Add utility code to qemu-riscv, but emulator itself has yet to be
    updated to new ISA and as such should not be used.
    Update Makefile to include all the files necessary for sbi interface.
    
    Clean up unused include in src/arch/riscv/include/atomic.h and
    whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld
    Fixed whitespace issues in spike_util.c
    
    Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
---
 src/arch/riscv/Makefile.inc                      |   3 +
 src/arch/riscv/bootblock.S                       | 108 ++++++++--
 src/arch/riscv/include/atomic.h                  |   1 -
 src/mainboard/emulation/qemu-riscv/Makefile.inc  |   3 +
 src/mainboard/emulation/qemu-riscv/qemu_util.c   | 218 +++++++++++++++++++
 src/mainboard/emulation/spike-riscv/memlayout.ld |  10 +-
 src/mainboard/emulation/spike-riscv/spike_util.c | 262 +++++++++++------------
 7 files changed, 454 insertions(+), 151 deletions(-)

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 6fac99c..de6eb91 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -31,6 +31,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
 bootblock-y = bootblock.S stages.c
 bootblock-y += trap_util.S
 bootblock-y += trap_handler.c
+bootblock-y += virtual_memory.c
 bootblock-y += boot.c
 bootblock-y += rom_media.c
 bootblock-y += \
@@ -85,6 +86,8 @@ endif
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 
 ramstage-y =
+ramstage-y += trap_handler.c
+ramstage-y += virtual_memory.c
 ramstage-y += rom_media.c
 ramstage-y += stages.c
 ramstage-y += misc.c
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index a26b144..4caeea6 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -1,7 +1,7 @@
 /*
  * Early initialization code for aarch64 (a.k.a. armv8)
  *
- * Copyright 2013Google Inc.
+ * Copyright 2013 Google Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -22,34 +22,112 @@
 
 .section ".text._start", "ax", %progbits
 // Maybe there's a better way.
-.space 0x200
+# machine mode handler when in supervisor mode
+.space 0x140
+supervisor_machine_handler:
+  j supervisor_trap_entry
+
+# handler for when
+.space 0x7c
+.globl machine_handler
+machine_handler:
+#  call trap_handler
+  j trap_entry
+
+.space 0x3c
 .globl _start
 _start:
 
 	// pending figuring out this f-ing toolchain. Hardcode what we know works.
-//  la sp, 0x4ef0 // .stacktop
-//  la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv
-  la sp, 0x7FF00 // stack start + stack size
+  la sp, 0x80FFF0 // stack start + stack size
 
-  // make room for HLS
+  # make room for HLS and initialize it
   addi sp, sp, -64 // MENTRY_FRAME_SIZE
-
+  csrr a0, mhartid
+  call hls_init
 
   //poison the stack
-  la t1, 0x40000
+  la t1, 0x800000
   li t0, 0xdeadbeef
   sd t0, 0(t1)
 
-//  la gp, _gp
+  la t0, exception_handler
+  csrw stvec, t0
 
   # clear any pending interrupts
-#if __GNUC__ < 5
-  csrwi clear_ipi, 0
-#else
   csrwi sip, 0
-#endif
 
+  # set up the mstatus register for VM
+  call mstatus_init
   call main
+.=0x2000
+    .space 0x800
+# sbi interface lives here
+
+# hart_id
+.align 5
+li a7, 0
+ecall
+ret
+
+# num_harts
+.align 4
+li a0, 1
+ret
+
+# query_memory
+.align 4
+li a7, 8
+ecall
+ret
+
+# console_putchar
+.align 4
+li a7, 1
+ecall
+ret
+
+# send_device_request
+.align 4
+li a7, 2
+ecall
+ret
+
+# receive_device_response
+.align 4
+li a7, 3
+ecall
+ret
+
+# send ipi
+.align 4
+li a7, 4
+ecall
+ret
+
+# clear ipi
+.align 4
+li a7, 5
+ecall
+ret
+
+# timebase
+.align 4
+li a0, 10000000 # temporary, we should provide the correct answer
+ret
+
+# shutdown
+.align 4
+li a7, 6
+ecall
+
+# set_timer
+.align 4
+li a7, 7
+ecall
+ret
+
+# end of SBI trampolines
 .=0x4000
 .stack:
 .align 8
@@ -59,7 +137,9 @@ _start:
 .align 3
 .stack_size:
 	.quad 0xf00
-
+.globl test_trap
+exception_handler:
+        call trap_handler
 reset:
 init_stack_loop:
 
diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h
index 8d7295d..f63f6e1 100644
--- a/src/arch/riscv/include/atomic.h
+++ b/src/arch/riscv/include/atomic.h
@@ -3,7 +3,6 @@
 #ifndef _RISCV_ATOMIC_H
 #define _RISCV_ATOMIC_H
 
-//#include "config.h"
 #include <arch/encoding.h>
 
 #define disable_irqsave() clear_csr(sstatus, SSTATUS_IE)
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc
index e60e0c1..87bc39a 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.inc
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc
@@ -14,9 +14,12 @@
 
 bootblock-y += bootblock.c
 bootblock-y += uart.c
+bootblock-y += qemu_util.c
 romstage-y += romstage.c
+romstage-y += qemu_util.c
 romstage-y += uart.c
 ramstage-y += uart.c
+ramstage-y += qemu_util.c
 
 bootblock-y += memlayout.ld
 romstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c
new file mode 100644
index 0000000..fca7d56
--- /dev/null
+++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2013, The Regents of the University of California (Regents).
+ * All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Regents nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+ * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+ * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+ * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+ */
+
+#include <spike_util.h>
+#include <arch/errno.h>
+#include <atomic.h>
+#include <string.h>
+#include <console/console.h>
+
+uintptr_t translate_address(uintptr_t vAddr) {
+	// TODO: implement the page table translation algorithm
+	//uintptr_t pageTableRoot = read_csr(sptbr);
+	uintptr_t physAddrMask = 0xfffffff;
+	uintptr_t translationResult = vAddr & physAddrMask;
+	printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n", vAddr, translationResult);
+	return translationResult;
+}
+
+uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p)
+{
+	uintptr_t physicalAddr = translate_address((uintptr_t) p);
+	memory_block_info *info = (memory_block_info*) physicalAddr;
+	if (id == 0) {
+		info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later
+		info->size = 0x7F000000 - info->base;
+		return 0;
+	}
+
+	return -1;
+}
+
+uintptr_t mcall_send_ipi(uintptr_t recipient)
+{
+	//if (recipient >= num_harts)
+	//return -1;
+
+	if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) {
+		mb();
+		write_csr(send_ipi, recipient);
+	}
+
+	return 0;
+}
+
+uintptr_t mcall_clear_ipi(void)
+{
+	// only clear SSIP if no other events are pending
+	if (HLS()->device_response_queue_head == NULL) {
+		clear_csr(mip, MIP_SSIP);
+		mb();
+	}
+
+	return atomic_swap(&HLS()->ipi_pending, 0);
+}
+
+uintptr_t mcall_shutdown(void)
+{
+	while (1) write_csr(mtohost, 1);
+	return 0;
+}
+
+uintptr_t mcall_set_timer(unsigned long long when)
+{
+	write_csr(mtimecmp, when);
+	clear_csr(mip, MIP_STIP);
+	set_csr(mie, MIP_MTIP);
+	return 0;
+}
+
+uintptr_t mcall_dev_req(sbi_device_message *m)
+{
+	if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL;
+
+	while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0);
+
+	m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head;
+	HLS()->device_request_queue_head = m;
+	HLS()->device_request_queue_size++;
+
+	return 0;
+}
+
+uintptr_t mcall_dev_resp(void)
+{
+	htif_interrupt(0, 0);
+
+	sbi_device_message* m = HLS()->device_response_queue_head;
+	if (m) {
+		//printm("resp %p\n", m);
+		sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data);
+		HLS()->device_response_queue_head = next;
+		if (!next) {
+			HLS()->device_response_queue_tail = 0;
+
+			// only clear SSIP if no other events are pending
+			clear_csr(mip, MIP_SSIP);
+			mb();
+			if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP);
+		}
+	}
+	return (uintptr_t)m;
+}
+
+uintptr_t mcall_hart_id(void)
+{
+	return HLS()->hart_id;
+}
+
+void hls_init(uint32_t hart_id)
+{
+	memset(HLS(), 0, sizeof(*HLS()));
+	HLS()->hart_id = hart_id;
+}
+
+uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) {
+	uintptr_t fromhost = swap_csr(mfromhost, 0);
+	if (!fromhost)
+	return 0;
+
+	uintptr_t dev = FROMHOST_DEV(fromhost);
+	uintptr_t cmd = FROMHOST_CMD(fromhost);
+	uintptr_t data = FROMHOST_DATA(fromhost);
+
+	sbi_device_message* m = HLS()->device_request_queue_head;
+	sbi_device_message* prev = 0x0;
+	unsigned long i, n;
+	for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) {
+		/*
+		if (!supervisor_paddr_valid(m, sizeof(*m))
+		&& EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M)
+		panic("htif: page fault");
+		*/
+
+		sbi_device_message* next = (void*)m->sbi_private_data;
+		if (m->dev == dev && m->cmd == cmd) {
+			m->data = data;
+
+			// dequeue from request queue
+			if (prev)
+			prev->sbi_private_data = (uintptr_t)next;
+			else
+			HLS()->device_request_queue_head = next;
+			HLS()->device_request_queue_size = n-1;
+			m->sbi_private_data = 0;
+
+			// enqueue to response queue
+			if (HLS()->device_response_queue_tail)
+			{
+				HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m;
+			}
+			else
+			{
+				HLS()->device_response_queue_head = m;
+			}
+			HLS()->device_response_queue_tail = m;
+
+			// signal software interrupt
+			set_csr(mip, MIP_SSIP);
+			return 0;
+		}
+
+		prev = m;
+		m = (void*)atomic_read(&m->sbi_private_data);
+	}
+	//HLT();
+	return 0;
+	//panic("htif: no record");
+}
+
+uintptr_t mcall_console_putchar(uint8_t ch)
+{
+	while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0);
+	while (1) {
+		uintptr_t fromhost = read_csr(mfromhost);
+		if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) {
+		if (fromhost)
+		htif_interrupt(0, 0);
+		continue;
+	}
+	write_csr(mfromhost, 0);
+	break;
+	}
+	return 0;
+}
+
+void testPrint(void) {
+	/* Print a test command to check Spike console output */
+	mcall_console_putchar('h');
+	mcall_console_putchar('e');
+	mcall_console_putchar('l');
+	mcall_console_putchar('l');
+	mcall_console_putchar('o');
+	mcall_console_putchar('\n');
+}
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index 8801f35..8e2e7ee 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -23,10 +23,10 @@
 
 SECTIONS
 {
-	DRAM_START(0x0)
+        DRAM_START(0x0)
 	BOOTBLOCK(0x0, 64K)
-	ROMSTAGE(0x20000, 128K)
-	STACK(0x40000, 0x3ff00)
-	PRERAM_CBMEM_CONSOLE(0x80000, 8K)
-	RAMSTAGE(0x100000, 16M)
+        STACK(8M, 64K)
+	ROMSTAGE(8M + 64K, 128K)
+	PRERAM_CBMEM_CONSOLE(8M + 192k, 8K)
+	RAMSTAGE(8M + 200K, 256K)
 }
diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c
index 9edc62d..fca7d56 100644
--- a/src/mainboard/emulation/spike-riscv/spike_util.c
+++ b/src/mainboard/emulation/spike-riscv/spike_util.c
@@ -32,187 +32,187 @@
 #include <console/console.h>
 
 uintptr_t translate_address(uintptr_t vAddr) {
-        // TODO: implement the page table translation algorithm
-        //uintptr_t pageTableRoot = read_csr(sptbr);
-        uintptr_t physAddrMask = 0xfffffff;
-        uintptr_t translationResult = vAddr & physAddrMask;
-        printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n", vAddr, translationResult);
-        return translationResult;
+	// TODO: implement the page table translation algorithm
+	//uintptr_t pageTableRoot = read_csr(sptbr);
+	uintptr_t physAddrMask = 0xfffffff;
+	uintptr_t translationResult = vAddr & physAddrMask;
+	printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n", vAddr, translationResult);
+	return translationResult;
 }
 
 uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p)
 {
-        uintptr_t physicalAddr = translate_address((uintptr_t) p);
-        memory_block_info *info = (memory_block_info*) physicalAddr;
-        if (id == 0) {
-                info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later
-                info->size = 0x7F000000 - info->base;
-                return 0;
-        }
-
-        return -1;
+	uintptr_t physicalAddr = translate_address((uintptr_t) p);
+	memory_block_info *info = (memory_block_info*) physicalAddr;
+	if (id == 0) {
+		info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later
+		info->size = 0x7F000000 - info->base;
+		return 0;
+	}
+
+	return -1;
 }
 
 uintptr_t mcall_send_ipi(uintptr_t recipient)
 {
-        //if (recipient >= num_harts)
-        //return -1;
+	//if (recipient >= num_harts)
+	//return -1;
 
-        if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) {
-                mb();
-                write_csr(send_ipi, recipient);
-        }
+	if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) {
+		mb();
+		write_csr(send_ipi, recipient);
+	}
 
-        return 0;
+	return 0;
 }
 
 uintptr_t mcall_clear_ipi(void)
 {
-        // only clear SSIP if no other events are pending
-        if (HLS()->device_response_queue_head == NULL) {
-                clear_csr(mip, MIP_SSIP);
-                mb();
-        }
+	// only clear SSIP if no other events are pending
+	if (HLS()->device_response_queue_head == NULL) {
+		clear_csr(mip, MIP_SSIP);
+		mb();
+	}
 
-        return atomic_swap(&HLS()->ipi_pending, 0);
+	return atomic_swap(&HLS()->ipi_pending, 0);
 }
 
 uintptr_t mcall_shutdown(void)
 {
-        while (1) write_csr(mtohost, 1);
-        return 0;
+	while (1) write_csr(mtohost, 1);
+	return 0;
 }
 
 uintptr_t mcall_set_timer(unsigned long long when)
 {
-        write_csr(mtimecmp, when);
-        clear_csr(mip, MIP_STIP);
-        set_csr(mie, MIP_MTIP);
-        return 0;
+	write_csr(mtimecmp, when);
+	clear_csr(mip, MIP_STIP);
+	set_csr(mie, MIP_MTIP);
+	return 0;
 }
 
 uintptr_t mcall_dev_req(sbi_device_message *m)
 {
-        if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL;
+	if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL;
 
-        while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0);
+	while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0);
 
-        m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head;
-        HLS()->device_request_queue_head = m;
-        HLS()->device_request_queue_size++;
+	m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head;
+	HLS()->device_request_queue_head = m;
+	HLS()->device_request_queue_size++;
 
-        return 0;
+	return 0;
 }
 
 uintptr_t mcall_dev_resp(void)
 {
-        htif_interrupt(0, 0);
-
-        sbi_device_message* m = HLS()->device_response_queue_head;
-        if (m) {
-                //printm("resp %p\n", m);
-                sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data);
-                HLS()->device_response_queue_head = next;
-                if (!next) {
-                        HLS()->device_response_queue_tail = 0;
-
-                        // only clear SSIP if no other events are pending
-                        clear_csr(mip, MIP_SSIP);
-                        mb();
-                        if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP);
-                }
-        }
-        return (uintptr_t)m;
+	htif_interrupt(0, 0);
+
+	sbi_device_message* m = HLS()->device_response_queue_head;
+	if (m) {
+		//printm("resp %p\n", m);
+		sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data);
+		HLS()->device_response_queue_head = next;
+		if (!next) {
+			HLS()->device_response_queue_tail = 0;
+
+			// only clear SSIP if no other events are pending
+			clear_csr(mip, MIP_SSIP);
+			mb();
+			if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP);
+		}
+	}
+	return (uintptr_t)m;
 }
 
 uintptr_t mcall_hart_id(void)
 {
-        return HLS()->hart_id;
+	return HLS()->hart_id;
 }
 
 void hls_init(uint32_t hart_id)
 {
-        memset(HLS(), 0, sizeof(*HLS()));
-        HLS()->hart_id = hart_id;
+	memset(HLS(), 0, sizeof(*HLS()));
+	HLS()->hart_id = hart_id;
 }
 
 uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) {
-        uintptr_t fromhost = swap_csr(mfromhost, 0);
-        if (!fromhost)
-        return 0;
-
-        uintptr_t dev = FROMHOST_DEV(fromhost);
-        uintptr_t cmd = FROMHOST_CMD(fromhost);
-        uintptr_t data = FROMHOST_DATA(fromhost);
-
-        sbi_device_message* m = HLS()->device_request_queue_head;
-        sbi_device_message* prev = 0x0;
-        unsigned long i, n;
-        for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) {
-                /*
-                if (!supervisor_paddr_valid(m, sizeof(*m))
-                && EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M)
-                panic("htif: page fault");
-                */
-
-                sbi_device_message* next = (void*)m->sbi_private_data;
-                if (m->dev == dev && m->cmd == cmd) {
-                        m->data = data;
-
-                        // dequeue from request queue
-                        if (prev)
-                        prev->sbi_private_data = (uintptr_t)next;
-                        else
-                        HLS()->device_request_queue_head = next;
-                        HLS()->device_request_queue_size = n-1;
-                        m->sbi_private_data = 0;
-
-                        // enqueue to response queue
-                        if (HLS()->device_response_queue_tail)
-                        {
-                                HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m;
-                        }
-                        else
-                        {
-                                HLS()->device_response_queue_head = m;
-                        }
-                        HLS()->device_response_queue_tail = m;
-
-                        // signal software interrupt
-                        set_csr(mip, MIP_SSIP);
-                        return 0;
-                }
-
-                prev = m;
-                m = (void*)atomic_read(&m->sbi_private_data);
-        }
-        //HLT();
-        return 0;
-        //panic("htif: no record");
+	uintptr_t fromhost = swap_csr(mfromhost, 0);
+	if (!fromhost)
+	return 0;
+
+	uintptr_t dev = FROMHOST_DEV(fromhost);
+	uintptr_t cmd = FROMHOST_CMD(fromhost);
+	uintptr_t data = FROMHOST_DATA(fromhost);
+
+	sbi_device_message* m = HLS()->device_request_queue_head;
+	sbi_device_message* prev = 0x0;
+	unsigned long i, n;
+	for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) {
+		/*
+		if (!supervisor_paddr_valid(m, sizeof(*m))
+		&& EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M)
+		panic("htif: page fault");
+		*/
+
+		sbi_device_message* next = (void*)m->sbi_private_data;
+		if (m->dev == dev && m->cmd == cmd) {
+			m->data = data;
+
+			// dequeue from request queue
+			if (prev)
+			prev->sbi_private_data = (uintptr_t)next;
+			else
+			HLS()->device_request_queue_head = next;
+			HLS()->device_request_queue_size = n-1;
+			m->sbi_private_data = 0;
+
+			// enqueue to response queue
+			if (HLS()->device_response_queue_tail)
+			{
+				HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m;
+			}
+			else
+			{
+				HLS()->device_response_queue_head = m;
+			}
+			HLS()->device_response_queue_tail = m;
+
+			// signal software interrupt
+			set_csr(mip, MIP_SSIP);
+			return 0;
+		}
+
+		prev = m;
+		m = (void*)atomic_read(&m->sbi_private_data);
+	}
+	//HLT();
+	return 0;
+	//panic("htif: no record");
 }
 
 uintptr_t mcall_console_putchar(uint8_t ch)
 {
-        while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0);
-        while (1) {
-                uintptr_t fromhost = read_csr(mfromhost);
-                if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) {
-                if (fromhost)
-                htif_interrupt(0, 0);
-                continue;
-        }
-        write_csr(mfromhost, 0);
-        break;
-        }
-        return 0;
+	while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0);
+	while (1) {
+		uintptr_t fromhost = read_csr(mfromhost);
+		if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) {
+		if (fromhost)
+		htif_interrupt(0, 0);
+		continue;
+	}
+	write_csr(mfromhost, 0);
+	break;
+	}
+	return 0;
 }
 
 void testPrint(void) {
-        /* Print a test command to check Spike console output */
-        mcall_console_putchar('h');
-        mcall_console_putchar('e');
-        mcall_console_putchar('l');
-        mcall_console_putchar('l');
-        mcall_console_putchar('o');
-        mcall_console_putchar('\n');
+	/* Print a test command to check Spike console output */
+	mcall_console_putchar('h');
+	mcall_console_putchar('e');
+	mcall_console_putchar('l');
+	mcall_console_putchar('l');
+	mcall_console_putchar('o');
+	mcall_console_putchar('\n');
 }


From gerrit at coreboot.org  Mon Sep 14 16:06:49 2015
From: gerrit at coreboot.org (Thaminda Edirisooriya (thaminda@google.com))
Date: Mon, 14 Sep 2015 16:06:49 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	riscv-trap-handling: Add functionality, prevent stack corruption
References: <I68ba3a114b7167b3212bb0bed181a7595f0b97d8+0@gerrit.coreboot.org>
Message-ID: <I68ba3a114b7167b3212bb0bed181a7595f0b97d8+2@gerrit.coreboot.org>

Thaminda Edirisooriya (thaminda at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11620

-gerrit

commit 3ef504cabb67721ab244bd7b440e8a5f3fb2c1ec
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Thu Sep 10 10:55:17 2015 -0700

    riscv-trap-handling: Add functionality, prevent stack corruption
    
    Trap handling code was bugged in that it loaded in the wrong stack
    pointer, overwriting the space the processor uses to talk to its host
    for doing device requests. Fix this issue, as well as add support for
    handling misaligned loads the same way we handle misaligned stores.
    
    Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
---
 src/arch/riscv/include/arch/exception.h |  2 +-
 src/arch/riscv/trap_handler.c           | 29 +++++++++++++++++++++++++++++
 src/arch/riscv/trap_util.S              |  2 +-
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h
index 4318cba..28b9279 100644
--- a/src/arch/riscv/include/arch/exception.h
+++ b/src/arch/riscv/include/arch/exception.h
@@ -55,7 +55,7 @@ static inline void exception_init(void)
 
 void trap_handler(trapframe* tf);
 void handle_supervisor_call(trapframe* tf);
-//void handleMisalignedLoad(trapframe *tf);
+void handleMisalignedLoad(trapframe *tf);
 void handle_misaligned_store(trapframe *tf);
 
 #endif
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index d4c9b87..6148037 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -162,6 +162,35 @@ void trap_handler(trapframe *tf) {
 	while(1);
 }
 
+void handleMisalignedLoad(trapframe *tf) {
+	printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
+	printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
+	insn_t faultingInstruction = 0;
+	uintptr_t faultingInstructionAddr = tf->epc;
+	asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr));
+	asm("lw t0, 0(t0)");
+	asm("move %0, t0" : "=r"(faultingInstruction));
+	printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
+	insn_t widthMask = 0x7000;
+	insn_t memWidth = (faultingInstruction & widthMask) >> 12;
+	insn_t destMask = 0xF80;
+	insn_t destRegister = (faultingInstruction & destMask) >> 7;
+	printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth);
+	if (memWidth == 3) {
+		// load double, handle the issue
+		void* badAddress = (void*) tf->badvaddr;
+		memcpy(&(tf->gpr[destRegister]), badAddress, 8);
+	} else {
+		// panic, this should not have happened
+		printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n");
+		while(1);
+	}
+
+	// return to where we came from
+	write_csr(mepc, read_csr(mepc) + 4);
+	asm volatile("j machine_call_return");
+}
+
 void handle_misaligned_store(trapframe *tf) {
 	printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
 	printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 9701aaf..274dca6 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -112,7 +112,7 @@
 supervisor_trap_entry:
     csrw mscratch, sp
     # load in the top of the machine stack
-    la sp, 0x80FFF0
+    la sp, 0x80FFF0 - 64
     1:addi sp,sp,-320
     save_tf
     move  a0,sp


From gerrit at coreboot.org  Mon Sep 14 16:06:52 2015
From: gerrit at coreboot.org (Thaminda Edirisooriya (thaminda@google.com))
Date: Mon, 14 Sep 2015 16:06:52 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	riscv-virtual-memory: move page tables into virtual address space
References: <I1d99e46f38a38a163fb1c7c517b1abca80cde0dc+0@gerrit.coreboot.org>
Message-ID: <I1d99e46f38a38a163fb1c7c517b1abca80cde0dc+2@gerrit.coreboot.org>

Thaminda Edirisooriya (thaminda at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11621

-gerrit

commit 6ebf1df7f7c44f38fb53c0754c4b4ff0145fca93
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Thu Sep 10 10:58:58 2015 -0700

    riscv-virtual-memory: move page tables into virtual address space
    
    If we use a linux payload/any payload that wants to manage virtual
    memory, and the payload is a supervisor (thus requiring virtual
    addressing before being started), we need to make sure that the page
    table is mapped into the virtual address space. Move the start address
    of the tables so the payload can manage virtual memory.
    
    Change-Id: I1d99e46f38a38a163fb1c7c517b1abca80cde0dc
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
---
 src/arch/riscv/virtual_memory.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 2095bfa..0163a45 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -107,7 +107,7 @@ void initVirtualMemory(void) {
 	printk(BIOS_DEBUG, "Initializing virtual memory...\n");
 	uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs
 	uintptr_t virtualStart = 0xffffffff81000000;
-	uintptr_t pageTableStart = 0x1f0000;
+	uintptr_t pageTableStart = 0x1400000;
 	init_vm(virtualStart, physicalStart, pageTableStart);
 	mb();
 	printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n");


From gerrit at coreboot.org  Mon Sep 14 16:27:39 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 14 Sep 2015 16:27:39 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool: drop
	extra copy of filetype->string map
References: <I08e478b92f3316139f14294e50ede657c7d5fb01+0@gerrit.coreboot.org>
Message-ID: <E1ZbWbT-00006P-Ih@mail.coreboot.org>

the following patch was just integrated into master:
commit dc37dab7fda215b996867eff5c4511b09f7aa37a
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 9 16:46:00 2015 +0200

    cbfstool: drop extra copy of filetype->string map
    
    We had two mappings of filetype IDs to strings. We shouldn't.
    
    Change-Id: I08e478b92f3316139f14294e50ede657c7d5fb01
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11626
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11626 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 14 16:47:03 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 14 Sep 2015 16:47:03 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: WIP: ifdtool:
	Do proper ser/deser of descriptor
References: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+0@gerrit.coreboot.org>
Message-ID: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11635

-gerrit

commit 833da426447c0b2d9aff299143f6cfd9459e8a08
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 14 09:47:24 2015 -0700

    WIP: ifdtool: Do proper ser/deser of descriptor
    
    Change-Id: Iccc063d08beb2fcafe9af910a0b1b984fcbc134f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/ifdtool/Makefile      |  2 +-
 util/ifdtool/ifd_drv_bin.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++
 util/ifdtool/ifdtool.c     | 56 +++++++++++++++++++++----------
 util/ifdtool/ifdtool.h     | 22 +++++++++++++
 4 files changed, 143 insertions(+), 19 deletions(-)

diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
index 02a02c4..ac43293 100644
--- a/util/ifdtool/Makefile
+++ b/util/ifdtool/Makefile
@@ -25,7 +25,7 @@ PREFIX  = /usr/local
 CFLAGS  = -O2 -g -Wall -W -Werror
 LDFLAGS =
 
-OBJS = ifdtool.o
+OBJS = ifdtool.o ifd_drv_bin.o
 
 all: dep $(PROGRAM)
 
diff --git a/util/ifdtool/ifd_drv_bin.c b/util/ifdtool/ifd_drv_bin.c
new file mode 100644
index 0000000..146475a
--- /dev/null
+++ b/util/ifdtool/ifd_drv_bin.c
@@ -0,0 +1,82 @@
+
+#include "ifdtool.h"
+#include "helpers.h"
+
+#include <stdlib.h>
+
+static void des_flmap0(struct flash_descriptor *desc, uint32_t flmap0)
+{
+	desc->num_regions = (flmap0 >> 24) & 7;
+	desc->frba_offset = ((flmap0 >> 16) & 0xff) << 4;
+	desc->num_components = ((flmap0 >> 8) & 0x3) + 1;
+	desc->fcba_offset = ((flmap0 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap0(const struct flash_descriptor *desc)
+{
+	uint32_t flmap0;
+
+	flmap0 = (desc->num_regions & 0x7) << 24;
+	flmap0 |= ((desc->frba_offset >> 4) & 0xff)  << 16;
+	flmap0 |= ((desc->num_components - 1) & 0x3) << 8;
+	flmap0 |= ((desc->fcba_offset >> 4) & 0xff) << 0;
+
+	return flmap0;
+}
+
+static void des_flmap1(struct flash_descriptor *desc, uint32_t flmap1)
+{
+	desc->num_pch_straps = (flmap1 >> 24) & 0xff;
+	desc->fpsba_offset = ((flmap1 >> 16) & 0xff) << 4;
+	desc->num_masters = (flmap1 >> 8) & 3;
+	desc->fmba_offset = ((flmap1 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap1(const struct flash_descriptor *desc)
+{
+	uint32_t flmap1;
+
+	flmap1 = (desc->num_pch_straps & 0xff) << 24;
+	flmap1 |= ((desc->fpsba_offset >> 4) & 0xff)  << 16;
+	flmap1 |= (desc->num_masters & 0x3) << 8;
+	flmap1 |= ((desc->fmba_offset >> 4) & 0xff) << 0;
+
+	return flmap1;
+}
+
+static void des_flmap2(struct flash_descriptor *desc, uint32_t flmap2)
+{
+	desc->iccriba_offset = ((flmap2 >> 16) & 0xff) << 4;
+	desc->num_pch_straps = (flmap2 >> 8) & 0xff;
+	desc->fmsba_offset = ((flmap2 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap2(const struct flash_descriptor *desc)
+{
+	uint32_t flmap2;
+
+	flmap2 = ((desc->iccriba_offset >> 4) & 0xff)  << 16;
+	flmap2 |= (desc->num_pch_straps & 0x3) << 8;
+	flmap2 |= ((desc->fmsba_offset >> 4) & 0xff) << 0;
+
+	return flmap2;
+}
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud)
+{
+	const uint8_t *ifd_regs = fud;
+
+	des_flmap0(desc, read_le32(ifd_regs + 0x04));
+	des_flmap1(desc, read_le32(ifd_regs + 0x08));
+	des_flmap2(desc, read_le32(ifd_regs + 0x0C));
+}
+
+void dont_compile_fail_me(void)
+{
+	des_flmap0(NULL, 0);
+	ser_flmap0(NULL);
+	des_flmap1(NULL, 0);
+	ser_flmap1(NULL);
+	des_flmap2(NULL, 0);
+	ser_flmap2(NULL);
+}
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index e6ed110..7b59ada 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -18,6 +18,7 @@
  */
 
 #include <unistd.h>
+#include <stdbool.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -25,6 +26,8 @@
 #include <fcntl.h>
 #include <sys/types.h>
 #include <sys/stat.h>
+
+#include "helpers.h"
 #include "ifdtool.h"
 
 #ifndef O_BINARY
@@ -33,7 +36,7 @@
 
 static int ifd_version;
 
-static const struct region_name region_names[MAX_REGIONS] = {
+static const struct region_name region_names_old_yester_years[9] = {
 	{ "Flash Descriptor", "fd" },
 	{ "BIOS", "bios" },
 	{ "Intel ME", "me" },
@@ -45,15 +48,29 @@ static const struct region_name region_names[MAX_REGIONS] = {
 	{ "EC", "ec" },
 };
 
-static fdbar_t *find_fd(char *image, int size)
+static const struct region_name region_names[9] = {
+	{ "Flash Descriptor", "fd" },
+	{ "IFWI", "bios" },
+	{ "TXE", "me" },
+	{ "Platform Data", "pd" },
+	{ "Device Expansion", "bs0" },
+	{ "Reserved", "res1" },
+	{ "Reserved", "res2" },
+	{ "Reserved", "res3" },
+	{ "Reserved", "res4" },
+};
+
+static void *find_fd(void *image, size_t size)
 {
-	int i, found = 0;
+	size_t i;
+	bool found = false;
+	uint8_t *base = image;
 
 	/* Scan for FD signature */
 	for (i = 0; i < (size - 4); i += 4) {
-		if (*(uint32_t *) (image + i) == 0x0FF0A55A) {
-			found = 1;
-			break;	// signature found.
+		if (read_le32(base + i) == 0x0FF0A55A) {
+			found = true;
+			break;	/* signature found. */
 		}
 	}
 
@@ -62,7 +79,7 @@ static fdbar_t *find_fd(char *image, int size)
 		return NULL;
 	}
 
-	return (fdbar_t *) (image + i);
+	return base + i;
 }
 
 /*
@@ -221,7 +238,7 @@ static int region_num(const char *name)
 
 static const char *region_filename(int region_type)
 {
-	static const char *region_filenames[MAX_REGIONS] = {
+	static const char *region_filenames[9] = {
 		"flashregion_0_flashdescriptor.bin",
 		"flashregion_1_bios.bin",
 		"flashregion_2_intel_me.bin",
@@ -590,25 +607,28 @@ static void dump_oem(uint8_t *oem)
 
 static void dump_fd(char *image, int size)
 {
+	struct flash_descriptor desc;
 	fdbar_t *fdb = find_fd(image, size);
 	if (!fdb)
 		exit(EXIT_FAILURE);
 
+	read_flash_descriptor(&desc,fdb);
+
 	printf("FLMAP0:    0x%08x\n", fdb->flmap0);
-	printf("  NR:      %d\n", (fdb->flmap0 >> 24) & 7);
-	printf("  FRBA:    0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
-	printf("  NC:      %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
-	printf("  FCBA:    0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+	printf("  NR:      %d\n", desc.num_regions);
+	printf("  FRBA:    0x%x\n", desc.frba_offset);
+	printf("  NC:      %d\n", desc.num_components);
+	printf("  FCBA:    0x%x\n", desc.fcba_offset);
 
 	printf("FLMAP1:    0x%08x\n", fdb->flmap1);
-	printf("  ISL:     0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
-	printf("  FPSBA:   0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
-	printf("  NM:      %d\n", (fdb->flmap1 >> 8) & 3);
-	printf("  FMBA:    0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+	printf("  ISL:     0x%02x\n", desc.num_pch_straps);
+	printf("  FPSBA:   0x%x\n", desc.fpsba_offset);
+	printf("  NM:      %d\n", desc.num_masters);
+	printf("  FMBA:    0x%x\n", desc.fmba_offset);
 
 	printf("FLMAP2:    0x%08x\n", fdb->flmap2);
-	printf("  PSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
-	printf("  FMSBA:   0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+	printf("  PSL:     0x%04x\n", desc.num_cpu_straps);
+	printf("  FMSBA:   0x%x\n", desc.fmsba_offset);
 
 	printf("FLUMAP1:   0x%08x\n", fdb->flumap1);
 	printf("  Intel ME VSCC Table Length (VTL):        %d\n",
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index 8b13283..8a222e5 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -134,3 +134,25 @@ struct region_name {
 	char *pretty;
 	char *terse;
 };
+
+struct flash_descriptor
+{
+	/* FLMAP0 */
+	uint8_t num_regions;
+	uint16_t frba_offset;
+	uint8_t num_components;
+	uint16_t fcba_offset;
+
+	/* FLMAP1 */
+	uint8_t num_pch_straps;
+	uint16_t fpsba_offset;
+	uint8_t num_masters;
+	uint16_t fmba_offset;
+
+	/* FLMAP2 */
+	uint16_t iccriba_offset;
+	uint8_t num_cpu_straps;
+	uint16_t fmsba_offset;
+};
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud);


From gerrit at coreboot.org  Mon Sep 14 16:58:18 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 14 Sep 2015 16:58:18 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: WIP: ifdtool: Do
	proper ser/deser of descriptor
References: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+0@gerrit.coreboot.org>
Message-ID: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+2@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11635

-gerrit

commit 22815cbe3ae54889f8f6fef84e46d0fcfaf35c9b
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 14 09:47:24 2015 -0700

    WIP: ifdtool: Do proper ser/deser of descriptor
    
    Change-Id: Iccc063d08beb2fcafe9af910a0b1b984fcbc134f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/ifdtool/Makefile      |  2 +-
 util/ifdtool/helpers.h     | 29 ++++++++++++++++
 util/ifdtool/ifd_drv_bin.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++
 util/ifdtool/ifdtool.c     | 56 +++++++++++++++++++++----------
 util/ifdtool/ifdtool.h     | 22 +++++++++++++
 5 files changed, 172 insertions(+), 19 deletions(-)

diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
index 02a02c4..ac43293 100644
--- a/util/ifdtool/Makefile
+++ b/util/ifdtool/Makefile
@@ -25,7 +25,7 @@ PREFIX  = /usr/local
 CFLAGS  = -O2 -g -Wall -W -Werror
 LDFLAGS =
 
-OBJS = ifdtool.o
+OBJS = ifdtool.o ifd_drv_bin.o
 
 all: dep $(PROGRAM)
 
diff --git a/util/ifdtool/helpers.h b/util/ifdtool/helpers.h
new file mode 100644
index 0000000..c0b067c
--- /dev/null
+++ b/util/ifdtool/helpers.h
@@ -0,0 +1,29 @@
+#include <stdint.h>
+
+inline static uint16_t read_le16(const void *src)
+{
+	const uint8_t *b = src;
+	return ((b[1] << 8) | (b[0] << 0));
+};
+
+inline static uint32_t read_le32(const void *src)
+{
+	const uint8_t *b = src;
+	return ((b[3] << 24) | (b[2] << 16) | (b[1] << 8) | (b[0] << 0));
+};
+
+inline static void put_le16(void *dest, uint16_t val16)
+{
+	uint8_t *b = dest;
+	b[0] = (val16 >> 0) & 0xff;
+	b[1] = (val16 >> 8) & 0xff;
+};
+
+inline static void put_le32(void *dest, uint32_t val32)
+{
+	uint8_t *b = dest;
+	b[0] = (val32 >> 0) & 0xff;
+	b[1] = (val32 >> 8) & 0xff;
+	b[2] = (val32 >> 16) & 0xff;
+	b[3] = (val32 >> 24) & 0xff;
+};
diff --git a/util/ifdtool/ifd_drv_bin.c b/util/ifdtool/ifd_drv_bin.c
new file mode 100644
index 0000000..146475a
--- /dev/null
+++ b/util/ifdtool/ifd_drv_bin.c
@@ -0,0 +1,82 @@
+
+#include "ifdtool.h"
+#include "helpers.h"
+
+#include <stdlib.h>
+
+static void des_flmap0(struct flash_descriptor *desc, uint32_t flmap0)
+{
+	desc->num_regions = (flmap0 >> 24) & 7;
+	desc->frba_offset = ((flmap0 >> 16) & 0xff) << 4;
+	desc->num_components = ((flmap0 >> 8) & 0x3) + 1;
+	desc->fcba_offset = ((flmap0 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap0(const struct flash_descriptor *desc)
+{
+	uint32_t flmap0;
+
+	flmap0 = (desc->num_regions & 0x7) << 24;
+	flmap0 |= ((desc->frba_offset >> 4) & 0xff)  << 16;
+	flmap0 |= ((desc->num_components - 1) & 0x3) << 8;
+	flmap0 |= ((desc->fcba_offset >> 4) & 0xff) << 0;
+
+	return flmap0;
+}
+
+static void des_flmap1(struct flash_descriptor *desc, uint32_t flmap1)
+{
+	desc->num_pch_straps = (flmap1 >> 24) & 0xff;
+	desc->fpsba_offset = ((flmap1 >> 16) & 0xff) << 4;
+	desc->num_masters = (flmap1 >> 8) & 3;
+	desc->fmba_offset = ((flmap1 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap1(const struct flash_descriptor *desc)
+{
+	uint32_t flmap1;
+
+	flmap1 = (desc->num_pch_straps & 0xff) << 24;
+	flmap1 |= ((desc->fpsba_offset >> 4) & 0xff)  << 16;
+	flmap1 |= (desc->num_masters & 0x3) << 8;
+	flmap1 |= ((desc->fmba_offset >> 4) & 0xff) << 0;
+
+	return flmap1;
+}
+
+static void des_flmap2(struct flash_descriptor *desc, uint32_t flmap2)
+{
+	desc->iccriba_offset = ((flmap2 >> 16) & 0xff) << 4;
+	desc->num_pch_straps = (flmap2 >> 8) & 0xff;
+	desc->fmsba_offset = ((flmap2 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap2(const struct flash_descriptor *desc)
+{
+	uint32_t flmap2;
+
+	flmap2 = ((desc->iccriba_offset >> 4) & 0xff)  << 16;
+	flmap2 |= (desc->num_pch_straps & 0x3) << 8;
+	flmap2 |= ((desc->fmsba_offset >> 4) & 0xff) << 0;
+
+	return flmap2;
+}
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud)
+{
+	const uint8_t *ifd_regs = fud;
+
+	des_flmap0(desc, read_le32(ifd_regs + 0x04));
+	des_flmap1(desc, read_le32(ifd_regs + 0x08));
+	des_flmap2(desc, read_le32(ifd_regs + 0x0C));
+}
+
+void dont_compile_fail_me(void)
+{
+	des_flmap0(NULL, 0);
+	ser_flmap0(NULL);
+	des_flmap1(NULL, 0);
+	ser_flmap1(NULL);
+	des_flmap2(NULL, 0);
+	ser_flmap2(NULL);
+}
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index e6ed110..7b59ada 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -18,6 +18,7 @@
  */
 
 #include <unistd.h>
+#include <stdbool.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -25,6 +26,8 @@
 #include <fcntl.h>
 #include <sys/types.h>
 #include <sys/stat.h>
+
+#include "helpers.h"
 #include "ifdtool.h"
 
 #ifndef O_BINARY
@@ -33,7 +36,7 @@
 
 static int ifd_version;
 
-static const struct region_name region_names[MAX_REGIONS] = {
+static const struct region_name region_names_old_yester_years[9] = {
 	{ "Flash Descriptor", "fd" },
 	{ "BIOS", "bios" },
 	{ "Intel ME", "me" },
@@ -45,15 +48,29 @@ static const struct region_name region_names[MAX_REGIONS] = {
 	{ "EC", "ec" },
 };
 
-static fdbar_t *find_fd(char *image, int size)
+static const struct region_name region_names[9] = {
+	{ "Flash Descriptor", "fd" },
+	{ "IFWI", "bios" },
+	{ "TXE", "me" },
+	{ "Platform Data", "pd" },
+	{ "Device Expansion", "bs0" },
+	{ "Reserved", "res1" },
+	{ "Reserved", "res2" },
+	{ "Reserved", "res3" },
+	{ "Reserved", "res4" },
+};
+
+static void *find_fd(void *image, size_t size)
 {
-	int i, found = 0;
+	size_t i;
+	bool found = false;
+	uint8_t *base = image;
 
 	/* Scan for FD signature */
 	for (i = 0; i < (size - 4); i += 4) {
-		if (*(uint32_t *) (image + i) == 0x0FF0A55A) {
-			found = 1;
-			break;	// signature found.
+		if (read_le32(base + i) == 0x0FF0A55A) {
+			found = true;
+			break;	/* signature found. */
 		}
 	}
 
@@ -62,7 +79,7 @@ static fdbar_t *find_fd(char *image, int size)
 		return NULL;
 	}
 
-	return (fdbar_t *) (image + i);
+	return base + i;
 }
 
 /*
@@ -221,7 +238,7 @@ static int region_num(const char *name)
 
 static const char *region_filename(int region_type)
 {
-	static const char *region_filenames[MAX_REGIONS] = {
+	static const char *region_filenames[9] = {
 		"flashregion_0_flashdescriptor.bin",
 		"flashregion_1_bios.bin",
 		"flashregion_2_intel_me.bin",
@@ -590,25 +607,28 @@ static void dump_oem(uint8_t *oem)
 
 static void dump_fd(char *image, int size)
 {
+	struct flash_descriptor desc;
 	fdbar_t *fdb = find_fd(image, size);
 	if (!fdb)
 		exit(EXIT_FAILURE);
 
+	read_flash_descriptor(&desc,fdb);
+
 	printf("FLMAP0:    0x%08x\n", fdb->flmap0);
-	printf("  NR:      %d\n", (fdb->flmap0 >> 24) & 7);
-	printf("  FRBA:    0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
-	printf("  NC:      %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
-	printf("  FCBA:    0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+	printf("  NR:      %d\n", desc.num_regions);
+	printf("  FRBA:    0x%x\n", desc.frba_offset);
+	printf("  NC:      %d\n", desc.num_components);
+	printf("  FCBA:    0x%x\n", desc.fcba_offset);
 
 	printf("FLMAP1:    0x%08x\n", fdb->flmap1);
-	printf("  ISL:     0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
-	printf("  FPSBA:   0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
-	printf("  NM:      %d\n", (fdb->flmap1 >> 8) & 3);
-	printf("  FMBA:    0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+	printf("  ISL:     0x%02x\n", desc.num_pch_straps);
+	printf("  FPSBA:   0x%x\n", desc.fpsba_offset);
+	printf("  NM:      %d\n", desc.num_masters);
+	printf("  FMBA:    0x%x\n", desc.fmba_offset);
 
 	printf("FLMAP2:    0x%08x\n", fdb->flmap2);
-	printf("  PSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
-	printf("  FMSBA:   0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+	printf("  PSL:     0x%04x\n", desc.num_cpu_straps);
+	printf("  FMSBA:   0x%x\n", desc.fmsba_offset);
 
 	printf("FLUMAP1:   0x%08x\n", fdb->flumap1);
 	printf("  Intel ME VSCC Table Length (VTL):        %d\n",
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index 8b13283..8a222e5 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -134,3 +134,25 @@ struct region_name {
 	char *pretty;
 	char *terse;
 };
+
+struct flash_descriptor
+{
+	/* FLMAP0 */
+	uint8_t num_regions;
+	uint16_t frba_offset;
+	uint8_t num_components;
+	uint16_t fcba_offset;
+
+	/* FLMAP1 */
+	uint8_t num_pch_straps;
+	uint16_t fpsba_offset;
+	uint8_t num_masters;
+	uint16_t fmba_offset;
+
+	/* FLMAP2 */
+	uint16_t iccriba_offset;
+	uint8_t num_cpu_straps;
+	uint16_t fmsba_offset;
+};
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud);


From gerrit at coreboot.org  Mon Sep 14 17:23:29 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 14 Sep 2015 17:23:29 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: qemu:
	initialize lapic
References: <I022f3742475d3f3477fc838b1e2bce69287b6b8e+0@gerrit.coreboot.org>
Message-ID: <E1ZbXTV-000102-ED@mail.coreboot.org>

the following patch was just integrated into master:
commit 59598b2e475b50e359c821e35fe1ab60dfce641e
Author: Gerd Hoffmann <kraxel at redhat.com>
Date:   Thu Sep 10 10:58:52 2015 +0200

    qemu: initialize lapic
    
    Recently qemu stopped doing a basic lapic setup and expects the
    firmware to handle this properly (like on real hardware).  So
    let's do that so coreboot works properly on qemu 2.4+.
    
    Here is the qemu commit message for the change:
    
    <quote>
      commit b8eb5512fd8a115f164edbbe897cdf8884920ccb
      Author: Nadav Amit <namit at cs.technion.ac.il>
      Date:   Mon Apr 13 02:32:08 2015 +0300
    
      target-i386: disable LINT0 after reset
    
      Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone
      and therefore this hack is no longer needed.  Since it violates the
      specifications, it is removed.
    
      Signed-off-by: Nadav Amit <namit at cs.technion.ac.il>
      Message-Id: <1428881529-29459-2-git-send-email-namit at cs.technion.ac.il>
      Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
    </quote>
    
    Change-Id: I022f3742475d3f3477fc838b1e2bce69287b6b8e
    Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
    Reviewed-on: http://review.coreboot.org/11611
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11611 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 14 17:49:02 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 14 Sep 2015 17:49:02 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Don't use
	fileno() to get file size
References: <I5be62a731f928333ea2e5843d81f541453fdb396+0@gerrit.coreboot.org>
Message-ID: <I5be62a731f928333ea2e5843d81f541453fdb396+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11636

-gerrit

commit 029438246a669e6327e6452fe385c067e8c863ca
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Sep 14 10:46:44 2015 -0700

    Don't use fileno() to get file size
    
    fileno() is a mess on some operating systems. Don't
    deliberately convert between FILE * and file handles.
    
    Change-Id: I5be62a731f928333ea2e5843d81f541453fdb396
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 util/cbfstool/common.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index f8ce2f9..44e40a9 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -46,14 +46,13 @@ int is_big_endian(void)
 
 static off_t get_file_size(FILE *f)
 {
-	struct stat s;
-	int fd = fileno(f);
-	if (fd == -1) return -1;
-	if (fstat(fd, &s) == -1) return -1;
-	return s.st_size;
+	off_t fsize;
+	fseek(f, 0, SEEK_END);
+	fsize = ftell(f);
+	fseek(f, 0, SEEK_SET);
 }
-/* Buffer and file I/O */
 
+/* Buffer and file I/O */
 int buffer_create(struct buffer *buffer, size_t size, const char *name)
 {
 	buffer->name = strdup(name);


From gerrit at coreboot.org  Mon Sep 14 18:02:26 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 14 Sep 2015 18:02:26 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Don't use
	fileno() to get file size
References: <I5be62a731f928333ea2e5843d81f541453fdb396+0@gerrit.coreboot.org>
Message-ID: <I5be62a731f928333ea2e5843d81f541453fdb396+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11636

-gerrit

commit 2fac589bd6795cfdd714bd0a9c1d0993107d578f
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Sep 14 10:46:44 2015 -0700

    Don't use fileno() to get file size
    
    fileno() is a mess on some operating systems. Don't
    deliberately convert between FILE * and file handles.
    
    Change-Id: I5be62a731f928333ea2e5843d81f541453fdb396
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 util/cbfstool/common.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index f8ce2f9..e0474b3 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -46,14 +46,14 @@ int is_big_endian(void)
 
 static off_t get_file_size(FILE *f)
 {
-	struct stat s;
-	int fd = fileno(f);
-	if (fd == -1) return -1;
-	if (fstat(fd, &s) == -1) return -1;
-	return s.st_size;
+	off_t fsize;
+	fseek(f, 0, SEEK_END);
+	fsize = ftell(f);
+	fseek(f, 0, SEEK_SET);
+	return fsize;
 }
-/* Buffer and file I/O */
 
+/* Buffer and file I/O */
 int buffer_create(struct buffer *buffer, size_t size, const char *name)
 {
 	buffer->name = strdup(name);


From gerrit at coreboot.org  Mon Sep 14 18:02:27 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 14 Sep 2015 18:02:27 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: fmd: Use
	_fileno() on MINGW
References: <If1e5f0b6834fb5b9b2b3dfbaf0ce36c46661907c+0@gerrit.coreboot.org>
Message-ID: <If1e5f0b6834fb5b9b2b3dfbaf0ce36c46661907c+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11637

-gerrit

commit 71589f7dbf1b4d280e4f55a8b0051111070d247b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Sep 14 11:01:12 2015 -0700

    fmd: Use _fileno() on MINGW
    
    fileno() is not available on non-Posix systems (like MINGW),
    so use the Windows specific _fileno() in those cases.
    
    Change-Id: If1e5f0b6834fb5b9b2b3dfbaf0ce36c46661907c
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 util/cbfstool/fmd_scanner.c_shipped | 32 ++++++++++++++++++--------------
 util/cbfstool/fmd_scanner.l         |  4 ++++
 2 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/util/cbfstool/fmd_scanner.c_shipped b/util/cbfstool/fmd_scanner.c_shipped
index b22011d..a414bf1 100644
--- a/util/cbfstool/fmd_scanner.c_shipped
+++ b/util/cbfstool/fmd_scanner.c_shipped
@@ -496,9 +496,13 @@ char *yytext;
 #include <assert.h>
 #include <string.h>
 
+#ifdef __MINGW32__
+#define fileno(x) _fileno(x)
+#endif
+
 int parse_integer(char *src, int base);
 int copy_string(const char *src);
-#line 502 "<stdout>"
+#line 506 "<stdout>"
 
 #define INITIAL 0
 
@@ -712,10 +716,10 @@ YY_DECL
 		}
 
 	{
-#line 34 "fmd_scanner.l"
+#line 38 "fmd_scanner.l"
 
 
-#line 719 "<stdout>"
+#line 723 "<stdout>"
 
 	while ( 1 )		/* loops until end-of-file is reached */
 		{
@@ -775,7 +779,7 @@ do_action:	/* This label is used only to access EOF actions. */
 case 1:
 /* rule 1 can match eol */
 YY_RULE_SETUP
-#line 36 "fmd_scanner.l"
+#line 40 "fmd_scanner.l"
 /* Eat whitespace. */
 	YY_BREAK
 case 2:
@@ -783,42 +787,42 @@ case 2:
 (yy_c_buf_p) = yy_cp -= 1;
 YY_DO_BEFORE_ACTION; /* set up yytext again */
 YY_RULE_SETUP
-#line 37 "fmd_scanner.l"
+#line 41 "fmd_scanner.l"
 /* Eat comments. */
 	YY_BREAK
 case 3:
-#line 39 "fmd_scanner.l"
+#line 43 "fmd_scanner.l"
 case 4:
 YY_RULE_SETUP
-#line 39 "fmd_scanner.l"
+#line 43 "fmd_scanner.l"
 return parse_integer(yytext, 10);
 	YY_BREAK
 case 5:
 YY_RULE_SETUP
-#line 40 "fmd_scanner.l"
+#line 44 "fmd_scanner.l"
 return OCTAL;
 	YY_BREAK
 case 6:
 YY_RULE_SETUP
-#line 41 "fmd_scanner.l"
+#line 45 "fmd_scanner.l"
 return parse_integer(yytext + 2, 16);
 	YY_BREAK
 case 7:
 YY_RULE_SETUP
-#line 42 "fmd_scanner.l"
+#line 46 "fmd_scanner.l"
 return copy_string(yytext);
 	YY_BREAK
 case 8:
 YY_RULE_SETUP
-#line 43 "fmd_scanner.l"
+#line 47 "fmd_scanner.l"
 return *yytext;
 	YY_BREAK
 case 9:
 YY_RULE_SETUP
-#line 45 "fmd_scanner.l"
+#line 49 "fmd_scanner.l"
 ECHO;
 	YY_BREAK
-#line 822 "<stdout>"
+#line 826 "<stdout>"
 case YY_STATE_EOF(INITIAL):
 	yyterminate();
 
@@ -1813,7 +1817,7 @@ void yyfree (void * ptr )
 
 #define YYTABLES_NAME "yytables"
 
-#line 44 "fmd_scanner.l"
+#line 48 "fmd_scanner.l"
 
 
 
diff --git a/util/cbfstool/fmd_scanner.l b/util/cbfstool/fmd_scanner.l
index 439548e..13e1df1 100644
--- a/util/cbfstool/fmd_scanner.l
+++ b/util/cbfstool/fmd_scanner.l
@@ -23,6 +23,10 @@
 #include <assert.h>
 #include <string.h>
 
+#ifdef __MINGW32__
+#define fileno(x) _fileno(x)
+#endif
+
 int parse_integer(char *src, int base);
 int copy_string(const char *src);
 %}


From gerrit at coreboot.org  Tue Sep 15 06:45:09 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Tue, 15 Sep 2015 06:45:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: buildgcc: Add
	patch for building binutils by clang 6.0
References: <I0f014b776e86e6d0cbebd560cb17f469f31e1dfb+0@gerrit.coreboot.org>
Message-ID: <I0f014b776e86e6d0cbebd560cb17f469f31e1dfb+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11638

-gerrit

commit a426d9563d2a2d02a9de1ce08ce3d41a1f79ceda
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 15 02:38:40 2015 -0400

    buildgcc: Add patch for building binutils by clang 6.0
    
    Clang is the default compiler on BSD and OS X. With this
    change. We don't have to install gcc any more.
    This is a known issue on GNU mail list. Please refer
    the link below.
    https://sourceware.org/bugzilla/show_bug.cgi?id=17473
    
    Change-Id: I0f014b776e86e6d0cbebd560cb17f469f31e1dfb
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/patches/binutils-2.25_host-clang.patch | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/util/crossgcc/patches/binutils-2.25_host-clang.patch b/util/crossgcc/patches/binutils-2.25_host-clang.patch
new file mode 100644
index 0000000..747587a
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.25_host-clang.patch
@@ -0,0 +1,14 @@
+--- binutils-2.25/gold/binary.cc	2014-10-14 00:32:04.000000000 -0700
++++ binutils-2.25.patched/gold/binary.cc	2015-09-15 07:02:40.000000000 -0700
+@@ -24,10 +24,10 @@
+ 
+ #include <cerrno>
+ #include <cstring>
++#include "stringpool.h"
+ #include "safe-ctype.h"
+ 
+ #include "elfcpp.h"
+-#include "stringpool.h"
+ #include "fileread.h"
+ #include "output.h"
+ #include "binary.h"


From gerrit at coreboot.org  Tue Sep 15 06:45:11 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Tue, 15 Sep 2015 06:45:11 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: buildgcc: Fix
	the binutils-no-doc patch with 2.25
References: <Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab+0@gerrit.coreboot.org>
Message-ID: <Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11639

-gerrit

commit c0049495997bc9c075f00ed567c68b52cfc3258f
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 15 02:43:01 2015 -0400

    buildgcc: Fix the binutils-no-doc patch with 2.25
    
    The binutils-2.25 has added some new line, making the hunk
    move downward a little. Remake the patch.
    
    Change-Id: Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
index 317c2b4..5ad70da 100644
--- a/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
+++ b/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
@@ -1,8 +1,8 @@
-diff -ur binutils-2.23.2/bfd/Makefile.in binutils-2.23.2.patched/bfd/Makefile.in
---- binutils-2.23.2/bfd/Makefile.in	2012-10-22 14:33:51.000000000 +0200
-+++ binutils-2.25/bfd/Makefile.in	2012-10-24 15:33:04.442080163 +0200
-@@ -323,7 +323,7 @@
- RELEASE = y
+diff -ur binutils-2.25/bfd/Makefile.in binutils-2.25.patched/bfd/Makefile.in
+--- binutils-2.25/bfd/Makefile.in	2015-09-15 06:25:42.000000000 -0700
++++ binutils-2.25.patched/bfd/Makefile.in	2015-09-15 05:51:01.000000000 -0700
+@@ -339,7 +339,7 @@
+ ACLOCAL_AMFLAGS = -I . -I .. -I ../config
  INCDIR = $(srcdir)/../include
  CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
 -SUBDIRS = doc po


From gerrit at coreboot.org  Tue Sep 15 07:28:59 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Tue, 15 Sep 2015 07:28:59 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Fix the
	binutils-no-doc patch with 2.25
References: <Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab+0@gerrit.coreboot.org>
Message-ID: <Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11639

-gerrit

commit 3b04ce9ae5b6dd5bc49a13a8153062625bfe4df7
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 15 03:28:29 2015 -0400

    buildgcc: Fix the binutils-no-doc patch with 2.25
    
    The binutils-2.25 has added some new line, making the hunk
    move downward a little. The utility patch can fix the offset
    with "fuzz" message.
    Remake the patch.
    
    Change-Id: Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
index 317c2b4..5ad70da 100644
--- a/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
+++ b/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
@@ -1,8 +1,8 @@
-diff -ur binutils-2.23.2/bfd/Makefile.in binutils-2.23.2.patched/bfd/Makefile.in
---- binutils-2.23.2/bfd/Makefile.in	2012-10-22 14:33:51.000000000 +0200
-+++ binutils-2.25/bfd/Makefile.in	2012-10-24 15:33:04.442080163 +0200
-@@ -323,7 +323,7 @@
- RELEASE = y
+diff -ur binutils-2.25/bfd/Makefile.in binutils-2.25.patched/bfd/Makefile.in
+--- binutils-2.25/bfd/Makefile.in	2015-09-15 06:25:42.000000000 -0700
++++ binutils-2.25.patched/bfd/Makefile.in	2015-09-15 05:51:01.000000000 -0700
+@@ -339,7 +339,7 @@
+ ACLOCAL_AMFLAGS = -I . -I .. -I ../config
  INCDIR = $(srcdir)/../include
  CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
 -SUBDIRS = doc po


From gerrit at coreboot.org  Tue Sep 15 07:29:03 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Tue, 15 Sep 2015 07:29:03 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Add
	patch for building binutils by clang 6.0
References: <I0f014b776e86e6d0cbebd560cb17f469f31e1dfb+0@gerrit.coreboot.org>
Message-ID: <I0f014b776e86e6d0cbebd560cb17f469f31e1dfb+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11638

-gerrit

commit 132b92fb43c8bc41e44380e81a3718269247739e
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 15 03:27:13 2015 -0400

    buildgcc: Add patch for building binutils by clang 6.0
    
    Clang is the default compiler on BSD and OS X. With this
    change. We don't have to install gcc any more.
    This is a known issue on GNU mail list. Please refer
    the link below.
    https://sourceware.org/bugzilla/show_bug.cgi?id=17473
    
    Change-Id: I0f014b776e86e6d0cbebd560cb17f469f31e1dfb
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/patches/binutils-2.25_host-clang.patch | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/util/crossgcc/patches/binutils-2.25_host-clang.patch b/util/crossgcc/patches/binutils-2.25_host-clang.patch
new file mode 100644
index 0000000..b34bacd
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.25_host-clang.patch
@@ -0,0 +1,18 @@
+This is a known issue on GNU mail list. Please refer
+the link below.
+https://sourceware.org/bugzilla/show_bug.cgi?id=17473
+
+--- binutils-2.25/gold/binary.cc	2014-10-14 00:32:04.000000000 -0700
++++ binutils-2.25.patched/gold/binary.cc	2015-09-15 07:02:40.000000000 -0700
+@@ -24,10 +24,10 @@
+ 
+ #include <cerrno>
+ #include <cstring>
++#include "stringpool.h"
+ #include "safe-ctype.h"
+ 
+ #include "elfcpp.h"
+-#include "stringpool.h"
+ #include "fileread.h"
+ #include "output.h"
+ #include "binary.h"


From gerrit at coreboot.org  Tue Sep 15 14:30:27 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 15 Sep 2015 14:30:27 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: expose
	rmodule logic
References: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+0@gerrit.coreboot.org>
Message-ID: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11598

-gerrit

commit 62d829369e95d2c7417ebed144b81e5934673506
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 17:24:04 2015 -0500

    cbfstool: expose rmodule logic
    
    In order to allow cbfstool to add XIP romstage on x86 without
    doing the 'cbfstool locate', relink, then 'cbfstool add' dance
    expose the core logic and of rmodule including proving an optional
    filter. The filter will be used for ignoring relocations to the
    .car.global region.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 62 ++++++++++++++++---------------------------------
 util/cbfstool/rmodule.h | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+), 42 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 03828f7..46c9384 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -24,39 +24,6 @@
 #include "rmodule.h"
 #include "../../src/include/rmodule-defs.h"
 
-struct rmod_context;
-
-struct arch_ops {
-	int arch;
-	/* Determine if relocation is a valid type for the architecture. */
-	int (*valid_type)(Elf64_Rela *rel);
-	/* Determine if relocation should be emitted. */
-	int (*should_emit)(Elf64_Rela *rel);
-};
-
-struct rmod_context {
-	/* Ops to process relocations. */
-	struct arch_ops *ops;
-
-	/* endian conversion ops */
-	struct xdr *xdr;
-
-	/* Parsed ELF sturcture. */
-	struct parsed_elf pelf;
-	/* Program segment. */
-	Elf64_Phdr *phdr;
-
-	/* Collection of relocation addresses fixup in the module. */
-	Elf64_Xword nrelocs;
-	Elf64_Addr *emitted_relocs;
-
-	/* The following fields are addresses within the linked program.  */
-	Elf64_Addr parameters_begin;
-	Elf64_Addr parameters_end;
-	Elf64_Addr bss_begin;
-	Elf64_Addr bss_end;
-};
-
 /*
  * Architecture specific support operations.
  */
@@ -130,7 +97,7 @@ static int should_emit_aarch64(Elf64_Rela *rel)
 	return (type == R_AARCH64_ABS64);
 }
 
-static struct arch_ops reloc_ops[] = {
+static const struct arch_ops reloc_ops[] = {
 	{
 		.arch = EM_386,
 		.valid_type = valid_reloc_386,
@@ -152,7 +119,8 @@ static struct arch_ops reloc_ops[] = {
  * Relocation processing loops.
  */
 
-static int for_each_reloc(struct rmod_context *ctx, int do_emit)
+static int for_each_reloc(struct rmod_context *ctx, struct reloc_filter *f,
+				int do_emit)
 {
 	Elf64_Half i;
 	struct parsed_elf *pelf = &ctx->pelf;
@@ -173,6 +141,7 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 		nrelocs = shdr->sh_size / shdr->sh_entsize;
 
 		for (j = 0; j < nrelocs; j++) {
+			int filter_emit = 1;
 			Elf64_Rela *r = &relocs[j];
 
 			if (!ctx->ops->valid_type(r)) {
@@ -181,7 +150,15 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 				return -1;
 			}
 
-			if (ctx->ops->should_emit(r)) {
+			/* Allow the provided filter to have precedence. */
+			if (f != NULL) {
+				filter_emit = f->filter(f, r);
+
+				if (filter_emit < 0)
+					return filter_emit;
+			}
+
+			if (filter_emit && ctx->ops->should_emit(r)) {
 				int n = ctx->nrelocs;
 				if (do_emit)
 					ctx->emitted_relocs[n] = r->r_offset;
@@ -303,7 +280,8 @@ static int vaddr_cmp(const void *a, const void *b)
 	return 0;
 }
 
-static int collect_relocations(struct rmod_context *ctx)
+int rmodule_collect_relocations(struct rmod_context *ctx,
+				struct reloc_filter *f)
 {
 	Elf64_Xword nrelocs;
 
@@ -312,7 +290,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	 * apply to the program. Count the number relocations. Then collect
 	 * them into the allocated buffer.
 	 */
-	if (for_each_reloc(ctx, 0))
+	if (for_each_reloc(ctx, f, 0))
 		return -1;
 
 	nrelocs = ctx->nrelocs;
@@ -324,7 +302,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	ctx->nrelocs = 0;
 	ctx->emitted_relocs = calloc(nrelocs, sizeof(Elf64_Addr));
 	/* Write out the relocations into the emitted_relocs array. */
-	if (for_each_reloc(ctx, 1))
+	if (for_each_reloc(ctx, f, 1))
 		return -1;
 
 	if (ctx->nrelocs != nrelocs) {
@@ -618,7 +596,7 @@ out:
 	return ret;
 }
 
-static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
 	struct parsed_elf *pelf;
 	int i;
@@ -670,7 +648,7 @@ out:
 	return ret;
 }
 
-static void rmodule_cleanup(struct rmod_context *ctx)
+void rmodule_cleanup(struct rmod_context *ctx)
 {
 	free(ctx->emitted_relocs);
 	parsed_elf_destroy(&ctx->pelf);
@@ -684,7 +662,7 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	if (rmodule_init(&ctx, elfin))
 		goto out;
 
-	if (collect_relocations(&ctx))
+	if (rmodule_collect_relocations(&ctx, NULL))
 		goto out;
 
 	if (populate_rmodule_info(&ctx))
diff --git a/util/cbfstool/rmodule.h b/util/cbfstool/rmodule.h
index 4531f8d..f3d750d 100644
--- a/util/cbfstool/rmodule.h
+++ b/util/cbfstool/rmodule.h
@@ -21,10 +21,71 @@
 #include "elf.h"
 #include "common.h"
 
+struct arch_ops {
+	int arch;
+	/* Determine if relocation is a valid type for the architecture. */
+	int (*valid_type)(Elf64_Rela *rel);
+	/* Determine if relocation should be emitted. */
+	int (*should_emit)(Elf64_Rela *rel);
+};
+
+/*
+ * The fields in rmod_context are read-only to the user. These are
+ * exposed for easy shareability.
+ */
+struct rmod_context {
+	/* Ops to process relocations. */
+	const struct arch_ops *ops;
+
+	/* endian conversion ops */
+	struct xdr *xdr;
+
+	/* Parsed ELF sturcture. */
+	struct parsed_elf pelf;
+	/* Program segment. */
+	Elf64_Phdr *phdr;
+
+	/* Collection of relocation addresses fixup in the module. */
+	Elf64_Xword nrelocs;
+	Elf64_Addr *emitted_relocs;
+
+	/* The following fields are addresses within the linked program.  */
+	Elf64_Addr parameters_begin;
+	Elf64_Addr parameters_end;
+	Elf64_Addr bss_begin;
+	Elf64_Addr bss_end;
+};
+
+struct reloc_filter {
+	/* Return < 0 on error. 0 to ignore relocation and 1 to include
+	 * relocation. */
+	int (*filter)(struct reloc_filter *f, const Elf64_Rela *r);
+	/* Pointer for filter provides */
+	void *context;
+};
+
 /*
  * Parse an ELF file within the elfin buffer and fill in the elfout buffer
  * with a created rmodule in ELF format. Return 0 on success, < 0 on error.
  */
 int rmodule_create(const struct buffer *elfin, struct buffer *elfout);
 
+/*
+ * Initialize an rmodule context from an ELF buffer. Returns 0 on scucess, < 0
+ * on error.
+ */
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin);
+
+/*
+ * Collect all the relocations that apply to the program in
+ * nrelocs/emitted_relocs. One can optionally provide a reloc_filter object
+ * to help in relocation filtering. The filter function will be called twice:
+ * once for counting and once for emitting. The same response should be
+ * provided for each call. Returns 0 on success, < 0 on error.
+ */
+int rmodule_collect_relocations(struct rmod_context *c, struct reloc_filter *f);
+
+/* Clean up the memory consumed by the rmdoule context. */
+void rmodule_cleanup(struct rmod_context *ctx);
+
 #endif /* TOOL_RMODULE_H */


From gerrit at coreboot.org  Tue Sep 15 14:30:39 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 15 Sep 2015 14:30:39 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: corebot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+10@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 095282d91ffcf9a56f3fc1a1f6e034f35625cf27
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    corebot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                                       |   4 +-
 src/arch/x86/include/arch/cbfs.h                   |   2 +-
 src/arch/x86/romcc_console.c                       |   2 +-
 src/commonlib/Makefile.inc                         |  10 +
 src/commonlib/include/commonlib/cbfs_serialized.h  | 190 ++++++++++
 src/commonlib/include/commonlib/cbmem_id.h         | 113 ++++++
 src/commonlib/include/commonlib/coreboot_tables.h  | 387 +++++++++++++++++++++
 src/commonlib/include/commonlib/fmap_serialized.h  |  73 ++++
 src/commonlib/include/commonlib/helpers.h          |  51 +++
 src/commonlib/include/commonlib/loglevel.h         | 178 ++++++++++
 src/commonlib/include/commonlib/mem_pool.h         |  73 ++++
 src/commonlib/include/commonlib/region.h           | 157 +++++++++
 src/commonlib/include/commonlib/rmodule-defs.h     |  63 ++++
 .../include/commonlib/timestamp_serialized.h       |  92 +++++
 src/commonlib/mem_pool.c                           |  51 +++
 src/commonlib/region.c                             | 196 +++++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |   2 +-
 src/include/assets.h                               |   2 +-
 src/include/boot/coreboot_tables.h                 | 384 +-------------------
 src/include/boot_device.h                          |   2 +-
 src/include/cbfs.h                                 |   4 +-
 src/include/cbfs_serialized.h                      | 190 ----------
 src/include/cbmem.h                                |   2 +-
 src/include/cbmem_id.h                             | 113 ------
 src/include/console/console.h                      |   2 +-
 src/include/console/early_print.h                  |   2 +-
 src/include/console/loglevel.h                     | 178 ----------
 src/include/fmap.h                                 |   4 +-
 src/include/fmap_serialized.h                      |  73 ----
 src/include/mem_pool.h                             |  73 ----
 src/include/region.h                               | 157 ---------
 src/include/rmodule-defs.h                         |  63 ----
 src/include/rmodule.h                              |   2 +-
 src/include/stddef.h                               |  34 +-
 src/include/stdlib.h                               |  14 -
 src/include/timestamp.h                            |  69 +---
 src/lib/Makefile.inc                               |   9 -
 src/lib/cbfs_boot_props.c                          |   2 +-
 src/lib/fmap.c                                     |   2 +-
 src/lib/mem_pool.c                                 |  51 ---
 src/lib/region.c                                   | 196 -----------
 src/mainboard/advansus/a785e-i/romstage.c          |   2 +-
 src/mainboard/amd/bimini_fam10/romstage.c          |   2 +-
 src/mainboard/amd/dinar/romstage.c                 |   2 +-
 src/mainboard/amd/inagua/romstage.c                |   2 +-
 src/mainboard/amd/lamar/romstage.c                 |   2 +-
 src/mainboard/amd/mahogany_fam10/romstage.c        |   2 +-
 src/mainboard/amd/olivehill/romstage.c             |   2 +-
 src/mainboard/amd/olivehillplus/romstage.c         |   2 +-
 src/mainboard/amd/parmer/romstage.c                |   2 +-
 src/mainboard/amd/persimmon/romstage.c             |   2 +-
 .../amd/serengeti_cheetah_fam10/romstage.c         |   2 +-
 src/mainboard/amd/south_station/romstage.c         |   2 +-
 src/mainboard/amd/thatcher/romstage.c              |   2 +-
 src/mainboard/amd/tilapia_fam10/romstage.c         |   2 +-
 src/mainboard/amd/torpedo/romstage.c               |   2 +-
 src/mainboard/amd/union_station/romstage.c         |   2 +-
 src/mainboard/asrock/e350m1/romstage.c             |   2 +-
 src/mainboard/asrock/imb-a180/romstage.c           |   2 +-
 src/mainboard/asus/m4a78-em/romstage.c             |   2 +-
 src/mainboard/asus/m4a785-m/romstage.c             |   2 +-
 src/mainboard/asus/m5a88-v/romstage.c              |   2 +-
 src/mainboard/avalue/eax-785e/romstage.c           |   2 +-
 src/mainboard/bap/ode_e20XX/romstage.c             |   2 +-
 src/mainboard/biostar/am1ml/romstage.c             |   2 +-
 src/mainboard/gigabyte/ma785gm/romstage.c          |   2 +-
 src/mainboard/gigabyte/ma785gmt/romstage.c         |   2 +-
 src/mainboard/gigabyte/ma78gm/romstage.c           |   2 +-
 src/mainboard/gizmosphere/gizmo/romstage.c         |   2 +-
 src/mainboard/gizmosphere/gizmo2/romstage.c        |   2 +-
 src/mainboard/google/peach_pit/romstage.c          |   2 +-
 src/mainboard/hp/abm/romstage.c                    |   2 +-
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |   2 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |   2 +-
 src/mainboard/jetway/pa78vm5/romstage.c            |   2 +-
 src/mainboard/lippert/frontrunner-af/romstage.c    |   2 +-
 src/mainboard/lippert/toucan-af/romstage.c         |   2 +-
 src/mainboard/pcengines/apu1/romstage.c            |   2 +-
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |   2 +-
 src/soc/intel/broadwell/include/soc/me.h           |   2 +-
 src/southbridge/amd/cimx/sb700/Platform.h          |   2 +-
 src/southbridge/amd/cimx/sb700/early.c             |   2 +-
 src/southbridge/amd/cimx/sb900/early.c             |   2 +-
 src/vendorcode/amd/agesa/common/Porting.h          |   2 +-
 src/vendorcode/amd/pi/00630F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c    |   2 +-
 src/vendorcode/amd/pi/00730F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/Makefile.inc                 |   1 +
 src/vendorcode/google/chromeos/vboot_common.h      |   2 +-
 util/cbfstool/Makefile                             |   1 +
 util/cbfstool/Makefile.inc                         |   1 +
 util/cbfstool/rmodule.c                            |   2 +-
 util/cbmem/Makefile                                |   2 +-
 util/cbmem/cbmem.c                                 |   9 +-
 95 files changed, 1711 insertions(+), 1673 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..34f3411 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
 #ifndef __INCLUDE_ARCH_CBFS__
 #define __INCLUDE_ARCH_CBFS__
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
 #include <endian.h>
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
 #include <build.h>
 #include <console/streams.h>
 #include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* Include the sources. */
 #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_PAYLOAD    0x20
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+	uint32_t compression;  /** Compression type */
+	uint64_t entry;  /** entry point */
+	uint64_t load;   /** Where to load in memory */
+	uint32_t len;          /** length of data to load */
+	uint32_t memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image.  Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing.   For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed.  This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ *   a particular motherboard is constructed? (Assuming the kernel
+ *   has drivers for all of the hardware but it does not have
+ *   assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not.  This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped.  Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+	uint64_t result;
+	result = value.hi;
+	result = (result << 32) + value.lo;
+	return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+	struct lb_uint64 result;
+	result.lo = (value >> 0) & 0xffffffff;
+	result.hi = (value >> 32) & 0xffffffff;
+	return result;
+}
+
+struct lb_header
+{
+	uint8_t  signature[4]; /* LBIO */
+	uint32_t header_bytes;
+	uint32_t header_checksum;
+	uint32_t table_bytes;
+	uint32_t table_checksum;
+	uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record.  Encoding both type and size.  The type is obviously
+ * so you can tell what it is.  The size allows you to skip that
+ * boot environment record if you don't know what it is.  This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+	uint32_t tag;		/* tag ID */
+	uint32_t size;		/* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED		0x0000
+
+#define LB_TAG_MEMORY		0x0001
+
+struct lb_memory_range {
+	struct lb_uint64 start;
+	struct lb_uint64 size;
+	uint32_t type;
+#define LB_MEM_RAM		 1	/* Memory anyone can use */
+#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
+#define LB_MEM_ACPI		 3	/* ACPI Tables */
+#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
+#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
+#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+	uint32_t tag;
+	uint32_t size;
+	struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB		0x0002
+struct lb_hwrpb {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
+#define LB_TAG_VERSION		0x0004
+#define LB_TAG_EXTRA_VERSION	0x0005
+#define LB_TAG_BUILD		0x0006
+#define LB_TAG_COMPILE_TIME	0x0007
+#define LB_TAG_COMPILE_BY	0x0008
+#define LB_TAG_COMPILE_HOST	0x0009
+#define LB_TAG_COMPILE_DOMAIN	0x000a
+#define LB_TAG_COMPILER		0x000b
+#define LB_TAG_LINKER		0x000c
+#define LB_TAG_ASSEMBLER	0x000d
+struct lb_string {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP	0x0026
+struct lb_timestamp {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL		0x000f
+struct lb_serial {
+	uint32_t tag;
+	uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
+	uint32_t baud;
+	uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE		0x0010
+struct lb_console {
+	uint32_t tag;
+	uint32_t size;
+	uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250	0
+#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI		5
+#define LB_TAG_CONSOLE_SERIAL8250MEM	6
+
+#define LB_TAG_FORWARD		0x0011
+struct lb_forward {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER	0x0012
+struct lb_framebuffer {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t physical_address;
+	uint32_t x_resolution;
+	uint32_t y_resolution;
+	uint32_t bytes_per_line;
+	uint8_t bits_per_pixel;
+	uint8_t red_mask_pos;
+	uint8_t red_mask_size;
+	uint8_t green_mask_pos;
+	uint8_t green_mask_size;
+	uint8_t blue_mask_pos;
+	uint8_t blue_mask_size;
+	uint8_t reserved_mask_pos;
+	uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT		0x0015
+#define LB_TAG_VBNV		0x0019
+#define LB_TAB_VBOOT_HANDOFF	0x0020
+#define LB_TAB_DMA		0x0022
+#define LB_TAG_RAM_OOPS		0x0023
+#define LB_TAG_MTC		0x002b
+struct lb_range {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t range_start;
+	uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+#define LB_TAG_ACPI_GNVS	0x0024
+#define LB_TAG_WIFI_CALIBRATION	0x0027
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR	0x0021
+struct lb_x86_rom_mtrr {
+	uint32_t tag;
+	uint32_t size;
+	/* The variable range MTRR index covering the ROM. */
+	uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID		0x0025
+struct lb_board_id {
+	uint32_t tag;
+	uint32_t size;
+	/* Board ID as retrieved from the board revision GPIOs. */
+	uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS	0x0026
+struct mac_address {
+	uint8_t mac_addr[6];
+	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t count;
+	struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE		0x0028
+struct lb_ram_code {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH	0x0029
+struct lb_spi_flash {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t flash_size;
+	uint32_t sector_size;
+	uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+	uint32_t tag;
+	uint32_t size;
+	/* offsets are relative to start of boot media */
+	uint64_t fmap_offset;
+	uint64_t cbfs_offset;
+	uint64_t cbfs_size;
+	uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO		0x002a
+#define MAX_SERIALNO_LENGTH	32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+	uint32_t tag;               /* CMOS definitions table type */
+	uint32_t size;               /* size of the entire table */
+	uint32_t header_length;      /* length of header */
+};
+
+/* cmos entry record
+        This record is variable length.  The name field may be
+        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+        anywhere in the byte, but can not span bytes unless it
+        starts at the beginning of the byte and the length is
+        fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+	uint32_t tag;                /* entry type */
+	uint32_t size;               /* length of this record */
+	uint32_t bit;                /* starting bit from start of image */
+	uint32_t length;             /* length of field in bits */
+	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
+	uint32_t config_id;          /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+					       variable length int aligned */
+};
+
+
+/* cmos enumerations record
+        This record is variable length.  The text field may be
+        shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+	uint32_t tag;		     /* enumeration type */
+	uint32_t size; 		     /* length of this record */
+	uint32_t config_id;          /* a number identifying the config id */
+	uint32_t value;              /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+						variable length int aligned */
+};
+
+/* cmos defaults record
+        This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+	uint32_t tag;                /* default type */
+	uint32_t size;               /* length of this record */
+	uint32_t name_length;        /* length of the following name field */
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct	cmos_checksum {
+	uint32_t tag;
+	uint32_t size;
+	/* In practice everything is byte aligned, but things are measured
+	 * in bits to be consistent.
+	 */
+	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
+	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
+	uint32_t location;	/* First bit of the checksum (byte aligned) */
+	uint32_t type;		/* Checksum algorithm that is used */
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __attribute__((packed));
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint16_t	max_entries;
+	uint16_t	tick_freq_mhz;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_VBOOT = 5,
+	TS_END_VBOOT = 6,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_START_BOOTBLOCK = 11,
+	TS_END_BOOTBLOCK = 12,
+	TS_START_COPYROM = 13,
+	TS_END_COPYROM = 14,
+	TS_START_ULZMA = 15,
+	TS_END_ULZMA = 16,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+
+	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+	TS_START_COPYVER = 501,
+	TS_END_COPYVER = 502,
+	TS_START_TPMINIT = 503,
+	TS_END_TPMINIT = 504,
+	TS_START_VERIFY_SLOT = 505,
+	TS_END_VERIFY_SLOT = 506,
+	TS_START_HASH_BODY = 507,
+	TS_DONE_LOADING = 508,
+	TS_DONE_HASHING = 509,
+	TS_END_HASH_BODY = 510,
+
+	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+	TS_FSP_MEMORY_INIT_START = 950,
+	TS_FSP_MEMORY_INIT_END = 951,
+	TS_FSP_TEMP_RAM_EXIT_START = 952,
+	TS_FSP_TEMP_RAM_EXIT_END = 953,
+	TS_FSP_SILICON_INIT_START = 954,
+	TS_FSP_SILICON_INIT_END = 955,
+	TS_FSP_BEFORE_ENUMERATE = 956,
+	TS_FSP_AFTER_ENUMERATE = 957,
+	TS_FSP_BEFORE_FINALIZE = 958,
+	TS_FSP_AFTER_FINALIZE = 959,
+
+	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 9695b3b..b3772a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
 #include <fsp/soc_binding.h>
 #include <fsp/gop.h>
 #include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
 #ifndef ASSETS_H
 #define ASSETS_H
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* An asset represents data used to boot the system. It can be found within
  * CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
 #ifndef COREBOOT_TABLES_H
 #define COREBOOT_TABLES_H
 
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image.  Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing.   For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed.  This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- *   a particular motherboard is constructed? (Assuming the kernel
- *   has drivers for all of the hardware but it does not have
- *   assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not.  This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped.  Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
-	uint32_t lo;
-	uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
-	uint64_t result;
-	result = value.hi;
-	result = (result << 32) + value.lo;
-	return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
-	struct lb_uint64 result;
-	result.lo = (value >> 0) & 0xffffffff;
-	result.hi = (value >> 32) & 0xffffffff;
-	return result;
-}
-
-struct lb_header
-{
-	uint8_t  signature[4]; /* LBIO */
-	uint32_t header_bytes;
-	uint32_t header_checksum;
-	uint32_t table_bytes;
-	uint32_t table_checksum;
-	uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record.  Encoding both type and size.  The type is obviously
- * so you can tell what it is.  The size allows you to skip that
- * boot environment record if you don't know what it is.  This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
-	uint32_t tag;		/* tag ID */
-	uint32_t size;		/* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED		0x0000
-
-#define LB_TAG_MEMORY		0x0001
-
-struct lb_memory_range {
-	struct lb_uint64 start;
-	struct lb_uint64 size;
-	uint32_t type;
-#define LB_MEM_RAM		 1	/* Memory anyone can use */
-#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
-#define LB_MEM_ACPI		 3	/* ACPI Tables */
-#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
-#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
-#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
-	uint32_t tag;
-	uint32_t size;
-	struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB		0x0002
-struct lb_hwrpb {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD	0x0003
-struct lb_mainboard {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  vendor_idx;
-	uint8_t  part_number_idx;
-	uint8_t  strings[0];
-};
-
-#define LB_TAG_VERSION		0x0004
-#define LB_TAG_EXTRA_VERSION	0x0005
-#define LB_TAG_BUILD		0x0006
-#define LB_TAG_COMPILE_TIME	0x0007
-#define LB_TAG_COMPILE_BY	0x0008
-#define LB_TAG_COMPILE_HOST	0x0009
-#define LB_TAG_COMPILE_DOMAIN	0x000a
-#define LB_TAG_COMPILER		0x000b
-#define LB_TAG_LINKER		0x000c
-#define LB_TAG_ASSEMBLER	0x000d
-struct lb_string {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP	0x0026
-struct lb_timestamp {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL		0x000f
-struct lb_serial {
-	uint32_t tag;
-	uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED     1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
-	uint32_t type;
-	uint32_t baseaddr;
-	uint32_t baud;
-	uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE		0x0010
-struct lb_console {
-	uint32_t tag;
-	uint32_t size;
-	uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250	0
-#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI		5
-#define LB_TAG_CONSOLE_SERIAL8250MEM	6
-
-#define LB_TAG_FORWARD		0x0011
-struct lb_forward {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER	0x0012
-struct lb_framebuffer {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t physical_address;
-	uint32_t x_resolution;
-	uint32_t y_resolution;
-	uint32_t bytes_per_line;
-	uint8_t bits_per_pixel;
-	uint8_t red_mask_pos;
-	uint8_t red_mask_size;
-	uint8_t green_mask_pos;
-	uint8_t green_mask_size;
-	uint8_t blue_mask_pos;
-	uint8_t blue_mask_size;
-	uint8_t reserved_mask_pos;
-	uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO	0x0013
-
-struct lb_gpio {
-	uint32_t port;
-	uint32_t polarity;
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-	uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
-        uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
-	uint32_t tag;
-	uint32_t size;
-
-	uint32_t count;
-	struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT		0x0015
-#define LB_TAG_VBNV		0x0019
-#define LB_TAB_VBOOT_HANDOFF	0x0020
-#define LB_TAB_DMA		0x0022
-#define LB_TAG_RAM_OOPS		0x0023
-#define LB_TAG_MTC		0x002b
-struct lb_range {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t range_start;
-	uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS	0x0016
-#define LB_TAG_CBMEM_CONSOLE	0x0017
-#define LB_TAG_MRC_CACHE	0x0018
-#define LB_TAG_ACPI_GNVS	0x0024
-#define LB_TAG_WIFI_CALIBRATION	0x0027
-struct lb_cbmem_ref {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR	0x0021
-struct lb_x86_rom_mtrr {
-	uint32_t tag;
-	uint32_t size;
-	/* The variable range MTRR index covering the ROM. */
-	uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID		0x0025
-struct lb_board_id {
-	uint32_t tag;
-	uint32_t size;
-	/* Board ID as retrieved from the board revision GPIOs. */
-	uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS	0x0026
-struct mac_address {
-	uint8_t mac_addr[6];
-	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t count;
-	struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE		0x0028
-struct lb_ram_code {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH	0x0029
-struct lb_spi_flash {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t flash_size;
-	uint32_t sector_size;
-	uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
-	uint32_t tag;
-	uint32_t size;
-	/* offsets are relative to start of boot media */
-	uint64_t fmap_offset;
-	uint64_t cbfs_offset;
-	uint64_t cbfs_size;
-	uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO		0x002a
-#define MAX_SERIALNO_LENGTH	32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
-	uint32_t tag;               /* CMOS definitions table type */
-	uint32_t size;               /* size of the entire table */
-	uint32_t header_length;      /* length of header */
-};
-
-/* cmos entry record
-        This record is variable length.  The name field may be
-        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
-        anywhere in the byte, but can not span bytes unless it
-        starts at the beginning of the byte and the length is
-        fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
-	uint32_t tag;                /* entry type */
-	uint32_t size;               /* length of this record */
-	uint32_t bit;                /* starting bit from start of image */
-	uint32_t length;             /* length of field in bits */
-	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
-	uint32_t config_id;          /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
-					       variable length int aligned */
-};
-
-
-/* cmos enumerations record
-        This record is variable length.  The text field may be
-        shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
-	uint32_t tag;		     /* enumeration type */
-	uint32_t size; 		     /* length of this record */
-	uint32_t config_id;          /* a number identifying the config id */
-	uint32_t value;              /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
-	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
-						variable length int aligned */
-};
-
-/* cmos defaults record
-        This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
-	uint32_t tag;                /* default type */
-	uint32_t size;               /* length of this record */
-	uint32_t name_length;        /* length of the following name field */
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
-	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct	cmos_checksum {
-	uint32_t tag;
-	uint32_t size;
-	/* In practice everything is byte aligned, but things are measured
-	 * in bits to be consistent.
-	 */
-	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
-	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
-	uint32_t location;	/* First bit of the checksum (byte aligned) */
-	uint32_t type;		/* Checksum algorithm that is used */
-#define CHECKSUM_NONE	0
-#define CHECKSUM_PCBIOS	1
-};
-
+#include <commonlib/coreboot_tables.h>
 /* function prototypes for building the coreboot table */
 
 unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
 #ifndef _BOOT_DEVICE_H_
 #define _BOOT_DEVICE_H_
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* Return the region_device for the read-only boot device. */
 const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
 #include <program_loading.h>
-#include <region.h>
 
 /*
  * CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
-    algorithms that coreboot knows about for stages and
-    payloads.  Of course, other CBFS users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE      0x10
-#define CBFS_TYPE_PAYLOAD    0x20
-#define CBFS_TYPE_OPTIONROM  0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW        0x50
-#define CBFS_TYPE_VSA        0x51
-#define CBFS_TYPE_MBI        0x52
-#define CBFS_TYPE_MICROCODE  0x53
-#define CBFS_TYPE_FSP        0x60
-#define CBFS_TYPE_MRC        0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD          0xab
-#define CBFS_TYPE_MRC_CACHE    0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
-	uint32_t magic;
-	uint32_t version;
-	uint32_t romsize;
-	uint32_t bootblocksize;
-	uint32_t align; /* fixed to 64 bytes */
-	uint32_t offset;
-	uint32_t architecture;
-	uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARM      0x00000010
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	uint32_t len;
-	uint32_t type;
-	uint32_t checksum;
-	uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	uint32_t compression;  /** Compression type */
-	uint64_t entry;  /** entry point */
-	uint64_t load;   /** Where to load in memory */
-	uint32_t len;          /** length of data to load */
-	uint32_t memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	uint32_t type;
-	uint32_t compression;
-	uint32_t offset;
-	uint64_t load_addr;
-	uint32_t len;
-	uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	uint32_t compression;
-	uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
 #include <rules.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <rules.h>
 #include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef __ROMCC__
 struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
 
 #include <console/console.h>
 #include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* While in romstage, console loglevel is built-time constant.
  * With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
 #ifndef _FMAP_H_
 #define _FMAP_H_
 
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
 
 /* Locate the fmap directory. Return 0 on success, < 0 on error. */
 int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *    * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE		"__FMAP__"
-#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
-#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
-#define FMAP_STRLEN		32	/* maximum length for strings, */
-					/* including null-terminator */
-
-enum fmap_flags {
-	FMAP_AREA_STATIC	= 1 << 0,
-	FMAP_AREA_COMPRESSED	= 1 << 1,
-	FMAP_AREA_RO		= 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
-	uint32_t offset;                /* offset relative to base */
-	uint32_t size;                  /* size in bytes */
-	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
-	uint16_t flags;                 /* flags for this area */
-}  __attribute__((packed));
-
-struct fmap {
-	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
-	uint8_t  ver_major;		/* major version */
-	uint8_t  ver_minor;		/* minor version */
-	uint64_t base;			/* address of the firmware binary */
-	uint32_t size;			/* size of firmware binary in bytes */
-	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
-	uint16_t nareas;		/* number of areas described by
-					   fmap_areas[] below */
-	struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
 
 enum {
 	RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <commonlib/helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
 
 #include <stddef.h>
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a)           ALIGN((x),(a))
-#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-
 #define min(a,b) MIN((a),(b))
 #define max(a,b) MAX((a),(b))
 
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
 #ifndef __TIMESTAMP_H__
 #define __TIMESTAMP_H__
 
-#include <stdint.h>
-
-struct timestamp_entry {
-	uint32_t	entry_id;
-	uint64_t	entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
-	uint64_t	base_time;
-	uint16_t	max_entries;
-	uint16_t	tick_freq_mhz;
-	uint32_t	num_entries;
-	struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
-	TS_START_ROMSTAGE = 1,
-	TS_BEFORE_INITRAM = 2,
-	TS_AFTER_INITRAM = 3,
-	TS_END_ROMSTAGE = 4,
-	TS_START_VBOOT = 5,
-	TS_END_VBOOT = 6,
-	TS_START_COPYRAM = 8,
-	TS_END_COPYRAM = 9,
-	TS_START_RAMSTAGE = 10,
-	TS_START_BOOTBLOCK = 11,
-	TS_END_BOOTBLOCK = 12,
-	TS_START_COPYROM = 13,
-	TS_END_COPYROM = 14,
-	TS_START_ULZMA = 15,
-	TS_END_ULZMA = 16,
-	TS_DEVICE_ENUMERATE = 30,
-	TS_DEVICE_CONFIGURE = 40,
-	TS_DEVICE_ENABLE = 50,
-	TS_DEVICE_INITIALIZE = 60,
-	TS_DEVICE_DONE = 70,
-	TS_CBMEM_POST = 75,
-	TS_WRITE_TABLES = 80,
-	TS_LOAD_PAYLOAD = 90,
-	TS_ACPI_WAKE_JUMP = 98,
-	TS_SELFBOOT_JUMP = 99,
-
-	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
-	TS_START_COPYVER = 501,
-	TS_END_COPYVER = 502,
-	TS_START_TPMINIT = 503,
-	TS_END_TPMINIT = 504,
-	TS_START_VERIFY_SLOT = 505,
-	TS_END_VERIFY_SLOT = 506,
-	TS_START_HASH_BODY = 507,
-	TS_DONE_LOADING = 508,
-	TS_DONE_HASHING = 509,
-	TS_END_HASH_BODY = 510,
-
-	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
-	TS_FSP_MEMORY_INIT_START = 950,
-	TS_FSP_MEMORY_INIT_END = 951,
-	TS_FSP_TEMP_RAM_EXIT_START = 952,
-	TS_FSP_TEMP_RAM_EXIT_END = 953,
-	TS_FSP_SILICON_INIT_START = 954,
-	TS_FSP_SILICON_INIT_END = 955,
-	TS_FSP_BEFORE_ENUMERATE = 956,
-	TS_FSP_AFTER_ENUMERATE = 957,
-	TS_FSP_BEFORE_FINALIZE = 958,
-	TS_FSP_AFTER_FINALIZE = 959,
-
-	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
 
 #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
 /*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* This function is marked as weak to allow a particular platform to
  * override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
 #include <stddef.h>
 #include <string.h>
 
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
 #include <spd.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <commonlib/region.h>
 #include <console/console.h>
 #include <device/i2c.h>
 #include <drivers/maxim/max77802/max77802.h>
 #include <program_loading.h>
-#include <region.h>
 #include <soc/clk.h>
 #include <soc/cpu.h>
 #include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
 #define ME_DELAY		10	/* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
 
 #include <cpu/amd/common/cbtypes.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #ifdef NULL
 #undef NULL
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
 #include "sb_cimx.h"
 #include "sb700_cfg.h"                /*sb700_cimx_config*/
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
 #include "SbPlatform.h"
 #include "sb_cimx.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
 #include "amdlib.h"
 #include "cbfs.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 // TODO Add a kconfig option to name the AGESA ROM file in CBFS
 #define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
 #include <assert.h>
 #include <config.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
 #define VBOOT_COMMON_H
 
 #include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* The FW areas consist of multiple components. At the beginning of
  * each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
 
 /*
  * Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
 #include <sys/mman.h>
 #include <libgen.h>
 #include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
 
 #ifdef __OpenBSD__
 #include <sys/param.h>
@@ -42,18 +45,12 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
 
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
-#include "timestamp.h"
-
 #define CBMEM_VERSION "1.1"
 
 /* verbose output? */


From gerrit at coreboot.org  Tue Sep 15 14:30:56 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 15 Sep 2015 14:30:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prepare
	for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <I176d0ae0ae1933cdf6adac67d393ba676198861a+8@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11595

-gerrit

commit 86c5e801fb3dd5407d3cab9a959d70e3cd9d2667
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 69 ++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 1f41d17..03828f7 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,14 +50,11 @@ struct rmod_context {
 	Elf64_Xword nrelocs;
 	Elf64_Addr *emitted_relocs;
 
-	/* The following fields are addresses within the linked program. */
-	Elf64_Addr link_addr;
-	Elf64_Addr entry;
+	/* The following fields are addresses within the linked program.  */
 	Elf64_Addr parameters_begin;
 	Elf64_Addr parameters_end;
 	Elf64_Addr bss_begin;
 	Elf64_Addr bss_end;
-	Elf64_Xword size;
 };
 
 /*
@@ -371,7 +368,7 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr,
 	return -1;
 }
 
-static int populate_program_info(struct rmod_context *ctx)
+static int populate_rmodule_info(struct rmod_context *ctx)
 {
 	int i;
 	const char *strtab;
@@ -423,15 +420,6 @@ static int populate_program_info(struct rmod_context *ctx)
 	if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0))
 		return -1;
 
-	/* Honor the entry point within the ELF header. */
-	ctx->entry = ehdr->e_entry;
-
-	/* Link address is the virtual address of the program segment. */
-	ctx->link_addr = ctx->phdr->p_vaddr;
-
-	/* The program size is the memsz of the program segment. */
-	ctx->size = ctx->phdr->p_memsz;
-
 	return 0;
 }
 
@@ -516,7 +504,6 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 
 	/* Create ELF writer with modified entry point. */
 	memcpy(&ehdr, &ctx->pelf.ehdr, sizeof(ehdr));
-	ehdr.e_entry = ctx->entry;
 	ew = elf_writer_init(&ehdr);
 
 	if (ew == NULL) {
@@ -544,11 +531,11 @@ write_elf(const struct rmod_context *ctx, const struct buffer *in,
 		loc += ctx->nrelocs * sizeof(Elf32_Addr);
 	ctx->xdr->put32(&rmod_header, loc);
 	/* module_link_start_address */
-	ctx->xdr->put32(&rmod_header, ctx->link_addr);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_vaddr);
 	/* module_program_size */
-	ctx->xdr->put32(&rmod_header, ctx->size);
+	ctx->xdr->put32(&rmod_header, ctx->phdr->p_memsz);
 	/* module_entry_point */
-	ctx->xdr->put32(&rmod_header, ctx->entry);
+	ctx->xdr->put32(&rmod_header, ctx->pelf.ehdr.e_entry);
 	/* parameters_begin */
 	ctx->xdr->put32(&rmod_header, ctx->parameters_begin);
 	/* parameters_end */
@@ -631,16 +618,15 @@ out:
 	return ret;
 }
 
-int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
-	struct rmod_context ctx;
 	struct parsed_elf *pelf;
 	int i;
 	int ret;
 
 	ret = -1;
-	memset(&ctx, 0, sizeof(ctx));
-	pelf = &ctx.pelf;
+	memset(ctx, 0, sizeof(*ctx));
+	pelf = &ctx->pelf;
 
 	if (parse_elf(elfin, pelf, ELF_PARSE_ALL)) {
 		ERROR("Couldn't parse ELF!\n");
@@ -656,32 +642,52 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	/* Determine if architecture is supported. */
 	for (i = 0; i < ARRAY_SIZE(reloc_ops); i++) {
 		if (reloc_ops[i].arch == pelf->ehdr.e_machine) {
-			ctx.ops = &reloc_ops[i];
+			ctx->ops = &reloc_ops[i];
 			break;
 		}
 	}
 
-	if (ctx.ops == NULL) {
+	if (ctx->ops == NULL) {
 		ERROR("ELF is unsupported arch: %u.\n", pelf->ehdr.e_machine);
 		goto out;
 	}
 
 	/* Set the endian ops. */
-	if (ctx.pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
-		ctx.xdr = &xdr_be;
+	if (ctx->pelf.ehdr.e_ident[EI_DATA] == ELFDATA2MSB)
+		ctx->xdr = &xdr_be;
 	else
-		ctx.xdr = &xdr_le;
+		ctx->xdr = &xdr_le;
 
-	if (find_program_segment(&ctx))
+	if (find_program_segment(ctx))
 		goto out;
 
-	if (filter_relocation_sections(&ctx))
+	if (filter_relocation_sections(ctx))
+		goto out;
+
+	ret = 0;
+
+out:
+	return ret;
+}
+
+static void rmodule_cleanup(struct rmod_context *ctx)
+{
+	free(ctx->emitted_relocs);
+	parsed_elf_destroy(&ctx->pelf);
+}
+
+int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
+{
+	struct rmod_context ctx;
+	int ret = -1;
+
+	if (rmodule_init(&ctx, elfin))
 		goto out;
 
 	if (collect_relocations(&ctx))
 		goto out;
 
-	if (populate_program_info(&ctx))
+	if (populate_rmodule_info(&ctx))
 		goto out;
 
 	if (write_elf(&ctx, elfin, elfout))
@@ -690,7 +696,6 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	ret = 0;
 
 out:
-	free(ctx.emitted_relocs);
-	parsed_elf_destroy(pelf);
+	rmodule_cleanup(&ctx);
 	return ret;
 }


From gerrit at coreboot.org  Tue Sep 15 14:53:25 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 15 Sep 2015 14:53:25 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: expose
	rmodule logic
References: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+0@gerrit.coreboot.org>
Message-ID: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11598

-gerrit

commit 1f98d47b1216e2a1b154e585545e282d1721ae82
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 17:24:04 2015 -0500

    cbfstool: expose rmodule logic
    
    In order to allow cbfstool to add XIP romstage on x86 without
    doing the 'cbfstool locate', relink, then 'cbfstool add' dance
    expose the core logic and of rmodule including proving an optional
    filter. The filter will be used for ignoring relocations to the
    .car.global region.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/rmodule.c | 62 ++++++++++++++++--------------------------------
 util/cbfstool/rmodule.h | 63 ++++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 82 insertions(+), 43 deletions(-)

diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 03828f7..46c9384 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -24,39 +24,6 @@
 #include "rmodule.h"
 #include "../../src/include/rmodule-defs.h"
 
-struct rmod_context;
-
-struct arch_ops {
-	int arch;
-	/* Determine if relocation is a valid type for the architecture. */
-	int (*valid_type)(Elf64_Rela *rel);
-	/* Determine if relocation should be emitted. */
-	int (*should_emit)(Elf64_Rela *rel);
-};
-
-struct rmod_context {
-	/* Ops to process relocations. */
-	struct arch_ops *ops;
-
-	/* endian conversion ops */
-	struct xdr *xdr;
-
-	/* Parsed ELF sturcture. */
-	struct parsed_elf pelf;
-	/* Program segment. */
-	Elf64_Phdr *phdr;
-
-	/* Collection of relocation addresses fixup in the module. */
-	Elf64_Xword nrelocs;
-	Elf64_Addr *emitted_relocs;
-
-	/* The following fields are addresses within the linked program.  */
-	Elf64_Addr parameters_begin;
-	Elf64_Addr parameters_end;
-	Elf64_Addr bss_begin;
-	Elf64_Addr bss_end;
-};
-
 /*
  * Architecture specific support operations.
  */
@@ -130,7 +97,7 @@ static int should_emit_aarch64(Elf64_Rela *rel)
 	return (type == R_AARCH64_ABS64);
 }
 
-static struct arch_ops reloc_ops[] = {
+static const struct arch_ops reloc_ops[] = {
 	{
 		.arch = EM_386,
 		.valid_type = valid_reloc_386,
@@ -152,7 +119,8 @@ static struct arch_ops reloc_ops[] = {
  * Relocation processing loops.
  */
 
-static int for_each_reloc(struct rmod_context *ctx, int do_emit)
+static int for_each_reloc(struct rmod_context *ctx, struct reloc_filter *f,
+				int do_emit)
 {
 	Elf64_Half i;
 	struct parsed_elf *pelf = &ctx->pelf;
@@ -173,6 +141,7 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 		nrelocs = shdr->sh_size / shdr->sh_entsize;
 
 		for (j = 0; j < nrelocs; j++) {
+			int filter_emit = 1;
 			Elf64_Rela *r = &relocs[j];
 
 			if (!ctx->ops->valid_type(r)) {
@@ -181,7 +150,15 @@ static int for_each_reloc(struct rmod_context *ctx, int do_emit)
 				return -1;
 			}
 
-			if (ctx->ops->should_emit(r)) {
+			/* Allow the provided filter to have precedence. */
+			if (f != NULL) {
+				filter_emit = f->filter(f, r);
+
+				if (filter_emit < 0)
+					return filter_emit;
+			}
+
+			if (filter_emit && ctx->ops->should_emit(r)) {
 				int n = ctx->nrelocs;
 				if (do_emit)
 					ctx->emitted_relocs[n] = r->r_offset;
@@ -303,7 +280,8 @@ static int vaddr_cmp(const void *a, const void *b)
 	return 0;
 }
 
-static int collect_relocations(struct rmod_context *ctx)
+int rmodule_collect_relocations(struct rmod_context *ctx,
+				struct reloc_filter *f)
 {
 	Elf64_Xword nrelocs;
 
@@ -312,7 +290,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	 * apply to the program. Count the number relocations. Then collect
 	 * them into the allocated buffer.
 	 */
-	if (for_each_reloc(ctx, 0))
+	if (for_each_reloc(ctx, f, 0))
 		return -1;
 
 	nrelocs = ctx->nrelocs;
@@ -324,7 +302,7 @@ static int collect_relocations(struct rmod_context *ctx)
 	ctx->nrelocs = 0;
 	ctx->emitted_relocs = calloc(nrelocs, sizeof(Elf64_Addr));
 	/* Write out the relocations into the emitted_relocs array. */
-	if (for_each_reloc(ctx, 1))
+	if (for_each_reloc(ctx, f, 1))
 		return -1;
 
 	if (ctx->nrelocs != nrelocs) {
@@ -618,7 +596,7 @@ out:
 	return ret;
 }
 
-static int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin)
 {
 	struct parsed_elf *pelf;
 	int i;
@@ -670,7 +648,7 @@ out:
 	return ret;
 }
 
-static void rmodule_cleanup(struct rmod_context *ctx)
+void rmodule_cleanup(struct rmod_context *ctx)
 {
 	free(ctx->emitted_relocs);
 	parsed_elf_destroy(&ctx->pelf);
@@ -684,7 +662,7 @@ int rmodule_create(const struct buffer *elfin, struct buffer *elfout)
 	if (rmodule_init(&ctx, elfin))
 		goto out;
 
-	if (collect_relocations(&ctx))
+	if (rmodule_collect_relocations(&ctx, NULL))
 		goto out;
 
 	if (populate_rmodule_info(&ctx))
diff --git a/util/cbfstool/rmodule.h b/util/cbfstool/rmodule.h
index 4531f8d..9a65677 100644
--- a/util/cbfstool/rmodule.h
+++ b/util/cbfstool/rmodule.h
@@ -18,13 +18,74 @@
 #ifndef TOOL_RMODULE_H
 #define TOOL_RMODULE_H
 
-#include "elf.h"
+#include "elfparsing.h"
 #include "common.h"
 
+struct arch_ops {
+	int arch;
+	/* Determine if relocation is a valid type for the architecture. */
+	int (*valid_type)(Elf64_Rela *rel);
+	/* Determine if relocation should be emitted. */
+	int (*should_emit)(Elf64_Rela *rel);
+};
+
+/*
+ * The fields in rmod_context are read-only to the user. These are
+ * exposed for easy shareability.
+ */
+struct rmod_context {
+	/* Ops to process relocations. */
+	const struct arch_ops *ops;
+
+	/* endian conversion ops */
+	struct xdr *xdr;
+
+	/* Parsed ELF sturcture. */
+	struct parsed_elf pelf;
+	/* Program segment. */
+	Elf64_Phdr *phdr;
+
+	/* Collection of relocation addresses fixup in the module. */
+	Elf64_Xword nrelocs;
+	Elf64_Addr *emitted_relocs;
+
+	/* The following fields are addresses within the linked program.  */
+	Elf64_Addr parameters_begin;
+	Elf64_Addr parameters_end;
+	Elf64_Addr bss_begin;
+	Elf64_Addr bss_end;
+};
+
+struct reloc_filter {
+	/* Return < 0 on error. 0 to ignore relocation and 1 to include
+	 * relocation. */
+	int (*filter)(struct reloc_filter *f, const Elf64_Rela *r);
+	/* Pointer for filter provides */
+	void *context;
+};
+
 /*
  * Parse an ELF file within the elfin buffer and fill in the elfout buffer
  * with a created rmodule in ELF format. Return 0 on success, < 0 on error.
  */
 int rmodule_create(const struct buffer *elfin, struct buffer *elfout);
 
+/*
+ * Initialize an rmodule context from an ELF buffer. Returns 0 on scucess, < 0
+ * on error.
+ */
+int rmodule_init(struct rmod_context *ctx, const struct buffer *elfin);
+
+/*
+ * Collect all the relocations that apply to the program in
+ * nrelocs/emitted_relocs. One can optionally provide a reloc_filter object
+ * to help in relocation filtering. The filter function will be called twice:
+ * once for counting and once for emitting. The same response should be
+ * provided for each call. Returns 0 on success, < 0 on error.
+ */
+int rmodule_collect_relocations(struct rmod_context *c, struct reloc_filter *f);
+
+/* Clean up the memory consumed by the rmdoule context. */
+void rmodule_cleanup(struct rmod_context *ctx);
+
 #endif /* TOOL_RMODULE_H */


From gerrit at coreboot.org  Tue Sep 15 14:53:36 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 15 Sep 2015 14:53:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: corebot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+11@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 15497094c29261f1cab243c22956cd0024a7154d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    corebot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                                       |   4 +-
 src/arch/x86/include/arch/cbfs.h                   |   2 +-
 src/arch/x86/romcc_console.c                       |   2 +-
 src/commonlib/Makefile.inc                         |  10 +
 src/commonlib/include/commonlib/cbfs_serialized.h  | 190 ++++++++++
 src/commonlib/include/commonlib/cbmem_id.h         | 113 ++++++
 src/commonlib/include/commonlib/coreboot_tables.h  | 387 +++++++++++++++++++++
 src/commonlib/include/commonlib/fmap_serialized.h  |  73 ++++
 src/commonlib/include/commonlib/helpers.h          |  51 +++
 src/commonlib/include/commonlib/loglevel.h         | 178 ++++++++++
 src/commonlib/include/commonlib/mem_pool.h         |  73 ++++
 src/commonlib/include/commonlib/region.h           | 157 +++++++++
 src/commonlib/include/commonlib/rmodule-defs.h     |  63 ++++
 .../include/commonlib/timestamp_serialized.h       |  92 +++++
 src/commonlib/mem_pool.c                           |  51 +++
 src/commonlib/region.c                             | 196 +++++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |   2 +-
 src/include/assets.h                               |   2 +-
 src/include/boot/coreboot_tables.h                 | 384 +-------------------
 src/include/boot_device.h                          |   2 +-
 src/include/cbfs.h                                 |   4 +-
 src/include/cbfs_serialized.h                      | 190 ----------
 src/include/cbmem.h                                |   2 +-
 src/include/cbmem_id.h                             | 113 ------
 src/include/console/console.h                      |   2 +-
 src/include/console/early_print.h                  |   2 +-
 src/include/console/loglevel.h                     | 178 ----------
 src/include/fmap.h                                 |   4 +-
 src/include/fmap_serialized.h                      |  73 ----
 src/include/mem_pool.h                             |  73 ----
 src/include/region.h                               | 157 ---------
 src/include/rmodule-defs.h                         |  63 ----
 src/include/rmodule.h                              |   2 +-
 src/include/stddef.h                               |  34 +-
 src/include/stdlib.h                               |  14 -
 src/include/timestamp.h                            |  69 +---
 src/lib/Makefile.inc                               |   9 -
 src/lib/cbfs_boot_props.c                          |   2 +-
 src/lib/fmap.c                                     |   2 +-
 src/lib/mem_pool.c                                 |  51 ---
 src/lib/region.c                                   | 196 -----------
 src/mainboard/advansus/a785e-i/romstage.c          |   2 +-
 src/mainboard/amd/bimini_fam10/romstage.c          |   2 +-
 src/mainboard/amd/dinar/romstage.c                 |   2 +-
 src/mainboard/amd/inagua/romstage.c                |   2 +-
 src/mainboard/amd/lamar/romstage.c                 |   2 +-
 src/mainboard/amd/mahogany_fam10/romstage.c        |   2 +-
 src/mainboard/amd/olivehill/romstage.c             |   2 +-
 src/mainboard/amd/olivehillplus/romstage.c         |   2 +-
 src/mainboard/amd/parmer/romstage.c                |   2 +-
 src/mainboard/amd/persimmon/romstage.c             |   2 +-
 .../amd/serengeti_cheetah_fam10/romstage.c         |   2 +-
 src/mainboard/amd/south_station/romstage.c         |   2 +-
 src/mainboard/amd/thatcher/romstage.c              |   2 +-
 src/mainboard/amd/tilapia_fam10/romstage.c         |   2 +-
 src/mainboard/amd/torpedo/romstage.c               |   2 +-
 src/mainboard/amd/union_station/romstage.c         |   2 +-
 src/mainboard/asrock/e350m1/romstage.c             |   2 +-
 src/mainboard/asrock/imb-a180/romstage.c           |   2 +-
 src/mainboard/asus/m4a78-em/romstage.c             |   2 +-
 src/mainboard/asus/m4a785-m/romstage.c             |   2 +-
 src/mainboard/asus/m5a88-v/romstage.c              |   2 +-
 src/mainboard/avalue/eax-785e/romstage.c           |   2 +-
 src/mainboard/bap/ode_e20XX/romstage.c             |   2 +-
 src/mainboard/biostar/am1ml/romstage.c             |   2 +-
 src/mainboard/gigabyte/ma785gm/romstage.c          |   2 +-
 src/mainboard/gigabyte/ma785gmt/romstage.c         |   2 +-
 src/mainboard/gigabyte/ma78gm/romstage.c           |   2 +-
 src/mainboard/gizmosphere/gizmo/romstage.c         |   2 +-
 src/mainboard/gizmosphere/gizmo2/romstage.c        |   2 +-
 src/mainboard/google/peach_pit/romstage.c          |   2 +-
 src/mainboard/hp/abm/romstage.c                    |   2 +-
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |   2 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |   2 +-
 src/mainboard/jetway/pa78vm5/romstage.c            |   2 +-
 src/mainboard/lippert/frontrunner-af/romstage.c    |   2 +-
 src/mainboard/lippert/toucan-af/romstage.c         |   2 +-
 src/mainboard/pcengines/apu1/romstage.c            |   2 +-
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |   2 +-
 src/soc/intel/broadwell/include/soc/me.h           |   2 +-
 src/southbridge/amd/cimx/sb700/Platform.h          |   2 +-
 src/southbridge/amd/cimx/sb700/early.c             |   2 +-
 src/southbridge/amd/cimx/sb900/early.c             |   2 +-
 src/vendorcode/amd/agesa/common/Porting.h          |   2 +-
 src/vendorcode/amd/pi/00630F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c    |   2 +-
 src/vendorcode/amd/pi/00730F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/Makefile.inc                 |   1 +
 src/vendorcode/google/chromeos/vboot_common.h      |   2 +-
 util/cbfstool/Makefile                             |   1 +
 util/cbfstool/Makefile.inc                         |   1 +
 util/cbfstool/rmodule.c                            |   2 +-
 util/cbmem/Makefile                                |   2 +-
 util/cbmem/cbmem.c                                 |   9 +-
 95 files changed, 1711 insertions(+), 1673 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..34f3411 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
 #ifndef __INCLUDE_ARCH_CBFS__
 #define __INCLUDE_ARCH_CBFS__
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
 #include <endian.h>
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
 #include <build.h>
 #include <console/streams.h>
 #include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* Include the sources. */
 #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_PAYLOAD    0x20
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+	uint32_t compression;  /** Compression type */
+	uint64_t entry;  /** entry point */
+	uint64_t load;   /** Where to load in memory */
+	uint32_t len;          /** length of data to load */
+	uint32_t memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image.  Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing.   For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed.  This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ *   a particular motherboard is constructed? (Assuming the kernel
+ *   has drivers for all of the hardware but it does not have
+ *   assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not.  This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped.  Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+	uint64_t result;
+	result = value.hi;
+	result = (result << 32) + value.lo;
+	return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+	struct lb_uint64 result;
+	result.lo = (value >> 0) & 0xffffffff;
+	result.hi = (value >> 32) & 0xffffffff;
+	return result;
+}
+
+struct lb_header
+{
+	uint8_t  signature[4]; /* LBIO */
+	uint32_t header_bytes;
+	uint32_t header_checksum;
+	uint32_t table_bytes;
+	uint32_t table_checksum;
+	uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record.  Encoding both type and size.  The type is obviously
+ * so you can tell what it is.  The size allows you to skip that
+ * boot environment record if you don't know what it is.  This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+	uint32_t tag;		/* tag ID */
+	uint32_t size;		/* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED		0x0000
+
+#define LB_TAG_MEMORY		0x0001
+
+struct lb_memory_range {
+	struct lb_uint64 start;
+	struct lb_uint64 size;
+	uint32_t type;
+#define LB_MEM_RAM		 1	/* Memory anyone can use */
+#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
+#define LB_MEM_ACPI		 3	/* ACPI Tables */
+#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
+#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
+#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+	uint32_t tag;
+	uint32_t size;
+	struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB		0x0002
+struct lb_hwrpb {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
+#define LB_TAG_VERSION		0x0004
+#define LB_TAG_EXTRA_VERSION	0x0005
+#define LB_TAG_BUILD		0x0006
+#define LB_TAG_COMPILE_TIME	0x0007
+#define LB_TAG_COMPILE_BY	0x0008
+#define LB_TAG_COMPILE_HOST	0x0009
+#define LB_TAG_COMPILE_DOMAIN	0x000a
+#define LB_TAG_COMPILER		0x000b
+#define LB_TAG_LINKER		0x000c
+#define LB_TAG_ASSEMBLER	0x000d
+struct lb_string {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP	0x0026
+struct lb_timestamp {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL		0x000f
+struct lb_serial {
+	uint32_t tag;
+	uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
+	uint32_t baud;
+	uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE		0x0010
+struct lb_console {
+	uint32_t tag;
+	uint32_t size;
+	uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250	0
+#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI		5
+#define LB_TAG_CONSOLE_SERIAL8250MEM	6
+
+#define LB_TAG_FORWARD		0x0011
+struct lb_forward {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER	0x0012
+struct lb_framebuffer {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t physical_address;
+	uint32_t x_resolution;
+	uint32_t y_resolution;
+	uint32_t bytes_per_line;
+	uint8_t bits_per_pixel;
+	uint8_t red_mask_pos;
+	uint8_t red_mask_size;
+	uint8_t green_mask_pos;
+	uint8_t green_mask_size;
+	uint8_t blue_mask_pos;
+	uint8_t blue_mask_size;
+	uint8_t reserved_mask_pos;
+	uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT		0x0015
+#define LB_TAG_VBNV		0x0019
+#define LB_TAB_VBOOT_HANDOFF	0x0020
+#define LB_TAB_DMA		0x0022
+#define LB_TAG_RAM_OOPS		0x0023
+#define LB_TAG_MTC		0x002b
+struct lb_range {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t range_start;
+	uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+#define LB_TAG_ACPI_GNVS	0x0024
+#define LB_TAG_WIFI_CALIBRATION	0x0027
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR	0x0021
+struct lb_x86_rom_mtrr {
+	uint32_t tag;
+	uint32_t size;
+	/* The variable range MTRR index covering the ROM. */
+	uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID		0x0025
+struct lb_board_id {
+	uint32_t tag;
+	uint32_t size;
+	/* Board ID as retrieved from the board revision GPIOs. */
+	uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS	0x0026
+struct mac_address {
+	uint8_t mac_addr[6];
+	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t count;
+	struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE		0x0028
+struct lb_ram_code {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH	0x0029
+struct lb_spi_flash {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t flash_size;
+	uint32_t sector_size;
+	uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+	uint32_t tag;
+	uint32_t size;
+	/* offsets are relative to start of boot media */
+	uint64_t fmap_offset;
+	uint64_t cbfs_offset;
+	uint64_t cbfs_size;
+	uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO		0x002a
+#define MAX_SERIALNO_LENGTH	32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+	uint32_t tag;               /* CMOS definitions table type */
+	uint32_t size;               /* size of the entire table */
+	uint32_t header_length;      /* length of header */
+};
+
+/* cmos entry record
+        This record is variable length.  The name field may be
+        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+        anywhere in the byte, but can not span bytes unless it
+        starts at the beginning of the byte and the length is
+        fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+	uint32_t tag;                /* entry type */
+	uint32_t size;               /* length of this record */
+	uint32_t bit;                /* starting bit from start of image */
+	uint32_t length;             /* length of field in bits */
+	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
+	uint32_t config_id;          /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+					       variable length int aligned */
+};
+
+
+/* cmos enumerations record
+        This record is variable length.  The text field may be
+        shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+	uint32_t tag;		     /* enumeration type */
+	uint32_t size; 		     /* length of this record */
+	uint32_t config_id;          /* a number identifying the config id */
+	uint32_t value;              /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+						variable length int aligned */
+};
+
+/* cmos defaults record
+        This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+	uint32_t tag;                /* default type */
+	uint32_t size;               /* length of this record */
+	uint32_t name_length;        /* length of the following name field */
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct	cmos_checksum {
+	uint32_t tag;
+	uint32_t size;
+	/* In practice everything is byte aligned, but things are measured
+	 * in bits to be consistent.
+	 */
+	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
+	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
+	uint32_t location;	/* First bit of the checksum (byte aligned) */
+	uint32_t type;		/* Checksum algorithm that is used */
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __attribute__((packed));
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint16_t	max_entries;
+	uint16_t	tick_freq_mhz;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_VBOOT = 5,
+	TS_END_VBOOT = 6,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_START_BOOTBLOCK = 11,
+	TS_END_BOOTBLOCK = 12,
+	TS_START_COPYROM = 13,
+	TS_END_COPYROM = 14,
+	TS_START_ULZMA = 15,
+	TS_END_ULZMA = 16,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+
+	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+	TS_START_COPYVER = 501,
+	TS_END_COPYVER = 502,
+	TS_START_TPMINIT = 503,
+	TS_END_TPMINIT = 504,
+	TS_START_VERIFY_SLOT = 505,
+	TS_END_VERIFY_SLOT = 506,
+	TS_START_HASH_BODY = 507,
+	TS_DONE_LOADING = 508,
+	TS_DONE_HASHING = 509,
+	TS_END_HASH_BODY = 510,
+
+	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+	TS_FSP_MEMORY_INIT_START = 950,
+	TS_FSP_MEMORY_INIT_END = 951,
+	TS_FSP_TEMP_RAM_EXIT_START = 952,
+	TS_FSP_TEMP_RAM_EXIT_END = 953,
+	TS_FSP_SILICON_INIT_START = 954,
+	TS_FSP_SILICON_INIT_END = 955,
+	TS_FSP_BEFORE_ENUMERATE = 956,
+	TS_FSP_AFTER_ENUMERATE = 957,
+	TS_FSP_BEFORE_FINALIZE = 958,
+	TS_FSP_AFTER_FINALIZE = 959,
+
+	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 9695b3b..b3772a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
 #include <fsp/soc_binding.h>
 #include <fsp/gop.h>
 #include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
 #ifndef ASSETS_H
 #define ASSETS_H
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* An asset represents data used to boot the system. It can be found within
  * CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
 #ifndef COREBOOT_TABLES_H
 #define COREBOOT_TABLES_H
 
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image.  Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing.   For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed.  This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- *   a particular motherboard is constructed? (Assuming the kernel
- *   has drivers for all of the hardware but it does not have
- *   assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not.  This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped.  Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
-	uint32_t lo;
-	uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
-	uint64_t result;
-	result = value.hi;
-	result = (result << 32) + value.lo;
-	return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
-	struct lb_uint64 result;
-	result.lo = (value >> 0) & 0xffffffff;
-	result.hi = (value >> 32) & 0xffffffff;
-	return result;
-}
-
-struct lb_header
-{
-	uint8_t  signature[4]; /* LBIO */
-	uint32_t header_bytes;
-	uint32_t header_checksum;
-	uint32_t table_bytes;
-	uint32_t table_checksum;
-	uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record.  Encoding both type and size.  The type is obviously
- * so you can tell what it is.  The size allows you to skip that
- * boot environment record if you don't know what it is.  This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
-	uint32_t tag;		/* tag ID */
-	uint32_t size;		/* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED		0x0000
-
-#define LB_TAG_MEMORY		0x0001
-
-struct lb_memory_range {
-	struct lb_uint64 start;
-	struct lb_uint64 size;
-	uint32_t type;
-#define LB_MEM_RAM		 1	/* Memory anyone can use */
-#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
-#define LB_MEM_ACPI		 3	/* ACPI Tables */
-#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
-#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
-#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
-	uint32_t tag;
-	uint32_t size;
-	struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB		0x0002
-struct lb_hwrpb {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD	0x0003
-struct lb_mainboard {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  vendor_idx;
-	uint8_t  part_number_idx;
-	uint8_t  strings[0];
-};
-
-#define LB_TAG_VERSION		0x0004
-#define LB_TAG_EXTRA_VERSION	0x0005
-#define LB_TAG_BUILD		0x0006
-#define LB_TAG_COMPILE_TIME	0x0007
-#define LB_TAG_COMPILE_BY	0x0008
-#define LB_TAG_COMPILE_HOST	0x0009
-#define LB_TAG_COMPILE_DOMAIN	0x000a
-#define LB_TAG_COMPILER		0x000b
-#define LB_TAG_LINKER		0x000c
-#define LB_TAG_ASSEMBLER	0x000d
-struct lb_string {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP	0x0026
-struct lb_timestamp {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL		0x000f
-struct lb_serial {
-	uint32_t tag;
-	uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED     1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
-	uint32_t type;
-	uint32_t baseaddr;
-	uint32_t baud;
-	uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE		0x0010
-struct lb_console {
-	uint32_t tag;
-	uint32_t size;
-	uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250	0
-#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI		5
-#define LB_TAG_CONSOLE_SERIAL8250MEM	6
-
-#define LB_TAG_FORWARD		0x0011
-struct lb_forward {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER	0x0012
-struct lb_framebuffer {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t physical_address;
-	uint32_t x_resolution;
-	uint32_t y_resolution;
-	uint32_t bytes_per_line;
-	uint8_t bits_per_pixel;
-	uint8_t red_mask_pos;
-	uint8_t red_mask_size;
-	uint8_t green_mask_pos;
-	uint8_t green_mask_size;
-	uint8_t blue_mask_pos;
-	uint8_t blue_mask_size;
-	uint8_t reserved_mask_pos;
-	uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO	0x0013
-
-struct lb_gpio {
-	uint32_t port;
-	uint32_t polarity;
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-	uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
-        uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
-	uint32_t tag;
-	uint32_t size;
-
-	uint32_t count;
-	struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT		0x0015
-#define LB_TAG_VBNV		0x0019
-#define LB_TAB_VBOOT_HANDOFF	0x0020
-#define LB_TAB_DMA		0x0022
-#define LB_TAG_RAM_OOPS		0x0023
-#define LB_TAG_MTC		0x002b
-struct lb_range {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t range_start;
-	uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS	0x0016
-#define LB_TAG_CBMEM_CONSOLE	0x0017
-#define LB_TAG_MRC_CACHE	0x0018
-#define LB_TAG_ACPI_GNVS	0x0024
-#define LB_TAG_WIFI_CALIBRATION	0x0027
-struct lb_cbmem_ref {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR	0x0021
-struct lb_x86_rom_mtrr {
-	uint32_t tag;
-	uint32_t size;
-	/* The variable range MTRR index covering the ROM. */
-	uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID		0x0025
-struct lb_board_id {
-	uint32_t tag;
-	uint32_t size;
-	/* Board ID as retrieved from the board revision GPIOs. */
-	uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS	0x0026
-struct mac_address {
-	uint8_t mac_addr[6];
-	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t count;
-	struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE		0x0028
-struct lb_ram_code {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH	0x0029
-struct lb_spi_flash {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t flash_size;
-	uint32_t sector_size;
-	uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
-	uint32_t tag;
-	uint32_t size;
-	/* offsets are relative to start of boot media */
-	uint64_t fmap_offset;
-	uint64_t cbfs_offset;
-	uint64_t cbfs_size;
-	uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO		0x002a
-#define MAX_SERIALNO_LENGTH	32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
-	uint32_t tag;               /* CMOS definitions table type */
-	uint32_t size;               /* size of the entire table */
-	uint32_t header_length;      /* length of header */
-};
-
-/* cmos entry record
-        This record is variable length.  The name field may be
-        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
-        anywhere in the byte, but can not span bytes unless it
-        starts at the beginning of the byte and the length is
-        fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
-	uint32_t tag;                /* entry type */
-	uint32_t size;               /* length of this record */
-	uint32_t bit;                /* starting bit from start of image */
-	uint32_t length;             /* length of field in bits */
-	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
-	uint32_t config_id;          /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
-					       variable length int aligned */
-};
-
-
-/* cmos enumerations record
-        This record is variable length.  The text field may be
-        shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
-	uint32_t tag;		     /* enumeration type */
-	uint32_t size; 		     /* length of this record */
-	uint32_t config_id;          /* a number identifying the config id */
-	uint32_t value;              /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
-	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
-						variable length int aligned */
-};
-
-/* cmos defaults record
-        This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
-	uint32_t tag;                /* default type */
-	uint32_t size;               /* length of this record */
-	uint32_t name_length;        /* length of the following name field */
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
-	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct	cmos_checksum {
-	uint32_t tag;
-	uint32_t size;
-	/* In practice everything is byte aligned, but things are measured
-	 * in bits to be consistent.
-	 */
-	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
-	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
-	uint32_t location;	/* First bit of the checksum (byte aligned) */
-	uint32_t type;		/* Checksum algorithm that is used */
-#define CHECKSUM_NONE	0
-#define CHECKSUM_PCBIOS	1
-};
-
+#include <commonlib/coreboot_tables.h>
 /* function prototypes for building the coreboot table */
 
 unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
 #ifndef _BOOT_DEVICE_H_
 #define _BOOT_DEVICE_H_
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* Return the region_device for the read-only boot device. */
 const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
 #include <program_loading.h>
-#include <region.h>
 
 /*
  * CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
-    algorithms that coreboot knows about for stages and
-    payloads.  Of course, other CBFS users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE      0x10
-#define CBFS_TYPE_PAYLOAD    0x20
-#define CBFS_TYPE_OPTIONROM  0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW        0x50
-#define CBFS_TYPE_VSA        0x51
-#define CBFS_TYPE_MBI        0x52
-#define CBFS_TYPE_MICROCODE  0x53
-#define CBFS_TYPE_FSP        0x60
-#define CBFS_TYPE_MRC        0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD          0xab
-#define CBFS_TYPE_MRC_CACHE    0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
-	uint32_t magic;
-	uint32_t version;
-	uint32_t romsize;
-	uint32_t bootblocksize;
-	uint32_t align; /* fixed to 64 bytes */
-	uint32_t offset;
-	uint32_t architecture;
-	uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARM      0x00000010
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	uint32_t len;
-	uint32_t type;
-	uint32_t checksum;
-	uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	uint32_t compression;  /** Compression type */
-	uint64_t entry;  /** entry point */
-	uint64_t load;   /** Where to load in memory */
-	uint32_t len;          /** length of data to load */
-	uint32_t memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	uint32_t type;
-	uint32_t compression;
-	uint32_t offset;
-	uint64_t load_addr;
-	uint32_t len;
-	uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	uint32_t compression;
-	uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
 #include <rules.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <rules.h>
 #include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef __ROMCC__
 struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
 
 #include <console/console.h>
 #include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* While in romstage, console loglevel is built-time constant.
  * With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
 #ifndef _FMAP_H_
 #define _FMAP_H_
 
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
 
 /* Locate the fmap directory. Return 0 on success, < 0 on error. */
 int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *    * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE		"__FMAP__"
-#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
-#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
-#define FMAP_STRLEN		32	/* maximum length for strings, */
-					/* including null-terminator */
-
-enum fmap_flags {
-	FMAP_AREA_STATIC	= 1 << 0,
-	FMAP_AREA_COMPRESSED	= 1 << 1,
-	FMAP_AREA_RO		= 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
-	uint32_t offset;                /* offset relative to base */
-	uint32_t size;                  /* size in bytes */
-	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
-	uint16_t flags;                 /* flags for this area */
-}  __attribute__((packed));
-
-struct fmap {
-	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
-	uint8_t  ver_major;		/* major version */
-	uint8_t  ver_minor;		/* minor version */
-	uint64_t base;			/* address of the firmware binary */
-	uint32_t size;			/* size of firmware binary in bytes */
-	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
-	uint16_t nareas;		/* number of areas described by
-					   fmap_areas[] below */
-	struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
 
 enum {
 	RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <commonlib/helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
 
 #include <stddef.h>
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a)           ALIGN((x),(a))
-#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-
 #define min(a,b) MIN((a),(b))
 #define max(a,b) MAX((a),(b))
 
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
 #ifndef __TIMESTAMP_H__
 #define __TIMESTAMP_H__
 
-#include <stdint.h>
-
-struct timestamp_entry {
-	uint32_t	entry_id;
-	uint64_t	entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
-	uint64_t	base_time;
-	uint16_t	max_entries;
-	uint16_t	tick_freq_mhz;
-	uint32_t	num_entries;
-	struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
-	TS_START_ROMSTAGE = 1,
-	TS_BEFORE_INITRAM = 2,
-	TS_AFTER_INITRAM = 3,
-	TS_END_ROMSTAGE = 4,
-	TS_START_VBOOT = 5,
-	TS_END_VBOOT = 6,
-	TS_START_COPYRAM = 8,
-	TS_END_COPYRAM = 9,
-	TS_START_RAMSTAGE = 10,
-	TS_START_BOOTBLOCK = 11,
-	TS_END_BOOTBLOCK = 12,
-	TS_START_COPYROM = 13,
-	TS_END_COPYROM = 14,
-	TS_START_ULZMA = 15,
-	TS_END_ULZMA = 16,
-	TS_DEVICE_ENUMERATE = 30,
-	TS_DEVICE_CONFIGURE = 40,
-	TS_DEVICE_ENABLE = 50,
-	TS_DEVICE_INITIALIZE = 60,
-	TS_DEVICE_DONE = 70,
-	TS_CBMEM_POST = 75,
-	TS_WRITE_TABLES = 80,
-	TS_LOAD_PAYLOAD = 90,
-	TS_ACPI_WAKE_JUMP = 98,
-	TS_SELFBOOT_JUMP = 99,
-
-	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
-	TS_START_COPYVER = 501,
-	TS_END_COPYVER = 502,
-	TS_START_TPMINIT = 503,
-	TS_END_TPMINIT = 504,
-	TS_START_VERIFY_SLOT = 505,
-	TS_END_VERIFY_SLOT = 506,
-	TS_START_HASH_BODY = 507,
-	TS_DONE_LOADING = 508,
-	TS_DONE_HASHING = 509,
-	TS_END_HASH_BODY = 510,
-
-	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
-	TS_FSP_MEMORY_INIT_START = 950,
-	TS_FSP_MEMORY_INIT_END = 951,
-	TS_FSP_TEMP_RAM_EXIT_START = 952,
-	TS_FSP_TEMP_RAM_EXIT_END = 953,
-	TS_FSP_SILICON_INIT_START = 954,
-	TS_FSP_SILICON_INIT_END = 955,
-	TS_FSP_BEFORE_ENUMERATE = 956,
-	TS_FSP_AFTER_ENUMERATE = 957,
-	TS_FSP_BEFORE_FINALIZE = 958,
-	TS_FSP_AFTER_FINALIZE = 959,
-
-	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
 
 #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
 /*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* This function is marked as weak to allow a particular platform to
  * override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
 #include <stddef.h>
 #include <string.h>
 
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
 #include <spd.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <commonlib/region.h>
 #include <console/console.h>
 #include <device/i2c.h>
 #include <drivers/maxim/max77802/max77802.h>
 #include <program_loading.h>
-#include <region.h>
 #include <soc/clk.h>
 #include <soc/cpu.h>
 #include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
 #define ME_DELAY		10	/* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
 
 #include <cpu/amd/common/cbtypes.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #ifdef NULL
 #undef NULL
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
 #include "sb_cimx.h"
 #include "sb700_cfg.h"                /*sb700_cimx_config*/
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
 #include "SbPlatform.h"
 #include "sb_cimx.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
 #include "amdlib.h"
 #include "cbfs.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 // TODO Add a kconfig option to name the AGESA ROM file in CBFS
 #define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
 #include <assert.h>
 #include <config.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
 #define VBOOT_COMMON_H
 
 #include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* The FW areas consist of multiple components. At the beginning of
  * each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
 
 /*
  * Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
 #include <sys/mman.h>
 #include <libgen.h>
 #include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
 
 #ifdef __OpenBSD__
 #include <sys/param.h>
@@ -42,18 +45,12 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
 
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
-#include "timestamp.h"
-
 #define CBMEM_VERSION "1.1"
 
 /* verbose output? */


From gerrit at coreboot.org  Tue Sep 15 17:33:04 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 17:33:04 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: abuild: don't
	create junit tests with empty testclass field
References: <Ifa79cbfd1f263e11a458b3cc320baeed6a3fbc98+0@gerrit.coreboot.org>
Message-ID: <Ifa79cbfd1f263e11a458b3cc320baeed6a3fbc98+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11640

-gerrit

commit 627e2c598712a68c3dc8eb1724b20188f78d7c9a
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Tue Sep 15 16:57:04 2015 +0200

    abuild: don't create junit tests with empty testclass field
    
    Variable expansion made abuild create board..foo/bar, which are annoying
    on jenkins' web UI because it doesn't cope properly with the empty
    namespace between the dots. make it create board.foo/bar or
    board.$class.foo/bar.
    
    Change-Id: Ifa79cbfd1f263e11a458b3cc320baeed6a3fbc98
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/abuild/abuild | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 9516da5..788ed7d 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -479,7 +479,8 @@ chromeos=false
 clean_work=false
 customizing=""
 configoptions=""
-testclass=
+# testclass needs to be undefined if not used for variable expansion to work
+unset testclass
 while true ; do
 	case "$1" in
 		-J|--junit)     shift; mode=junit; rm -f $XMLFILE ;;


From gerrit at coreboot.org  Tue Sep 15 17:33:06 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 17:33:06 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: abuild: log
	bulding tools
References: <Ibcd3b02bce9a314c30b5f7414e9e4cf0149ffd6a+0@gerrit.coreboot.org>
Message-ID: <Ibcd3b02bce9a314c30b5f7414e9e4cf0149ffd6a+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11641

-gerrit

commit f10cf285dbea92c40cacdcb483aafac75106a74f
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Tue Sep 15 17:30:52 2015 +0200

    abuild: log bulding tools
    
    We build the coreboot utilities in a separate step as a minor
    optimization. When logging in junit format (for jenkins), we want to
    have a report on those as well (instead of an xml error).
    
    Change-Id: Ibcd3b02bce9a314c30b5f7414e9e4cf0149ffd6a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/abuild/abuild | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 788ed7d..73ec8c3 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -602,7 +602,32 @@ build_all_targets()
 		rm -rf ${scanbuild_out}
 		BUILDPREFIX="scan-build -o ${scanbuild_out}tmp"
 	fi
-	$BUILDPREFIX $MAKE -j $cpus DOTCONFIG=$TMPCFG obj=$TARGET/temp objutil=$TARGET/sharedutils tools || exit 1
+	mkdir -p $TARGET/abuild
+	local ABSPATH=`cd $TARGET/abuild; pwd`
+	local XMLFILE=$ABSPATH/__util.xml
+	local stime=`perl -e 'print time();' 2>/dev/null || date +%s`
+	$BUILDPREFIX $MAKE -j $cpus DOTCONFIG=$TMPCFG obj=$TARGET/temp objutil=$TARGET/sharedutils tools > $TARGET/sharedutils/make.log 2>&1
+	local ret=$?
+	local etime=`perl -e 'print time();' 2>/dev/null || date +%s`
+	local duration=$(( $etime - $stime ))
+
+	junit " <testcase classname='util' name='all' time='$duration' >"
+	if [ $ret -eq 0 ]; then
+		junit "<system-out>"
+		junitfile $TARGET/sharedutils/make.log
+		junit "</system-out>"
+		junit "</testcase>"
+	else
+		junit "<failure type='BuildFailed'>"
+		junitfile $TARGET/sharedutils/make.log
+		junit "</failure>"
+		junit "</testcase>"
+		return
+	fi
+	if [ $ret -eq 1 ]; then
+		return
+	fi
+
 	if [ "$scanbuild" = "true" ]; then
 		mv ${scanbuild_out}tmp/* ${scanbuild_out}
 		rmdir ${scanbuild_out}tmp


From gerrit at coreboot.org  Tue Sep 15 17:33:08 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 17:33:08 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: abuild: don't
	complain about missing junit reports for skipped boards
References: <I906fd04a315de70340ce76d7c38eaaf88cc6580a+0@gerrit.coreboot.org>
Message-ID: <I906fd04a315de70340ce76d7c38eaaf88cc6580a+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11642

-gerrit

commit d5a2f097252bffbebfa9ec80a84c2ae4ea73e837
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Tue Sep 15 19:32:28 2015 +0200

    abuild: don't complain about missing junit reports for skipped boards
    
    There's no need to whine about missing files, so test for them first.
    
    Change-Id: I906fd04a315de70340ce76d7c38eaaf88cc6580a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/abuild/abuild | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 73ec8c3..98550e1 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -660,7 +660,9 @@ if [ "$target" != "" ]; then
 		build_target $VENDOR $MAINBOARD $CONFIG
 		test_target $VENDOR $MAINBOARD
 		remove_target $VENDOR $MAINBOARD
-		test "$mode" != "text" && cat $TARGET/abuild/${VENDOR}_${MAINBOARD}.xml >> $REAL_XMLFILE
+		test "$mode" != "text" && \
+		test -f $TARGET/abuild/${VENDOR}_${MAINBOARD}.xml && \
+		cat $TARGET/abuild/${VENDOR}_${MAINBOARD}.xml >> $REAL_XMLFILE
 		XMLFILE=$REAL_XMLFILE
 	fi
 else


From gerrit at coreboot.org  Tue Sep 15 18:04:41 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 15 Sep 2015 18:04:41 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	riscv-trap-handling: Add functionality, prevent stack corruption
References: <I68ba3a114b7167b3212bb0bed181a7595f0b97d8+0@gerrit.coreboot.org>
Message-ID: <E1Zbuav-0005ID-KE@mail.coreboot.org>

the following patch was just integrated into master:
commit d9653e1328f8ec07bc1e1fc082f404130c2eee77
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Thu Sep 10 10:55:17 2015 -0700

    riscv-trap-handling: Add functionality, prevent stack corruption
    
    Trap handling code was bugged in that it loaded in the wrong stack
    pointer, overwriting the space the processor uses to talk to its host
    for doing device requests. Fix this issue, as well as add support for
    handling misaligned loads the same way we handle misaligned stores.
    
    Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
    Reviewed-on: http://review.coreboot.org/11620
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See http://review.coreboot.org/11620 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 15 19:39:16 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfs: read cbfs
	offset and size from sysinfo
References: <I86434fd249467e7c90d59d6b82f0e6c514bc2d05+0@gerrit.coreboot.org>
Message-ID: <I86434fd249467e7c90d59d6b82f0e6c514bc2d05+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11557

-gerrit

commit e1d97304a46e77fd52fdcf5bdc98f5a7b5d2a63f
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Sep 2 10:53:13 2015 -0700

    cbfs: read cbfs offset and size from sysinfo
    
    This change allows libpayload to read cbfs offset and size from sysinfo.
    Legacy way of locating cbfs reagion is still supported in case sysinfo
    doesn't store the offset and the size.
    
    BUG=none
    BRANCH=master
    TEST=tested on samus and smaug
    
    Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c
    Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296993
    Original-Commit-Ready: Daisuke Nojiri <dnojiri at google.com>
    Original-Tested-by: Daisuke Nojiri <dnojiri at google.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 payloads/libpayload/libcbfs/cbfs_core.c | 70 +++++++++++++++++++++------------
 1 file changed, 45 insertions(+), 25 deletions(-)

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 7926d9d..90f600c 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -47,6 +47,7 @@
 
 #include <cbfs.h>
 #include <string.h>
+#include <sysinfo.h>
 
 /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS
  *  on failure */
@@ -94,52 +95,71 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
 	return header;
 }
 
-/* public API starts here*/
-struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end,
+			  struct cbfs_media *media)
 {
-	const char *file_name;
-	uint32_t offset, romsize, name_len;
 	const struct cbfs_header *header;
-	struct cbfs_file file, *file_ptr;
-	struct cbfs_media default_media;
 
-	if (media == CBFS_DEFAULT_MEDIA) {
-		media = &default_media;
-		if (init_default_cbfs_media(media) != 0) {
-			ERROR("Failed to initialize default media.\n");
-			return NULL;
-		}
+	if (lib_sysinfo.cbfs_offset && lib_sysinfo.cbfs_size) {
+		*offset = lib_sysinfo.cbfs_offset;
+		*cbfs_end = *offset + lib_sysinfo.cbfs_size;
+		return 0;
 	}
 
-	if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media)))
-		return NULL;
-
+	/*
+	 * If sysinfo doesn't have offset or size, we read them from
+	 * a master header.
+	 */
+	DEBUG("CBFS offset & size not found in sysinfo\n");
+	header = cbfs_get_header(media);
+	if (header == CBFS_HEADER_INVALID_ADDRESS)
+		return -1;
 	// Logical offset (for source media) of first file.
-	offset = ntohl(header->offset);
-	romsize = ntohl(header->romsize);
-
-	// TODO Add a "size" in CBFS header for a platform independent way to
-	// determine the end of CBFS data.
+	*offset = ntohl(header->offset);
+	*cbfs_end = ntohl(header->romsize);
 #if IS_ENABLED(CONFIG_LP_ARCH_X86)
 	// resolve actual length of ROM used for CBFS components
 	// the bootblock size was not taken into account
-	romsize -= ntohl(header->bootblocksize);
+	*cbfs_end -= ntohl(header->bootblocksize);
 
 	// fine tune the length to handle alignment positioning.
 	// using (bootblock size) % align, to derive the
 	// number of bytes the bootblock is off from the alignment size.
 	if ((ntohl(header->bootblocksize) % CBFS_ALIGNMENT))
-		romsize -= (CBFS_ALIGNMENT -
+		*cbfs_end -= (CBFS_ALIGNMENT -
 			(ntohl(header->bootblocksize) % CBFS_ALIGNMENT));
 	else
-		romsize -= 1;
+		*cbfs_end -= 1;
 #endif
+	return 0;
+}
+
+/* public API starts here*/
+struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+{
+	const char *file_name;
+	uint32_t offset, cbfs_end, name_len;
+	struct cbfs_file file, *file_ptr;
+	struct cbfs_media default_media;
+
+	if (media == CBFS_DEFAULT_MEDIA) {
+		media = &default_media;
+		if (init_default_cbfs_media(media) != 0) {
+			ERROR("Failed to initialize default media.\n");
+			return NULL;
+		}
+	}
+
+	if (get_cbfs_range(&offset, &cbfs_end, media)) {
+		ERROR("Failed to find cbfs range\n");
+		return NULL;
+	}
 
-	DEBUG("CBFS location: 0x%x~0x%x\n", offset, romsize);
+	DEBUG("CBFS location: 0x%x~0x%x\n", offset, cbfs_end);
 	DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset);
 
 	media->open(media);
-	while (offset < romsize &&
+	while (offset < cbfs_end &&
 	       media->read(media, &file, offset, sizeof(file)) == sizeof(file)) {
 		if (memcmp(CBFS_FILE_MAGIC, file.magic,
 			   sizeof(file.magic)) != 0) {


From gerrit at coreboot.org  Tue Sep 15 19:39:19 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:19 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Disable Deep S3 on kunimitsu platform
References: <Iad87b7a8f7bf560861a270a8c19153cfc3850bc4+0@gerrit.coreboot.org>
Message-ID: <Iad87b7a8f7bf560861a270a8c19153cfc3850bc4+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11643

-gerrit

commit 770e81763d5d1a422f9b019136244dfa7ecce1d7
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Tue Sep 8 20:46:49 2015 +0530

    kunimitsu: Disable Deep S3 on kunimitsu platform
    
    This patch will reset Deep S3 flag, hence S3 will work.
    
    BUG=chrome-os-partner:40635
    BRANCH=None
    TEST=Build and Boot Kunimitsu and verify S3 is working.
    
    Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5
    Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297903
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 3d69086..4e99d68 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -1,7 +1,7 @@
 chip soc/intel/skylake
 
 	# Enable deep Sx states
-	register "deep_s3_enable" = "1"
+	register "deep_s3_enable" = "0"
 	register "deep_s5_enable" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 


From gerrit at coreboot.org  Tue Sep 15 19:39:22 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:22 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Enable
	ALS connected to EC
References: <I4a4913a1b407720d85f6e630b674e550bf5e36df+0@gerrit.coreboot.org>
Message-ID: <I4a4913a1b407720d85f6e630b674e550bf5e36df+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11644

-gerrit

commit 52335dfd936abe8504f1f9e0b8e41be4b634ab61
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Sep 9 10:06:09 2015 -0700

    glados: Enable ALS connected to EC
    
    Glados has an ambient light sensor connected to the EC which
    is presented to the OS as a standard ACPI0008 device.
    
    BUG=chrome-os-partner:43493
    BRANCH=none
    TEST=test ALS functionality on glados P2 board
    
    Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054
    Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298251
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi/ec.asl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl
index d69ebe2..6546a75 100644
--- a/src/mainboard/google/glados/acpi/ec.asl
+++ b/src/mainboard/google/glados/acpi/ec.asl
@@ -21,6 +21,9 @@
 #include "../ec.h"
 #include "../gpio.h"
 
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 


From gerrit at coreboot.org  Tue Sep 15 19:39:24 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:24 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Enable ALS connected to EC
References: <I7998c19e5514eda781cc20888cdb0732f81389ae+0@gerrit.coreboot.org>
Message-ID: <I7998c19e5514eda781cc20888cdb0732f81389ae+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11645

-gerrit

commit fdb529e36b50d61ef58c3e4b5e14a419a7f96694
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Sep 9 10:09:26 2015 -0700

    kunimitsu: Enable ALS connected to EC
    
    Kunimitsu has an ambient light sensor connected to the EC which
    is presented to the OS as a standard ACPI0008 device.
    
    BUG=chrome-os-partner:43493
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I7998c19e5514eda781cc20888cdb0732f81389ae
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a67e5ddfccea0776841fabe04be55c1854bf31f2
    Original-Change-Id: I381dc9c5777370df2ea4c41c9e153b3277082718
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298252
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/acpi/ec.asl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/intel/kunimitsu/acpi/ec.asl b/src/mainboard/intel/kunimitsu/acpi/ec.asl
index 63c45de..10ca834 100644
--- a/src/mainboard/intel/kunimitsu/acpi/ec.asl
+++ b/src/mainboard/intel/kunimitsu/acpi/ec.asl
@@ -21,6 +21,9 @@
 #include "../ec.h"
 #include "../gpio.h"
 
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 


From gerrit at coreboot.org  Tue Sep 15 19:39:27 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:27 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: intel/common:
	Add common code for filling out ACPI _SWS
References: <I4f3511adcc89a9be5d97a7442055c227a38c5f42+0@gerrit.coreboot.org>
Message-ID: <I4f3511adcc89a9be5d97a7442055c227a38c5f42+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11646

-gerrit

commit 87d3ff72697d070926da7c71950a1d6cdce40f6c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:09:28 2015 -0700

    intel/common: Add common code for filling out ACPI _SWS
    
    Add common code for filling out the NVS fields that are used by
    the ACPI _SWS methods.  The SOC must provide a function to fill
    out the wake source data since the specific data inputs vary by
    platform.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I4f3511adcc89a9be5d97a7442055c227a38c5f42
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: cee5fa176c16ca44712bce8f3c8045daa5f07339
    Original-Change-Id: I16f446ef67777acb57223a84d38062be9f43fcb9
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298167
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/common/Kconfig                   |  4 ++
 src/soc/intel/common/Makefile.inc              |  1 +
 src/soc/intel/common/acpi.h                    | 36 +++++++++++
 src/soc/intel/common/acpi/acpi_wake_source.asl | 36 +++++++++++
 src/soc/intel/common/acpi_wake_source.c        | 90 ++++++++++++++++++++++++++
 5 files changed, 167 insertions(+)

diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 8e632bb..43c52b5 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -69,4 +69,8 @@ config ROMSTAGE_RAM_STACK_SIZE
 	default 0x5000
 	depends on SOC_INTEL_COMMON_STACK
 
+config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+	bool
+	default n
+
 endif # SOC_INTEL_COMMON
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 892ae95..ade5456 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -16,6 +16,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c
 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c
 ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
 
 # Create and add the MRC cache to the cbfs image
 ifneq ($(CONFIG_CHROMEOS),y)
diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h
new file mode 100644
index 0000000..8ee81a6
--- /dev/null
+++ b/src/soc/intel/common/acpi.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _INTEL_COMMON_ACPI_H_
+#define _INTEL_COMMON_ACPI_H_
+
+#include <stdint.h>
+
+/*
+ * SOC specific handler to provide the wake source data for ACPI _SWS.
+ *
+ * @pm1:  PM1_STS register with only enabled events set
+ * @gpe0: GPE0_STS registers with only enabled events set
+ *
+ * return the number of registers in the gpe0 array or -1 if nothing
+ * is provided by this function.
+ */
+int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0);
+
+#endif
diff --git a/src/soc/intel/common/acpi/acpi_wake_source.asl b/src/soc/intel/common/acpi/acpi_wake_source.asl
new file mode 100644
index 0000000..30e70d9
--- /dev/null
+++ b/src/soc/intel/common/acpi/acpi_wake_source.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Scope (\_SB)
+{
+	Method (_SWS)
+	{
+		/* Index into PM1 for device that caused wake */
+		Return (\PM1I)
+	}
+}
+
+Scope (\_GPE)
+{
+	Method (_SWS)
+	{
+		/* Index into GPE for device that caused wake */
+		Return (\GPEI)
+	}
+}
diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c
new file mode 100644
index 0000000..43d6b03
--- /dev/null
+++ b/src/soc/intel/common/acpi_wake_source.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/acpi.h>
+#include <bootstate.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <soc/nvs.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "acpi.h"
+
+__attribute__((weak)) int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
+{
+	return -1;
+}
+
+/* Save wake source data for ACPI _SWS methods in NVS */
+static void acpi_save_wake_source(void *unused)
+{
+	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+	uint32_t pm1, *gpe0;
+	int gpe_reg, gpe_reg_count;
+	int reg_size = sizeof(uint32_t) * 8;
+
+	if (!gnvs)
+		return;
+
+	gnvs->pm1i = -1;
+	gnvs->gpei = -1;
+
+	gpe_reg_count = soc_fill_acpi_wake(&pm1, &gpe0);
+	if (gpe_reg_count < 0)
+		return;
+
+	/* Scan for first set bit in PM1 */
+	for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) {
+		if (pm1 & 1)
+			break;
+		pm1 >>= 1;
+	}
+
+	/* If unable to determine then return -1 */
+	if (gnvs->pm1i >= 16)
+		gnvs->pm1i = -1;
+
+	/* Scan for first set bit in GPE registers */
+	for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) {
+		uint32_t gpe = gpe0[gpe_reg];
+		int start = gpe_reg * reg_size;
+		int end = start + reg_size;
+
+		if (gpe == 0) {
+			if (!gnvs->gpei)
+				gnvs->gpei = end;
+			continue;
+		}
+
+		for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
+			if (gpe & 1)
+				break;
+			gpe >>= 1;
+		}
+	}
+
+	/* If unable to determine then return -1 */
+	if (gnvs->gpei >= gpe_reg_count * reg_size)
+		gnvs->gpei = -1;
+
+	printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
+	       (long long)gnvs->pm1i, (long long)gnvs->gpei);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL);


From gerrit at coreboot.org  Tue Sep 15 19:39:31 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:31 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: broadwell:
	Switch to using common ACPI _SWS code
References: <I3d2ceca8585314122b78317acb7f848efb6e9a14+0@gerrit.coreboot.org>
Message-ID: <I3d2ceca8585314122b78317acb7f848efb6e9a14+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11647

-gerrit

commit a1ca7fbbbee11926abb545f9d87e181fdf81d26b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:10:30 2015 -0700

    broadwell: Switch to using common ACPI _SWS code
    
    Use the common ACPI _SWS code and provide a function to fill out
    the wake source data.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-samus coreboot
    
    Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d8afaee8e27222639c5e249d53be28cddcb78f72
    Original-Change-Id: Ie551ecf3397c304216046cc2046c071f7b766e5f
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298168
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/broadwell/Kconfig           |  1 +
 src/soc/intel/broadwell/acpi/platform.asl | 21 ++----------
 src/soc/intel/broadwell/ramstage.c        | 57 ++++++-------------------------
 3 files changed, 15 insertions(+), 64 deletions(-)

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index c2db2a1..de98f08 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
 	select SOC_INTEL_COMMON
+	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 
 config BOOTBLOCK_CPU_INIT
 	string
diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl
index d302720..c00edeb 100644
--- a/src/soc/intel/broadwell/acpi/platform.asl
+++ b/src/soc/intel/broadwell/acpi/platform.asl
@@ -18,6 +18,9 @@
  * Foundation, Inc.
  */
 
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
 /* The APM port can be used for generating software SMIs */
 
 OperationRegion (APMP, SystemIO, 0xb2, 2)
@@ -71,21 +74,3 @@ Method (_WAK, 1)
 {
 	Return (Package (){ 0, 0 })
 }
-
-Scope (\_SB)
-{
-	Method (_SWS)
-	{
-		/* Index into PM1 for device that caused wake */
-		Return (\PM1I)
-	}
-}
-
-Scope (\_GPE)
-{
-	Method (_SWS)
-	{
-		/* Index into GPE for device that caused wake */
-		Return (\GPEI)
-	}
-}
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index e699e02..c8fb6ed 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -27,56 +27,23 @@
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/intel/broadwell/chip.h>
+#include <soc/intel/common/acpi.h>
 
-/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
-static void save_acpi_wake_source(global_nvs_t *gnvs)
+/* Save wake source information for calculating ACPI _SWS values */
+int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
 {
 	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
-	uint16_t pm1;
-	int gpe_reg;
+	static uint32_t gpe0_sts[GPE0_REG_MAX];
+	int i;
 
-	if (!ps)
-		return;
-
-	pm1 = ps->pm1_sts & ps->pm1_en;
-
-	/* Scan for first set bit in PM1 */
-	for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
-		if (pm1 & 1)
-			break;
-		pm1 >>= 1;
-	}
-
-	/* If unable to determine then return -1 */
-	if (gnvs->pm1i >= 16)
-		gnvs->pm1i = -1;
-
-	/* Scan for first set bit in GPE registers */
-	gnvs->gpei = -1;
-	for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
-		u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
-		int start = gpe_reg * GPE0_REG_SIZE;
-		int end = start + GPE0_REG_SIZE;
-
-		if (gpe == 0) {
-			if (!gnvs->gpei)
-				gnvs->gpei = end;
-			continue;
-		}
-
-		for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
-			if (gpe & 1)
-				break;
-			gpe >>= 1;
-		}
-	}
+	*pm1 = ps->pm1_sts & ps->pm1_en;
 
-	/* If unable to determine then return -1 */
-	if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
-		gnvs->gpei = -1;
+	/* Mask off GPE0 status bits that are not enabled */
+	*gpe0 = &gpe0_sts[0];
+	for (i = 0; i < GPE0_REG_MAX; i++)
+		gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
 
-	printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
-	       gnvs->pm1i, gnvs->gpei);
+	return GPE0_REG_MAX;
 }
 
 static void s3_resume_prepare(void)
@@ -89,8 +56,6 @@ static void s3_resume_prepare(void)
 
 	if (!acpi_is_wakeup_s3())
 		memset(gnvs, 0, sizeof(global_nvs_t));
-	else
-		save_acpi_wake_source(gnvs);
 }
 
 void broadwell_init_pre_device(void *chip_info)


From gerrit at coreboot.org  Tue Sep 15 19:39:35 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:35 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: Use
	common ACPI _SWS code
References: <I93a4f740f2e2ef1c34e948db1d8e273332296921+0@gerrit.coreboot.org>
Message-ID: <I93a4f740f2e2ef1c34e948db1d8e273332296921+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11648

-gerrit

commit ba79449dc976f30558f3ca4f34fad029480d3ac3
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:12:44 2015 -0700

    skylake: Use common ACPI _SWS code
    
    Enable and use the common code for filling out the NVS data used
    by the _SWS methods.  Add a function to provide the wake source
    data.  With Deep S3 enabled skylake does not retain the contents
    of the PM1_EN register so instead just select the wake related
    events in PM1_STS.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=tested on glados by checking for valid _SWS string in
    /sys/firmware/log after suspend/resume.  Wake sources that were
    tested are RTC, power button, keypress, trackpad, and wifi.
    
    Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0
    Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298169
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/Kconfig           |  1 +
 src/soc/intel/skylake/acpi.c            | 21 +++++++++++++++++++++
 src/soc/intel/skylake/acpi/platform.asl | 21 +++------------------
 3 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 07c1d41..1ccde4a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
 	select RELOCATABLE_MODULES
 	select RELOCATABLE_RAMSTAGE
 	select SOC_INTEL_COMMON
+	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_FSP_RAM_INIT
 	select SOC_INTEL_COMMON_FSP_ROMSTAGE
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 18cd2d9..f2ab534 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -37,6 +37,7 @@
 #include <cpu/intel/turbo.h>
 #include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/gnvs.h>
+#include <soc/intel/common/acpi.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
@@ -604,6 +605,26 @@ void southcluster_inject_dsdt(device_t device)
 	}
 }
 
+/* Save wake source information for calculating ACPI _SWS values */
+int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
+{
+	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+	static uint32_t gpe0_sts[GPE0_REG_MAX];
+	uint32_t pm1_en;
+	int i;
+
+	/* PM1_EN state is lost in Deep S3 so enable basic wake events */
+	pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS;
+	*pm1 = ps->pm1_sts & pm1_en;
+
+	/* Mask off GPE0 status bits that are not enabled */
+	*gpe0 = &gpe0_sts[0];
+	for (i = 0; i < GPE0_REG_MAX; i++)
+		gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
+
+	return GPE0_REG_MAX;
+}
+
 __attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs)
 {
 }
diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl
index f0ed4e0..24df241 100644
--- a/src/soc/intel/skylake/acpi/platform.asl
+++ b/src/soc/intel/skylake/acpi/platform.asl
@@ -19,6 +19,9 @@
  * Foundation, Inc.
  */
 
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
 /* The APM port can be used for generating software SMIs */
 
 OperationRegion (APMP, SystemIO, 0xb2, 2)
@@ -83,21 +86,3 @@ Method (_WAK, 1)
 {
 	Return (Package (){ 0, 0 })
 }
-
-Scope (\_SB)
-{
-	Method (_SWS)
-	{
-		/* Index into PM1 for device that caused wake */
-		Return (\PM1I)
-	}
-}
-
-Scope (\_GPE)
-{
-	Method (_SWS)
-	{
-		/* Index into GPE for device that caused wake */
-		Return (\GPEI)
-	}
-}


From gerrit at coreboot.org  Tue Sep 15 19:39:41 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:41 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: braswell:
	Switch to using common ACPI _SWS code
References: <I41c2a141c15f78dc0d9482954c157f81bd0759fa+0@gerrit.coreboot.org>
Message-ID: <I41c2a141c15f78dc0d9482954c157f81bd0759fa+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11649

-gerrit

commit a4c0c4aa5e2d60299de3146ae541d721b2f6bade
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:16:34 2015 -0700

    braswell: Switch to using common ACPI _SWS code
    
    Switch braswell to use the common code for filling out the NVS
    data used by ACPI _SWS methods.  This code was out of date on
    braswell so also update it to provide the \_GPE.SWS method.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-cyan coreboot
    
    Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0
    Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298230
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/braswell/Kconfig            |  1 +
 src/soc/intel/braswell/acpi/globalnvs.asl |  3 ++-
 src/soc/intel/braswell/acpi/platform.asl  |  9 +++------
 src/soc/intel/braswell/include/soc/nvs.h  |  5 +++--
 src/soc/intel/braswell/ramstage.c         | 29 ++++++++---------------------
 5 files changed, 17 insertions(+), 30 deletions(-)

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index ab99a08..361a9c4 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PLATFORM_USES_FSP1_1
 	select REG_SCRIPT
 	select SOC_INTEL_COMMON
+	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_FSP_RAM_INIT
 	select SOC_INTEL_COMMON_FSP_ROMSTAGE
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index fe131f9..f37bf45 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -53,7 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TLVL,	 8,	/* 0x13 - Throttle Level */
 	PPCM,	 8,	/* 0x14 - Maximum P-state usable by OS */
 	PM1I,	 32,	/* 0x15 - System Wake Source - PM1 Index */
-	BDID,	 8,	/* 0x19 - Board ID */
+	GPEI,	 32,	/* 0x19 - GPE Wake Source */
+	BDID,	 8,	/* 0x1d - Board ID */
 
 	/* Device Config */
 	Offset (0x20),
diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl
index 33be9ee..6f5e662 100644
--- a/src/soc/intel/braswell/acpi/platform.asl
+++ b/src/soc/intel/braswell/acpi/platform.asl
@@ -18,6 +18,9 @@
  * Foundation, Inc.
  */
 
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
 /* The APM port can be used for generating software SMIs */
 
 OperationRegion (APMP, SystemIO, 0xb2, 2)
@@ -72,9 +75,3 @@ Method(_WAK,1)
 {
 	Return(Package(){0,0})
 }
-
-Method (_SWS)
-{
-	/* Index into PM1 for device that caused wake */
-	Return (\PM1I)
-}
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 9492f2c..23bd719 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -46,8 +46,9 @@ typedef struct {
 	u8	tlvl; /* 0x13 - Throttle Level */
 	u8	ppcm; /* 0x14 - Maximum P-state usable by OS */
 	u32	pm1i; /* 0x15 - System Wake Source - PM1 Index */
-	u8	bdid; /* 0x19 - Board ID */
-	u8	rsvd1[6];
+	u32	gpei; /* 0x19 - GPE Wake Source */
+	u8	bdid; /* 0x1d - Board ID */
+	u8	rsvd1[2];
 
 	/* Device Config */
 	u8	s5u0; /* 0x20 - Enable USB0 in S5 */
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 26c23bc..2454c6b 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -39,6 +39,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/ramstage.h>
+#include <soc/intel/common/acpi.h>
 #include <soc/intel/common/ramstage.h>
 #include <boardid.h>
 #include <stdlib.h>
@@ -142,30 +143,18 @@ static inline void set_acpi_sleep_type(int val)
 #endif
 }
 
-/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
-static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
+/* Save wake source information for calculating ACPI _SWS values */
+int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
 {
 	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
-	uint16_t pm1;
+	static uint32_t gpe0_sts;
 
-	if (!ps)
-		return;
-
-	pm1 = ps->pm1_sts & ps->pm1_en;
-
-	/* Scan for first set bit in PM1 */
-	for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
-		if (pm1 & 1)
-			break;
-		pm1 >>= 1;
-	}
+	*pm1 = ps->pm1_sts & ps->pm1_en;
 
-	/* If unable to determine then return -1 */
-	if (gnvs->pm1i >= 16)
-		gnvs->pm1i = -1;
+	gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
+	*gpe0 = &gpe0_sts;
 
-	printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n",
-	       gnvs->pm1i);
+	return 1;
 }
 
 static void s3_resume_prepare(void)
@@ -184,8 +173,6 @@ static void s3_resume_prepare(void)
 	}
 
 	set_acpi_sleep_type(3);
-
-	s3_save_acpi_wake_source(gnvs);
 }
 
 static void set_board_id(void)


From gerrit at coreboot.org  Tue Sep 15 19:39:45 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:45 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Enable
	wake-on-wifi
References: <I989768615e9da8ecf6354852d2db7aae8069aa82+0@gerrit.coreboot.org>
Message-ID: <I989768615e9da8ecf6354852d2db7aae8069aa82+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11650

-gerrit

commit 4d05af1df7939fd63ebd855da9c55d4fda8b9796
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:24:20 2015 -0700

    glados: Enable wake-on-wifi
    
    - Assign GPE DW0 to GPP_B block
    - Enable GPP_B16 as ACPI_SCI for wake
    - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW
    
    Note that current designs cannot wake from Deep S3 via wifi.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=tested on glados:
    1-disable deep s3 in devicetree.cb
    2-enable magic packet with "iw phy phy0 wowlan enable magic-packet"
    3-powerd_dbus_suspend to go to S3
    4-wake system with magic packet
    
    Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2
    Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298231
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi/mainboard.asl | 13 +++++++++++++
 src/mainboard/google/glados/devicetree.cb      |  2 +-
 src/mainboard/google/glados/gpio.h             |  7 +++++--
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
index 0184a6a..038a4ef 100644
--- a/src/mainboard/google/glados/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -57,6 +57,19 @@ Scope (\_SB.PCI0.LPCB)
 	#include <drivers/pc80/tpm/acpi/tpm.asl>
 }
 
+/*
+ * WLAN connected to Root Port 1
+ */
+Scope (\_SB.PCI0.RP01)
+{
+	Device (WLAN)
+	{
+		Name (_ADR, 0x00000000)
+		Name (_DDR, "Wireless LAN")
+		Name (_PRW, Package () { GPE_WLAN_WAKE, 3 })
+	}
+}
+
 Scope (\_SB.PCI0.I2C0)
 {
 	/* Touchscreen */
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 60966c7..e57c490 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -9,7 +9,7 @@ chip soc/intel/skylake
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_C"
+	register "gpe0_dw0" = "GPP_B"
 	register "gpe0_dw1" = "GPP_D"
 	register "gpe0_dw2" = "GPP_E"
 
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index fb37b3b..c3d0835 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -38,12 +38,15 @@
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE		GPE0_LAN_WAK
 
+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_WLAN_WAKE		GPE0_DW0_16
+
 /* Input device interrupt configuration */
 #define TOUCHPAD_INT_L		GPP_B3_IRQ
 #define TOUCHSCREEN_INT_L	GPP_E7_IRQ
 #define MIC_INT_L		GPP_F10_IRQ
 
-/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
 #define EC_SCI_GPI		GPE0_DW2_16
 #define EC_SMI_GPI		GPP_E15
 
@@ -90,7 +93,7 @@ static const struct pad_config gpio_table[] = {
 /* PLTRST# */		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 /* SPKR */		/* GPP_B14 */
 /* GSPI0_CS# */		/* GPP_B15 */
-/* GSPI0_CLK */		PAD_CFG_GPI_APIC(GPP_B16, NONE, DEEP), /* WLAN WAKE */
+/* GSPI0_CLK */		PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */
 /* GSPI0_MISO */	/* GPP_B17 */
 /* GSPI0_MOSI */	/* GPP_B18 */
 /* GSPI1_CS# */		/* GPP_B19 */


From gerrit at coreboot.org  Tue Sep 15 19:39:48 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:48 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Enable wake-on-wifi
References: <I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48+0@gerrit.coreboot.org>
Message-ID: <I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11651

-gerrit

commit d8823c134fbc0058352df8b7ebed0af8f25c30ad
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:28:21 2015 -0700

    kunimitsu: Enable wake-on-wifi
    
    - Assign GPE DW0 to GPP_B block
    - Enable GPP_B16 as ACPI_SCI for wake
    - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW
    
    Note that current designs cannot wake from Deep S3 via wifi.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529
    Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298232
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 13 +++++++++++++
 src/mainboard/intel/kunimitsu/devicetree.cb      |  2 +-
 src/mainboard/intel/kunimitsu/gpio.h             |  7 +++++--
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
index dce1371..73193dd 100644
--- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
+++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
@@ -58,6 +58,19 @@ Scope (\_SB.PCI0.LPCB)
 	#include <drivers/pc80/tpm/acpi/tpm.asl>
 }
 
+/*
+ * WLAN connected to Root Port 1
+ */
+Scope (\_SB.PCI0.RP01)
+{
+	Device (WLAN)
+	{
+		Name (_ADR, 0x00000000)
+		Name (_DDR, "Wireless LAN")
+		Name (_PRW, Package () { GPE_WLAN_WAKE, 3 })
+	}
+}
+
 Scope (\_SB.PCI0.I2C0)
 {
 	/* Touchscreen */
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 4e99d68..21af62a 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -9,7 +9,7 @@ chip soc/intel/skylake
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_C"
+	register "gpe0_dw0" = "GPP_B"
 	register "gpe0_dw1" = "GPP_D"
 	register "gpe0_dw2" = "GPP_E"
 
diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index 87380d2..1441738 100755
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -39,12 +39,15 @@
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE		GPE0_LAN_WAK
 
+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_WLAN_WAKE		GPE0_DW0_16
+
 /* Input device interrupt configuration */
 #define TOUCHPAD_INT_L		GPP_B3_IRQ
 #define TOUCHSCREEN_INT_L	GPP_E7_IRQ
 #define MIC_INT_L		GPP_F10_IRQ
 
-/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
 #define EC_SCI_GPI		GPE0_DW2_16
 #define EC_SMI_GPI		GPP_E15
 
@@ -91,7 +94,7 @@ static const struct pad_config gpio_table[] = {
 /* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 /* GPP_B_14_SPKR */	PAD_CFG_GPI(GPP_B14, NONE, DEEP),
 /* GSPI0_CS# */		/* GPP_B15 */
-/* WLAN_PCIE_WAKE */	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+/* WLAN_PCIE_WAKE */	PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
 /* SSD_PCIE_WAKE */	PAD_CFG_GPI(GPP_B17, NONE, DEEP),
 /* GSPI0_MOSI */	/* GPP_B18 */
 /* CCODEC_SPI_CS */	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),


From gerrit at coreboot.org  Tue Sep 15 19:39:50 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:50 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Remove
	code to set USB charge behavior on sleep
References: <Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3+0@gerrit.coreboot.org>
Message-ID: <Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11652

-gerrit

commit 9705ae4bb1f5b9cc7684aec5e91247dd7be71fd4
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:29:58 2015 -0700

    glados: Remove code to set USB charge behavior on sleep
    
    The EC doesn't support these commands so sending them is
    not working.  We have had a default policy of wake on USB
    for a long time now and this runtime config isn't really
    needed any longer.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655
    Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298233
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/smihandler.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c
index 041d5dc..2a90089 100644
--- a/src/mainboard/google/glados/smihandler.c
+++ b/src/mainboard/google/glados/smihandler.c
@@ -87,27 +87,12 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts)
 void mainboard_smi_sleep(u8 slp_typ)
 {
 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case 3:
-		if (smm_get_gnvs()->s3u0 == 0) {
-			google_chromeec_set_usb_charge_mode(
-				0, USB_CHARGE_MODE_DISABLED);
-			google_chromeec_set_usb_charge_mode(
-				1, USB_CHARGE_MODE_DISABLED);
-		}
-
 		/* Enable wake events */
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
 		break;
 	case 5:
-		if (smm_get_gnvs()->s5u0 == 0) {
-			google_chromeec_set_usb_charge_mode(
-				0, USB_CHARGE_MODE_DISABLED);
-			google_chromeec_set_usb_charge_mode(
-				1, USB_CHARGE_MODE_DISABLED);
-		}
-
 		/* Enable wake events */
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
 		break;


From gerrit at coreboot.org  Tue Sep 15 19:39:53 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:53 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu:
	Remove code to set USB charge behavior on sleep
References: <I547d92b4e852664567792060bf1f7b60976bb9a6+0@gerrit.coreboot.org>
Message-ID: <I547d92b4e852664567792060bf1f7b60976bb9a6+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11653

-gerrit

commit a10bea29af7a138f52e79fd98189ed1f04f50b29
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:31:09 2015 -0700

    kunimitsu: Remove code to set USB charge behavior on sleep
    
    The EC doesn't support these commands so sending them is
    not working.  We have had a default policy of wake on USB
    for a long time now and this runtime config isn't really
    needed any longer.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I547d92b4e852664567792060bf1f7b60976bb9a6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4a929eb9ec422e145006505ea4d5fbd1ef3950be
    Original-Change-Id: I01e80de65e6e1cdcabb24edb43bc671f5a8aa437
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298234
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/smihandler.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c
index 1662144..c2f9d81 100644
--- a/src/mainboard/intel/kunimitsu/smihandler.c
+++ b/src/mainboard/intel/kunimitsu/smihandler.c
@@ -87,27 +87,12 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts)
 void mainboard_smi_sleep(u8 slp_typ)
 {
 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case 3:
-		if (smm_get_gnvs()->s3u0 == 0) {
-			google_chromeec_set_usb_charge_mode(
-				0, USB_CHARGE_MODE_DISABLED);
-			google_chromeec_set_usb_charge_mode(
-				1, USB_CHARGE_MODE_DISABLED);
-		}
-
 		/* Enable wake events */
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
 		break;
 	case 5:
-		if (smm_get_gnvs()->s5u0 == 0) {
-			google_chromeec_set_usb_charge_mode(
-				0, USB_CHARGE_MODE_DISABLED);
-			google_chromeec_set_usb_charge_mode(
-				1, USB_CHARGE_MODE_DISABLED);
-		}
-
 		/* Enable wake events */
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
 		break;


From gerrit at coreboot.org  Tue Sep 15 19:39:55 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:55 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: vbnv: check
	alignment of nvram in advance
References: <I3add4671ed354d9763e21bf96616c8aeca0cb777+0@gerrit.coreboot.org>
Message-ID: <I3add4671ed354d9763e21bf96616c8aeca0cb777+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11654

-gerrit

commit cf784386b64bb61fd46079ec241b481c4f01f388
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Fri Sep 4 14:32:49 2015 -0700

    vbnv: check alignment of nvram in advance
    
    Currently, erase operation only works if the region is sector-aligned.
    These asserts ensure we can erase the region when it's all used up.
    
    Erase operation can be updated to handle unaligned erases by read,
    update, write-back cycle. However, these asserts will still remain useful
    in case the adjacent region contains critical data and mis-updating it
    can cause a critical failure.
    
    Additionaly we should write a FAFT test but it's more reliable to catch
    it here since FAFT can fail in many ways.
    
    BUG=none
    BRANCH=master
    TEST=tested on samus using misaligned nvram region
    
    Change-Id: I3add4671ed354d9763e21bf96616c8aeca0cb777
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fc001a4d3446cf96b76367dde492c3453aa948c6
    Original-Change-Id: Ib4df8f620bf7531b345364fa4c3e274aba09f677
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297801
---
 src/vendorcode/google/chromeos/vbnv_flash.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/vendorcode/google/chromeos/vbnv_flash.c b/src/vendorcode/google/chromeos/vbnv_flash.c
index 656c3ea..0ee9eaa 100644
--- a/src/vendorcode/google/chromeos/vbnv_flash.c
+++ b/src/vendorcode/google/chromeos/vbnv_flash.c
@@ -19,6 +19,7 @@
  * TODO: Make this CAR-friendly in case we use it on x86 some day.
  */
 
+#include <assert.h>
 #include <console/console.h>
 #include <spi_flash.h>
 #include <string.h>
@@ -111,6 +112,23 @@ static int init_vbnv(void)
 	return 0;
 }
 
+static void vbnv_is_erasable(void)
+{
+	/*
+	 * We check whether the region is aligned or not in advance to ensure
+	 * we can erase the region when it's all used up.
+	 *
+	 * The region offset & size are determined by fmap.dts yet the check can
+	 * be confidently done only by the spi flash driver. We use the same
+	 * check as the one used by spi_flash_cmd_erase, which happens to be
+	 * common to all the spi flash parts we support.
+	 *
+	 * TODO: Check by calling can_erase implemented by each spi flash driver
+	 */
+	assert(!(region_device_offset(&nvram_region) % spi_flash->sector_size));
+	assert(!(region_device_sz(&nvram_region) % spi_flash->sector_size));
+}
+
 static int vbnv_flash_probe(void)
 {
 	if (!spi_flash) {
@@ -119,6 +137,11 @@ static int vbnv_flash_probe(void)
 			printk(BIOS_ERR, "failed to probe spi flash\n");
 			return 1;
 		}
+		/*
+		 * Called here instead of init_vbnv to reduce impact on boot
+		 * speed.
+		 */
+		vbnv_is_erasable();
 	}
 	return 0;
 }


From gerrit at coreboot.org  Tue Sep 15 19:39:58 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:39:58 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Skylake:
	Creating "RtcLock" Silicon UPD from Coreboot
References: <I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7+0@gerrit.coreboot.org>
Message-ID: <I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11655

-gerrit

commit f2a26ee577006da2e0215664b79515745458fb48
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Tue Sep 8 16:00:46 2015 +0530

    Skylake: Creating "RtcLock" Silicon UPD from Coreboot
    
    FSP should not lock CMOS unconditionally. Coreboot sends Silicon
    UPD parameter "RtcLock" to FSP to take action on CMOS
    region locking/un-locking.This patch has CB generec code for
    creating the Silicon UPD paramater.
    
    BUG=chrome-os-partner:44484
    BRANCH=none
    TEST=Build and booted in kunimitsu, tested using below command-
    When DIsabled RtcLock from devicetree in coreboot, booted to kernel
    and run following commands -
    >> crossystem fw_result=success
    >> crossystem | grep fw_result
    It should reflect the value that is set. Here, success.
    If ENabled RtcLock from Coreboot devicetree, The same commands will
    fail to update the fw_result status from crossystem utility.
    CQ-DEPEND=CL:*229144
    
    Change-Id: I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c7b8293a2c55117d7ca2001ac9ec0de24d35b80b
    Original-Change-Id: If708e2c782644dcf7f03785d1bfa235ef5385d80
    Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297980
    Original-Commit-Ready: Subrata Banik <subrata.banik at intel.com>
    Original-Tested-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.c | 3 +++
 src/soc/intel/skylake/chip.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index afb0ff6..fd959b2 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -94,6 +94,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->DspEnable = config->DspEnable;
 	params->XdciEnable = config->XdciEnable;
 	params->Device4Enable = config->Device4Enable;
+	params->RtcLock = config->RtcLock;
 
 	/* Show SPI controller if enabled in devicetree.cb */
 	dev = dev_find_slot(0, PCH_DEVFN_SPI);
@@ -265,6 +266,8 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
 		params->HsioMessaging);
 	soc_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled,
 		params->Heci3Enabled);
+	soc_display_upd_value("RtcLock", 1, original->RtcLock,
+		params->RtcLock);
 }
 
 static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 94aa3a4..95f9502 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -229,6 +229,7 @@ struct soc_intel_skylake_config {
 	u32 LogoSize;
 	u32 GraphicsConfigPtr;
 	u8 Device4Enable;
+	u8 RtcLock;
 };
 
 typedef struct soc_intel_skylake_config config_t;


From gerrit at coreboot.org  Tue Sep 15 19:40:00 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:00 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: t210:
	lp0_resume: Configure unused SDMMC1/3 pads for low power leakage
References: <If5d5cebc89b8220480b3c72293a410e782eb437e+0@gerrit.coreboot.org>
Message-ID: <If5d5cebc89b8220480b3c72293a410e782eb437e+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11656

-gerrit

commit c4984569f6a3561558929f433c89905bc84ccb00
Author: Yen Lin <yelin at nvidia.com>
Date:   Tue Sep 8 15:13:13 2015 -0700

    t210: lp0_resume: Configure unused SDMMC1/3 pads for low power leakage
    
    In LP0 resume, a couple of SDMMCx pad settings need to be set to 0 to
    reduce power leakage.
    
    BUG=None
    BRANCH=None
    TEST=Tested on Smaug; able to suspend/resume >100 times
    
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9f35a90a8af2180443db2c4be75d4566d0990de5
    Original-Change-Id: Ifc946b0cea437ef0807cea0c11609d8e09387e8e
    Original-Signed-off-by: Yen Lin <yelin at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298195
    Original-Reviewed-by: Andrew Bresticker <abrestic at chromium.org>
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Tested-by: Joseph Lo <josephl at nvidia.com>
    Original-(cherry picked from commit be3ac49a6bc4c9088d3799555d69c87c8ce1693c)
    Original-Reviewed-on: https://chromium-review.googlesource.com/298154
    Original-Commit-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    
    Change-Id: If5d5cebc89b8220480b3c72293a410e782eb437e
---
 src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 50 ++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 956e8c5..87e42e3 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -30,6 +30,8 @@ enum {
 	PMC_CTLR_BASE = 0x7000e400,
 	MC_CTLR_BASE = 0x70019000,
 	FUSE_BASE = 0x7000F800,
+	TEGRA_SDMMC1_BASE = 0x700b0000,
+	TEGRA_SDMMC3_BASE = 0x700b0400,
 	EMC_BASE = 0x7001B000,
 	I2C5_BASE = 0x7000D000,
 	I2S_BASE = 0x702d1000
@@ -79,6 +81,8 @@ enum {
 	SWR_TRIG_SYS_RST = 0x1 << 2
 };
 
+static uint32_t *clk_rst_rst_devices_u_ptr = (void *)(CLK_RST_BASE + 0xc);
+
 static uint32_t *clk_rst_cclkg_burst_policy_ptr = (void *)(CLK_RST_BASE + 0x368);
 enum {
 	CCLKG_PLLP_BURST_POLICY = 0x20004444
@@ -810,6 +814,49 @@ static void mbist_workaround(void)
 		write32(clk_rst_clk_enb_w_set_ptr, CLK_ENB_MC1);
 }
 
+static uint32_t *sdmmc1_vendor_io_trim = (void *)(TEGRA_SDMMC1_BASE + 0x1ac);
+static uint32_t *sdmmc3_vendor_io_trim = (void *)(TEGRA_SDMMC3_BASE + 0x1ac);
+static uint32_t *sdmmc1_comppadctrl = (void *)(TEGRA_SDMMC1_BASE + 0x1e0);
+static uint32_t *sdmmc3_comppadctrl = (void *)(TEGRA_SDMMC3_BASE + 0x1e0);
+
+enum {
+	SDMMC1_DEV_L = 0x1 << 14,
+	SDMMC3_DEV_U = 0x1 << 5,
+	PAD_E_INPUT_COMPPADCTRL = 0x1 << 31,
+	SEL_VREG_VENDOR_IO_TRIM = 0x1 << 2
+};
+
+static void low_power_sdmmc_pads(void)
+{
+	/* Enable SDMMC1 clock */
+	setbits32(SDMMC1_DEV_L, clk_rst_clk_out_enb_l_ptr);
+	udelay(2);
+	/* Unreset SDMMC1 */
+	clrbits32(SDMMC1_DEV_L, clk_rst_rst_devices_l_ptr);
+
+	/* Clear SEL_VREG bit and PAD_E_INPUT bit of SDMMC1 */
+	clrbits32(SEL_VREG_VENDOR_IO_TRIM, sdmmc1_vendor_io_trim);
+	clrbits32(PAD_E_INPUT_COMPPADCTRL, sdmmc1_comppadctrl);
+	/* Read the last accessed SDMMC1 register then disable SDMMC1 clock */
+	read32(sdmmc1_comppadctrl);
+	/* Disable SDMMC1 clock, but keep SDMMC1 un-reset */
+	clrbits32(SDMMC1_DEV_L, clk_rst_clk_out_enb_l_ptr);
+
+	/* Enable SDMMC3 clock */
+	setbits32(SDMMC3_DEV_U, clk_rst_clk_out_enb_u_ptr);
+	udelay(2);
+	/* Unreset SDMMC3 */
+	clrbits32(SDMMC3_DEV_U, clk_rst_rst_devices_u_ptr);
+
+	/* Clear SEL_VREG bit and PAD_E_INPUT bit of SDMMC3 */
+	clrbits32(SEL_VREG_VENDOR_IO_TRIM, sdmmc3_vendor_io_trim);
+	clrbits32(PAD_E_INPUT_COMPPADCTRL, sdmmc3_comppadctrl);
+	/* Read the last accessed SDMMC3 register then disable SDMMC3 clock */
+	read32(sdmmc3_comppadctrl);
+	/* Disable SDMMC3 clock, but keep SDMMC3 un-reset */
+	clrbits32(SDMMC3_DEV_U, clk_rst_clk_out_enb_u_ptr);
+}
+
 static void config_mselect(void)
 {
 	/* Set MSELECT clock source to PLL_P with 1:4 divider */
@@ -895,6 +942,9 @@ void lp0_resume(void)
 	/* Restore CAR CE's, SLCG overrides */
 	mbist_workaround();
 
+	/* Configure unused SDMMC1/3 pads for low power leakage */
+	low_power_sdmmc_pads();
+
 	/*
 	 * Find out which CPU (slow or fast) to wake up. The default setting
 	 * in flow controller is to wake up GCPU


From gerrit at coreboot.org  Tue Sep 15 19:40:02 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:02 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	glados/kunimitsu: remove the implementation of
	mainboard_add_dimm_info
References: <I949e287372b190affac36a0efde8a30402eecdc8+0@gerrit.coreboot.org>
Message-ID: <I949e287372b190affac36a0efde8a30402eecdc8+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11657

-gerrit

commit 6ca9b9351bb7b29060c013649ebe0d9727fbbfc0
Author: robbie zhang <robbie.zhang at intel.com>
Date:   Thu Sep 10 16:24:44 2015 -0700

    glados/kunimitsu: remove the implementation of mainboard_add_dimm_info
    
    This is a follow-up patch to
    https://chromium-review.googlesource.com/#/c/286877, after fsp support
    is landed in v1.5.
    
    BUG=chrome-os-partner:42975
    BRANCH=none
    TEST=execute "mosys memory spd print all" on glados and kunimitsu
    
    Change-Id: I949e287372b190affac36a0efde8a30402eecdc8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa
    Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3
    Original-Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298967
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/glados/romstage.c   | 16 ----------------
 src/mainboard/intel/kunimitsu/romstage.c | 16 ----------------
 2 files changed, 32 deletions(-)

diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
index 315ddb9..69e6e0d 100644
--- a/src/mainboard/google/glados/romstage.c
+++ b/src/mainboard/google/glados/romstage.c
@@ -21,7 +21,6 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include <memory_info.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
 #include <soc/gpio.h>
@@ -77,18 +76,3 @@ void mainboard_memory_init_params(struct romstage_params *params,
 	memory_params->MemorySpdDataLen = SPD_LEN;
 	memory_params->DqPinsInterleaved = FALSE;
 }
-
-void mainboard_add_dimm_info(struct romstage_params *params,
-			     struct memory_info *mem_info,
-			     int channel, int dimm, int index)
-{
-	/* Set the manufacturer */
-	memcpy(&mem_info->dimm[index].mod_id,
-	       &params->pei_data->spd_data[channel][dimm][SPD_MANU_OFF],
-	       sizeof(mem_info->dimm[index].mod_id));
-
-	/* Set the module part number */
-	memcpy(mem_info->dimm[index].module_part_number,
-	       &params->pei_data->spd_data[channel][dimm][SPD_PART_OFF],
-	       sizeof(mem_info->dimm[index].module_part_number));
-}
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c
index af16dce..a0eeafc 100644
--- a/src/mainboard/intel/kunimitsu/romstage.c
+++ b/src/mainboard/intel/kunimitsu/romstage.c
@@ -21,7 +21,6 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include <memory_info.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
 #include <soc/gpio.h>
@@ -77,18 +76,3 @@ void mainboard_memory_init_params(struct romstage_params *params,
 	memory_params->MemorySpdDataLen = SPD_LEN;
 	memory_params->DqPinsInterleaved = FALSE;
 }
-
-void mainboard_add_dimm_info(struct romstage_params *params,
-			     struct memory_info *mem_info,
-			     int channel, int dimm, int index)
-{
-	/* Set the manufacturer */
-	memcpy(&mem_info->dimm[index].mod_id,
-	       &params->pei_data->spd_data[channel][dimm][SPD_MANU_OFF],
-	       sizeof(mem_info->dimm[index].mod_id));
-
-	/* Set the module part number */
-	memcpy(mem_info->dimm[index].module_part_number,
-	       &params->pei_data->spd_data[channel][dimm][SPD_PART_OFF],
-	       sizeof(mem_info->dimm[index].module_part_number));
-}


From gerrit at coreboot.org  Tue Sep 15 19:40:04 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:04 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: ifdtool:
	Properly set + decode flmstr regs for IFD v2
References: <I8a65bdc5edd0d888138b88c1189f8badd1404b64+0@gerrit.coreboot.org>
Message-ID: <I8a65bdc5edd0d888138b88c1189f8badd1404b64+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11658

-gerrit

commit 3f788da25cd79a349d07279cd24a7fbb16a11c4d
Author: Shawn Nematbakhsh <shawnn at chromium.org>
Date:   Thu Sep 10 19:07:13 2015 -0700

    ifdtool: Properly set + decode flmstr regs for IFD v2
    
    flmstr register bits have slightly different meaning for IFD v2.
    
    BUG=chrome-os-partner:45091, chrome-os-partner:43461
    TEST=Run `ifdtool -d image.bin` on IFD v1 locked squawks image:
    
    Found Master Section
    FLMSTR1:   0x0a0b0000 (Host CPU/BIOS)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      disabled
      Host CPU/BIOS Region Write Access: enabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       disabled
      Host CPU/BIOS Region Read Access:  enabled
      Flash Descriptor Read Access:      enabled
      Requester ID:                      0x0000
    
    FLMSTR2:   0x0c0d0000 (Intel ME)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      enabled
      Host CPU/BIOS Region Write Access: disabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       enabled
      Host CPU/BIOS Region Read Access:  disabled
      Flash Descriptor Read Access:      enabled
      Requester ID:                      0x0000
    
    FLMSTR3:   0x08080118 (GbE)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      disabled
      Host CPU/BIOS Region Write Access: disabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       disabled
      Host CPU/BIOS Region Read Access:  disabled
      Flash Descriptor Read Access:      disabled
      Requester ID:                      0x0118
    
    Then, run `ifdtool -l image.bin` and verify newly locked image is identical.
    Next, run `ifdtool -l image.bin` on unlocked glados image. Verify that locked
    and unlocked regions are identical to above.
    Finally, burn glados image, run `flashrom -V`, and verify ME regions is
    locked and descriptor region is RO.
    BRANCH=None
    
    Change-Id: I8a65bdc5edd0d888138b88c1189f8badd1404b64
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 11c434835a66a50ab2c0c01a084edc96cbe052da
    Original-Signed-off-by: Shawn Nematbakhsh <shawnn at chromium.org>
    Original-Change-Id: I875dfce6f5cf57831714702872bfe636f8f953f4
    Original-Reviewed-on: https://chromium-review.googlesource.com/298968
    Original-Commit-Ready: Shawn N <shawnn at chromium.org>
    Original-Tested-by: Shawn N <shawnn at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 util/ifdtool/ifdtool.c | 91 +++++++++++++++++++++++++++++++++++++++-----------
 util/ifdtool/ifdtool.h |  9 +++++
 2 files changed, 80 insertions(+), 20 deletions(-)

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index e6ed110..feaffa8 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -443,36 +443,50 @@ static void dump_fpsba(fpsba_t * fpsba)
 
 static void decode_flmstr(uint32_t flmstr)
 {
+	int wr_shift, rd_shift;
+	if (ifd_version >= IFD_VERSION_2) {
+		wr_shift = FLMSTR_WR_SHIFT_V2;
+		rd_shift = FLMSTR_RD_SHIFT_V2;
+	} else {
+		wr_shift = FLMSTR_WR_SHIFT_V1;
+		rd_shift = FLMSTR_RD_SHIFT_V1;
+	}
+
+	/* EC region access only available on v2+ */
 	if (ifd_version >= IFD_VERSION_2)
 		printf("  EC Region Write Access:            %s\n",
-		       (flmstr & (1 << 29)) ? "enabled" : "disabled");
+		       (flmstr & (1 << (wr_shift + 8))) ?
+		       "enabled" : "disabled");
 	printf("  Platform Data Region Write Access: %s\n",
-		(flmstr & (1 << 28)) ? "enabled" : "disabled");
+		(flmstr & (1 << (wr_shift + 4))) ? "enabled" : "disabled");
 	printf("  GbE Region Write Access:           %s\n",
-		(flmstr & (1 << 27)) ? "enabled" : "disabled");
+		(flmstr & (1 << (wr_shift + 3))) ? "enabled" : "disabled");
 	printf("  Intel ME Region Write Access:      %s\n",
-		(flmstr & (1 << 26)) ? "enabled" : "disabled");
+		(flmstr & (1 << (wr_shift + 2))) ? "enabled" : "disabled");
 	printf("  Host CPU/BIOS Region Write Access: %s\n",
-		(flmstr & (1 << 25)) ? "enabled" : "disabled");
+		(flmstr & (1 << (wr_shift + 1))) ? "enabled" : "disabled");
 	printf("  Flash Descriptor Write Access:     %s\n",
-		(flmstr & (1 << 24)) ? "enabled" : "disabled");
+		(flmstr & (1 << wr_shift)) ? "enabled" : "disabled");
 
 	if (ifd_version >= IFD_VERSION_2)
 		printf("  EC Region Read Access:             %s\n",
-		       (flmstr & (1 << 21)) ? "enabled" : "disabled");
+		       (flmstr & (1 << (rd_shift + 8))) ?
+		       "enabled" : "disabled");
 	printf("  Platform Data Region Read Access:  %s\n",
-		(flmstr & (1 << 20)) ? "enabled" : "disabled");
+		(flmstr & (1 << (rd_shift + 4))) ? "enabled" : "disabled");
 	printf("  GbE Region Read Access:            %s\n",
-		(flmstr & (1 << 19)) ? "enabled" : "disabled");
+		(flmstr & (1 << (rd_shift + 3))) ? "enabled" : "disabled");
 	printf("  Intel ME Region Read Access:       %s\n",
-		(flmstr & (1 << 18)) ? "enabled" : "disabled");
+		(flmstr & (1 << (rd_shift + 2))) ? "enabled" : "disabled");
 	printf("  Host CPU/BIOS Region Read Access:  %s\n",
-		(flmstr & (1 << 17)) ? "enabled" : "disabled");
+		(flmstr & (1 << (rd_shift + 1))) ? "enabled" : "disabled");
 	printf("  Flash Descriptor Read Access:      %s\n",
-		(flmstr & (1 << 16)) ? "enabled" : "disabled");
+		(flmstr & (1 << rd_shift)) ? "enabled" : "disabled");
 
-	printf("  Requester ID:                      0x%04x\n\n",
-		flmstr & 0xffff);
+	/* Requestor ID doesn't exist for ifd 2 */
+	if (ifd_version < IFD_VERSION_2)
+		printf("  Requester ID:                      0x%04x\n\n",
+			flmstr & 0xffff);
 }
 
 static void dump_fmba(fmba_t * fmba)
@@ -740,14 +754,43 @@ static void set_em100_mode(char *filename, char *image, int size)
 
 static void lock_descriptor(char *filename, char *image, int size)
 {
+	int wr_shift, rd_shift;
 	fdbar_t *fdb = find_fd(image, size);
 	fmba_t *fmba = (fmba_t *) (image + (((fdb->flmap1) & 0xff) << 4));
 	/* TODO: Dynamically take Platform Data Region and GbE Region
 	 * into regard.
 	 */
-	fmba->flmstr1 = 0x0a0b0000;
-	fmba->flmstr2 = 0x0c0d0000;
-	fmba->flmstr3 = 0x08080118;
+
+	if (ifd_version >= IFD_VERSION_2) {
+		wr_shift = FLMSTR_WR_SHIFT_V2;
+		rd_shift = FLMSTR_RD_SHIFT_V2;
+
+		/* Clear non-reserved bits */
+		fmba->flmstr1 &= 0xff;
+		fmba->flmstr2 &= 0xff;
+		fmba->flmstr3 &= 0xff;
+	} else {
+		wr_shift = FLMSTR_WR_SHIFT_V1;
+		rd_shift = FLMSTR_RD_SHIFT_V1;
+
+		fmba->flmstr1 = 0;
+		fmba->flmstr2 = 0;
+		/* Requestor ID */
+		fmba->flmstr3 = 0x118;
+	}
+
+	/* CPU/BIOS can read descriptor, BIOS, and GbE. */
+	fmba->flmstr1 |= 0xb << rd_shift;
+	/* CPU/BIOS can write BIOS and GbE. */
+	fmba->flmstr1 |= 0xa << wr_shift;
+	/* ME can read descriptor, ME, and GbE. */
+	fmba->flmstr2 |= 0xd << rd_shift;
+	/* ME can write ME and GbE. */
+	fmba->flmstr2 |= 0xc << wr_shift;
+	/* GbE can write only GbE. */
+	fmba->flmstr3 |= 0x8 << rd_shift;
+	/* GbE can read only GbE. */
+	fmba->flmstr3 |= 0x8 << wr_shift;
 
 	write_image(filename, image, size);
 }
@@ -756,9 +799,17 @@ static void unlock_descriptor(char *filename, char *image, int size)
 {
 	fdbar_t *fdb = find_fd(image, size);
 	fmba_t *fmba = (fmba_t *) (image + (((fdb->flmap1) & 0xff) << 4));
-	fmba->flmstr1 = 0xffff0000;
-	fmba->flmstr2 = 0xffff0000;
-	fmba->flmstr3 = 0x08080118;
+
+	if (ifd_version >= IFD_VERSION_2) {
+		/* Access bits for each region are read: 19:8 write: 31:20 */
+		fmba->flmstr1 = 0xffffff00 | (fmba->flmstr1 & 0xff);
+		fmba->flmstr2 = 0xffffff00 | (fmba->flmstr2 & 0xff);
+		fmba->flmstr3 = 0xffffff00 | (fmba->flmstr3 & 0xff);
+	} else {
+		fmba->flmstr1 = 0xffff0000;
+		fmba->flmstr2 = 0xffff0000;
+		fmba->flmstr3 = 0x08080118;
+	}
 
 	write_image(filename, image, size);
 }
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index 8b13283..195d91c 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -101,6 +101,15 @@ typedef struct {
 	uint32_t pchstrp17;
 } __attribute__((packed)) fpsba_t;
 
+/*
+ * WR / RD bits start at different locations within the flmstr regs, but
+ * otherwise have identical meaning.
+ */
+#define FLMSTR_WR_SHIFT_V1 24
+#define FLMSTR_WR_SHIFT_V2 20
+#define FLMSTR_RD_SHIFT_V1 16
+#define FLMSTR_RD_SHIFT_V2 8
+
 // master
 typedef struct {
 	uint32_t flmstr1;


From gerrit at coreboot.org  Tue Sep 15 19:40:07 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:07 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Skylake: update
	C state latency and power numbers
References: <Ia6bd336a71b0313801b59990c78822fa0d789e36+0@gerrit.coreboot.org>
Message-ID: <Ia6bd336a71b0313801b59990c78822fa0d789e36+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11659

-gerrit

commit 38dcdb1a2b26967e44735c187c6b471e87a06c16
Author: robbie zhang <robbie.zhang at intel.com>
Date:   Fri Sep 11 14:25:15 2015 -0700

    Skylake: update C state latency and power numbers
    
    The values are taken from latest BWG as well fsp src.
    
    BRANCH=none
    BUG=chrome-os-partner:45208
    TEST=Built and boot on kunimitsu
    Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    
    Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164
    Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b
    Original-Reviewed-on: https://chromium-review.googlesource.com/299480
    Original-Commit-Ready: Wenkai Du <wenkai.du at intel.com>
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi.c            | 24 ++++++++++++------------
 src/soc/intel/skylake/include/soc/cpu.h | 21 +++++++++++++++------
 2 files changed, 27 insertions(+), 18 deletions(-)

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index f2ab534..471fd17 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -78,62 +78,62 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = {
 	[C_STATE_C0] = { },
 	[C_STATE_C1] = {
 		.latency = 0,
-		.power = 1000,
+		.power = C1_POWER,
 		.resource = MWAIT_RES(0, 0),
 	},
 	[C_STATE_C1E] = {
 		.latency = 0,
-		.power = 1000,
+		.power = C1_POWER,
 		.resource = MWAIT_RES(0, 1),
 	},
 	[C_STATE_C3] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
-		.power = 500,
+		.power = C3_POWER,
 		.resource = MWAIT_RES(1, 0),
 	},
 	[C_STATE_C6_SHORT_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 350,
+		.power = C6_POWER,
 		.resource = MWAIT_RES(2, 0),
 	},
 	[C_STATE_C6_LONG_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 350,
+		.power = C6_POWER,
 		.resource = MWAIT_RES(2, 1),
 	},
 	[C_STATE_C7_SHORT_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 200,
+		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 0),
 	},
 	[C_STATE_C7_LONG_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 200,
+		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 1),
 	},
 	[C_STATE_C7S_SHORT_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 200,
+		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 2),
 	},
 	[C_STATE_C7S_LONG_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 200,
+		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 3),
 	},
 	[C_STATE_C8] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(3),
-		.power = 200,
+		.power = C8_POWER,
 		.resource = MWAIT_RES(4, 0),
 	},
 	[C_STATE_C9] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(4),
-		.power = 200,
+		.power = C9_POWER,
 		.resource = MWAIT_RES(5, 0),
 	},
 	[C_STATE_C10] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(5),
-		.power = 200,
+		.power = C10_POWER,
 		.resource = MWAIT_RES(6, 0),
 	},
 };
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index c62b308..8d5c2a0 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -35,12 +35,21 @@
 #define CPU_BCLK		100
 
 /* Latency times in units of 1024ns. */
-#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
-#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
-#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
-#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
-#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
-#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
+#define C_STATE_LATENCY_CONTROL_0_LIMIT	0x4e
+#define C_STATE_LATENCY_CONTROL_1_LIMIT	0x76
+#define C_STATE_LATENCY_CONTROL_2_LIMIT	0x94
+#define C_STATE_LATENCY_CONTROL_3_LIMIT	0xfa
+#define C_STATE_LATENCY_CONTROL_4_LIMIT	0x14c
+#define C_STATE_LATENCY_CONTROL_5_LIMIT	0x3f2
+
+/* Power in units of mW */
+#define C1_POWER	0x3e8
+#define C3_POWER	0x1f4
+#define C6_POWER	0x15e
+#define C7_POWER	0xc8
+#define C8_POWER	0xc8
+#define C9_POWER	0xc8
+#define C10_POWER	0xc8
 
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)


From gerrit at coreboot.org  Tue Sep 15 19:40:09 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: linking: Repair
	special treatments for non-x86 bootblocks
References: <I54271b8b59a9c773d858d676cde0218cb7f20e74+0@gerrit.coreboot.org>
Message-ID: <I54271b8b59a9c773d858d676cde0218cb7f20e74+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11660

-gerrit

commit 2c079593c8d0f51230480f6e1a04f9bd66da0935
Author: Julius Werner <jwerner at chromium.org>
Date:   Fri Sep 11 16:17:50 2015 -0700

    linking: Repair special treatments for non-x86 bootblocks
    
    Patch b2a62622b (linking: move romstage and bootblock to use program.ld)
    unified the linker scripts between different stages. Unfortunately it
    omitted several special cases from the old bootblock.ld script that are
    required for non-x86 environments.
    
    This patch expands program.ld to once again merge the .BSS into the
    program image for bootblocks (ensuring correct initialization by the
    external loader). It also revives the .id section (which adds a
    human-readable blurb of information to the top of an image) and fixes a
    problem with unintended automated section alignment.
    
    BRANCH=None
    BUG=None
    TEST=Jerry and Oak boot again.
    
    Change-Id: I54271b8b59a9c773d858d676cde0218cb7f20e74
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6fddbc00963e363039634fa31a9b66254b6cf18f
    Original-Change-Id: I4d748056f1ab29a8e730f861879982bdf4c33eab
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/299413
    Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/lib/program.ld | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/src/lib/program.ld b/src/lib/program.ld
index 9f28d65..c8ce5ee 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -23,8 +23,11 @@
 
 /* First we place the code and read only data (typically const declared).
  * This could theoretically be placed in rom.
+ * The '.' in '.text . : {' is actually significant to prevent missing some
+ * SoC's entry points due to artificial alignment restrictions, see
+ * https://sourceware.org/binutils/docs/ld/Output-Section-Address.html
  */
-.text : {
+.text . : {
 	_program = .;
 	_text = .;
 	/*
@@ -35,6 +38,7 @@
 	*(.rom.data);
 	*(.text._start);
 	*(.text.stage_entry);
+	KEEP(*(.id));
 	*(.text);
 	*(.text.*);
 
@@ -64,7 +68,7 @@
 } : to_load
 
 #if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
+.ctors . : {
 	. = ALIGN(0x100)
 	__CTOR_LIST__ = .;
 	KEEP(*(.ctors));
@@ -76,7 +80,7 @@
 
 /* Include data, bss, and heap in that order. Not defined for all stages. */
 #if ARCH_STAGE_HAS_DATA_SECTION
-.data : {
+.data . : {
 	. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
 	_data = .;
 
@@ -107,7 +111,14 @@
 #endif
 
 #if ARCH_STAGE_HAS_BSS_SECTION
-.bss : {
+#if ENV_BOOTBLOCK
+/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
+ * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
+ * the BSS into the .data section so those zeroes get loaded explicitly. */
+.data . : {
+#else
+.bss . : {
+#endif
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bss = .;
 	*(.bss)
@@ -120,7 +131,7 @@
 #endif
 
 #if ARCH_STAGE_HAS_HEAP_SECTION
-.heap : {
+.heap . : {
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_heap = .;
 	. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);


From gerrit at coreboot.org  Tue Sep 15 19:40:11 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:11 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: libpayload:
	usb: dwc2: fix hub hot-plug bug
References: <Ib4604097743f2f9d763b29ee27f3bc1788a85a62+0@gerrit.coreboot.org>
Message-ID: <Ib4604097743f2f9d763b29ee27f3bc1788a85a62+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11661

-gerrit

commit 49d615ca6393de631f78ab622a96ad472e648bc4
Author: Yunzhi Li <lyz at rock-chips.com>
Date:   Fri Aug 28 09:43:44 2015 +0800

    libpayload: usb: dwc2: fix hub hot-plug bug
    
    When disconnect detected in dwc2_split_transfear() split configure
    registers should be cleared before return
    
    BRANCH=None
    BUG=chrome-os-partner:44534
    TEST=tested on Jerry, usb hot plug could be supported in coreboot
    
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 37594d8b4490b6d393d19d17d8e497db7de8817d
    Original-Change-Id: Ie1eecec067305874513c6ceb95df4240dc393cd6
    Original-Signed-off-by: Yunzhi Li <lyz at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295625
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Commit-Queue: Lin Huang <hl at rock-chips.com>
    Original-Tested-by: Lin Huang <hl at rock-chips.com>
    Original-(cherry picked from commit d543e14cdc73bd549dd553c8d1d07672a1307981)
    Original-Reviewed-on: https://chromium-review.googlesource.com/299700
    Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: Ib4604097743f2f9d763b29ee27f3bc1788a85a62
---
 payloads/libpayload/drivers/usb/dwc2.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index 30e00fb..0941eb6 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -323,8 +323,10 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 	do {
 		hfnum.d32 = readl(&reg->host.hfnum);
 
-		if (dwc2_disconnected(ep->dev->controller))
-			return -HCSTAT_DISCONNECTED;
+		if (dwc2_disconnected(ep->dev->controller)) {
+			ret = -HCSTAT_DISCONNECTED;
+			goto out;
+		}
 	} while (hfnum.frnum % 8 != 0);
 
 	/* Handle Start-Split */


From gerrit at coreboot.org  Tue Sep 15 19:40:13 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:13 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: libpayload:
	usb: dwc2: check device connect state before enable channel
References: <Idf48ffbc4c2794900e09dec6b2e34e33b21f87b4+0@gerrit.coreboot.org>
Message-ID: <Idf48ffbc4c2794900e09dec6b2e34e33b21f87b4+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11662

-gerrit

commit b178488b4f71b627d76440de17c5e3d5ca83539a
Author: Yunzhi Li <lyz at rock-chips.com>
Date:   Thu Sep 10 11:42:30 2015 +0800

    libpayload: usb: dwc2: check device connect state before enable channel
    
    If the device has already been disconnected then we shouldn't enable
    host channel to start any transfer, otherwise this channel goes into
    an odd state the channel is enabled but can not be disabled by set
    hcchar.chdis=1. So we need check the device connect status before
    enable channel.
    
    BRANCH=None
    BUG=chrome-os-partner:44534
    TEST=None
    
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: ae3e690b2cd4a9ea8b5766ac873b0e00bf3a23de
    Original-Change-Id: Ib3ecf486649ca11b302144f9c00a5e88424e90fa
    Original-Signed-off-by: Yunzhi Li <lyz at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298402
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Commit-Queue: Lin Huang <hl at rock-chips.com>
    Original-Tested-by: Lin Huang <hl at rock-chips.com>
    Original-(cherry picked from commit ea96f947b5304fdde2e0991d23febaeba209dde1)
    Original-Reviewed-on: https://chromium-review.googlesource.com/299398
    Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: Idf48ffbc4c2794900e09dec6b2e34e33b21f87b4
---
 payloads/libpayload/drivers/usb/dwc2.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index 0941eb6..c51c0e7 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -274,6 +274,9 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 	if (do_copy && (dir == EPDIR_OUT))
 		memcpy(aligned_buf, data_buf, size);
 
+	if (dwc2_disconnected(ep->dev->controller))
+		return -HCSTAT_DISCONNECTED;
+
 	writel(hctsiz.d32, &reg->host.hchn[ch_num].hctsizn);
 	writel((uint32_t)virt_to_bus(aligned_buf),
 		&reg->host.hchn[ch_num].hcdman);


From gerrit at coreboot.org  Tue Sep 15 19:40:15 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:15 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	drivers/intel/fsp1_1: prepare relocation code for sharing
References: <I650a08ffb9caf7e0438a988cae9bec56dd31753c+0@gerrit.coreboot.org>
Message-ID: <I650a08ffb9caf7e0438a988cae9bec56dd31753c+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11663

-gerrit

commit cfea5f208deb009d3c05be18a6902078fafddfcf
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 21:19:25 2015 -0500

    drivers/intel/fsp1_1: prepare relocation code for sharing
    
    In order to integrate fsp 1.1 relocation with cbfstool one
    needs to be able to supply the address to relocate the FSP
    image. Therefore, allow this by returning offset for return
    values. Note that exposed API has not changed.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados. Confirmed relocation values matched.
    
    Change-Id: I650a08ffb9caf7e0438a988cae9bec56dd31753c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 53870b0df809418e9a09e7d380ad2399a09fb4fb
    Original-Change-Id: Ic2ec63681ed4e652e2624b40e132f95d1e5a0887
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298831
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy at intel.com>
---
 src/drivers/intel/fsp1_1/fsp_relocate.c | 60 +++++++++++++++++++++------------
 1 file changed, 38 insertions(+), 22 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
index 2cc2560..351fcc8 100644
--- a/src/drivers/intel/fsp1_1/fsp_relocate.c
+++ b/src/drivers/intel/fsp1_1/fsp_relocate.c
@@ -82,7 +82,7 @@ static size_t reloc_offset(uint16_t reloc_entry)
 	return reloc_entry & ((1 << 12) - 1);
 }
 
-static int te_relocate_in_place(void *te, size_t size)
+static int te_relocate(uintptr_t new_addr, void *te, size_t size)
 {
 	EFI_TE_IMAGE_HEADER *teih;
 	EFI_IMAGE_DATA_DIRECTORY *relocd;
@@ -115,11 +115,11 @@ static int te_relocate_in_place(void *te, size_t size)
 	te_base = te;
 	te_base -= fixup_offset;
 
-	adj = (uintptr_t)te - (teih->ImageBase + fixup_offset);
+	adj = new_addr - (teih->ImageBase + fixup_offset);
 
 	printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n",
 		(void *)(uintptr_t)(teih->ImageBase + fixup_offset),
-		te, adj);
+		(void *)new_addr, adj);
 
 	/* Adjust ImageBase for consistency. */
 	teih->ImageBase = (uint32_t)(teih->ImageBase + adj);
@@ -266,7 +266,8 @@ static int relocate_patch_table(void *fsp, size_t size, size_t offset,
 	return 0;
 }
 
-static void *relocate_remaining_items(void *fsp, size_t size, size_t fih_offset)
+static ssize_t relocate_remaining_items(void *fsp, size_t size,
+					uintptr_t new_addr, size_t fih_offset)
 {
 	EFI_FFS_FILE_HEADER *ffsfh;
 	EFI_COMMON_SECTION_HEADER *csh;
@@ -278,7 +279,7 @@ static void *relocate_remaining_items(void *fsp, size_t size, size_t fih_offset)
 
 	if (fih_offset == 0) {
 		printk(BIOS_ERR, "FSP_INFO_HEADER offset is 0.\n");
-		return NULL;
+		return -1;
 	}
 
 	/* FSP_INFO_HEADER at first file in FV within first RAW section. */
@@ -290,22 +291,22 @@ static void *relocate_remaining_items(void *fsp, size_t size, size_t fih_offset)
 
 	if (memcmp(&ffsfh->Name, &fih_guid, sizeof(fih_guid))) {
 		printk(BIOS_ERR, "Bad FIH GUID.\n");
-		return NULL;
+		return -1;
 	}
 
 	if (csh->Type != EFI_SECTION_RAW) {
 		printk(BIOS_ERR, "FIH file should have raw section: %x\n",
 			csh->Type);
-		return NULL;
+		return -1;
 	}
 
 	if (fih->Signature != FSP_SIG) {
 		printk(BIOS_ERR, "Unexpected FIH signature: %08x\n",
 			fih->Signature);
-		return NULL;
+		return -1;
 	}
 
-	adjustment = (intptr_t)fsp - fih->ImageBase;
+	adjustment = (intptr_t)new_addr - fih->ImageBase;
 
 	/* Update ImageBase to reflect FSP's new home. */
 	fih->ImageBase += adjustment;
@@ -330,18 +331,18 @@ static void *relocate_remaining_items(void *fsp, size_t size, size_t fih_offset)
 
 		if (relocate_patch_table(fsp, size, offset, adjustment)) {
 			printk(BIOS_ERR, "FSPP relocation failed.\n");
-			return NULL;
+			return -1;
 		}
 
-		return fih;
+		return fih_offset;
 	}
 
 	printk(BIOS_ERR, "Could not find the FSP patch table.\n");
-	return NULL;
+	return -1;
 }
 
-static ssize_t relocate_fvh(void *fsp, size_t fsp_size, size_t fvh_offset,
-				size_t *fih_offset)
+static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
+				size_t fvh_offset, size_t *fih_offset)
 {
 	EFI_FIRMWARE_VOLUME_HEADER *fvh;
 	EFI_FFS_FILE_HEADER *ffsfh;
@@ -431,14 +432,24 @@ static ssize_t relocate_fvh(void *fsp, size_t fsp_size, size_t fvh_offset,
 				return -1;
 			}
 
+			/*
+			 * The entire FSP 1.1 image can be thought of as one
+			 * program with a single link address even though there
+			 * are multiple TEs linked separately. The reason is
+			 * that each TE is linked for XIP. So in order to
+			 * relocate the TE properly we need to form the
+			 * relocated address based on the TE offset within
+			 * FSP proper.
+			 */
 			if (csh->Type == EFI_SECTION_TE) {
 				void *te;
 				size_t te_offset = offset + data_offset;
+				uintptr_t te_addr = new_addr + te_offset;
 
 				printk(FSP_DBG_LVL, "TE image at offset %zx\n",
 					te_offset);
 				te = relative_offset(fsp, te_offset);
-				te_relocate_in_place(te, data_size);
+				te_relocate(te_addr, te, data_size);
 			}
 
 			offset += data_size + data_offset;
@@ -451,7 +462,7 @@ static ssize_t relocate_fvh(void *fsp, size_t fsp_size, size_t fvh_offset,
 	return fvh->FvLength;
 }
 
-static FSP_INFO_HEADER *fsp_relocate_in_place(void *fsp, size_t size)
+static ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size)
 {
 	size_t offset;
 	size_t fih_offset;
@@ -464,27 +475,30 @@ static FSP_INFO_HEADER *fsp_relocate_in_place(void *fsp, size_t size)
 		/* Relocate each FV within the FSP region. The FSP_INFO_HEADER
 		 * should only be located in the first FV. */
 		if (offset == 0)
-			nparsed = relocate_fvh(fsp, size, offset, &fih_offset);
+			nparsed = relocate_fvh(new_addr, fsp, size, offset,
+						&fih_offset);
 		else
-			nparsed = relocate_fvh(fsp, size, offset, NULL);
+			nparsed = relocate_fvh(new_addr, fsp, size, offset,
+						NULL);
 
 		/* FV should be larger than 0 or failed to parse. */
 		if (nparsed <= 0) {
 			printk(BIOS_ERR, "FV @ offset %zx relocation failed\n",
 				offset);
-			return NULL;
+			return -1;
 		}
 
 		offset += nparsed;
 	}
 
-	return relocate_remaining_items(fsp, size, fih_offset);
+	return relocate_remaining_items(fsp, size, new_addr, fih_offset);
 }
 
 int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src)
 {
 	void *new_loc;
 	void *fih;
+	ssize_t fih_offset;
 	size_t size = region_device_sz(fsp_src);
 
 	new_loc = cbmem_add(CBMEM_ID_REFCODE, size);
@@ -499,13 +513,15 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src)
 		return -1;
 	}
 
-	fih = fsp_relocate_in_place(new_loc, size);
+	fih_offset = fsp1_1_relocate((uintptr_t)new_loc, new_loc, size);
 
-	if (fih == NULL) {
+	if (fih_offset <= 0) {
 		printk(BIOS_ERR, "ERROR: FSP relocation faiulre.\n");
 		return -1;
 	}
 
+	fih = relative_offset(new_loc, fih_offset);
+
 	prog_set_area(fsp_relocd, new_loc, size);
 	prog_set_entry(fsp_relocd, fih, NULL);
 


From gerrit at coreboot.org  Tue Sep 15 19:40:16 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:16 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	drivers/intel/fsp1_1: handle UEFI endianness
References: <I39f4de84688e48978a4650303b8af8345f44fd03+0@gerrit.coreboot.org>
Message-ID: <I39f4de84688e48978a4650303b8af8345f44fd03+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11664

-gerrit

commit a4ca7ad61bc5d65138a8a22269684672e080f619
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 22:36:20 2015 -0500

    drivers/intel/fsp1_1: handle UEFI endianness
    
    UEFI defines everything as little endian. Additionally the
    EDK II header files assume they are used on machines
    which are running UEFI -- thus little endian. This patch
    attempts to fix up all the possible endian violations
    when running on a big endian machine. This is for
    in preparation of using the FSP 1.1 code in userland
    for relocating FSP images.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I39f4de84688e48978a4650303b8af8345f44fd03
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3c7eab9b7c10765355feffa3c3cac403275f9479
    Original-Change-Id: I33a7661281307cf31ae33899d1a4eb6a2fbd01a1
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298832
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/drivers/intel/fsp1_1/fsp_relocate.c | 160 ++++++++++++++++++++------------
 1 file changed, 102 insertions(+), 58 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
index 351fcc8..6e2a2a7 100644
--- a/src/drivers/intel/fsp1_1/fsp_relocate.c
+++ b/src/drivers/intel/fsp1_1/fsp_relocate.c
@@ -19,6 +19,7 @@
 
 #include <console/console.h>
 #include <cbmem.h>
+#include <endian.h>
 #include <fsp/util.h>
 #include <stdlib.h>
 #include <stdint.h>
@@ -26,6 +27,32 @@
 
 #define FSP_DBG_LVL BIOS_NEVER
 
+/*
+ * UEFI defines everything as little endian. However, this piece of code
+ * can be integrated in a userland tool. That tool could be on a big endian
+ * machine so one needs to access the fields within UEFI structures using
+ * endian-aware accesses.
+ */
+
+/* Return 0 if equal. Non-zero if not equal. */
+static int guid_compare(const EFI_GUID *le_guid, const EFI_GUID *native_guid)
+{
+	if (le32toh(le_guid->Data1) != native_guid->Data1)
+		return 1;
+	if (le16toh(le_guid->Data2) != native_guid->Data2)
+		return 1;
+	if (le16toh(le_guid->Data3) != native_guid->Data3)
+		return 1;
+	return memcmp(le_guid->Data4, native_guid->Data4,
+			ARRAY_SIZE(le_guid->Data4));
+}
+
+/* Provide this for symmetry when accessing UEFI fields. */
+static inline uint8_t le8toh(uint8_t byte)
+{
+	return byte;
+}
+
 static const EFI_GUID ffs2_guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID;
 static const EFI_GUID fih_guid = FSP_INFO_HEADER_GUID;
 
@@ -87,6 +114,7 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size)
 	EFI_TE_IMAGE_HEADER *teih;
 	EFI_IMAGE_DATA_DIRECTORY *relocd;
 	EFI_IMAGE_BASE_RELOCATION *relocb;
+	uintptr_t image_base;
 	size_t fixup_offset;
 	size_t num_relocs;
 	uint16_t *reloc;
@@ -96,9 +124,10 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size)
 
 	teih = te;
 
-	if (teih->Signature != EFI_TE_IMAGE_HEADER_SIGNATURE) {
+	if (le16toh(teih->Signature) != EFI_TE_IMAGE_HEADER_SIGNATURE) {
 		printk(BIOS_ERR, "TE Signature mismatch: %x vs %x\n",
-			teih->Signature, EFI_TE_IMAGE_HEADER_SIGNATURE);
+			le16toh(teih->Signature),
+			EFI_TE_IMAGE_HEADER_SIGNATURE);
 		return -1;
 	}
 
@@ -109,54 +138,58 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size)
 	 * from the encoded offets.  Similarly, the linked address of the
 	 * program is found by adding the fixup_offset to the ImageBase.
 	 */
-	fixup_offset = teih->StrippedSize - sizeof(EFI_TE_IMAGE_HEADER);
+	fixup_offset = le16toh(teih->StrippedSize);
+	fixup_offset -= sizeof(EFI_TE_IMAGE_HEADER);
 	/* Keep track of a base that is correctly adjusted so that offsets
 	 * can be used directly. */
 	te_base = te;
 	te_base -= fixup_offset;
 
-	adj = new_addr - (teih->ImageBase + fixup_offset);
+	image_base = le64toh(teih->ImageBase);
+	adj = new_addr - (image_base + fixup_offset);
 
 	printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n",
-		(void *)(uintptr_t)(teih->ImageBase + fixup_offset),
-		(void *)new_addr, adj);
+		(void *)image_base, (void *)new_addr, adj);
 
 	/* Adjust ImageBase for consistency. */
-	teih->ImageBase = (uint32_t)(teih->ImageBase + adj);
+	teih->ImageBase = htole32(image_base + adj);
 
 	relocd = &teih->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC];
 
 	relocd_offset = 0;
 	/* Though the field name is VirtualAddress it's actually relative to
 	 * the beginning of the image which is linked at ImageBase. */
-	relocb = relative_offset(te, relocd->VirtualAddress - fixup_offset);
+	relocb = relative_offset(te,
+			le32toh(relocd->VirtualAddress) - fixup_offset);
 	while (relocd_offset < relocd->Size) {
-		size_t rva_offset = relocb->VirtualAddress;
+		size_t rva_offset = le32toh(relocb->VirtualAddress);
 
 		printk(FSP_DBG_LVL, "Relocs for RVA offset %zx\n", rva_offset);
-		num_relocs = relocb->SizeOfBlock - sizeof(*relocb);
+		num_relocs = le32toh(relocb->SizeOfBlock) - sizeof(*relocb);
 		num_relocs /= sizeof(uint16_t);
 		reloc = relative_offset(relocb, sizeof(*relocb));
 
 		printk(FSP_DBG_LVL, "Num relocs in block: %zx\n", num_relocs);
 
 		while (num_relocs > 0) {
-			int type = reloc_type(*reloc);
-			size_t offset = reloc_offset(*reloc);
+			uint16_t reloc_val = le16toh(*reloc);
+			int type = reloc_type(reloc_val);
+			size_t offset = reloc_offset(reloc_val);
 
 			printk(FSP_DBG_LVL, "reloc type %x offset %zx\n",
 				type, offset);
 
 			if (type == EFI_IMAGE_REL_BASED_HIGHLOW) {
 				uint32_t *reloc_addr;
+				uint32_t val;
 
 				offset += rva_offset;
 				reloc_addr = (void *)&te_base[offset];
+				val = le32toh(*reloc_addr);
 
 				printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
-					reloc_addr, *reloc_addr,
-					*reloc_addr + adj);
-				*reloc_addr += adj;
+					reloc_addr, val, val + adj);
+				*reloc_addr = htole32(val + adj);
 			} else if (type != EFI_IMAGE_REL_BASED_ABSOLUTE) {
 				printk(BIOS_ERR, "Unknown reloc type: %x\n",
 					type);
@@ -167,9 +200,9 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size)
 		}
 
 		/* Track consumption of relocation directory contents. */
-		relocd_offset += relocb->SizeOfBlock;
+		relocd_offset += le32toh(relocb->SizeOfBlock);
 		/* Get next relocation block to process. */
-		relocb = relative_offset(relocb, relocb->SizeOfBlock);
+		relocb = relative_offset(relocb, le32toh(relocb->SizeOfBlock));
 	}
 
 	return 0;
@@ -181,9 +214,9 @@ static size_t csh_size(const EFI_COMMON_SECTION_HEADER *csh)
 
 	/* Unpack the array into a type that can be used. */
 	size = 0;
-	size |= csh->Size[0] << 0;
-	size |= csh->Size[1] << 8;
-	size |= csh->Size[2] << 16;
+	size |= le8toh(csh->Size[0]) << 0;
+	size |= le8toh(csh->Size[1]) << 8;
+	size |= le8toh(csh->Size[2]) << 16;
 
 	return size;
 }
@@ -201,7 +234,7 @@ static size_t section_data_size(const EFI_COMMON_SECTION_HEADER *csh)
 	size_t section_size;
 
 	if (csh_size(csh) == 0x00ffffff)
-		section_size = SECTION2_SIZE(csh);
+		section_size = le32toh(SECTION2_SIZE(csh));
 	else
 		section_size = csh_size(csh);
 
@@ -221,11 +254,11 @@ static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh)
 	size_t size;
 
 	if (IS_FFS_FILE2(ffsfh))
-		size = FFS_FILE2_SIZE(ffsfh);
+		size = le32toh(FFS_FILE2_SIZE(ffsfh));
 	else {
-		size = ffsfh->Size[0] << 0;
-		size |= ffsfh->Size[1] << 8;
-		size |= ffsfh->Size[2] << 16;
+		size = le8toh(ffsfh->Size[0]) << 0;
+		size |= le8toh(ffsfh->Size[1]) << 8;
+		size |= le8toh(ffsfh->Size[2]) << 16;
 	}
 	return size;
 }
@@ -234,33 +267,39 @@ static int relocate_patch_table(void *fsp, size_t size, size_t offset,
 				ssize_t adjustment)
 {
 	struct fsp_patch_table *table;
-	uint32_t num;
+	size_t num;
+	size_t num_entries;
 
 	table = relative_offset(fsp, offset);
 
 	if ((offset + sizeof(*table) > size) ||
-	    (table->header_length + offset) > size) {
+	    (le16toh(table->header_length) + offset) > size) {
 		printk(BIOS_ERR, "FSPP not entirely contained in region.\n");
 		return -1;
 	}
 
-	printk(FSP_DBG_LVL, "FSPP relocs: %x\n", table->patch_entry_num);
+	num_entries = le32toh(table->patch_entry_num);
+	printk(FSP_DBG_LVL, "FSPP relocs: %zx\n", num_entries);
 
 	for (num = 0; num < table->patch_entry_num; num++) {
 		uint32_t *reloc;
+		uint32_t reloc_val;
 
-		reloc = fspp_reloc(fsp, size, table->patch_entries[num]);
+		reloc = fspp_reloc(fsp, size,
+				le32toh(table->patch_entries[num]));
 
 		if (reloc == NULL) {
 			printk(BIOS_ERR, "Ignoring FSPP entry: %x\n",
-				table->patch_entries[num]);
+				le32toh(table->patch_entries[num]));
 			continue;
 		}
 
+		reloc_val = le32toh(*reloc);
 		printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
-			reloc, *reloc, (unsigned int)(*reloc + adjustment));
+			reloc, reloc_val,
+			(unsigned int)(reloc_val + adjustment));
 
-		*reloc += adjustment;
+		*reloc = htole32(reloc_val + adjustment);
 	}
 
 	return 0;
@@ -289,33 +328,33 @@ static ssize_t relocate_remaining_items(void *fsp, size_t size,
 	fih_offset += section_data_offset(csh);
 	fih = relative_offset(fsp, fih_offset);
 
-	if (memcmp(&ffsfh->Name, &fih_guid, sizeof(fih_guid))) {
+	if (guid_compare(&ffsfh->Name, &fih_guid)) {
 		printk(BIOS_ERR, "Bad FIH GUID.\n");
 		return -1;
 	}
 
-	if (csh->Type != EFI_SECTION_RAW) {
+	if (le8toh(csh->Type) != EFI_SECTION_RAW) {
 		printk(BIOS_ERR, "FIH file should have raw section: %x\n",
 			csh->Type);
 		return -1;
 	}
 
-	if (fih->Signature != FSP_SIG) {
+	if (le32toh(fih->Signature) != FSP_SIG) {
 		printk(BIOS_ERR, "Unexpected FIH signature: %08x\n",
-			fih->Signature);
+			le32toh(fih->Signature));
 		return -1;
 	}
 
-	adjustment = (intptr_t)new_addr - fih->ImageBase;
+	adjustment = (intptr_t)new_addr - le32toh(fih->ImageBase);
 
 	/* Update ImageBase to reflect FSP's new home. */
-	fih->ImageBase += adjustment;
+	fih->ImageBase = htole32(adjustment + le32toh(fih->ImageBase));
 
 	/* Need to find patch table and adjust each entry. The tables
 	 * following FSP_INFO_HEADER have a 32-bit signature and header
 	 * length. The patch table is denoted as having a 'FSPP' signature;
 	 * the table format doesn't follow the other tables. */
-	offset = fih_offset + fih->HeaderLength;
+	offset = fih_offset + le32toh(fih->HeaderLength);
 	while (offset + 2 * sizeof(uint32_t) <= size) {
 		uint32_t *table_headers;
 
@@ -324,8 +363,8 @@ static ssize_t relocate_remaining_items(void *fsp, size_t size,
 		printk(FSP_DBG_LVL, "Checking offset %zx for 'FSPP'\n",
 			offset);
 
-		if (table_headers[0] != FSPP_SIG) {
-			offset += table_headers[1];
+		if (le32toh(table_headers[0]) != FSPP_SIG) {
+			offset += le32toh(table_headers[1]);
 			continue;
 		}
 
@@ -350,41 +389,44 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
 	size_t offset;
 	size_t file_offset;
 	size_t size;
+	size_t fv_length;
 
 	offset = fvh_offset;
 	fvh = relative_offset(fsp, offset);
 
-	if (fvh->Signature != EFI_FVH_SIGNATURE)
+	if (le32toh(fvh->Signature) != EFI_FVH_SIGNATURE)
 		return -1;
 
+	fv_length = le64toh(fvh->FvLength);
+
 	printk(FSP_DBG_LVL, "FVH length: %zx Offset: %zx Mapping length: %zx\n",
-		(size_t)fvh->FvLength, offset, fsp_size);
+		fv_length, offset, fsp_size);
 
 	if (fvh->FvLength + offset > fsp_size)
 		return -1;
 
 	/* Parse only this FV. However, the algorithm uses offsets into the
 	 * entire FSP region so make size include the starting offset. */
-	size = fvh->FvLength + offset;
+	size = fv_length + offset;
 
-	if (memcmp(&fvh->FileSystemGuid, &ffs2_guid, sizeof(ffs2_guid))) {
+	if (guid_compare(&fvh->FileSystemGuid, &ffs2_guid)) {
 		printk(BIOS_ERR, "FVH not an FFS2 type.\n");
 		return -1;
 	}
 
-	if (fvh->ExtHeaderOffset != 0) {
+	if (le16toh(fvh->ExtHeaderOffset) != 0) {
 		EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh;
 
-		offset += fvh->ExtHeaderOffset;
+		offset += le16toh(fvh->ExtHeaderOffset);
 		fveh = relative_offset(fsp, offset);
 		printk(FSP_DBG_LVL, "Extended Header Offset: %zx Size: %zx\n",
-			(size_t)fvh->ExtHeaderOffset,
-			(size_t)fveh->ExtHeaderSize);
-		offset += fveh->ExtHeaderSize;
+			(size_t)le16toh(fvh->ExtHeaderOffset),
+			(size_t)le32toh(fveh->ExtHeaderSize));
+		offset += le32toh(fveh->ExtHeaderSize);
 		/* FFS files are 8 byte aligned after extended header. */
 		offset = ALIGN_UP(offset, 8);
 	} else {
-		offset += fvh->HeaderLength;
+		offset += le16toh(fvh->HeaderLength);
 	}
 
 	file_offset = offset;
@@ -398,11 +440,12 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
 
 		ffsfh = relative_offset(fsp, file_offset);
 
-		printk(FSP_DBG_LVL, "file type = %x\n", ffsfh->Type);
-		printk(FSP_DBG_LVL, "file attribs = %x\n", ffsfh->Attributes);
+		printk(FSP_DBG_LVL, "file type = %x\n", le8toh(ffsfh->Type));
+		printk(FSP_DBG_LVL, "file attribs = %x\n",
+			le8toh(ffsfh->Attributes));
 
 		/* Exit FV relocation when empty space found */
-		if (ffsfh->Type == EFI_FV_FILETYPE_FFS_MAX)
+		if (le8toh(ffsfh->Type) == EFI_FV_FILETYPE_FFS_MAX)
 			break;
 
 		/* Next file on 8 byte alignment. */
@@ -410,7 +453,7 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
 		file_offset = ALIGN_UP(file_offset, 8);
 
 		/* Padding files have no section information. */
-		if (ffsfh->Type == EFI_FV_FILETYPE_FFS_PAD)
+		if (le8toh(ffsfh->Type) == EFI_FV_FILETYPE_FFS_PAD)
 			continue;
 
 		offset += file_section_offset(ffsfh);
@@ -422,7 +465,8 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
 			csh = relative_offset(fsp, offset);
 
 			printk(FSP_DBG_LVL, "section offset: %zx\n", offset);
-			printk(FSP_DBG_LVL, "section type: %x\n", csh->Type);
+			printk(FSP_DBG_LVL, "section type: %x\n",
+				le8toh(csh->Type));
 
 			data_size = section_data_size(csh);
 			data_offset = section_data_offset(csh);
@@ -441,7 +485,7 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
 			 * relocated address based on the TE offset within
 			 * FSP proper.
 			 */
-			if (csh->Type == EFI_SECTION_TE) {
+			if (le8toh(csh->Type) == EFI_SECTION_TE) {
 				void *te;
 				size_t te_offset = offset + data_offset;
 				uintptr_t te_addr = new_addr + te_offset;
@@ -459,7 +503,7 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
 	}
 
 	/* Return amount of buffer parsed: FV size. */
-	return fvh->FvLength;
+	return fv_length;
 }
 
 static ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size)


From gerrit at coreboot.org  Tue Sep 15 19:40:17 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 15 Sep 2015 19:40:17 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	drivers/intel/fsp1_1: split relocation code for tool use
References: <I49998b8621611c638375bc90884e80d0cd3bdf78+0@gerrit.coreboot.org>
Message-ID: <I49998b8621611c638375bc90884e80d0cd3bdf78+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11665

-gerrit

commit 94faf554e888e6bcbcf261c832ecb4915faf4eef
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 22:52:27 2015 -0500

    drivers/intel/fsp1_1: split relocation code for tool use
    
    In order for easier consumption in userland tools split the
    FSP 1.1 relocation logic into a single file w/ an aptly named
    function name.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I49998b8621611c638375bc90884e80d0cd3bdf78
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: bc898e1c528df60683575d553d6194a1e8200afa
    Original-Change-Id: I736c0059d43f6d0be4fdb6e6f47cdb5c189a7ae8
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298833
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/drivers/intel/fsp1_1/Makefile.inc       |   1 +
 src/drivers/intel/fsp1_1/fsp1_1_relocate.c  | 539 ++++++++++++++++++++++++++++
 src/drivers/intel/fsp1_1/fsp_relocate.c     | 519 +-------------------------
 src/drivers/intel/fsp1_1/include/fsp/util.h |   6 +
 4 files changed, 547 insertions(+), 518 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index bab68e1..dffb6d2 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -23,6 +23,7 @@ romstage-y += hob.c
 
 ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
 ramstage-y += fsp_relocate.c
+ramstage-y += fsp1_1_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
 
diff --git a/src/drivers/intel/fsp1_1/fsp1_1_relocate.c b/src/drivers/intel/fsp1_1/fsp1_1_relocate.c
new file mode 100644
index 0000000..d57a18c
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/fsp1_1_relocate.c
@@ -0,0 +1,539 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <endian.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+
+#define FSP_DBG_LVL BIOS_NEVER
+
+/*
+ * UEFI defines everything as little endian. However, this piece of code
+ * can be integrated in a userland tool. That tool could be on a big endian
+ * machine so one needs to access the fields within UEFI structures using
+ * endian-aware accesses.
+ */
+
+/* Return 0 if equal. Non-zero if not equal. */
+static int guid_compare(const EFI_GUID *le_guid, const EFI_GUID *native_guid)
+{
+	if (le32toh(le_guid->Data1) != native_guid->Data1)
+		return 1;
+	if (le16toh(le_guid->Data2) != native_guid->Data2)
+		return 1;
+	if (le16toh(le_guid->Data3) != native_guid->Data3)
+		return 1;
+	return memcmp(le_guid->Data4, native_guid->Data4,
+			ARRAY_SIZE(le_guid->Data4));
+}
+
+/* Provide this for symmetry when accessing UEFI fields. */
+static inline uint8_t le8toh(uint8_t byte)
+{
+	return byte;
+}
+
+static const EFI_GUID ffs2_guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID;
+static const EFI_GUID fih_guid = FSP_INFO_HEADER_GUID;
+
+struct fsp_patch_table {
+	uint32_t signature;
+	uint16_t header_length;
+	uint8_t header_revision;
+	uint8_t reserved;
+	uint32_t patch_entry_num;
+	uint32_t patch_entries[0];
+} __attribute__((packed));
+
+#define FSPP_SIG 0x50505346
+
+static void *relative_offset(void *base, ssize_t offset)
+{
+	uintptr_t loc;
+
+	loc = (uintptr_t)base;
+	loc += offset;
+
+	return (void *)loc;
+}
+
+static uint32_t *fspp_reloc(void *fsp, size_t fsp_size, uint32_t e)
+{
+	size_t offset;
+
+	/* Offsets live in bits 23:0. */
+	offset = e & 0xffffff;
+
+	/* If bit 31 is set then the offset is considered a negative value
+	 * relative to the end of the image using 16MiB as the offset's
+	 * reference. */
+	if (e & (1 << 31))
+		offset = fsp_size - (16 * MiB - offset);
+
+	/* Determine if offset falls within fsp_size for a 32 bit relocation. */
+	if (offset > fsp_size - sizeof(uint32_t))
+		return NULL;
+
+	return relative_offset(fsp, offset);
+}
+
+static int reloc_type(uint16_t reloc_entry)
+{
+	/* Reloc type in upper 4 bits */
+	return reloc_entry >> 12;
+}
+
+static size_t reloc_offset(uint16_t reloc_entry)
+{
+	/* Offsets are in low 12 bits. */
+	return reloc_entry & ((1 << 12) - 1);
+}
+
+static int te_relocate(uintptr_t new_addr, void *te, size_t size)
+{
+	EFI_TE_IMAGE_HEADER *teih;
+	EFI_IMAGE_DATA_DIRECTORY *relocd;
+	EFI_IMAGE_BASE_RELOCATION *relocb;
+	uintptr_t image_base;
+	size_t fixup_offset;
+	size_t num_relocs;
+	uint16_t *reloc;
+	size_t relocd_offset;
+	uint8_t *te_base;
+	uint32_t adj;
+
+	teih = te;
+
+	if (le16toh(teih->Signature) != EFI_TE_IMAGE_HEADER_SIGNATURE) {
+		printk(BIOS_ERR, "TE Signature mismatch: %x vs %x\n",
+			le16toh(teih->Signature),
+			EFI_TE_IMAGE_HEADER_SIGNATURE);
+		return -1;
+	}
+
+	/*
+	 * A TE image is created by converting a PE file. Because of this
+	 * the offsets within the headers are off. In order to calculate
+	 * the correct releative offets one needs to subtract fixup_offset
+	 * from the encoded offets.  Similarly, the linked address of the
+	 * program is found by adding the fixup_offset to the ImageBase.
+	 */
+	fixup_offset = le16toh(teih->StrippedSize);
+	fixup_offset -= sizeof(EFI_TE_IMAGE_HEADER);
+	/* Keep track of a base that is correctly adjusted so that offsets
+	 * can be used directly. */
+	te_base = te;
+	te_base -= fixup_offset;
+
+	image_base = le64toh(teih->ImageBase);
+	adj = new_addr - (image_base + fixup_offset);
+
+	printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n",
+		(void *)image_base, (void *)new_addr, adj);
+
+	/* Adjust ImageBase for consistency. */
+	teih->ImageBase = htole32(image_base + adj);
+
+	relocd = &teih->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC];
+
+	relocd_offset = 0;
+	/* Though the field name is VirtualAddress it's actually relative to
+	 * the beginning of the image which is linked at ImageBase. */
+	relocb = relative_offset(te,
+			le32toh(relocd->VirtualAddress) - fixup_offset);
+	while (relocd_offset < relocd->Size) {
+		size_t rva_offset = le32toh(relocb->VirtualAddress);
+
+		printk(FSP_DBG_LVL, "Relocs for RVA offset %zx\n", rva_offset);
+		num_relocs = le32toh(relocb->SizeOfBlock) - sizeof(*relocb);
+		num_relocs /= sizeof(uint16_t);
+		reloc = relative_offset(relocb, sizeof(*relocb));
+
+		printk(FSP_DBG_LVL, "Num relocs in block: %zx\n", num_relocs);
+
+		while (num_relocs > 0) {
+			uint16_t reloc_val = le16toh(*reloc);
+			int type = reloc_type(reloc_val);
+			size_t offset = reloc_offset(reloc_val);
+
+			printk(FSP_DBG_LVL, "reloc type %x offset %zx\n",
+				type, offset);
+
+			if (type == EFI_IMAGE_REL_BASED_HIGHLOW) {
+				uint32_t *reloc_addr;
+				uint32_t val;
+
+				offset += rva_offset;
+				reloc_addr = (void *)&te_base[offset];
+				val = le32toh(*reloc_addr);
+
+				printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
+					reloc_addr, val, val + adj);
+				*reloc_addr = htole32(val + adj);
+			} else if (type != EFI_IMAGE_REL_BASED_ABSOLUTE) {
+				printk(BIOS_ERR, "Unknown reloc type: %x\n",
+					type);
+				return -1;
+			}
+			num_relocs--;
+			reloc++;
+		}
+
+		/* Track consumption of relocation directory contents. */
+		relocd_offset += le32toh(relocb->SizeOfBlock);
+		/* Get next relocation block to process. */
+		relocb = relative_offset(relocb, le32toh(relocb->SizeOfBlock));
+	}
+
+	return 0;
+}
+
+static size_t csh_size(const EFI_COMMON_SECTION_HEADER *csh)
+{
+	size_t size;
+
+	/* Unpack the array into a type that can be used. */
+	size = 0;
+	size |= le8toh(csh->Size[0]) << 0;
+	size |= le8toh(csh->Size[1]) << 8;
+	size |= le8toh(csh->Size[2]) << 16;
+
+	return size;
+}
+
+static size_t section_data_offset(const EFI_COMMON_SECTION_HEADER *csh)
+{
+	if (csh_size(csh) == 0x00ffffff)
+		return sizeof(EFI_COMMON_SECTION_HEADER2);
+	else
+		return sizeof(EFI_COMMON_SECTION_HEADER);
+}
+
+static size_t section_data_size(const EFI_COMMON_SECTION_HEADER *csh)
+{
+	size_t section_size;
+
+	if (csh_size(csh) == 0x00ffffff)
+		section_size = le32toh(SECTION2_SIZE(csh));
+	else
+		section_size = csh_size(csh);
+
+	return section_size - section_data_offset(csh);
+}
+
+static size_t file_section_offset(const EFI_FFS_FILE_HEADER *ffsfh)
+{
+	if (IS_FFS_FILE2(ffsfh))
+		return sizeof(EFI_FFS_FILE_HEADER2);
+	else
+		return sizeof(EFI_FFS_FILE_HEADER);
+}
+
+static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh)
+{
+	size_t size;
+
+	if (IS_FFS_FILE2(ffsfh))
+		size = le32toh(FFS_FILE2_SIZE(ffsfh));
+	else {
+		size = le8toh(ffsfh->Size[0]) << 0;
+		size |= le8toh(ffsfh->Size[1]) << 8;
+		size |= le8toh(ffsfh->Size[2]) << 16;
+	}
+	return size;
+}
+
+static int relocate_patch_table(void *fsp, size_t size, size_t offset,
+				ssize_t adjustment)
+{
+	struct fsp_patch_table *table;
+	size_t num;
+	size_t num_entries;
+
+	table = relative_offset(fsp, offset);
+
+	if ((offset + sizeof(*table) > size) ||
+	    (le16toh(table->header_length) + offset) > size) {
+		printk(BIOS_ERR, "FSPP not entirely contained in region.\n");
+		return -1;
+	}
+
+	num_entries = le32toh(table->patch_entry_num);
+	printk(FSP_DBG_LVL, "FSPP relocs: %zx\n", num_entries);
+
+	for (num = 0; num < table->patch_entry_num; num++) {
+		uint32_t *reloc;
+		uint32_t reloc_val;
+
+		reloc = fspp_reloc(fsp, size,
+				le32toh(table->patch_entries[num]));
+
+		if (reloc == NULL) {
+			printk(BIOS_ERR, "Ignoring FSPP entry: %x\n",
+				le32toh(table->patch_entries[num]));
+			continue;
+		}
+
+		reloc_val = le32toh(*reloc);
+		printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
+			reloc, reloc_val,
+			(unsigned int)(reloc_val + adjustment));
+
+		*reloc = htole32(reloc_val + adjustment);
+	}
+
+	return 0;
+}
+
+static ssize_t relocate_remaining_items(void *fsp, size_t size,
+					uintptr_t new_addr, size_t fih_offset)
+{
+	EFI_FFS_FILE_HEADER *ffsfh;
+	EFI_COMMON_SECTION_HEADER *csh;
+	FSP_INFO_HEADER *fih;
+	ssize_t adjustment;
+	size_t offset;
+
+	printk(FSP_DBG_LVL, "FSP_INFO_HEADER offset is %zx\n", fih_offset);
+
+	if (fih_offset == 0) {
+		printk(BIOS_ERR, "FSP_INFO_HEADER offset is 0.\n");
+		return -1;
+	}
+
+	/* FSP_INFO_HEADER at first file in FV within first RAW section. */
+	ffsfh = relative_offset(fsp, fih_offset);
+	fih_offset += file_section_offset(ffsfh);
+	csh = relative_offset(fsp, fih_offset);
+	fih_offset += section_data_offset(csh);
+	fih = relative_offset(fsp, fih_offset);
+
+	if (guid_compare(&ffsfh->Name, &fih_guid)) {
+		printk(BIOS_ERR, "Bad FIH GUID.\n");
+		return -1;
+	}
+
+	if (le8toh(csh->Type) != EFI_SECTION_RAW) {
+		printk(BIOS_ERR, "FIH file should have raw section: %x\n",
+			csh->Type);
+		return -1;
+	}
+
+	if (le32toh(fih->Signature) != FSP_SIG) {
+		printk(BIOS_ERR, "Unexpected FIH signature: %08x\n",
+			le32toh(fih->Signature));
+		return -1;
+	}
+
+	adjustment = (intptr_t)new_addr - le32toh(fih->ImageBase);
+
+	/* Update ImageBase to reflect FSP's new home. */
+	fih->ImageBase = htole32(adjustment + le32toh(fih->ImageBase));
+
+	/* Need to find patch table and adjust each entry. The tables
+	 * following FSP_INFO_HEADER have a 32-bit signature and header
+	 * length. The patch table is denoted as having a 'FSPP' signature;
+	 * the table format doesn't follow the other tables. */
+	offset = fih_offset + le32toh(fih->HeaderLength);
+	while (offset + 2 * sizeof(uint32_t) <= size) {
+		uint32_t *table_headers;
+
+		table_headers = relative_offset(fsp, offset);
+
+		printk(FSP_DBG_LVL, "Checking offset %zx for 'FSPP'\n",
+			offset);
+
+		if (le32toh(table_headers[0]) != FSPP_SIG) {
+			offset += le32toh(table_headers[1]);
+			continue;
+		}
+
+		if (relocate_patch_table(fsp, size, offset, adjustment)) {
+			printk(BIOS_ERR, "FSPP relocation failed.\n");
+			return -1;
+		}
+
+		return fih_offset;
+	}
+
+	printk(BIOS_ERR, "Could not find the FSP patch table.\n");
+	return -1;
+}
+
+static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
+				size_t fvh_offset, size_t *fih_offset)
+{
+	EFI_FIRMWARE_VOLUME_HEADER *fvh;
+	EFI_FFS_FILE_HEADER *ffsfh;
+	EFI_COMMON_SECTION_HEADER *csh;
+	size_t offset;
+	size_t file_offset;
+	size_t size;
+	size_t fv_length;
+
+	offset = fvh_offset;
+	fvh = relative_offset(fsp, offset);
+
+	if (le32toh(fvh->Signature) != EFI_FVH_SIGNATURE)
+		return -1;
+
+	fv_length = le64toh(fvh->FvLength);
+
+	printk(FSP_DBG_LVL, "FVH length: %zx Offset: %zx Mapping length: %zx\n",
+		fv_length, offset, fsp_size);
+
+	if (fvh->FvLength + offset > fsp_size)
+		return -1;
+
+	/* Parse only this FV. However, the algorithm uses offsets into the
+	 * entire FSP region so make size include the starting offset. */
+	size = fv_length + offset;
+
+	if (guid_compare(&fvh->FileSystemGuid, &ffs2_guid)) {
+		printk(BIOS_ERR, "FVH not an FFS2 type.\n");
+		return -1;
+	}
+
+	if (le16toh(fvh->ExtHeaderOffset) != 0) {
+		EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh;
+
+		offset += le16toh(fvh->ExtHeaderOffset);
+		fveh = relative_offset(fsp, offset);
+		printk(FSP_DBG_LVL, "Extended Header Offset: %zx Size: %zx\n",
+			(size_t)le16toh(fvh->ExtHeaderOffset),
+			(size_t)le32toh(fveh->ExtHeaderSize));
+		offset += le32toh(fveh->ExtHeaderSize);
+		/* FFS files are 8 byte aligned after extended header. */
+		offset = ALIGN_UP(offset, 8);
+	} else {
+		offset += le16toh(fvh->HeaderLength);
+	}
+
+	file_offset = offset;
+	while (file_offset + sizeof(*ffsfh) < size) {
+		offset = file_offset;
+		printk(FSP_DBG_LVL, "file offset: %zx\n", file_offset);
+
+		/* First file and section should be FSP info header. */
+		if (fih_offset != NULL && *fih_offset == 0)
+			*fih_offset = file_offset;
+
+		ffsfh = relative_offset(fsp, file_offset);
+
+		printk(FSP_DBG_LVL, "file type = %x\n", le8toh(ffsfh->Type));
+		printk(FSP_DBG_LVL, "file attribs = %x\n",
+			le8toh(ffsfh->Attributes));
+
+		/* Exit FV relocation when empty space found */
+		if (le8toh(ffsfh->Type) == EFI_FV_FILETYPE_FFS_MAX)
+			break;
+
+		/* Next file on 8 byte alignment. */
+		file_offset += ffs_file_size(ffsfh);
+		file_offset = ALIGN_UP(file_offset, 8);
+
+		/* Padding files have no section information. */
+		if (le8toh(ffsfh->Type) == EFI_FV_FILETYPE_FFS_PAD)
+			continue;
+
+		offset += file_section_offset(ffsfh);
+
+		while (offset + sizeof(*csh) < file_offset) {
+			size_t data_size;
+			size_t data_offset;
+
+			csh = relative_offset(fsp, offset);
+
+			printk(FSP_DBG_LVL, "section offset: %zx\n", offset);
+			printk(FSP_DBG_LVL, "section type: %x\n",
+				le8toh(csh->Type));
+
+			data_size = section_data_size(csh);
+			data_offset = section_data_offset(csh);
+
+			if (data_size + data_offset + offset > file_offset) {
+				printk(BIOS_ERR, "Section exceeds FV size.\n");
+				return -1;
+			}
+
+			/*
+			 * The entire FSP 1.1 image can be thought of as one
+			 * program with a single link address even though there
+			 * are multiple TEs linked separately. The reason is
+			 * that each TE is linked for XIP. So in order to
+			 * relocate the TE properly we need to form the
+			 * relocated address based on the TE offset within
+			 * FSP proper.
+			 */
+			if (le8toh(csh->Type) == EFI_SECTION_TE) {
+				void *te;
+				size_t te_offset = offset + data_offset;
+				uintptr_t te_addr = new_addr + te_offset;
+
+				printk(FSP_DBG_LVL, "TE image at offset %zx\n",
+					te_offset);
+				te = relative_offset(fsp, te_offset);
+				te_relocate(te_addr, te, data_size);
+			}
+
+			offset += data_size + data_offset;
+			/* Sections are aligned to 4 bytes. */
+			offset = ALIGN_UP(offset, 4);
+		}
+	}
+
+	/* Return amount of buffer parsed: FV size. */
+	return fv_length;
+}
+
+ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size)
+{
+	size_t offset;
+	size_t fih_offset;
+
+	offset = 0;
+	fih_offset = 0;
+	while (offset < size) {
+		ssize_t nparsed;
+
+		/* Relocate each FV within the FSP region. The FSP_INFO_HEADER
+		 * should only be located in the first FV. */
+		if (offset == 0)
+			nparsed = relocate_fvh(new_addr, fsp, size, offset,
+						&fih_offset);
+		else
+			nparsed = relocate_fvh(new_addr, fsp, size, offset,
+						NULL);
+
+		/* FV should be larger than 0 or failed to parse. */
+		if (nparsed <= 0) {
+			printk(BIOS_ERR, "FV @ offset %zx relocation failed\n",
+				offset);
+			return -1;
+		}
+
+		offset += nparsed;
+	}
+
+	return relocate_remaining_items(fsp, size, new_addr, fih_offset);
+}
diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
index 6e2a2a7..da0b341 100644
--- a/src/drivers/intel/fsp1_1/fsp_relocate.c
+++ b/src/drivers/intel/fsp1_1/fsp_relocate.c
@@ -19,524 +19,7 @@
 
 #include <console/console.h>
 #include <cbmem.h>
-#include <endian.h>
 #include <fsp/util.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <string.h>
-
-#define FSP_DBG_LVL BIOS_NEVER
-
-/*
- * UEFI defines everything as little endian. However, this piece of code
- * can be integrated in a userland tool. That tool could be on a big endian
- * machine so one needs to access the fields within UEFI structures using
- * endian-aware accesses.
- */
-
-/* Return 0 if equal. Non-zero if not equal. */
-static int guid_compare(const EFI_GUID *le_guid, const EFI_GUID *native_guid)
-{
-	if (le32toh(le_guid->Data1) != native_guid->Data1)
-		return 1;
-	if (le16toh(le_guid->Data2) != native_guid->Data2)
-		return 1;
-	if (le16toh(le_guid->Data3) != native_guid->Data3)
-		return 1;
-	return memcmp(le_guid->Data4, native_guid->Data4,
-			ARRAY_SIZE(le_guid->Data4));
-}
-
-/* Provide this for symmetry when accessing UEFI fields. */
-static inline uint8_t le8toh(uint8_t byte)
-{
-	return byte;
-}
-
-static const EFI_GUID ffs2_guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID;
-static const EFI_GUID fih_guid = FSP_INFO_HEADER_GUID;
-
-struct fsp_patch_table {
-	uint32_t signature;
-	uint16_t header_length;
-	uint8_t header_revision;
-	uint8_t reserved;
-	uint32_t patch_entry_num;
-	uint32_t patch_entries[0];
-} __attribute__((packed));
-
-#define FSPP_SIG 0x50505346
-
-static void *relative_offset(void *base, ssize_t offset)
-{
-	uintptr_t loc;
-
-	loc = (uintptr_t)base;
-	loc += offset;
-
-	return (void *)loc;
-}
-
-static uint32_t *fspp_reloc(void *fsp, size_t fsp_size, uint32_t e)
-{
-	size_t offset;
-
-	/* Offsets live in bits 23:0. */
-	offset = e & 0xffffff;
-
-	/* If bit 31 is set then the offset is considered a negative value
-	 * relative to the end of the image using 16MiB as the offset's
-	 * reference. */
-	if (e & (1 << 31))
-		offset = fsp_size - (16 * MiB - offset);
-
-	/* Determine if offset falls within fsp_size for a 32 bit relocation. */
-	if (offset > fsp_size - sizeof(uint32_t))
-		return NULL;
-
-	return relative_offset(fsp, offset);
-}
-
-static int reloc_type(uint16_t reloc_entry)
-{
-	/* Reloc type in upper 4 bits */
-	return reloc_entry >> 12;
-}
-
-static size_t reloc_offset(uint16_t reloc_entry)
-{
-	/* Offsets are in low 12 bits. */
-	return reloc_entry & ((1 << 12) - 1);
-}
-
-static int te_relocate(uintptr_t new_addr, void *te, size_t size)
-{
-	EFI_TE_IMAGE_HEADER *teih;
-	EFI_IMAGE_DATA_DIRECTORY *relocd;
-	EFI_IMAGE_BASE_RELOCATION *relocb;
-	uintptr_t image_base;
-	size_t fixup_offset;
-	size_t num_relocs;
-	uint16_t *reloc;
-	size_t relocd_offset;
-	uint8_t *te_base;
-	uint32_t adj;
-
-	teih = te;
-
-	if (le16toh(teih->Signature) != EFI_TE_IMAGE_HEADER_SIGNATURE) {
-		printk(BIOS_ERR, "TE Signature mismatch: %x vs %x\n",
-			le16toh(teih->Signature),
-			EFI_TE_IMAGE_HEADER_SIGNATURE);
-		return -1;
-	}
-
-	/*
-	 * A TE image is created by converting a PE file. Because of this
-	 * the offsets within the headers are off. In order to calculate
-	 * the correct releative offets one needs to subtract fixup_offset
-	 * from the encoded offets.  Similarly, the linked address of the
-	 * program is found by adding the fixup_offset to the ImageBase.
-	 */
-	fixup_offset = le16toh(teih->StrippedSize);
-	fixup_offset -= sizeof(EFI_TE_IMAGE_HEADER);
-	/* Keep track of a base that is correctly adjusted so that offsets
-	 * can be used directly. */
-	te_base = te;
-	te_base -= fixup_offset;
-
-	image_base = le64toh(teih->ImageBase);
-	adj = new_addr - (image_base + fixup_offset);
-
-	printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n",
-		(void *)image_base, (void *)new_addr, adj);
-
-	/* Adjust ImageBase for consistency. */
-	teih->ImageBase = htole32(image_base + adj);
-
-	relocd = &teih->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC];
-
-	relocd_offset = 0;
-	/* Though the field name is VirtualAddress it's actually relative to
-	 * the beginning of the image which is linked at ImageBase. */
-	relocb = relative_offset(te,
-			le32toh(relocd->VirtualAddress) - fixup_offset);
-	while (relocd_offset < relocd->Size) {
-		size_t rva_offset = le32toh(relocb->VirtualAddress);
-
-		printk(FSP_DBG_LVL, "Relocs for RVA offset %zx\n", rva_offset);
-		num_relocs = le32toh(relocb->SizeOfBlock) - sizeof(*relocb);
-		num_relocs /= sizeof(uint16_t);
-		reloc = relative_offset(relocb, sizeof(*relocb));
-
-		printk(FSP_DBG_LVL, "Num relocs in block: %zx\n", num_relocs);
-
-		while (num_relocs > 0) {
-			uint16_t reloc_val = le16toh(*reloc);
-			int type = reloc_type(reloc_val);
-			size_t offset = reloc_offset(reloc_val);
-
-			printk(FSP_DBG_LVL, "reloc type %x offset %zx\n",
-				type, offset);
-
-			if (type == EFI_IMAGE_REL_BASED_HIGHLOW) {
-				uint32_t *reloc_addr;
-				uint32_t val;
-
-				offset += rva_offset;
-				reloc_addr = (void *)&te_base[offset];
-				val = le32toh(*reloc_addr);
-
-				printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
-					reloc_addr, val, val + adj);
-				*reloc_addr = htole32(val + adj);
-			} else if (type != EFI_IMAGE_REL_BASED_ABSOLUTE) {
-				printk(BIOS_ERR, "Unknown reloc type: %x\n",
-					type);
-				return -1;
-			}
-			num_relocs--;
-			reloc++;
-		}
-
-		/* Track consumption of relocation directory contents. */
-		relocd_offset += le32toh(relocb->SizeOfBlock);
-		/* Get next relocation block to process. */
-		relocb = relative_offset(relocb, le32toh(relocb->SizeOfBlock));
-	}
-
-	return 0;
-}
-
-static size_t csh_size(const EFI_COMMON_SECTION_HEADER *csh)
-{
-	size_t size;
-
-	/* Unpack the array into a type that can be used. */
-	size = 0;
-	size |= le8toh(csh->Size[0]) << 0;
-	size |= le8toh(csh->Size[1]) << 8;
-	size |= le8toh(csh->Size[2]) << 16;
-
-	return size;
-}
-
-static size_t section_data_offset(const EFI_COMMON_SECTION_HEADER *csh)
-{
-	if (csh_size(csh) == 0x00ffffff)
-		return sizeof(EFI_COMMON_SECTION_HEADER2);
-	else
-		return sizeof(EFI_COMMON_SECTION_HEADER);
-}
-
-static size_t section_data_size(const EFI_COMMON_SECTION_HEADER *csh)
-{
-	size_t section_size;
-
-	if (csh_size(csh) == 0x00ffffff)
-		section_size = le32toh(SECTION2_SIZE(csh));
-	else
-		section_size = csh_size(csh);
-
-	return section_size - section_data_offset(csh);
-}
-
-static size_t file_section_offset(const EFI_FFS_FILE_HEADER *ffsfh)
-{
-	if (IS_FFS_FILE2(ffsfh))
-		return sizeof(EFI_FFS_FILE_HEADER2);
-	else
-		return sizeof(EFI_FFS_FILE_HEADER);
-}
-
-static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh)
-{
-	size_t size;
-
-	if (IS_FFS_FILE2(ffsfh))
-		size = le32toh(FFS_FILE2_SIZE(ffsfh));
-	else {
-		size = le8toh(ffsfh->Size[0]) << 0;
-		size |= le8toh(ffsfh->Size[1]) << 8;
-		size |= le8toh(ffsfh->Size[2]) << 16;
-	}
-	return size;
-}
-
-static int relocate_patch_table(void *fsp, size_t size, size_t offset,
-				ssize_t adjustment)
-{
-	struct fsp_patch_table *table;
-	size_t num;
-	size_t num_entries;
-
-	table = relative_offset(fsp, offset);
-
-	if ((offset + sizeof(*table) > size) ||
-	    (le16toh(table->header_length) + offset) > size) {
-		printk(BIOS_ERR, "FSPP not entirely contained in region.\n");
-		return -1;
-	}
-
-	num_entries = le32toh(table->patch_entry_num);
-	printk(FSP_DBG_LVL, "FSPP relocs: %zx\n", num_entries);
-
-	for (num = 0; num < table->patch_entry_num; num++) {
-		uint32_t *reloc;
-		uint32_t reloc_val;
-
-		reloc = fspp_reloc(fsp, size,
-				le32toh(table->patch_entries[num]));
-
-		if (reloc == NULL) {
-			printk(BIOS_ERR, "Ignoring FSPP entry: %x\n",
-				le32toh(table->patch_entries[num]));
-			continue;
-		}
-
-		reloc_val = le32toh(*reloc);
-		printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
-			reloc, reloc_val,
-			(unsigned int)(reloc_val + adjustment));
-
-		*reloc = htole32(reloc_val + adjustment);
-	}
-
-	return 0;
-}
-
-static ssize_t relocate_remaining_items(void *fsp, size_t size,
-					uintptr_t new_addr, size_t fih_offset)
-{
-	EFI_FFS_FILE_HEADER *ffsfh;
-	EFI_COMMON_SECTION_HEADER *csh;
-	FSP_INFO_HEADER *fih;
-	ssize_t adjustment;
-	size_t offset;
-
-	printk(FSP_DBG_LVL, "FSP_INFO_HEADER offset is %zx\n", fih_offset);
-
-	if (fih_offset == 0) {
-		printk(BIOS_ERR, "FSP_INFO_HEADER offset is 0.\n");
-		return -1;
-	}
-
-	/* FSP_INFO_HEADER at first file in FV within first RAW section. */
-	ffsfh = relative_offset(fsp, fih_offset);
-	fih_offset += file_section_offset(ffsfh);
-	csh = relative_offset(fsp, fih_offset);
-	fih_offset += section_data_offset(csh);
-	fih = relative_offset(fsp, fih_offset);
-
-	if (guid_compare(&ffsfh->Name, &fih_guid)) {
-		printk(BIOS_ERR, "Bad FIH GUID.\n");
-		return -1;
-	}
-
-	if (le8toh(csh->Type) != EFI_SECTION_RAW) {
-		printk(BIOS_ERR, "FIH file should have raw section: %x\n",
-			csh->Type);
-		return -1;
-	}
-
-	if (le32toh(fih->Signature) != FSP_SIG) {
-		printk(BIOS_ERR, "Unexpected FIH signature: %08x\n",
-			le32toh(fih->Signature));
-		return -1;
-	}
-
-	adjustment = (intptr_t)new_addr - le32toh(fih->ImageBase);
-
-	/* Update ImageBase to reflect FSP's new home. */
-	fih->ImageBase = htole32(adjustment + le32toh(fih->ImageBase));
-
-	/* Need to find patch table and adjust each entry. The tables
-	 * following FSP_INFO_HEADER have a 32-bit signature and header
-	 * length. The patch table is denoted as having a 'FSPP' signature;
-	 * the table format doesn't follow the other tables. */
-	offset = fih_offset + le32toh(fih->HeaderLength);
-	while (offset + 2 * sizeof(uint32_t) <= size) {
-		uint32_t *table_headers;
-
-		table_headers = relative_offset(fsp, offset);
-
-		printk(FSP_DBG_LVL, "Checking offset %zx for 'FSPP'\n",
-			offset);
-
-		if (le32toh(table_headers[0]) != FSPP_SIG) {
-			offset += le32toh(table_headers[1]);
-			continue;
-		}
-
-		if (relocate_patch_table(fsp, size, offset, adjustment)) {
-			printk(BIOS_ERR, "FSPP relocation failed.\n");
-			return -1;
-		}
-
-		return fih_offset;
-	}
-
-	printk(BIOS_ERR, "Could not find the FSP patch table.\n");
-	return -1;
-}
-
-static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size,
-				size_t fvh_offset, size_t *fih_offset)
-{
-	EFI_FIRMWARE_VOLUME_HEADER *fvh;
-	EFI_FFS_FILE_HEADER *ffsfh;
-	EFI_COMMON_SECTION_HEADER *csh;
-	size_t offset;
-	size_t file_offset;
-	size_t size;
-	size_t fv_length;
-
-	offset = fvh_offset;
-	fvh = relative_offset(fsp, offset);
-
-	if (le32toh(fvh->Signature) != EFI_FVH_SIGNATURE)
-		return -1;
-
-	fv_length = le64toh(fvh->FvLength);
-
-	printk(FSP_DBG_LVL, "FVH length: %zx Offset: %zx Mapping length: %zx\n",
-		fv_length, offset, fsp_size);
-
-	if (fvh->FvLength + offset > fsp_size)
-		return -1;
-
-	/* Parse only this FV. However, the algorithm uses offsets into the
-	 * entire FSP region so make size include the starting offset. */
-	size = fv_length + offset;
-
-	if (guid_compare(&fvh->FileSystemGuid, &ffs2_guid)) {
-		printk(BIOS_ERR, "FVH not an FFS2 type.\n");
-		return -1;
-	}
-
-	if (le16toh(fvh->ExtHeaderOffset) != 0) {
-		EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh;
-
-		offset += le16toh(fvh->ExtHeaderOffset);
-		fveh = relative_offset(fsp, offset);
-		printk(FSP_DBG_LVL, "Extended Header Offset: %zx Size: %zx\n",
-			(size_t)le16toh(fvh->ExtHeaderOffset),
-			(size_t)le32toh(fveh->ExtHeaderSize));
-		offset += le32toh(fveh->ExtHeaderSize);
-		/* FFS files are 8 byte aligned after extended header. */
-		offset = ALIGN_UP(offset, 8);
-	} else {
-		offset += le16toh(fvh->HeaderLength);
-	}
-
-	file_offset = offset;
-	while (file_offset + sizeof(*ffsfh) < size) {
-		offset = file_offset;
-		printk(FSP_DBG_LVL, "file offset: %zx\n", file_offset);
-
-		/* First file and section should be FSP info header. */
-		if (fih_offset != NULL && *fih_offset == 0)
-			*fih_offset = file_offset;
-
-		ffsfh = relative_offset(fsp, file_offset);
-
-		printk(FSP_DBG_LVL, "file type = %x\n", le8toh(ffsfh->Type));
-		printk(FSP_DBG_LVL, "file attribs = %x\n",
-			le8toh(ffsfh->Attributes));
-
-		/* Exit FV relocation when empty space found */
-		if (le8toh(ffsfh->Type) == EFI_FV_FILETYPE_FFS_MAX)
-			break;
-
-		/* Next file on 8 byte alignment. */
-		file_offset += ffs_file_size(ffsfh);
-		file_offset = ALIGN_UP(file_offset, 8);
-
-		/* Padding files have no section information. */
-		if (le8toh(ffsfh->Type) == EFI_FV_FILETYPE_FFS_PAD)
-			continue;
-
-		offset += file_section_offset(ffsfh);
-
-		while (offset + sizeof(*csh) < file_offset) {
-			size_t data_size;
-			size_t data_offset;
-
-			csh = relative_offset(fsp, offset);
-
-			printk(FSP_DBG_LVL, "section offset: %zx\n", offset);
-			printk(FSP_DBG_LVL, "section type: %x\n",
-				le8toh(csh->Type));
-
-			data_size = section_data_size(csh);
-			data_offset = section_data_offset(csh);
-
-			if (data_size + data_offset + offset > file_offset) {
-				printk(BIOS_ERR, "Section exceeds FV size.\n");
-				return -1;
-			}
-
-			/*
-			 * The entire FSP 1.1 image can be thought of as one
-			 * program with a single link address even though there
-			 * are multiple TEs linked separately. The reason is
-			 * that each TE is linked for XIP. So in order to
-			 * relocate the TE properly we need to form the
-			 * relocated address based on the TE offset within
-			 * FSP proper.
-			 */
-			if (le8toh(csh->Type) == EFI_SECTION_TE) {
-				void *te;
-				size_t te_offset = offset + data_offset;
-				uintptr_t te_addr = new_addr + te_offset;
-
-				printk(FSP_DBG_LVL, "TE image at offset %zx\n",
-					te_offset);
-				te = relative_offset(fsp, te_offset);
-				te_relocate(te_addr, te, data_size);
-			}
-
-			offset += data_size + data_offset;
-			/* Sections are aligned to 4 bytes. */
-			offset = ALIGN_UP(offset, 4);
-		}
-	}
-
-	/* Return amount of buffer parsed: FV size. */
-	return fv_length;
-}
-
-static ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size)
-{
-	size_t offset;
-	size_t fih_offset;
-
-	offset = 0;
-	fih_offset = 0;
-	while (offset < size) {
-		ssize_t nparsed;
-
-		/* Relocate each FV within the FSP region. The FSP_INFO_HEADER
-		 * should only be located in the first FV. */
-		if (offset == 0)
-			nparsed = relocate_fvh(new_addr, fsp, size, offset,
-						&fih_offset);
-		else
-			nparsed = relocate_fvh(new_addr, fsp, size, offset,
-						NULL);
-
-		/* FV should be larger than 0 or failed to parse. */
-		if (nparsed <= 0) {
-			printk(BIOS_ERR, "FV @ offset %zx relocation failed\n",
-				offset);
-			return -1;
-		}
-
-		offset += nparsed;
-	}
-
-	return relocate_remaining_items(fsp, size, new_addr, fih_offset);
-}
 
 int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src)
 {
@@ -564,7 +47,7 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src)
 		return -1;
 	}
 
-	fih = relative_offset(new_loc, fih_offset);
+	fih = (void *)((uint8_t *)new_loc + fih_offset);
 
 	prog_set_area(fsp_relocd, new_loc, size);
 	prog_set_entry(fsp_relocd, fih, NULL);
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 9695b3b..041c0f1 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -53,6 +53,12 @@ void *get_first_resource_hob(const EFI_GUID *guid);
  */
 int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
 
+/*
+ * Relocate FSP held within buffer defined by size to new_addr. Returns < 0
+ * on error, offset to FSP_INFO_HEADER on success.
+ */
+ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size);
+
 /* Additional HOB types not included in the FSP:
  * #define EFI_HOB_TYPE_HANDOFF 0x0001
  * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002


From gerrit at coreboot.org  Tue Sep 15 23:57:20 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 15 Sep 2015 23:57:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: Don't
	use fileno() to get file size
References: <I5be62a731f928333ea2e5843d81f541453fdb396+0@gerrit.coreboot.org>
Message-ID: <I5be62a731f928333ea2e5843d81f541453fdb396+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11636

-gerrit

commit 7537b72979188f4555ca3a6a2e46e6aa8dc3e7f9
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Sep 14 10:46:44 2015 -0700

    cbfstool: Don't use fileno() to get file size
    
    fileno() is a mess on some operating systems. Don't
    deliberately convert between FILE * and file handles.
    
    Change-Id: I5be62a731f928333ea2e5843d81f541453fdb396
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 util/cbfstool/common.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index f8ce2f9..e0474b3 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -46,14 +46,14 @@ int is_big_endian(void)
 
 static off_t get_file_size(FILE *f)
 {
-	struct stat s;
-	int fd = fileno(f);
-	if (fd == -1) return -1;
-	if (fstat(fd, &s) == -1) return -1;
-	return s.st_size;
+	off_t fsize;
+	fseek(f, 0, SEEK_END);
+	fsize = ftell(f);
+	fseek(f, 0, SEEK_SET);
+	return fsize;
 }
-/* Buffer and file I/O */
 
+/* Buffer and file I/O */
 int buffer_create(struct buffer *buffer, size_t size, const char *name)
 {
 	buffer->name = strdup(name);


From gerrit at coreboot.org  Wed Sep 16 00:39:08 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 16 Sep 2015 00:39:08 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: Fix
	tolower() calls on Cygwin
References: <Ie89153518d6af2bacce3f48fc7952fee17a688dd+0@gerrit.coreboot.org>
Message-ID: <Ie89153518d6af2bacce3f48fc7952fee17a688dd+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11666

-gerrit

commit 412c4732cf369edc2773521820145f4dee64aedb
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Sep 15 17:37:14 2015 -0700

    cbfstool: Fix tolower() calls on Cygwin
    
    Cygwin complains:
    
    cbfstool.c: 1075:5 error: array subscript has type 'char' [-Werror=char-subscripts]
    
    so add an explicit cast.
    
    Change-Id: Ie89153518d6af2bacce3f48fc7952fee17a688dd
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 util/cbfstool/cbfstool.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index d6c116a..7a2b7fe 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -1072,10 +1072,10 @@ int main(int argc, char **argv)
 				break;
 			case 's':
 				param.size = strtoul(optarg, &suffix, 0);
-				if (tolower(suffix[0])=='k') {
+				if (tolower((int)suffix[0])=='k') {
 					param.size *= 1024;
 				}
-				if (tolower(suffix[0])=='m') {
+				if (tolower((int)suffix[0])=='m') {
 					param.size *= 1024 * 1024;
 				}
 				break;


From gerrit at coreboot.org  Wed Sep 16 00:47:33 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 16 Sep 2015 00:47:33 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	compile successfully on Cygwin
References: <I068b181d67daf9c7280110e64aefb634aa20c69b+0@gerrit.coreboot.org>
Message-ID: <I068b181d67daf9c7280110e64aefb634aa20c69b+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11667

-gerrit

commit 6bd73d2fb74ef30b3259039d71f55cb3c9541a3b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Sep 15 17:41:07 2015 -0700

    cbfstool: compile successfully on Cygwin
    
    As reported in http://review.coreboot.org/#/c/10027
    cbfstool on Cygwin likes to be compiled with -D_GNU_SOURCE.
    That patch was abandoned because it would unwantedly turn on
    more GNU extensions. Instead of doing that, only enable the
    define on Cygwin, switch to -std=gnu99 instead of -std=c99 to
    make fileno and strdup actually available.
    A MINGW32 check that was forgotten in Makefile was copied over
    from Makefile.inc to keep the two files in sync.
    
    This patch has no impact on non-Windows builds.
    
    Change-Id: I068b181d67daf9c7280110e64aefb634aa20c69b
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 util/cbfstool/Makefile     | 11 ++++++++++-
 util/cbfstool/Makefile.inc |  7 ++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..0b47541 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -3,7 +3,7 @@ obj ?= .
 HOSTCC ?= $(CC)
 
 CFLAGS += -g3
-CFLAGS += -std=c99 -Werror -Wall -Wextra
+CFLAGS += -Werror -Wall -Wextra
 CFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
 CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
@@ -11,6 +11,15 @@ CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
 LDFLAGS += -g3
 
+ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
+CFLAGS+=-mno-ms-bitfields
+endif
+ifeq ($(shell uname -o), Cygwin)
+CFLAGS+=-std=gnu99 -D_GNU_SOURCE
+else
+CFLAGS+=-std=c99
+endif
+
 CBFSTOOL_BINARY:=$(obj)/cbfstool
 CBFSTOOL_COMMON:=common.o cbfs_image.o compress.o fit.o
 CBFSTOOL_COMMON+=elfheaders.o cbfs-mkstage.o cbfs-mkpayload.o xdr.o
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..ef03cc4 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -41,7 +41,7 @@ rmodobj += common.o
 rmodobj += elfheaders.o
 rmodobj += xdr.o
 
-TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra
+TOOLCFLAGS ?= -Werror -Wall -Wextra
 TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
 TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings
 TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h
@@ -54,6 +54,11 @@ TOOLLDFLAGS ?=
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
 TOOLFLAGS+=-mno-ms-bitfields
 endif
+ifeq ($(shell uname -o), Cygwin)
+TOOLFLAGS+=-std=gnu99 -D_GNU_SOURCE
+else
+TOOLFLAGS+=-std=c99
+endif
 
 $(objutil)/cbfstool/%.o: $(objutil)/cbfstool/%.c
 	printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"


From gerrit at coreboot.org  Wed Sep 16 01:21:38 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 16 Sep 2015 01:21:38 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	provide metadata size to cbfs_locate_entry()
References: <I2771116ea1ff439ea53b8886e1f33e0e637a79d4+0@gerrit.coreboot.org>
Message-ID: <I2771116ea1ff439ea53b8886e1f33e0e637a79d4+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11668

-gerrit

commit a2ef767a6438f683884873401bc3c17d1be69def
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 12:50:14 2015 -0500

    cbfstool: provide metadata size to cbfs_locate_entry()
    
    The cbfs_locate_entry() function had a hack in there which
    assumed a struct cbfs_stage data was being added in addition
    to the struct cbfs_file and name. Move that logic out to the
    callers while still maintaining the logic for consistency.
    The only impacted commands cbfs_add and cbfs_locate, but
    those are using the default 'always adding struct cbfs_stage'
    in addition to cbfs_file + name. Eventually those should be
    removed when cbfs_locate is removed as cbfs_add has no smarts
    related to the cbfs file type provided.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I2771116ea1ff439ea53b8886e1f33e0e637a79d4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/cbfs_image.c | 41 +++++++++++++++++------------------------
 util/cbfstool/cbfs_image.h |  4 ++--
 util/cbfstool/cbfstool.c   | 23 ++++++++++++++++++-----
 3 files changed, 37 insertions(+), 31 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index c2f0b37..55f8084 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -1136,20 +1136,20 @@ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page)
 }
 
 /* Tests if data can fit in a range by given offset:
- *  start ->| header_len | offset (+ size) |<- end
+ *  start ->| metadata_size | offset (+ size) |<- end
  */
-static int is_in_range(uint32_t start, uint32_t end, uint32_t header_len,
-		       uint32_t offset, uint32_t size)
+static int is_in_range(size_t start, size_t end, size_t metadata_size,
+		       size_t offset, size_t size)
 {
-	return (offset >= start + header_len && offset + size <= end);
+	return (offset >= start + metadata_size && offset + size <= end);
 }
 
-int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name,
-			  uint32_t size, uint32_t page_size, uint32_t align)
+int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size,
+			  size_t page_size, size_t align, size_t metadata_size)
 {
 	struct cbfs_file *entry;
 	size_t need_len;
-	uint32_t addr, addr_next, addr2, addr3, offset, header_len;
+	size_t addr, addr_next, addr2, addr3, offset;
 
 	/* Default values: allow fitting anywhere in ROM. */
 	if (!page_size)
@@ -1159,23 +1159,16 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name,
 		align = 1;
 
 	if (size > page_size)
-		ERROR("Input file size (%d) greater than page size (%d).\n",
+		ERROR("Input file size (%zd) greater than page size (%zd).\n",
 		      size, page_size);
 
-	uint32_t image_align = image->has_header ? image->header.align :
+	size_t image_align = image->has_header ? image->header.align :
 							CBFS_ENTRY_ALIGNMENT;
 	if (page_size % image_align)
-		WARN("%s: Page size (%#x) not aligned with CBFS image (%#x).\n",
+		WARN("%s: Page size (%#zx) not aligned with CBFS image (%#zx).\n",
 		     __func__, page_size, image_align);
 
-	/* TODO Old cbfstool always assume input is a stage file (and adding
-	 * sizeof(cbfs_stage) for header. We should fix that by adding "-t"
-	 * (type) param in future. For right now, we assume cbfs_stage is the
-	 * largest structure and add it into header size. */
-	assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload));
-	header_len = (cbfs_calculate_file_header_size(name) +
-		      sizeof(struct cbfs_stage));
-	need_len = header_len + size;
+	need_len = metadata_size + size;
 
 	// Merge empty entries to build get max available space.
 	cbfs_walk(image, cbfs_merge_empty_entry, NULL);
@@ -1215,26 +1208,26 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name,
 		if (addr_next - addr < need_len)
 			continue;
 
-		offset = align_up(addr + header_len, align);
+		offset = align_up(addr + metadata_size, align);
 		if (is_in_same_page(offset, size, page_size) &&
-		    is_in_range(addr, addr_next, header_len, offset, size)) {
+		    is_in_range(addr, addr_next, metadata_size, offset, size)) {
 			DEBUG("cbfs_locate_entry: FIT (PAGE1).");
 			return offset;
 		}
 
 		addr2 = align_up(addr, page_size);
 		offset = align_up(addr2, align);
-		if (is_in_range(addr, addr_next, header_len, offset, size)) {
+		if (is_in_range(addr, addr_next, metadata_size, offset, size)) {
 			DEBUG("cbfs_locate_entry: OVERLAP (PAGE2).");
 			return offset;
 		}
 
-		/* Assume page_size >= header_len so adding one page will
+		/* Assume page_size >= metadata_size so adding one page will
 		 * definitely provide the space for header. */
-		assert(page_size >= header_len);
+		assert(page_size >= metadata_size);
 		addr3 = addr2 + page_size;
 		offset = align_up(addr3, align);
-		if (is_in_range(addr, addr_next, header_len, offset, size)) {
+		if (is_in_range(addr, addr_next, metadata_size, offset, size)) {
 			DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3).");
 			return offset;
 		}
diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h
index aea8260..baceb51 100644
--- a/util/cbfstool/cbfs_image.h
+++ b/util/cbfstool/cbfs_image.h
@@ -112,8 +112,8 @@ int cbfs_create_empty_entry(struct cbfs_file *entry, int type,
  *  "page_size" limits the content to fit on same memory page, and
  *  "align" specifies starting address alignment.
  * Returns a valid offset, or -1 on failure. */
-int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name,
-			  uint32_t size, uint32_t page_size, uint32_t align);
+int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size,
+			  size_t page_size, size_t align, size_t metadata_size);
 
 /* Callback function used by cbfs_walk.
  * Returns 0 on success, or non-zero to stop further iteration. */
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index d6c116a..182fc8e 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -328,7 +328,7 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer,
 	return 0;
 }
 
-static int do_cbfs_locate(int32_t *cbfs_addr)
+static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size)
 {
 	if (!param.filename) {
 		ERROR("You need to specify -f/--filename.\n");
@@ -354,8 +354,11 @@ static int do_cbfs_locate(int32_t *cbfs_addr)
 		return 1;
 	}
 
-	int32_t address = cbfs_locate_entry(&image, param.name, buffer.size,
-				    param.pagesize, param.alignment);
+	/* Include cbfs_file size along with space for with name. */
+	metadata_size += cbfs_calculate_file_header_size(param.name);
+
+	int32_t address = cbfs_locate_entry(&image, buffer.size, param.pagesize,
+						param.alignment, metadata_size);
 	buffer_delete(&buffer);
 
 	if (address == -1) {
@@ -372,6 +375,16 @@ static int do_cbfs_locate(int32_t *cbfs_addr)
 	return 0;
 }
 
+static size_t cbfs_default_metadata_size(void)
+{
+	/* TODO Old cbfstool always assume input is a stage file (and adding
+	 * sizeof(cbfs_stage) for header. We should fix that by adding "-t"
+	 * (type) param in future. For right now, we assume cbfs_stage is the
+	 * largest structure and add it into header size. */
+	assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload));
+	return sizeof(struct cbfs_stage);
+}
+
 static int cbfs_add(void)
 {
 	int32_t address;
@@ -382,7 +395,7 @@ static int cbfs_add(void)
 	}
 
 	if (param.alignment) {
-		if (do_cbfs_locate(&address))
+		if (do_cbfs_locate(&address, cbfs_default_metadata_size()))
 			return 1;
 		param.baseaddress = address;
 	}
@@ -553,7 +566,7 @@ static int cbfs_locate(void)
 {
 	int32_t address;
 
-	if (do_cbfs_locate(&address) != 0)
+	if (do_cbfs_locate(&address, cbfs_default_metadata_size()) != 0)
 		return 1;
 
 	printf("0x%x\n", address);


From gerrit at coreboot.org  Wed Sep 16 01:21:40 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 16 Sep 2015 01:21:40 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: add
	--xip support to add-stage for x86
References: <I585619886f257e35f00961a1574009a51c28ff2b+0@gerrit.coreboot.org>
Message-ID: <I585619886f257e35f00961a1574009a51c28ff2b+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11669

-gerrit

commit cd00651df8229f023b65b540ce40b859aba3a4cb
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 17:00:23 2015 -0500

    cbfstool: add --xip support to add-stage for x86
    
    Instead of going through the locate then add-stage
    dance while linking romstage twice allow for adding romstage
    with --xip flags to perform the relocation while adding it
    into CBFS. The -P (page-size) and -a (alignment) parameters
    were added as well so one could specify the necessary
    parameters for x86 romstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted on glados.
    
    Change-Id: I585619886f257e35f00961a1574009a51c28ff2b
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/Makefile       |   1 +
 util/cbfstool/Makefile.inc   |   1 +
 util/cbfstool/cbfs-mkstage.c | 169 ++++++++++++++++++++++++++++++++++++++++---
 util/cbfstool/cbfstool.c     | 136 +++++++++++++++++++++-------------
 util/cbfstool/common.h       |   3 +
 5 files changed, 251 insertions(+), 59 deletions(-)

diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..b6fb38c 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -15,6 +15,7 @@ CBFSTOOL_BINARY:=$(obj)/cbfstool
 CBFSTOOL_COMMON:=common.o cbfs_image.o compress.o fit.o
 CBFSTOOL_COMMON+=elfheaders.o cbfs-mkstage.o cbfs-mkpayload.o xdr.o
 CBFSTOOL_COMMON+=partitioned_file.o linux_trampoline.o cbfs-payload-linux.o
+CBFSTOOL_COMMON+=rmodule.o
 # LZMA
 CBFSTOOL_COMMON+=lzma/lzma.o
 CBFSTOOL_COMMON+=lzma/C/LzFind.o  lzma/C/LzmaDec.o  lzma/C/LzmaEnc.o
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..99df7d7 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -6,6 +6,7 @@ cbfsobj += cbfs_image.o
 cbfsobj += cbfs-mkstage.o
 cbfsobj += cbfs-mkpayload.o
 cbfsobj += elfheaders.o
+cbfsobj += rmodule.o
 cbfsobj += xdr.o
 cbfsobj += fit.o
 cbfsobj += partitioned_file.o
diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c
index 3e62525..d2a2c46 100644
--- a/util/cbfstool/cbfs-mkstage.c
+++ b/util/cbfstool/cbfs-mkstage.c
@@ -28,6 +28,7 @@
 #include "elfparsing.h"
 #include "common.h"
 #include "cbfs.h"
+#include "rmodule.h"
 
 /* Checks if program segment contains the ignored section */
 static int is_phdr_ignored(Elf64_Phdr *phdr, Elf64_Shdr *shdr)
@@ -90,6 +91,21 @@ static Elf64_Shdr *find_ignored_section_header(struct parsed_elf *pelf,
 	return NULL;
 }
 
+static void fill_cbfs_stage(struct buffer *outheader, enum comp_algo algo,
+				uint64_t entry, uint64_t loadaddr,
+				uint32_t filesize, uint32_t memsize)
+{
+	/* N.B. The original plan was that SELF data was B.E.
+	 * but: this is all L.E.
+	 * Maybe we should just change the spec.
+	 */
+	xdr_le.put32(outheader, algo);
+	xdr_le.put64(outheader, entry);
+	xdr_le.put64(outheader, loadaddr);
+	xdr_le.put32(outheader, filesize);
+	xdr_le.put32(outheader, memsize);
+}
+
 /* returns size of result, or -1 if error.
  * Note that, with the new code, this function
  * works for all elf files, not just the restricted set.
@@ -262,18 +278,12 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
 	/* Set up for output marshaling. */
 	outheader.data = output->data;
 	outheader.size = 0;
-	/* N.B. The original plan was that SELF data was B.E.
-	 * but: this is all L.E.
-	 * Maybe we should just change the spec.
-	 */
-	xdr_le.put32(&outheader, algo);
+
 	/* Coreboot expects entry point to be physical address. Thus, adjust the
 	 * entry point accordingly.
 	 */
-	xdr_le.put64(&outheader, ehdr->e_entry + virt_to_phys);
-	xdr_le.put64(&outheader, data_start);
-	xdr_le.put32(&outheader, outlen);
-	xdr_le.put32(&outheader, mem_end - data_start);
+	fill_cbfs_stage(&outheader, algo, ehdr->e_entry + virt_to_phys,
+			data_start, outlen, mem_end - data_start);
 
 	if (*location)
 		*location -= sizeof(struct cbfs_stage);
@@ -284,3 +294,144 @@ err:
 	parsed_elf_destroy(&pelf);
 	return ret;
 }
+
+struct xip_context {
+	struct rmod_context rmodctx;
+	size_t ignored_section_idx;
+	Elf64_Shdr *ignored_section;
+};
+
+static int rmod_filter(struct reloc_filter *f, const Elf64_Rela *r)
+{
+	size_t symbol_index;
+	int reloc_type;
+	struct parsed_elf *pelf;
+	Elf64_Sym *sym;
+	struct xip_context *xipctx;
+
+	xipctx = f->context;
+	pelf = &xipctx->rmodctx.pelf;
+
+	/* Allow everything through if there isn't an ignored section. */
+	if (xipctx->ignored_section == NULL)
+		return 1;
+
+	reloc_type = ELF64_R_TYPE(r->r_info);
+	symbol_index = ELF64_R_SYM(r->r_info);
+	sym = &pelf->syms[symbol_index];
+
+	/* Nothing to filter. Relocation is not being applied to the
+	 * ignored section. */
+	if (sym->st_shndx != xipctx->ignored_section_idx)
+		return 1;
+
+	/* If there is any relocation to the ignored section that isn't
+	 * absolute fail as current assumptions are that all relocations
+	 * are absolute. */
+	if (reloc_type != R_386_32) {
+		ERROR("Invalid reloc to ignored section: %x\n", reloc_type);
+		return -1;
+	}
+
+	/* Relocation referencing ignored section. Don't emit it. */
+	return 0;
+}
+
+int parse_elf_to_xip_stage(const struct buffer *input, struct buffer *output,
+				uint32_t *location, const char *ignore_section)
+{
+	struct xip_context xipctx;
+	struct rmod_context *rmodctx;
+	struct reloc_filter filter;
+	struct parsed_elf *pelf;
+	size_t output_sz;
+	uint32_t adjustment;
+	struct buffer binput;
+	struct buffer boutput;
+	Elf64_Xword i;
+	int ret = -1;
+
+	xipctx.ignored_section_idx = 0;
+	rmodctx = &xipctx.rmodctx;
+	pelf = &rmodctx->pelf;
+
+	if (rmodule_init(rmodctx, input))
+		return -1;
+
+	/* Only support x86 XIP currently. */
+	if (rmodctx->pelf.ehdr.e_machine != EM_386) {
+		ERROR("Only support XIP stages for x86\n");
+		goto out;
+	}
+
+	xipctx.ignored_section =
+		find_ignored_section_header(pelf, ignore_section);
+
+	if (xipctx.ignored_section != NULL)
+		xipctx.ignored_section_idx =
+			xipctx.ignored_section - pelf->shdr;
+
+	filter.filter = rmod_filter;
+	filter.context = &xipctx;
+
+	if (rmodule_collect_relocations(rmodctx, &filter))
+		goto out;
+
+	output_sz = sizeof(struct cbfs_stage) + pelf->phdr->p_filesz;
+	if (buffer_create(output, output_sz, input->name) != 0) {
+		ERROR("Unable to allocate memory: %m\n");
+		goto out;
+	}
+	buffer_clone(&boutput, output);
+	memset(buffer_get(&boutput), 0, output_sz);
+	buffer_set_size(&boutput, 0);
+
+	/* Single loadable segment. The entire segment moves to final
+	 * location from based on virtual address of loadable segment. */
+	adjustment = *location - pelf->phdr->p_vaddr;
+	DEBUG("Relocation adjustment: %08x\n", adjustment);
+
+	fill_cbfs_stage(&boutput, CBFS_COMPRESS_NONE,
+			(uint32_t)pelf->ehdr.e_entry + adjustment,
+			(uint32_t)pelf->phdr->p_vaddr + adjustment,
+			pelf->phdr->p_filesz, pelf->phdr->p_memsz);
+	/* Need an adjustable buffer. */
+	buffer_clone(&binput, input);
+	buffer_seek(&binput, pelf->phdr->p_offset);
+	bputs(&boutput, buffer_get(&binput), pelf->phdr->p_filesz);
+
+	buffer_clone(&boutput, output);
+	buffer_seek(&boutput, sizeof(struct cbfs_stage));
+
+	/* Make adjustments to all the relocations within the program. */
+	for (i = 0; i < rmodctx->nrelocs; i++) {
+		size_t reloc_offset;
+		uint32_t val;
+		struct buffer in, out;
+
+		/* The relocations represent in-program addresses of the
+		 * linked program. Obtain the offset into the program to do
+		 * the adjustment. */
+		reloc_offset = rmodctx->emitted_relocs[i] - pelf->phdr->p_vaddr;
+
+		buffer_clone(&out, &boutput);
+		buffer_seek(&out, reloc_offset);
+		buffer_clone(&in, &out);
+		/* Appease around xdr semantics: xdr decrements buffer
+		 * size when get()ing and appends to size when put()ing. */
+		buffer_set_size(&out, 0);
+
+		val = xdr_le.get32(&in);
+		DEBUG("reloc %zx %08x -> %08x\n", reloc_offset, val,
+			val + adjustment);
+		xdr_le.put32(&out, val + adjustment);
+	}
+
+	/* Need to back up the location to include cbfs stage metadata. */
+	*location -= sizeof(struct cbfs_stage);
+	ret = 0;
+
+out:
+	rmodule_cleanup(rmodctx);
+	return ret;
+}
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 182fc8e..6f8f1f4 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -74,6 +74,7 @@ static struct param {
 	bool fill_partial_upward;
 	bool fill_partial_downward;
 	bool show_immutable;
+	bool stage_xip;
 	int fit_empty_entries;
 	enum comp_algo compression;
 	/* for linux payloads */
@@ -115,6 +116,53 @@ static unsigned convert_to_from_top_aligned(const struct buffer *region,
 	return image_size - region->offset - offset;
 }
 
+static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size)
+{
+	if (!param.filename) {
+		ERROR("You need to specify -f/--filename.\n");
+		return 1;
+	}
+
+	if (!param.name) {
+		ERROR("You need to specify -n/--name.\n");
+		return 1;
+	}
+
+	struct cbfs_image image;
+	if (cbfs_image_from_buffer(&image, param.image_region,
+							param.headeroffset))
+		return 1;
+
+	if (cbfs_get_entry(&image, param.name))
+		WARN("'%s' already in CBFS.\n", param.name);
+
+	struct buffer buffer;
+	if (buffer_from_file(&buffer, param.filename) != 0) {
+		ERROR("Cannot load %s.\n", param.filename);
+		return 1;
+	}
+
+	/* Include cbfs_file size along with space for with name. */
+	metadata_size += cbfs_calculate_file_header_size(param.name);
+
+	int32_t address = cbfs_locate_entry(&image, buffer.size, param.pagesize,
+						param.alignment, metadata_size);
+	buffer_delete(&buffer);
+
+	if (address == -1) {
+		ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n",
+		      param.name, param.pagesize, param.alignment);
+		return 1;
+	}
+
+	if (param.top_aligned)
+		address = -convert_to_from_top_aligned(param.image_region,
+								address);
+
+	*cbfs_addr = address;
+	return 0;
+}
+
 typedef int (*convert_buffer_t)(struct buffer *buffer, uint32_t *offset,
 	struct cbfs_file *header);
 
@@ -269,8 +317,26 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset,
 {
 	struct buffer output;
 	int ret;
-	ret = parse_elf_to_stage(buffer, &output, param.compression, offset,
-							param.ignore_section);
+
+	if (param.stage_xip) {
+		int32_t address;
+
+		if (do_cbfs_locate(&address, sizeof(struct cbfs_stage)))  {
+			ERROR("Could not find location for XIP stage.\n");
+			return 1;
+		}
+
+		/* Pass in a top aligned address. */
+		address = -convert_to_from_top_aligned(param.image_region,
+								address);
+		*offset = address;
+
+		ret = parse_elf_to_xip_stage(buffer, &output, offset,
+						param.ignore_section);
+	} else
+		ret = parse_elf_to_stage(buffer, &output, param.compression,
+					 offset, param.ignore_section);
+
 	if (ret != 0)
 		return -1;
 	buffer_delete(buffer);
@@ -328,53 +394,6 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer,
 	return 0;
 }
 
-static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size)
-{
-	if (!param.filename) {
-		ERROR("You need to specify -f/--filename.\n");
-		return 1;
-	}
-
-	if (!param.name) {
-		ERROR("You need to specify -n/--name.\n");
-		return 1;
-	}
-
-	struct cbfs_image image;
-	if (cbfs_image_from_buffer(&image, param.image_region,
-							param.headeroffset))
-		return 1;
-
-	if (cbfs_get_entry(&image, param.name))
-		WARN("'%s' already in CBFS.\n", param.name);
-
-	struct buffer buffer;
-	if (buffer_from_file(&buffer, param.filename) != 0) {
-		ERROR("Cannot load %s.\n", param.filename);
-		return 1;
-	}
-
-	/* Include cbfs_file size along with space for with name. */
-	metadata_size += cbfs_calculate_file_header_size(param.name);
-
-	int32_t address = cbfs_locate_entry(&image, buffer.size, param.pagesize,
-						param.alignment, metadata_size);
-	buffer_delete(&buffer);
-
-	if (address == -1) {
-		ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n",
-		      param.name, param.pagesize, param.alignment);
-		return 1;
-	}
-
-	if (param.top_aligned)
-		address = -convert_to_from_top_aligned(param.image_region,
-								address);
-
-	*cbfs_addr = address;
-	return 0;
-}
-
 static size_t cbfs_default_metadata_size(void)
 {
 	/* TODO Old cbfstool always assume input is a stage file (and adding
@@ -410,6 +429,18 @@ static int cbfs_add(void)
 
 static int cbfs_add_stage(void)
 {
+	if (param.stage_xip) {
+		if (param.baseaddress_assigned) {
+			ERROR("Cannot specify base address for XIP.\n");
+			return 1;
+		}
+
+		if (param.compression != CBFS_COMPRESS_NONE) {
+			ERROR("Cannot specify compression for XIP.\n");
+			return 1;
+		}
+	}
+
 	return cbfs_add_component(param.filename,
 				  param.name,
 				  CBFS_COMPONENT_STAGE,
@@ -822,7 +853,7 @@ static const struct command commands[] = {
 	{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
 									true},
 	{"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true},
-	{"add-stage", "H:r:f:n:t:c:b:S:vh?", cbfs_add_stage, true, true},
+	{"add-stage", "a:H:r:f:n:t:c:b:P:S:yvh?", cbfs_add_stage, true, true},
 	{"add-int", "H:r:i:n:b:vh?", cbfs_add_integer, true, true},
 	{"copy", "H:D:s:h?", cbfs_copy, true, true},
 	{"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true},
@@ -865,6 +896,7 @@ static struct option long_options[] = {
 	{"type",          required_argument, 0, 't' },
 	{"verbose",       no_argument,       0, 'v' },
 	{"with-readonly", no_argument,       0, 'w' },
+	{"xip",           no_argument,       0, 'y' },
 	{NULL,            0,                 0,  0  }
 };
 
@@ -941,6 +973,7 @@ static void usage(char *name)
 	     "        (linux specific: [-C cmdline] [-I initrd])\n"
 	     " add-stage [-r image,regions] -f FILE -n NAME \\\n"
 	     "        [-c compression] [-b base] [-S section-to-ignore]    "
+	     "        [-a alignment] [-y|--xip] [-P page-size]"
 			"Add a stage to the ROM\n"
 	     " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n"
 	     "        -l load-address -e entry-point [-c compression] \\\n"
@@ -1150,6 +1183,9 @@ int main(int argc, char **argv)
 			case 'S':
 				param.ignore_section = optarg;
 				break;
+			case 'y':
+				param.stage_xip = true;
+				break;
 			case 'h':
 			case '?':
 				usage(argv[0]);
diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h
index 4a97fed..8073d12 100644
--- a/util/cbfstool/common.h
+++ b/util/cbfstool/common.h
@@ -184,6 +184,9 @@ int parse_flat_binary_to_payload(const struct buffer *input,
 int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
 		       enum comp_algo algo, uint32_t *location,
 		       const char *ignore_section);
+/* location is TOP aligned. */
+int parse_elf_to_xip_stage(const struct buffer *input, struct buffer *output,
+				uint32_t *location, const char *ignore_section);
 
 void print_supported_filetypes(void);
 


From gerrit at coreboot.org  Wed Sep 16 01:21:42 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 16 Sep 2015 01:21:42 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: remove
	double link step for romstage
References: <I1ec555f523a94dd4b15fe8186cbe530520c622c0+0@gerrit.coreboot.org>
Message-ID: <I1ec555f523a94dd4b15fe8186cbe530520c622c0+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11670

-gerrit

commit 83001541f62c417cca9af9cf1427b0eeca8690c4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 17:04:13 2015 -0500

    x86: remove double link step for romstage
    
    Now that cbfstool supports XIP for romstage utilize it.
    This removes the double link steps with the cbfstool
    locate and add-stage sandwich.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted on glados.
    
    Change-Id: I1ec555f523a94dd4b15fe8186cbe530520c622c0
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc | 43 ++++++++++---------------------------------
 src/arch/x86/memlayout.ld |  5 +++--
 2 files changed, 13 insertions(+), 35 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 68ed810..79b82e0 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -54,8 +54,15 @@ mbi.bin-type := mbi
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 CBFSTOOL_PRE1_OPTS = -m x86 -s $(CONFIG_ROM_SIZE) \
 		     -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
+# Use a '-a 64' option to cbfstool locate to provide a minimum alignment
+# requirement for the overall romstage. While the first object within
+# romstage could have a 4 byte minimum alignment that doesn't mean the linker
+# won't decide the entire section should be aligned to a larger value. In the
+# future cbfstool should add XIP files proper and honor the alignment
+# requirements of the program segment.
+#
 # Make sure that segment for .car.data is ignored while adding romstage.
-CBFSTOOL_PRE_OPTS  = -b $(shell cat $(objcbfs)/base_xip.txt) -S ".car.data"
+CBFSTOOL_PRE_OPTS  = -a 64 --xip -S ".car.data" -P $(CONFIG_XIP_ROM_SIZE)
 endif
 
 ## Calculate the base address of CBFS for later comparisons
@@ -178,9 +185,9 @@ else
 romstage-oformat=elf64-x86-64
 endif
 
-$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
+$(objcbfs)/romstage.debug: $$(romstage-objs) $$(romstage-libs)
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat)
+	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(obj)/arch/x86/memlayout.romstage.ld --oformat $(romstage-oformat)
 	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
 	grep -v "Empty loadable segment detected" && \
 	$(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
@@ -188,36 +195,6 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.
 		$(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \
 		else true; fi
 
-$(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
-	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
-
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	rm -f $@
-	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $< >> $@.tmp
-	mv $@.tmp $@
-
-$(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	rm -f $@
-	sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(objcbfs)/base_xip.txt > $@.tmp
-	sed -e '/^ROMSTAGE_BASE/d' $(objgenerated)/romstage_null.ld >> $@.tmp
-	mv $@.tmp $@
-
-# Use a '-a 64' option to cbfstool locate to provide a minimum alignment
-# requirement for the overall romstage. While the first object within
-# romstage could have a 4 byte minimum alignment that doesn't mean the linker
-# won't decide the entire section should be aligned to a larger value. In the
-# future cbfstool should add XIP files proper and honor the alignment
-# requirements of the program segment.
-$(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
-	rm -f $@
-	$(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) -a 64 > $@.tmp \
-	 || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
-	mv $@.tmp $@
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 43c5229..475f9bc 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -33,8 +33,9 @@ SECTIONS
 	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 
 #elif ENV_ROMSTAGE
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
+	/* The 1M size is not allocated. It's just for basic size checking.
+	 * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
+	ROMSTAGE(32M, 1M)
 
 	/* Pull in the cache-as-ram rules. */
 	#include "car.ld"


From gerrit at coreboot.org  Wed Sep 16 01:52:02 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 01:52:02 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: AMD Steppe
	Eagle: update vendorcode header files to MullinsPI 1.0.0.A
References: <I605df26b61bdffabd74846206ad0b7bf677ebed1+0@gerrit.coreboot.org>
Message-ID: <E1Zc1tD-0000no-0H@mail.coreboot.org>

the following patch was just integrated into master:
commit 762cef9198bc79d98ceebebe063b42063b644479
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Wed Aug 12 08:44:30 2015 +0800

    AMD Steppe Eagle: update vendorcode header files to MullinsPI 1.0.0.A
    
    This is required the BLOB change I67817dc59
    AMD Steppe Eagle: Update to  MullinsPI 1.0.0.A (Binary PI 1.1).
    
    This is tested on Olive Hill Plus. The board can boot to Windows 7.
    PCIe slot, USB and NIC work.
    
    Change-Id: I605df26b61bdffabd74846206ad0b7bf677ebed1
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
    Reviewed-on: http://review.coreboot.org/11225
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11225 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 01:57:45 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 01:57:45 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: AMD Merlin
	Falcon: update vendorcode header files to CarrizoPI 1.1.0.0
References: <Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c+0@gerrit.coreboot.org>
Message-ID: <E1Zc1yj-0001FI-Bl@mail.coreboot.org>

the following patch was just integrated into master:
commit 9763d8e9d1f9e6d4dc26075544d1f9b20d86c614
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Mon Aug 10 06:43:31 2015 +0800

    AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.0
    
    This is required the BLOB change Icb7a4f07
    "AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)"
    
    This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the
    boards can boot to Windows 8.1. PCIe slots, USB and NIC work.
    
    Change-Id: Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
    Reviewed-on: http://review.coreboot.org/11148
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc at marcjonesconsulting.com>


See http://review.coreboot.org/11148 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 02:33:47 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 16 Sep 2015 02:33:47 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	remove locate command
References: <I3b6647bd4cac04a113ab3592f345281fbcd681af+0@gerrit.coreboot.org>
Message-ID: <I3b6647bd4cac04a113ab3592f345281fbcd681af+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11671

-gerrit

commit 8443a8fed4bf153deeb9b370e02915b8eb1623cb
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 21:30:58 2015 -0500

    cbfstool: remove locate command
    
    The locate command was previously being used for x86 romstage
    linking as well as alignment handling of files. The add command
    already supports alignment so there's no more users of the
    locate command. Remove the command as well as the '-T' (top-aligned)
    option.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Noted microcode being directly added.
    
    Change-Id: I3b6647bd4cac04a113ab3592f345281fbcd681af
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc             |  6 ++----
 util/cbfstool/cbfstool.c | 34 +++-------------------------------
 2 files changed, 5 insertions(+), 35 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..46d6eb2 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -562,8 +562,7 @@ cbfs-add-cmd = \
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 prebuild-files = \
 	       $(foreach file,$(cbfs-files), \
-	       $(if $(call extract_nth,6,$(file)),$(CBFSTOOL) $@.tmp locate -f $(call extract_nth,1,$(file)) -n $(call extract_nth,2,$(file)) -a $(call extract_nth,6,$(file))|xargs -i \
-	       $(cbfs-add-cmd) -b {} &&,\
+	       $(if $(call extract_nth,6,$(file)),$(cbfs-add-cmd) -a $(call extract_nth,6,$(file)) &&, \
 	       $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&))
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
@@ -580,8 +579,7 @@ prebuild-files = \
 	$(foreach file,$(cbfs-files), \
 	       $(if $(filter $(call strip_quotes, $(CONFIG_CBFS_PREFIX))/%,\
 	           $(call extract_nth,2,$(file))), \
-	       $(if $(call extract_nth,6,$(file)),$(CBFSTOOL) $@.tmp locate -f $(call extract_nth,1,$(file)) -n $(call extract_nth,2,$(file)) -a $(call extract_nth,6,$(file))|xargs -i \
-	       $(cbfs-add-cmd) -b {} &&,\
+	       $(if $(call extract_nth,6,$(file)),$(cbfs-add-cmd) -a $(call extract_nth,6,$(file)) &&,\
 	       $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)))
 
 .PHONY: $(obj)/coreboot.pre1
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 6f8f1f4..51a7501 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -70,7 +70,6 @@ static struct param {
 	uint32_t cbfsoffset;
 	uint32_t cbfsoffset_assigned;
 	uint32_t arch;
-	bool top_aligned;
 	bool fill_partial_upward;
 	bool fill_partial_downward;
 	bool show_immutable;
@@ -155,10 +154,6 @@ static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size)
 		return 1;
 	}
 
-	if (param.top_aligned)
-		address = -convert_to_from_top_aligned(param.image_region,
-								address);
-
 	*cbfs_addr = address;
 	return 0;
 }
@@ -394,16 +389,6 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer,
 	return 0;
 }
 
-static size_t cbfs_default_metadata_size(void)
-{
-	/* TODO Old cbfstool always assume input is a stage file (and adding
-	 * sizeof(cbfs_stage) for header. We should fix that by adding "-t"
-	 * (type) param in future. For right now, we assume cbfs_stage is the
-	 * largest structure and add it into header size. */
-	assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload));
-	return sizeof(struct cbfs_stage);
-}
-
 static int cbfs_add(void)
 {
 	int32_t address;
@@ -414,7 +399,9 @@ static int cbfs_add(void)
 	}
 
 	if (param.alignment) {
-		if (do_cbfs_locate(&address, cbfs_default_metadata_size()))
+		/* CBFS compression file attributes are uncondtionally added. */
+		size_t metadata_sz = sizeof(struct cbfs_file_attr_compression);
+		if (do_cbfs_locate(&address, metadata_sz))
 			return 1;
 		param.baseaddress = address;
 	}
@@ -593,17 +580,6 @@ static int cbfs_create(void)
 	return ret;
 }
 
-static int cbfs_locate(void)
-{
-	int32_t address;
-
-	if (do_cbfs_locate(&address, cbfs_default_metadata_size()) != 0)
-		return 1;
-
-	printf("0x%x\n", address);
-	return 0;
-}
-
 static int cbfs_layout(void)
 {
 	const struct fmap *fmap = partitioned_file_get_fmap(param.image_file);
@@ -858,7 +834,6 @@ static const struct command commands[] = {
 	{"copy", "H:D:s:h?", cbfs_copy, true, true},
 	{"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true},
 	{"extract", "H:r:n:f:vh?", cbfs_extract, true, false},
-	{"locate", "H:r:f:n:P:a:Tvh?", cbfs_locate, true, false},
 	{"layout", "wvh?", cbfs_layout, false, false},
 	{"print", "H:r:vh?", cbfs_print, true, false},
 	{"read", "r:f:vh?", cbfs_read, true, false},
@@ -1153,9 +1128,6 @@ int main(int argc, char **argv)
 			case 'i':
 				param.u64val = strtoull(optarg, NULL, 0);
 				break;
-			case 'T':
-				param.top_aligned = true;
-				break;
 			case 'u':
 				param.fill_partial_upward = true;
 				break;


From gerrit at coreboot.org  Wed Sep 16 07:43:38 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 07:43:38 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: abuild: don't
	create junit tests with empty testclass field
References: <Ifa79cbfd1f263e11a458b3cc320baeed6a3fbc98+0@gerrit.coreboot.org>
Message-ID: <E1Zc7NS-0000vf-9i@mail.coreboot.org>

the following patch was just integrated into master:
commit 098c4a80962437c6d23dc3fde894a1c3a7bf0ca0
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Tue Sep 15 16:57:04 2015 +0200

    abuild: don't create junit tests with empty testclass field
    
    Variable expansion made abuild create board..foo/bar, which are annoying
    on jenkins' web UI because it doesn't cope properly with the empty
    namespace between the dots. make it create board.foo/bar or
    board.$class.foo/bar.
    
    Change-Id: Ifa79cbfd1f263e11a458b3cc320baeed6a3fbc98
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11640
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11640 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 07:43:49 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 07:43:49 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: abuild: log
	bulding tools
References: <Ibcd3b02bce9a314c30b5f7414e9e4cf0149ffd6a+0@gerrit.coreboot.org>
Message-ID: <E1Zc7Nd-0000xM-Qs@mail.coreboot.org>

the following patch was just integrated into master:
commit 053322f891961be7d7826617d2e68dab340f9a09
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Tue Sep 15 17:30:52 2015 +0200

    abuild: log bulding tools
    
    We build the coreboot utilities in a separate step as a minor
    optimization. When logging in junit format (for jenkins), we want to
    have a report on those as well (instead of an xml error).
    
    Change-Id: Ibcd3b02bce9a314c30b5f7414e9e4cf0149ffd6a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11641
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11641 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 07:44:01 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 07:44:01 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: abuild: don't
	complain about missing junit reports for skipped boards
References: <I906fd04a315de70340ce76d7c38eaaf88cc6580a+0@gerrit.coreboot.org>
Message-ID: <E1Zc7Np-0000zH-Bv@mail.coreboot.org>

the following patch was just integrated into master:
commit a0e77384638878ffb8b6a970f4655eb071e8a7c1
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Tue Sep 15 19:32:28 2015 +0200

    abuild: don't complain about missing junit reports for skipped boards
    
    There's no need to whine about missing files, so test for them first.
    
    Change-Id: I906fd04a315de70340ce76d7c38eaaf88cc6580a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11642
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11642 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 10:52:41 2015
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Wed, 16 Sep 2015 10:52:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: sandy/ivy: Fix
	PIRQs on Chromebooks
References: <Ic90343401ac20ca8673baf927cd7703c3481aeab+0@gerrit.coreboot.org>
Message-ID: <Ic90343401ac20ca8673baf927cd7703c3481aeab+6@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9993

-gerrit

commit 786de4bec7a15ccd7714d429b54eb77f4b903274
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Sat Jun 6 11:52:24 2015 +0300

    sandy/ivy: Fix PIRQs on Chromebooks
    
    This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its
    internal USB EHCI controller broken, with no assigned IRQ.
    
    PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive
    for the GPIO to use. They cannot be used for PCI devices at the same time.
    
    Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 .../google/butterfly/acpi/sandybridge_pci_irqs.asl | 64 +++++++++++++++++++
 src/mainboard/google/butterfly/dsdt.asl            |  2 +-
 src/mainboard/google/butterfly/romstage.c          | 42 ++++++++++++-
 .../google/link/acpi/sandybridge_pci_irqs.asl      | 68 ++++++++++++++++++++
 src/mainboard/google/link/dsdt.asl                 |  2 +-
 src/mainboard/google/link/romstage.c               | 39 +++++++++++-
 .../google/parrot/acpi/sandybridge_pci_irqs.asl    | 68 ++++++++++++++++++++
 src/mainboard/google/parrot/dsdt.asl               |  2 +-
 src/mainboard/google/parrot/romstage.c             | 43 ++++++++++++-
 .../google/stout/acpi/sandybridge_pci_irqs.asl     | 72 ++++++++++++++++++++++
 src/mainboard/google/stout/dsdt.asl                |  2 +-
 src/mainboard/google/stout/romstage.c              | 43 ++++++++++++-
 .../samsung/lumpy/acpi/sandybridge_pci_irqs.asl    | 68 ++++++++++++++++++++
 src/mainboard/samsung/lumpy/dsdt.asl               |  2 +-
 src/mainboard/samsung/lumpy/romstage.c             | 36 ++++++++++-
 .../samsung/stumpy/acpi/sandybridge_pci_irqs.asl   | 68 ++++++++++++++++++++
 src/mainboard/samsung/stumpy/dsdt.asl              |  2 +-
 src/mainboard/samsung/stumpy/romstage.c            | 38 +++++++++++-
 18 files changed, 649 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..f2afacd
--- /dev/null
+++ b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P1IP  WLAN   INTA -> PIRQB
+			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P2IP  ETH0   INTB -> PIRQF
+			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P3IP  SDCARD INTC -> PIRQD
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },//  D26IP_E2P   EHCI2  INTA -> PIRQF
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP   SATA   INTA -> PIRQB (MSI)
+			Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP  SMBUS  INTB -> PIRQH
+			Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP  THRT   INTC -> PIRQA
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl
index 0a2f37d..365f89a 100644
--- a/src/mainboard/google/butterfly/dsdt.asl
+++ b/src/mainboard/google/butterfly/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index b25492d..f73e6bc 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -60,7 +60,47 @@ void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P2IP  ETH0   INTB -> PIRQF
+	 * D28IP_P3IP  SDCARD INTC -> PIRQD
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQF
+	 * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
+	 * D31IP_TTIP  THRT   INTC -> PIRQA
+	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+	 *
+	 * Trackpad interrupt is edge triggered and cannot be shared.
+	 * TRACKPAD                -> PIRQG
+
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+			(INTC << D28IP_P3IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..2c2e1ec
--- /dev/null
+++ b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 },
+			Package() { 0x001fffff, 1, 0, 23 },
+			Package() { 0x001fffff, 2, 0, 16 },
+			Package() { 0x001fffff, 3, 0, 18 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl
index a01533f..1b35193 100644
--- a/src/mainboard/google/link/dsdt.asl
+++ b/src/mainboard/google/link/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index e9b4a09..505e25c 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -76,7 +76,44 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P3IP  WLAN   INTA -> PIRQB
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQF
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
+	 * D31IP_TTIP  THRT   INTC -> PIRQA
+	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+	 *
+	 * TRACKPAD                -> PIRQE (Edge Triggered)
+	 * TOUCHSCREEN             -> PIRQG (Edge Triggered)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P3IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..2c2e1ec
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 },
+			Package() { 0x001fffff, 1, 0, 23 },
+			Package() { 0x001fffff, 2, 0, 16 },
+			Package() { 0x001fffff, 3, 0, 18 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl
index 0a2f37d..365f89a 100644
--- a/src/mainboard/google/parrot/dsdt.asl
+++ b/src/mainboard/google/parrot/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index a947c48..b073fe7 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -60,7 +60,48 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P2IP  WLAN   INTA -> PIRQB
+	 * D28IP_P3IP  ETH0   INTC -> PIRQD
+	 * D29IP_E1P   EHCI1  INTA -> PIRQE
+	 * D26IP_E2P   EHCI2  INTA -> PIRQE
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
+	 * D31IP_TTIP  THRT   INTC -> PIRQH
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 *
+	 * Trackpad DVT PIRQA (16)
+	 * Trackpad DVT PIRQE (20)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
+		(INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
+		(NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
+		(NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..3fe7a46
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// XHCI	0:14.0
+			Package() { 0x0014ffff, 0, 0, 19 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 },
+			Package() { 0x001fffff, 1, 0, 23 },
+			Package() { 0x001fffff, 2, 0, 16 },
+			Package() { 0x001fffff, 3, 0, 18 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// XHCI   0:14.0
+			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl
index 01e4001..c7ab62d 100644
--- a/src/mainboard/google/stout/dsdt.asl
+++ b/src/mainboard/google/stout/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 31b61e2..43ac459 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -66,7 +66,48 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX         INTA -> PIRQA (MSI)
+	 * D20IP_XHCI  XHCI        INTA -> PIRQD (MSI)
+	 * D26IP_E2P   EHCI #2     INTA -> PIRQF
+	 * D27IP_ZIP   HDA         INTA -> PIRQA (MSI)
+	 * D28IP_P2IP  WLAN        INTA -> PIRQD
+	 * D28IP_P3IP  Card Reader INTB -> PIRQE
+	 * D28IP_P6IP  LAN         INTC -> PIRQB
+	 * D29IP_E1P   EHCI #1     INTA -> PIRQD
+	 * D31IP_SIP   SATA        INTA -> PIRQB (MSI)
+	 * D31IP_SMIP  SMBUS       INTB -> PIRQH
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
+		(INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
+		(NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
+		(NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+	RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
+	DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..3762372
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 16 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 17 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 16 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 17 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
index 1ab6322..107e1aa 100644
--- a/src/mainboard/samsung/lumpy/dsdt.asl
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -50,7 +50,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 015ae08..e067da0 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -72,7 +72,41 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC (MSI)
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQB
+	 * D31IP_SIP   SATA   INTA -> PIRQA (MSI)
+	 * D31IP_SMIP  SMBUS  INTC -> PIRQH
+	 * D31IP_TTIP  THRT   INTB -> PIRQG
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 *
+	 * LIGHTSENSOR             -> PIRQE (Edge Triggered)
+	 * TRACKPAD                -> PIRQF (Edge Triggered)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTC << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 
 	/* Enable IOAPIC (generic) */
 	RCBA16(OIC) = 0x0100;
diff --git a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..7d692b9
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 20 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 20 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 21 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 16 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl
index 0a2f37d..365f89a 100644
--- a/src/mainboard/samsung/stumpy/dsdt.asl
+++ b/src/mainboard/samsung/stumpy/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 161c8d1..fc0a2e9 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -84,7 +84,43 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQE
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
+	 * D31IP_TTIP  THRT   INTC -> PIRQH
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);


From gerrit at coreboot.org  Wed Sep 16 12:28:49 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 16 Sep 2015 12:28:49 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: Add
	header file for ntohl & htonl on Apple
References: <Ia942c58f34637c18222fbf985b93c48abf63c5b8+0@gerrit.coreboot.org>
Message-ID: <Ia942c58f34637c18222fbf985b93c48abf63c5b8+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11672

-gerrit

commit a9d4f828d81b558fc1cdbefb568a60d8eb2e0f1b
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Sep 16 13:27:22 2015 -0700

    cbfstool: Add header file for ntohl & htonl on Apple
    
    On Apple OS X, the ntohl and htonl need including header,
     #include <arpa/inet.h>
    
    Please refer the manpage for these command on OS X,
    https://developer.apple.com/library/mac/documentation/Darwin/Reference/ManPages/man3/htonl.3.html
    
    Change-Id: Ia942c58f34637c18222fbf985b93c48abf63c5b8
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/cbfstool/swab.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/cbfstool/swab.h b/util/cbfstool/swab.h
index 22ae8b4..a45a767 100644
--- a/util/cbfstool/swab.h
+++ b/util/cbfstool/swab.h
@@ -18,7 +18,7 @@
 #if !defined(__APPLE__) && !defined(__NetBSD__)
 #define ntohl(x)	(is_big_endian() ? (uint32_t)(x) : swab32(x))
 #define htonl(x)	(is_big_endian() ? (uint32_t)(x) : swab32(x))
-#elif defined(__NetBSD__)
+#else
 #include <arpa/inet.h>
 #endif
 #define ntohll(x)	(is_big_endian() ? (uint64_t)(x) : swab64(x))


From gerrit at coreboot.org  Wed Sep 16 13:24:27 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 16 Sep 2015 13:24:27 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload: usb:
	dwc2: fix hub hot-plug bug
References: <Ib4604097743f2f9d763b29ee27f3bc1788a85a62+0@gerrit.coreboot.org>
Message-ID: <Ib4604097743f2f9d763b29ee27f3bc1788a85a62+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11661

-gerrit

commit f189d3ea9752d84a8e56f4dec89f469e26a0efc0
Author: Yunzhi Li <lyz at rock-chips.com>
Date:   Fri Aug 28 09:43:44 2015 +0800

    libpayload: usb: dwc2: fix hub hot-plug bug
    
    When disconnect is detected in dwc2_split_transfer() the split
    configuration registers should be cleared before return.
    
    BRANCH=None
    BUG=chrome-os-partner:44534
    TEST=On Jerry, usb hot plug works with devices behind hubs
    
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 37594d8b4490b6d393d19d17d8e497db7de8817d
    Original-Change-Id: Ie1eecec067305874513c6ceb95df4240dc393cd6
    Original-Signed-off-by: Yunzhi Li <lyz at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295625
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Commit-Queue: Lin Huang <hl at rock-chips.com>
    Original-Tested-by: Lin Huang <hl at rock-chips.com>
    Original-(cherry picked from commit d543e14cdc73bd549dd553c8d1d07672a1307981)
    Original-Reviewed-on: https://chromium-review.googlesource.com/299700
    Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: Ib4604097743f2f9d763b29ee27f3bc1788a85a62
---
 payloads/libpayload/drivers/usb/dwc2.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index 30e00fb..0941eb6 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -323,8 +323,10 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 	do {
 		hfnum.d32 = readl(&reg->host.hfnum);
 
-		if (dwc2_disconnected(ep->dev->controller))
-			return -HCSTAT_DISCONNECTED;
+		if (dwc2_disconnected(ep->dev->controller)) {
+			ret = -HCSTAT_DISCONNECTED;
+			goto out;
+		}
 	} while (hfnum.frnum % 8 != 0);
 
 	/* Handle Start-Split */


From gerrit at coreboot.org  Wed Sep 16 13:32:52 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 16 Sep 2015 13:32:52 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: remove
	locate command
References: <I3b6647bd4cac04a113ab3592f345281fbcd681af+0@gerrit.coreboot.org>
Message-ID: <I3b6647bd4cac04a113ab3592f345281fbcd681af+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11671

-gerrit

commit a91165cc1f35328113ed718a89896ab95ab4572a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 21:30:58 2015 -0500

    cbfstool: remove locate command
    
    The locate command was previously being used for x86 romstage
    linking as well as alignment handling of files. The add command
    already supports alignment so there's no more users of the
    locate command. Remove the command as well as the '-T' (top-aligned)
    option.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Noted microcode being directly added.
    
    Change-Id: I3b6647bd4cac04a113ab3592f345281fbcd681af
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc             |  6 ++----
 util/cbfstool/cbfstool.c | 34 +++-------------------------------
 2 files changed, 5 insertions(+), 35 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..46d6eb2 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -562,8 +562,7 @@ cbfs-add-cmd = \
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 prebuild-files = \
 	       $(foreach file,$(cbfs-files), \
-	       $(if $(call extract_nth,6,$(file)),$(CBFSTOOL) $@.tmp locate -f $(call extract_nth,1,$(file)) -n $(call extract_nth,2,$(file)) -a $(call extract_nth,6,$(file))|xargs -i \
-	       $(cbfs-add-cmd) -b {} &&,\
+	       $(if $(call extract_nth,6,$(file)),$(cbfs-add-cmd) -a $(call extract_nth,6,$(file)) &&, \
 	       $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&))
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
@@ -580,8 +579,7 @@ prebuild-files = \
 	$(foreach file,$(cbfs-files), \
 	       $(if $(filter $(call strip_quotes, $(CONFIG_CBFS_PREFIX))/%,\
 	           $(call extract_nth,2,$(file))), \
-	       $(if $(call extract_nth,6,$(file)),$(CBFSTOOL) $@.tmp locate -f $(call extract_nth,1,$(file)) -n $(call extract_nth,2,$(file)) -a $(call extract_nth,6,$(file))|xargs -i \
-	       $(cbfs-add-cmd) -b {} &&,\
+	       $(if $(call extract_nth,6,$(file)),$(cbfs-add-cmd) -a $(call extract_nth,6,$(file)) &&,\
 	       $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)))
 
 .PHONY: $(obj)/coreboot.pre1
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 6f8f1f4..c45f316 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -70,7 +70,6 @@ static struct param {
 	uint32_t cbfsoffset;
 	uint32_t cbfsoffset_assigned;
 	uint32_t arch;
-	bool top_aligned;
 	bool fill_partial_upward;
 	bool fill_partial_downward;
 	bool show_immutable;
@@ -155,10 +154,6 @@ static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size)
 		return 1;
 	}
 
-	if (param.top_aligned)
-		address = -convert_to_from_top_aligned(param.image_region,
-								address);
-
 	*cbfs_addr = address;
 	return 0;
 }
@@ -394,16 +389,6 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer,
 	return 0;
 }
 
-static size_t cbfs_default_metadata_size(void)
-{
-	/* TODO Old cbfstool always assume input is a stage file (and adding
-	 * sizeof(cbfs_stage) for header. We should fix that by adding "-t"
-	 * (type) param in future. For right now, we assume cbfs_stage is the
-	 * largest structure and add it into header size. */
-	assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload));
-	return sizeof(struct cbfs_stage);
-}
-
 static int cbfs_add(void)
 {
 	int32_t address;
@@ -414,7 +399,9 @@ static int cbfs_add(void)
 	}
 
 	if (param.alignment) {
-		if (do_cbfs_locate(&address, cbfs_default_metadata_size()))
+		/* CBFS compression file attribute is unconditionally added. */
+		size_t metadata_sz = sizeof(struct cbfs_file_attr_compression);
+		if (do_cbfs_locate(&address, metadata_sz))
 			return 1;
 		param.baseaddress = address;
 	}
@@ -593,17 +580,6 @@ static int cbfs_create(void)
 	return ret;
 }
 
-static int cbfs_locate(void)
-{
-	int32_t address;
-
-	if (do_cbfs_locate(&address, cbfs_default_metadata_size()) != 0)
-		return 1;
-
-	printf("0x%x\n", address);
-	return 0;
-}
-
 static int cbfs_layout(void)
 {
 	const struct fmap *fmap = partitioned_file_get_fmap(param.image_file);
@@ -858,7 +834,6 @@ static const struct command commands[] = {
 	{"copy", "H:D:s:h?", cbfs_copy, true, true},
 	{"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true},
 	{"extract", "H:r:n:f:vh?", cbfs_extract, true, false},
-	{"locate", "H:r:f:n:P:a:Tvh?", cbfs_locate, true, false},
 	{"layout", "wvh?", cbfs_layout, false, false},
 	{"print", "H:r:vh?", cbfs_print, true, false},
 	{"read", "r:f:vh?", cbfs_read, true, false},
@@ -1153,9 +1128,6 @@ int main(int argc, char **argv)
 			case 'i':
 				param.u64val = strtoull(optarg, NULL, 0);
 				break;
-			case 'T':
-				param.top_aligned = true;
-				break;
 			case 'u':
 				param.fill_partial_upward = true;
 				break;


From gerrit at coreboot.org  Wed Sep 16 14:10:45 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:10:45 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	prepare for exposing rmodule logic
References: <I176d0ae0ae1933cdf6adac67d393ba676198861a+0@gerrit.coreboot.org>
Message-ID: <E1ZcDQ6-0001J3-0I@mail.coreboot.org>

the following patch was just integrated into master:
commit 051a181f0c0823d1dc08ac0c8d5d3820ef61d03e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 15:52:01 2015 -0500

    cbfstool: prepare for exposing rmodule logic
    
    The core logic of the rmodule parser is ideal for
    processing romstage ELF files for XIP. To that
    end start the work of exposing the logic from
    rmodule so cbfstool can take advantage of it.
    
    The properties that both need require:
    - Single program segment
    - Relocation information
    - Filter relocation processing
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11595
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11595 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:10:56 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:10:56 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	expose rmodule logic
References: <I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4+0@gerrit.coreboot.org>
Message-ID: <E1ZcDQG-0001KX-KY@mail.coreboot.org>

the following patch was just integrated into master:
commit b39a974d75ac597b29eb83b5ce347a506e0e6015
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 17:24:04 2015 -0500

    cbfstool: expose rmodule logic
    
    In order to allow cbfstool to add XIP romstage on x86 without
    doing the 'cbfstool locate', relink, then 'cbfstool add' dance
    expose the core logic and of rmodule including proving an optional
    filter. The filter will be used for ignoring relocations to the
    .car.global region.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11598
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11598 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:11:10 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:11:10 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	provide metadata size to cbfs_locate_entry()
References: <I2771116ea1ff439ea53b8886e1f33e0e637a79d4+0@gerrit.coreboot.org>
Message-ID: <E1ZcDQU-0001N2-1q@mail.coreboot.org>

the following patch was just integrated into master:
commit d7339411a983e562cddeba676384ad836bb56ec9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 12:50:14 2015 -0500

    cbfstool: provide metadata size to cbfs_locate_entry()
    
    The cbfs_locate_entry() function had a hack in there which
    assumed a struct cbfs_stage data was being added in addition
    to the struct cbfs_file and name. Move that logic out to the
    callers while still maintaining the logic for consistency.
    The only impacted commands cbfs_add and cbfs_locate, but
    those are using the default 'always adding struct cbfs_stage'
    in addition to cbfs_file + name. Eventually those should be
    removed when cbfs_locate is removed as cbfs_add has no smarts
    related to the cbfs file type provided.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi.
    
    Change-Id: I2771116ea1ff439ea53b8886e1f33e0e637a79d4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11668
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11668 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:11:16 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:11:16 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool: add
	--xip support to add-stage for x86
References: <I585619886f257e35f00961a1574009a51c28ff2b+0@gerrit.coreboot.org>
Message-ID: <E1ZcDQa-0001O8-Mu@mail.coreboot.org>

the following patch was just integrated into master:
commit 4be1674d32f7027a69a253704081599463188462
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 17:00:23 2015 -0500

    cbfstool: add --xip support to add-stage for x86
    
    Instead of going through the locate then add-stage
    dance while linking romstage twice allow for adding romstage
    with --xip flags to perform the relocation while adding it
    into CBFS. The -P (page-size) and -a (alignment) parameters
    were added as well so one could specify the necessary
    parameters for x86 romstage.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted on glados.
    
    Change-Id: I585619886f257e35f00961a1574009a51c28ff2b
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11669
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11669 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:11:24 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:11:24 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: remove
	double link step for romstage
References: <I1ec555f523a94dd4b15fe8186cbe530520c622c0+0@gerrit.coreboot.org>
Message-ID: <E1ZcDQi-0001Pz-Hr@mail.coreboot.org>

the following patch was just integrated into master:
commit 294ce854241db5c50af7ab012f5fdb23b033fabf
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 17:04:13 2015 -0500

    x86: remove double link step for romstage
    
    Now that cbfstool supports XIP for romstage utilize it.
    This removes the double link steps with the cbfstool
    locate and add-stage sandwich.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted on glados.
    
    Change-Id: I1ec555f523a94dd4b15fe8186cbe530520c622c0
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11670
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11670 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:11:33 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:11:33 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	remove locate command
References: <I3b6647bd4cac04a113ab3592f345281fbcd681af+0@gerrit.coreboot.org>
Message-ID: <E1ZcDQr-0001RU-IG@mail.coreboot.org>

the following patch was just integrated into master:
commit 9b9d4b3a474a4be3e9fd62651258152cffde6c82
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 15 21:30:58 2015 -0500

    cbfstool: remove locate command
    
    The locate command was previously being used for x86 romstage
    linking as well as alignment handling of files. The add command
    already supports alignment so there's no more users of the
    locate command. Remove the command as well as the '-T' (top-aligned)
    option.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built rambi. Noted microcode being directly added.
    
    Change-Id: I3b6647bd4cac04a113ab3592f345281fbcd681af
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11671
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11671 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:35:56 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 16 Sep 2015 14:35:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Move final Intel
	chipsets with ME to intel/common/firmware
References: <Id3bec6dbe2e1a8a90f51d9378150dbb44258b596+0@gerrit.coreboot.org>
Message-ID: <Id3bec6dbe2e1a8a90f51d9378150dbb44258b596+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10876

-gerrit

commit 70c461e8744d434964e52e7466c203bf099ab48c
Author: Martin Roth <gaumless at gmail.com>
Date:   Thu Jul 9 21:02:26 2015 -0600

    Move final Intel chipsets with ME to intel/common/firmware
    
    This switches the final 4 Intel platforms that use ME firmware from
    using code specific to the platform to the common IFD Kconfig and
    Makefile.
    
    braswell, broadwell, bd82x6x (cougar point & panther point) and ibexpeak
    
    Change-Id: Id3bec6dbe2e1a8a90f51d9378150dbb44258b596
    Signed-off-by: Martin Roth <gaumless at gmail.com>
---
 src/soc/intel/braswell/Kconfig              | 68 ++--------------------
 src/soc/intel/braswell/Makefile.inc         | 51 +----------------
 src/soc/intel/broadwell/Kconfig             | 69 +---------------------
 src/soc/intel/broadwell/Makefile.inc        | 46 +--------------
 src/southbridge/intel/bd82x6x/Kconfig       | 88 +----------------------------
 src/southbridge/intel/bd82x6x/Makefile.inc  | 53 +----------------
 src/southbridge/intel/ibexpeak/Kconfig      | 63 +--------------------
 src/southbridge/intel/ibexpeak/Makefile.inc | 51 +----------------
 8 files changed, 16 insertions(+), 473 deletions(-)

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index ab99a08..043dc1a 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
 	select USE_GENERIC_FSP_CAR_INC
+	select HAVE_INTEL_FIRMWARE
 
 config BOOTBLOCK_CPU_INIT
 	string
@@ -116,19 +117,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
 	  the system will reset otherwise the ramstage will be reloaded from
 	  cbfs.
 
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
-
 config ENABLE_BUILTIN_COM1
 	bool "Enable builtin COM1 Serial Port"
 	default n
@@ -138,66 +126,18 @@ config ENABLE_BUILTIN_COM1
 	  the debug console.
 
 config HAVE_IFD_BIN
-	bool
-	default y
+	def_bool y
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-		   was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+	def_bool !HAVE_IFD_BIN
 
 config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
+	def_bool y
 
 config IED_REGION_SIZE
 	hex
 	default 0x400000
 
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
-
 config CHIPSET_BOOTBLOCK_INCLUDE
 	string
 	default "soc/intel/braswell/bootblock/timestamp.inc"
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index fae97b8..eda9f76 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../southbridge/intel/common/firmware
 
 romstage-y += gpio_support.c
 romstage-y += iosf.c
@@ -56,54 +57,4 @@ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE := pch_add_me
-
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	printf "CONFIG_IFD_BIN_PATH: $(CONFIG_IFD_BIN_PATH)\n"
-	printf "IFD_BIN_PATH: $(IFD_BIN_PATH)\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-	printf "CONFIG_HAVE_ME_BIN: $(CONFIG_HAVE_ME_BIN)\n"
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	printf "CONFIG_ME_BIN_PATH: $(CONFIG_ME_BIN_PATH)\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += pch_add_me
-
 endif
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index c2db2a1..e01d559 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
 	select SOC_INTEL_COMMON
+	select HAVE_INTEL_FIRMWARE
 
 config BOOTBLOCK_CPU_INIT
 	string
@@ -203,74 +204,10 @@ config REFCODE_BLOB_FILE
 endif # HAVE_REFCODE_BLOB
 
 config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
-
-config HAVE_IFD_BIN
-	bool "Use Intel Firmware Descriptor from existing binary"
-	default n
+	def_bool y
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-		   was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
+	def_bool !HAVE_IFD_BIN
 
 config CHIPSET_BOOTBLOCK_INCLUDE
 	string
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index ca295fc..183c40f 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += acpi.c
 ramstage-y += adsp.c
@@ -75,51 +76,6 @@ endif
 
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE := broadwell_add_me
-
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-broadwell_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-endif
-
-PHONY += broadwell_add_me
-
 # If an MRC file is an ELF file determine the entry address and first loadable
 # section offset in the file. Subtract the offset from the entry address to
 # determine the final location.
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 3a68fec..9bdeefa 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -38,6 +38,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select SPI_FLASH
 	select COMMON_FADT
 	select ACPI_SATA_GENERATOR
+	select HAVE_INTEL_FIRMWARE
 
 config EHCI_BAR
 	hex
@@ -63,93 +64,10 @@ config HPET_MIN_TICKS
 	default 0x80
 
 config HAVE_IFD_BIN
-	bool
-	default y
+	def_bool y
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-	           was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_GBE_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config HAVE_GBE_BIN
-	bool "Add gigabit ethernet firmware"
-	default n
-	help
-	  The integrated gigabit ethernet controller needs a firmware file.
-	  Select this if you are going to use the PCH integrated controller
-	  and have the firmware.
-
-config GBE_BIN_PATH
-	string "Path to gigabit ethernet firmware"
-	depends on HAVE_GBE_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
-
-config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
-
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	depends on !BUILD_WITH_FAKE_IFD
-	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
+	def_bool !HAVE_IFD_BIN
 
 endif
 
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index a7b509c..9214450 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -19,10 +19,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE+=bd82x6x_add_me
+subdirs-y += ../common/firmware
 
 ramstage-y += pch.c
 ramstage-y += azalia.c
@@ -62,52 +59,4 @@ romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early
 
 ramstage-y += madt.c
 
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-ifeq ($(CONFIG_HAVE_GBE_BIN),y)
-	printf "    IFDTOOL    gbe.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i GbE:$(CONFIG_GBE_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += bd82x6x_add_me
-
 endif
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index f31f83c..a2c5153 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -36,6 +36,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select HAVE_USBDEBUG_OPTIONS
 	select COMMON_FADT
 	select ACPI_SATA_GENERATOR
+	select HAVE_INTEL_FIRMWARE
 
 config EHCI_BAR
 	hex
@@ -57,70 +58,10 @@ config SERIRQ_CONTINUOUS_MODE
 	  operated in continuous mode.
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-	           was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-
-config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default n
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
+	def_bool !HAVE_IFD_BIN
 
 config HPET_MIN_TICKS
 	hex
 	default 0x80
 
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
-
 endif
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 06c5853..57c498d 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -19,10 +19,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE+=bd82x6x_add_me
+subdirs-y += ../common/firmware
 
 ramstage-y += ../bd82x6x/pch.c
 ramstage-y += azalia.c
@@ -57,50 +54,4 @@ romstage-y += ../bd82x6x/early_rcba.c
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c
 
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built without Management Engine firmware.\n"
-	printf "Never write a complete coreboot.rom without ME to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-endif
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += bd82x6x_add_me
-
 endif


From gerrit at coreboot.org  Wed Sep 16 14:36:04 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:36:04 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: Move final
	Intel chipsets with ME to intel/common/firmware
References: <Id3bec6dbe2e1a8a90f51d9378150dbb44258b596+0@gerrit.coreboot.org>
Message-ID: <E1ZcDoa-0003Z0-NR@mail.coreboot.org>

the following patch was just integrated into master:
commit 3fda3c2f8d61e7b5d23534ecdcb580005dff6292
Author: Martin Roth <gaumless at gmail.com>
Date:   Thu Jul 9 21:02:26 2015 -0600

    Move final Intel chipsets with ME to intel/common/firmware
    
    This switches the final 4 Intel platforms that use ME firmware from
    using code specific to the platform to the common IFD Kconfig and
    Makefile.
    
    braswell, broadwell, bd82x6x (cougar point & panther point) and ibexpeak
    
    Change-Id: Id3bec6dbe2e1a8a90f51d9378150dbb44258b596
    Signed-off-by: Martin Roth <gaumless at gmail.com>
    Reviewed-on: http://review.coreboot.org/10876
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/10876 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:37:31 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 16 Sep 2015 14:37:31 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	actually use no-ms-bitfields flag on mingw
References: <I869ffdda7e04b5c615931473c760d66b803fb98b+0@gerrit.coreboot.org>
Message-ID: <I869ffdda7e04b5c615931473c760d66b803fb98b+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11673

-gerrit

commit 1f05194d083741570b0ab34390228bc2f0fb6233
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 16:19:26 2015 +0200

    cbfstool: actually use no-ms-bitfields flag on mingw
    
    It was added to an unused variable.
    
    Change-Id: I869ffdda7e04b5c615931473c760d66b803fb98b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 99df7d7..2a3dedf 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -53,7 +53,7 @@ TOOLCPPFLAGS += -I$(objutil)/cbfstool
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
-TOOLFLAGS+=-mno-ms-bitfields
+TOOLCFLAGS += -mno-ms-bitfields
 endif
 
 $(objutil)/cbfstool/%.o: $(objutil)/cbfstool/%.c


From gerrit at coreboot.org  Wed Sep 16 14:37:36 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 16 Sep 2015 14:37:36 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	deduplicate Makefiles
References: <I26bb8c884e98afe74fd9df11464bcf88e130cd92+0@gerrit.coreboot.org>
Message-ID: <I26bb8c884e98afe74fd9df11464bcf88e130cd92+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11674

-gerrit

commit 43317d9d7a8fddeb5c016aeff3ace5c0ce5fd4e8
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 16:34:15 2015 +0200

    cbfstool: deduplicate Makefiles
    
    There's no need to maintain two lists of dependencies that need to be
    changed every. single. time.
    
    Change-Id: I26bb8c884e98afe74fd9df11464bcf88e130cd92
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/Makefile | 111 ++++++-------------------------------------------
 1 file changed, 12 insertions(+), 99 deletions(-)

diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index b6fb38c..e6d082c 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -1,107 +1,20 @@
-obj ?= .
+top ?= $(abspath ../..)
+objutil ?= $(top)/util
+obj ?= $(objutil)/cbfsutil
 
-HOSTCC ?= $(CC)
-
-CFLAGS += -g3
-CFLAGS += -std=c99 -Werror -Wall -Wextra
-CFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
-CFLAGS += -Wstrict-prototypes -Wwrite-strings
-CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
-CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
-CPPFLAGS += -Iflashmap
-LDFLAGS += -g3
-
-CBFSTOOL_BINARY:=$(obj)/cbfstool
-CBFSTOOL_COMMON:=common.o cbfs_image.o compress.o fit.o
-CBFSTOOL_COMMON+=elfheaders.o cbfs-mkstage.o cbfs-mkpayload.o xdr.o
-CBFSTOOL_COMMON+=partitioned_file.o linux_trampoline.o cbfs-payload-linux.o
-CBFSTOOL_COMMON+=rmodule.o
-# LZMA
-CBFSTOOL_COMMON+=lzma/lzma.o
-CBFSTOOL_COMMON+=lzma/C/LzFind.o  lzma/C/LzmaDec.o  lzma/C/LzmaEnc.o
-# FMAP
-CBFSTOOL_COMMON+=flashmap/fmap.o
-CBFSTOOL_COMMON+=flashmap/kv_pair.o flashmap/valstr.o
-
-CBFSTOOL_COMMON:=$(addprefix $(obj)/,$(CBFSTOOL_COMMON))
-
-FMAPTOOL_BINARY:=$(obj)/fmaptool
-FMAPTOOL_COMMON:=cbfs_sections.o fmap_from_fmd.o
-FMAPTOOL_COMMON+=fmd.o fmd_parser.o fmd_scanner.o
-# FMAP
-FMAPTOOL_COMMON+=flashmap/fmap.o
-FMAPTOOL_COMMON+=flashmap/kv_pair.o flashmap/valstr.o
-
-FMAPTOOL_COMMON:=$(addprefix $(obj)/,$(FMAPTOOL_COMMON))
-
-RMODTOOL_BINARY:=$(obj)/rmodtool
-RMODTOOL_COMMON:=rmodule.o common.o elfheaders.o xdr.o
-
-RMODTOOL_COMMON:=$(addprefix $(obj)/,$(RMODTOOL_COMMON))
-
-FMAPTESTS_BINARY:=$(obj)/flashmap_tests
-FMAPTESTS_COMMON:=flashmap/fmap.o flashmap/valstr.o flashmap/kv_pair.o
-
-FMAPTESTS_COMMON:=$(addprefix $(obj)/,$(FMAPTESTS_COMMON))
+CONFIG_FMD_GENPARSER := y
 
-GENERATED:=fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h
+HOSTCC ?= $(CC)
 
 .PHONY: all
-all: .dependencies $(CBFSTOOL_BINARY) $(FMAPTOOL_BINARY) $(RMODTOOL_BINARY)
-
-$(obj)/%: $(obj)/%.o
-	mkdir -p $(dir $@)
-	$(HOSTCC) $(LDFLAGS) -o $@ $^ $(LDLIBS)
-$(obj)/%.o: %.c
-	mkdir -p $(dir $@)
-	$(HOSTCC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<
-
-fmd_scanner.h: fmd_scanner.c
-fmd_scanner.c: fmd_scanner.l
-	$(LEX) $(LFLAGS) -t --header-file=$*.h $< >$*.c
-
-fmd_parser.h: fmd_parser.c
-fmd_parser.c: fmd_parser.y
-	$(YACC) $(YFLAGS) -d $<
-	mv -f y.tab.c $*.c
-	mv -f y.tab.h $*.h
+all: $(objutil)/cbfstool/cbfstool \
+	$(objutil)/cbfstool/fmaptool \
+	$(objutil)/cbfstool/rmodtool \
 
 .PHONY: clean
 clean:
-	$(RM) $(CBFSTOOL_COMMON) $(CBFSTOOL_BINARY).o $(CBFSTOOL_BINARY)
-	$(RM) $(FMAPTOOL_COMMON) $(FMAPTOOL_BINARY).o $(FMAPTOOL_BINARY)
-	$(RM) $(RMODTOOL_COMMON) $(RMODTOOL_BINARY).o $(RMODTOOL_BINARY)
-	$(RM) $(FMAPTESTS_COMMON) $(FMAPTESTS_BINARY).o $(FMAPTESTS_BINARY)
-.PHONY: distclean
-distclean: clean
-	$(RM) .dependencies
-.PHONY: maintainer-clean
-maintainer-clean: distclean
-	$(RM) $(GENERATED)
-
-tags: $(GENERATED)
-	ctags *.[ch]
-
-.dependencies: $(GENERATED)
-	@$(HOSTCC) $(CPPFLAGS) $(CFLAGS) -MM -MG *.c > $@
-	@$(HOSTCC) $(CPPFLAGS) $(CFLAGS) -MM flashmap/*.c >> $@
-	@$(HOSTCC) $(CPPFLAGS) $(CFLAGS) -MM lzma/*.c >> $@
-	@$(HOSTCC) $(CPPFLAGS) $(CFLAGS) -MM lzma/C/*.c >> $@
-	@sed -i 's|.*:.*|$$(obj)/&|' $@
-
-$(CBFSTOOL_BINARY): $(CBFSTOOL_COMMON)
-$(FMAPTOOL_BINARY): $(FMAPTOOL_COMMON)
-$(RMODTOOL_BINARY): $(RMODTOOL_COMMON)
-
-# This target must be built manually
-$(FMAPTESTS_BINARY): $(FMAPTESTS_COMMON)
-
-# Yacc source is superset of header
-$(obj)/fmd_parser.o: CFLAGS += -Wno-redundant-decls
-# Lex generates unneeded functions and declarations
-$(obj)/fmd_scanner.o: CFLAGS += -Wno-redundant-decls
-$(obj)/fmd_scanner.o: CFLAGS += -Wno-unused-function
-# Tolerate lzma sdk warnings
-$(obj)/lzma/C/LzmaEnc.o: CFLAGS += -Wno-sign-compare -Wno-cast-qual
+	$(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj)
+	$(RM) $(objutil)/cbfstool/fmaptool $(fmapobj)
+	$(RM) $(objutil)/cbfstool/rmodtool $(rmodobj)
 
--include .dependencies
+include Makefile.inc


From gerrit at coreboot.org  Wed Sep 16 14:55:47 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:55:47 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Disable Deep S3 on kunimitsu platform
References: <Iad87b7a8f7bf560861a270a8c19153cfc3850bc4+0@gerrit.coreboot.org>
Message-ID: <E1ZcE7f-0005Dr-Sa@mail.coreboot.org>

the following patch was just integrated into master:
commit 179623a691aab2ccf923c86a0ddc245eed05b2c7
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Tue Sep 8 20:46:49 2015 +0530

    kunimitsu: Disable Deep S3 on kunimitsu platform
    
    This patch will reset Deep S3 flag, hence S3 will work.
    
    BUG=chrome-os-partner:40635
    BRANCH=None
    TEST=Build and Boot Kunimitsu and verify S3 is working.
    
    Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5
    Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297903
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11643
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11643 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:56:00 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:56:00 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Enable
	ALS connected to EC
References: <I4a4913a1b407720d85f6e630b674e550bf5e36df+0@gerrit.coreboot.org>
Message-ID: <E1ZcE7t-0005FQ-0F@mail.coreboot.org>

the following patch was just integrated into master:
commit 6e6d0425308c2c98e7d63ab3c0260644b916d386
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Sep 9 10:06:09 2015 -0700

    glados: Enable ALS connected to EC
    
    Glados has an ambient light sensor connected to the EC which
    is presented to the OS as a standard ACPI0008 device.
    
    BUG=chrome-os-partner:43493
    BRANCH=none
    TEST=test ALS functionality on glados P2 board
    
    Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054
    Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298251
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11644
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11644 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 14:56:13 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 14:56:13 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Enable ALS connected to EC
References: <I7998c19e5514eda781cc20888cdb0732f81389ae+0@gerrit.coreboot.org>
Message-ID: <E1ZcE85-0005HG-Me@mail.coreboot.org>

the following patch was just integrated into master:
commit ebf623b53caea9fb1781668143fb3dc9fff08f6a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Sep 9 10:09:26 2015 -0700

    kunimitsu: Enable ALS connected to EC
    
    Kunimitsu has an ambient light sensor connected to the EC which
    is presented to the OS as a standard ACPI0008 device.
    
    BUG=chrome-os-partner:43493
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I7998c19e5514eda781cc20888cdb0732f81389ae
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a67e5ddfccea0776841fabe04be55c1854bf31f2
    Original-Change-Id: I381dc9c5777370df2ea4c41c9e153b3277082718
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298252
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11645
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11645 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 16:41:19 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 16 Sep 2015 16:41:19 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos:
	vboot-related functions move to common vboot code
References: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+0@gerrit.coreboot.org>
Message-ID: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+2@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11497

-gerrit

commit bb404a4f3dba20455a05ad38ad9526c07b44d9f4
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:41:14 2015 +0200

    chromeos: vboot-related functions move to common vboot code
    
    This moves a few vboot-prefixed functions that were defined in chromeos.c to
    vboot_common.c, since those are only relevant to vboot and depend on the vboot
    handoff data. This allows more separation between CONFIG_CHROMEOS and what
    CONFIG_CHROMEOS selects, so that each separate option (such as
    CONFIG_VBOOT_VERIFY_FIRMWARE) can be enabled separately.
    
    Thus, the actual definitions of these functions will only be declared when
    CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling
    vboot_skip_display_init in bootmode was also adapted.
    
    Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/lib/bootmode.c                            |  2 +-
 src/vendorcode/google/chromeos/chromeos.c     | 32 ---------------------------
 src/vendorcode/google/chromeos/chromeos.h     | 10 ++++-----
 src/vendorcode/google/chromeos/vboot_common.c | 27 ++++++++++++++++++++++
 4 files changed, 33 insertions(+), 38 deletions(-)

diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index f2ff72a..d0aa40e 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -80,7 +80,7 @@ void gfx_set_init_done(int done)
 int display_init_required(void)
 {
 	/* For Chrome OS always honor vboot_skip_display_init(). */
-	if (IS_ENABLED(CONFIG_CHROMEOS))
+	if (IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE))
 		return !vboot_skip_display_init();
 
 	/* By default always initialize display. */
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index c2190b7..4864b8c 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -20,38 +20,6 @@
 #include <stddef.h>
 #include <string.h>
 #include "chromeos.h"
-#include <boot/coreboot_tables.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include "vboot_handoff.h"
-
-static int vboot_handoff_flag(uint32_t flag)
-{
-	struct vboot_handoff *vbho;
-
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
-
-	if (vbho == NULL)
-		return 0;
-
-	return !!(vbho->init_params.out_flags & flag);
-}
-
-int vboot_skip_display_init(void)
-{
-	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
-}
-
-int vboot_enable_developer(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
-}
-
-int vboot_enable_recovery(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
-}
 
 int __attribute__((weak)) clear_recovery_mode_switch(void)
 {
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index 798ab3e..15513eb 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -45,15 +45,10 @@ void elog_add_boot_reason(void);
 /* functions implemented in watchdog.c */
 void elog_add_watchdog_reset(void);
 void reboot_from_watchdog(void);
-
-int vboot_enable_developer(void);
-int vboot_enable_recovery(void);
-int vboot_skip_display_init(void);
 #else
 static inline void elog_add_boot_reason(void) { return; }
 static inline void elog_add_watchdog_reset(void) { return; }
 static inline void reboot_from_watchdog(void) { return; }
-static inline int vboot_skip_display_init(void) { return 0; }
 #endif /* CONFIG_CHROMEOS */
 
 struct romstage_handoff;
@@ -61,11 +56,16 @@ struct romstage_handoff;
 #if CONFIG_VBOOT_VERIFY_FIRMWARE
 /* Returns 0 on success < 0 on error. */
 int vboot_get_handoff_info(void **addr, uint32_t *size);
+
+int vboot_enable_developer(void);
+int vboot_enable_recovery(void);
+int vboot_skip_display_init(void);
 #else /* CONFIG_VBOOT_VERIFY_FIRMWARE */
 static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
 {
 	return -1;
 }
+static inline int vboot_skip_display_init(void) { return 0; }
 #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
 
 #include "gnvs.h"
diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 2fd29b6..1c216d0 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -55,6 +55,33 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 	return 0;
 }
 
+static int vboot_handoff_flag(uint32_t flag)
+{
+	struct vboot_handoff *vbho;
+
+	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
+
+	if (vbho == NULL)
+		return 0;
+
+	return !!(vbho->init_params.out_flags & flag);
+}
+
+int vboot_skip_display_init(void)
+{
+	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
+}
+
+int vboot_enable_developer(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
+}
+
+int vboot_enable_recovery(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
+}
+
 void vboot_reboot(void)
 {
 	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))


From gerrit at coreboot.org  Wed Sep 16 16:41:21 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 16 Sep 2015 16:41:21 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos: vboot
	and chromeos dependency removal for sw write protect state
References: <I47ce31530a03f6749e0f370e5d868466318b3bb6+0@gerrit.coreboot.org>
Message-ID: <I47ce31530a03f6749e0f370e5d868466318b3bb6+3@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11496

-gerrit

commit 0a8253ccec0555d7be1ce2954c6909d66ee7644d
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:27:27 2015 +0200

    chromeos: vboot and chromeos dependency removal for sw write protect state
    
    This removes the dependency on chromeos and vboot for the sw write protect state
    function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to
    both reflect this change and become consistent with the definition of
    get_write_protect_state that is already in use.
    
    Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/include/bootmode.h                                | 1 +
 src/soc/intel/baytrail/romstage/romstage.c            | 4 +---
 src/soc/intel/broadwell/romstage/romstage.c           | 4 +---
 src/soc/intel/skylake/romstage/romstage.c             | 4 +---
 src/vendorcode/google/chromeos/chromeos.c             | 2 +-
 src/vendorcode/google/chromeos/chromeos.h             | 2 --
 src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 2 +-
 7 files changed, 6 insertions(+), 13 deletions(-)

diff --git a/src/include/bootmode.h b/src/include/bootmode.h
index 96c789b..730c0f3 100644
--- a/src/include/bootmode.h
+++ b/src/include/bootmode.h
@@ -23,6 +23,7 @@
 /* functions implemented per mainboard: */
 void init_bootmode_straps(void);
 int get_write_protect_state(void);
+int get_sw_write_protect_state(void);
 int get_developer_mode_switch(void);
 int get_recovery_mode_switch(void);
 int clear_recovery_mode_switch(void);
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 1b93eb6..7bd2663 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -362,11 +362,9 @@ void ramstage_cache_invalid(void)
 #endif
 }
 
-#if CONFIG_CHROMEOS
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 	/* Return unprotected status if status read fails. */
 	return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
 }
-#endif
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 27fb0f2..884c274 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -147,13 +147,11 @@ void ramstage_cache_invalid(void)
 #endif
 }
 
-#if CONFIG_CHROMEOS
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 	/* Return unprotected status if status read fails. */
 	return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
 }
 
-#endif
 void __attribute__((weak)) mainboard_pre_console_init(void) {}
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 6c5d64a..6804459 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -68,15 +68,13 @@ void soc_romstage_init(struct romstage_params *params)
 	pch_early_init();
 }
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 
 	/* Return unprotected status if status read fails. */
 	return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80);
 }
-#endif
 
 /* UPD parameters to be initialized before MemoryInit */
 void soc_memory_init_params(struct romstage_params *params,
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index 0737267..c2190b7 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -65,7 +65,7 @@ void __attribute__((weak)) save_chromeos_gpios(void)
 	// Can be implemented by a mainboard
 }
 
-int __attribute__((weak)) vboot_get_sw_write_protect(void)
+int __attribute__((weak)) get_sw_write_protect_state(void)
 {
 	// Can be implemented by a platform / mainboard
 	return 0;
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index c7048dd..798ab3e 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -68,8 +68,6 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
 }
 #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
 
-int vboot_get_sw_write_protect(void);
-
 #include "gnvs.h"
 struct device;
 
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index c8ba114..8e12fdc 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -61,7 +61,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff,
 
 	if (get_write_protect_state())
 		vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED;
-	if (vboot_get_sw_write_protect())
+	if (get_sw_write_protect_state())
 		vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED;
 
 	if (vb2_sd->recovery_reason) {


From gerrit at coreboot.org  Wed Sep 16 16:41:25 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 16 Sep 2015 16:41:25 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos:
	vboot_common: Avoid code duplication when grabbing the handoff info
References: <I28f1decce98f988f90c446a3a0dbe7409d714527+0@gerrit.coreboot.org>
Message-ID: <I28f1decce98f988f90c446a3a0dbe7409d714527+2@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11498

-gerrit

commit ddbc045690b1ec2a7fade5df0d6e435b32daf236
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:44:56 2015 +0200

    chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
    
    vboot_handoff_flag was duplicating the logic to grab the handoff info, that is
    already made available with vboot_get_handoff_info.
    This uses vboot_get_handoff_info in vboot_handoff_flag instead.
    
    Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/vendorcode/google/chromeos/vboot_common.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 1c216d0..9ef2e0b 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -57,11 +57,13 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 
 static int vboot_handoff_flag(uint32_t flag)
 {
-	struct vboot_handoff *vbho;
+	struct vboot_handoff *vbho = NULL;
+	uint32_t size = 0;
+	int ret;
 
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
+	ret = vboot_get_handoff_info((void **)&vbho, &size);
 
-	if (vbho == NULL)
+	if (ret)
 		return 0;
 
 	return !!(vbho->init_params.out_flags & flag);


From gerrit at coreboot.org  Wed Sep 16 16:41:26 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 16 Sep 2015 16:41:26 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: google: veyron:
	CBFS_SIZE to match the available size for Coreboot in ChromeOS
References: <I168386a5011222866654a496d8d054faff7a9406+0@gerrit.coreboot.org>
Message-ID: <I168386a5011222866654a496d8d054faff7a9406+3@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11117

-gerrit

commit 4b8fc1fd706413a6264f039265d5589aaf66207d
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Wed Sep 16 18:23:23 2015 +0200

    google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOS
    
    When building for ChromeOS, it is expected that Coreboot will only occupy the
    first MiB of the SPI flash, according to the veyron fmap description.
    Otherwise, it makes sense to use the full ROM size.
    
    Change-Id: I168386a5011222866654a496d8d054faff7a9406
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/mainboard/google/veyron/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
index c474bd6..38a9ef6 100644
--- a/src/mainboard/google/veyron/Kconfig
+++ b/src/mainboard/google/veyron/Kconfig
@@ -85,4 +85,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON


From gerrit at coreboot.org  Wed Sep 16 17:17:14 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 17:17:14 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	riscv-memlayout: fix existing memlayout issues, add sbi interface
References: <Id97fe75e45ac1361005bec6d421756ee3f98a508+0@gerrit.coreboot.org>
Message-ID: <E1ZcGKY-0007N2-2e@mail.coreboot.org>

the following patch was just integrated into master:
commit a47738d10f9c6e4d14ffbd35a01c6e70c2c494e5
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Wed Aug 26 15:39:16 2015 -0700

    riscv-memlayout: fix existing memlayout issues, add sbi interface
    
    Existing memlayout code placed sections in overlapping areas, and would
    overwrite the payload if it was large enough. Update memlayout.ld in
    src/mainboard/emulation/spike-riscv to represent the spike emulator, and
    add sbi interface which now has room into src/arch/riscv/bootblock.S.
    Add utility code to qemu-riscv, but emulator itself has yet to be
    updated to new ISA and as such should not be used.
    Update Makefile to include all the files necessary for sbi interface.
    
    Clean up unused include in src/arch/riscv/include/atomic.h and
    whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld
    Fixed whitespace issues in spike_util.c
    
    Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
    Reviewed-on: http://review.coreboot.org/11370
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See http://review.coreboot.org/11370 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 17:17:36 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 16 Sep 2015 17:17:36 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	riscv-virtual-memory: move page tables into virtual address space
References: <I1d99e46f38a38a163fb1c7c517b1abca80cde0dc+0@gerrit.coreboot.org>
Message-ID: <E1ZcGKu-0007Qq-2J@mail.coreboot.org>

the following patch was just integrated into master:
commit 08c10a9cbceb21de260f277751d164d1c285f1c0
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Thu Sep 10 10:58:58 2015 -0700

    riscv-virtual-memory: move page tables into virtual address space
    
    If we use a linux payload/any payload that wants to manage virtual
    memory, and the payload is a supervisor (thus requiring virtual
    addressing before being started), we need to make sure that the page
    table is mapped into the virtual address space. Move the start address
    of the tables so the payload can manage virtual memory.
    
    Change-Id: I1d99e46f38a38a163fb1c7c517b1abca80cde0dc
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
    Reviewed-on: http://review.coreboot.org/11621
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11621 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 16 22:05:48 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 16 Sep 2015 22:05:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload: allow
	compression at file header level
References: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+0@gerrit.coreboot.org>
Message-ID: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+3@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10938

-gerrit

commit b35818a4082e32b93e77d5112b82e42b96129924
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: allow compression at file header level
    
    Sample call sequence for loading a compressed file is as follows:
    
    [pg: the following example isn't correct right now, but
     cbfs_get_file_content's interface will change once again before this
     gets merged.]
    	const char *name = "foo.bmp";
    	struct cbfs_file *file = cbfs_get_file(media, name);
    	struct cbfs_file_attributes *attr = CBFS_FILE_ATTRIBUTES(file);
    	if (attr) {
    		void *dst = malloc(ntohl(attr->uncompressed_size));
    		dst = cbfs_get_file_content(media, name, type, NULL, file, dst);
    	}
    
    cbfs_stage and cbfs_payload_segment continue to support compression at
    subheader level because stages and payloads have to be decompressed to the load
    address, which is stored in the subheader. For these, file level compression
    should be turned off.
    
    Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/cbfs_core.h | 26 +++++++++++--
 payloads/libpayload/libcbfs/cbfs.c      | 14 ++++---
 payloads/libpayload/libcbfs/cbfs_core.c | 65 +++++++++++++++++++++++----------
 3 files changed, 77 insertions(+), 28 deletions(-)

diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index a2ee744..66307c1 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -141,6 +141,7 @@ struct cbfs_file {
  * 0xff. Support both. */
 #define CBFS_FILE_ATTR_TAG_UNUSED 0
 #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
 
 /* The common fields of extended cbfs file attributes.
    Attributes are expected to start with tag/len, then append their
@@ -152,6 +153,14 @@ struct cbfs_file_attribute {
 	uint8_t data[0];
 } __attribute__((packed));
 
+struct cbfs_file_attr_compression {
+	uint32_t tag;
+	uint32_t len;
+	/* whole file compression format. 0 if no compression. */
+	uint32_t compression;
+	uint32_t decompressed_size;
+} __attribute__((packed));
+
 /* Given a cbfs_file, return the first file attribute, or NULL. */
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
 
@@ -237,12 +246,23 @@ struct cbfs_media {
 	int (*close)(struct cbfs_media *media);
 };
 
-/* returns pointer to a file entry inside CBFS or NULL */
+/* returns pointer to a file entry inside CBFS or NULL on error */
 struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name);
 
-/* returns pointer to file content inside CBFS after if type is correct */
+/*
+ * returns pointer to file content inside CBFS after if type is correct
+ * or NULL on error.
+ *
+ * if the file is compressed, it's decompressed and copied to dst allocated by
+ * the caller.
+ *
+ * it can be invoked using previously mapped file content pointed by *file.
+ * if *file is not NULL, loading file will be skipped, assuming the file has
+ * not been unmapped.
+ */
 void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
-			    int type, size_t *sz);
+			    int type, size_t *sz,
+			    struct cbfs_file *file, void *dst);
 
 /* returns decompressed size on success, 0 on failure */
 int cbfs_decompress(int algo, void *src, void *dst, int len);
diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
index 3e614b6..c619075 100644
--- a/payloads/libpayload/libcbfs/cbfs.c
+++ b/payloads/libpayload/libcbfs/cbfs.c
@@ -89,7 +89,8 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
 	tohex16(device, name+8);
 
 	orom = (struct cbfs_optionrom *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
+		cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM,
+			NULL, NULL, NULL);
 
 	if (orom == NULL)
 		return NULL;
@@ -119,7 +120,8 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
 void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 {
 	struct cbfs_stage *stage = (struct cbfs_stage *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL);
+		cbfs_get_file_content(media, name, CBFS_TYPE_STAGE,
+			NULL, NULL, NULL);
 	/* this is a mess. There is no ntohll. */
 	/* for now, assume compatible byte order until we solve this. */
 	uintptr_t entry;
@@ -155,7 +157,8 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 int cbfs_execute_stage(struct cbfs_media *media, const char *name)
 {
 	struct cbfs_stage *stage = (struct cbfs_stage *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL);
+		cbfs_get_file_content(media, name, CBFS_TYPE_STAGE,
+			NULL, NULL, NULL);
 
 	if (stage == NULL)
 		return 1;
@@ -173,7 +176,7 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name)
 void *cbfs_load_payload(struct cbfs_media *media, const char *name)
 {
 	return (struct cbfs_payload *)cbfs_get_file_content(
-		media, name, CBFS_TYPE_PAYLOAD, NULL);
+		media, name, CBFS_TYPE_PAYLOAD, NULL, NULL, NULL);
 }
 
 struct cbfs_file *cbfs_find(const char *name) {
@@ -181,7 +184,8 @@ struct cbfs_file *cbfs_find(const char *name) {
 }
 
 void *cbfs_find_file(const char *name, int type) {
-	return cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type, NULL);
+	return cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type,
+		NULL, NULL, NULL);
 }
 
 const struct cbfs_header *get_cbfs_header(void) {
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 6a19b26..90aa9ad 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -97,8 +97,8 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
 /* public API starts here*/
 struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
 {
-	const char *file_name;
-	uint32_t offset, romsize, name_len;
+	const char *vardata;
+	uint32_t offset, romsize, vardata_len;
 	const struct cbfs_header *header;
 	struct cbfs_file file, *file_ptr;
 	struct cbfs_media default_media;
@@ -153,29 +153,29 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
 			offset += new_align;
 			continue;
 		}
-		name_len = ntohl(file.offset) - sizeof(file);
-		DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset,
-		      name_len);
+		vardata_len = ntohl(file.offset) - sizeof(file);
+		DEBUG(" - load entry 0x%x variable data (%d bytes)...\n",
+			offset, vardata_len);
 
 		// load file name (arbitrary length).
-		file_name = (const char*)media->map(
-				media, offset + sizeof(file), name_len);
-		if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) {
+		vardata = (const char*)media->map(
+				media, offset + sizeof(file), vardata_len);
+		if (vardata == CBFS_MEDIA_INVALID_MAP_ADDRESS) {
 			ERROR("ERROR: Failed to get filename: 0x%x.\n", offset);
-		} else if (strcmp(file_name, name) == 0) {
+		} else if (strcmp(vardata, name) == 0) {
 			int file_offset = ntohl(file.offset),
 			    file_len = ntohl(file.len);
 			DEBUG("Found file (offset=0x%x, len=%d).\n",
 			    offset + file_offset, file_len);
-			media->unmap(media, file_name);
+			media->unmap(media, vardata);
 			file_ptr = media->map(media, offset,
 					      file_offset + file_len);
 			media->close(media);
 			return file_ptr;
 		} else {
 			DEBUG(" (unmatched file @0x%x: %s)\n", offset,
-			      file_name);
-			media->unmap(media, file_name);
+			      vardata);
+			media->unmap(media, vardata);
 		}
 
 		// Move to next file.
@@ -189,18 +189,20 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
 }
 
 void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
-			    int type, size_t *sz)
+			    int type, size_t *sz, struct cbfs_file *file,
+			    void *dst)
 {
-	struct cbfs_file *file = cbfs_get_file(media, name);
+	if (file == NULL) {
+		file = cbfs_get_file(media, name);
+		if (file == NULL) {
+			ERROR("Could not find file '%s'.\n", name);
+			return NULL;
+		}
+	}
 
 	if (sz)
 		*sz = 0;
 
-	if (file == NULL) {
-		ERROR("Could not find file '%s'.\n", name);
-		return NULL;
-	}
-
 	if (ntohl(file->type) != type) {
 		ERROR("File '%s' is of type %x, but we requested %x.\n", name,
 		      ntohl(file->type), type);
@@ -210,7 +212,30 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 	if (sz)
 		*sz = ntohl(file->len);
 
-	return (void *)CBFS_SUBHEADER(file);
+	void *file_content = (void *)CBFS_SUBHEADER(file);
+
+	struct cbfs_file_attribute *attr = cbfs_file_first_attr(file);
+	while (attr) {
+		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION)
+			break;
+		attr = cbfs_file_next_attr(file, attr);
+	}
+	if (attr) {
+		struct cbfs_file_attr_compression *comp =
+			(struct cbfs_file_attr_compression *)attr;
+		uint32_t alg = ntohl(comp->compression);
+		DEBUG("File '%s' is compressed (alg=%d)\n", alg);
+		if (!dst) {
+			ERROR("Memory for decompressed data not provided\n");
+			return NULL;
+		}
+		if (cbfs_decompress(alg, file_content, dst,
+				    ntohl(comp->decompressed_size)))
+			return NULL;
+		file_content = dst;
+	}
+
+	return file_content;
 }
 
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file)


From gerrit at coreboot.org  Wed Sep 16 22:05:50 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 16 Sep 2015 22:05:50 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: libpayload:
	bring in file attribute support from cbfstool
References: <I86baefe5c299125a4733fa20523efd5d06de7182+0@gerrit.coreboot.org>
Message-ID: <I86baefe5c299125a4733fa20523efd5d06de7182+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11675

-gerrit

commit ed67e363df66b76ad1e52a312a7cf0b0d95b9082
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 18:53:40 2015 +0200

    libpayload: bring in file attribute support from cbfstool
    
    This comes from cbfstool (GPL) into libpayload (BSD-l), but I could have
    just as well written it in libpayload first.
    
    Change-Id: I86baefe5c299125a4733fa20523efd5d06de7182
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/cbfs_core.h | 26 ++++++++++++++++++++-
 payloads/libpayload/libcbfs/cbfs_core.c | 41 +++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index a95cef7..a2ee744 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -132,10 +132,34 @@ struct cbfs_file {
 	char magic[8];
 	uint32_t len;
 	uint32_t type;
-	uint32_t checksum;
+	uint32_t attributes_offset;
 	uint32_t offset;
+	char filename[];
 } __attribute__((packed));
 
+/* Depending on how the header was initialized, it may be backed with 0x00 or
+ * 0xff. Support both. */
+#define CBFS_FILE_ATTR_TAG_UNUSED 0
+#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+
+/* The common fields of extended cbfs file attributes.
+   Attributes are expected to start with tag/len, then append their
+   specific fields. */
+struct cbfs_file_attribute {
+	uint32_t tag;
+	/* len covers the whole structure, incl. tag and len */
+	uint32_t len;
+	uint8_t data[0];
+} __attribute__((packed));
+
+/* Given a cbfs_file, return the first file attribute, or NULL. */
+struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
+
+/* Given a cbfs_file and a cbfs_file_attribute, return the attribute that
+ * follows it, or NULL. */
+struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file,
+	struct cbfs_file_attribute *attr);
+
 /*** Component sub-headers ***/
 
 /* Following are component sub-headers for the "standard"
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 7926d9d..6a19b26 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -213,6 +213,47 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 	return (void *)CBFS_SUBHEADER(file);
 }
 
+struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file)
+{
+	/* attributes_offset should be 0 when there is no attribute, but all
+	 * values that point into the cbfs_file header are invalid, too. */
+	if (ntohl(file->attributes_offset) <= sizeof(*file))
+		return NULL;
+
+	/* There needs to be enough space for the file header and one
+	 * attribute header for this to make sense. */
+	if (ntohl(file->offset) <=
+		sizeof(*file) + sizeof(struct cbfs_file_attribute))
+		return NULL;
+
+	return (struct cbfs_file_attribute *)
+		(((uint8_t *)file) + ntohl(file->attributes_offset));
+}
+
+struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file,
+	struct cbfs_file_attribute *attr)
+{
+	/* ex falso sequitur quodlibet */
+	if (attr == NULL)
+		return NULL;
+
+	/* Is there enough space for another attribute? */
+	if ((uint8_t *)attr + ntohl(attr->len) +
+		sizeof(struct cbfs_file_attribute) >=
+		(uint8_t *)file + ntohl(file->offset))
+		return NULL;
+
+	struct cbfs_file_attribute *next = (struct cbfs_file_attribute *)
+		(((uint8_t *)attr) + ntohl(attr->len));
+	/* If any, "unused" attributes must come last. */
+	if (ntohl(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED)
+		return NULL;
+	if (ntohl(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED2)
+		return NULL;
+
+	return next;
+}
+
 int cbfs_decompress(int algo, void *src, void *dst, int len)
 {
 	switch (algo) {


From gerrit at coreboot.org  Thu Sep 17 04:41:52 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 04:41:52 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: coreboot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+12@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit b68f1cebf4895d3476fb0725f2459627066d8cb7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    coreboot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                                       |   4 +-
 src/arch/x86/include/arch/cbfs.h                   |   2 +-
 src/arch/x86/romcc_console.c                       |   2 +-
 src/commonlib/Makefile.inc                         |  10 +
 src/commonlib/include/commonlib/cbfs_serialized.h  | 190 ++++++++++
 src/commonlib/include/commonlib/cbmem_id.h         | 113 ++++++
 src/commonlib/include/commonlib/coreboot_tables.h  | 387 +++++++++++++++++++++
 src/commonlib/include/commonlib/fmap_serialized.h  |  73 ++++
 src/commonlib/include/commonlib/helpers.h          |  51 +++
 src/commonlib/include/commonlib/loglevel.h         | 178 ++++++++++
 src/commonlib/include/commonlib/mem_pool.h         |  73 ++++
 src/commonlib/include/commonlib/region.h           | 157 +++++++++
 src/commonlib/include/commonlib/rmodule-defs.h     |  63 ++++
 .../include/commonlib/timestamp_serialized.h       |  92 +++++
 src/commonlib/mem_pool.c                           |  51 +++
 src/commonlib/region.c                             | 196 +++++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |   2 +-
 src/include/assets.h                               |   2 +-
 src/include/boot/coreboot_tables.h                 | 384 +-------------------
 src/include/boot_device.h                          |   2 +-
 src/include/cbfs.h                                 |   4 +-
 src/include/cbfs_serialized.h                      | 190 ----------
 src/include/cbmem.h                                |   2 +-
 src/include/cbmem_id.h                             | 113 ------
 src/include/console/console.h                      |   2 +-
 src/include/console/early_print.h                  |   2 +-
 src/include/console/loglevel.h                     | 178 ----------
 src/include/fmap.h                                 |   4 +-
 src/include/fmap_serialized.h                      |  73 ----
 src/include/mem_pool.h                             |  73 ----
 src/include/region.h                               | 157 ---------
 src/include/rmodule-defs.h                         |  63 ----
 src/include/rmodule.h                              |   2 +-
 src/include/stddef.h                               |  34 +-
 src/include/stdlib.h                               |  14 -
 src/include/timestamp.h                            |  69 +---
 src/lib/Makefile.inc                               |   9 -
 src/lib/cbfs_boot_props.c                          |   2 +-
 src/lib/fmap.c                                     |   2 +-
 src/lib/mem_pool.c                                 |  51 ---
 src/lib/region.c                                   | 196 -----------
 src/mainboard/advansus/a785e-i/romstage.c          |   2 +-
 src/mainboard/amd/bimini_fam10/romstage.c          |   2 +-
 src/mainboard/amd/dinar/romstage.c                 |   2 +-
 src/mainboard/amd/inagua/romstage.c                |   2 +-
 src/mainboard/amd/lamar/romstage.c                 |   2 +-
 src/mainboard/amd/mahogany_fam10/romstage.c        |   2 +-
 src/mainboard/amd/olivehill/romstage.c             |   2 +-
 src/mainboard/amd/olivehillplus/romstage.c         |   2 +-
 src/mainboard/amd/parmer/romstage.c                |   2 +-
 src/mainboard/amd/persimmon/romstage.c             |   2 +-
 .../amd/serengeti_cheetah_fam10/romstage.c         |   2 +-
 src/mainboard/amd/south_station/romstage.c         |   2 +-
 src/mainboard/amd/thatcher/romstage.c              |   2 +-
 src/mainboard/amd/tilapia_fam10/romstage.c         |   2 +-
 src/mainboard/amd/torpedo/romstage.c               |   2 +-
 src/mainboard/amd/union_station/romstage.c         |   2 +-
 src/mainboard/asrock/e350m1/romstage.c             |   2 +-
 src/mainboard/asrock/imb-a180/romstage.c           |   2 +-
 src/mainboard/asus/m4a78-em/romstage.c             |   2 +-
 src/mainboard/asus/m4a785-m/romstage.c             |   2 +-
 src/mainboard/asus/m5a88-v/romstage.c              |   2 +-
 src/mainboard/avalue/eax-785e/romstage.c           |   2 +-
 src/mainboard/bap/ode_e20XX/romstage.c             |   2 +-
 src/mainboard/biostar/am1ml/romstage.c             |   2 +-
 src/mainboard/gigabyte/ma785gm/romstage.c          |   2 +-
 src/mainboard/gigabyte/ma785gmt/romstage.c         |   2 +-
 src/mainboard/gigabyte/ma78gm/romstage.c           |   2 +-
 src/mainboard/gizmosphere/gizmo/romstage.c         |   2 +-
 src/mainboard/gizmosphere/gizmo2/romstage.c        |   2 +-
 src/mainboard/google/peach_pit/romstage.c          |   2 +-
 src/mainboard/hp/abm/romstage.c                    |   2 +-
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |   2 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |   2 +-
 src/mainboard/jetway/pa78vm5/romstage.c            |   2 +-
 src/mainboard/lippert/frontrunner-af/romstage.c    |   2 +-
 src/mainboard/lippert/toucan-af/romstage.c         |   2 +-
 src/mainboard/pcengines/apu1/romstage.c            |   2 +-
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |   2 +-
 src/soc/intel/broadwell/include/soc/me.h           |   2 +-
 src/southbridge/amd/cimx/sb700/Platform.h          |   2 +-
 src/southbridge/amd/cimx/sb700/early.c             |   2 +-
 src/southbridge/amd/cimx/sb900/early.c             |   2 +-
 src/vendorcode/amd/agesa/common/Porting.h          |   2 +-
 src/vendorcode/amd/pi/00630F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c    |   2 +-
 src/vendorcode/amd/pi/00730F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/Makefile.inc                 |   1 +
 src/vendorcode/google/chromeos/vboot_common.h      |   2 +-
 util/cbfstool/Makefile                             |   1 +
 util/cbfstool/Makefile.inc                         |   1 +
 util/cbfstool/rmodule.c                            |   2 +-
 util/cbmem/Makefile                                |   2 +-
 util/cbmem/cbmem.c                                 |   9 +-
 95 files changed, 1711 insertions(+), 1673 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 46d6eb2..81c149d 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
 #ifndef __INCLUDE_ARCH_CBFS__
 #define __INCLUDE_ARCH_CBFS__
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
 #include <endian.h>
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
 #include <build.h>
 #include <console/streams.h>
 #include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* Include the sources. */
 #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_PAYLOAD    0x20
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+	uint32_t compression;  /** Compression type */
+	uint64_t entry;  /** entry point */
+	uint64_t load;   /** Where to load in memory */
+	uint32_t len;          /** length of data to load */
+	uint32_t memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image.  Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing.   For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed.  This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ *   a particular motherboard is constructed? (Assuming the kernel
+ *   has drivers for all of the hardware but it does not have
+ *   assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not.  This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped.  Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+	uint64_t result;
+	result = value.hi;
+	result = (result << 32) + value.lo;
+	return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+	struct lb_uint64 result;
+	result.lo = (value >> 0) & 0xffffffff;
+	result.hi = (value >> 32) & 0xffffffff;
+	return result;
+}
+
+struct lb_header
+{
+	uint8_t  signature[4]; /* LBIO */
+	uint32_t header_bytes;
+	uint32_t header_checksum;
+	uint32_t table_bytes;
+	uint32_t table_checksum;
+	uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record.  Encoding both type and size.  The type is obviously
+ * so you can tell what it is.  The size allows you to skip that
+ * boot environment record if you don't know what it is.  This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+	uint32_t tag;		/* tag ID */
+	uint32_t size;		/* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED		0x0000
+
+#define LB_TAG_MEMORY		0x0001
+
+struct lb_memory_range {
+	struct lb_uint64 start;
+	struct lb_uint64 size;
+	uint32_t type;
+#define LB_MEM_RAM		 1	/* Memory anyone can use */
+#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
+#define LB_MEM_ACPI		 3	/* ACPI Tables */
+#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
+#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
+#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+	uint32_t tag;
+	uint32_t size;
+	struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB		0x0002
+struct lb_hwrpb {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
+#define LB_TAG_VERSION		0x0004
+#define LB_TAG_EXTRA_VERSION	0x0005
+#define LB_TAG_BUILD		0x0006
+#define LB_TAG_COMPILE_TIME	0x0007
+#define LB_TAG_COMPILE_BY	0x0008
+#define LB_TAG_COMPILE_HOST	0x0009
+#define LB_TAG_COMPILE_DOMAIN	0x000a
+#define LB_TAG_COMPILER		0x000b
+#define LB_TAG_LINKER		0x000c
+#define LB_TAG_ASSEMBLER	0x000d
+struct lb_string {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP	0x0026
+struct lb_timestamp {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL		0x000f
+struct lb_serial {
+	uint32_t tag;
+	uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
+	uint32_t baud;
+	uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE		0x0010
+struct lb_console {
+	uint32_t tag;
+	uint32_t size;
+	uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250	0
+#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI		5
+#define LB_TAG_CONSOLE_SERIAL8250MEM	6
+
+#define LB_TAG_FORWARD		0x0011
+struct lb_forward {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER	0x0012
+struct lb_framebuffer {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t physical_address;
+	uint32_t x_resolution;
+	uint32_t y_resolution;
+	uint32_t bytes_per_line;
+	uint8_t bits_per_pixel;
+	uint8_t red_mask_pos;
+	uint8_t red_mask_size;
+	uint8_t green_mask_pos;
+	uint8_t green_mask_size;
+	uint8_t blue_mask_pos;
+	uint8_t blue_mask_size;
+	uint8_t reserved_mask_pos;
+	uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT		0x0015
+#define LB_TAG_VBNV		0x0019
+#define LB_TAB_VBOOT_HANDOFF	0x0020
+#define LB_TAB_DMA		0x0022
+#define LB_TAG_RAM_OOPS		0x0023
+#define LB_TAG_MTC		0x002b
+struct lb_range {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t range_start;
+	uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+#define LB_TAG_ACPI_GNVS	0x0024
+#define LB_TAG_WIFI_CALIBRATION	0x0027
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR	0x0021
+struct lb_x86_rom_mtrr {
+	uint32_t tag;
+	uint32_t size;
+	/* The variable range MTRR index covering the ROM. */
+	uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID		0x0025
+struct lb_board_id {
+	uint32_t tag;
+	uint32_t size;
+	/* Board ID as retrieved from the board revision GPIOs. */
+	uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS	0x0026
+struct mac_address {
+	uint8_t mac_addr[6];
+	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t count;
+	struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE		0x0028
+struct lb_ram_code {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH	0x0029
+struct lb_spi_flash {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t flash_size;
+	uint32_t sector_size;
+	uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+	uint32_t tag;
+	uint32_t size;
+	/* offsets are relative to start of boot media */
+	uint64_t fmap_offset;
+	uint64_t cbfs_offset;
+	uint64_t cbfs_size;
+	uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO		0x002a
+#define MAX_SERIALNO_LENGTH	32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+	uint32_t tag;               /* CMOS definitions table type */
+	uint32_t size;               /* size of the entire table */
+	uint32_t header_length;      /* length of header */
+};
+
+/* cmos entry record
+        This record is variable length.  The name field may be
+        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+        anywhere in the byte, but can not span bytes unless it
+        starts at the beginning of the byte and the length is
+        fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+	uint32_t tag;                /* entry type */
+	uint32_t size;               /* length of this record */
+	uint32_t bit;                /* starting bit from start of image */
+	uint32_t length;             /* length of field in bits */
+	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
+	uint32_t config_id;          /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+					       variable length int aligned */
+};
+
+
+/* cmos enumerations record
+        This record is variable length.  The text field may be
+        shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+	uint32_t tag;		     /* enumeration type */
+	uint32_t size; 		     /* length of this record */
+	uint32_t config_id;          /* a number identifying the config id */
+	uint32_t value;              /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+						variable length int aligned */
+};
+
+/* cmos defaults record
+        This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+	uint32_t tag;                /* default type */
+	uint32_t size;               /* length of this record */
+	uint32_t name_length;        /* length of the following name field */
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct	cmos_checksum {
+	uint32_t tag;
+	uint32_t size;
+	/* In practice everything is byte aligned, but things are measured
+	 * in bits to be consistent.
+	 */
+	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
+	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
+	uint32_t location;	/* First bit of the checksum (byte aligned) */
+	uint32_t type;		/* Checksum algorithm that is used */
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __attribute__((packed));
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint16_t	max_entries;
+	uint16_t	tick_freq_mhz;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_VBOOT = 5,
+	TS_END_VBOOT = 6,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_START_BOOTBLOCK = 11,
+	TS_END_BOOTBLOCK = 12,
+	TS_START_COPYROM = 13,
+	TS_END_COPYROM = 14,
+	TS_START_ULZMA = 15,
+	TS_END_ULZMA = 16,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+
+	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+	TS_START_COPYVER = 501,
+	TS_END_COPYVER = 502,
+	TS_START_TPMINIT = 503,
+	TS_END_TPMINIT = 504,
+	TS_START_VERIFY_SLOT = 505,
+	TS_END_VERIFY_SLOT = 506,
+	TS_START_HASH_BODY = 507,
+	TS_DONE_LOADING = 508,
+	TS_DONE_HASHING = 509,
+	TS_END_HASH_BODY = 510,
+
+	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+	TS_FSP_MEMORY_INIT_START = 950,
+	TS_FSP_MEMORY_INIT_END = 951,
+	TS_FSP_TEMP_RAM_EXIT_START = 952,
+	TS_FSP_TEMP_RAM_EXIT_END = 953,
+	TS_FSP_SILICON_INIT_START = 954,
+	TS_FSP_SILICON_INIT_END = 955,
+	TS_FSP_BEFORE_ENUMERATE = 956,
+	TS_FSP_AFTER_ENUMERATE = 957,
+	TS_FSP_BEFORE_FINALIZE = 958,
+	TS_FSP_AFTER_FINALIZE = 959,
+
+	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 9695b3b..b3772a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
 #include <fsp/soc_binding.h>
 #include <fsp/gop.h>
 #include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
 #ifndef ASSETS_H
 #define ASSETS_H
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* An asset represents data used to boot the system. It can be found within
  * CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
 #ifndef COREBOOT_TABLES_H
 #define COREBOOT_TABLES_H
 
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image.  Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing.   For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed.  This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- *   a particular motherboard is constructed? (Assuming the kernel
- *   has drivers for all of the hardware but it does not have
- *   assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not.  This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped.  Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
-	uint32_t lo;
-	uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
-	uint64_t result;
-	result = value.hi;
-	result = (result << 32) + value.lo;
-	return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
-	struct lb_uint64 result;
-	result.lo = (value >> 0) & 0xffffffff;
-	result.hi = (value >> 32) & 0xffffffff;
-	return result;
-}
-
-struct lb_header
-{
-	uint8_t  signature[4]; /* LBIO */
-	uint32_t header_bytes;
-	uint32_t header_checksum;
-	uint32_t table_bytes;
-	uint32_t table_checksum;
-	uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record.  Encoding both type and size.  The type is obviously
- * so you can tell what it is.  The size allows you to skip that
- * boot environment record if you don't know what it is.  This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
-	uint32_t tag;		/* tag ID */
-	uint32_t size;		/* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED		0x0000
-
-#define LB_TAG_MEMORY		0x0001
-
-struct lb_memory_range {
-	struct lb_uint64 start;
-	struct lb_uint64 size;
-	uint32_t type;
-#define LB_MEM_RAM		 1	/* Memory anyone can use */
-#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
-#define LB_MEM_ACPI		 3	/* ACPI Tables */
-#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
-#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
-#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
-	uint32_t tag;
-	uint32_t size;
-	struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB		0x0002
-struct lb_hwrpb {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD	0x0003
-struct lb_mainboard {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  vendor_idx;
-	uint8_t  part_number_idx;
-	uint8_t  strings[0];
-};
-
-#define LB_TAG_VERSION		0x0004
-#define LB_TAG_EXTRA_VERSION	0x0005
-#define LB_TAG_BUILD		0x0006
-#define LB_TAG_COMPILE_TIME	0x0007
-#define LB_TAG_COMPILE_BY	0x0008
-#define LB_TAG_COMPILE_HOST	0x0009
-#define LB_TAG_COMPILE_DOMAIN	0x000a
-#define LB_TAG_COMPILER		0x000b
-#define LB_TAG_LINKER		0x000c
-#define LB_TAG_ASSEMBLER	0x000d
-struct lb_string {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP	0x0026
-struct lb_timestamp {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL		0x000f
-struct lb_serial {
-	uint32_t tag;
-	uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED     1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
-	uint32_t type;
-	uint32_t baseaddr;
-	uint32_t baud;
-	uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE		0x0010
-struct lb_console {
-	uint32_t tag;
-	uint32_t size;
-	uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250	0
-#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI		5
-#define LB_TAG_CONSOLE_SERIAL8250MEM	6
-
-#define LB_TAG_FORWARD		0x0011
-struct lb_forward {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER	0x0012
-struct lb_framebuffer {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t physical_address;
-	uint32_t x_resolution;
-	uint32_t y_resolution;
-	uint32_t bytes_per_line;
-	uint8_t bits_per_pixel;
-	uint8_t red_mask_pos;
-	uint8_t red_mask_size;
-	uint8_t green_mask_pos;
-	uint8_t green_mask_size;
-	uint8_t blue_mask_pos;
-	uint8_t blue_mask_size;
-	uint8_t reserved_mask_pos;
-	uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO	0x0013
-
-struct lb_gpio {
-	uint32_t port;
-	uint32_t polarity;
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-	uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
-        uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
-	uint32_t tag;
-	uint32_t size;
-
-	uint32_t count;
-	struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT		0x0015
-#define LB_TAG_VBNV		0x0019
-#define LB_TAB_VBOOT_HANDOFF	0x0020
-#define LB_TAB_DMA		0x0022
-#define LB_TAG_RAM_OOPS		0x0023
-#define LB_TAG_MTC		0x002b
-struct lb_range {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t range_start;
-	uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS	0x0016
-#define LB_TAG_CBMEM_CONSOLE	0x0017
-#define LB_TAG_MRC_CACHE	0x0018
-#define LB_TAG_ACPI_GNVS	0x0024
-#define LB_TAG_WIFI_CALIBRATION	0x0027
-struct lb_cbmem_ref {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR	0x0021
-struct lb_x86_rom_mtrr {
-	uint32_t tag;
-	uint32_t size;
-	/* The variable range MTRR index covering the ROM. */
-	uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID		0x0025
-struct lb_board_id {
-	uint32_t tag;
-	uint32_t size;
-	/* Board ID as retrieved from the board revision GPIOs. */
-	uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS	0x0026
-struct mac_address {
-	uint8_t mac_addr[6];
-	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t count;
-	struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE		0x0028
-struct lb_ram_code {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH	0x0029
-struct lb_spi_flash {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t flash_size;
-	uint32_t sector_size;
-	uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
-	uint32_t tag;
-	uint32_t size;
-	/* offsets are relative to start of boot media */
-	uint64_t fmap_offset;
-	uint64_t cbfs_offset;
-	uint64_t cbfs_size;
-	uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO		0x002a
-#define MAX_SERIALNO_LENGTH	32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
-	uint32_t tag;               /* CMOS definitions table type */
-	uint32_t size;               /* size of the entire table */
-	uint32_t header_length;      /* length of header */
-};
-
-/* cmos entry record
-        This record is variable length.  The name field may be
-        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
-        anywhere in the byte, but can not span bytes unless it
-        starts at the beginning of the byte and the length is
-        fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
-	uint32_t tag;                /* entry type */
-	uint32_t size;               /* length of this record */
-	uint32_t bit;                /* starting bit from start of image */
-	uint32_t length;             /* length of field in bits */
-	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
-	uint32_t config_id;          /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
-					       variable length int aligned */
-};
-
-
-/* cmos enumerations record
-        This record is variable length.  The text field may be
-        shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
-	uint32_t tag;		     /* enumeration type */
-	uint32_t size; 		     /* length of this record */
-	uint32_t config_id;          /* a number identifying the config id */
-	uint32_t value;              /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
-	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
-						variable length int aligned */
-};
-
-/* cmos defaults record
-        This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
-	uint32_t tag;                /* default type */
-	uint32_t size;               /* length of this record */
-	uint32_t name_length;        /* length of the following name field */
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
-	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct	cmos_checksum {
-	uint32_t tag;
-	uint32_t size;
-	/* In practice everything is byte aligned, but things are measured
-	 * in bits to be consistent.
-	 */
-	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
-	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
-	uint32_t location;	/* First bit of the checksum (byte aligned) */
-	uint32_t type;		/* Checksum algorithm that is used */
-#define CHECKSUM_NONE	0
-#define CHECKSUM_PCBIOS	1
-};
-
+#include <commonlib/coreboot_tables.h>
 /* function prototypes for building the coreboot table */
 
 unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
 #ifndef _BOOT_DEVICE_H_
 #define _BOOT_DEVICE_H_
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* Return the region_device for the read-only boot device. */
 const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
 #include <program_loading.h>
-#include <region.h>
 
 /*
  * CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
-    algorithms that coreboot knows about for stages and
-    payloads.  Of course, other CBFS users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE      0x10
-#define CBFS_TYPE_PAYLOAD    0x20
-#define CBFS_TYPE_OPTIONROM  0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW        0x50
-#define CBFS_TYPE_VSA        0x51
-#define CBFS_TYPE_MBI        0x52
-#define CBFS_TYPE_MICROCODE  0x53
-#define CBFS_TYPE_FSP        0x60
-#define CBFS_TYPE_MRC        0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD          0xab
-#define CBFS_TYPE_MRC_CACHE    0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
-	uint32_t magic;
-	uint32_t version;
-	uint32_t romsize;
-	uint32_t bootblocksize;
-	uint32_t align; /* fixed to 64 bytes */
-	uint32_t offset;
-	uint32_t architecture;
-	uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARM      0x00000010
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	uint32_t len;
-	uint32_t type;
-	uint32_t checksum;
-	uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	uint32_t compression;  /** Compression type */
-	uint64_t entry;  /** entry point */
-	uint64_t load;   /** Where to load in memory */
-	uint32_t len;          /** length of data to load */
-	uint32_t memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	uint32_t type;
-	uint32_t compression;
-	uint32_t offset;
-	uint64_t load_addr;
-	uint32_t len;
-	uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	uint32_t compression;
-	uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
 #include <rules.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <rules.h>
 #include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef __ROMCC__
 struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
 
 #include <console/console.h>
 #include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* While in romstage, console loglevel is built-time constant.
  * With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
 #ifndef _FMAP_H_
 #define _FMAP_H_
 
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
 
 /* Locate the fmap directory. Return 0 on success, < 0 on error. */
 int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *    * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE		"__FMAP__"
-#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
-#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
-#define FMAP_STRLEN		32	/* maximum length for strings, */
-					/* including null-terminator */
-
-enum fmap_flags {
-	FMAP_AREA_STATIC	= 1 << 0,
-	FMAP_AREA_COMPRESSED	= 1 << 1,
-	FMAP_AREA_RO		= 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
-	uint32_t offset;                /* offset relative to base */
-	uint32_t size;                  /* size in bytes */
-	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
-	uint16_t flags;                 /* flags for this area */
-}  __attribute__((packed));
-
-struct fmap {
-	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
-	uint8_t  ver_major;		/* major version */
-	uint8_t  ver_minor;		/* minor version */
-	uint64_t base;			/* address of the firmware binary */
-	uint32_t size;			/* size of firmware binary in bytes */
-	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
-	uint16_t nareas;		/* number of areas described by
-					   fmap_areas[] below */
-	struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
 
 enum {
 	RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <commonlib/helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
 
 #include <stddef.h>
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a)           ALIGN((x),(a))
-#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-
 #define min(a,b) MIN((a),(b))
 #define max(a,b) MAX((a),(b))
 
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
 #ifndef __TIMESTAMP_H__
 #define __TIMESTAMP_H__
 
-#include <stdint.h>
-
-struct timestamp_entry {
-	uint32_t	entry_id;
-	uint64_t	entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
-	uint64_t	base_time;
-	uint16_t	max_entries;
-	uint16_t	tick_freq_mhz;
-	uint32_t	num_entries;
-	struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
-	TS_START_ROMSTAGE = 1,
-	TS_BEFORE_INITRAM = 2,
-	TS_AFTER_INITRAM = 3,
-	TS_END_ROMSTAGE = 4,
-	TS_START_VBOOT = 5,
-	TS_END_VBOOT = 6,
-	TS_START_COPYRAM = 8,
-	TS_END_COPYRAM = 9,
-	TS_START_RAMSTAGE = 10,
-	TS_START_BOOTBLOCK = 11,
-	TS_END_BOOTBLOCK = 12,
-	TS_START_COPYROM = 13,
-	TS_END_COPYROM = 14,
-	TS_START_ULZMA = 15,
-	TS_END_ULZMA = 16,
-	TS_DEVICE_ENUMERATE = 30,
-	TS_DEVICE_CONFIGURE = 40,
-	TS_DEVICE_ENABLE = 50,
-	TS_DEVICE_INITIALIZE = 60,
-	TS_DEVICE_DONE = 70,
-	TS_CBMEM_POST = 75,
-	TS_WRITE_TABLES = 80,
-	TS_LOAD_PAYLOAD = 90,
-	TS_ACPI_WAKE_JUMP = 98,
-	TS_SELFBOOT_JUMP = 99,
-
-	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
-	TS_START_COPYVER = 501,
-	TS_END_COPYVER = 502,
-	TS_START_TPMINIT = 503,
-	TS_END_TPMINIT = 504,
-	TS_START_VERIFY_SLOT = 505,
-	TS_END_VERIFY_SLOT = 506,
-	TS_START_HASH_BODY = 507,
-	TS_DONE_LOADING = 508,
-	TS_DONE_HASHING = 509,
-	TS_END_HASH_BODY = 510,
-
-	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
-	TS_FSP_MEMORY_INIT_START = 950,
-	TS_FSP_MEMORY_INIT_END = 951,
-	TS_FSP_TEMP_RAM_EXIT_START = 952,
-	TS_FSP_TEMP_RAM_EXIT_END = 953,
-	TS_FSP_SILICON_INIT_START = 954,
-	TS_FSP_SILICON_INIT_END = 955,
-	TS_FSP_BEFORE_ENUMERATE = 956,
-	TS_FSP_AFTER_ENUMERATE = 957,
-	TS_FSP_BEFORE_FINALIZE = 958,
-	TS_FSP_AFTER_FINALIZE = 959,
-
-	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
 
 #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
 /*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* This function is marked as weak to allow a particular platform to
  * override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
 #include <stddef.h>
 #include <string.h>
 
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
 #include <spd.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <commonlib/region.h>
 #include <console/console.h>
 #include <device/i2c.h>
 #include <drivers/maxim/max77802/max77802.h>
 #include <program_loading.h>
-#include <region.h>
 #include <soc/clk.h>
 #include <soc/cpu.h>
 #include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
 #define ME_DELAY		10	/* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
 
 #include <cpu/amd/common/cbtypes.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #ifdef NULL
 #undef NULL
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
 #include "sb_cimx.h"
 #include "sb700_cfg.h"                /*sb700_cimx_config*/
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
 #include "SbPlatform.h"
 #include "sb_cimx.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
 #include "amdlib.h"
 #include "cbfs.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 // TODO Add a kconfig option to name the AGESA ROM file in CBFS
 #define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
 #include <assert.h>
 #include <config.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
 #define VBOOT_COMMON_H
 
 #include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* The FW areas consist of multiple components. At the beginning of
  * each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index b6fb38c..b4211b2 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
 CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
 CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
 CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
 LDFLAGS += -g3
 
 CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 99df7d7..039448f 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -50,6 +50,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
 
 /*
  * Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
 #include <sys/mman.h>
 #include <libgen.h>
 #include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
 
 #ifdef __OpenBSD__
 #include <sys/param.h>
@@ -42,18 +45,12 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
 
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
-#include "timestamp.h"
-
 #define CBMEM_VERSION "1.1"
 
 /* verbose output? */


From gerrit at coreboot.org  Thu Sep 17 07:31:48 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Thu, 17 Sep 2015 07:31:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Check
	free disk and warn if its size is too small
References: <Iae988300937018f166ff626b75c3a16bfa757ad9+0@gerrit.coreboot.org>
Message-ID: <Iae988300937018f166ff626b75c3a16bfa757ad9+4@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11474

-gerrit

commit b48fce3bd79facc63c849df258fa085b9e0ee8c7
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 1 22:31:08 2015 -0400

    buildgcc: Check free disk and warn if its size is too small
    
    We can only warn and can not stop building, because if the user
    saves the temp file the last time, the space might be enough.
    
    3G is an estimated size, which is required when I build i386-elf.
    
    Command "df" is installed on Linux, FreeBSD, OS X, Cygwin, with
    same output.
    
    Change-Id: Iae988300937018f166ff626b75c3a16bfa757ad9
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index c714718..e2c4e4f 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -291,6 +291,11 @@ cleanup()
 	printf "${green}ok${NC}\n"
 }
 
+freedisk() {
+	avail=$(LC_ALL=C eval df -k ./ | sed 1d | awk '{print $4}')
+	test $avail -lt 3145728 && printf "${red}WARNING: There might be not enough space.${NC}\n"
+}
+
 myhelp()
 {
 	printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n"
@@ -594,6 +599,7 @@ case "$PACKAGE" in
 		;;
 esac
 
+freedisk
 # Find all the required tools:
 
 TAR=$(searchtool tar) || exit $?


From gerrit at coreboot.org  Thu Sep 17 07:31:50 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Thu, 17 Sep 2015 07:31:50 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Fix the
	binutils-no-doc patch with 2.25
References: <Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab+0@gerrit.coreboot.org>
Message-ID: <Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab+3@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11639

-gerrit

commit f79b65941c1a6111e2e3acbd6014bfbd9d703c10
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 15 03:28:29 2015 -0400

    buildgcc: Fix the binutils-no-doc patch with 2.25
    
    The binutils-2.25 has added some new line, making the hunk
    move downward a little. The utility patch can fix the offset
    with "fuzz" message. So, recreate the patch to avoid that
    message.
    
    Change-Id: Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
index 317c2b4..5ad70da 100644
--- a/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
+++ b/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
@@ -1,8 +1,8 @@
-diff -ur binutils-2.23.2/bfd/Makefile.in binutils-2.23.2.patched/bfd/Makefile.in
---- binutils-2.23.2/bfd/Makefile.in	2012-10-22 14:33:51.000000000 +0200
-+++ binutils-2.25/bfd/Makefile.in	2012-10-24 15:33:04.442080163 +0200
-@@ -323,7 +323,7 @@
- RELEASE = y
+diff -ur binutils-2.25/bfd/Makefile.in binutils-2.25.patched/bfd/Makefile.in
+--- binutils-2.25/bfd/Makefile.in	2015-09-15 06:25:42.000000000 -0700
++++ binutils-2.25.patched/bfd/Makefile.in	2015-09-15 05:51:01.000000000 -0700
+@@ -339,7 +339,7 @@
+ ACLOCAL_AMFLAGS = -I . -I .. -I ../config
  INCDIR = $(srcdir)/../include
  CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
 -SUBDIRS = doc po


From gerrit at coreboot.org  Thu Sep 17 07:31:53 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Thu, 17 Sep 2015 07:31:53 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Show
	the progress when downloading
References: <I4559e88d541738a594dce92e23589992f234cb9b+0@gerrit.coreboot.org>
Message-ID: <I4559e88d541738a594dce92e23589992f234cb9b+4@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11520

-gerrit

commit c38c52c0afcaccae8be395eb06ad12c7feda7b7c
Author: zbao <fishbaozi at gmail.com>
Date:   Sun Sep 6 05:00:04 2015 -0400

    buildgcc: Show the progress when downloading
    
    Grep the output of wget, showing only the percentage.
    Leave the final "100%" unerased.
    Checking return code of wget is removed.
    
    Change-Id: I4559e88d541738a594dce92e23589992f234cb9b
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index e2c4e4f..2d845df 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -189,6 +189,16 @@ compute_sum() {
 	printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}"
 }
 
+download_showing_percentage() {
+	url=$1
+	printf " ..${red}  0%%"
+	wget --no-check-certificate $url 2>&1 | while read line; do
+		printf "${red}"
+		echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}'
+		printf "${NC}"
+	done
+}
+
 download() {
 	package=$1
 	archive="$(eval echo \$$package"_ARCHIVE")"
@@ -202,14 +212,13 @@ download() {
 		printf "(downloading from $archive)"
 		rm -f tarballs/$FILE
 		cd tarballs
-		wget --no-check-certificate -q $archive
-		wgetret=$?
+		download_showing_percentage $archive
 		cd ..
 		compute_sum $FILE
 	fi
 
 	if [ ! -f tarballs/$FILE ]; then
-		printf "\n${RED}Failed to download $FILE. Wget returns $wgetret. See 'man wget'.${NC}\n"
+		printf "\n${RED}Failed to download $FILE.${NC}\n"
 		exit 1
 	fi
 	printf "\n"


From gerrit at coreboot.org  Thu Sep 17 07:31:56 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Thu, 17 Sep 2015 07:31:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Add
	patch for building binutils by clang 6.0
References: <I0f014b776e86e6d0cbebd560cb17f469f31e1dfb+0@gerrit.coreboot.org>
Message-ID: <I0f014b776e86e6d0cbebd560cb17f469f31e1dfb+3@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11638

-gerrit

commit d4a9ed4c20ac237354392e4a35c49f87c350caff
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 15 03:27:13 2015 -0400

    buildgcc: Add patch for building binutils by clang 6.0
    
    Clang is the default compiler on BSD and OS X. With this
    change, we don't have to install gcc any more. Clang can
    act as host cc.
    This is a known issue on GNU mail list. Please refer
    the link below.
    https://sourceware.org/bugzilla/show_bug.cgi?id=17473
    
    Change-Id: I0f014b776e86e6d0cbebd560cb17f469f31e1dfb
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/patches/binutils-2.25_host-clang.patch | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/util/crossgcc/patches/binutils-2.25_host-clang.patch b/util/crossgcc/patches/binutils-2.25_host-clang.patch
new file mode 100644
index 0000000..b34bacd
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.25_host-clang.patch
@@ -0,0 +1,18 @@
+This is a known issue on GNU mail list. Please refer
+the link below.
+https://sourceware.org/bugzilla/show_bug.cgi?id=17473
+
+--- binutils-2.25/gold/binary.cc	2014-10-14 00:32:04.000000000 -0700
++++ binutils-2.25.patched/gold/binary.cc	2015-09-15 07:02:40.000000000 -0700
+@@ -24,10 +24,10 @@
+ 
+ #include <cerrno>
+ #include <cstring>
++#include "stringpool.h"
+ #include "safe-ctype.h"
+ 
+ #include "elfcpp.h"
+-#include "stringpool.h"
+ #include "fileread.h"
+ #include "output.h"
+ #include "binary.h"


From gerrit at coreboot.org  Thu Sep 17 07:31:58 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Thu, 17 Sep 2015 07:31:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: buildgcc: Search
	the cksum command without checking OS type
References: <Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa+0@gerrit.coreboot.org>
Message-ID: <Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11483

-gerrit

commit 25480ca920a59f0563bb162e70be40829563dd26
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Sep 1 22:28:57 2015 -0400

    buildgcc: Search the cksum command without checking OS type
    
    The checksum command might appear to be unpredictable only by
    checking the OS. Just list the candidates, sorted by possibility.
    
    Change-Id: Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/crossgcc/buildgcc | 41 ++++++++++++++++++++++-------------------
 1 file changed, 22 insertions(+), 19 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 4bd89a2..c714718 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -150,24 +150,26 @@ searchtool()
 			fi
 		fi
 	fi
-	if [ "$(echo $1 | cut -b -3)" = "sha" ]; then
-		if [ $UNAME = "FreeBSD" ]; then
-			if [ -x "$(which sha1 2>/dev/null)" ]; then
-				echo sha1
-				return
-			fi
-		fi
-		if [ $UNAME = "NetBSD" ]; then
-			if [ -x "$(which cksum 2>/dev/null)" ]; then
-				echo cksum -a $(echo $1 | sed -e 's,sum,,')
-				return
-			fi
-		fi
-		if [ $UNAME = "Darwin" ]; then
-			if [ -x "$(which openssl 2>/dev/null)" ]; then
-				echo openssl $(echo $1 | sed -e 's,sum,,')
-				return
-			fi
+	if echo $1 | grep -q "sum" ; then
+		algor=$(echo $1 | sed -e 's,sum,,')
+		if [ -x "$(which $1 2>/dev/null)" ]; then
+			#xxxsum [file]
+			echo $1
+			return
+		elif [ -x "$(which $algor 2>/dev/null)" ]; then
+			#xxx [file]
+			echo $algor
+			return
+		elif [ -x "$(which openssl 2>/dev/null)" ]; then
+			#openssl xxx [file]
+			echo openssl $algor
+			return
+		elif [ -x "$(which cksum 2>/dev/null)" ]; then
+			#cksum -a xxx [file]
+			#cksum has special options in NetBSD. Actually, NetBSD will use the second case above.
+			echo "buildgcc" | cksum -a $algor > /dev/null 2>/dev/null && \
+			echo cksum -a $algor
+			return
 		fi
 	fi
 	please_install $1
@@ -598,7 +600,8 @@ TAR=$(searchtool tar) || exit $?
 PATCH=$(searchtool patch) || exit $?
 MAKE=$(searchtool make) || exit $?
 SHA1SUM=$(searchtool sha1sum)
-SHA512SUM=$(searchtool sha512sum)
+#SHA512SUM=$(searchtool sha512sum)
+#MD5SUM=$(searchtool md5sum)
 CHECKSUM=$SHA1SUM
 
 searchtool m4 > /dev/null


From gerrit at coreboot.org  Thu Sep 17 07:40:47 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 07:40:47 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	actually use no-ms-bitfields flag on mingw
References: <I869ffdda7e04b5c615931473c760d66b803fb98b+0@gerrit.coreboot.org>
Message-ID: <E1ZcToF-000836-Jz@mail.coreboot.org>

the following patch was just integrated into master:
commit cdeb1c4f61b62cb161beb37d841757d3f764425d
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 16:19:26 2015 +0200

    cbfstool: actually use no-ms-bitfields flag on mingw
    
    It was added to an unused variable.
    
    Change-Id: I869ffdda7e04b5c615931473c760d66b803fb98b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11673
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11673 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 07:41:09 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 07:41:09 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	deduplicate Makefiles
References: <I26bb8c884e98afe74fd9df11464bcf88e130cd92+0@gerrit.coreboot.org>
Message-ID: <E1ZcTob-000861-OC@mail.coreboot.org>

the following patch was just integrated into master:
commit ae570d5cee7c8a416ad3887110f172763513e5a4
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 16:34:15 2015 +0200

    cbfstool: deduplicate Makefiles
    
    There's no need to maintain two lists of dependencies that need to be
    changed every. single. time.
    
    Change-Id: I26bb8c884e98afe74fd9df11464bcf88e130cd92
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11674
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11674 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 09:26:32 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Thu, 17 Sep 2015 09:26:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: Fix
	usb device in devicetree for Carrizo
References: <Ieeca06c68fe8c8eef6be4fab43193b898aebf013+0@gerrit.coreboot.org>
Message-ID: <Ieeca06c68fe8c8eef6be4fab43193b898aebf013+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11378

-gerrit

commit 23934efd3b6958e816cde1477a18572f4a618d86
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Aug 26 22:29:07 2015 -0400

    AMD Bettong: Fix usb device in devicetree for Carrizo
    
    Add some missing devices to device tree and header.
    Remove the obsolete devices.
    
    Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/include/device/pci_ids.h            | 1 +
 src/mainboard/amd/bettong/devicetree.cb | 4 +---
 src/southbridge/amd/pi/hudson/usb.c     | 1 +
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 5ba183b..dcb8a42 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -434,6 +434,7 @@
 #define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI  0x7901
 #define PCI_DEVICE_ID_AMD_CZ_USB_0      0x7907
 #define PCI_DEVICE_ID_AMD_CZ_USB_1      0x7908
+#define PCI_DEVICE_ID_AMD_CZ_USB3_0     0x7914
 
 #define PCI_VENDOR_ID_VLSI		0x1004
 #define PCI_DEVICE_ID_VLSI_82C592	0x0005
diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb
index 90b0324..41a5655 100644
--- a/src/mainboard/amd/bettong/devicetree.cb
+++ b/src/mainboard/amd/bettong/devicetree.cb
@@ -44,11 +44,9 @@ chip northbridge/amd/pi/00660F01/root_complex
 			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
 				device pci 9.0 on  end # HDA
 				device pci 9.2 on  end # HDA
+				device pci 10.0 on  end # USB
 				device pci 11.0 on  end # SATA
 				device pci 12.0 on  end # USB
-#				device pci 12.2 on  end # USB
-				device pci 13.0 on  end # USB
-#				device pci 13.2 on  end # USB
 				device pci 14.0 on      # SM
 					chip drivers/generic/generic #dimm 0-0-0
 						device i2c 50 on end
diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c
index f686521..ef8f675 100644
--- a/src/southbridge/amd/pi/hudson/usb.c
+++ b/src/southbridge/amd/pi/hudson/usb.c
@@ -49,6 +49,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_ATI_SB900_USB_20_5,
 	PCI_DEVICE_ID_AMD_CZ_USB_0,
 	PCI_DEVICE_ID_AMD_CZ_USB_1,
+	PCI_DEVICE_ID_AMD_CZ_USB3_0,
 	0
 };
 


From gerrit at coreboot.org  Thu Sep 17 09:28:05 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Thu, 17 Sep 2015 09:28:05 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: AMD bettong: Fix
	the interrupt routing.
References: <I893e73f2aab3227381e44406fa285613e4ba2904+0@gerrit.coreboot.org>
Message-ID: <I893e73f2aab3227381e44406fa285613e4ba2904+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11374

-gerrit

commit a60871067a1076adf823026fa5c4c7060c69a129
Author: zbao <fishbaozi at gmail.com>
Date:   Tue Aug 4 06:34:50 2015 -0400

    AMD bettong: Fix the interrupt routing.
    
    The unchanged code worked because the OS uses MSI
    instead of APIC.
    
    Change-Id: I893e73f2aab3227381e44406fa285613e4ba2904
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/mainboard/amd/bettong/acpi/routing.asl         | 90 ++++++++++++++++------
 .../amd/pi/00660F01/acpi/northbridge.asl           | 35 +++++++++
 2 files changed, 100 insertions(+), 25 deletions(-)

diff --git a/src/mainboard/amd/bettong/acpi/routing.asl b/src/mainboard/amd/bettong/acpi/routing.asl
index 3cfdb79..2a559c8 100644
--- a/src/mainboard/amd/bettong/acpi/routing.asl
+++ b/src/mainboard/amd/bettong/acpi/routing.asl
@@ -109,12 +109,9 @@ Name(APR0, Package(){
 	Package(){0x0013FFFF, 0, 0, 18 },
 	Package(){0x0013FFFF, 1, 0, 17 },
 
-	Package(){0x0016FFFF, 0, 0, 18 },
-	Package(){0x0016FFFF, 1, 0, 17 },
-
 	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, 0, 0x12},
-	Package(){0x0010FFFF, 1, 0, 0x11},
+	Package(){0x0010FFFF, 0, 0, 18},
+	Package(){0x0010FFFF, 1, 0, 17},
 
 	/* Bus 0, Dev 17 - SATA controller */
 	Package(){0x0011FFFF, 0, 0, 19 },
@@ -148,10 +145,10 @@ Name(PS4, Package(){
 })
 Name(APS4, Package(){
 	/* PCIe slot - Hooked to PCIe slot 4 */
-	Package(){0x0000FFFF, 0, 0, 16 },
-	Package(){0x0000FFFF, 1, 0, 17 },
-	Package(){0x0000FFFF, 2, 0, 18 },
-	Package(){0x0000FFFF, 3, 0, 19 },
+	Package(){0x0000FFFF, 0, 0, 24 },
+	Package(){0x0000FFFF, 1, 0, 25 },
+	Package(){0x0000FFFF, 2, 0, 26 },
+	Package(){0x0000FFFF, 3, 0, 27 },
 })
 
 /* GPP 0 */
@@ -162,10 +159,10 @@ Name(PS5, Package(){
 	Package(){0x0000FFFF, 3, INTA, 0 },
 })
 Name(APS5, Package(){
-	Package(){0x0000FFFF, 0, 0, 17 },
-	Package(){0x0000FFFF, 1, 0, 18 },
-	Package(){0x0000FFFF, 2, 0, 19 },
-	Package(){0x0000FFFF, 3, 0, 16 },
+	Package(){0x0000FFFF, 0, 0, 28 },
+	Package(){0x0000FFFF, 1, 0, 29 },
+	Package(){0x0000FFFF, 2, 0, 30 },
+	Package(){0x0000FFFF, 3, 0, 31 },
 })
 
 /* GPP 1 */
@@ -176,10 +173,10 @@ Name(PS6, Package(){
 	Package(){0x0000FFFF, 3, INTB, 0 },
 })
 Name(APS6, Package(){
-	Package(){0x0000FFFF, 0, 0, 18 },
-	Package(){0x0000FFFF, 1, 0, 19 },
-	Package(){0x0000FFFF, 2, 0, 16 },
-	Package(){0x0000FFFF, 3, 0, 17 },
+	Package(){0x0000FFFF, 0, 0, 32 },
+	Package(){0x0000FFFF, 1, 0, 33 },
+	Package(){0x0000FFFF, 2, 0, 34 },
+	Package(){0x0000FFFF, 3, 0, 35 },
 })
 
 /* GPP 2 */
@@ -190,10 +187,10 @@ Name(PS7, Package(){
 	Package(){0x0000FFFF, 3, INTC, 0 },
 })
 Name(APS7, Package(){
-	Package(){0x0000FFFF, 0, 0, 19 },
-	Package(){0x0000FFFF, 1, 0, 16 },
-	Package(){0x0000FFFF, 2, 0, 17 },
-	Package(){0x0000FFFF, 3, 0, 18 },
+	Package(){0x0000FFFF, 0, 0, 36 },
+	Package(){0x0000FFFF, 1, 0, 37 },
+	Package(){0x0000FFFF, 2, 0, 38 },
+	Package(){0x0000FFFF, 3, 0, 39 },
 })
 
 /* GPP 3 */
@@ -204,9 +201,52 @@ Name(PS8, Package(){
 	Package(){0x0000FFFF, 3, INTD, 0 },
 })
 Name(APS8, Package(){
-	Package(){0x0000FFFF, 0, 0, 16 },
-	Package(){0x0000FFFF, 1, 0, 17 },
-	Package(){0x0000FFFF, 2, 0, 18 },
-	Package(){0x0000FFFF, 3, 0, 18 },
+	Package(){0x0000FFFF, 0, 0, 40 },
+	Package(){0x0000FFFF, 1, 0, 41 },
+	Package(){0x0000FFFF, 2, 0, 42 },
+	Package(){0x0000FFFF, 3, 0, 43 },
+})
+
+/* GFX 2 */
+Name(PSA, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
 })
+Name(APSA, Package(){
+	Package(){0x0000FFFF, 0, 0, 52 },
+	Package(){0x0000FFFF, 1, 0, 53 },
+	Package(){0x0000FFFF, 2, 0, 54 },
+	Package(){0x0000FFFF, 3, 0, 55 },
+})
+
+/* GFX 3 */
+Name(PSB, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APSB, Package(){
+	Package(){0x0000FFFF, 0, 0, 27 },
+	Package(){0x0000FFFF, 1, 0, 24 },
+	Package(){0x0000FFFF, 2, 0, 25 },
+	Package(){0x0000FFFF, 3, 0, 26 },
+})
+
+/* GFX 4 */
+Name(PSC, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APSC, Package(){
+	Package(){0x0000FFFF, 0, 0, 31 },
+	Package(){0x0000FFFF, 1, 0, 28 },
+	Package(){0x0000FFFF, 2, 0, 29 },
+	Package(){0x0000FFFF, 3, 0, 30 },
+})
+
 
diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
index 7a9960f..b3df987 100644
--- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
@@ -98,3 +98,38 @@ Device(PBR8) {
 		Return (PS8)			/* PIC Mode */
 	} /* end _PRT */
 } /* end PBR8 */
+
+/* GFX 1 */
+Device(PBR9) {
+	Name(_ADR, 0x00030002)
+} /* end PBR8 */
+
+/* GFX 2 */
+Device(PBRA) {
+	Name(_ADR, 0x00030003)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APSA) }	/* APIC mode */
+		Return (PSA)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR8 */
+
+/* GFX 3 */
+Device(PBRB) {
+	Name(_ADR, 0x00030004)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APSB) }	/* APIC mode */
+		Return (PSB)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR8 */
+
+/* GFX 4 */
+Device(PBRC) {
+	Name(_ADR, 0x00030005)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APSC) }	/* APIC mode */
+		Return (PSC)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR8 */


From gerrit at coreboot.org  Thu Sep 17 11:21:16 2015
From: gerrit at coreboot.org (Nicolas Reinecke (nr@das-labor.org))
Date: Thu, 17 Sep 2015 11:21:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	southbridge/intel/bd82x6x: add option to not enable gpu audio codec
References: <Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da+0@gerrit.coreboot.org>
Message-ID: <Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da+8@gerrit.coreboot.org>

Nicolas Reinecke (nr at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8303

-gerrit

commit 5e96c39a62a1da8ea38eaad296944d0378962158
Author: Nicolas Reinecke <nr at das-labor.org>
Date:   Sat Jul 4 22:44:19 2015 +0200

    southbridge/intel/bd82x6x: add option to not enable gpu audio codec
    
    Some Thinkpads like T420s or T520 with discrete GPU have only VGA
    and LVDS conntected to the IGP. For this devices is it usefull to
    have an option to not enable audio codec. The audio dev shows up in
    linux as hdmi codec but is complete useless.
    
    Change-Id: Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da
    Signed-off-by: Nicolas Reinecke <nr at das-labor.org>
---
 src/mainboard/lenovo/t420s/devicetree.cb |  3 +++
 src/mainboard/lenovo/t520/devicetree.cb  |  3 +++
 src/southbridge/intel/bd82x6x/azalia.c   | 17 ++++++++++-------
 src/southbridge/intel/bd82x6x/chip.h     |  2 ++
 4 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index cd70228..0da501f 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -60,6 +60,9 @@ chip northbridge/intel/sandybridge
 			# Set max SATA speed to 6.0 Gb/s
 			register "sata_interface_speed_support" = "0x3"
 
+			# not enable audio codec on digital video outups. (for discrete gpu models)
+			register "azalia_video_codec_skip_enable" = "1"
+
 			register "gen1_dec" = "0x7c1601"
 			register "gen2_dec" = "0x0c15e1"
 			register "gen4_dec" = "0x0c06a1"
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index ff9745e..3d22e39 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -57,6 +57,9 @@ chip northbridge/intel/sandybridge
 			# Set max SATA speed to 6.0 Gb/s
 			register "sata_interface_speed_support" = "0x3"
 
+			# not enable audio codec on digital video outups. (for discrete gpu models)
+			register "azalia_video_codec_skip_enable" = "1"
+
 			register "gen1_dec" = "0x7c1601"
 			register "gen2_dec" = "0x0c15e1"
 			register "gen4_dec" = "0x0c06a1"
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 2dd8836..cb4a913 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -229,6 +229,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
 
 static void azalia_init(struct device *dev)
 {
+	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 	u8 *base;
 	struct resource *res;
 	u32 codec_mask;
@@ -268,14 +269,16 @@ static void azalia_init(struct device *dev)
 	reg32 |= (1 << 31);
 	pci_write_config32(dev, 0x120, reg32);
 
-	// Enable HDMI codec:
-	reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 1);
-	pci_write_config32(dev, 0xc4, reg32);
+	if (!(config->azalia_video_codec_skip_enable)) {
+		// Enable HDMI codec:
+		reg32 = pci_read_config32(dev, 0xc4);
+		reg32 |= (1 << 1);
+		pci_write_config32(dev, 0xc4, reg32);
 
-	reg8 = pci_read_config8(dev, 0x43);
-	reg8 |= (1 << 6);
-	pci_write_config8(dev, 0x43, reg8);
+		reg8 = pci_read_config8(dev, 0x43);
+		reg8 |= (1 << 6);
+		pci_write_config8(dev, 0x43, reg8);
+	}
 
 	/* Additional programming steps */
 	reg32 = pci_read_config32(dev, 0xc4);
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 3fa9192..731bbf9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -96,6 +96,8 @@ struct southbridge_intel_bd82x6x_config {
 	uint32_t superspeed_capable_ports;
 	/* Overcurrent Mapping for USB 3.0 Ports */
 	uint32_t xhci_overcurrent_mapping;
+	/* do not enable audio codec on digital video outputs */
+	uint8_t azalia_video_codec_skip_enable;
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */


From gerrit at coreboot.org  Thu Sep 17 14:13:40 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:13:40 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel/common:
	Add common code for filling out ACPI _SWS
References: <I4f3511adcc89a9be5d97a7442055c227a38c5f42+0@gerrit.coreboot.org>
Message-ID: <E1ZcZwS-0001rN-G2@mail.coreboot.org>

the following patch was just integrated into master:
commit 63ebc80e987c6778d5f15583e59a1476d4943c66
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:09:28 2015 -0700

    intel/common: Add common code for filling out ACPI _SWS
    
    Add common code for filling out the NVS fields that are used by
    the ACPI _SWS methods.  The SOC must provide a function to fill
    out the wake source data since the specific data inputs vary by
    platform.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I4f3511adcc89a9be5d97a7442055c227a38c5f42
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: cee5fa176c16ca44712bce8f3c8045daa5f07339
    Original-Change-Id: I16f446ef67777acb57223a84d38062be9f43fcb9
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298167
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11646
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11646 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:14:38 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:14:38 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Remove
	code to set USB charge behavior on sleep
References: <Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3+0@gerrit.coreboot.org>
Message-ID: <E1ZcZxO-0001ut-Kj@mail.coreboot.org>

the following patch was just integrated into master:
commit 0d19805f34f1191a6474f0a012ab38a5c7ed6294
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:29:58 2015 -0700

    glados: Remove code to set USB charge behavior on sleep
    
    The EC doesn't support these commands so sending them is
    not working.  We have had a default policy of wake on USB
    for a long time now and this runtime config isn't really
    needed any longer.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655
    Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298233
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11652
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11652 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:14:51 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:14:51 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Remove code to set USB charge behavior on sleep
References: <I547d92b4e852664567792060bf1f7b60976bb9a6+0@gerrit.coreboot.org>
Message-ID: <E1ZcZxb-0001wO-D5@mail.coreboot.org>

the following patch was just integrated into master:
commit 4a69562d01cc4fc716dcf25500d1de2b7ddb3ee5
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:31:09 2015 -0700

    kunimitsu: Remove code to set USB charge behavior on sleep
    
    The EC doesn't support these commands so sending them is
    not working.  We have had a default policy of wake on USB
    for a long time now and this runtime config isn't really
    needed any longer.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I547d92b4e852664567792060bf1f7b60976bb9a6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4a929eb9ec422e145006505ea4d5fbd1ef3950be
    Original-Change-Id: I01e80de65e6e1cdcabb24edb43bc671f5a8aa437
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298234
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11653
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11653 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:15:03 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:15:03 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: vbnv: check
	alignment of nvram in advance
References: <I3add4671ed354d9763e21bf96616c8aeca0cb777+0@gerrit.coreboot.org>
Message-ID: <E1ZcZxn-00020i-4R@mail.coreboot.org>

the following patch was just integrated into master:
commit 914a21ed9ceb403b178c30bedbc354e816b98e92
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Fri Sep 4 14:32:49 2015 -0700

    vbnv: check alignment of nvram in advance
    
    Currently, erase operation only works if the region is sector-aligned.
    These asserts ensure we can erase the region when it's all used up.
    
    Erase operation can be updated to handle unaligned erases by read,
    update, write-back cycle. However, these asserts will still remain useful
    in case the adjacent region contains critical data and mis-updating it
    can cause a critical failure.
    
    Additionaly we should write a FAFT test but it's more reliable to catch
    it here since FAFT can fail in many ways.
    
    BUG=none
    BRANCH=master
    TEST=tested on samus using misaligned nvram region
    
    Change-Id: I3add4671ed354d9763e21bf96616c8aeca0cb777
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fc001a4d3446cf96b76367dde492c3453aa948c6
    Original-Change-Id: Ib4df8f620bf7531b345364fa4c3e274aba09f677
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297801
    Reviewed-on: http://review.coreboot.org/11654
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11654 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:16:53 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 14:16:53 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/skylake:
	Create "RtcLock" Silicon UPD from coreboot
References: <I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7+0@gerrit.coreboot.org>
Message-ID: <I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11655

-gerrit

commit 29079e52878d0fed60baf6bb88b201a1e713834a
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Tue Sep 8 16:00:46 2015 +0530

    intel/skylake: Create "RtcLock" Silicon UPD from coreboot
    
    FSP should not lock CMOS unconditionally. coreboot sends Silicon
    UPD parameter "RtcLock" to FSP to take action on CMOS
    region locking/un-locking. This patch has CB generic code for
    creating the Silicon UPD paramater.
    
    BUG=chrome-os-partner:44484
    BRANCH=none
    TEST=Build and booted in kunimitsu, tested using below command-
    When DIsabled RtcLock from devicetree in coreboot, booted to kernel
    and run following commands -
    >> crossystem fw_result=success
    >> crossystem | grep fw_result
    It should reflect the value that is set. Here, success.
    If ENabled RtcLock from Coreboot devicetree, The same commands will
    fail to update the fw_result status from crossystem utility.
    CQ-DEPEND=CL:*229144
    
    Change-Id: I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c7b8293a2c55117d7ca2001ac9ec0de24d35b80b
    Original-Change-Id: If708e2c782644dcf7f03785d1bfa235ef5385d80
    Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297980
    Original-Commit-Ready: Subrata Banik <subrata.banik at intel.com>
    Original-Tested-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.c | 3 +++
 src/soc/intel/skylake/chip.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index afb0ff6..fd959b2 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -94,6 +94,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->DspEnable = config->DspEnable;
 	params->XdciEnable = config->XdciEnable;
 	params->Device4Enable = config->Device4Enable;
+	params->RtcLock = config->RtcLock;
 
 	/* Show SPI controller if enabled in devicetree.cb */
 	dev = dev_find_slot(0, PCH_DEVFN_SPI);
@@ -265,6 +266,8 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
 		params->HsioMessaging);
 	soc_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled,
 		params->Heci3Enabled);
+	soc_display_upd_value("RtcLock", 1, original->RtcLock,
+		params->RtcLock);
 }
 
 static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 94aa3a4..95f9502 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -229,6 +229,7 @@ struct soc_intel_skylake_config {
 	u32 LogoSize;
 	u32 GraphicsConfigPtr;
 	u8 Device4Enable;
+	u8 RtcLock;
 };
 
 typedef struct soc_intel_skylake_config config_t;


From gerrit at coreboot.org  Thu Sep 17 14:17:03 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:17:03 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel/skylake:
	Create "RtcLock" Silicon UPD from coreboot
References: <I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7+0@gerrit.coreboot.org>
Message-ID: <E1ZcZzj-0002NT-VT@mail.coreboot.org>

the following patch was just integrated into master:
commit b090a268a2e993fc7fa719ab3b9b7283034c9d10
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Tue Sep 8 16:00:46 2015 +0530

    intel/skylake: Create "RtcLock" Silicon UPD from coreboot
    
    FSP should not lock CMOS unconditionally. coreboot sends Silicon
    UPD parameter "RtcLock" to FSP to take action on CMOS
    region locking/un-locking. This patch has CB generic code for
    creating the Silicon UPD paramater.
    
    BUG=chrome-os-partner:44484
    BRANCH=none
    TEST=Build and booted in kunimitsu, tested using below command-
    When DIsabled RtcLock from devicetree in coreboot, booted to kernel
    and run following commands -
    >> crossystem fw_result=success
    >> crossystem | grep fw_result
    It should reflect the value that is set. Here, success.
    If ENabled RtcLock from Coreboot devicetree, The same commands will
    fail to update the fw_result status from crossystem utility.
    CQ-DEPEND=CL:*229144
    
    Change-Id: I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c7b8293a2c55117d7ca2001ac9ec0de24d35b80b
    Original-Change-Id: If708e2c782644dcf7f03785d1bfa235ef5385d80
    Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297980
    Original-Commit-Ready: Subrata Banik <subrata.banik at intel.com>
    Original-Tested-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11655
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11655 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:17:22 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:17:22 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: t210:
	lp0_resume: Configure unused SDMMC1/3 pads for low power leakage
References: <If5d5cebc89b8220480b3c72293a410e782eb437e+0@gerrit.coreboot.org>
Message-ID: <E1Zca02-0002PZ-0h@mail.coreboot.org>

the following patch was just integrated into master:
commit 741537e1d99ed7465f5a7e74089667ef1d3a5bfc
Author: Yen Lin <yelin at nvidia.com>
Date:   Tue Sep 8 15:13:13 2015 -0700

    t210: lp0_resume: Configure unused SDMMC1/3 pads for low power leakage
    
    In LP0 resume, a couple of SDMMCx pad settings need to be set to 0 to
    reduce power leakage.
    
    BUG=None
    BRANCH=None
    TEST=Tested on Smaug; able to suspend/resume >100 times
    
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9f35a90a8af2180443db2c4be75d4566d0990de5
    Original-Change-Id: Ifc946b0cea437ef0807cea0c11609d8e09387e8e
    Original-Signed-off-by: Yen Lin <yelin at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298195
    Original-Reviewed-by: Andrew Bresticker <abrestic at chromium.org>
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Tested-by: Joseph Lo <josephl at nvidia.com>
    Original-(cherry picked from commit be3ac49a6bc4c9088d3799555d69c87c8ce1693c)
    Original-Reviewed-on: https://chromium-review.googlesource.com/298154
    Original-Commit-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    
    Change-Id: If5d5cebc89b8220480b3c72293a410e782eb437e
    Reviewed-on: http://review.coreboot.org/11656
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11656 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:17:37 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:17:37 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: ifdtool:
	Properly set + decode flmstr regs for IFD v2
References: <I8a65bdc5edd0d888138b88c1189f8badd1404b64+0@gerrit.coreboot.org>
Message-ID: <E1Zca0H-0002RE-58@mail.coreboot.org>

the following patch was just integrated into master:
commit d2cb11811ca0fd45ebfb3a08f1c4cc8faa1d56d4
Author: Shawn Nematbakhsh <shawnn at chromium.org>
Date:   Thu Sep 10 19:07:13 2015 -0700

    ifdtool: Properly set + decode flmstr regs for IFD v2
    
    flmstr register bits have slightly different meaning for IFD v2.
    
    BUG=chrome-os-partner:45091, chrome-os-partner:43461
    TEST=Run `ifdtool -d image.bin` on IFD v1 locked squawks image:
    
    Found Master Section
    FLMSTR1:   0x0a0b0000 (Host CPU/BIOS)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      disabled
      Host CPU/BIOS Region Write Access: enabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       disabled
      Host CPU/BIOS Region Read Access:  enabled
      Flash Descriptor Read Access:      enabled
      Requester ID:                      0x0000
    
    FLMSTR2:   0x0c0d0000 (Intel ME)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      enabled
      Host CPU/BIOS Region Write Access: disabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       enabled
      Host CPU/BIOS Region Read Access:  disabled
      Flash Descriptor Read Access:      enabled
      Requester ID:                      0x0000
    
    FLMSTR3:   0x08080118 (GbE)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      disabled
      Host CPU/BIOS Region Write Access: disabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       disabled
      Host CPU/BIOS Region Read Access:  disabled
      Flash Descriptor Read Access:      disabled
      Requester ID:                      0x0118
    
    Then, run `ifdtool -l image.bin` and verify newly locked image is identical.
    Next, run `ifdtool -l image.bin` on unlocked glados image. Verify that locked
    and unlocked regions are identical to above.
    Finally, burn glados image, run `flashrom -V`, and verify ME regions is
    locked and descriptor region is RO.
    BRANCH=None
    
    Change-Id: I8a65bdc5edd0d888138b88c1189f8badd1404b64
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 11c434835a66a50ab2c0c01a084edc96cbe052da
    Original-Signed-off-by: Shawn Nematbakhsh <shawnn at chromium.org>
    Original-Change-Id: I875dfce6f5cf57831714702872bfe636f8f953f4
    Original-Reviewed-on: https://chromium-review.googlesource.com/298968
    Original-Commit-Ready: Shawn N <shawnn at chromium.org>
    Original-Tested-by: Shawn N <shawnn at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11658
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11658 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:18:02 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:18:02 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: linking:
	Repair special treatments for non-x86 bootblocks
References: <I54271b8b59a9c773d858d676cde0218cb7f20e74+0@gerrit.coreboot.org>
Message-ID: <E1Zca0g-0002Vk-8B@mail.coreboot.org>

the following patch was just integrated into master:
commit 52a92606bb594c52da50b8c5dcfc9f9307c481e6
Author: Julius Werner <jwerner at chromium.org>
Date:   Fri Sep 11 16:17:50 2015 -0700

    linking: Repair special treatments for non-x86 bootblocks
    
    Patch b2a62622b (linking: move romstage and bootblock to use program.ld)
    unified the linker scripts between different stages. Unfortunately it
    omitted several special cases from the old bootblock.ld script that are
    required for non-x86 environments.
    
    This patch expands program.ld to once again merge the .BSS into the
    program image for bootblocks (ensuring correct initialization by the
    external loader). It also revives the .id section (which adds a
    human-readable blurb of information to the top of an image) and fixes a
    problem with unintended automated section alignment.
    
    BRANCH=None
    BUG=None
    TEST=Jerry and Oak boot again.
    
    Change-Id: I54271b8b59a9c773d858d676cde0218cb7f20e74
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6fddbc00963e363039634fa31a9b66254b6cf18f
    Original-Change-Id: I4d748056f1ab29a8e730f861879982bdf4c33eab
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/299413
    Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11660
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11660 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:18:16 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:18:16 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	usb: dwc2: fix hub hot-plug bug
References: <Ib4604097743f2f9d763b29ee27f3bc1788a85a62+0@gerrit.coreboot.org>
Message-ID: <E1Zca0u-0002Y6-59@mail.coreboot.org>

the following patch was just integrated into master:
commit a881000cd1d5df26f512e4ce7a1a1a6161a8b636
Author: Yunzhi Li <lyz at rock-chips.com>
Date:   Fri Aug 28 09:43:44 2015 +0800

    libpayload: usb: dwc2: fix hub hot-plug bug
    
    When disconnect is detected in dwc2_split_transfer() the split
    configuration registers should be cleared before return.
    
    BRANCH=None
    BUG=chrome-os-partner:44534
    TEST=On Jerry, usb hot plug works with devices behind hubs
    
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 37594d8b4490b6d393d19d17d8e497db7de8817d
    Original-Change-Id: Ie1eecec067305874513c6ceb95df4240dc393cd6
    Original-Signed-off-by: Yunzhi Li <lyz at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295625
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Commit-Queue: Lin Huang <hl at rock-chips.com>
    Original-Tested-by: Lin Huang <hl at rock-chips.com>
    Original-(cherry picked from commit d543e14cdc73bd549dd553c8d1d07672a1307981)
    Original-Reviewed-on: https://chromium-review.googlesource.com/299700
    Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: Ib4604097743f2f9d763b29ee27f3bc1788a85a62
    Reviewed-on: http://review.coreboot.org/11661
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11661 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:18:38 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:18:38 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	usb: dwc2: check device connect state before enable channel
References: <Idf48ffbc4c2794900e09dec6b2e34e33b21f87b4+0@gerrit.coreboot.org>
Message-ID: <E1Zca1G-0002ar-Ds@mail.coreboot.org>

the following patch was just integrated into master:
commit 87c9f0eaa90253f45c8114fc542ad3a46caa2647
Author: Yunzhi Li <lyz at rock-chips.com>
Date:   Thu Sep 10 11:42:30 2015 +0800

    libpayload: usb: dwc2: check device connect state before enable channel
    
    If the device has already been disconnected then we shouldn't enable
    host channel to start any transfer, otherwise this channel goes into
    an odd state the channel is enabled but can not be disabled by set
    hcchar.chdis=1. So we need check the device connect status before
    enable channel.
    
    BRANCH=None
    BUG=chrome-os-partner:44534
    TEST=None
    
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: ae3e690b2cd4a9ea8b5766ac873b0e00bf3a23de
    Original-Change-Id: Ib3ecf486649ca11b302144f9c00a5e88424e90fa
    Original-Signed-off-by: Yunzhi Li <lyz at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298402
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Commit-Queue: Lin Huang <hl at rock-chips.com>
    Original-Tested-by: Lin Huang <hl at rock-chips.com>
    Original-(cherry picked from commit ea96f947b5304fdde2e0991d23febaeba209dde1)
    Original-Reviewed-on: https://chromium-review.googlesource.com/299398
    Original-Commit-Ready: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: Idf48ffbc4c2794900e09dec6b2e34e33b21f87b4
    Reviewed-on: http://review.coreboot.org/11662
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11662 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:18:52 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:18:52 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	drivers/intel/fsp1_1: prepare relocation code for sharing
References: <I650a08ffb9caf7e0438a988cae9bec56dd31753c+0@gerrit.coreboot.org>
Message-ID: <E1Zca1U-0002cu-EO@mail.coreboot.org>

the following patch was just integrated into master:
commit 8007c6b6e82d85a1c3f96870b0f239d9ce1549bc
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 21:19:25 2015 -0500

    drivers/intel/fsp1_1: prepare relocation code for sharing
    
    In order to integrate fsp 1.1 relocation with cbfstool one
    needs to be able to supply the address to relocate the FSP
    image. Therefore, allow this by returning offset for return
    values. Note that exposed API has not changed.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados. Confirmed relocation values matched.
    
    Change-Id: I650a08ffb9caf7e0438a988cae9bec56dd31753c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 53870b0df809418e9a09e7d380ad2399a09fb4fb
    Original-Change-Id: Ic2ec63681ed4e652e2624b40e132f95d1e5a0887
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298831
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    Reviewed-on: http://review.coreboot.org/11663
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11663 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:19:03 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:19:03 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	drivers/intel/fsp1_1: handle UEFI endianness
References: <I39f4de84688e48978a4650303b8af8345f44fd03+0@gerrit.coreboot.org>
Message-ID: <E1Zca1g-0002eh-0J@mail.coreboot.org>

the following patch was just integrated into master:
commit a77d0d6b39cbd87265b7b55a45dca0ca4b4ded43
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 22:36:20 2015 -0500

    drivers/intel/fsp1_1: handle UEFI endianness
    
    UEFI defines everything as little endian. Additionally the
    EDK II header files assume they are used on machines
    which are running UEFI -- thus little endian. This patch
    attempts to fix up all the possible endian violations
    when running on a big endian machine. This is for
    in preparation of using the FSP 1.1 code in userland
    for relocating FSP images.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I39f4de84688e48978a4650303b8af8345f44fd03
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3c7eab9b7c10765355feffa3c3cac403275f9479
    Original-Change-Id: I33a7661281307cf31ae33899d1a4eb6a2fbd01a1
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298832
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11664
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11664 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:19:25 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:19:25 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	drivers/intel/fsp1_1: split relocation code for tool use
References: <I49998b8621611c638375bc90884e80d0cd3bdf78+0@gerrit.coreboot.org>
Message-ID: <E1Zca21-0002hY-Kv@mail.coreboot.org>

the following patch was just integrated into master:
commit a5be7fa5c14a56d8544502c54cccc43637fab258
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 10 22:52:27 2015 -0500

    drivers/intel/fsp1_1: split relocation code for tool use
    
    In order for easier consumption in userland tools split the
    FSP 1.1 relocation logic into a single file w/ an aptly named
    function name.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I49998b8621611c638375bc90884e80d0cd3bdf78
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: bc898e1c528df60683575d553d6194a1e8200afa
    Original-Change-Id: I736c0059d43f6d0be4fdb6e6f47cdb5c189a7ae8
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298833
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11665
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11665 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:19:38 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:19:38 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: Skylake:
	update C state latency and power numbers
References: <Ia6bd336a71b0313801b59990c78822fa0d789e36+0@gerrit.coreboot.org>
Message-ID: <E1Zca2E-0002jM-1m@mail.coreboot.org>

the following patch was just integrated into master:
commit c16b1fd8ac549160b2ac564ab20c6b8ef3de8afb
Author: robbie zhang <robbie.zhang at intel.com>
Date:   Fri Sep 11 14:25:15 2015 -0700

    Skylake: update C state latency and power numbers
    
    The values are taken from latest BWG as well fsp src.
    
    BRANCH=none
    BUG=chrome-os-partner:45208
    TEST=Built and boot on kunimitsu
    Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    
    Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164
    Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b
    Original-Reviewed-on: https://chromium-review.googlesource.com/299480
    Original-Commit-Ready: Wenkai Du <wenkai.du at intel.com>
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11659
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11659 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:20:49 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:20:49 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Enable
	wake-on-wifi
References: <I989768615e9da8ecf6354852d2db7aae8069aa82+0@gerrit.coreboot.org>
Message-ID: <E1Zca3N-00031E-Sg@mail.coreboot.org>

the following patch was just integrated into master:
commit e09eb68088983694ea2ad9694a1178ee0f8e33a5
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:24:20 2015 -0700

    glados: Enable wake-on-wifi
    
    - Assign GPE DW0 to GPP_B block
    - Enable GPP_B16 as ACPI_SCI for wake
    - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW
    
    Note that current designs cannot wake from Deep S3 via wifi.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=tested on glados:
    1-disable deep s3 in devicetree.cb
    2-enable magic packet with "iw phy phy0 wowlan enable magic-packet"
    3-powerd_dbus_suspend to go to S3
    4-wake system with magic packet
    
    Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2
    Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298231
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11650
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11650 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:21:07 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:21:07 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu:
	Enable wake-on-wifi
References: <I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48+0@gerrit.coreboot.org>
Message-ID: <E1Zca3f-00034Q-ME@mail.coreboot.org>

the following patch was just integrated into master:
commit d6a42f9af8776d2b2b924d6da0c08ce992da922a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:28:21 2015 -0700

    kunimitsu: Enable wake-on-wifi
    
    - Assign GPE DW0 to GPP_B block
    - Enable GPP_B16 as ACPI_SCI for wake
    - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW
    
    Note that current designs cannot wake from Deep S3 via wifi.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529
    Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298232
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11651
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11651 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:21:18 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:21:18 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	glados/kunimitsu: remove the implementation of
	mainboard_add_dimm_info
References: <I949e287372b190affac36a0efde8a30402eecdc8+0@gerrit.coreboot.org>
Message-ID: <E1Zca3q-00035g-GI@mail.coreboot.org>

the following patch was just integrated into master:
commit 47a0b8494b59cf292dcc3372a01ee597b6de3923
Author: robbie zhang <robbie.zhang at intel.com>
Date:   Thu Sep 10 16:24:44 2015 -0700

    glados/kunimitsu: remove the implementation of mainboard_add_dimm_info
    
    This is a follow-up patch to
    https://chromium-review.googlesource.com/#/c/286877, after fsp support
    is landed in v1.5.
    
    BUG=chrome-os-partner:42975
    BRANCH=none
    TEST=execute "mosys memory spd print all" on glados and kunimitsu
    
    Change-Id: I949e287372b190affac36a0efde8a30402eecdc8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa
    Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3
    Original-Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298967
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11657
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11657 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:23:46 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:23:46 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: Use
	common ACPI _SWS code
References: <I93a4f740f2e2ef1c34e948db1d8e273332296921+0@gerrit.coreboot.org>
Message-ID: <E1Zca6E-0003IN-Gg@mail.coreboot.org>

the following patch was just integrated into master:
commit a1c8b34d7b1b3a8df5b86faab79010c06b037445
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:12:44 2015 -0700

    skylake: Use common ACPI _SWS code
    
    Enable and use the common code for filling out the NVS data used
    by the _SWS methods.  Add a function to provide the wake source
    data.  With Deep S3 enabled skylake does not retain the contents
    of the PM1_EN register so instead just select the wake related
    events in PM1_STS.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=tested on glados by checking for valid _SWS string in
    /sys/firmware/log after suspend/resume.  Wake sources that were
    tested are RTC, power button, keypress, trackpad, and wifi.
    
    Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0
    Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298169
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11648
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11648 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:23:59 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:23:59 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: braswell:
	Switch to using common ACPI _SWS code
References: <I41c2a141c15f78dc0d9482954c157f81bd0759fa+0@gerrit.coreboot.org>
Message-ID: <E1Zca6R-0003L4-BG@mail.coreboot.org>

the following patch was just integrated into master:
commit e73da80d2c63f14cdc301a2436cf9b93dc5a531f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:16:34 2015 -0700

    braswell: Switch to using common ACPI _SWS code
    
    Switch braswell to use the common code for filling out the NVS
    data used by ACPI _SWS methods.  This code was out of date on
    braswell so also update it to provide the \_GPE.SWS method.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-cyan coreboot
    
    Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0
    Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298230
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11649
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11649 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:24:50 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 14:24:50 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: broadwell: Switch
	to using common ACPI _SWS code
References: <I3d2ceca8585314122b78317acb7f848efb6e9a14+0@gerrit.coreboot.org>
Message-ID: <I3d2ceca8585314122b78317acb7f848efb6e9a14+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11647

-gerrit

commit 76f8ffef2f8cde457b4bdb1a3d1de40224fe4a2d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:10:30 2015 -0700

    broadwell: Switch to using common ACPI _SWS code
    
    Use the common ACPI _SWS code and provide a function to fill out
    the wake source data.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-samus coreboot
    
    Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d8afaee8e27222639c5e249d53be28cddcb78f72
    Original-Change-Id: Ie551ecf3397c304216046cc2046c071f7b766e5f
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298168
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/broadwell/Kconfig           |  1 +
 src/soc/intel/broadwell/acpi/platform.asl | 21 ++----------
 src/soc/intel/broadwell/ramstage.c        | 57 ++++++-------------------------
 3 files changed, 15 insertions(+), 64 deletions(-)

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index e01d559..6561fe2 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select SOC_INTEL_COMMON
 	select HAVE_INTEL_FIRMWARE
+	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 
 config BOOTBLOCK_CPU_INIT
 	string
diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl
index d302720..c00edeb 100644
--- a/src/soc/intel/broadwell/acpi/platform.asl
+++ b/src/soc/intel/broadwell/acpi/platform.asl
@@ -18,6 +18,9 @@
  * Foundation, Inc.
  */
 
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
 /* The APM port can be used for generating software SMIs */
 
 OperationRegion (APMP, SystemIO, 0xb2, 2)
@@ -71,21 +74,3 @@ Method (_WAK, 1)
 {
 	Return (Package (){ 0, 0 })
 }
-
-Scope (\_SB)
-{
-	Method (_SWS)
-	{
-		/* Index into PM1 for device that caused wake */
-		Return (\PM1I)
-	}
-}
-
-Scope (\_GPE)
-{
-	Method (_SWS)
-	{
-		/* Index into GPE for device that caused wake */
-		Return (\GPEI)
-	}
-}
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index e699e02..c8fb6ed 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -27,56 +27,23 @@
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/intel/broadwell/chip.h>
+#include <soc/intel/common/acpi.h>
 
-/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
-static void save_acpi_wake_source(global_nvs_t *gnvs)
+/* Save wake source information for calculating ACPI _SWS values */
+int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
 {
 	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
-	uint16_t pm1;
-	int gpe_reg;
+	static uint32_t gpe0_sts[GPE0_REG_MAX];
+	int i;
 
-	if (!ps)
-		return;
-
-	pm1 = ps->pm1_sts & ps->pm1_en;
-
-	/* Scan for first set bit in PM1 */
-	for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
-		if (pm1 & 1)
-			break;
-		pm1 >>= 1;
-	}
-
-	/* If unable to determine then return -1 */
-	if (gnvs->pm1i >= 16)
-		gnvs->pm1i = -1;
-
-	/* Scan for first set bit in GPE registers */
-	gnvs->gpei = -1;
-	for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
-		u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
-		int start = gpe_reg * GPE0_REG_SIZE;
-		int end = start + GPE0_REG_SIZE;
-
-		if (gpe == 0) {
-			if (!gnvs->gpei)
-				gnvs->gpei = end;
-			continue;
-		}
-
-		for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
-			if (gpe & 1)
-				break;
-			gpe >>= 1;
-		}
-	}
+	*pm1 = ps->pm1_sts & ps->pm1_en;
 
-	/* If unable to determine then return -1 */
-	if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
-		gnvs->gpei = -1;
+	/* Mask off GPE0 status bits that are not enabled */
+	*gpe0 = &gpe0_sts[0];
+	for (i = 0; i < GPE0_REG_MAX; i++)
+		gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
 
-	printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
-	       gnvs->pm1i, gnvs->gpei);
+	return GPE0_REG_MAX;
 }
 
 static void s3_resume_prepare(void)
@@ -89,8 +56,6 @@ static void s3_resume_prepare(void)
 
 	if (!acpi_is_wakeup_s3())
 		memset(gnvs, 0, sizeof(global_nvs_t));
-	else
-		save_acpi_wake_source(gnvs);
 }
 
 void broadwell_init_pre_device(void *chip_info)


From gerrit at coreboot.org  Thu Sep 17 14:25:01 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 14:25:01 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfs: read cbfs
	offset and size from sysinfo
References: <I86434fd249467e7c90d59d6b82f0e6c514bc2d05+0@gerrit.coreboot.org>
Message-ID: <I86434fd249467e7c90d59d6b82f0e6c514bc2d05+3@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11557

-gerrit

commit 6736fe697a1837ad32d7fd2aa6c01632d1ea0c9b
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Sep 2 10:53:13 2015 -0700

    cbfs: read cbfs offset and size from sysinfo
    
    This change allows libpayload to read cbfs offset and size from sysinfo.
    Legacy way of locating cbfs reagion is still supported in case sysinfo
    doesn't store the offset and the size.
    
    BUG=none
    BRANCH=master
    TEST=tested on samus and smaug
    
    Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c
    Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296993
    Original-Commit-Ready: Daisuke Nojiri <dnojiri at google.com>
    Original-Tested-by: Daisuke Nojiri <dnojiri at google.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 payloads/libpayload/libcbfs/cbfs_core.c | 70 +++++++++++++++++++++------------
 1 file changed, 45 insertions(+), 25 deletions(-)

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 7926d9d..90f600c 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -47,6 +47,7 @@
 
 #include <cbfs.h>
 #include <string.h>
+#include <sysinfo.h>
 
 /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS
  *  on failure */
@@ -94,52 +95,71 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
 	return header;
 }
 
-/* public API starts here*/
-struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end,
+			  struct cbfs_media *media)
 {
-	const char *file_name;
-	uint32_t offset, romsize, name_len;
 	const struct cbfs_header *header;
-	struct cbfs_file file, *file_ptr;
-	struct cbfs_media default_media;
 
-	if (media == CBFS_DEFAULT_MEDIA) {
-		media = &default_media;
-		if (init_default_cbfs_media(media) != 0) {
-			ERROR("Failed to initialize default media.\n");
-			return NULL;
-		}
+	if (lib_sysinfo.cbfs_offset && lib_sysinfo.cbfs_size) {
+		*offset = lib_sysinfo.cbfs_offset;
+		*cbfs_end = *offset + lib_sysinfo.cbfs_size;
+		return 0;
 	}
 
-	if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media)))
-		return NULL;
-
+	/*
+	 * If sysinfo doesn't have offset or size, we read them from
+	 * a master header.
+	 */
+	DEBUG("CBFS offset & size not found in sysinfo\n");
+	header = cbfs_get_header(media);
+	if (header == CBFS_HEADER_INVALID_ADDRESS)
+		return -1;
 	// Logical offset (for source media) of first file.
-	offset = ntohl(header->offset);
-	romsize = ntohl(header->romsize);
-
-	// TODO Add a "size" in CBFS header for a platform independent way to
-	// determine the end of CBFS data.
+	*offset = ntohl(header->offset);
+	*cbfs_end = ntohl(header->romsize);
 #if IS_ENABLED(CONFIG_LP_ARCH_X86)
 	// resolve actual length of ROM used for CBFS components
 	// the bootblock size was not taken into account
-	romsize -= ntohl(header->bootblocksize);
+	*cbfs_end -= ntohl(header->bootblocksize);
 
 	// fine tune the length to handle alignment positioning.
 	// using (bootblock size) % align, to derive the
 	// number of bytes the bootblock is off from the alignment size.
 	if ((ntohl(header->bootblocksize) % CBFS_ALIGNMENT))
-		romsize -= (CBFS_ALIGNMENT -
+		*cbfs_end -= (CBFS_ALIGNMENT -
 			(ntohl(header->bootblocksize) % CBFS_ALIGNMENT));
 	else
-		romsize -= 1;
+		*cbfs_end -= 1;
 #endif
+	return 0;
+}
+
+/* public API starts here*/
+struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+{
+	const char *file_name;
+	uint32_t offset, cbfs_end, name_len;
+	struct cbfs_file file, *file_ptr;
+	struct cbfs_media default_media;
+
+	if (media == CBFS_DEFAULT_MEDIA) {
+		media = &default_media;
+		if (init_default_cbfs_media(media) != 0) {
+			ERROR("Failed to initialize default media.\n");
+			return NULL;
+		}
+	}
+
+	if (get_cbfs_range(&offset, &cbfs_end, media)) {
+		ERROR("Failed to find cbfs range\n");
+		return NULL;
+	}
 
-	DEBUG("CBFS location: 0x%x~0x%x\n", offset, romsize);
+	DEBUG("CBFS location: 0x%x~0x%x\n", offset, cbfs_end);
 	DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset);
 
 	media->open(media);
-	while (offset < romsize &&
+	while (offset < cbfs_end &&
 	       media->read(media, &file, offset, sizeof(file)) == sizeof(file)) {
 		if (memcmp(CBFS_FILE_MAGIC, file.magic,
 			   sizeof(file.magic)) != 0) {


From gerrit at coreboot.org  Thu Sep 17 14:26:20 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 14:26:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload: allow
	compression at file header level
References: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+0@gerrit.coreboot.org>
Message-ID: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10938

-gerrit

commit f87649d00eef28ba4f7ca5bb48c7c4a9865d087b
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: allow compression at file header level
    
    Decompression is handled transparently within cbfs_get_file_content:
    
    	const char *name = "foo.bmp";
    	void *dst = cbfs_get_file_content(media, name, type, NULL);
    
    To keep things consistent, a couple of API changes were necessary:
    - cbfs_get_file_content always returns a copy of the data, even for
      uncompressed files. It's the callers responsibility to free the
      memory.
    - same for cbfs_load_payload and cbfs_find_file.
    - cbfs_load_optionrom doesn't take a "dest" argument anymore but always
      returns a copy of the data, for compressed and uncompressed files.
      Like with cbfs_get_file_content, the caller is responsible to free it.
      It also decompresses based on extended file attributes instead of the
      cbfs_optionrom subheader that libpayload specified but that (AFAIK)
      nobody ever used, given that there's not even tooling for that.
    
    Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/cbfs.h      |  2 +-
 payloads/libpayload/include/cbfs_core.h | 18 ++++++++++++++--
 payloads/libpayload/libcbfs/cbfs.c      | 37 +++++++--------------------------
 payloads/libpayload/libcbfs/cbfs_core.c | 24 ++++++++++++++++++++-
 4 files changed, 47 insertions(+), 34 deletions(-)

diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h
index 59c31db..f57dce0 100644
--- a/payloads/libpayload/include/cbfs.h
+++ b/payloads/libpayload/include/cbfs.h
@@ -59,7 +59,7 @@ void *cbfs_find_file(const char *name, int type);
 
 int cbfs_execute_stage(struct cbfs_media *media, const char *name);
 void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device, void * dest);
+			  uint16_t device);
 void *cbfs_load_payload(struct cbfs_media *media, const char *name);
 void *cbfs_load_stage(struct cbfs_media *media, const char *name);
 
diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index a2ee744..3878e55 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -53,6 +53,7 @@
 #include <endian.h>
 #include <stddef.h>
 #include <stdint.h>
+#include <stdlib.h>
 
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
@@ -141,6 +142,7 @@ struct cbfs_file {
  * 0xff. Support both. */
 #define CBFS_FILE_ATTR_TAG_UNUSED 0
 #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
 
 /* The common fields of extended cbfs file attributes.
    Attributes are expected to start with tag/len, then append their
@@ -152,6 +154,14 @@ struct cbfs_file_attribute {
 	uint8_t data[0];
 } __attribute__((packed));
 
+struct cbfs_file_attr_compression {
+	uint32_t tag;
+	uint32_t len;
+	/* whole file compression format. 0 if no compression. */
+	uint32_t compression;
+	uint32_t decompressed_size;
+} __attribute__((packed));
+
 /* Given a cbfs_file, return the first file attribute, or NULL. */
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
 
@@ -237,10 +247,14 @@ struct cbfs_media {
 	int (*close)(struct cbfs_media *media);
 };
 
-/* returns pointer to a file entry inside CBFS or NULL */
+/* returns pointer to a file entry inside CBFS or NULL on error */
 struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name);
 
-/* returns pointer to file content inside CBFS after if type is correct */
+/*
+ * Returns pointer to a copy of the file content or NULL on error.
+ * If the file is compressed, data will be decompressed.
+ * The caller owns the returned memory.
+ */
 void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 			    int type, size_t *sz);
 
diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
index 3e614b6..49e4941 100644
--- a/payloads/libpayload/libcbfs/cbfs.c
+++ b/payloads/libpayload/libcbfs/cbfs.c
@@ -79,41 +79,14 @@ static void tohex16(unsigned int val, char* dest)
 }
 
 void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device, void *dest)
+			  uint16_t device)
 {
 	char name[17] = "pciXXXX,XXXX.rom";
-	struct cbfs_optionrom *orom;
-	uint8_t *src;
 
 	tohex16(vendor, name+3);
 	tohex16(device, name+8);
 
-	orom = (struct cbfs_optionrom *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
-
-	if (orom == NULL)
-		return NULL;
-
-	/* They might have specified a dest address. If so, we can decompress.
-	 * If not, there's not much hope of decompressing or relocating the rom.
-	 * in the common case, the expansion rom is uncompressed, we
-	 * pass 0 in for the dest, and all we have to do is find the rom and
-	 * return a pointer to it.
-	 */
-
-	/* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */
-	src = (uint8_t*)orom; // + sizeof(struct cbfs_optionrom);
-
-	if (! dest)
-		return src;
-
-	if (!cbfs_decompress(ntohl(orom->compression),
-			     src,
-			     dest,
-			     ntohl(orom->len)))
-		return NULL;
-
-	return dest;
+	return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
 }
 
 void * cbfs_load_stage(struct cbfs_media *media, const char *name)
@@ -149,6 +122,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 	entry = stage->entry;
 	// entry = ntohll(stage->entry);
 
+	free(stage);
 	return (void *) entry;
 }
 
@@ -163,11 +137,14 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name)
 	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
 		LOG("Unable to run %s:  Compressed file"
 		       "Not supported for in-place execution\n", name);
+		free(stage);
 		return 1;
 	}
 
 	LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry));
-	return run_address((void *)(uintptr_t)ntohll(stage->entry));
+	int result = run_address((void *)(uintptr_t)ntohll(stage->entry));
+	free(stage);
+	return result;
 }
 
 void *cbfs_load_payload(struct cbfs_media *media, const char *name)
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 5541f02..213ea44 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -210,7 +210,29 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 	if (sz)
 		*sz = ntohl(file->len);
 
-	return (void *)CBFS_SUBHEADER(file);
+	void *file_content = (void *)CBFS_SUBHEADER(file);
+
+	struct cbfs_file_attribute *attr = cbfs_file_first_attr(file);
+	while (attr) {
+		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION)
+			break;
+		attr = cbfs_file_next_attr(file, attr);
+	}
+	size_t final_size = ntohl(file->len);
+	int compression_algo = CBFS_COMPRESS_NONE;
+	if (attr) {
+		struct cbfs_file_attr_compression *comp =
+			(struct cbfs_file_attr_compression *)attr;
+		compression_algo = ntohl(comp->compression);
+		DEBUG("File '%s' is compressed (alg=%d)\n", compression_algo);
+		final_size = ntohl(comp->decompressed_size);
+	}
+	void *dst = malloc(final_size);
+	if (cbfs_decompress(compression_algo, file_content, dst, final_size)) {
+		free(dst);
+		return NULL;
+	}
+	return dst;
 }
 
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file)


From gerrit at coreboot.org  Thu Sep 17 14:26:28 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 14:26:28 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: libpayload:
	rename cbfs variable from name to vardata
References: <I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761+0@gerrit.coreboot.org>
Message-ID: <I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11676

-gerrit

commit 4260ba2e7aa28631e5a60042c22b46b86c37b19d
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: rename cbfs variable from name to vardata
    
    The dynamically sized region after struct cbfs_file doesn't contain only
    the file name anymore.
    
    Change-Id: I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/libcbfs/cbfs_core.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 6a19b26..5541f02 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -97,8 +97,8 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
 /* public API starts here*/
 struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
 {
-	const char *file_name;
-	uint32_t offset, romsize, name_len;
+	const char *vardata;
+	uint32_t offset, romsize, vardata_len;
 	const struct cbfs_header *header;
 	struct cbfs_file file, *file_ptr;
 	struct cbfs_media default_media;
@@ -153,29 +153,29 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
 			offset += new_align;
 			continue;
 		}
-		name_len = ntohl(file.offset) - sizeof(file);
-		DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset,
-		      name_len);
+		vardata_len = ntohl(file.offset) - sizeof(file);
+		DEBUG(" - load entry 0x%x variable data (%d bytes)...\n",
+			offset, vardata_len);
 
 		// load file name (arbitrary length).
-		file_name = (const char*)media->map(
-				media, offset + sizeof(file), name_len);
-		if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) {
+		vardata = (const char*)media->map(
+				media, offset + sizeof(file), vardata_len);
+		if (vardata == CBFS_MEDIA_INVALID_MAP_ADDRESS) {
 			ERROR("ERROR: Failed to get filename: 0x%x.\n", offset);
-		} else if (strcmp(file_name, name) == 0) {
+		} else if (strcmp(vardata, name) == 0) {
 			int file_offset = ntohl(file.offset),
 			    file_len = ntohl(file.len);
 			DEBUG("Found file (offset=0x%x, len=%d).\n",
 			    offset + file_offset, file_len);
-			media->unmap(media, file_name);
+			media->unmap(media, vardata);
 			file_ptr = media->map(media, offset,
 					      file_offset + file_len);
 			media->close(media);
 			return file_ptr;
 		} else {
 			DEBUG(" (unmatched file @0x%x: %s)\n", offset,
-			      file_name);
-			media->unmap(media, file_name);
+			      vardata);
+			media->unmap(media, vardata);
 		}
 
 		// Move to next file.


From gerrit at coreboot.org  Thu Sep 17 14:46:56 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 14:46:56 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: broadwell:
	Switch to using common ACPI _SWS code
References: <I3d2ceca8585314122b78317acb7f848efb6e9a14+0@gerrit.coreboot.org>
Message-ID: <E1ZcaSf-0005wL-0x@mail.coreboot.org>

the following patch was just integrated into master:
commit 81a4c85acf664156bb68807f681cd40928bf8267
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 8 16:10:30 2015 -0700

    broadwell: Switch to using common ACPI _SWS code
    
    Use the common ACPI _SWS code and provide a function to fill out
    the wake source data.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-samus coreboot
    
    Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d8afaee8e27222639c5e249d53be28cddcb78f72
    Original-Change-Id: Ie551ecf3397c304216046cc2046c071f7b766e5f
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/298168
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11647
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11647 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 14:55:58 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 14:55:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload: allow
	compression at file header level
References: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+0@gerrit.coreboot.org>
Message-ID: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+5@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10938

-gerrit

commit d7afb984d3dea362e0c2bfaf34578bbcca00f6c0
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: allow compression at file header level
    
    Decompression is handled transparently within cbfs_get_file_content:
    
    	const char *name = "foo.bmp";
    	void *dst = cbfs_get_file_content(media, name, type, NULL);
    
    To keep things consistent, a couple of API changes were necessary:
    - cbfs_get_file_content always returns a copy of the data, even for
      uncompressed files. It's the callers responsibility to free the
      memory.
    - same for cbfs_load_payload and cbfs_find_file.
    - cbfs_load_optionrom doesn't take a "dest" argument anymore but always
      returns a copy of the data, for compressed and uncompressed files.
      Like with cbfs_get_file_content, the caller is responsible to free it.
      It also decompresses based on extended file attributes instead of the
      cbfs_optionrom subheader that libpayload specified but that (AFAIK)
      nobody ever used, given that there's not even tooling for that.
    
    Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/cbfs.h      |  2 +-
 payloads/libpayload/include/cbfs_core.h | 18 ++++++++++++++--
 payloads/libpayload/libcbfs/cbfs.c      | 37 +++++++--------------------------
 payloads/libpayload/libcbfs/cbfs_core.c | 23 +++++++++++++++++++-
 4 files changed, 46 insertions(+), 34 deletions(-)

diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h
index 59c31db..f57dce0 100644
--- a/payloads/libpayload/include/cbfs.h
+++ b/payloads/libpayload/include/cbfs.h
@@ -59,7 +59,7 @@ void *cbfs_find_file(const char *name, int type);
 
 int cbfs_execute_stage(struct cbfs_media *media, const char *name);
 void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device, void * dest);
+			  uint16_t device);
 void *cbfs_load_payload(struct cbfs_media *media, const char *name);
 void *cbfs_load_stage(struct cbfs_media *media, const char *name);
 
diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index a2ee744..3878e55 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -53,6 +53,7 @@
 #include <endian.h>
 #include <stddef.h>
 #include <stdint.h>
+#include <stdlib.h>
 
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
@@ -141,6 +142,7 @@ struct cbfs_file {
  * 0xff. Support both. */
 #define CBFS_FILE_ATTR_TAG_UNUSED 0
 #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
 
 /* The common fields of extended cbfs file attributes.
    Attributes are expected to start with tag/len, then append their
@@ -152,6 +154,14 @@ struct cbfs_file_attribute {
 	uint8_t data[0];
 } __attribute__((packed));
 
+struct cbfs_file_attr_compression {
+	uint32_t tag;
+	uint32_t len;
+	/* whole file compression format. 0 if no compression. */
+	uint32_t compression;
+	uint32_t decompressed_size;
+} __attribute__((packed));
+
 /* Given a cbfs_file, return the first file attribute, or NULL. */
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
 
@@ -237,10 +247,14 @@ struct cbfs_media {
 	int (*close)(struct cbfs_media *media);
 };
 
-/* returns pointer to a file entry inside CBFS or NULL */
+/* returns pointer to a file entry inside CBFS or NULL on error */
 struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name);
 
-/* returns pointer to file content inside CBFS after if type is correct */
+/*
+ * Returns pointer to a copy of the file content or NULL on error.
+ * If the file is compressed, data will be decompressed.
+ * The caller owns the returned memory.
+ */
 void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 			    int type, size_t *sz);
 
diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
index 3e614b6..49e4941 100644
--- a/payloads/libpayload/libcbfs/cbfs.c
+++ b/payloads/libpayload/libcbfs/cbfs.c
@@ -79,41 +79,14 @@ static void tohex16(unsigned int val, char* dest)
 }
 
 void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device, void *dest)
+			  uint16_t device)
 {
 	char name[17] = "pciXXXX,XXXX.rom";
-	struct cbfs_optionrom *orom;
-	uint8_t *src;
 
 	tohex16(vendor, name+3);
 	tohex16(device, name+8);
 
-	orom = (struct cbfs_optionrom *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
-
-	if (orom == NULL)
-		return NULL;
-
-	/* They might have specified a dest address. If so, we can decompress.
-	 * If not, there's not much hope of decompressing or relocating the rom.
-	 * in the common case, the expansion rom is uncompressed, we
-	 * pass 0 in for the dest, and all we have to do is find the rom and
-	 * return a pointer to it.
-	 */
-
-	/* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */
-	src = (uint8_t*)orom; // + sizeof(struct cbfs_optionrom);
-
-	if (! dest)
-		return src;
-
-	if (!cbfs_decompress(ntohl(orom->compression),
-			     src,
-			     dest,
-			     ntohl(orom->len)))
-		return NULL;
-
-	return dest;
+	return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
 }
 
 void * cbfs_load_stage(struct cbfs_media *media, const char *name)
@@ -149,6 +122,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 	entry = stage->entry;
 	// entry = ntohll(stage->entry);
 
+	free(stage);
 	return (void *) entry;
 }
 
@@ -163,11 +137,14 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name)
 	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
 		LOG("Unable to run %s:  Compressed file"
 		       "Not supported for in-place execution\n", name);
+		free(stage);
 		return 1;
 	}
 
 	LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry));
-	return run_address((void *)(uintptr_t)ntohll(stage->entry));
+	int result = run_address((void *)(uintptr_t)ntohll(stage->entry));
+	free(stage);
+	return result;
 }
 
 void *cbfs_load_payload(struct cbfs_media *media, const char *name)
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 5541f02..36d310e 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -210,7 +210,28 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 	if (sz)
 		*sz = ntohl(file->len);
 
-	return (void *)CBFS_SUBHEADER(file);
+	void *file_content = (void *)CBFS_SUBHEADER(file);
+
+	struct cbfs_file_attribute *attr = cbfs_file_first_attr(file);
+	while (attr) {
+		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION)
+			break;
+		attr = cbfs_file_next_attr(file, attr);
+	}
+	int compression_algo = CBFS_COMPRESS_NONE;
+	if (attr) {
+		struct cbfs_file_attr_compression *comp =
+			(struct cbfs_file_attr_compression *)attr;
+		compression_algo = ntohl(comp->compression);
+		DEBUG("File '%s' is compressed (alg=%d)\n", compression_algo);
+		*sz = ntohl(comp->decompressed_size);
+	}
+	void *dst = malloc(*sz);
+	if (!cbfs_decompress(compression_algo, file_content, dst, *sz)) {
+		free(dst);
+		return NULL;
+	}
+	return dst;
 }
 
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file)


From gerrit at coreboot.org  Thu Sep 17 16:55:15 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 16:55:15 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: coreboot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+13@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit d6b9e1cd2de508902063e70df694d44e824208ff
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    coreboot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                                       |   4 +-
 src/arch/x86/include/arch/cbfs.h                   |   2 +-
 src/arch/x86/romcc_console.c                       |   2 +-
 src/commonlib/Makefile.inc                         |  10 +
 src/commonlib/include/commonlib/cbfs_serialized.h  | 190 ++++++++++
 src/commonlib/include/commonlib/cbmem_id.h         | 113 ++++++
 src/commonlib/include/commonlib/coreboot_tables.h  | 387 +++++++++++++++++++++
 src/commonlib/include/commonlib/fmap_serialized.h  |  73 ++++
 src/commonlib/include/commonlib/helpers.h          |  51 +++
 src/commonlib/include/commonlib/loglevel.h         | 178 ++++++++++
 src/commonlib/include/commonlib/mem_pool.h         |  73 ++++
 src/commonlib/include/commonlib/region.h           | 157 +++++++++
 src/commonlib/include/commonlib/rmodule-defs.h     |  63 ++++
 .../include/commonlib/timestamp_serialized.h       |  92 +++++
 src/commonlib/mem_pool.c                           |  51 +++
 src/commonlib/region.c                             | 196 +++++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |   2 +-
 src/include/assets.h                               |   2 +-
 src/include/boot/coreboot_tables.h                 | 384 +-------------------
 src/include/boot_device.h                          |   2 +-
 src/include/cbfs.h                                 |   4 +-
 src/include/cbfs_serialized.h                      | 190 ----------
 src/include/cbmem.h                                |   2 +-
 src/include/cbmem_id.h                             | 113 ------
 src/include/console/console.h                      |   2 +-
 src/include/console/early_print.h                  |   2 +-
 src/include/console/loglevel.h                     | 178 ----------
 src/include/fmap.h                                 |   4 +-
 src/include/fmap_serialized.h                      |  73 ----
 src/include/mem_pool.h                             |  73 ----
 src/include/region.h                               | 157 ---------
 src/include/rmodule-defs.h                         |  63 ----
 src/include/rmodule.h                              |   2 +-
 src/include/stddef.h                               |  34 +-
 src/include/stdlib.h                               |  14 -
 src/include/timestamp.h                            |  69 +---
 src/lib/Makefile.inc                               |   9 -
 src/lib/cbfs_boot_props.c                          |   2 +-
 src/lib/fmap.c                                     |   2 +-
 src/lib/mem_pool.c                                 |  51 ---
 src/lib/region.c                                   | 196 -----------
 src/mainboard/advansus/a785e-i/romstage.c          |   2 +-
 src/mainboard/amd/bimini_fam10/romstage.c          |   2 +-
 src/mainboard/amd/dinar/romstage.c                 |   2 +-
 src/mainboard/amd/inagua/romstage.c                |   2 +-
 src/mainboard/amd/lamar/romstage.c                 |   2 +-
 src/mainboard/amd/mahogany_fam10/romstage.c        |   2 +-
 src/mainboard/amd/olivehill/romstage.c             |   2 +-
 src/mainboard/amd/olivehillplus/romstage.c         |   2 +-
 src/mainboard/amd/parmer/romstage.c                |   2 +-
 src/mainboard/amd/persimmon/romstage.c             |   2 +-
 .../amd/serengeti_cheetah_fam10/romstage.c         |   2 +-
 src/mainboard/amd/south_station/romstage.c         |   2 +-
 src/mainboard/amd/thatcher/romstage.c              |   2 +-
 src/mainboard/amd/tilapia_fam10/romstage.c         |   2 +-
 src/mainboard/amd/torpedo/romstage.c               |   2 +-
 src/mainboard/amd/union_station/romstage.c         |   2 +-
 src/mainboard/asrock/e350m1/romstage.c             |   2 +-
 src/mainboard/asrock/imb-a180/romstage.c           |   2 +-
 src/mainboard/asus/m4a78-em/romstage.c             |   2 +-
 src/mainboard/asus/m4a785-m/romstage.c             |   2 +-
 src/mainboard/asus/m5a88-v/romstage.c              |   2 +-
 src/mainboard/avalue/eax-785e/romstage.c           |   2 +-
 src/mainboard/bap/ode_e20XX/romstage.c             |   2 +-
 src/mainboard/biostar/am1ml/romstage.c             |   2 +-
 src/mainboard/gigabyte/ma785gm/romstage.c          |   2 +-
 src/mainboard/gigabyte/ma785gmt/romstage.c         |   2 +-
 src/mainboard/gigabyte/ma78gm/romstage.c           |   2 +-
 src/mainboard/gizmosphere/gizmo/romstage.c         |   2 +-
 src/mainboard/gizmosphere/gizmo2/romstage.c        |   2 +-
 src/mainboard/google/peach_pit/romstage.c          |   2 +-
 src/mainboard/hp/abm/romstage.c                    |   2 +-
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |   2 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |   2 +-
 src/mainboard/jetway/pa78vm5/romstage.c            |   2 +-
 src/mainboard/lippert/frontrunner-af/romstage.c    |   2 +-
 src/mainboard/lippert/toucan-af/romstage.c         |   2 +-
 src/mainboard/pcengines/apu1/romstage.c            |   2 +-
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |   2 +-
 src/soc/intel/broadwell/include/soc/me.h           |   2 +-
 src/southbridge/amd/cimx/sb700/Platform.h          |   2 +-
 src/southbridge/amd/cimx/sb700/early.c             |   2 +-
 src/southbridge/amd/cimx/sb900/early.c             |   2 +-
 src/vendorcode/amd/agesa/common/Porting.h          |   2 +-
 src/vendorcode/amd/pi/00630F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c    |   2 +-
 src/vendorcode/amd/pi/00730F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/Makefile.inc                 |   1 +
 src/vendorcode/google/chromeos/vboot_common.h      |   2 +-
 util/cbfstool/Makefile.inc                         |   1 +
 util/cbfstool/rmodule.c                            |   2 +-
 util/cbmem/Makefile                                |   2 +-
 util/cbmem/cbmem.c                                 |   9 +-
 94 files changed, 1710 insertions(+), 1673 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 46d6eb2..81c149d 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
 #ifndef __INCLUDE_ARCH_CBFS__
 #define __INCLUDE_ARCH_CBFS__
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
 #include <endian.h>
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
 #include <build.h>
 #include <console/streams.h>
 #include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* Include the sources. */
 #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_PAYLOAD    0x20
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+	uint32_t compression;  /** Compression type */
+	uint64_t entry;  /** entry point */
+	uint64_t load;   /** Where to load in memory */
+	uint32_t len;          /** length of data to load */
+	uint32_t memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image.  Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing.   For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed.  This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ *   a particular motherboard is constructed? (Assuming the kernel
+ *   has drivers for all of the hardware but it does not have
+ *   assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not.  This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped.  Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+	uint64_t result;
+	result = value.hi;
+	result = (result << 32) + value.lo;
+	return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+	struct lb_uint64 result;
+	result.lo = (value >> 0) & 0xffffffff;
+	result.hi = (value >> 32) & 0xffffffff;
+	return result;
+}
+
+struct lb_header
+{
+	uint8_t  signature[4]; /* LBIO */
+	uint32_t header_bytes;
+	uint32_t header_checksum;
+	uint32_t table_bytes;
+	uint32_t table_checksum;
+	uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record.  Encoding both type and size.  The type is obviously
+ * so you can tell what it is.  The size allows you to skip that
+ * boot environment record if you don't know what it is.  This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+	uint32_t tag;		/* tag ID */
+	uint32_t size;		/* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED		0x0000
+
+#define LB_TAG_MEMORY		0x0001
+
+struct lb_memory_range {
+	struct lb_uint64 start;
+	struct lb_uint64 size;
+	uint32_t type;
+#define LB_MEM_RAM		 1	/* Memory anyone can use */
+#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
+#define LB_MEM_ACPI		 3	/* ACPI Tables */
+#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
+#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
+#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+	uint32_t tag;
+	uint32_t size;
+	struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB		0x0002
+struct lb_hwrpb {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
+#define LB_TAG_VERSION		0x0004
+#define LB_TAG_EXTRA_VERSION	0x0005
+#define LB_TAG_BUILD		0x0006
+#define LB_TAG_COMPILE_TIME	0x0007
+#define LB_TAG_COMPILE_BY	0x0008
+#define LB_TAG_COMPILE_HOST	0x0009
+#define LB_TAG_COMPILE_DOMAIN	0x000a
+#define LB_TAG_COMPILER		0x000b
+#define LB_TAG_LINKER		0x000c
+#define LB_TAG_ASSEMBLER	0x000d
+struct lb_string {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP	0x0026
+struct lb_timestamp {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL		0x000f
+struct lb_serial {
+	uint32_t tag;
+	uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
+	uint32_t baud;
+	uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE		0x0010
+struct lb_console {
+	uint32_t tag;
+	uint32_t size;
+	uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250	0
+#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI		5
+#define LB_TAG_CONSOLE_SERIAL8250MEM	6
+
+#define LB_TAG_FORWARD		0x0011
+struct lb_forward {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER	0x0012
+struct lb_framebuffer {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t physical_address;
+	uint32_t x_resolution;
+	uint32_t y_resolution;
+	uint32_t bytes_per_line;
+	uint8_t bits_per_pixel;
+	uint8_t red_mask_pos;
+	uint8_t red_mask_size;
+	uint8_t green_mask_pos;
+	uint8_t green_mask_size;
+	uint8_t blue_mask_pos;
+	uint8_t blue_mask_size;
+	uint8_t reserved_mask_pos;
+	uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT		0x0015
+#define LB_TAG_VBNV		0x0019
+#define LB_TAB_VBOOT_HANDOFF	0x0020
+#define LB_TAB_DMA		0x0022
+#define LB_TAG_RAM_OOPS		0x0023
+#define LB_TAG_MTC		0x002b
+struct lb_range {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t range_start;
+	uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+#define LB_TAG_ACPI_GNVS	0x0024
+#define LB_TAG_WIFI_CALIBRATION	0x0027
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR	0x0021
+struct lb_x86_rom_mtrr {
+	uint32_t tag;
+	uint32_t size;
+	/* The variable range MTRR index covering the ROM. */
+	uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID		0x0025
+struct lb_board_id {
+	uint32_t tag;
+	uint32_t size;
+	/* Board ID as retrieved from the board revision GPIOs. */
+	uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS	0x0026
+struct mac_address {
+	uint8_t mac_addr[6];
+	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t count;
+	struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE		0x0028
+struct lb_ram_code {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH	0x0029
+struct lb_spi_flash {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t flash_size;
+	uint32_t sector_size;
+	uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+	uint32_t tag;
+	uint32_t size;
+	/* offsets are relative to start of boot media */
+	uint64_t fmap_offset;
+	uint64_t cbfs_offset;
+	uint64_t cbfs_size;
+	uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO		0x002a
+#define MAX_SERIALNO_LENGTH	32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+	uint32_t tag;               /* CMOS definitions table type */
+	uint32_t size;               /* size of the entire table */
+	uint32_t header_length;      /* length of header */
+};
+
+/* cmos entry record
+        This record is variable length.  The name field may be
+        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+        anywhere in the byte, but can not span bytes unless it
+        starts at the beginning of the byte and the length is
+        fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+	uint32_t tag;                /* entry type */
+	uint32_t size;               /* length of this record */
+	uint32_t bit;                /* starting bit from start of image */
+	uint32_t length;             /* length of field in bits */
+	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
+	uint32_t config_id;          /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+					       variable length int aligned */
+};
+
+
+/* cmos enumerations record
+        This record is variable length.  The text field may be
+        shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+	uint32_t tag;		     /* enumeration type */
+	uint32_t size; 		     /* length of this record */
+	uint32_t config_id;          /* a number identifying the config id */
+	uint32_t value;              /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+						variable length int aligned */
+};
+
+/* cmos defaults record
+        This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+	uint32_t tag;                /* default type */
+	uint32_t size;               /* length of this record */
+	uint32_t name_length;        /* length of the following name field */
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct	cmos_checksum {
+	uint32_t tag;
+	uint32_t size;
+	/* In practice everything is byte aligned, but things are measured
+	 * in bits to be consistent.
+	 */
+	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
+	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
+	uint32_t location;	/* First bit of the checksum (byte aligned) */
+	uint32_t type;		/* Checksum algorithm that is used */
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __attribute__((packed));
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint16_t	max_entries;
+	uint16_t	tick_freq_mhz;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_VBOOT = 5,
+	TS_END_VBOOT = 6,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_START_BOOTBLOCK = 11,
+	TS_END_BOOTBLOCK = 12,
+	TS_START_COPYROM = 13,
+	TS_END_COPYROM = 14,
+	TS_START_ULZMA = 15,
+	TS_END_ULZMA = 16,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+
+	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+	TS_START_COPYVER = 501,
+	TS_END_COPYVER = 502,
+	TS_START_TPMINIT = 503,
+	TS_END_TPMINIT = 504,
+	TS_START_VERIFY_SLOT = 505,
+	TS_END_VERIFY_SLOT = 506,
+	TS_START_HASH_BODY = 507,
+	TS_DONE_LOADING = 508,
+	TS_DONE_HASHING = 509,
+	TS_END_HASH_BODY = 510,
+
+	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+	TS_FSP_MEMORY_INIT_START = 950,
+	TS_FSP_MEMORY_INIT_END = 951,
+	TS_FSP_TEMP_RAM_EXIT_START = 952,
+	TS_FSP_TEMP_RAM_EXIT_END = 953,
+	TS_FSP_SILICON_INIT_START = 954,
+	TS_FSP_SILICON_INIT_END = 955,
+	TS_FSP_BEFORE_ENUMERATE = 956,
+	TS_FSP_AFTER_ENUMERATE = 957,
+	TS_FSP_BEFORE_FINALIZE = 958,
+	TS_FSP_AFTER_FINALIZE = 959,
+
+	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 041c0f1..79c348a 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
 #include <fsp/soc_binding.h>
 #include <fsp/gop.h>
 #include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
 #ifndef ASSETS_H
 #define ASSETS_H
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* An asset represents data used to boot the system. It can be found within
  * CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
 #ifndef COREBOOT_TABLES_H
 #define COREBOOT_TABLES_H
 
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image.  Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing.   For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed.  This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- *   a particular motherboard is constructed? (Assuming the kernel
- *   has drivers for all of the hardware but it does not have
- *   assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not.  This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped.  Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
-	uint32_t lo;
-	uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
-	uint64_t result;
-	result = value.hi;
-	result = (result << 32) + value.lo;
-	return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
-	struct lb_uint64 result;
-	result.lo = (value >> 0) & 0xffffffff;
-	result.hi = (value >> 32) & 0xffffffff;
-	return result;
-}
-
-struct lb_header
-{
-	uint8_t  signature[4]; /* LBIO */
-	uint32_t header_bytes;
-	uint32_t header_checksum;
-	uint32_t table_bytes;
-	uint32_t table_checksum;
-	uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record.  Encoding both type and size.  The type is obviously
- * so you can tell what it is.  The size allows you to skip that
- * boot environment record if you don't know what it is.  This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
-	uint32_t tag;		/* tag ID */
-	uint32_t size;		/* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED		0x0000
-
-#define LB_TAG_MEMORY		0x0001
-
-struct lb_memory_range {
-	struct lb_uint64 start;
-	struct lb_uint64 size;
-	uint32_t type;
-#define LB_MEM_RAM		 1	/* Memory anyone can use */
-#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
-#define LB_MEM_ACPI		 3	/* ACPI Tables */
-#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
-#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
-#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
-	uint32_t tag;
-	uint32_t size;
-	struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB		0x0002
-struct lb_hwrpb {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD	0x0003
-struct lb_mainboard {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  vendor_idx;
-	uint8_t  part_number_idx;
-	uint8_t  strings[0];
-};
-
-#define LB_TAG_VERSION		0x0004
-#define LB_TAG_EXTRA_VERSION	0x0005
-#define LB_TAG_BUILD		0x0006
-#define LB_TAG_COMPILE_TIME	0x0007
-#define LB_TAG_COMPILE_BY	0x0008
-#define LB_TAG_COMPILE_HOST	0x0009
-#define LB_TAG_COMPILE_DOMAIN	0x000a
-#define LB_TAG_COMPILER		0x000b
-#define LB_TAG_LINKER		0x000c
-#define LB_TAG_ASSEMBLER	0x000d
-struct lb_string {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP	0x0026
-struct lb_timestamp {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL		0x000f
-struct lb_serial {
-	uint32_t tag;
-	uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED     1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
-	uint32_t type;
-	uint32_t baseaddr;
-	uint32_t baud;
-	uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE		0x0010
-struct lb_console {
-	uint32_t tag;
-	uint32_t size;
-	uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250	0
-#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI		5
-#define LB_TAG_CONSOLE_SERIAL8250MEM	6
-
-#define LB_TAG_FORWARD		0x0011
-struct lb_forward {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER	0x0012
-struct lb_framebuffer {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t physical_address;
-	uint32_t x_resolution;
-	uint32_t y_resolution;
-	uint32_t bytes_per_line;
-	uint8_t bits_per_pixel;
-	uint8_t red_mask_pos;
-	uint8_t red_mask_size;
-	uint8_t green_mask_pos;
-	uint8_t green_mask_size;
-	uint8_t blue_mask_pos;
-	uint8_t blue_mask_size;
-	uint8_t reserved_mask_pos;
-	uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO	0x0013
-
-struct lb_gpio {
-	uint32_t port;
-	uint32_t polarity;
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-	uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
-        uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
-	uint32_t tag;
-	uint32_t size;
-
-	uint32_t count;
-	struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT		0x0015
-#define LB_TAG_VBNV		0x0019
-#define LB_TAB_VBOOT_HANDOFF	0x0020
-#define LB_TAB_DMA		0x0022
-#define LB_TAG_RAM_OOPS		0x0023
-#define LB_TAG_MTC		0x002b
-struct lb_range {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t range_start;
-	uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS	0x0016
-#define LB_TAG_CBMEM_CONSOLE	0x0017
-#define LB_TAG_MRC_CACHE	0x0018
-#define LB_TAG_ACPI_GNVS	0x0024
-#define LB_TAG_WIFI_CALIBRATION	0x0027
-struct lb_cbmem_ref {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR	0x0021
-struct lb_x86_rom_mtrr {
-	uint32_t tag;
-	uint32_t size;
-	/* The variable range MTRR index covering the ROM. */
-	uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID		0x0025
-struct lb_board_id {
-	uint32_t tag;
-	uint32_t size;
-	/* Board ID as retrieved from the board revision GPIOs. */
-	uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS	0x0026
-struct mac_address {
-	uint8_t mac_addr[6];
-	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t count;
-	struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE		0x0028
-struct lb_ram_code {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH	0x0029
-struct lb_spi_flash {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t flash_size;
-	uint32_t sector_size;
-	uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
-	uint32_t tag;
-	uint32_t size;
-	/* offsets are relative to start of boot media */
-	uint64_t fmap_offset;
-	uint64_t cbfs_offset;
-	uint64_t cbfs_size;
-	uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO		0x002a
-#define MAX_SERIALNO_LENGTH	32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
-	uint32_t tag;               /* CMOS definitions table type */
-	uint32_t size;               /* size of the entire table */
-	uint32_t header_length;      /* length of header */
-};
-
-/* cmos entry record
-        This record is variable length.  The name field may be
-        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
-        anywhere in the byte, but can not span bytes unless it
-        starts at the beginning of the byte and the length is
-        fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
-	uint32_t tag;                /* entry type */
-	uint32_t size;               /* length of this record */
-	uint32_t bit;                /* starting bit from start of image */
-	uint32_t length;             /* length of field in bits */
-	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
-	uint32_t config_id;          /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
-					       variable length int aligned */
-};
-
-
-/* cmos enumerations record
-        This record is variable length.  The text field may be
-        shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
-	uint32_t tag;		     /* enumeration type */
-	uint32_t size; 		     /* length of this record */
-	uint32_t config_id;          /* a number identifying the config id */
-	uint32_t value;              /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
-	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
-						variable length int aligned */
-};
-
-/* cmos defaults record
-        This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
-	uint32_t tag;                /* default type */
-	uint32_t size;               /* length of this record */
-	uint32_t name_length;        /* length of the following name field */
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
-	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct	cmos_checksum {
-	uint32_t tag;
-	uint32_t size;
-	/* In practice everything is byte aligned, but things are measured
-	 * in bits to be consistent.
-	 */
-	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
-	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
-	uint32_t location;	/* First bit of the checksum (byte aligned) */
-	uint32_t type;		/* Checksum algorithm that is used */
-#define CHECKSUM_NONE	0
-#define CHECKSUM_PCBIOS	1
-};
-
+#include <commonlib/coreboot_tables.h>
 /* function prototypes for building the coreboot table */
 
 unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
 #ifndef _BOOT_DEVICE_H_
 #define _BOOT_DEVICE_H_
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* Return the region_device for the read-only boot device. */
 const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
 #include <program_loading.h>
-#include <region.h>
 
 /*
  * CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
-    algorithms that coreboot knows about for stages and
-    payloads.  Of course, other CBFS users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE      0x10
-#define CBFS_TYPE_PAYLOAD    0x20
-#define CBFS_TYPE_OPTIONROM  0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW        0x50
-#define CBFS_TYPE_VSA        0x51
-#define CBFS_TYPE_MBI        0x52
-#define CBFS_TYPE_MICROCODE  0x53
-#define CBFS_TYPE_FSP        0x60
-#define CBFS_TYPE_MRC        0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD          0xab
-#define CBFS_TYPE_MRC_CACHE    0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
-	uint32_t magic;
-	uint32_t version;
-	uint32_t romsize;
-	uint32_t bootblocksize;
-	uint32_t align; /* fixed to 64 bytes */
-	uint32_t offset;
-	uint32_t architecture;
-	uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARM      0x00000010
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	uint32_t len;
-	uint32_t type;
-	uint32_t checksum;
-	uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	uint32_t compression;  /** Compression type */
-	uint64_t entry;  /** entry point */
-	uint64_t load;   /** Where to load in memory */
-	uint32_t len;          /** length of data to load */
-	uint32_t memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	uint32_t type;
-	uint32_t compression;
-	uint32_t offset;
-	uint64_t load_addr;
-	uint32_t len;
-	uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	uint32_t compression;
-	uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
 #include <rules.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <rules.h>
 #include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef __ROMCC__
 struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
 
 #include <console/console.h>
 #include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* While in romstage, console loglevel is built-time constant.
  * With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
 #ifndef _FMAP_H_
 #define _FMAP_H_
 
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
 
 /* Locate the fmap directory. Return 0 on success, < 0 on error. */
 int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *    * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE		"__FMAP__"
-#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
-#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
-#define FMAP_STRLEN		32	/* maximum length for strings, */
-					/* including null-terminator */
-
-enum fmap_flags {
-	FMAP_AREA_STATIC	= 1 << 0,
-	FMAP_AREA_COMPRESSED	= 1 << 1,
-	FMAP_AREA_RO		= 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
-	uint32_t offset;                /* offset relative to base */
-	uint32_t size;                  /* size in bytes */
-	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
-	uint16_t flags;                 /* flags for this area */
-}  __attribute__((packed));
-
-struct fmap {
-	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
-	uint8_t  ver_major;		/* major version */
-	uint8_t  ver_minor;		/* minor version */
-	uint64_t base;			/* address of the firmware binary */
-	uint32_t size;			/* size of firmware binary in bytes */
-	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
-	uint16_t nareas;		/* number of areas described by
-					   fmap_areas[] below */
-	struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
 
 enum {
 	RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <commonlib/helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
 
 #include <stddef.h>
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a)           ALIGN((x),(a))
-#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-
 #define min(a,b) MIN((a),(b))
 #define max(a,b) MAX((a),(b))
 
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
 #ifndef __TIMESTAMP_H__
 #define __TIMESTAMP_H__
 
-#include <stdint.h>
-
-struct timestamp_entry {
-	uint32_t	entry_id;
-	uint64_t	entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
-	uint64_t	base_time;
-	uint16_t	max_entries;
-	uint16_t	tick_freq_mhz;
-	uint32_t	num_entries;
-	struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
-	TS_START_ROMSTAGE = 1,
-	TS_BEFORE_INITRAM = 2,
-	TS_AFTER_INITRAM = 3,
-	TS_END_ROMSTAGE = 4,
-	TS_START_VBOOT = 5,
-	TS_END_VBOOT = 6,
-	TS_START_COPYRAM = 8,
-	TS_END_COPYRAM = 9,
-	TS_START_RAMSTAGE = 10,
-	TS_START_BOOTBLOCK = 11,
-	TS_END_BOOTBLOCK = 12,
-	TS_START_COPYROM = 13,
-	TS_END_COPYROM = 14,
-	TS_START_ULZMA = 15,
-	TS_END_ULZMA = 16,
-	TS_DEVICE_ENUMERATE = 30,
-	TS_DEVICE_CONFIGURE = 40,
-	TS_DEVICE_ENABLE = 50,
-	TS_DEVICE_INITIALIZE = 60,
-	TS_DEVICE_DONE = 70,
-	TS_CBMEM_POST = 75,
-	TS_WRITE_TABLES = 80,
-	TS_LOAD_PAYLOAD = 90,
-	TS_ACPI_WAKE_JUMP = 98,
-	TS_SELFBOOT_JUMP = 99,
-
-	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
-	TS_START_COPYVER = 501,
-	TS_END_COPYVER = 502,
-	TS_START_TPMINIT = 503,
-	TS_END_TPMINIT = 504,
-	TS_START_VERIFY_SLOT = 505,
-	TS_END_VERIFY_SLOT = 506,
-	TS_START_HASH_BODY = 507,
-	TS_DONE_LOADING = 508,
-	TS_DONE_HASHING = 509,
-	TS_END_HASH_BODY = 510,
-
-	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
-	TS_FSP_MEMORY_INIT_START = 950,
-	TS_FSP_MEMORY_INIT_END = 951,
-	TS_FSP_TEMP_RAM_EXIT_START = 952,
-	TS_FSP_TEMP_RAM_EXIT_END = 953,
-	TS_FSP_SILICON_INIT_START = 954,
-	TS_FSP_SILICON_INIT_END = 955,
-	TS_FSP_BEFORE_ENUMERATE = 956,
-	TS_FSP_AFTER_ENUMERATE = 957,
-	TS_FSP_BEFORE_FINALIZE = 958,
-	TS_FSP_AFTER_FINALIZE = 959,
-
-	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
 
 #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
 /*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* This function is marked as weak to allow a particular platform to
  * override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
 #include <stddef.h>
 #include <string.h>
 
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
 #include <spd.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <commonlib/region.h>
 #include <console/console.h>
 #include <device/i2c.h>
 #include <drivers/maxim/max77802/max77802.h>
 #include <program_loading.h>
-#include <region.h>
 #include <soc/clk.h>
 #include <soc/cpu.h>
 #include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
 #define ME_DELAY		10	/* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
 
 #include <cpu/amd/common/cbtypes.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #ifdef NULL
 #undef NULL
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
 #include "sb_cimx.h"
 #include "sb700_cfg.h"                /*sb700_cimx_config*/
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
 #include "SbPlatform.h"
 #include "sb_cimx.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
 #include "amdlib.h"
 #include "cbfs.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 // TODO Add a kconfig option to name the AGESA ROM file in CBFS
 #define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
 #include <assert.h>
 #include <config.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
 #define VBOOT_COMMON_H
 
 #include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* The FW areas consist of multiple components. At the beginning of
  * each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 2a3dedf..0938ea9 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -50,6 +50,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
 
 /*
  * Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
 #include <sys/mman.h>
 #include <libgen.h>
 #include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
 
 #ifdef __OpenBSD__
 #include <sys/param.h>
@@ -42,18 +45,12 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
 
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
-#include "timestamp.h"
-
 #define CBMEM_VERSION "1.1"
 
 /* verbose output? */


From gerrit at coreboot.org  Thu Sep 17 16:55:16 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 16:55:16 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: commonlib: add
	endian related accessor functions
References: <If44c4d489f0dab86a73b73580c039e364c7e517d+0@gerrit.coreboot.org>
Message-ID: <If44c4d489f0dab86a73b73580c039e364c7e517d+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11677

-gerrit

commit fdfb2b0b39caae446424ea63a00036f85a832eb6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 11:24:08 2015 -0500

    commonlib: add endian related accessor functions
    
    This commit adds read/write functions for both big and
    little endian interpretations. Additionally there are
    variants that allow an offse to be provided into the
    source buffer.
    
    Along with this commit is a change to the cbfs locating
    code to use the new API.
    
    BUG=None
    TEST=Wrote test harness for functions.  Also booted ARM QEMU
         through end of payload.
    
    Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/include/arch/cbfs.h                  |   4 +-
 src/commonlib/include/commonlib/cbfs_serialized.h |   2 +-
 src/commonlib/include/commonlib/endian.h          | 261 ++++++++++++++++++++++
 src/cpu/intel/microcode/microcode.c               |   2 +-
 src/lib/cbfs.c                                    |  38 +++-
 5 files changed, 296 insertions(+), 11 deletions(-)

diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index 195c06f..ff45edb 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -25,7 +25,7 @@
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
 
-static struct cbfs_file *walkcbfs_head(char *target)
+static struct cbfs_file_serialized *walkcbfs_head(char *target)
 {
 	void *entry;
 	asm volatile (
@@ -37,7 +37,7 @@ static struct cbfs_file *walkcbfs_head(char *target)
 
 static void *walkcbfs(char *target)
 {
-	struct cbfs_file *head = walkcbfs_head(target);
+	struct cbfs_file_serialized *head = walkcbfs_head(target);
 	if ((u32)head != 0)
 		return CBFS_SUBHEADER(head);
 
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
index f672095..c655fc1 100644
--- a/src/commonlib/include/commonlib/cbfs_serialized.h
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -128,7 +128,7 @@ struct cbfs_header {
 
 #define CBFS_FILE_MAGIC "LARCHIVE"
 
-struct cbfs_file {
+struct cbfs_file_serialized {
 	char magic[8];
 	uint32_t len;
 	uint32_t type;
diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h
new file mode 100644
index 0000000..bcd3b39
--- /dev/null
+++ b/src/commonlib/include/commonlib/endian.h
@@ -0,0 +1,261 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _COMMONLIB_ENDIAN_H_
+#define _COMMONLIB_ENDIAN_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* Endian agnostic functions working on single byte. */
+
+static inline uint8_t read_ble8(const void *src)
+{
+	const uint8_t *s = src;
+	return *s;
+}
+
+static inline uint8_t read_at_ble8(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_ble8(s);
+}
+
+static inline void write_ble8(void *dest, uint8_t val)
+{
+	*(uint8_t *)dest = val;
+}
+
+static inline void write_at_ble8(void *dest, uint8_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_ble8(d, val);
+}
+
+/* Big Endian functions. */
+
+static inline uint8_t read_be8(const void *src)
+{
+	return read_ble8(src);
+}
+
+static inline uint8_t read_at_be8(const void *src, size_t offset)
+{
+	return read_at_ble8(src, offset);
+}
+
+static inline void write_be8(void *dest, uint8_t val)
+{
+	write_ble8(dest, val);
+}
+
+static inline void write_at_be8(void *dest, uint8_t val, size_t offset)
+{
+	write_at_ble8(dest, val, offset);
+}
+
+static inline uint16_t read_be16(const void *src)
+{
+	const uint8_t *s = src;
+	return (((uint16_t)s[0]) << 8) | (((uint16_t)s[1]) << 0);
+}
+
+static inline uint16_t read_at_be16(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_be16(s);
+}
+
+static inline void write_be16(void *dest, uint16_t val)
+{
+	write_be8(dest, val >> 8);
+	write_at_be8(dest, val >> 0, sizeof(uint8_t));
+}
+
+static inline void write_at_be16(void *dest, uint16_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_be16(d, val);
+}
+
+static inline uint32_t read_be32(const void *src)
+{
+	const uint8_t *s = src;
+	return (((uint32_t)s[0]) << 24) | (((uint32_t)s[1]) << 16) |
+		(((uint32_t)s[2]) << 8) | (((uint32_t)s[3]) << 0);
+}
+
+static inline uint32_t read_at_be32(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_be32(s);
+}
+
+static inline void write_be32(void *dest, uint32_t val)
+{
+	write_be16(dest, val >> 16);
+	write_at_be16(dest, val >> 0, sizeof(uint16_t));
+}
+
+static inline void write_at_be32(void *dest, uint32_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_be32(d, val);
+}
+
+static inline uint64_t read_be64(const void *src)
+{
+	uint64_t val;
+	val = read_be32(src);
+	val <<= 32;
+	val |= read_at_be32(src, sizeof(uint32_t));
+	return val;
+}
+
+static inline uint64_t read_at_be64(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_be64(s);
+}
+
+static inline void write_be64(void *dest, uint64_t val)
+{
+	write_be32(dest, val >> 32);
+	write_at_be32(dest, val >> 0, sizeof(uint32_t));
+}
+
+static inline void write_at_be64(void *dest, uint64_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_be64(d, val);
+}
+
+/* Little Endian functions. */
+
+static inline uint8_t read_le8(const void *src)
+{
+	return read_ble8(src);
+}
+
+static inline uint8_t read_at_le8(const void *src, size_t offset)
+{
+	return read_at_ble8(src, offset);
+}
+
+static inline void write_le8(void *dest, uint8_t val)
+{
+	write_ble8(dest, val);
+}
+
+static inline void write_at_le8(void *dest, uint8_t val, size_t offset)
+{
+	write_at_ble8(dest, val, offset);
+}
+
+static inline uint16_t read_le16(const void *src)
+{
+	const uint8_t *s = src;
+	return (((uint16_t)s[1]) << 8) | (((uint16_t)s[0]) << 0);
+}
+
+static inline uint16_t read_at_le16(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_le16(s);
+}
+
+static inline void write_le16(void *dest, uint16_t val)
+{
+	write_le8(dest, val >> 0);
+	write_at_le8(dest, val >> 8, sizeof(uint8_t));
+}
+
+static inline void write_at_le16(void *dest, uint16_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_le16(d, val);
+}
+
+static inline uint32_t read_le32(const void *src)
+{
+	const uint8_t *s = src;
+	return (((uint32_t)s[3]) << 24) | (((uint32_t)s[2]) << 16) |
+		(((uint32_t)s[1]) << 8) | (((uint32_t)s[0]) << 0);
+}
+
+static inline uint32_t read_at_le32(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_le32(s);
+}
+
+static inline void write_le32(void *dest, uint32_t val)
+{
+	write_le16(dest, val >> 0);
+	write_at_le16(dest, val >> 16, sizeof(uint16_t));
+}
+
+static inline void write_at_le32(void *dest, uint32_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_le32(d, val);
+}
+
+static inline uint64_t read_le64(const void *src)
+{
+	uint64_t val;
+	val = read_at_le32(src, sizeof(uint32_t));
+	val <<= 32;
+	val |= read_le32(src);
+	return val;
+}
+
+static inline uint64_t read_at_le64(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_le64(s);
+}
+
+static inline void write_le64(void *dest, uint64_t val)
+{
+	write_le32(dest, val >> 0);
+	write_at_le32(dest, val >> 32, sizeof(uint32_t));
+}
+
+static inline void write_at_le64(void *dest, uint64_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_le64(d, val);
+}
+
+#endif
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 8791a2e..1cee30f 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -126,7 +126,7 @@ const void *intel_microcode_find(void)
 	msr_t msr;
 
 #ifdef __PRE_RAM__
-	struct cbfs_file *microcode_file;
+	struct cbfs_file_serialized *microcode_file;
 
 	microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE);
 	if (!microcode_file)
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index abc4077..c4eff5b 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -23,7 +23,7 @@
 #include <stdlib.h>
 #include <boot_device.h>
 #include <cbfs.h>
-#include <endian.h>
+#include <commonlib/endian.h>
 #include <lib.h>
 #include <symbols.h>
 
@@ -35,6 +35,30 @@
 #define DEBUG(x...)
 #endif
 
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+};
+
+static void cbfs_file_deserialize(struct cbfs_file *f, void *from)
+{
+	size_t off;
+
+	off = 0;
+	memcpy(&f->magic, from, sizeof(f->magic));
+	off += sizeof(f->magic);
+	f->len = read_at_be32(from, off);
+	off += sizeof(f->len);
+	f->type = read_at_be32(from, off);
+	off += sizeof(f->type);
+	f->checksum = read_at_be32(from, off);
+	off += sizeof(f->checksum);
+	f->offset = read_at_be32(from, off);
+}
+
 int cbfs_boot_locate(struct region_device *fh, const char *name, uint32_t *type)
 {
 	struct cbfsd cbfs;
@@ -91,16 +115,20 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 	/* Try to scan the entire cbfs region looking for file name. */
 	while (1) {
 		struct cbfs_file file;
-		const size_t fsz = sizeof(file);
+		const size_t fsz = sizeof(struct cbfs_file_serialized);
 		char *fname;
 		int name_match;
 		size_t datasz;
+		void *mapping;
 
 		DEBUG("Checking offset %zx\n", offset);
 
+		mapping = rdev_mmap(rd, offset, fsz);
 		/* Can't read file. Nothing else to do but bail out. */
-		if (rdev_readat(rd, &file, offset, fsz) != fsz)
+		if (mapping == NULL)
 			break;
+		cbfs_file_deserialize(&file, mapping);
+		rdev_munmap(rd, mapping);
 
 		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
 			offset++;
@@ -108,10 +136,6 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 			continue;
 		}
 
-		file.len = ntohl(file.len);
-		file.type = ntohl(file.type);
-		file.offset = ntohl(file.offset);
-
 		/* See if names match. */
 		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
 


From gerrit at coreboot.org  Thu Sep 17 18:02:24 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 18:02:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload: allow
	compression at file header level
References: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+0@gerrit.coreboot.org>
Message-ID: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+6@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10938

-gerrit

commit 4f1d71cc863902a82363cc0d57d79301c13beede
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: allow compression at file header level
    
    Decompression is handled transparently within cbfs_get_file_content:
    
    	const char *name = "foo.bmp";
    	void *dst = cbfs_get_file_content(media, name, type, NULL);
    
    To keep things consistent, a couple of API changes were necessary:
    - cbfs_get_file_content always returns a copy of the data, even for
      uncompressed files. It's the callers responsibility to free the
      memory.
    - same for cbfs_load_payload and cbfs_find_file.
    - cbfs_load_optionrom doesn't take a "dest" argument anymore but always
      returns a copy of the data, for compressed and uncompressed files.
      Like with cbfs_get_file_content, the caller is responsible to free it.
      It also decompresses based on extended file attributes instead of the
      cbfs_optionrom subheader that libpayload specified but that (AFAIK)
      nobody ever used, given that there's not even tooling for that.
    
    Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/cbfs.h      |  2 +-
 payloads/libpayload/include/cbfs_core.h | 18 ++++++++++++++--
 payloads/libpayload/libcbfs/cbfs.c      | 37 +++++++--------------------------
 payloads/libpayload/libcbfs/cbfs_core.c | 33 ++++++++++++++++++++++++++++-
 4 files changed, 56 insertions(+), 34 deletions(-)

diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h
index 59c31db..f57dce0 100644
--- a/payloads/libpayload/include/cbfs.h
+++ b/payloads/libpayload/include/cbfs.h
@@ -59,7 +59,7 @@ void *cbfs_find_file(const char *name, int type);
 
 int cbfs_execute_stage(struct cbfs_media *media, const char *name);
 void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device, void * dest);
+			  uint16_t device);
 void *cbfs_load_payload(struct cbfs_media *media, const char *name);
 void *cbfs_load_stage(struct cbfs_media *media, const char *name);
 
diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index a2ee744..3878e55 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -53,6 +53,7 @@
 #include <endian.h>
 #include <stddef.h>
 #include <stdint.h>
+#include <stdlib.h>
 
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
@@ -141,6 +142,7 @@ struct cbfs_file {
  * 0xff. Support both. */
 #define CBFS_FILE_ATTR_TAG_UNUSED 0
 #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
 
 /* The common fields of extended cbfs file attributes.
    Attributes are expected to start with tag/len, then append their
@@ -152,6 +154,14 @@ struct cbfs_file_attribute {
 	uint8_t data[0];
 } __attribute__((packed));
 
+struct cbfs_file_attr_compression {
+	uint32_t tag;
+	uint32_t len;
+	/* whole file compression format. 0 if no compression. */
+	uint32_t compression;
+	uint32_t decompressed_size;
+} __attribute__((packed));
+
 /* Given a cbfs_file, return the first file attribute, or NULL. */
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
 
@@ -237,10 +247,14 @@ struct cbfs_media {
 	int (*close)(struct cbfs_media *media);
 };
 
-/* returns pointer to a file entry inside CBFS or NULL */
+/* returns pointer to a file entry inside CBFS or NULL on error */
 struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name);
 
-/* returns pointer to file content inside CBFS after if type is correct */
+/*
+ * Returns pointer to a copy of the file content or NULL on error.
+ * If the file is compressed, data will be decompressed.
+ * The caller owns the returned memory.
+ */
 void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 			    int type, size_t *sz);
 
diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
index 3e614b6..49e4941 100644
--- a/payloads/libpayload/libcbfs/cbfs.c
+++ b/payloads/libpayload/libcbfs/cbfs.c
@@ -79,41 +79,14 @@ static void tohex16(unsigned int val, char* dest)
 }
 
 void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device, void *dest)
+			  uint16_t device)
 {
 	char name[17] = "pciXXXX,XXXX.rom";
-	struct cbfs_optionrom *orom;
-	uint8_t *src;
 
 	tohex16(vendor, name+3);
 	tohex16(device, name+8);
 
-	orom = (struct cbfs_optionrom *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
-
-	if (orom == NULL)
-		return NULL;
-
-	/* They might have specified a dest address. If so, we can decompress.
-	 * If not, there's not much hope of decompressing or relocating the rom.
-	 * in the common case, the expansion rom is uncompressed, we
-	 * pass 0 in for the dest, and all we have to do is find the rom and
-	 * return a pointer to it.
-	 */
-
-	/* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */
-	src = (uint8_t*)orom; // + sizeof(struct cbfs_optionrom);
-
-	if (! dest)
-		return src;
-
-	if (!cbfs_decompress(ntohl(orom->compression),
-			     src,
-			     dest,
-			     ntohl(orom->len)))
-		return NULL;
-
-	return dest;
+	return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
 }
 
 void * cbfs_load_stage(struct cbfs_media *media, const char *name)
@@ -149,6 +122,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 	entry = stage->entry;
 	// entry = ntohll(stage->entry);
 
+	free(stage);
 	return (void *) entry;
 }
 
@@ -163,11 +137,14 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name)
 	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
 		LOG("Unable to run %s:  Compressed file"
 		       "Not supported for in-place execution\n", name);
+		free(stage);
 		return 1;
 	}
 
 	LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry));
-	return run_address((void *)(uintptr_t)ntohll(stage->entry));
+	int result = run_address((void *)(uintptr_t)ntohll(stage->entry));
+	free(stage);
+	return result;
 }
 
 void *cbfs_load_payload(struct cbfs_media *media, const char *name)
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 5541f02..5a46af8 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -210,7 +210,38 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 	if (sz)
 		*sz = ntohl(file->len);
 
-	return (void *)CBFS_SUBHEADER(file);
+	void *file_content = (void *)CBFS_SUBHEADER(file);
+
+	struct cbfs_file_attribute *attr = cbfs_file_first_attr(file);
+	while (attr) {
+		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION)
+			break;
+		attr = cbfs_file_next_attr(file, attr);
+	}
+
+	int compression_algo = CBFS_COMPRESS_NONE;
+	if (attr) {
+		struct cbfs_file_attr_compression *comp =
+			(struct cbfs_file_attr_compression *)attr;
+		compression_algo = ntohl(comp->compression);
+		DEBUG("File '%s' is compressed (alg=%d)\n", compression_algo);
+		*sz = ntohl(comp->decompressed_size);
+	}
+
+	void *dst = malloc(*sz);
+	if (dst == NULL)
+		goto err;
+
+	if (!cbfs_decompress(compression_algo, file_content, dst, *sz))
+		goto err;
+
+	media->unmap(media, file);
+	return dst;
+
+err:
+	media->unmap(media, file);
+	free(dst);
+	return NULL;
 }
 
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file)


From gerrit at coreboot.org  Thu Sep 17 18:46:53 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 18:46:53 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload: allow
	compression at file header level
References: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+0@gerrit.coreboot.org>
Message-ID: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+7@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10938

-gerrit

commit 076277f82204b8644c6dc03bd126f8045d416d57
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: allow compression at file header level
    
    Decompression is handled transparently within cbfs_get_file_content:
    
    	const char *name = "foo.bmp";
    	void *dst = cbfs_get_file_content(media, name, type, NULL);
    
    To keep things consistent, a couple of API changes were necessary:
    - cbfs_get_file_content always returns a copy of the data, even for
      uncompressed files. It's the callers responsibility to free the
      memory.
    - same for cbfs_load_payload and cbfs_find_file.
    - cbfs_load_optionrom doesn't take a "dest" argument anymore but always
      returns a copy of the data, for compressed and uncompressed files.
      Like with cbfs_get_file_content, the caller is responsible to free it.
      It also decompresses based on extended file attributes instead of the
      cbfs_optionrom subheader that libpayload specified but that (AFAIK)
      nobody ever used, given that there's not even tooling for that.
    
    Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/cbfs.h      |  2 +-
 payloads/libpayload/include/cbfs_core.h | 18 ++++++++++++++--
 payloads/libpayload/libcbfs/cbfs.c      | 37 +++++++--------------------------
 payloads/libpayload/libcbfs/cbfs_core.c | 33 ++++++++++++++++++++++++++++-
 4 files changed, 56 insertions(+), 34 deletions(-)

diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h
index 59c31db..f57dce0 100644
--- a/payloads/libpayload/include/cbfs.h
+++ b/payloads/libpayload/include/cbfs.h
@@ -59,7 +59,7 @@ void *cbfs_find_file(const char *name, int type);
 
 int cbfs_execute_stage(struct cbfs_media *media, const char *name);
 void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device, void * dest);
+			  uint16_t device);
 void *cbfs_load_payload(struct cbfs_media *media, const char *name);
 void *cbfs_load_stage(struct cbfs_media *media, const char *name);
 
diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index a2ee744..3878e55 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -53,6 +53,7 @@
 #include <endian.h>
 #include <stddef.h>
 #include <stdint.h>
+#include <stdlib.h>
 
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
@@ -141,6 +142,7 @@ struct cbfs_file {
  * 0xff. Support both. */
 #define CBFS_FILE_ATTR_TAG_UNUSED 0
 #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
 
 /* The common fields of extended cbfs file attributes.
    Attributes are expected to start with tag/len, then append their
@@ -152,6 +154,14 @@ struct cbfs_file_attribute {
 	uint8_t data[0];
 } __attribute__((packed));
 
+struct cbfs_file_attr_compression {
+	uint32_t tag;
+	uint32_t len;
+	/* whole file compression format. 0 if no compression. */
+	uint32_t compression;
+	uint32_t decompressed_size;
+} __attribute__((packed));
+
 /* Given a cbfs_file, return the first file attribute, or NULL. */
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
 
@@ -237,10 +247,14 @@ struct cbfs_media {
 	int (*close)(struct cbfs_media *media);
 };
 
-/* returns pointer to a file entry inside CBFS or NULL */
+/* returns pointer to a file entry inside CBFS or NULL on error */
 struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name);
 
-/* returns pointer to file content inside CBFS after if type is correct */
+/*
+ * Returns pointer to a copy of the file content or NULL on error.
+ * If the file is compressed, data will be decompressed.
+ * The caller owns the returned memory.
+ */
 void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 			    int type, size_t *sz);
 
diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
index 3e614b6..49e4941 100644
--- a/payloads/libpayload/libcbfs/cbfs.c
+++ b/payloads/libpayload/libcbfs/cbfs.c
@@ -79,41 +79,14 @@ static void tohex16(unsigned int val, char* dest)
 }
 
 void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device, void *dest)
+			  uint16_t device)
 {
 	char name[17] = "pciXXXX,XXXX.rom";
-	struct cbfs_optionrom *orom;
-	uint8_t *src;
 
 	tohex16(vendor, name+3);
 	tohex16(device, name+8);
 
-	orom = (struct cbfs_optionrom *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
-
-	if (orom == NULL)
-		return NULL;
-
-	/* They might have specified a dest address. If so, we can decompress.
-	 * If not, there's not much hope of decompressing or relocating the rom.
-	 * in the common case, the expansion rom is uncompressed, we
-	 * pass 0 in for the dest, and all we have to do is find the rom and
-	 * return a pointer to it.
-	 */
-
-	/* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */
-	src = (uint8_t*)orom; // + sizeof(struct cbfs_optionrom);
-
-	if (! dest)
-		return src;
-
-	if (!cbfs_decompress(ntohl(orom->compression),
-			     src,
-			     dest,
-			     ntohl(orom->len)))
-		return NULL;
-
-	return dest;
+	return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
 }
 
 void * cbfs_load_stage(struct cbfs_media *media, const char *name)
@@ -149,6 +122,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 	entry = stage->entry;
 	// entry = ntohll(stage->entry);
 
+	free(stage);
 	return (void *) entry;
 }
 
@@ -163,11 +137,14 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name)
 	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
 		LOG("Unable to run %s:  Compressed file"
 		       "Not supported for in-place execution\n", name);
+		free(stage);
 		return 1;
 	}
 
 	LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry));
-	return run_address((void *)(uintptr_t)ntohll(stage->entry));
+	int result = run_address((void *)(uintptr_t)ntohll(stage->entry));
+	free(stage);
+	return result;
 }
 
 void *cbfs_load_payload(struct cbfs_media *media, const char *name)
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 5541f02..5a46af8 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -210,7 +210,38 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 	if (sz)
 		*sz = ntohl(file->len);
 
-	return (void *)CBFS_SUBHEADER(file);
+	void *file_content = (void *)CBFS_SUBHEADER(file);
+
+	struct cbfs_file_attribute *attr = cbfs_file_first_attr(file);
+	while (attr) {
+		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION)
+			break;
+		attr = cbfs_file_next_attr(file, attr);
+	}
+
+	int compression_algo = CBFS_COMPRESS_NONE;
+	if (attr) {
+		struct cbfs_file_attr_compression *comp =
+			(struct cbfs_file_attr_compression *)attr;
+		compression_algo = ntohl(comp->compression);
+		DEBUG("File '%s' is compressed (alg=%d)\n", compression_algo);
+		*sz = ntohl(comp->decompressed_size);
+	}
+
+	void *dst = malloc(*sz);
+	if (dst == NULL)
+		goto err;
+
+	if (!cbfs_decompress(compression_algo, file_content, dst, *sz))
+		goto err;
+
+	media->unmap(media, file);
+	return dst;
+
+err:
+	media->unmap(media, file);
+	free(dst);
+	return NULL;
 }
 
 struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file)


From gerrit at coreboot.org  Thu Sep 17 18:46:56 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 18:46:56 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload: bring
	in file attribute support from cbfstool
References: <I86baefe5c299125a4733fa20523efd5d06de7182+0@gerrit.coreboot.org>
Message-ID: <I86baefe5c299125a4733fa20523efd5d06de7182+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11675

-gerrit

commit 21c711f15b577b3188b1f7855cc35f86c45955b9
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 18:53:40 2015 +0200

    libpayload: bring in file attribute support from cbfstool
    
    This comes from cbfstool (GPL) into libpayload (BSD-l), but I could have
    just as well written it in libpayload first.
    
    Change-Id: I86baefe5c299125a4733fa20523efd5d06de7182
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/cbfs_core.h | 26 ++++++++++++++++++++-
 payloads/libpayload/libcbfs/cbfs_core.c | 41 +++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index a95cef7..a2ee744 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -132,10 +132,34 @@ struct cbfs_file {
 	char magic[8];
 	uint32_t len;
 	uint32_t type;
-	uint32_t checksum;
+	uint32_t attributes_offset;
 	uint32_t offset;
+	char filename[];
 } __attribute__((packed));
 
+/* Depending on how the header was initialized, it may be backed with 0x00 or
+ * 0xff. Support both. */
+#define CBFS_FILE_ATTR_TAG_UNUSED 0
+#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+
+/* The common fields of extended cbfs file attributes.
+   Attributes are expected to start with tag/len, then append their
+   specific fields. */
+struct cbfs_file_attribute {
+	uint32_t tag;
+	/* len covers the whole structure, incl. tag and len */
+	uint32_t len;
+	uint8_t data[0];
+} __attribute__((packed));
+
+/* Given a cbfs_file, return the first file attribute, or NULL. */
+struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
+
+/* Given a cbfs_file and a cbfs_file_attribute, return the attribute that
+ * follows it, or NULL. */
+struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file,
+	struct cbfs_file_attribute *attr);
+
 /*** Component sub-headers ***/
 
 /* Following are component sub-headers for the "standard"
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 7926d9d..6a19b26 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -213,6 +213,47 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 	return (void *)CBFS_SUBHEADER(file);
 }
 
+struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file)
+{
+	/* attributes_offset should be 0 when there is no attribute, but all
+	 * values that point into the cbfs_file header are invalid, too. */
+	if (ntohl(file->attributes_offset) <= sizeof(*file))
+		return NULL;
+
+	/* There needs to be enough space for the file header and one
+	 * attribute header for this to make sense. */
+	if (ntohl(file->offset) <=
+		sizeof(*file) + sizeof(struct cbfs_file_attribute))
+		return NULL;
+
+	return (struct cbfs_file_attribute *)
+		(((uint8_t *)file) + ntohl(file->attributes_offset));
+}
+
+struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file,
+	struct cbfs_file_attribute *attr)
+{
+	/* ex falso sequitur quodlibet */
+	if (attr == NULL)
+		return NULL;
+
+	/* Is there enough space for another attribute? */
+	if ((uint8_t *)attr + ntohl(attr->len) +
+		sizeof(struct cbfs_file_attribute) >=
+		(uint8_t *)file + ntohl(file->offset))
+		return NULL;
+
+	struct cbfs_file_attribute *next = (struct cbfs_file_attribute *)
+		(((uint8_t *)attr) + ntohl(attr->len));
+	/* If any, "unused" attributes must come last. */
+	if (ntohl(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED)
+		return NULL;
+	if (ntohl(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED2)
+		return NULL;
+
+	return next;
+}
+
 int cbfs_decompress(int algo, void *src, void *dst, int len)
 {
 	switch (algo) {


From gerrit at coreboot.org  Thu Sep 17 18:47:00 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 18:47:00 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: libpayload:
	rename cbfs variable from name to vardata
References: <I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761+0@gerrit.coreboot.org>
Message-ID: <I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11676

-gerrit

commit aa39cf3ff0bb891abc0c7f975a0ffc98d913ae7d
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: rename cbfs variable from name to vardata
    
    The dynamically sized region after struct cbfs_file doesn't contain only
    the file name anymore.
    
    Change-Id: I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/libcbfs/cbfs_core.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 6a19b26..5541f02 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -97,8 +97,8 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
 /* public API starts here*/
 struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
 {
-	const char *file_name;
-	uint32_t offset, romsize, name_len;
+	const char *vardata;
+	uint32_t offset, romsize, vardata_len;
 	const struct cbfs_header *header;
 	struct cbfs_file file, *file_ptr;
 	struct cbfs_media default_media;
@@ -153,29 +153,29 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
 			offset += new_align;
 			continue;
 		}
-		name_len = ntohl(file.offset) - sizeof(file);
-		DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset,
-		      name_len);
+		vardata_len = ntohl(file.offset) - sizeof(file);
+		DEBUG(" - load entry 0x%x variable data (%d bytes)...\n",
+			offset, vardata_len);
 
 		// load file name (arbitrary length).
-		file_name = (const char*)media->map(
-				media, offset + sizeof(file), name_len);
-		if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) {
+		vardata = (const char*)media->map(
+				media, offset + sizeof(file), vardata_len);
+		if (vardata == CBFS_MEDIA_INVALID_MAP_ADDRESS) {
 			ERROR("ERROR: Failed to get filename: 0x%x.\n", offset);
-		} else if (strcmp(file_name, name) == 0) {
+		} else if (strcmp(vardata, name) == 0) {
 			int file_offset = ntohl(file.offset),
 			    file_len = ntohl(file.len);
 			DEBUG("Found file (offset=0x%x, len=%d).\n",
 			    offset + file_offset, file_len);
-			media->unmap(media, file_name);
+			media->unmap(media, vardata);
 			file_ptr = media->map(media, offset,
 					      file_offset + file_len);
 			media->close(media);
 			return file_ptr;
 		} else {
 			DEBUG(" (unmatched file @0x%x: %s)\n", offset,
-			      file_name);
-			media->unmap(media, file_name);
+			      vardata);
+			media->unmap(media, vardata);
 		}
 
 		// Move to next file.


From gerrit at coreboot.org  Thu Sep 17 18:47:03 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Thu, 17 Sep 2015 18:47:03 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: libpayload:
	provide cbfs_file_find_attr()
References: <I78ee3b996b4b086605244c5d7d57ef7e3fc1db47+0@gerrit.coreboot.org>
Message-ID: <I78ee3b996b4b086605244c5d7d57ef7e3fc1db47+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11678

-gerrit

commit 127b77edf15046dc89bdc4925d4acaf89e8498e7
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Thu Sep 17 20:45:52 2015 +0200

    libpayload: provide cbfs_file_find_attr()
    
    cbfs_file_find_attr(file, tag) finds the first attribute of file with
    the given tag.
    
    Change-Id: I78ee3b996b4b086605244c5d7d57ef7e3fc1db47
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/cbfs_core.h |  5 +++++
 payloads/libpayload/libcbfs/cbfs_core.c | 21 +++++++++++++++------
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index 3878e55..ec59a20 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -170,6 +170,11 @@ struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file);
 struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file,
 	struct cbfs_file_attribute *attr);
 
+/* Given a cbfs_file and an attribute tag, return the first instance of the
+ * attribute or NULL if none found. */
+struct cbfs_file_attribute *cbfs_file_find_attr(struct cbfs_file *file,
+	uint32_t tag);
+
 /*** Component sub-headers ***/
 
 /* Following are component sub-headers for the "standard"
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 5a46af8..153dc8a 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -212,12 +212,8 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 
 	void *file_content = (void *)CBFS_SUBHEADER(file);
 
-	struct cbfs_file_attribute *attr = cbfs_file_first_attr(file);
-	while (attr) {
-		if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION)
-			break;
-		attr = cbfs_file_next_attr(file, attr);
-	}
+	struct cbfs_file_attribute *attr =
+		cbfs_file_find_attr(file, CBFS_FILE_ATTR_TAG_COMPRESSION);
 
 	int compression_algo = CBFS_COMPRESS_NONE;
 	if (attr) {
@@ -285,6 +281,19 @@ struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file,
 	return next;
 }
 
+struct cbfs_file_attribute *cbfs_file_find_attr(struct cbfs_file *file,
+	uint32_t tag)
+{
+	struct cbfs_file_attribute *attr = cbfs_file_first_attr(file);
+	while (attr) {
+		if (ntohl(attr->tag) == tag)
+			break;
+		attr = cbfs_file_next_attr(file, attr);
+	}
+	return attr;
+
+}
+
 int cbfs_decompress(int algo, void *src, void *dst, int len)
 {
 	switch (algo) {


From gerrit at coreboot.org  Thu Sep 17 18:48:13 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 18:48:13 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	bring in file attribute support from cbfstool
References: <I86baefe5c299125a4733fa20523efd5d06de7182+0@gerrit.coreboot.org>
Message-ID: <E1ZceE9-0003wO-7o@mail.coreboot.org>

the following patch was just integrated into master:
commit 377d1db57dae282cda94a2c24994707a32efdd00
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 18:53:40 2015 +0200

    libpayload: bring in file attribute support from cbfstool
    
    This comes from cbfstool (GPL) into libpayload (BSD-l), but I could have
    just as well written it in libpayload first.
    
    Change-Id: I86baefe5c299125a4733fa20523efd5d06de7182
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11675
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11675 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 18:52:51 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 18:52:51 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	rename cbfs variable from name to vardata
References: <I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761+0@gerrit.coreboot.org>
Message-ID: <E1ZceId-0004Kp-Cx@mail.coreboot.org>

the following patch was just integrated into master:
commit 5c6dc72501329226b9ead5a184fb49f5af732dd3
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: rename cbfs variable from name to vardata
    
    The dynamically sized region after struct cbfs_file doesn't contain only
    the file name anymore.
    
    Change-Id: I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11676
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11676 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 18:53:02 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 18:53:02 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	allow compression at file header level
References: <If959e3dff9b93c6ae45ec7358afcc7840bc17218+0@gerrit.coreboot.org>
Message-ID: <E1ZceIo-0004Md-RG@mail.coreboot.org>

the following patch was just integrated into master:
commit d66f1da846f8e524a6211518c46a993d563b4ffc
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Thu Jul 9 15:07:45 2015 -0700

    libpayload: allow compression at file header level
    
    Decompression is handled transparently within cbfs_get_file_content:
    
    	const char *name = "foo.bmp";
    	void *dst = cbfs_get_file_content(media, name, type, NULL);
    
    To keep things consistent, a couple of API changes were necessary:
    - cbfs_get_file_content always returns a copy of the data, even for
      uncompressed files. It's the callers responsibility to free the
      memory.
    - same for cbfs_load_payload and cbfs_find_file.
    - cbfs_load_optionrom doesn't take a "dest" argument anymore but always
      returns a copy of the data, for compressed and uncompressed files.
      Like with cbfs_get_file_content, the caller is responsible to free it.
      It also decompresses based on extended file attributes instead of the
      cbfs_optionrom subheader that libpayload specified but that (AFAIK)
      nobody ever used, given that there's not even tooling for that.
    
    Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/10938
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/10938 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 19:17:09 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 19:17:09 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	Don't use fileno() to get file size
References: <I5be62a731f928333ea2e5843d81f541453fdb396+0@gerrit.coreboot.org>
Message-ID: <E1ZcegA-0003Ew-0Q@mail.coreboot.org>

the following patch was just integrated into master:
commit 1bb487c474c378cf61bd28f83b9eb87162ffc1c4
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Sep 14 10:46:44 2015 -0700

    cbfstool: Don't use fileno() to get file size
    
    fileno() is a mess on some operating systems. Don't
    deliberately convert between FILE * and file handles.
    
    Change-Id: I5be62a731f928333ea2e5843d81f541453fdb396
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Reviewed-on: http://review.coreboot.org/11636
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/11636 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 19:56:28 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 17 Sep 2015 19:56:28 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: compile
	successfully on Cygwin
References: <I068b181d67daf9c7280110e64aefb634aa20c69b+0@gerrit.coreboot.org>
Message-ID: <I068b181d67daf9c7280110e64aefb634aa20c69b+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11667

-gerrit

commit cf46be2a2910385cd271017fe1e79cededd80e4b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Sep 15 17:41:07 2015 -0700

    cbfstool: compile successfully on Cygwin
    
    As reported in http://review.coreboot.org/#/c/10027
    cbfstool on Cygwin likes to be compiled with -D_GNU_SOURCE.
    That patch was abandoned because it would unwantedly turn on
    more GNU extensions. Instead of doing that, only enable the
    define on Cygwin, switch to -std=gnu99 instead of -std=c99 to
    make fileno and strdup actually available.
    A MINGW32 check that was forgotten in Makefile was copied over
    from Makefile.inc to keep the two files in sync.
    
    This patch has no impact on non-Windows builds.
    
    Change-Id: I068b181d67daf9c7280110e64aefb634aa20c69b
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 util/cbfstool/Makefile.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 2a3dedf..97f053b 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -42,7 +42,7 @@ rmodobj += common.o
 rmodobj += elfheaders.o
 rmodobj += xdr.o
 
-TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra
+TOOLCFLAGS ?= -Werror -Wall -Wextra
 TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
 TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings
 TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h
@@ -55,6 +55,11 @@ TOOLLDFLAGS ?=
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
 TOOLCFLAGS += -mno-ms-bitfields
 endif
+ifeq ($(shell uname -o), Cygwin)
+TOOLFLAGS+=-std=gnu99 -D_GNU_SOURCE
+else
+TOOLFLAGS+=-std=c99
+endif
 
 $(objutil)/cbfstool/%.o: $(objutil)/cbfstool/%.c
 	printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"


From gerrit at coreboot.org  Thu Sep 17 20:01:12 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 17 Sep 2015 20:01:12 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: compile
	successfully on Cygwin
References: <I068b181d67daf9c7280110e64aefb634aa20c69b+0@gerrit.coreboot.org>
Message-ID: <I068b181d67daf9c7280110e64aefb634aa20c69b+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11667

-gerrit

commit 92c58b2c010fc38b17f7c6a4fa38dfa43fd85732
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Sep 15 17:41:07 2015 -0700

    cbfstool: compile successfully on Cygwin
    
    As reported in http://review.coreboot.org/#/c/10027
    cbfstool on Cygwin likes to be compiled with -D_GNU_SOURCE.
    That patch was abandoned because it would unwantedly turn on
    more GNU extensions. Instead of doing that, only enable the
    define on Cygwin, switch to -std=gnu99 instead of -std=c99 to
    make fileno and strdup actually available.
    A MINGW32 check that was forgotten in Makefile was copied over
    from Makefile.inc to keep the two files in sync.
    
    This patch has no impact on non-Windows builds.
    
    Change-Id: I068b181d67daf9c7280110e64aefb634aa20c69b
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 util/cbfstool/Makefile.inc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 2a3dedf..aa93119 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -42,7 +42,7 @@ rmodobj += common.o
 rmodobj += elfheaders.o
 rmodobj += xdr.o
 
-TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra
+TOOLCFLAGS ?= -Werror -Wall -Wextra
 TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
 TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings
 TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h
@@ -55,6 +55,12 @@ TOOLLDFLAGS ?=
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
 TOOLCFLAGS += -mno-ms-bitfields
 endif
+ifeq ($(shell uname -o), Cygwin)
+TOOLCFLAGS+=-std=gnu99
+TOOLCPPFLAGS+=-D_GNU_SOURCE
+else
+TOOLCFLAGS+=-std=c99
+endif
 
 $(objutil)/cbfstool/%.o: $(objutil)/cbfstool/%.c
 	printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"


From gerrit at coreboot.org  Thu Sep 17 20:13:50 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 17 Sep 2015 20:13:50 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: libpayload:
	provide cbfs_file_find_attr()
References: <I78ee3b996b4b086605244c5d7d57ef7e3fc1db47+0@gerrit.coreboot.org>
Message-ID: <E1ZcfZ0-0004cX-HZ@mail.coreboot.org>

the following patch was just integrated into master:
commit eb33b3f80e2fac8f92035a7960cf460981487b2d
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Thu Sep 17 20:45:52 2015 +0200

    libpayload: provide cbfs_file_find_attr()
    
    cbfs_file_find_attr(file, tag) finds the first attribute of file with
    the given tag.
    
    Change-Id: I78ee3b996b4b086605244c5d7d57ef7e3fc1db47
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11678
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11678 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 17 22:16:47 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 22:16:47 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfs: add
	struct cbfsf
References: <I05486c6cf6cfcafa5c64b36324833b2374f763c2+0@gerrit.coreboot.org>
Message-ID: <I05486c6cf6cfcafa5c64b36324833b2374f763c2+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11679

-gerrit

commit 687e0fdb218e253f8ecf445c3d6c03ebd0bd75b7
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 16:09:30 2015 -0500

    cbfs: add struct cbfsf
    
    Now that cbfs is adding more metadata in the cbfs file
    header one needs to access that metadata. Therefore,
    add struct cbfsf which tracks the metadata and data
    of the file separately. Note that stage and payload
    metadata specific to itself is still contained within
    the 'data' portion of a cbfs file. Update the cbfs
    API to use struct cbfsf. Additionally, remove struct
    cbfsd as there's nothing else associated with a cbfs
    region aside from offset and size which tracked
    by a region_device (thanks, CBFS_ALIGNMENT!).
    
    BUG=None
    BRANCH=None
    TEST=Built and booted through end of ramstage on qemu armv7.
    
    Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/cbfs.h                                 | 20 ++++++----
 src/lib/assets.c                                   |  9 ++++-
 src/lib/cbfs.c                                     | 45 +++++++++++-----------
 src/soc/intel/common/fsp_ramstage.c                |  6 +--
 src/soc/nvidia/tegra132/ccplex.c                   |  5 ++-
 src/soc/nvidia/tegra210/mtc.c                      |  5 ++-
 .../google/chromeos/vboot2/vboot_loader.c          | 18 ++++++---
 7 files changed, 66 insertions(+), 42 deletions(-)

diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f23a82a..5d60716 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -30,8 +30,8 @@
  * - cbfsd which is a descriptor for representing a cbfs instance
  */
 
-/* Descriptor for cbfs lookup operations. */
-struct cbfsd;
+/* Object representing cbfs files. */
+struct cbfsf;
 
 /***********************************************
  * Perform CBFS operations on the boot device. *
@@ -43,8 +43,7 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device);
  * failure. */
 void *cbfs_boot_load_stage_by_name(const char *name);
 /* Locate file by name and optional type. Return 0 on success. < 0 on error. */
-int cbfs_boot_locate(struct region_device *fh, const char *name,
-			uint32_t *type);
+int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type);
 /* Map file into memory leaking the mapping. Only should be used when
  * leaking mappings are a no-op. Returns NULL on error, else returns
  * the mapping and sets the size of the file. */
@@ -55,7 +54,7 @@ int cbfs_prog_stage_load(struct prog *prog);
 
 /* Locate file by name and optional type. Returns 0 on succcess else < 0 on
  * error.*/
-int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
+int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
 		const char *name, uint32_t *type);
 
 /*****************************************************************
@@ -64,10 +63,17 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
  * API.                                                          *
  *****************************************************************/
 
-struct cbfsd {
-	const struct region_device *rdev;
+struct cbfsf {
+	struct region_device metadata;
+	struct region_device data;
 };
 
+static inline void cbfs_file_data(struct region_device *data,
+					const struct cbfsf *file)
+{
+	rdev_chain(data, &file->data, 0, region_device_sz(&file->data));
+}
+
 /* The cbfs_props struct describes the properties associated with a CBFS. */
 struct cbfs_props {
 	/* CBFS starts at the following offset within the boot region. */
diff --git a/src/lib/assets.c b/src/lib/assets.c
index 656f0b1..0115243 100644
--- a/src/lib/assets.c
+++ b/src/lib/assets.c
@@ -31,7 +31,14 @@
 #if DEFAULT_CBFS_PROVIDER_PRESENT
 static int cbfs_boot_asset_locate(struct asset *asset)
 {
-	return cbfs_boot_locate(&asset->rdev, asset->name, NULL);
+	struct cbfsf file;
+
+	if (cbfs_boot_locate(&file, asset_name(asset), NULL))
+		return -1;
+
+	cbfs_file_data(asset_rdev(asset), &file);
+
+	return 0;
 }
 
 static const struct asset_provider cbfs_default_provider = {
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index c4eff5b..e6d9a7c 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -59,9 +59,8 @@ static void cbfs_file_deserialize(struct cbfs_file *f, void *from)
 	f->offset = read_at_be32(from, off);
 }
 
-int cbfs_boot_locate(struct region_device *fh, const char *name, uint32_t *type)
+int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
 {
-	struct cbfsd cbfs;
 	struct region_device rdev;
 	const struct region_device *boot_dev;
 	struct cbfs_props props;
@@ -80,35 +79,29 @@ int cbfs_boot_locate(struct region_device *fh, const char *name, uint32_t *type)
 	if (rdev_chain(&rdev, boot_dev, props.offset, props.size))
 		return -1;
 
-	cbfs.rdev = &rdev;
-
-	return cbfs_locate(fh, &cbfs, name, type);
+	return cbfs_locate(fh, &rdev, name, type);
 }
 
 void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size)
 {
-	struct region_device fh;
+	struct cbfsf fh;
 	size_t fsize;
 
 	if (cbfs_boot_locate(&fh, name, &type))
 		return NULL;
 
-	fsize = region_device_sz(&fh);
+	fsize = region_device_sz(&fh.data);
 
 	if (size != NULL)
 		*size = fsize;
 
-	return rdev_mmap(&fh, 0, fsize);
+	return rdev_mmap(&fh.data, 0, fsize);
 }
 
-int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
+int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
 		const char *name, uint32_t *type)
 {
-	size_t offset;
-	const struct region_device *rd;
-
-	offset = 0;
-	rd = cbfs->rdev;
+	size_t offset = 0;
 
 	LOG("Locating '%s'\n", name);
 
@@ -123,12 +116,12 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		mapping = rdev_mmap(rd, offset, fsz);
+		mapping = rdev_mmap(cbfs, offset, fsz);
 		/* Can't read file. Nothing else to do but bail out. */
 		if (mapping == NULL)
 			break;
 		cbfs_file_deserialize(&file, mapping);
-		rdev_munmap(rd, mapping);
+		rdev_munmap(cbfs, mapping);
 
 		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
 			offset++;
@@ -137,13 +130,13 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 		}
 
 		/* See if names match. */
-		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
+		fname = rdev_mmap(cbfs, offset + fsz, file.offset - fsz);
 
 		if (fname == NULL)
 			break;
 
 		name_match = !strcmp(fname, name);
-		rdev_munmap(rd, fname);
+		rdev_munmap(cbfs, fname);
 
 		if (!name_match) {
 			DEBUG(" Unmatched '%s' at %zx\n", fname, offset);
@@ -160,11 +153,13 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 		}
 
 		LOG("Found @ offset %zx size %x\n", offset, file.len);
-		/* File and type match. Create a chained region_device to
-		 * represent the cbfs file. */
+		/* File and type match. Keep track of both the metadata and
+		 * the data for the file. */
+		if (rdev_chain(&fh->metadata, cbfs, offset, file.offset))
+			break;
 		offset += file.offset;
 		datasz = file.len;
-		if (rdev_chain(fh, rd, offset, datasz))
+		if (rdev_chain(&fh->data, cbfs, offset, datasz))
 			break;
 
 		/* Success. */
@@ -209,12 +204,16 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
 
 void *cbfs_boot_load_stage_by_name(const char *name)
 {
+	struct cbfsf fh;
 	struct prog stage = PROG_INIT(ASSET_UNKNOWN, name);
 	uint32_t type = CBFS_TYPE_STAGE;
 
-	if (cbfs_boot_locate(&stage.asset.rdev, name, &type))
+	if (cbfs_boot_locate(&fh, name, &type))
 		return NULL;
 
+	/* Chain data portion in the prog. */
+	cbfs_file_data(prog_rdev(&stage), &fh);
+
 	if (cbfs_prog_stage_load(&stage))
 		return NULL;
 
@@ -228,7 +227,7 @@ int cbfs_prog_stage_load(struct prog *pstage)
 	void *entry;
 	size_t fsize;
 	size_t foffset;
-	const struct region_device *fh = &pstage->asset.rdev;
+	const struct region_device *fh = prog_rdev(pstage);
 
 	if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage))
 		return 0;
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index d1f2e49..c8dfad1 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -164,15 +164,15 @@ static void fsp_cache_save(struct prog *fsp)
 
 static int fsp_find_and_relocate(struct prog *fsp)
 {
-	struct region_device fsp_rdev;
+	struct cbfsf fsp_file;
 	uint32_t type = CBFS_TYPE_FSP;
 
-	if (cbfs_boot_locate(&fsp_rdev, prog_name(fsp), &type)) {
+	if (cbfs_boot_locate(&fsp_file, prog_name(fsp), &type)) {
 		printk(BIOS_ERR, "ERROR: Couldn't find fsp.bin in CBFS.\n");
 		return -1;
 	}
 
-	if (fsp_relocate(fsp, &fsp_rdev)) {
+	if (fsp_relocate(fsp, &fsp_file.data)) {
 		printk(BIOS_ERR, "ERROR: FSP relocation failed.\n");
 		return -1;
 	}
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index e133b48..b003ec1 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -77,6 +77,7 @@ int ccplex_load_mts(void)
 {
 	ssize_t nread;
 	struct stopwatch sw;
+	struct cbfsf mts_file;
 	struct region_device fh;
 
 	/*
@@ -87,11 +88,13 @@ int ccplex_load_mts(void)
 	void * const mts = (void *)(uintptr_t)MTS_LOAD_ADDRESS;
 
 	stopwatch_init(&sw);
-	if (cbfs_boot_locate(&fh, MTS_FILE_NAME, NULL)) {
+	if (cbfs_boot_locate(&mts_file, MTS_FILE_NAME, NULL)) {
 		printk(BIOS_DEBUG, "MTS file not found: %s\n", MTS_FILE_NAME);
 		return -1;
 	}
 
+	cbfs_file_data(&fh, &mts_file);
+
 	/* Read MTS file into the carveout region. */
 	nread = rdev_readat(&fh, mts, 0, region_device_sz(&fh));
 
diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c
index fb6c9cb..b402a14 100644
--- a/src/soc/nvidia/tegra210/mtc.c
+++ b/src/soc/nvidia/tegra210/mtc.c
@@ -33,16 +33,19 @@ int tegra210_run_mtc(void)
 {
 	ssize_t nread;
 	struct region_device fh;
+	struct cbfsf mtc_file;
 
 	void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS;
 	void *dvfs_table;
 	size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc;
 
-	if (cbfs_boot_locate(&fh, "tegra_mtc.bin", NULL)) {
+	if (cbfs_boot_locate(&mtc_file, "tegra_mtc.bin", NULL)) {
 		printk(BIOS_ERR, "MTC file not found: tegra_mtc.bin\n");
 		return -1;
 	}
 
+	cbfs_file_data(&fh, &mtc_file);
+
 	/* Read MTC file into predefined region. */
 	nread = rdev_readat(&fh, mtc, 0, region_device_sz(&fh));
 
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
index 90ada1e..90cf11d 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
@@ -73,6 +73,7 @@ static int vboot_active(struct asset *asset)
 	if (run_verification) {
 		verstage_main();
 	} else if (verstage_should_load()) {
+		struct cbfsf file;
 		struct prog verstage =
 			PROG_INIT(ASSET_VERSTAGE,
 				CONFIG_CBFS_PREFIX "/verstage");
@@ -80,9 +81,12 @@ static int vboot_active(struct asset *asset)
 		printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n");
 
 		/* load verstage from RO */
-		if (cbfs_boot_locate(prog_rdev(&verstage),
-						prog_name(&verstage), NULL) ||
-		    cbfs_prog_stage_load(&verstage))
+		if (cbfs_boot_locate(&file, prog_name(&verstage), NULL))
+			die("failed to load verstage");
+
+		cbfs_file_data(&prog_rdev(&verstage, &file));
+
+		if (cbfs_prog_stage_load(&verstage))
 			die("failed to load verstage");
 
 		/* verify and select a slot */
@@ -162,9 +166,9 @@ static int vboot_locate_by_components(const struct region_device *fw_main,
 static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main,
 					struct asset *asset)
 {
-	struct cbfsd cbfs;
 	struct region_device rdev;
 	struct cbfs_props props;
+	struct cbfsf file;
 
 	if (cbfs_boot_region_properties(&props))
 		return -1;
@@ -172,9 +176,11 @@ static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main,
 	if (rdev_chain(&rdev, fw_main, props.offset, props.size))
 		return -1;
 
-	cbfs.rdev = &rdev;
+	if (cbfs_locate(file, &cbfs, asset_name(asset), NULL))
+		return -1;
 
-	return cbfs_locate(asset_rdev(asset), &cbfs, asset_name(asset), NULL);
+	cbfs_file_data(asset_rdev(asset), &file);
+	return 0;
 }
 
 static int vboot_asset_locate(const struct region_device *fw_main,


From gerrit at coreboot.org  Thu Sep 17 22:16:49 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 22:16:49 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: linking: link
	bootblock.elf with .data and .bss sections again
References: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+0@gerrit.coreboot.org>
Message-ID: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11680

-gerrit

commit ac22c8eeb77af0821211069355bfebff539a6f11
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 17:02:53 2015 -0500

    linking: link bootblock.elf with .data and .bss sections again
    
    Currently coreboot expects the loader to clear the bss section
    for all stages. i.e. stages don't clear their own bss. On ARM
    SoCs the BootROM would be responsible for this. To do that
    one needs to include the bss section data (all zeros) in the
    bootblock.bin file. This was previously being attempted by
    keeping the .bss info in the .data section because objcopy
    happened zero out non-file allocated data section data.
    
    Instead go back to linking bootblock with the bss section
    but mark the bss section as loadable allocatable data. That
    way it will be included in the binary properly when objcopy
    -O binary is emplyed. Also do the same for the data section
    in the case of no non-zero object values are in the data
    section.
    
    Without this change the trick of including .bss in .data
    was not working when there wasn't a non-zero value object
    in the data section.
    
    BUG=None
    BRANCH=None
    TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
         the cleared bss.
    
    Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc       | 12 ++++++++++++
 src/lib/program.ld |  7 -------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 81c149d..55635ba 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -531,6 +531,18 @@ find-substr = $(word 1,$(subst _, ,$(1)))
 # and remove .x the next time and finally return romstage
 find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call find-substr,$(1))),$(call find-class,$(basename $(1))))
 
+# Bootblocks are not CBFS stages. coreboot is currently expecting the bss to
+# be cleared by the loader of the stage. For ARM SoCs that means one needs to
+# include the bss section in the binary so the BootROM clears the bss on
+# loading of the bootblock stage. Achieve this by marking the bss section
+# loadable,allocatable, and data. Do the same for the .data section in case
+# it's marked as NOBITS.
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf
+	$(eval class := $(call find-class,$(@F)))
+	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
+	$(OBJCOPY_$(class)) --set-section-flags .bss=load,alloc,data --set-section-flags .data=loa,alloc,data $< $<.tmp
+	$(OBJCOPY_$(class)) -O binary $<.tmp $@
+
 $(objcbfs)/%.bin: $(objcbfs)/%.elf
 	$(eval class := $(call find-class,$(@F)))
 	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
diff --git a/src/lib/program.ld b/src/lib/program.ld
index c8ce5ee..ab36239 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -111,14 +111,7 @@
 #endif
 
 #if ARCH_STAGE_HAS_BSS_SECTION
-#if ENV_BOOTBLOCK
-/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
- * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
- * the BSS into the .data section so those zeroes get loaded explicitly. */
-.data . : {
-#else
 .bss . : {
-#endif
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bss = .;
 	*(.bss)


From gerrit at coreboot.org  Thu Sep 17 22:23:51 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 22:23:51 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: link
	bootblock.elf with .data and .bss sections again
References: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+0@gerrit.coreboot.org>
Message-ID: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11680

-gerrit

commit a26fee0eee6596fc743dd887ed963230e7803c5f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 17:02:53 2015 -0500

    linking: link bootblock.elf with .data and .bss sections again
    
    Currently coreboot expects the loader to clear the bss section
    for all stages. i.e. stages don't clear their own bss. On ARM
    SoCs the BootROM would be responsible for this. To do that
    one needs to include the bss section data (all zeros) in the
    bootblock.bin file. This was previously being attempted by
    keeping the .bss info in the .data section because objcopy
    happened zero out non-file allocated data section data.
    
    Instead go back to linking bootblock with the bss section
    but mark the bss section as loadable allocatable data. That
    way it will be included in the binary properly when objcopy
    -O binary is emplyed. Also do the same for the data section
    in the case of no non-zero object values are in the data
    section.
    
    Without this change the trick of including .bss in .data
    was not working when there wasn't a non-zero value object
    in the data section.
    
    BUG=None
    BRANCH=None
    TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
         the cleared bss.
    
    Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc       | 12 ++++++++++++
 src/lib/program.ld |  7 -------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 81c149d..55635ba 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -531,6 +531,18 @@ find-substr = $(word 1,$(subst _, ,$(1)))
 # and remove .x the next time and finally return romstage
 find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call find-substr,$(1))),$(call find-class,$(basename $(1))))
 
+# Bootblocks are not CBFS stages. coreboot is currently expecting the bss to
+# be cleared by the loader of the stage. For ARM SoCs that means one needs to
+# include the bss section in the binary so the BootROM clears the bss on
+# loading of the bootblock stage. Achieve this by marking the bss section
+# loadable,allocatable, and data. Do the same for the .data section in case
+# it's marked as NOBITS.
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf
+	$(eval class := $(call find-class,$(@F)))
+	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
+	$(OBJCOPY_$(class)) --set-section-flags .bss=load,alloc,data --set-section-flags .data=loa,alloc,data $< $<.tmp
+	$(OBJCOPY_$(class)) -O binary $<.tmp $@
+
 $(objcbfs)/%.bin: $(objcbfs)/%.elf
 	$(eval class := $(call find-class,$(@F)))
 	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
diff --git a/src/lib/program.ld b/src/lib/program.ld
index c8ce5ee..ab36239 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -111,14 +111,7 @@
 #endif
 
 #if ARCH_STAGE_HAS_BSS_SECTION
-#if ENV_BOOTBLOCK
-/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
- * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
- * the BSS into the .data section so those zeroes get loaded explicitly. */
-.data . : {
-#else
 .bss . : {
-#endif
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bss = .;
 	*(.bss)


From gerrit at coreboot.org  Thu Sep 17 22:23:55 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 22:23:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfs: add struct
	cbfsf
References: <I05486c6cf6cfcafa5c64b36324833b2374f763c2+0@gerrit.coreboot.org>
Message-ID: <I05486c6cf6cfcafa5c64b36324833b2374f763c2+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11679

-gerrit

commit 182020e9a72b4c005135aca690f08a5c7e5c7cb9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 16:09:30 2015 -0500

    cbfs: add struct cbfsf
    
    Now that cbfs is adding more metadata in the cbfs file
    header one needs to access that metadata. Therefore,
    add struct cbfsf which tracks the metadata and data
    of the file separately. Note that stage and payload
    metadata specific to itself is still contained within
    the 'data' portion of a cbfs file. Update the cbfs
    API to use struct cbfsf. Additionally, remove struct
    cbfsd as there's nothing else associated with a cbfs
    region aside from offset and size which tracked
    by a region_device (thanks, CBFS_ALIGNMENT!).
    
    BUG=None
    BRANCH=None
    TEST=Built and booted through end of ramstage on qemu armv7.
    
    Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/cbfs.h                                 | 20 ++++++----
 src/lib/assets.c                                   |  9 ++++-
 src/lib/cbfs.c                                     | 45 +++++++++++-----------
 src/soc/intel/common/fsp_ramstage.c                |  6 +--
 src/soc/nvidia/tegra132/ccplex.c                   |  5 ++-
 src/soc/nvidia/tegra210/mtc.c                      |  5 ++-
 .../google/chromeos/vboot2/vboot_loader.c          | 18 ++++++---
 7 files changed, 66 insertions(+), 42 deletions(-)

diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f23a82a..5d60716 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -30,8 +30,8 @@
  * - cbfsd which is a descriptor for representing a cbfs instance
  */
 
-/* Descriptor for cbfs lookup operations. */
-struct cbfsd;
+/* Object representing cbfs files. */
+struct cbfsf;
 
 /***********************************************
  * Perform CBFS operations on the boot device. *
@@ -43,8 +43,7 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device);
  * failure. */
 void *cbfs_boot_load_stage_by_name(const char *name);
 /* Locate file by name and optional type. Return 0 on success. < 0 on error. */
-int cbfs_boot_locate(struct region_device *fh, const char *name,
-			uint32_t *type);
+int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type);
 /* Map file into memory leaking the mapping. Only should be used when
  * leaking mappings are a no-op. Returns NULL on error, else returns
  * the mapping and sets the size of the file. */
@@ -55,7 +54,7 @@ int cbfs_prog_stage_load(struct prog *prog);
 
 /* Locate file by name and optional type. Returns 0 on succcess else < 0 on
  * error.*/
-int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
+int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
 		const char *name, uint32_t *type);
 
 /*****************************************************************
@@ -64,10 +63,17 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
  * API.                                                          *
  *****************************************************************/
 
-struct cbfsd {
-	const struct region_device *rdev;
+struct cbfsf {
+	struct region_device metadata;
+	struct region_device data;
 };
 
+static inline void cbfs_file_data(struct region_device *data,
+					const struct cbfsf *file)
+{
+	rdev_chain(data, &file->data, 0, region_device_sz(&file->data));
+}
+
 /* The cbfs_props struct describes the properties associated with a CBFS. */
 struct cbfs_props {
 	/* CBFS starts at the following offset within the boot region. */
diff --git a/src/lib/assets.c b/src/lib/assets.c
index 656f0b1..0115243 100644
--- a/src/lib/assets.c
+++ b/src/lib/assets.c
@@ -31,7 +31,14 @@
 #if DEFAULT_CBFS_PROVIDER_PRESENT
 static int cbfs_boot_asset_locate(struct asset *asset)
 {
-	return cbfs_boot_locate(&asset->rdev, asset->name, NULL);
+	struct cbfsf file;
+
+	if (cbfs_boot_locate(&file, asset_name(asset), NULL))
+		return -1;
+
+	cbfs_file_data(asset_rdev(asset), &file);
+
+	return 0;
 }
 
 static const struct asset_provider cbfs_default_provider = {
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index c4eff5b..e6d9a7c 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -59,9 +59,8 @@ static void cbfs_file_deserialize(struct cbfs_file *f, void *from)
 	f->offset = read_at_be32(from, off);
 }
 
-int cbfs_boot_locate(struct region_device *fh, const char *name, uint32_t *type)
+int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
 {
-	struct cbfsd cbfs;
 	struct region_device rdev;
 	const struct region_device *boot_dev;
 	struct cbfs_props props;
@@ -80,35 +79,29 @@ int cbfs_boot_locate(struct region_device *fh, const char *name, uint32_t *type)
 	if (rdev_chain(&rdev, boot_dev, props.offset, props.size))
 		return -1;
 
-	cbfs.rdev = &rdev;
-
-	return cbfs_locate(fh, &cbfs, name, type);
+	return cbfs_locate(fh, &rdev, name, type);
 }
 
 void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size)
 {
-	struct region_device fh;
+	struct cbfsf fh;
 	size_t fsize;
 
 	if (cbfs_boot_locate(&fh, name, &type))
 		return NULL;
 
-	fsize = region_device_sz(&fh);
+	fsize = region_device_sz(&fh.data);
 
 	if (size != NULL)
 		*size = fsize;
 
-	return rdev_mmap(&fh, 0, fsize);
+	return rdev_mmap(&fh.data, 0, fsize);
 }
 
-int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
+int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
 		const char *name, uint32_t *type)
 {
-	size_t offset;
-	const struct region_device *rd;
-
-	offset = 0;
-	rd = cbfs->rdev;
+	size_t offset = 0;
 
 	LOG("Locating '%s'\n", name);
 
@@ -123,12 +116,12 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		mapping = rdev_mmap(rd, offset, fsz);
+		mapping = rdev_mmap(cbfs, offset, fsz);
 		/* Can't read file. Nothing else to do but bail out. */
 		if (mapping == NULL)
 			break;
 		cbfs_file_deserialize(&file, mapping);
-		rdev_munmap(rd, mapping);
+		rdev_munmap(cbfs, mapping);
 
 		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
 			offset++;
@@ -137,13 +130,13 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 		}
 
 		/* See if names match. */
-		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
+		fname = rdev_mmap(cbfs, offset + fsz, file.offset - fsz);
 
 		if (fname == NULL)
 			break;
 
 		name_match = !strcmp(fname, name);
-		rdev_munmap(rd, fname);
+		rdev_munmap(cbfs, fname);
 
 		if (!name_match) {
 			DEBUG(" Unmatched '%s' at %zx\n", fname, offset);
@@ -160,11 +153,13 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 		}
 
 		LOG("Found @ offset %zx size %x\n", offset, file.len);
-		/* File and type match. Create a chained region_device to
-		 * represent the cbfs file. */
+		/* File and type match. Keep track of both the metadata and
+		 * the data for the file. */
+		if (rdev_chain(&fh->metadata, cbfs, offset, file.offset))
+			break;
 		offset += file.offset;
 		datasz = file.len;
-		if (rdev_chain(fh, rd, offset, datasz))
+		if (rdev_chain(&fh->data, cbfs, offset, datasz))
 			break;
 
 		/* Success. */
@@ -209,12 +204,16 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
 
 void *cbfs_boot_load_stage_by_name(const char *name)
 {
+	struct cbfsf fh;
 	struct prog stage = PROG_INIT(ASSET_UNKNOWN, name);
 	uint32_t type = CBFS_TYPE_STAGE;
 
-	if (cbfs_boot_locate(&stage.asset.rdev, name, &type))
+	if (cbfs_boot_locate(&fh, name, &type))
 		return NULL;
 
+	/* Chain data portion in the prog. */
+	cbfs_file_data(prog_rdev(&stage), &fh);
+
 	if (cbfs_prog_stage_load(&stage))
 		return NULL;
 
@@ -228,7 +227,7 @@ int cbfs_prog_stage_load(struct prog *pstage)
 	void *entry;
 	size_t fsize;
 	size_t foffset;
-	const struct region_device *fh = &pstage->asset.rdev;
+	const struct region_device *fh = prog_rdev(pstage);
 
 	if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage))
 		return 0;
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index d1f2e49..c8dfad1 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -164,15 +164,15 @@ static void fsp_cache_save(struct prog *fsp)
 
 static int fsp_find_and_relocate(struct prog *fsp)
 {
-	struct region_device fsp_rdev;
+	struct cbfsf fsp_file;
 	uint32_t type = CBFS_TYPE_FSP;
 
-	if (cbfs_boot_locate(&fsp_rdev, prog_name(fsp), &type)) {
+	if (cbfs_boot_locate(&fsp_file, prog_name(fsp), &type)) {
 		printk(BIOS_ERR, "ERROR: Couldn't find fsp.bin in CBFS.\n");
 		return -1;
 	}
 
-	if (fsp_relocate(fsp, &fsp_rdev)) {
+	if (fsp_relocate(fsp, &fsp_file.data)) {
 		printk(BIOS_ERR, "ERROR: FSP relocation failed.\n");
 		return -1;
 	}
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index e133b48..b003ec1 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -77,6 +77,7 @@ int ccplex_load_mts(void)
 {
 	ssize_t nread;
 	struct stopwatch sw;
+	struct cbfsf mts_file;
 	struct region_device fh;
 
 	/*
@@ -87,11 +88,13 @@ int ccplex_load_mts(void)
 	void * const mts = (void *)(uintptr_t)MTS_LOAD_ADDRESS;
 
 	stopwatch_init(&sw);
-	if (cbfs_boot_locate(&fh, MTS_FILE_NAME, NULL)) {
+	if (cbfs_boot_locate(&mts_file, MTS_FILE_NAME, NULL)) {
 		printk(BIOS_DEBUG, "MTS file not found: %s\n", MTS_FILE_NAME);
 		return -1;
 	}
 
+	cbfs_file_data(&fh, &mts_file);
+
 	/* Read MTS file into the carveout region. */
 	nread = rdev_readat(&fh, mts, 0, region_device_sz(&fh));
 
diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c
index fb6c9cb..b402a14 100644
--- a/src/soc/nvidia/tegra210/mtc.c
+++ b/src/soc/nvidia/tegra210/mtc.c
@@ -33,16 +33,19 @@ int tegra210_run_mtc(void)
 {
 	ssize_t nread;
 	struct region_device fh;
+	struct cbfsf mtc_file;
 
 	void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS;
 	void *dvfs_table;
 	size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc;
 
-	if (cbfs_boot_locate(&fh, "tegra_mtc.bin", NULL)) {
+	if (cbfs_boot_locate(&mtc_file, "tegra_mtc.bin", NULL)) {
 		printk(BIOS_ERR, "MTC file not found: tegra_mtc.bin\n");
 		return -1;
 	}
 
+	cbfs_file_data(&fh, &mtc_file);
+
 	/* Read MTC file into predefined region. */
 	nread = rdev_readat(&fh, mtc, 0, region_device_sz(&fh));
 
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
index 90ada1e..ff72693 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
@@ -73,6 +73,7 @@ static int vboot_active(struct asset *asset)
 	if (run_verification) {
 		verstage_main();
 	} else if (verstage_should_load()) {
+		struct cbfsf file;
 		struct prog verstage =
 			PROG_INIT(ASSET_VERSTAGE,
 				CONFIG_CBFS_PREFIX "/verstage");
@@ -80,9 +81,12 @@ static int vboot_active(struct asset *asset)
 		printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n");
 
 		/* load verstage from RO */
-		if (cbfs_boot_locate(prog_rdev(&verstage),
-						prog_name(&verstage), NULL) ||
-		    cbfs_prog_stage_load(&verstage))
+		if (cbfs_boot_locate(&file, prog_name(&verstage), NULL))
+			die("failed to load verstage");
+
+		cbfs_file_data(&prog_rdev(&verstage), &file);
+
+		if (cbfs_prog_stage_load(&verstage))
 			die("failed to load verstage");
 
 		/* verify and select a slot */
@@ -162,9 +166,9 @@ static int vboot_locate_by_components(const struct region_device *fw_main,
 static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main,
 					struct asset *asset)
 {
-	struct cbfsd cbfs;
 	struct region_device rdev;
 	struct cbfs_props props;
+	struct cbfsf file;
 
 	if (cbfs_boot_region_properties(&props))
 		return -1;
@@ -172,9 +176,11 @@ static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main,
 	if (rdev_chain(&rdev, fw_main, props.offset, props.size))
 		return -1;
 
-	cbfs.rdev = &rdev;
+	if (cbfs_locate(file, &cbfs, asset_name(asset), NULL))
+		return -1;
 
-	return cbfs_locate(asset_rdev(asset), &cbfs, asset_name(asset), NULL);
+	cbfs_file_data(asset_rdev(asset), &file);
+	return 0;
 }
 
 static int vboot_asset_locate(const struct region_device *fw_main,


From gerrit at coreboot.org  Thu Sep 17 22:36:20 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 22:36:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: link
	bootblock.elf with .data and .bss sections again
References: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+0@gerrit.coreboot.org>
Message-ID: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11680

-gerrit

commit ef5737858eaf8cb734d1fb2be181ec3d080c32b5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 17:02:53 2015 -0500

    linking: link bootblock.elf with .data and .bss sections again
    
    Currently coreboot expects the loader to clear the bss section
    for all stages. i.e. stages don't clear their own bss. On ARM
    SoCs the BootROM would be responsible for this. To do that
    one needs to include the bss section data (all zeros) in the
    bootblock.bin file. This was previously being attempted by
    keeping the .bss info in the .data section because objcopy
    happened zero out non-file allocated data section data.
    
    Instead go back to linking bootblock with the bss section
    but mark the bss section as loadable allocatable data. That
    way it will be included in the binary properly when objcopy
    -O binary is emplyed. Also do the same for the data section
    in the case of no non-zero object values are in the data
    section.
    
    Without this change the trick of including .bss in .data
    was not working when there wasn't a non-zero value object
    in the data section.
    
    BUG=None
    BRANCH=None
    TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
         the cleared bss.
    
    Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc       | 12 ++++++++++++
 src/lib/program.ld |  7 -------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 81c149d..55635ba 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -531,6 +531,18 @@ find-substr = $(word 1,$(subst _, ,$(1)))
 # and remove .x the next time and finally return romstage
 find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call find-substr,$(1))),$(call find-class,$(basename $(1))))
 
+# Bootblocks are not CBFS stages. coreboot is currently expecting the bss to
+# be cleared by the loader of the stage. For ARM SoCs that means one needs to
+# include the bss section in the binary so the BootROM clears the bss on
+# loading of the bootblock stage. Achieve this by marking the bss section
+# loadable,allocatable, and data. Do the same for the .data section in case
+# it's marked as NOBITS.
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf
+	$(eval class := $(call find-class,$(@F)))
+	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
+	$(OBJCOPY_$(class)) --set-section-flags .bss=load,alloc,data --set-section-flags .data=loa,alloc,data $< $<.tmp
+	$(OBJCOPY_$(class)) -O binary $<.tmp $@
+
 $(objcbfs)/%.bin: $(objcbfs)/%.elf
 	$(eval class := $(call find-class,$(@F)))
 	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
diff --git a/src/lib/program.ld b/src/lib/program.ld
index c8ce5ee..ab36239 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -111,14 +111,7 @@
 #endif
 
 #if ARCH_STAGE_HAS_BSS_SECTION
-#if ENV_BOOTBLOCK
-/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
- * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
- * the BSS into the .data section so those zeroes get loaded explicitly. */
-.data . : {
-#else
 .bss . : {
-#endif
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bss = .;
 	*(.bss)


From gerrit at coreboot.org  Thu Sep 17 22:36:21 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 17 Sep 2015 22:36:21 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfs: add struct
	cbfsf
References: <I05486c6cf6cfcafa5c64b36324833b2374f763c2+0@gerrit.coreboot.org>
Message-ID: <I05486c6cf6cfcafa5c64b36324833b2374f763c2+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11679

-gerrit

commit 94f3382e6df5380851b78df90d1ee4e7e820115e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 16:09:30 2015 -0500

    cbfs: add struct cbfsf
    
    Now that cbfs is adding more metadata in the cbfs file
    header one needs to access that metadata. Therefore,
    add struct cbfsf which tracks the metadata and data
    of the file separately. Note that stage and payload
    metadata specific to itself is still contained within
    the 'data' portion of a cbfs file. Update the cbfs
    API to use struct cbfsf. Additionally, remove struct
    cbfsd as there's nothing else associated with a cbfs
    region aside from offset and size which tracked
    by a region_device (thanks, CBFS_ALIGNMENT!).
    
    BUG=None
    BRANCH=None
    TEST=Built and booted through end of ramstage on qemu armv7.
         Built and booted glados using Chrome OS.
    
    Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/cbfs.h                                 | 20 ++++++----
 src/lib/assets.c                                   |  9 ++++-
 src/lib/cbfs.c                                     | 45 +++++++++++-----------
 src/soc/intel/common/fsp_ramstage.c                |  6 +--
 src/soc/nvidia/tegra132/ccplex.c                   |  5 ++-
 src/soc/nvidia/tegra210/mtc.c                      |  5 ++-
 .../google/chromeos/vboot2/vboot_loader.c          | 18 ++++++---
 7 files changed, 66 insertions(+), 42 deletions(-)

diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f23a82a..5d60716 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -30,8 +30,8 @@
  * - cbfsd which is a descriptor for representing a cbfs instance
  */
 
-/* Descriptor for cbfs lookup operations. */
-struct cbfsd;
+/* Object representing cbfs files. */
+struct cbfsf;
 
 /***********************************************
  * Perform CBFS operations on the boot device. *
@@ -43,8 +43,7 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device);
  * failure. */
 void *cbfs_boot_load_stage_by_name(const char *name);
 /* Locate file by name and optional type. Return 0 on success. < 0 on error. */
-int cbfs_boot_locate(struct region_device *fh, const char *name,
-			uint32_t *type);
+int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type);
 /* Map file into memory leaking the mapping. Only should be used when
  * leaking mappings are a no-op. Returns NULL on error, else returns
  * the mapping and sets the size of the file. */
@@ -55,7 +54,7 @@ int cbfs_prog_stage_load(struct prog *prog);
 
 /* Locate file by name and optional type. Returns 0 on succcess else < 0 on
  * error.*/
-int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
+int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
 		const char *name, uint32_t *type);
 
 /*****************************************************************
@@ -64,10 +63,17 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
  * API.                                                          *
  *****************************************************************/
 
-struct cbfsd {
-	const struct region_device *rdev;
+struct cbfsf {
+	struct region_device metadata;
+	struct region_device data;
 };
 
+static inline void cbfs_file_data(struct region_device *data,
+					const struct cbfsf *file)
+{
+	rdev_chain(data, &file->data, 0, region_device_sz(&file->data));
+}
+
 /* The cbfs_props struct describes the properties associated with a CBFS. */
 struct cbfs_props {
 	/* CBFS starts at the following offset within the boot region. */
diff --git a/src/lib/assets.c b/src/lib/assets.c
index 656f0b1..0115243 100644
--- a/src/lib/assets.c
+++ b/src/lib/assets.c
@@ -31,7 +31,14 @@
 #if DEFAULT_CBFS_PROVIDER_PRESENT
 static int cbfs_boot_asset_locate(struct asset *asset)
 {
-	return cbfs_boot_locate(&asset->rdev, asset->name, NULL);
+	struct cbfsf file;
+
+	if (cbfs_boot_locate(&file, asset_name(asset), NULL))
+		return -1;
+
+	cbfs_file_data(asset_rdev(asset), &file);
+
+	return 0;
 }
 
 static const struct asset_provider cbfs_default_provider = {
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index c4eff5b..e6d9a7c 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -59,9 +59,8 @@ static void cbfs_file_deserialize(struct cbfs_file *f, void *from)
 	f->offset = read_at_be32(from, off);
 }
 
-int cbfs_boot_locate(struct region_device *fh, const char *name, uint32_t *type)
+int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
 {
-	struct cbfsd cbfs;
 	struct region_device rdev;
 	const struct region_device *boot_dev;
 	struct cbfs_props props;
@@ -80,35 +79,29 @@ int cbfs_boot_locate(struct region_device *fh, const char *name, uint32_t *type)
 	if (rdev_chain(&rdev, boot_dev, props.offset, props.size))
 		return -1;
 
-	cbfs.rdev = &rdev;
-
-	return cbfs_locate(fh, &cbfs, name, type);
+	return cbfs_locate(fh, &rdev, name, type);
 }
 
 void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size)
 {
-	struct region_device fh;
+	struct cbfsf fh;
 	size_t fsize;
 
 	if (cbfs_boot_locate(&fh, name, &type))
 		return NULL;
 
-	fsize = region_device_sz(&fh);
+	fsize = region_device_sz(&fh.data);
 
 	if (size != NULL)
 		*size = fsize;
 
-	return rdev_mmap(&fh, 0, fsize);
+	return rdev_mmap(&fh.data, 0, fsize);
 }
 
-int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
+int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
 		const char *name, uint32_t *type)
 {
-	size_t offset;
-	const struct region_device *rd;
-
-	offset = 0;
-	rd = cbfs->rdev;
+	size_t offset = 0;
 
 	LOG("Locating '%s'\n", name);
 
@@ -123,12 +116,12 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 
 		DEBUG("Checking offset %zx\n", offset);
 
-		mapping = rdev_mmap(rd, offset, fsz);
+		mapping = rdev_mmap(cbfs, offset, fsz);
 		/* Can't read file. Nothing else to do but bail out. */
 		if (mapping == NULL)
 			break;
 		cbfs_file_deserialize(&file, mapping);
-		rdev_munmap(rd, mapping);
+		rdev_munmap(cbfs, mapping);
 
 		if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) {
 			offset++;
@@ -137,13 +130,13 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 		}
 
 		/* See if names match. */
-		fname = rdev_mmap(rd, offset + fsz, file.offset - fsz);
+		fname = rdev_mmap(cbfs, offset + fsz, file.offset - fsz);
 
 		if (fname == NULL)
 			break;
 
 		name_match = !strcmp(fname, name);
-		rdev_munmap(rd, fname);
+		rdev_munmap(cbfs, fname);
 
 		if (!name_match) {
 			DEBUG(" Unmatched '%s' at %zx\n", fname, offset);
@@ -160,11 +153,13 @@ int cbfs_locate(struct region_device *fh, const struct cbfsd *cbfs,
 		}
 
 		LOG("Found @ offset %zx size %x\n", offset, file.len);
-		/* File and type match. Create a chained region_device to
-		 * represent the cbfs file. */
+		/* File and type match. Keep track of both the metadata and
+		 * the data for the file. */
+		if (rdev_chain(&fh->metadata, cbfs, offset, file.offset))
+			break;
 		offset += file.offset;
 		datasz = file.len;
-		if (rdev_chain(fh, rd, offset, datasz))
+		if (rdev_chain(&fh->data, cbfs, offset, datasz))
 			break;
 
 		/* Success. */
@@ -209,12 +204,16 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
 
 void *cbfs_boot_load_stage_by_name(const char *name)
 {
+	struct cbfsf fh;
 	struct prog stage = PROG_INIT(ASSET_UNKNOWN, name);
 	uint32_t type = CBFS_TYPE_STAGE;
 
-	if (cbfs_boot_locate(&stage.asset.rdev, name, &type))
+	if (cbfs_boot_locate(&fh, name, &type))
 		return NULL;
 
+	/* Chain data portion in the prog. */
+	cbfs_file_data(prog_rdev(&stage), &fh);
+
 	if (cbfs_prog_stage_load(&stage))
 		return NULL;
 
@@ -228,7 +227,7 @@ int cbfs_prog_stage_load(struct prog *pstage)
 	void *entry;
 	size_t fsize;
 	size_t foffset;
-	const struct region_device *fh = &pstage->asset.rdev;
+	const struct region_device *fh = prog_rdev(pstage);
 
 	if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage))
 		return 0;
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index d1f2e49..c8dfad1 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -164,15 +164,15 @@ static void fsp_cache_save(struct prog *fsp)
 
 static int fsp_find_and_relocate(struct prog *fsp)
 {
-	struct region_device fsp_rdev;
+	struct cbfsf fsp_file;
 	uint32_t type = CBFS_TYPE_FSP;
 
-	if (cbfs_boot_locate(&fsp_rdev, prog_name(fsp), &type)) {
+	if (cbfs_boot_locate(&fsp_file, prog_name(fsp), &type)) {
 		printk(BIOS_ERR, "ERROR: Couldn't find fsp.bin in CBFS.\n");
 		return -1;
 	}
 
-	if (fsp_relocate(fsp, &fsp_rdev)) {
+	if (fsp_relocate(fsp, &fsp_file.data)) {
 		printk(BIOS_ERR, "ERROR: FSP relocation failed.\n");
 		return -1;
 	}
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index e133b48..b003ec1 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -77,6 +77,7 @@ int ccplex_load_mts(void)
 {
 	ssize_t nread;
 	struct stopwatch sw;
+	struct cbfsf mts_file;
 	struct region_device fh;
 
 	/*
@@ -87,11 +88,13 @@ int ccplex_load_mts(void)
 	void * const mts = (void *)(uintptr_t)MTS_LOAD_ADDRESS;
 
 	stopwatch_init(&sw);
-	if (cbfs_boot_locate(&fh, MTS_FILE_NAME, NULL)) {
+	if (cbfs_boot_locate(&mts_file, MTS_FILE_NAME, NULL)) {
 		printk(BIOS_DEBUG, "MTS file not found: %s\n", MTS_FILE_NAME);
 		return -1;
 	}
 
+	cbfs_file_data(&fh, &mts_file);
+
 	/* Read MTS file into the carveout region. */
 	nread = rdev_readat(&fh, mts, 0, region_device_sz(&fh));
 
diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c
index fb6c9cb..b402a14 100644
--- a/src/soc/nvidia/tegra210/mtc.c
+++ b/src/soc/nvidia/tegra210/mtc.c
@@ -33,16 +33,19 @@ int tegra210_run_mtc(void)
 {
 	ssize_t nread;
 	struct region_device fh;
+	struct cbfsf mtc_file;
 
 	void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS;
 	void *dvfs_table;
 	size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc;
 
-	if (cbfs_boot_locate(&fh, "tegra_mtc.bin", NULL)) {
+	if (cbfs_boot_locate(&mtc_file, "tegra_mtc.bin", NULL)) {
 		printk(BIOS_ERR, "MTC file not found: tegra_mtc.bin\n");
 		return -1;
 	}
 
+	cbfs_file_data(&fh, &mtc_file);
+
 	/* Read MTC file into predefined region. */
 	nread = rdev_readat(&fh, mtc, 0, region_device_sz(&fh));
 
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
index 90ada1e..2439af2 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
@@ -73,6 +73,7 @@ static int vboot_active(struct asset *asset)
 	if (run_verification) {
 		verstage_main();
 	} else if (verstage_should_load()) {
+		struct cbfsf file;
 		struct prog verstage =
 			PROG_INIT(ASSET_VERSTAGE,
 				CONFIG_CBFS_PREFIX "/verstage");
@@ -80,9 +81,12 @@ static int vboot_active(struct asset *asset)
 		printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n");
 
 		/* load verstage from RO */
-		if (cbfs_boot_locate(prog_rdev(&verstage),
-						prog_name(&verstage), NULL) ||
-		    cbfs_prog_stage_load(&verstage))
+		if (cbfs_boot_locate(&file, prog_name(&verstage), NULL))
+			die("failed to load verstage");
+
+		cbfs_file_data(prog_rdev(&verstage), &file);
+
+		if (cbfs_prog_stage_load(&verstage))
 			die("failed to load verstage");
 
 		/* verify and select a slot */
@@ -162,9 +166,9 @@ static int vboot_locate_by_components(const struct region_device *fw_main,
 static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main,
 					struct asset *asset)
 {
-	struct cbfsd cbfs;
 	struct region_device rdev;
 	struct cbfs_props props;
+	struct cbfsf file;
 
 	if (cbfs_boot_region_properties(&props))
 		return -1;
@@ -172,9 +176,11 @@ static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main,
 	if (rdev_chain(&rdev, fw_main, props.offset, props.size))
 		return -1;
 
-	cbfs.rdev = &rdev;
+	if (cbfs_locate(&file, &rdev, asset_name(asset), NULL))
+		return -1;
 
-	return cbfs_locate(asset_rdev(asset), &cbfs, asset_name(asset), NULL);
+	cbfs_file_data(asset_rdev(asset), &file);
+	return 0;
 }
 
 static int vboot_asset_locate(const struct region_device *fw_main,


From gerrit at coreboot.org  Fri Sep 18 00:34:23 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Fri, 18 Sep 2015 00:34:23 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: link
	bootblock.elf with .data and .bss sections again
References: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+0@gerrit.coreboot.org>
Message-ID: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11680

-gerrit

commit 9ec6d72cefb3b9d098c86e346328f8be83dddaea
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 17:02:53 2015 -0500

    linking: link bootblock.elf with .data and .bss sections again
    
    Currently coreboot expects the loader to clear the bss section
    for all stages. i.e. stages don't clear their own bss. On ARM
    SoCs the BootROM would be responsible for this. To do that
    one needs to include the bss section data (all zeros) in the
    bootblock.bin file. This was previously being attempted by
    keeping the .bss info in the .data section because objcopy
    happened zero out non-file allocated data section data.
    
    Instead go back to linking bootblock with the bss section
    but mark the bss section as loadable allocatable data. That
    way it will be included in the binary properly when objcopy
    -O binary is emplyed. Also do the same for the data section
    in the case of no non-zero object values are in the data
    section.
    
    Without this change the trick of including .bss in .data
    was not working when there wasn't a non-zero value object
    in the data section.
    
    BUG=None
    BRANCH=None
    TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
         the cleared bss.
    
    Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                            | 17 +++++++++++++----
 src/lib/program.ld                      |  7 -------
 src/soc/broadcom/cygnus/Makefile.inc    |  6 +-----
 src/soc/imgtec/pistachio/Makefile.inc   |  8 +-------
 src/soc/marvell/bg4cd/Makefile.inc      |  3 ---
 src/soc/nvidia/tegra124/Makefile.inc    |  3 ---
 src/soc/nvidia/tegra132/Makefile.inc    |  3 ---
 src/soc/qualcomm/ipq806x/Makefile.inc   |  8 +-------
 src/soc/rockchip/rk3288/Makefile.inc    |  3 ---
 src/soc/samsung/exynos5250/Makefile.inc |  3 ---
 src/soc/samsung/exynos5420/Makefile.inc |  3 ---
 11 files changed, 16 insertions(+), 48 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 81c149d..069de39 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -531,10 +531,19 @@ find-substr = $(word 1,$(subst _, ,$(1)))
 # and remove .x the next time and finally return romstage
 find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call find-substr,$(1))),$(call find-class,$(basename $(1))))
 
-$(objcbfs)/%.bin: $(objcbfs)/%.elf
-	$(eval class := $(call find-class,$(@F)))
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_$(class)) -O binary $< $@
+# Bootblocks are not CBFS stages. coreboot is currently expecting the bss to
+# be cleared by the loader of the stage. For ARM SoCs that means one needs to
+# include the bss section in the binary so the BootROM clears the bss on
+# loading of the bootblock stage. Achieve this by marking the bss section
+# loadable,allocatable, and data. Do the same for the .data section in case
+# it's marked as NOBITS.
+$(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.elf
+	@printf "    OBJCOPY    $(notdir $(@))\n"
+	$(OBJCOPY_bootblock) --set-section-flags .bss=load,alloc,data --set-section-flags .data=loa,alloc,data $< $<.tmp
+	$(OBJCOPY_bootblock) -O binary $<.tmp $@
+
+$(objcbfs)/%.bin: $(objcbfs)/%.raw.bin
+	cp $< $@
 
 $(objcbfs)/%.elf: $(objcbfs)/%.debug
 	$(eval class := $(call find-class,$(@F)))
diff --git a/src/lib/program.ld b/src/lib/program.ld
index c8ce5ee..ab36239 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -111,14 +111,7 @@
 #endif
 
 #if ARCH_STAGE_HAS_BSS_SECTION
-#if ENV_BOOTBLOCK
-/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
- * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
- * the BSS into the .data section so those zeroes get loaded explicitly. */
-.data . : {
-#else
 .bss . : {
-#endif
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bss = .;
 	*(.bss)
diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc
index ff231f7..8bad15f 100644
--- a/src/soc/broadcom/cygnus/Makefile.inc
+++ b/src/soc/broadcom/cygnus/Makefile.inc
@@ -62,10 +62,6 @@ ramstage-y += usb.c
 
 CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
 
-$(objcbfs)/bootblock.tmp: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@
-
 ifneq ($(V),1)
 redirect := > /dev/null
 endif
@@ -96,7 +92,7 @@ endif
 #   SLEEP		1
 #   DEEP_SLEEP		2
 #   EXCEPTION		4
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.tmp \
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
 		$(objutil)/broadcom/secimage/secimage \
 		util/broadcom/unauth.cfg \
 		util/broadcom/khmacsha256
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index df9fbcf..7f06db5 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -46,14 +46,8 @@ romstage-y += monotonic_timer.c
 
 CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/
 
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@.tmp
-	@mv $@.tmp $@
-
 # Create a complete bootblock which will start up the system
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BIMGTOOL)
 	@printf "    BIMGTOOL   $(subst $(obj)/,,$(@))\n"
 	$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
 
diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc
index 1a801c0..ded1917 100644
--- a/src/soc/marvell/bg4cd/Makefile.inc
+++ b/src/soc/marvell/bg4cd/Makefile.inc
@@ -45,9 +45,6 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c
 
 CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "Generating: $(subst $(obj)/,,$(@))\n"
 	@mkdir -p $(dir $@)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 46ce59d..38ba4f6 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -84,9 +84,6 @@ CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/
 # package up the image pull in bootblock.bin, it will be this wrapped version
 # instead of the raw bootblock.
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
 	@printf "    CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
 	$(CBOOTIMAGE) -gbct --soc tegra124 $< $@
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index c192055..bdd8074 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -121,9 +121,6 @@ CBOOTIMAGE_OPTS = --soc tegra132
 # package up the image pull in bootblock.bin, it will be this wrapped version
 # instead of the raw bootblock.
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
 	@printf "    CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
 	$(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 84eae0b..83b5e06 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -56,14 +56,8 @@ ramstage-y += tz_wrapper.S
 
 ifeq ($(CONFIG_USE_BLOBS),y)
 
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@.tmp
-	@mv $@.tmp $@
-
 # Add MBN header to allow SBL3 to start coreboot bootblock
-$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
+$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin
 	@printf "    ADD MBN    $(subst $(obj)/,,$(@))\n"
 	./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
 	@mv $@.tmp $@
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index cd523b0..830ae1e 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -75,9 +75,6 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "Generating: $(subst $(obj)/,,$(@))\n"
 	@mkdir -p $(dir $@)
diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc
index 9f49134..2731f17 100644
--- a/src/soc/samsung/exynos5250/Makefile.inc
+++ b/src/soc/samsung/exynos5250/Makefile.inc
@@ -46,9 +46,6 @@ ramstage-y += cbmem.c
 
 CPPFLAGS_common += -Isrc/soc/samsung/exynos5250/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "    BL1, CKSUM $(subst $(obj)/,,$(@))\n"
 	util/exynos/fixed_cksum.py $< $<.cksum 32768
diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc
index 753e6d0..498e8d1 100644
--- a/src/soc/samsung/exynos5420/Makefile.inc
+++ b/src/soc/samsung/exynos5420/Makefile.inc
@@ -48,9 +48,6 @@ rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c
 
 CPPFLAGS_common += -Isrc/soc/samsung/exynos5420/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "    BL1, CKSUM $(subst $(obj)/,,$(@))\n"
 	util/exynos/variable_cksum.py $< $<.cksum


From gerrit at coreboot.org  Fri Sep 18 05:25:36 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Fri, 18 Sep 2015 05:25:36 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: xcompile:
	Redirect the objdump stderr to /dev/null
References: <I9940f069f66e097973ed6138cf3c696087fa5531+0@gerrit.coreboot.org>
Message-ID: <I9940f069f66e097973ed6138cf3c696087fa5531+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11681

-gerrit

commit 7b5d27c07fa0796ec18e08211c3139938b2b5a43
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 18 06:17:09 2015 -0700

    xcompile: Redirect the objdump stderr to /dev/null
    
    On system with clang, "as" is available but "objdump" is not by default.
    So if ${gccprefix} is empty, "as" can run successfully and the "objdump"
    below might report error. Mask that output.
    
    Change-Id: I9940f069f66e097973ed6138cf3c696087fa5531
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/xcompile/xcompile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 46a30d1..d664464 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -115,7 +115,7 @@ testas() {
 		2>/dev/null || return 1
 
 	# Check output content type.
-	local obj_type="$(LANG=C LC_ALL= ${gccprefix}objdump -p $obj_file)"
+	local obj_type="$(LANG=C LC_ALL= ${gccprefix}objdump -p $obj_file 2>/dev/null)"
 	local obj_arch="$(expr "$obj_type" : '.*format \(.[a-z0-9-]*\)')"
 	[ "$obj_arch" = "$full_arch" ] || return 1
 


From gerrit at coreboot.org  Fri Sep 18 10:34:49 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Fri, 18 Sep 2015 10:34:49 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: Build
	with -Wno-error=implicit-function-declaration
References: <Idaf4236fa107c6f809c6d0b15eb62e4c090fde09+0@gerrit.coreboot.org>
Message-ID: <Idaf4236fa107c6f809c6d0b15eb62e4c090fde09+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11682

-gerrit

commit 10c429cd50d603d2138f2b110891ec14e4078a07
Author: Nico Huber <nico.huber at secunet.com>
Date:   Fri Sep 18 12:28:34 2015 +0200

    cbfstool: Build with -Wno-error=implicit-function-declaration
    
    I don't like it but some versions of yacc/bison just don't declare
    yyparse().
    
    Change-Id: Idaf4236fa107c6f809c6d0b15eb62e4c090fde09
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 util/cbfstool/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 2a3dedf..49fdeaa 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -45,6 +45,7 @@ rmodobj += xdr.o
 TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra
 TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
 TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings
+TOOLCFLAGS += -Wno-error=implicit-function-declaration
 TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h
 TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap


From gerrit at coreboot.org  Sat Sep 19 12:07:13 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 19 Sep 2015 12:07:13 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	introduce new file types
References: <I1b4149c7f3b8564ee358a2c18ba91e6a7a6797da+0@gerrit.coreboot.org>
Message-ID: <E1ZdGvB-0007ZN-KJ@mail.coreboot.org>

the following patch was just integrated into master:
commit 239c74231b7758a2eea99ccb327c4f8f1482503b
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 9 20:11:26 2015 +0200

    cbfstool: introduce new file types
    
    Let's move x86 style bootblocks (and later the others) and the master header
    into the CBFS structure. Prepare for this by adding file types.
    
    Change-Id: I1b4149c7f3b8564ee358a2c18ba91e6a7a6797da
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11627
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11627 for details.

-gerrit


From gerrit at coreboot.org  Sat Sep 19 14:05:29 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sat, 19 Sep 2015 14:05:29 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Kconfig: Add
	ROM_START variable
References: <Icc747eccf4263875f15806fcb38ec29e4665cf11+0@gerrit.coreboot.org>
Message-ID: <Icc747eccf4263875f15806fcb38ec29e4665cf11+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11630

-gerrit

commit 832f657ac8dec9b30d94adfbf3c795d02005bcb9
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 15:29:42 2015 +0200

    Kconfig: Add ROM_START variable
    
    It's automatically derived from ROM_SIZE and specifies the offset of
    flash in memory. On non-x86 that's 0, on x86 it's 4GB-ROM_SIZE.
    
    Change-Id: Icc747eccf4263875f15806fcb38ec29e4665cf11
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/mainboard/Kconfig | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index ab8ee26..3098803 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -128,6 +128,20 @@ config ROM_SIZE
 	default 0xc00000 if COREBOOT_ROMSIZE_KB_12288
 	default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
 
+config ROM_START
+	hex
+	default 0 if !ARCH_X86
+	default 0xffff0000 if COREBOOT_ROMSIZE_KB_64
+	default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+	default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+	default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+	default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+	default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+	default 0xffc00000 if COREBOOT_ROMSIZE_KB_4096
+	default 0xff800000 if COREBOOT_ROMSIZE_KB_8192
+	default 0xff400000 if COREBOOT_ROMSIZE_KB_12288
+	default 0xff000000 if COREBOOT_ROMSIZE_KB_16384
+
 config ENABLE_POWER_BUTTON
 	bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
 	default y if POWER_BUTTON_DEFAULT_ENABLE


From gerrit at coreboot.org  Sat Sep 19 14:05:31 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sat, 19 Sep 2015 14:05:31 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: add new
	add-master-header command
References: <I5bc7fbcb5962b35a95261f30f0c93008e760680d+0@gerrit.coreboot.org>
Message-ID: <I5bc7fbcb5962b35a95261f30f0c93008e760680d+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11628

-gerrit

commit e060717dcad860d168847753c701682b6fe9ec52
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Thu Sep 10 15:28:27 2015 +0200

    cbfstool: add new add-master-header command
    
    The command adds a new cbfs file, fills in the CBFS meta data in cbfs
    master header format, then points the master header pointer (which
    resides at the last 4 bytes of the CBFS region) to the data area of the
    new file.
    
    This can leak some space in CBFS if an old-style CBFS with native master
    header gets the treatment, because a new header is created and pointed
    at. flashmap based images have no such header, and the attempt to create
    a second file with the (hardcoded) name will fail.
    
    Change-Id: I5bc7fbcb5962b35a95261f30f0c93008e760680d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfstool.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index c45f316..2bb8edc 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -19,6 +19,7 @@
  * Foundation, Inc.
  */
 
+#include <endian.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
@@ -211,6 +212,72 @@ done:
 	return ret;
 }
 
+static int cbfs_add_master_header(void)
+{
+	const char * const name = "cbfs master header";
+	struct cbfs_image image;
+	struct cbfs_file *header = NULL;
+	struct buffer buffer;
+	int ret = 1;
+
+	if (cbfs_image_from_buffer(&image, param.image_region,
+		param.headeroffset)) {
+		ERROR("Selected image region is not a CBFS.\n");
+		return 1;
+	}
+
+	if (cbfs_get_entry(&image, name)) {
+		ERROR("'%s' already in ROM image.\n", name);
+		return 1;
+	}
+
+	if (buffer_create(&buffer, sizeof(struct cbfs_header), name) != 0)
+		return 1;
+
+	struct cbfs_header *h = (struct cbfs_header *)buffer.data;
+	h->magic = htonl(CBFS_HEADER_MAGIC);
+	h->version = htonl(CBFS_HEADER_VERSION);
+	h->romsize = htonl(param.image_region->size);
+	/* The 4 bytes are left out for two reasons:
+	 * 1. the cbfs master header pointer resides there
+	 * 2. some cbfs implementations assume that an image that resides
+	 *    below 4GB has a bootblock and get confused when the end of the
+	 *    image is at 4GB == 0.
+	 */
+	h->bootblocksize = htonl(4);
+	h->align = htonl(CBFS_ENTRY_ALIGNMENT);
+	h->offset = htonl(param.image_region->offset);
+	h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN);
+
+	header = cbfs_create_file_header(CBFS_COMPONENT_CBFSHEADER,
+		buffer.size, name);
+	if (cbfs_add_entry(&image, &buffer, 0, header) != 0) {
+		ERROR("Failed to add cbfs master header into ROM image.\n");
+		goto done;
+	}
+
+	struct cbfs_file *entry;
+	if ((entry = cbfs_get_entry(&image, name)) == NULL) {
+		ERROR("'%s' not in ROM image?!?\n", name);
+		goto done;
+	}
+
+	uint32_t header_offset = CBFS_SUBHEADER(entry) -
+		(void *)buffer_get(&image.buffer);
+	header_offset = -(buffer_size(&image.buffer) - header_offset);
+
+	// TODO: when we have a BE target, we'll need to store this as BE
+	*(uint32_t *)(image.buffer.data + image.buffer.size - 4) =
+		htole32(header_offset);
+
+	ret = 0;
+
+done:
+	free(header);
+	buffer_delete(&buffer);
+	return ret;
+}
+
 static int cbfs_add_component(const char *filename,
 			      const char *name,
 			      uint32_t type,
@@ -831,6 +898,8 @@ static const struct command commands[] = {
 	{"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true},
 	{"add-stage", "a:H:r:f:n:t:c:b:P:S:yvh?", cbfs_add_stage, true, true},
 	{"add-int", "H:r:i:n:b:vh?", cbfs_add_integer, true, true},
+	{"add-master-header", "H:r:vh?", cbfs_add_master_header, true,
+		true},
 	{"copy", "H:D:s:h?", cbfs_copy, true, true},
 	{"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true},
 	{"extract", "H:r:n:f:vh?", cbfs_extract, true, false},
@@ -956,6 +1025,8 @@ static void usage(char *name)
 			"Add a 32bit flat mode binary\n"
 	     " add-int [-r image,regions] -i INTEGER -n NAME [-b base]     "
 			"Add a raw 64-bit integer value\n"
+	     " add-master-header [-r image,regions]                        "
+			"Add a legacy CBFS master header\n"
 	     " remove [-r image,regions] -n NAME                           "
 			"Remove a component\n"
 	     " copy -D new_header_offset -s region size \\\n"


From gerrit at coreboot.org  Sat Sep 19 14:05:32 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sat, 19 Sep 2015 14:05:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prefer
	fmap data over cbfs master header if it exists
References: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+0@gerrit.coreboot.org>
Message-ID: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11629

-gerrit

commit f76093ee1656a352385e779b6b682787a090db35
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 18:34:39 2015 +0200

    cbfstool: prefer fmap data over cbfs master header if it exists
    
    Up to now, if both fmap and a master header existed, the master header
    was used. Now, use the master header only if no fmap is found.
    
    Change-Id: Iafbf2c9dc325597e23a9780b495549b5d912e9ad
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfs_image.c       | 12 +++++++-----
 util/cbfstool/cbfstool.c         |  9 +--------
 util/cbfstool/partitioned_file.c | 15 +--------------
 util/cbfstool/partitioned_file.h | 24 +++++-------------------
 4 files changed, 14 insertions(+), 46 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 55f8084..24ab0c4 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -343,20 +343,22 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in,
 	buffer_clone(&out->buffer, in);
 	out->has_header = false;
 
+	if (cbfs_is_valid_cbfs(out)) {
+		return 0;
+	}
+
 	void *header_loc = cbfs_find_header(in->data, in->size, offset);
 	if (header_loc) {
 		cbfs_get_header(&out->header, header_loc);
 		out->has_header = true;
 		cbfs_fix_legacy_size(out, header_loc);
+		return 0;
 	} else if (offset != ~0u) {
 		ERROR("The -H switch is only valid on legacy images having CBFS master headers.\n");
 		return 1;
-	} else if (!cbfs_is_valid_cbfs(out)) {
-		ERROR("Selected image region is not a valid CBFS.\n");
-		return 1;
 	}
-
-	return 0;
+	ERROR("Selected image region is not a valid CBFS.\n");
+	return 1;
 }
 
 int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset,
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 4750666..7bd8049 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -878,12 +878,6 @@ static int cbfs_copy(void)
 	return cbfs_copy_instance(&image, param.copyoffset, param.size);
 }
 
-static bool cbfs_is_legacy_format(struct buffer *buffer)
-{
-	// Legacy CBFSes are those containing the deprecated CBFS master header.
-	return cbfs_find_header(buffer->data, buffer->size, -1);
-}
-
 static const struct command commands[] = {
 	{"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true},
 	{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
@@ -1248,8 +1242,7 @@ int main(int argc, char **argv)
 			}
 		} else {
 			param.image_file =
-				partitioned_file_reopen(image_name,
-							cbfs_is_legacy_format);
+				partitioned_file_reopen(image_name);
 		}
 		if (!param.image_file)
 			return 1;
diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c
index 9d67832..041ef11 100644
--- a/util/cbfstool/partitioned_file.c
+++ b/util/cbfstool/partitioned_file.c
@@ -165,8 +165,7 @@ partitioned_file_t *partitioned_file_create(const char *filename,
 	return file;
 }
 
-partitioned_file_t *partitioned_file_reopen(const char *filename,
-				partitioned_file_flat_decider_t flat_override)
+partitioned_file_t *partitioned_file_reopen(const char *filename)
 {
 	assert(filename);
 
@@ -174,11 +173,6 @@ partitioned_file_t *partitioned_file_reopen(const char *filename,
 	if (!file)
 		return NULL;
 
-	if (flat_override && flat_override(&file->buffer)) {
-		INFO("Opening image as a flat file in response to explicit request\n");
-		return file;
-	}
-
 	long fmap_region_offset = fmap_find((const uint8_t *)file->buffer.data,
 							file->buffer.size);
 	if (fmap_region_offset < 0) {
@@ -365,10 +359,3 @@ static bool select_parents_of(const struct fmap_area *parent, const void *arg)
 }
 const partitioned_file_fmap_selector_t partitioned_file_fmap_select_parents_of =
 							select_parents_of;
-
-static bool open_as_flat(unused struct buffer *buffer)
-{
-	return true;
-}
-const partitioned_file_flat_decider_t partitioned_file_open_as_flat =
-								open_as_flat;
diff --git a/util/cbfstool/partitioned_file.h b/util/cbfstool/partitioned_file.h
index 4583316..3698a19 100644
--- a/util/cbfstool/partitioned_file.h
+++ b/util/cbfstool/partitioned_file.h
@@ -28,15 +28,6 @@
 
 typedef struct partitioned_file partitioned_file_t;
 
-/** @return Whether the specific existing file should be opened in flat mode. */
-typedef bool (*partitioned_file_flat_decider_t)(struct buffer *buffer);
-
-/** Pass to partitioned_file_reopen() to force opening as a partitioned file. */
-#define partitioned_file_open_as_partitioned NULL
-
-/** Pass to partitioned_file_reopen() to force opening as a flat file. */
-extern const partitioned_file_flat_decider_t partitioned_file_open_as_flat;
-
 /**
  * Create a new filesystem-backed flat buffer.
  * This backwards-compatibility function creates a new in-memory buffer and
@@ -76,22 +67,17 @@ partitioned_file_t *partitioned_file_create(const char *filename,
 
 /**
  * Read a file back in from the disk.
- * An in-memory buffer is created and populated with the file's contents. If
- * flat_override is NULL and the image contains an FMAP, it will be opened as a
- * full partitioned file; otherwise, it will be opened as a flat file as if it
- * had been created by partitioned_file_create_flat(). This selection behavior
- * is extensible: if a flat_override function is provided, it is invoked before
- * searching for an FMAP, and has the option of explicitly instructing the
- * module to open the image as a flat file based on its contents.
+ * An in-memory buffer is created and populated with the file's
+ * contents. If the image contains an FMAP, it will be opened as a
+ * full partitioned file; otherwise, it will be opened as a flat file as
+ * if it had been created by partitioned_file_create_flat().
  * The partitioned_file_t returned from this function is separately owned by the
  * caller, and must later be passed to partitioned_file_close();
  *
  * @param filename      Name of the file to read in
- * @param flat_override Callback that can decide to open it as flat, or NULL
  * @return              Caller-owned partitioned file, or NULL on error
  */
-partitioned_file_t *partitioned_file_reopen(const char *filename,
-				partitioned_file_flat_decider_t flat_override);
+partitioned_file_t *partitioned_file_reopen(const char *filename);
 
 /**
  * Write a buffer's contents to its original region within a segmented file.


From gerrit at coreboot.org  Sat Sep 19 14:05:36 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sat, 19 Sep 2015 14:05:36 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: ifdfake: allow
	"base+size" description of regions
References: <Iecf8250e84d6eb267711ded446909b21147f1a9c+0@gerrit.coreboot.org>
Message-ID: <Iecf8250e84d6eb267711ded446909b21147f1a9c+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11623

-gerrit

commit 23fec99fdb6c112756fd7e8be2ea88ecfad5c609
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 13:48:24 2015 +0200

    ifdfake: allow "base+size" description of regions
    
    This is more in line with how fmd/fmap specify ranges.
    
    Change-Id: Iecf8250e84d6eb267711ded446909b21147f1a9c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/ifdfake/ifdfake.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/util/ifdfake/ifdfake.c b/util/ifdfake/ifdfake.c
index b70b6ae..7b268df 100644
--- a/util/ifdfake/ifdfake.c
+++ b/util/ifdfake/ifdfake.c
@@ -91,24 +91,39 @@ static void write_image(const region_t regions[], const char *const image)
 static int parse_region(const char *_arg, region_t *const region)
 {
 	char *const start = strdup(_arg);
+	int size_spec = 0;
+	unsigned long first, second;
 	if (!start) {
 		fprintf(stderr, "Out of memory.\n");
 		exit(EXIT_FAILURE);
 	}
 
-	char *const colon = strchr(start, ':');
+	char *colon = strchr(start, ':');
 	if (!colon) {
-		free(start);
-		return -1;
+		colon = strchr(start, '+');
+		if (!colon) {
+			free(start);
+			return -1;
+		}
+		size_spec = 1;
 	}
 	*colon = '\0';
 
 	char *const end = colon + 1;
 
 	errno = 0;
-	region->base = strtoul(start, NULL, 0);
-	region->limit = strtoul(end, NULL, 0);
-	region->size = region->limit - region->base + 1;
+	first = strtoul(start, NULL, 0);
+	second = strtoul(end, NULL, 0);
+
+	if (size_spec) {
+		region->base = first;
+		region->size = second;
+		region->limit = region->base + region->size - 1;
+	} else {
+		region->base = first;
+		region->limit = second;
+		region->size = region->limit - region->base + 1;
+	}
 
 	free(start);
 	if (errno) {


From gerrit at coreboot.org  Sat Sep 19 14:05:38 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sat, 19 Sep 2015 14:05:38 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: make
	fmap search more strict
References: <Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9+0@gerrit.coreboot.org>
Message-ID: <Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11690

-gerrit

commit e49b1f7faa770b99bbd573c97a1e42128e612fa9
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Sat Sep 19 13:59:36 2015 +0200

    cbfstool: make fmap search more strict
    
    Since fmap doesn't come with a checksum, we resort to a number of
    heuristics to determine if a given location hosts an fmap (instead of
    another data structure that happens to store the fmap magic string at
    the right location).
    
    The version test is particularly effective against strings containing
    the magic (which either terminate with 0, or have some other ASCII data,
    but rarely a '\001' byte inside the string).
    
    Change-Id: Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/flashmap/fmap.c | 35 +++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)

diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c
index f143beb..92707ec 100644
--- a/util/cbfstool/flashmap/fmap.c
+++ b/util/cbfstool/flashmap/fmap.c
@@ -34,6 +34,7 @@
 
 #define _XOPEN_SOURCE 700
 
+#include <ctype.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -69,6 +70,31 @@ int fmap_size(const struct fmap *fmap)
 	return sizeof(*fmap) + (fmap->nareas * sizeof(struct fmap_area));
 }
 
+/* Make a best-effort assessment if the given fmap is real */
+static int is_valid_fmap(const struct fmap *fmap)
+{
+	int i;
+	if (memcmp(fmap, FMAP_SIGNATURE, strlen(FMAP_SIGNATURE)) != 0)
+		return 0;
+	/* strings containing the magic tend to fail here */
+	if (fmap->ver_major != 1)
+		return 0;
+	/* a basic consistency check: flash should be larger than fmap */
+	if (fmap->size <
+		sizeof(*fmap) + fmap->nareas * sizeof(struct fmap_area))
+		return 0;
+
+	/* fmap-alikes along binary data tend to fail on the string test */
+	i = strlen((const char *)fmap->name);
+	if (i >= 32)
+		return 0;
+	for (i--; i >= 0; i--)
+		if (!isalnum(fmap->name[i]))
+			return 0;
+	return 1;
+
+}
+
 /* brute force linear search */
 static long int fmap_lsearch(const uint8_t *image, size_t len)
 {
@@ -76,9 +102,7 @@ static long int fmap_lsearch(const uint8_t *image, size_t len)
 	int fmap_found = 0;
 
 	for (offset = 0; offset < len - strlen(FMAP_SIGNATURE); offset++) {
-		if (!memcmp(&image[offset],
-			    FMAP_SIGNATURE,
-			    strlen(FMAP_SIGNATURE))) {
+		if (is_valid_fmap((const struct fmap *)&image[offset])) {
 			fmap_found = 1;
 			break;
 		}
@@ -114,9 +138,8 @@ static long int fmap_bsearch(const uint8_t *image, size_t len)
 		     offset += stride) {
 			if ((offset % (stride * 2) == 0) && (offset != 0))
 					continue;
-			if (!memcmp(&image[offset],
-				    FMAP_SIGNATURE,
-				    strlen(FMAP_SIGNATURE))) {
+			if (is_valid_fmap(
+				(const struct fmap *)&image[offset])) {
 				fmap_found = 1;
 				break;
 			}


From gerrit at coreboot.org  Sat Sep 19 14:05:39 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sat, 19 Sep 2015 14:05:39 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: have
	update-fit always work from CBFS
References: <Ie139215b73e01027bc0586701361e9a0afa9150e+0@gerrit.coreboot.org>
Message-ID: <Ie139215b73e01027bc0586701361e9a0afa9150e+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11691

-gerrit

commit 4c2b6cb90f45411e5af568bb9d7b6ba5d445492c
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Sat Sep 19 14:04:45 2015 +0200

    cbfstool: have update-fit always work from CBFS
    
    On x86, the bootblock can (and will) become part of the regular file
    system, so there's no distinct fixed-size region for the bootblock
    there.
    
    Change-Id: Ie139215b73e01027bc0586701361e9a0afa9150e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfstool.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 2bb8edc..4750666 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -835,16 +835,9 @@ static int cbfs_update_fit(void)
 		return 1;
 	}
 
-	// Decide which region to read/write the FIT table from/to.
 	struct buffer bootblock;
-	if (partitioned_file_is_partitioned(param.image_file)) {
-		if (!partitioned_file_read_region(&bootblock, param.image_file,
-							SECTION_WITH_FIT_TABLE))
-			return 1;
-	} else {
-		// In legacy images, the bootblock is part of the CBFS.
-		buffer_clone(&bootblock, param.image_region);
-	}
+	// The bootblock is part of the CBFS on x86
+	buffer_clone(&bootblock, param.image_region);
 
 	struct cbfs_image image;
 	if (cbfs_image_from_buffer(&image, param.image_region,


From gerrit at coreboot.org  Sat Sep 19 14:05:42 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sat, 19 Sep 2015 14:05:42 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Switch to fmap
	based firmware layout
References: <Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c+0@gerrit.coreboot.org>
Message-ID: <Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11692

-gerrit

commit 1766de6a5df1252df50ba1df19dfe2ee85109a3f
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 18:10:52 2015 +0200

    Switch to fmap based firmware layout
    
    We still add a master header for compatibility purposes, and the default
    layouts don't cover anything non-coreboot (eg. IFD regions) yet.
    
    The default layouts can be overridden by specifying an fmd file, from
    which the fmap is generated.
    
    Future work:
    - map IFD regions to fmap regions
    - non-x86: build minimalistic trampolines that jump into the first cbfs
      file, so the bootblock can be part of CBFS instead of reserving a
      whole 64K for it.
    - teach coreboot's cbfs code to work without the master header
    - teach coreboot's cbfs code to work on different fmap regions
    
    Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 Makefile.inc                  | 75 +++++++++++++++++++++++++++++++++++++++++--
 util/cbfstool/default-x86.fmd | 15 +++++++++
 util/cbfstool/default.fmd     | 17 ++++++++++
 3 files changed, 104 insertions(+), 3 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 46d6eb2..ee49118 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -566,10 +566,79 @@ prebuild-files = \
 	       $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&))
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
+ifeq ($(CONFIG_ARCH_X86),y)
+DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd
+# entire flash
+FMAP_ROM_BASE := $(CONFIG_ROM_START)
+FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
+# entire "BIOS" region (everything directly of concern to the host system)
+# relative to ROM_BASE
+FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE))
+FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
+# position and size of flashmap, relative to BIOS_BASE
+FMAP_FMAP_BASE := 0
+FMAP_FMAP_SIZE := 0x100
+# position and size of CBFS, relative to BIOS_BASE
+FMAP_CBFS_BASE := $(FMAP_FMAP_SIZE)
+FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_FMAP_SIZE))
+else
+DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
+# entire flash
+FMAP_ROM_BASE := $(CONFIG_ROM_START)
+FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
+# entire "BIOS" region (everything directly of concern to the host system)
+# relative to ROM_BASE
+FMAP_BIOS_BASE := 0
+FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
+# position and size of flashmap, relative to BIOS_BASE
+FMAP_FMAP_BASE := 0x10000
+FMAP_FMAP_SIZE := 0x100
+# position and size of CBFS, relative to BIOS_BASE
+FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
+FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
+endif
+
 $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
-	$(CBFSTOOL) $@.tmp create \
-	-B $(objcbfs)/bootblock.bin \
-	$(CBFSTOOL_PRE1_OPTS)
+ifeq ($(CONFIG_FMDFILE),)
+	sed -e "s,##ROM_BASE##,$(FMAP_ROM_BASE)," \
+	    -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \
+	    -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \
+	    -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \
+	    -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \
+	    -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \
+	    -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
+	    -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
+		$(DEFAULT_FLASHMAP) > $@.tmp.fmd
+	$(FMAPTOOL) $@.tmp.fmd $@.tmp.fmap
+else
+	$(FMAPTOOL) $(CONFIG_FMDFILE) $@.tmp.fmap
+endif
+	$(CBFSTOOL) $@.tmp create -M $@.tmp.fmap
+ifeq ($(CONFIG_ARCH_X86),y)
+	$(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock \
+		-t bootblock \
+		-b -$(call file-size,$(objcbfs)/bootblock.bin)
+else
+	# don't add bootblock to cbfs yet, it's just a waste of space
+	true $(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock \
+		-t bootblock \
+		-b 0
+	$(CBFSTOOL) $@.tmp write -u \
+		-r BOOTBLOCK \
+		-f $(objcbfs)/bootblock.bin
+	printf "ptr_" > $@.tmp.2 # 4 characters
+	$(CBFSTOOL) $@.tmp add \
+		-f $@.tmp.2 \
+		-n "header pointer" \
+		-t "cbfs header" \
+		-b -4
+	rm -f $@.tmp.2
+endif
+	$(CBFSTOOL) $@.tmp add-master-header
 	$(prebuild-files) true
 	mv $@.tmp $@
 else
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
new file mode 100644
index 0000000..d7d0326
--- /dev/null
+++ b/util/cbfstool/default-x86.fmd
@@ -0,0 +1,15 @@
+# layout for firmware residing at top of 4GB address space
+# 4GB - ROM_SIZE:	start of flash
+# 4GB - CBFS_SIZE:	start of fmap
+#  + 0x100:		start of CBFS
+# 4GB			end of flash
+
+# ##CBFS_SIZE## differs from the CBFS_SIZE specified above in that it already
+# excludes the fmap size. CONFIG_CBFS_SIZE contains it.
+
+FLASH@##ROM_BASE## ##ROM_SIZE## {
+	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
+		FMAP@##FMAP_BASE## ##FMAP_SIZE##
+		COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
+	}
+}
diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd
new file mode 100644
index 0000000..21617d5
--- /dev/null
+++ b/util/cbfstool/default.fmd
@@ -0,0 +1,17 @@
+# layout for firmware when flash address space matches used address layout
+# 0:			start of flash, start of bootblock region
+# 0x10000:		start of fmap
+# 0x10100:		start of cbfs
+# CBFS_SIZE		end of fmap, end of used flash space
+# ROM_SIZE		end of flash
+
+# ##CBFS_SIZE## differs from the CBFS_SIZE specified above in that it already
+# excludes the fmap size. CONFIG_CBFS_SIZE contains it.
+
+FLASH@##ROM_BASE## ##ROM_SIZE## {
+	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
+		BOOTBLOCK 64K
+		FMAP@##FMAP_BASE## ##FMAP_SIZE##
+		COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
+	}
+}


From gerrit at coreboot.org  Sun Sep 20 09:39:15 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Sun, 20 Sep 2015 09:39:15 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos:
	vboot-related functions move to common vboot code
References: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+0@gerrit.coreboot.org>
Message-ID: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+3@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11497

-gerrit

commit b67f8d01585c3e2a69531f251ef5264b0a10185c
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:41:14 2015 +0200

    chromeos: vboot-related functions move to common vboot code
    
    This moves a few vboot-prefixed functions that were defined in chromeos.c to
    vboot_common.c, since those are only relevant to vboot and depend on the vboot
    handoff data. This allows more separation between CONFIG_CHROMEOS and what
    CONFIG_CHROMEOS selects, so that each separate option (such as
    CONFIG_VBOOT_VERIFY_FIRMWARE) can be enabled separately.
    
    Thus, the actual definitions of these functions will only be declared when
    CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling
    vboot_skip_display_init in bootmode was also adapted.
    
    Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/lib/bootmode.c                            |  2 ++
 src/vendorcode/google/chromeos/chromeos.c     | 32 ---------------------------
 src/vendorcode/google/chromeos/chromeos.h     | 16 --------------
 src/vendorcode/google/chromeos/vboot_common.c | 27 ++++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot_common.h |  7 ++++++
 5 files changed, 36 insertions(+), 48 deletions(-)

diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index f2ff72a..13c0130 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -80,8 +80,10 @@ void gfx_set_init_done(int done)
 int display_init_required(void)
 {
 	/* For Chrome OS always honor vboot_skip_display_init(). */
+#if CONFIG_VBOOT_VERIFY_FIRMWARE
 	if (IS_ENABLED(CONFIG_CHROMEOS))
 		return !vboot_skip_display_init();
+#endif
 
 	/* By default always initialize display. */
 	return 1;
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index c2190b7..4864b8c 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -20,38 +20,6 @@
 #include <stddef.h>
 #include <string.h>
 #include "chromeos.h"
-#include <boot/coreboot_tables.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include "vboot_handoff.h"
-
-static int vboot_handoff_flag(uint32_t flag)
-{
-	struct vboot_handoff *vbho;
-
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
-
-	if (vbho == NULL)
-		return 0;
-
-	return !!(vbho->init_params.out_flags & flag);
-}
-
-int vboot_skip_display_init(void)
-{
-	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
-}
-
-int vboot_enable_developer(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
-}
-
-int vboot_enable_recovery(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
-}
 
 int __attribute__((weak)) clear_recovery_mode_switch(void)
 {
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index 798ab3e..bdc9435 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -45,29 +45,14 @@ void elog_add_boot_reason(void);
 /* functions implemented in watchdog.c */
 void elog_add_watchdog_reset(void);
 void reboot_from_watchdog(void);
-
-int vboot_enable_developer(void);
-int vboot_enable_recovery(void);
-int vboot_skip_display_init(void);
 #else
 static inline void elog_add_boot_reason(void) { return; }
 static inline void elog_add_watchdog_reset(void) { return; }
 static inline void reboot_from_watchdog(void) { return; }
-static inline int vboot_skip_display_init(void) { return 0; }
 #endif /* CONFIG_CHROMEOS */
 
 struct romstage_handoff;
 
-#if CONFIG_VBOOT_VERIFY_FIRMWARE
-/* Returns 0 on success < 0 on error. */
-int vboot_get_handoff_info(void **addr, uint32_t *size);
-#else /* CONFIG_VBOOT_VERIFY_FIRMWARE */
-static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
-{
-	return -1;
-}
-#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
-
 #include "gnvs.h"
 struct device;
 
@@ -84,6 +69,5 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {}
 #endif /* CONFIG_CHROMEOS_RAMOOPS */
 
 void cbmem_add_vpd_calibration_data(void);
-void vboot_reboot(void);
 
 #endif /* __CHROMEOS_H__ */
diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 2fd29b6..1c216d0 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -55,6 +55,33 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 	return 0;
 }
 
+static int vboot_handoff_flag(uint32_t flag)
+{
+	struct vboot_handoff *vbho;
+
+	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
+
+	if (vbho == NULL)
+		return 0;
+
+	return !!(vbho->init_params.out_flags & flag);
+}
+
+int vboot_skip_display_init(void)
+{
+	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
+}
+
+int vboot_enable_developer(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
+}
+
+int vboot_enable_recovery(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
+}
+
 void vboot_reboot(void)
 {
 	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..df8591e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -40,4 +40,11 @@ struct vboot_components {
 int vboot_named_region_device(const char *name, struct region_device *rdev);
 int vboot_region_device(const struct region *reg, struct region_device *rdev);
 
+int vboot_get_handoff_info(void **addr, uint32_t *size);
+int vboot_skip_display_init(void);
+int vboot_enable_recovery(void);
+int vboot_enable_developer(void);
+
+void vboot_reboot(void);
+
 #endif /* VBOOT_COMMON_H */


From gerrit at coreboot.org  Sun Sep 20 09:39:19 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Sun, 20 Sep 2015 09:39:19 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos: vboot
	and chromeos dependency removal for sw write protect state
References: <I47ce31530a03f6749e0f370e5d868466318b3bb6+0@gerrit.coreboot.org>
Message-ID: <I47ce31530a03f6749e0f370e5d868466318b3bb6+4@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11496

-gerrit

commit 17f6043f65f5952997fcbd82a9c3d816ec36bd33
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:27:27 2015 +0200

    chromeos: vboot and chromeos dependency removal for sw write protect state
    
    This removes the dependency on chromeos and vboot for the sw write protect state
    function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to
    both reflect this change and become consistent with the definition of
    get_write_protect_state that is already in use.
    
    Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/include/bootmode.h                                | 1 +
 src/soc/intel/baytrail/romstage/romstage.c            | 4 +---
 src/soc/intel/broadwell/romstage/romstage.c           | 4 +---
 src/soc/intel/skylake/romstage/romstage.c             | 4 +---
 src/vendorcode/google/chromeos/chromeos.c             | 2 +-
 src/vendorcode/google/chromeos/chromeos.h             | 2 --
 src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 2 +-
 7 files changed, 6 insertions(+), 13 deletions(-)

diff --git a/src/include/bootmode.h b/src/include/bootmode.h
index 96c789b..730c0f3 100644
--- a/src/include/bootmode.h
+++ b/src/include/bootmode.h
@@ -23,6 +23,7 @@
 /* functions implemented per mainboard: */
 void init_bootmode_straps(void);
 int get_write_protect_state(void);
+int get_sw_write_protect_state(void);
 int get_developer_mode_switch(void);
 int get_recovery_mode_switch(void);
 int clear_recovery_mode_switch(void);
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 1b93eb6..7bd2663 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -362,11 +362,9 @@ void ramstage_cache_invalid(void)
 #endif
 }
 
-#if CONFIG_CHROMEOS
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 	/* Return unprotected status if status read fails. */
 	return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
 }
-#endif
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 27fb0f2..884c274 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -147,13 +147,11 @@ void ramstage_cache_invalid(void)
 #endif
 }
 
-#if CONFIG_CHROMEOS
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 	/* Return unprotected status if status read fails. */
 	return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
 }
 
-#endif
 void __attribute__((weak)) mainboard_pre_console_init(void) {}
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 6c5d64a..6804459 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -68,15 +68,13 @@ void soc_romstage_init(struct romstage_params *params)
 	pch_early_init();
 }
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
-int vboot_get_sw_write_protect(void)
+int get_sw_write_protect_state(void)
 {
 	u8 status;
 
 	/* Return unprotected status if status read fails. */
 	return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80);
 }
-#endif
 
 /* UPD parameters to be initialized before MemoryInit */
 void soc_memory_init_params(struct romstage_params *params,
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index 0737267..c2190b7 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -65,7 +65,7 @@ void __attribute__((weak)) save_chromeos_gpios(void)
 	// Can be implemented by a mainboard
 }
 
-int __attribute__((weak)) vboot_get_sw_write_protect(void)
+int __attribute__((weak)) get_sw_write_protect_state(void)
 {
 	// Can be implemented by a platform / mainboard
 	return 0;
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index c7048dd..798ab3e 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -68,8 +68,6 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
 }
 #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
 
-int vboot_get_sw_write_protect(void);
-
 #include "gnvs.h"
 struct device;
 
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index c8ba114..8e12fdc 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -61,7 +61,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff,
 
 	if (get_write_protect_state())
 		vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED;
-	if (vboot_get_sw_write_protect())
+	if (get_sw_write_protect_state())
 		vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED;
 
 	if (vb2_sd->recovery_reason) {


From gerrit at coreboot.org  Sun Sep 20 09:39:24 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Sun, 20 Sep 2015 09:39:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos:
	vboot_common: Avoid code duplication when grabbing the handoff info
References: <I28f1decce98f988f90c446a3a0dbe7409d714527+0@gerrit.coreboot.org>
Message-ID: <I28f1decce98f988f90c446a3a0dbe7409d714527+3@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11498

-gerrit

commit fc94595d2a5c125e7a4b57d5358e0a4b0b8a5e30
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:44:56 2015 +0200

    chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
    
    vboot_handoff_flag was duplicating the logic to grab the handoff info, that is
    already made available with vboot_get_handoff_info.
    This uses vboot_get_handoff_info in vboot_handoff_flag instead.
    
    Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/vendorcode/google/chromeos/vboot_common.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 1c216d0..6184b0d 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -58,10 +58,9 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 static int vboot_handoff_flag(uint32_t flag)
 {
 	struct vboot_handoff *vbho;
+	uint32_t size;
 
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
-
-	if (vbho == NULL)
+	if (vboot_get_handoff_info((void **)&vbho, &size))
 		return 0;
 
 	return !!(vbho->init_params.out_flags & flag);


From gerrit at coreboot.org  Sun Sep 20 09:39:28 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Sun, 20 Sep 2015 09:39:28 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: google: veyron:
	CBFS_SIZE to match the available size for Coreboot in ChromeOS
References: <I168386a5011222866654a496d8d054faff7a9406+0@gerrit.coreboot.org>
Message-ID: <I168386a5011222866654a496d8d054faff7a9406+4@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11117

-gerrit

commit fa9366124f05060be51e7e85f2a6382732238c0d
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Wed Sep 16 18:23:23 2015 +0200

    google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOS
    
    When building for ChromeOS, it is expected that Coreboot will only occupy the
    first MiB of the SPI flash, according to the veyron fmap description.
    Otherwise, it makes sense to use the full ROM size.
    
    Change-Id: I168386a5011222866654a496d8d054faff7a9406
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/mainboard/google/veyron/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
index c474bd6..38a9ef6 100644
--- a/src/mainboard/google/veyron/Kconfig
+++ b/src/mainboard/google/veyron/Kconfig
@@ -85,4 +85,9 @@ config PMIC_BUS
 	int
 	default 0
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 endif #  BOARD_GOOGLE_VEYRON


From gerrit at coreboot.org  Mon Sep 21 02:47:47 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Mon, 21 Sep 2015 02:47:47 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: xcompile:
	Redirect the objdump stderr to /dev/null
References: <I9940f069f66e097973ed6138cf3c696087fa5531+0@gerrit.coreboot.org>
Message-ID: <I9940f069f66e097973ed6138cf3c696087fa5531+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11681

-gerrit

commit 285d48ad26deb6a3e732c4fbb83f6e91941536a6
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 18 06:17:09 2015 -0700

    xcompile: Redirect the objdump stderr to /dev/null
    
    On system with clang, "as" is available but "objdump" is not by default.
    So if ${gccprefix} is empty, "as" can run successfully and the "objdump"
    below might report error.
    ......
    util/xcompile/xcompile: line 118: objdump: command not found
    util/xcompile/xcompile: line 118: objdump: command not found
    Warning: no suitable compiler for arm64.
    util/xcompile/xcompile: line 118: objdump: command not found
    util/xcompile/xcompile: line 118: objdump: command not found
    Warning: no suitable compiler for mipsel.
    util/xcompile/xcompile: line 118: objdump: command not found
    Warning: no suitable compiler for riscv.
    util/xcompile/xcompile: line 118: objdump: command not found
    ......
    Mask that output.
    
    Change-Id: I9940f069f66e097973ed6138cf3c696087fa5531
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/xcompile/xcompile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 46a30d1..d664464 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -115,7 +115,7 @@ testas() {
 		2>/dev/null || return 1
 
 	# Check output content type.
-	local obj_type="$(LANG=C LC_ALL= ${gccprefix}objdump -p $obj_file)"
+	local obj_type="$(LANG=C LC_ALL= ${gccprefix}objdump -p $obj_file 2>/dev/null)"
 	local obj_arch="$(expr "$obj_type" : '.*format \(.[a-z0-9-]*\)')"
 	[ "$obj_arch" = "$full_arch" ] || return 1
 


From gerrit at coreboot.org  Mon Sep 21 04:30:07 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 21 Sep 2015 04:30:07 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+2@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit 900647ed677b8253a33e41e193d8e9325cb5027f
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                           | 23 ++++++++----------
 src/cpu/amd/model_10xxx/Makefile.inc           |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c       |  3 ---
 src/cpu/amd/model_fxx/Makefile.inc             |  2 +-
 src/cpu/intel/ep80579/Makefile.inc             |  2 --
 src/cpu/intel/ep80579/microcode_blob.c         |  8 -------
 src/cpu/intel/fsp_model_206ax/Kconfig          |  5 ----
 src/cpu/intel/fsp_model_206ax/Makefile.inc     | 10 ++------
 src/cpu/intel/fsp_model_206ax/microcode_blob.c | 22 -----------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h | 33 --------------------------
 src/cpu/intel/fsp_model_406dx/Kconfig          |  4 ----
 src/cpu/intel/fsp_model_406dx/Makefile.inc     | 11 +++------
 src/cpu/intel/fsp_model_406dx/microcode_blob.c | 29 ----------------------
 src/cpu/intel/model_1067x/Makefile.inc         |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c     |  3 ---
 src/cpu/intel/model_106cx/Makefile.inc         |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c     |  3 ---
 src/cpu/intel/model_2065x/Makefile.inc         |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c     | 22 -----------------
 src/cpu/intel/model_206ax/Makefile.inc         |  3 +++
 src/cpu/intel/model_206ax/microcode_blob.c     | 23 ------------------
 src/cpu/intel/model_65x/Makefile.inc           |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_67x/Makefile.inc           |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_68x/Makefile.inc           |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_69x/Makefile.inc           |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6bx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6dx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6ex/Makefile.inc           |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6fx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6xx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_f0x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f1x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f2x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f3x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_f4x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c       |  3 ---
 src/cpu/via/nano/Makefile.inc                  |  4 +---
 50 files changed, 38 insertions(+), 253 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..3b38cc4 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,5 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..05794df 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,6 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..4b74ce2 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -8,4 +8,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
+
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc


From gerrit at coreboot.org  Mon Sep 21 04:30:09 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 21 Sep 2015 04:30:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: 3dparty/blobs:
	Advance to pull in binary microcode
References: <I2071586e1f3b4464464928c11475f9283084dbcd+0@gerrit.coreboot.org>
Message-ID: <I2071586e1f3b4464464928c11475f9283084dbcd+1@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11693

-gerrit

commit 45db02851b0eb0abc26780837ea343aadb585068
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sun Sep 20 21:08:05 2015 -0700

    3dparty/blobs: Advance to pull in binary microcode
    
    Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 3rdparty/blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index b4ade40..df1f219 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7
+Subproject commit df1f21931c75aae9ee14cdc52da57783a6e0a9ad


From gerrit at coreboot.org  Mon Sep 21 05:06:47 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 21 Sep 2015 05:06:47 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+3@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit 302c2627a790878f9efa07982b108b9179bb491f
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                           | 23 ++++++++----------
 src/cpu/amd/model_10xxx/Makefile.inc           |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c       |  3 ---
 src/cpu/amd/model_fxx/Makefile.inc             |  2 +-
 src/cpu/intel/ep80579/Makefile.inc             |  2 --
 src/cpu/intel/ep80579/microcode_blob.c         |  8 -------
 src/cpu/intel/fsp_model_206ax/Kconfig          |  5 ----
 src/cpu/intel/fsp_model_206ax/Makefile.inc     | 10 ++------
 src/cpu/intel/fsp_model_206ax/microcode_blob.c | 22 -----------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h | 33 --------------------------
 src/cpu/intel/fsp_model_406dx/Kconfig          |  4 ----
 src/cpu/intel/fsp_model_406dx/Makefile.inc     | 11 +++------
 src/cpu/intel/fsp_model_406dx/microcode_blob.c | 29 ----------------------
 src/cpu/intel/haswell/Makefile.inc             |  5 ++--
 src/cpu/intel/haswell/microcode_blob.c         | 30 -----------------------
 src/cpu/intel/model_1067x/Makefile.inc         |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c     |  3 ---
 src/cpu/intel/model_106cx/Makefile.inc         |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c     |  3 ---
 src/cpu/intel/model_2065x/Makefile.inc         |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c     | 22 -----------------
 src/cpu/intel/model_206ax/Makefile.inc         |  3 ++-
 src/cpu/intel/model_206ax/microcode_blob.c     | 23 ------------------
 src/cpu/intel/model_65x/Makefile.inc           |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_67x/Makefile.inc           |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_68x/Makefile.inc           |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_69x/Makefile.inc           |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6bx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6dx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6ex/Makefile.inc           |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6fx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6xx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_f0x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f1x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f2x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f3x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_f4x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c       |  3 ---
 src/cpu/via/nano/Makefile.inc                  |  4 +---
 52 files changed, 40 insertions(+), 286 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..3b38cc4 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,5 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..05794df 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,6 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc


From gerrit at coreboot.org  Mon Sep 21 06:31:30 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Mon, 21 Sep 2015 06:31:30 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+4@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit fa307fbda4aed1168e6e4e5bd86fba1cf96d8ba6
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                           | 23 ++++++++----------
 src/cpu/amd/model_10xxx/Makefile.inc           |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c       |  3 ---
 src/cpu/amd/model_fxx/Makefile.inc             |  2 +-
 src/cpu/intel/ep80579/Makefile.inc             |  2 --
 src/cpu/intel/ep80579/microcode_blob.c         |  8 -------
 src/cpu/intel/fsp_model_206ax/Kconfig          |  5 ----
 src/cpu/intel/fsp_model_206ax/Makefile.inc     |  9 ++-----
 src/cpu/intel/fsp_model_206ax/microcode_blob.c | 22 -----------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h | 33 --------------------------
 src/cpu/intel/fsp_model_406dx/Kconfig          |  4 ----
 src/cpu/intel/fsp_model_406dx/Makefile.inc     | 10 +++-----
 src/cpu/intel/fsp_model_406dx/microcode_blob.c | 29 ----------------------
 src/cpu/intel/haswell/Makefile.inc             |  5 ++--
 src/cpu/intel/haswell/microcode_blob.c         | 30 -----------------------
 src/cpu/intel/model_1067x/Makefile.inc         |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c     |  3 ---
 src/cpu/intel/model_106cx/Makefile.inc         |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c     |  3 ---
 src/cpu/intel/model_2065x/Makefile.inc         |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c     | 22 -----------------
 src/cpu/intel/model_206ax/Makefile.inc         |  3 ++-
 src/cpu/intel/model_206ax/microcode_blob.c     | 23 ------------------
 src/cpu/intel/model_65x/Makefile.inc           |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_67x/Makefile.inc           |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_68x/Makefile.inc           |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_69x/Makefile.inc           |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6bx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6dx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6ex/Makefile.inc           |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6fx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_6xx/Makefile.inc           |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c       |  3 ---
 src/cpu/intel/model_f0x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f1x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f2x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c       |  4 ----
 src/cpu/intel/model_f3x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c       |  3 ---
 src/cpu/intel/model_f4x/Makefile.inc           |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c       |  3 ---
 src/cpu/via/nano/Makefile.inc                  |  4 +---
 52 files changed, 40 insertions(+), 284 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc


From gerrit at coreboot.org  Mon Sep 21 13:01:25 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 21 Sep 2015 13:01:25 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: ifdfake: allow
	"base+size" description of regions
References: <Iecf8250e84d6eb267711ded446909b21147f1a9c+0@gerrit.coreboot.org>
Message-ID: <E1Ze0ij-00079R-Uc@mail.coreboot.org>

the following patch was just integrated into master:
commit a9992d3da5d28dc9f8423fe17497231f894fa9d9
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 13:48:24 2015 +0200

    ifdfake: allow "base+size" description of regions
    
    This is more in line with how fmd/fmap specify ranges.
    
    Change-Id: Iecf8250e84d6eb267711ded446909b21147f1a9c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11623
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11623 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 21 15:02:19 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 21 Sep 2015 15:02:19 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Kconfig: Add
	ROM_START variable
References: <Icc747eccf4263875f15806fcb38ec29e4665cf11+0@gerrit.coreboot.org>
Message-ID: <Icc747eccf4263875f15806fcb38ec29e4665cf11+3@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11630

-gerrit

commit b95fe8cc45e17f1e051b12fa26991dad6788e6d1
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 15:29:42 2015 +0200

    Kconfig: Add ROM_START variable
    
    It's automatically derived from ROM_SIZE and specifies the offset of
    flash in memory. On non-x86 that's 0, on x86 it's 4GB-ROM_SIZE.
    
    Change-Id: Icc747eccf4263875f15806fcb38ec29e4665cf11
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/mainboard/Kconfig | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index ab8ee26..3098803 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -128,6 +128,20 @@ config ROM_SIZE
 	default 0xc00000 if COREBOOT_ROMSIZE_KB_12288
 	default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
 
+config ROM_START
+	hex
+	default 0 if !ARCH_X86
+	default 0xffff0000 if COREBOOT_ROMSIZE_KB_64
+	default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+	default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+	default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+	default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+	default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+	default 0xffc00000 if COREBOOT_ROMSIZE_KB_4096
+	default 0xff800000 if COREBOOT_ROMSIZE_KB_8192
+	default 0xff400000 if COREBOOT_ROMSIZE_KB_12288
+	default 0xff000000 if COREBOOT_ROMSIZE_KB_16384
+
 config ENABLE_POWER_BUTTON
 	bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
 	default y if POWER_BUTTON_DEFAULT_ENABLE


From gerrit at coreboot.org  Mon Sep 21 15:02:23 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 21 Sep 2015 15:02:23 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: add new
	add-master-header command
References: <I5bc7fbcb5962b35a95261f30f0c93008e760680d+0@gerrit.coreboot.org>
Message-ID: <I5bc7fbcb5962b35a95261f30f0c93008e760680d+3@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11628

-gerrit

commit d2f1c6d2b257fdfe14702fee6e1f262ffeaa6369
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Thu Sep 10 15:28:27 2015 +0200

    cbfstool: add new add-master-header command
    
    The command adds a new cbfs file, fills in the CBFS meta data in cbfs
    master header format, then points the master header pointer (which
    resides at the last 4 bytes of the CBFS region) to the data area of the
    new file.
    
    This can leak some space in CBFS if an old-style CBFS with native master
    header gets the treatment, because a new header is created and pointed
    at. flashmap based images have no such header, and the attempt to create
    a second file with the (hardcoded) name will fail.
    
    Change-Id: I5bc7fbcb5962b35a95261f30f0c93008e760680d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfstool.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index c45f316..ed6e898 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -19,6 +19,7 @@
  * Foundation, Inc.
  */
 
+#include <endian.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
@@ -211,6 +212,76 @@ done:
 	return ret;
 }
 
+static int cbfs_add_master_header(void)
+{
+	const char * const name = "cbfs master header";
+	struct cbfs_image image;
+	struct cbfs_file *header = NULL;
+	struct buffer buffer;
+	int ret = 1;
+
+	if (cbfs_image_from_buffer(&image, param.image_region,
+		param.headeroffset)) {
+		ERROR("Selected image region is not a CBFS.\n");
+		return 1;
+	}
+
+	if (cbfs_get_entry(&image, name)) {
+		ERROR("'%s' already in ROM image.\n", name);
+		return 1;
+	}
+
+	if (buffer_create(&buffer, sizeof(struct cbfs_header), name) != 0)
+		return 1;
+
+	struct cbfs_header *h = (struct cbfs_header *)buffer.data;
+	h->magic = htonl(CBFS_HEADER_MAGIC);
+	h->version = htonl(CBFS_HEADER_VERSION);
+	h->romsize = htonl(param.image_region->size);
+	/* The 4 bytes are left out for two reasons:
+	 * 1. the cbfs master header pointer resides there
+	 * 2. some cbfs implementations assume that an image that resides
+	 *    below 4GB has a bootblock and get confused when the end of the
+	 *    image is at 4GB == 0.
+	 */
+	h->bootblocksize = htonl(4);
+	h->align = htonl(CBFS_ENTRY_ALIGNMENT);
+	/* offset relative to romsize above, which covers precisely the CBFS
+	 * region.
+	 */
+	h->offset = htonl(0);
+	h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN);
+
+	header = cbfs_create_file_header(CBFS_COMPONENT_CBFSHEADER,
+		buffer_size(&buffer), name);
+	if (cbfs_add_entry(&image, &buffer, 0, header) != 0) {
+		ERROR("Failed to add cbfs master header into ROM image.\n");
+		goto done;
+	}
+
+	struct cbfs_file *entry;
+	if ((entry = cbfs_get_entry(&image, name)) == NULL) {
+		ERROR("'%s' not in ROM image?!?\n", name);
+		goto done;
+	}
+
+	uint32_t header_offset = CBFS_SUBHEADER(entry) -
+		buffer_get(&image.buffer);
+	header_offset = -(buffer_size(&image.buffer) - header_offset);
+
+	// TODO: when we have a BE target, we'll need to store this as BE
+	*(uint32_t *)(buffer_get(&image.buffer) +
+		buffer_size(&image.buffer) - 4) =
+		htole32(header_offset);
+
+	ret = 0;
+
+done:
+	free(header);
+	buffer_delete(&buffer);
+	return ret;
+}
+
 static int cbfs_add_component(const char *filename,
 			      const char *name,
 			      uint32_t type,
@@ -831,6 +902,7 @@ static const struct command commands[] = {
 	{"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true},
 	{"add-stage", "a:H:r:f:n:t:c:b:P:S:yvh?", cbfs_add_stage, true, true},
 	{"add-int", "H:r:i:n:b:vh?", cbfs_add_integer, true, true},
+	{"add-master-header", "H:r:vh?", cbfs_add_master_header, true, true},
 	{"copy", "H:D:s:h?", cbfs_copy, true, true},
 	{"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true},
 	{"extract", "H:r:n:f:vh?", cbfs_extract, true, false},
@@ -956,6 +1028,8 @@ static void usage(char *name)
 			"Add a 32bit flat mode binary\n"
 	     " add-int [-r image,regions] -i INTEGER -n NAME [-b base]     "
 			"Add a raw 64-bit integer value\n"
+	     " add-master-header [-r image,regions]                        "
+			"Add a legacy CBFS master header\n"
 	     " remove [-r image,regions] -n NAME                           "
 			"Remove a component\n"
 	     " copy -D new_header_offset -s region size \\\n"


From gerrit at coreboot.org  Mon Sep 21 15:02:26 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 21 Sep 2015 15:02:26 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prefer
	fmap data over cbfs master header if it exists
References: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+0@gerrit.coreboot.org>
Message-ID: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+3@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11629

-gerrit

commit 62d676521f244bfaac9ca138ff720097138046cd
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 18:34:39 2015 +0200

    cbfstool: prefer fmap data over cbfs master header if it exists
    
    Up to now, if both fmap and a master header existed, the master header
    was used. Now, use the master header only if no fmap is found.
    
    Change-Id: Iafbf2c9dc325597e23a9780b495549b5d912e9ad
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfs_image.c       | 12 +++++++-----
 util/cbfstool/cbfstool.c         |  9 +--------
 util/cbfstool/partitioned_file.c | 15 +--------------
 util/cbfstool/partitioned_file.h | 24 +++++-------------------
 4 files changed, 14 insertions(+), 46 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 55f8084..24ab0c4 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -343,20 +343,22 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in,
 	buffer_clone(&out->buffer, in);
 	out->has_header = false;
 
+	if (cbfs_is_valid_cbfs(out)) {
+		return 0;
+	}
+
 	void *header_loc = cbfs_find_header(in->data, in->size, offset);
 	if (header_loc) {
 		cbfs_get_header(&out->header, header_loc);
 		out->has_header = true;
 		cbfs_fix_legacy_size(out, header_loc);
+		return 0;
 	} else if (offset != ~0u) {
 		ERROR("The -H switch is only valid on legacy images having CBFS master headers.\n");
 		return 1;
-	} else if (!cbfs_is_valid_cbfs(out)) {
-		ERROR("Selected image region is not a valid CBFS.\n");
-		return 1;
 	}
-
-	return 0;
+	ERROR("Selected image region is not a valid CBFS.\n");
+	return 1;
 }
 
 int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset,
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 4dd2843..8bb1732 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -882,12 +882,6 @@ static int cbfs_copy(void)
 	return cbfs_copy_instance(&image, param.copyoffset, param.size);
 }
 
-static bool cbfs_is_legacy_format(struct buffer *buffer)
-{
-	// Legacy CBFSes are those containing the deprecated CBFS master header.
-	return cbfs_find_header(buffer->data, buffer->size, -1);
-}
-
 static const struct command commands[] = {
 	{"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true},
 	{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
@@ -1251,8 +1245,7 @@ int main(int argc, char **argv)
 			}
 		} else {
 			param.image_file =
-				partitioned_file_reopen(image_name,
-							cbfs_is_legacy_format);
+				partitioned_file_reopen(image_name);
 		}
 		if (!param.image_file)
 			return 1;
diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c
index 9d67832..041ef11 100644
--- a/util/cbfstool/partitioned_file.c
+++ b/util/cbfstool/partitioned_file.c
@@ -165,8 +165,7 @@ partitioned_file_t *partitioned_file_create(const char *filename,
 	return file;
 }
 
-partitioned_file_t *partitioned_file_reopen(const char *filename,
-				partitioned_file_flat_decider_t flat_override)
+partitioned_file_t *partitioned_file_reopen(const char *filename)
 {
 	assert(filename);
 
@@ -174,11 +173,6 @@ partitioned_file_t *partitioned_file_reopen(const char *filename,
 	if (!file)
 		return NULL;
 
-	if (flat_override && flat_override(&file->buffer)) {
-		INFO("Opening image as a flat file in response to explicit request\n");
-		return file;
-	}
-
 	long fmap_region_offset = fmap_find((const uint8_t *)file->buffer.data,
 							file->buffer.size);
 	if (fmap_region_offset < 0) {
@@ -365,10 +359,3 @@ static bool select_parents_of(const struct fmap_area *parent, const void *arg)
 }
 const partitioned_file_fmap_selector_t partitioned_file_fmap_select_parents_of =
 							select_parents_of;
-
-static bool open_as_flat(unused struct buffer *buffer)
-{
-	return true;
-}
-const partitioned_file_flat_decider_t partitioned_file_open_as_flat =
-								open_as_flat;
diff --git a/util/cbfstool/partitioned_file.h b/util/cbfstool/partitioned_file.h
index 4583316..3698a19 100644
--- a/util/cbfstool/partitioned_file.h
+++ b/util/cbfstool/partitioned_file.h
@@ -28,15 +28,6 @@
 
 typedef struct partitioned_file partitioned_file_t;
 
-/** @return Whether the specific existing file should be opened in flat mode. */
-typedef bool (*partitioned_file_flat_decider_t)(struct buffer *buffer);
-
-/** Pass to partitioned_file_reopen() to force opening as a partitioned file. */
-#define partitioned_file_open_as_partitioned NULL
-
-/** Pass to partitioned_file_reopen() to force opening as a flat file. */
-extern const partitioned_file_flat_decider_t partitioned_file_open_as_flat;
-
 /**
  * Create a new filesystem-backed flat buffer.
  * This backwards-compatibility function creates a new in-memory buffer and
@@ -76,22 +67,17 @@ partitioned_file_t *partitioned_file_create(const char *filename,
 
 /**
  * Read a file back in from the disk.
- * An in-memory buffer is created and populated with the file's contents. If
- * flat_override is NULL and the image contains an FMAP, it will be opened as a
- * full partitioned file; otherwise, it will be opened as a flat file as if it
- * had been created by partitioned_file_create_flat(). This selection behavior
- * is extensible: if a flat_override function is provided, it is invoked before
- * searching for an FMAP, and has the option of explicitly instructing the
- * module to open the image as a flat file based on its contents.
+ * An in-memory buffer is created and populated with the file's
+ * contents. If the image contains an FMAP, it will be opened as a
+ * full partitioned file; otherwise, it will be opened as a flat file as
+ * if it had been created by partitioned_file_create_flat().
  * The partitioned_file_t returned from this function is separately owned by the
  * caller, and must later be passed to partitioned_file_close();
  *
  * @param filename      Name of the file to read in
- * @param flat_override Callback that can decide to open it as flat, or NULL
  * @return              Caller-owned partitioned file, or NULL on error
  */
-partitioned_file_t *partitioned_file_reopen(const char *filename,
-				partitioned_file_flat_decider_t flat_override);
+partitioned_file_t *partitioned_file_reopen(const char *filename);
 
 /**
  * Write a buffer's contents to its original region within a segmented file.


From gerrit at coreboot.org  Mon Sep 21 15:02:30 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 21 Sep 2015 15:02:30 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: have
	update-fit always work from CBFS
References: <Ie139215b73e01027bc0586701361e9a0afa9150e+0@gerrit.coreboot.org>
Message-ID: <Ie139215b73e01027bc0586701361e9a0afa9150e+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11691

-gerrit

commit 2f845979a694d6e0b6421a8deb122a4e55d196fb
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Sat Sep 19 14:04:45 2015 +0200

    cbfstool: have update-fit always work from CBFS
    
    On x86, the bootblock can (and will) become part of the regular file
    system, so there's no distinct fixed-size region for the bootblock
    there.
    
    Change-Id: Ie139215b73e01027bc0586701361e9a0afa9150e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfstool.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index ed6e898..4dd2843 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -839,16 +839,9 @@ static int cbfs_update_fit(void)
 		return 1;
 	}
 
-	// Decide which region to read/write the FIT table from/to.
 	struct buffer bootblock;
-	if (partitioned_file_is_partitioned(param.image_file)) {
-		if (!partitioned_file_read_region(&bootblock, param.image_file,
-							SECTION_WITH_FIT_TABLE))
-			return 1;
-	} else {
-		// In legacy images, the bootblock is part of the CBFS.
-		buffer_clone(&bootblock, param.image_region);
-	}
+	// The bootblock is part of the CBFS on x86
+	buffer_clone(&bootblock, param.image_region);
 
 	struct cbfs_image image;
 	if (cbfs_image_from_buffer(&image, param.image_region,


From gerrit at coreboot.org  Mon Sep 21 15:02:37 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 21 Sep 2015 15:02:37 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: make
	fmap search more strict
References: <Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9+0@gerrit.coreboot.org>
Message-ID: <Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11690

-gerrit

commit b1dbdb2b15b92d16278d7be82b957d484fe9e568
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Sat Sep 19 13:59:36 2015 +0200

    cbfstool: make fmap search more strict
    
    Since fmap doesn't come with a checksum, we resort to a number of
    heuristics to determine if a given location hosts an fmap (instead of
    another data structure that happens to store the fmap magic string at
    the right location).
    
    The version test is particularly effective against strings containing
    the magic (which either terminate with 0, or have some other ASCII data,
    but rarely a '\001' byte inside the string).
    
    Change-Id: Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/flashmap/fmap.c | 45 +++++++++++++++++++++++++++++++++++++------
 1 file changed, 39 insertions(+), 6 deletions(-)

diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c
index f143beb..f803d6c 100644
--- a/util/cbfstool/flashmap/fmap.c
+++ b/util/cbfstool/flashmap/fmap.c
@@ -34,6 +34,7 @@
 
 #define _XOPEN_SOURCE 700
 
+#include <ctype.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -69,6 +70,41 @@ int fmap_size(const struct fmap *fmap)
 	return sizeof(*fmap) + (fmap->nareas * sizeof(struct fmap_area));
 }
 
+/* Make a best-effort assessment if the given fmap is real */
+static int is_valid_fmap(const struct fmap *fmap)
+{
+	if (memcmp(fmap, FMAP_SIGNATURE, strlen(FMAP_SIGNATURE)) != 0)
+		return 0;
+	/* strings containing the magic tend to fail here */
+	if (fmap->ver_major != FMAP_VER_MAJOR)
+		return 0;
+	/* a basic consistency check: flash should be larger than fmap */
+	if (fmap->size <
+		sizeof(*fmap) + fmap->nareas * sizeof(struct fmap_area))
+		return 0;
+
+	/* fmap-alikes along binary data tend to fail on having a valid,
+	 * null-terminated string in the name field.*/
+	int i = 0;
+	while (i < FMAP_STRLEN) {
+		if (fmap->name[i] == 0)
+			break;
+		if (!isalnum(fmap->name[i]))
+			return 0;
+		if (i == FMAP_STRLEN - 1) {
+			/* name is specified to be null terminated. We didn't
+			 * break in the 0 test, we didn't fail on the alnum
+			 * test, so we're seeing FMAP_STRLEN alphanumerical
+			 * symbols, which is one too many.
+			 */
+			 return 0;
+		}
+		i++;
+	}
+	return 1;
+
+}
+
 /* brute force linear search */
 static long int fmap_lsearch(const uint8_t *image, size_t len)
 {
@@ -76,9 +112,7 @@ static long int fmap_lsearch(const uint8_t *image, size_t len)
 	int fmap_found = 0;
 
 	for (offset = 0; offset < len - strlen(FMAP_SIGNATURE); offset++) {
-		if (!memcmp(&image[offset],
-			    FMAP_SIGNATURE,
-			    strlen(FMAP_SIGNATURE))) {
+		if (is_valid_fmap((const struct fmap *)&image[offset])) {
 			fmap_found = 1;
 			break;
 		}
@@ -114,9 +148,8 @@ static long int fmap_bsearch(const uint8_t *image, size_t len)
 		     offset += stride) {
 			if ((offset % (stride * 2) == 0) && (offset != 0))
 					continue;
-			if (!memcmp(&image[offset],
-				    FMAP_SIGNATURE,
-				    strlen(FMAP_SIGNATURE))) {
+			if (is_valid_fmap(
+				(const struct fmap *)&image[offset])) {
 				fmap_found = 1;
 				break;
 			}


From gerrit at coreboot.org  Mon Sep 21 15:02:45 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 21 Sep 2015 15:02:45 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Switch to fmap
	based firmware layout
References: <Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c+0@gerrit.coreboot.org>
Message-ID: <Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c+2@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11692

-gerrit

commit e4a0dda1f2cb0a61f8208015a1c54ce76b36511d
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 18:10:52 2015 +0200

    Switch to fmap based firmware layout
    
    We still add a master header for compatibility purposes, and the default
    layouts don't cover anything non-coreboot (eg. IFD regions) yet.
    
    The default layouts can be overridden by specifying an fmd file, from
    which the fmap is generated.
    
    Future work:
    - map IFD regions to fmap regions
    - non-x86: build minimalistic trampolines that jump into the first cbfs
      file, so the bootblock can be part of CBFS instead of reserving a
      whole 64K for it.
    - teach coreboot's cbfs code to work without the master header
    - teach coreboot's cbfs code to work on different fmap regions
    
    Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 Makefile.inc                  | 75 +++++++++++++++++++++++++++++++++++++++++--
 util/cbfstool/default-x86.fmd | 15 +++++++++
 util/cbfstool/default.fmd     | 17 ++++++++++
 3 files changed, 104 insertions(+), 3 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 46d6eb2..ee49118 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -566,10 +566,79 @@ prebuild-files = \
 	       $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&))
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
+ifeq ($(CONFIG_ARCH_X86),y)
+DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd
+# entire flash
+FMAP_ROM_BASE := $(CONFIG_ROM_START)
+FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
+# entire "BIOS" region (everything directly of concern to the host system)
+# relative to ROM_BASE
+FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE))
+FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
+# position and size of flashmap, relative to BIOS_BASE
+FMAP_FMAP_BASE := 0
+FMAP_FMAP_SIZE := 0x100
+# position and size of CBFS, relative to BIOS_BASE
+FMAP_CBFS_BASE := $(FMAP_FMAP_SIZE)
+FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_FMAP_SIZE))
+else
+DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
+# entire flash
+FMAP_ROM_BASE := $(CONFIG_ROM_START)
+FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
+# entire "BIOS" region (everything directly of concern to the host system)
+# relative to ROM_BASE
+FMAP_BIOS_BASE := 0
+FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
+# position and size of flashmap, relative to BIOS_BASE
+FMAP_FMAP_BASE := 0x10000
+FMAP_FMAP_SIZE := 0x100
+# position and size of CBFS, relative to BIOS_BASE
+FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
+FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
+endif
+
 $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
-	$(CBFSTOOL) $@.tmp create \
-	-B $(objcbfs)/bootblock.bin \
-	$(CBFSTOOL_PRE1_OPTS)
+ifeq ($(CONFIG_FMDFILE),)
+	sed -e "s,##ROM_BASE##,$(FMAP_ROM_BASE)," \
+	    -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \
+	    -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \
+	    -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \
+	    -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \
+	    -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \
+	    -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
+	    -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
+		$(DEFAULT_FLASHMAP) > $@.tmp.fmd
+	$(FMAPTOOL) $@.tmp.fmd $@.tmp.fmap
+else
+	$(FMAPTOOL) $(CONFIG_FMDFILE) $@.tmp.fmap
+endif
+	$(CBFSTOOL) $@.tmp create -M $@.tmp.fmap
+ifeq ($(CONFIG_ARCH_X86),y)
+	$(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock \
+		-t bootblock \
+		-b -$(call file-size,$(objcbfs)/bootblock.bin)
+else
+	# don't add bootblock to cbfs yet, it's just a waste of space
+	true $(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock \
+		-t bootblock \
+		-b 0
+	$(CBFSTOOL) $@.tmp write -u \
+		-r BOOTBLOCK \
+		-f $(objcbfs)/bootblock.bin
+	printf "ptr_" > $@.tmp.2 # 4 characters
+	$(CBFSTOOL) $@.tmp add \
+		-f $@.tmp.2 \
+		-n "header pointer" \
+		-t "cbfs header" \
+		-b -4
+	rm -f $@.tmp.2
+endif
+	$(CBFSTOOL) $@.tmp add-master-header
 	$(prebuild-files) true
 	mv $@.tmp $@
 else
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
new file mode 100644
index 0000000..d7d0326
--- /dev/null
+++ b/util/cbfstool/default-x86.fmd
@@ -0,0 +1,15 @@
+# layout for firmware residing at top of 4GB address space
+# 4GB - ROM_SIZE:	start of flash
+# 4GB - CBFS_SIZE:	start of fmap
+#  + 0x100:		start of CBFS
+# 4GB			end of flash
+
+# ##CBFS_SIZE## differs from the CBFS_SIZE specified above in that it already
+# excludes the fmap size. CONFIG_CBFS_SIZE contains it.
+
+FLASH@##ROM_BASE## ##ROM_SIZE## {
+	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
+		FMAP@##FMAP_BASE## ##FMAP_SIZE##
+		COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
+	}
+}
diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd
new file mode 100644
index 0000000..21617d5
--- /dev/null
+++ b/util/cbfstool/default.fmd
@@ -0,0 +1,17 @@
+# layout for firmware when flash address space matches used address layout
+# 0:			start of flash, start of bootblock region
+# 0x10000:		start of fmap
+# 0x10100:		start of cbfs
+# CBFS_SIZE		end of fmap, end of used flash space
+# ROM_SIZE		end of flash
+
+# ##CBFS_SIZE## differs from the CBFS_SIZE specified above in that it already
+# excludes the fmap size. CONFIG_CBFS_SIZE contains it.
+
+FLASH@##ROM_BASE## ##ROM_SIZE## {
+	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
+		BOOTBLOCK 64K
+		FMAP@##FMAP_BASE## ##FMAP_SIZE##
+		COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
+	}
+}


From gerrit at coreboot.org  Mon Sep 21 16:03:51 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 21 Sep 2015 16:03:51 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool: add
	new add-master-header command
References: <I5bc7fbcb5962b35a95261f30f0c93008e760680d+0@gerrit.coreboot.org>
Message-ID: <E1Ze3ZH-0006U7-VE@mail.coreboot.org>

the following patch was just integrated into master:
commit 59e52b975e3ffe29709f82e57849ccf8254b9cd1
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Thu Sep 10 15:28:27 2015 +0200

    cbfstool: add new add-master-header command
    
    The command adds a new cbfs file, fills in the CBFS meta data in cbfs
    master header format, then points the master header pointer (which
    resides at the last 4 bytes of the CBFS region) to the data area of the
    new file.
    
    This can leak some space in CBFS if an old-style CBFS with native master
    header gets the treatment, because a new header is created and pointed
    at. flashmap based images have no such header, and the attempt to create
    a second file with the (hardcoded) name will fail.
    
    Change-Id: I5bc7fbcb5962b35a95261f30f0c93008e760680d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11628
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11628 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 21 16:04:29 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 21 Sep 2015 16:04:29 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool: make
	fmap search more strict
References: <Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9+0@gerrit.coreboot.org>
Message-ID: <E1Ze3Zt-0000BH-IQ@mail.coreboot.org>

the following patch was just integrated into master:
commit b946f12ed0c4a4177b64c032f17dd5b3fd2a0c99
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Sat Sep 19 13:59:36 2015 +0200

    cbfstool: make fmap search more strict
    
    Since fmap doesn't come with a checksum, we resort to a number of
    heuristics to determine if a given location hosts an fmap (instead of
    another data structure that happens to store the fmap magic string at
    the right location).
    
    The version test is particularly effective against strings containing
    the magic (which either terminate with 0, or have some other ASCII data,
    but rarely a '\001' byte inside the string).
    
    Change-Id: Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11690
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11690 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 21 17:51:11 2015
From: gerrit at coreboot.org (Alexander Couzens (lynxis@fe80.eu))
Date: Mon, 21 Sep 2015 17:51:11 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: mipseb support
	+ ath79
References: <I6c514d8bd75338f0f47698eee66fa2b11b80d697+0@gerrit.coreboot.org>
Message-ID: <I6c514d8bd75338f0f47698eee66fa2b11b80d697+1@gerrit.coreboot.org>

Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11694

-gerrit

commit 5883a7f34c11929e86e9137d7b0594e7d5e68eb5
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Fri Sep 18 05:23:38 2015 +0200

    mipseb support + ath79
    
    this is just hacky big stupid commit to let other people see over.
    /src/arch/mipseb/ is just copied over from  arch/mips (mipsel).
    
    /src/console must apply the same fixes for mipsel.
    
    Change-Id: I6c514d8bd75338f0f47698eee66fa2b11b80d697
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 Makefile.inc                                       |  14 +-
 src/arch/mipseb/Kconfig                            |  40 ++
 src/arch/mipseb/Makefile.inc                       |  99 ++++
 src/arch/mipseb/ashldi3.c                          |  55 ++
 src/arch/mipseb/boot.c                             |  29 ++
 src/arch/mipseb/bootblock.S                        |  48 ++
 src/arch/mipseb/bootblock_simple.c                 |  45 ++
 src/arch/mipseb/cache.c                            | 119 +++++
 src/arch/mipseb/include/arch/byteorder.h           |  29 ++
 src/arch/mipseb/include/arch/cache.h               |  48 ++
 src/arch/mipseb/include/arch/cpu.h                 | 171 +++++++
 src/arch/mipseb/include/arch/early_variables.h     |  31 ++
 src/arch/mipseb/include/arch/exception.h           |  25 +
 src/arch/mipseb/include/arch/header.ld             |  32 ++
 src/arch/mipseb/include/arch/hlt.h                 |  29 ++
 src/arch/mipseb/include/arch/io.h                  |  70 +++
 src/arch/mipseb/include/arch/memlayout.h           |  33 ++
 src/arch/mipseb/include/arch/mmu.h                 |  59 +++
 src/arch/mipseb/include/arch/pci_ops.h             |  30 ++
 src/arch/mipseb/include/arch/stages.h              |  28 ++
 src/arch/mipseb/include/arch/types.h               |  67 +++
 src/arch/mipseb/include/bootblock_common.h         |  30 ++
 src/arch/mipseb/include/stdint.h                   | 104 ++++
 src/arch/mipseb/mmu.c                              | 104 ++++
 src/arch/mipseb/stages.c                           |  32 ++
 src/arch/mipseb/tables.c                           |  61 +++
 src/console/Kconfig                                |   2 +-
 src/console/vtxprintf.c                            |   2 +
 src/cpu/mips/Kconfig                               |   7 +
 src/mainboard/ubiquity/Kconfig                     |  34 ++
 src/mainboard/ubiquity/Kconfig.name                |   2 +
 src/mainboard/ubiquity/nanostation_xm/Kconfig      |  61 +++
 src/mainboard/ubiquity/nanostation_xm/Kconfig.name |   2 +
 src/mainboard/ubiquity/nanostation_xm/Makefile.inc |  29 ++
 src/mainboard/ubiquity/nanostation_xm/bootblock.c  |  35 ++
 src/mainboard/ubiquity/nanostation_xm/clocks.c     |  23 +
 .../ubiquity/nanostation_xm/devicetree.cb          |  23 +
 src/mainboard/ubiquity/nanostation_xm/mainboard.c  |  17 +
 src/mainboard/ubiquity/nanostation_xm/memlayout.ld |   1 +
 src/soc/atheros/ar7240/Kconfig                     |  40 ++
 src/soc/atheros/ar7240/Makefile.inc                |  60 +++
 src/soc/atheros/ar7240/bootblock.c                 |  65 +++
 src/soc/atheros/ar7240/cbmem.c                     |  29 ++
 src/soc/atheros/ar7240/clocks.c                    | 101 ++++
 src/soc/atheros/ar7240/ddr1_init.c                 |   0
 src/soc/atheros/ar7240/ddr2_init.c                 |   0
 src/soc/atheros/ar7240/include/soc/clocks.h        |  91 ++++
 src/soc/atheros/ar7240/include/soc/ddr_init.h      |  26 +
 .../atheros/ar7240/include/soc/ddr_private_reg.h   | 138 +++++
 src/soc/atheros/ar7240/include/soc/gpio.h          |  25 +
 src/soc/atheros/ar7240/include/soc/memlayout.ld    |  60 +++
 src/soc/atheros/ar7240/include/soc/spi.h           | 358 +++++++++++++
 src/soc/atheros/ar7240/monotonic_timer.c           |  51 ++
 src/soc/atheros/ar7240/romstage.c                  |  10 +
 src/soc/atheros/ar7240/spi.c                       | 188 +++++++
 src/soc/atheros/ar7240/uart.c                      | 162 ++++++
 src/soc/atheros/common/include/soc/ar71xx_regs.h   | 559 +++++++++++++++++++++
 toolchain.inc                                      |   4 +
 util/crossgcc/Makefile                             |  13 +-
 util/crossgcc/README                               |   1 +
 util/crossgcc/buildgcc                             |   3 +-
 util/xcompile/xcompile                             |  20 +-
 62 files changed, 3664 insertions(+), 10 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..380fc36 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -458,9 +458,9 @@ gitconfig:
 	git config remote.origin.push HEAD:refs/for/master
 	(git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email at example.com\n'; exit 1)
 
-crossgcc: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv
+crossgcc: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-mipseb crossgcc-riscv
 
-.PHONY: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv
+.PHONY: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-mipseb crossgcc-riscv
 crossgcc-i386: clean-for-update
 	$(MAKE) -C util/crossgcc build-i386-without-gdb
 
@@ -476,12 +476,15 @@ crossgcc-aarch64: clean-for-update
 crossgcc-mips: clean-for-update
 	$(MAKE) -C util/crossgcc build-mips-without-gdb
 
+crossgcc-mipseb: clean-for-update
+	$(MAKE) -C util/crossgcc build-mipseb-without-gdb
+
 crossgcc-riscv: clean-for-update
 	$(MAKE) -C util/crossgcc build-riscv-without-gdb
 
-crosstools: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv
+crosstools: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-mipseb crosstools-riscv
 
-.PHONY: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv
+.PHONY: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-mipseb crosstools-riscv
 crosstools-i386: clean-for-update
 	$(MAKE) -C util/crossgcc build-i386
 
@@ -497,6 +500,9 @@ crosstools-aarch64: clean-for-update
 crosstools-mips: clean-for-update
 	$(MAKE) -C util/crossgcc build-mips
 
+crosstools-mipseb: clean-for-update
+	$(MAKE) -C util/crossgcc build-mipseb
+
 crosstools-riscv: clean-for-update
 	$(MAKE) -C util/crossgcc build-riscv
 
diff --git a/src/arch/mipseb/Kconfig b/src/arch/mipseb/Kconfig
new file mode 100644
index 0000000..874c52f
--- /dev/null
+++ b/src/arch/mipseb/Kconfig
@@ -0,0 +1,40 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+config ARCH_MIPSEB
+	bool
+	default n
+
+config ARCH_BOOTBLOCK_MIPSEB
+	bool
+	default n
+	select ARCH_MIPSEB
+
+config ARCH_VERSTAGE_MIPSEB
+	bool
+	default n
+
+config ARCH_ROMSTAGE_MIPSEB
+	bool
+	default n
+
+config ARCH_RAMSTAGE_MIPSEB
+	bool
+	default n
diff --git a/src/arch/mipseb/Makefile.inc b/src/arch/mipseb/Makefile.inc
new file mode 100644
index 0000000..cd94b09
--- /dev/null
+++ b/src/arch/mipseb/Makefile.inc
@@ -0,0 +1,99 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+###############################################################################
+# MIPS specific options
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPSEB),y)
+CBFSTOOL_PRE1_OPTS = -m mips -s $(CONFIG_CBFS_SIZE)
+endif
+
+###############################################################################
+# bootblock
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPSEB),y)
+
+bootblock-y += boot.c
+bootblock-y += bootblock.S
+bootblock-y += bootblock_simple.c
+bootblock-y += cache.c
+bootblock-y += mmu.c
+bootblock-y += stages.c
+bootblock-y += ../../lib/memcpy.c
+bootblock-y += ../../lib/memmove.c
+bootblock-y += ../../lib/memset.c
+
+# Much of the assembly code is generated by the compiler, and may contain
+# terms which the preprocessor will happily go on to replace. For example
+# "mips" would be replaced with "1". Clear all the built in definitions to
+# prevent that.
+bootblock-S-ccopts += -undef
+
+$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
+	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
+	$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+
+endif # CONFIG_ARCH_ROMSTAGE_MIPSEB
+
+###############################################################################
+# romstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPSEB),y)
+
+romstage-y += boot.c
+romstage-y += cache.c
+romstage-y += mmu.c
+romstage-y += stages.c
+romstage-y += ../../lib/memcpy.c
+romstage-y += ../../lib/memmove.c
+romstage-y += ../../lib/memset.c
+
+$(objcbfs)/romstage.debug: $$(romstage-objs)
+	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
+	$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+
+endif # CONFIG_ARCH_ROMSTAGE_MIPS CONFIG_ARCH_ROMSTAGE_MIPSEB
+
+###############################################################################
+# ramstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPSEB),y)
+
+ramstage-y += ashldi3.c
+ramstage-y += boot.c
+ramstage-y += cache.c
+ramstage-y += mmu.c
+ramstage-y += stages.c
+ramstage-y += tables.c
+ramstage-y += ../../lib/memcpy.c
+ramstage-y += ../../lib/memmove.c
+ramstage-y += ../../lib/memset.c
+
+ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
+
+$(objcbfs)/ramstage.debug: $$(ramstage-objs)
+	@printf "    CC         $(subst $(obj)/,,$(@))\n"
+	$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+
+endif # CONFIG_ARCH_RAMSTAGE_MIPSEB
diff --git a/src/arch/mipseb/ashldi3.c b/src/arch/mipseb/ashldi3.c
new file mode 100644
index 0000000..5bc73f2
--- /dev/null
+++ b/src/arch/mipseb/ashldi3.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * Based on linux arch/mips/lib/ashldi3.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+typedef unsigned word_type;
+long long __ashldi3(long long u, word_type b);
+
+struct DWstruct {
+	int low, high;
+};
+typedef union {
+	struct DWstruct s;
+	long long ll;
+} DWunion;
+
+long long __ashldi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.low = 0;
+		w.s.high = (unsigned int) uu.s.low << -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+		w.s.low = (unsigned int) uu.s.low << b;
+		w.s.high = ((unsigned int) uu.s.high << b) | carries;
+	}
+
+	return w.ll;
+}
diff --git a/src/arch/mipseb/boot.c b/src/arch/mipseb/boot.c
new file mode 100644
index 0000000..c09af05
--- /dev/null
+++ b/src/arch/mipseb/boot.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/stages.h>
+#include <program_loading.h>
+
+void arch_prog_run(struct prog *prog)
+{
+	void *cb_tables = prog_entry_arg(prog);
+	void (*doit)(void *) = prog_entry(prog);
+
+	doit(cb_tables);
+}
diff --git a/src/arch/mipseb/bootblock.S b/src/arch/mipseb/bootblock.S
new file mode 100644
index 0000000..e24848d
--- /dev/null
+++ b/src/arch/mipseb/bootblock.S
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+.set	noreorder	/* Prevent assembler from "optimizing" this code. */
+
+.section ".text._start", "ax", %progbits
+.globl _start
+_start:
+	/* Set the stack pointer */
+	la	$sp, _estack
+
+	/*
+	 * Initialise the stack to a known value, used later to check for
+	 * overflow.
+	 */
+	la	$t0, _stack
+	addi	$t1, $sp, -4
+	li	$t2, 0xdeadbeef
+1:	sw	$t2, 0($t0)
+	bne	$t0, $t1, 1b
+	addi	$t0, $t0, 4
+
+	/* Run main */
+	b	main
+
+	/*
+	 * Should never return from main. Make sure there is no branch in the
+	 * branch delay slot.
+	 */
+2:	nop
+	b	2b
+	nop	/* Make sure there is no branch after this either. */
diff --git a/src/arch/mipseb/bootblock_simple.c b/src/arch/mipseb/bootblock_simple.c
new file mode 100644
index 0000000..1a3c677
--- /dev/null
+++ b/src/arch/mipseb/bootblock_simple.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <halt.h>
+#include <program_loading.h>
+
+void main(void)
+{
+	bootblock_cpu_init();
+
+	/* Mainboard basic init */
+	bootblock_mainboard_init();
+
+#if CONFIG_BOOTBLOCK_CONSOLE
+	console_init();
+#endif
+
+	bootblock_mmu_init();
+
+	if (init_extra_hardware()) {
+		printk(BIOS_ERR, "bootblock_simple: failed to init HW.\n");
+	} else {
+		run_romstage();
+	}
+	halt();
+}
diff --git a/src/arch/mipseb/cache.c b/src/arch/mipseb/cache.c
new file mode 100644
index 0000000..c7a125f
--- /dev/null
+++ b/src/arch/mipseb/cache.c
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cache.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <symbols.h>
+
+/* cache_op: issues cache operation for specified address */
+#define cache_op(op, addr)						\
+({									\
+	__asm__ __volatile__(						\
+		".set push\n\t"						\
+		".set noreorder\n\t"					\
+		".set mips32\n\t"					\
+		"cache %0, %1\n\t"					\
+		".set mips0\n\t"					\
+		".set pop\n\t"						\
+		:							\
+		: "i" (op), "R" (*(unsigned char *)(addr)));		\
+})
+
+#define MIPS_CONFIG1_DL_SHIFT	10
+#define MIPS_CONFIG1_DL_MASK	(0x00000007)
+#define MIPS_CONFIG1_IL_SHIFT	19
+#define MIPS_CONFIG1_IL_MASK	(0x00000007)
+#define MIPS_CONFIG2_SL_SHIFT	4
+#define MIPS_CONFIG2_SL_MASK	(0x0000000F)
+
+/*
+ * get_cache_line_size:
+ * Read config register
+ * Isolate instruction cache line size
+ * Interpret value as per MIPS manual: 2 << value
+ * Return cache line size
+ */
+static int get_cache_line_size(uint8_t type)
+{
+	switch (type) {
+	case ICACHE:
+		return 2 << ((read_c0_config1() >> MIPS_CONFIG1_IL_SHIFT) &
+				MIPS_CONFIG1_IL_MASK);
+	case DCACHE:
+		return 2 << ((read_c0_config1() >> MIPS_CONFIG1_DL_SHIFT) &
+				MIPS_CONFIG1_DL_MASK);
+	case L2CACHE:
+		return 2 << ((read_c0_config2() >> MIPS_CONFIG2_SL_SHIFT) &
+				MIPS_CONFIG2_SL_MASK);
+	default:
+		printk(BIOS_ERR, "%s: Error: unsupported cache type.\n",
+				__func__);
+		return 0;
+	}
+	return 0;
+}
+
+void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation)
+{
+	u32 line_size, line_mask;
+	uintptr_t end;
+
+	line_size = get_cache_line_size((operation >> CACHE_TYPE_SHIFT) &
+					CACHE_TYPE_MASK);
+	if (!line_size)
+		return;
+	line_mask = ~(line_size-1);
+	end = (start + (line_size - 1) + size) & line_mask;
+	start &= line_mask;
+	if ((operation & L2CACHE) == L2CACHE)
+		write_c0_l23taglo(0);
+	while (start < end) {
+		switch (operation) {
+		case CACHE_CODE(ICACHE, WB_INVD):
+			cache_op(CACHE_CODE(ICACHE, WB_INVD), start);
+			break;
+		case CACHE_CODE(DCACHE, WB_INVD):
+			cache_op(CACHE_CODE(DCACHE, WB_INVD), start);
+			break;
+		case CACHE_CODE(L2CACHE, WB_INVD):
+			cache_op(CACHE_CODE(L2CACHE, WB_INVD), start);
+			break;
+		default:
+			return;
+		}
+		start += line_size;
+	}
+	asm("sync");
+}
+
+void cache_invalidate_all(uintptr_t start, size_t size)
+{
+	perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD));
+	perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD));
+	perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD));
+}
+
+void arch_segment_loaded(uintptr_t start, size_t size, int flags)
+{
+	cache_invalidate_all(start, size);
+	if (flags & SEG_FINAL)
+		cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size);
+}
diff --git a/src/arch/mipseb/include/arch/byteorder.h b/src/arch/mipseb/include/arch/byteorder.h
new file mode 100644
index 0000000..a4360ed
--- /dev/null
+++ b/src/arch/mipseb/include/arch/byteorder.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_BYTEORDER_H
+#define __MIPS_ARCH_BYTEORDER_H
+
+#ifndef __ORDER_LITTLE_ENDIAN__
+#errror "What endian are you!?"
+#endif
+
+#define __LITTLE_ENDIAN 1234
+
+#endif /* __MIPS_ARCH_BYTEORDER_H */
diff --git a/src/arch/mipseb/include/arch/cache.h b/src/arch/mipseb/include/arch/cache.h
new file mode 100644
index 0000000..a6fda1e
--- /dev/null
+++ b/src/arch/mipseb/include/arch/cache.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_CACHE_H
+#define __MIPS_ARCH_CACHE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#define CACHE_TYPE_SHIFT	(0)
+#define CACHE_OP_SHIFT		(2)
+#define CACHE_TYPE_MASK		(0x3)
+#define CACHE_OP_MASK		(0x7)
+
+/* Cache type */
+#define ICACHE			0x00
+#define DCACHE			0x01
+#define L2CACHE			0x03
+
+/* Cache operation*/
+#define WB_INVD			0x05
+
+#define CACHE_CODE(type, op)	((((type) & (CACHE_TYPE_MASK)) <<	\
+				(CACHE_TYPE_SHIFT)) |			\
+				(((op) & (CACHE_OP_MASK)) << (CACHE_OP_SHIFT)))
+
+/* Perform cache operation on cache lines for target addresses */
+void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation);
+/* Invalidate all caches: instruction, data, L2 data */
+void cache_invalidate_all(uintptr_t start, size_t size);
+
+#endif /* __MIPS_ARCH_CACHE_H */
diff --git a/src/arch/mipseb/include/arch/cpu.h b/src/arch/mipseb/include/arch/cpu.h
new file mode 100644
index 0000000..a13113c
--- /dev/null
+++ b/src/arch/mipseb/include/arch/cpu.h
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_CPU_H
+#define __MIPS_ARCH_CPU_H
+
+#define asmlinkage
+
+#ifndef __PRE_RAM__
+
+#include <device/device.h>
+
+struct cpu_driver {
+	struct device_operations *ops;
+	struct cpu_device_id *id_table;
+};
+
+struct thread;
+
+struct cpu_info {
+	device_t cpu;
+	unsigned long index;
+};
+
+#endif /* !__PRE_RAM__ */
+
+/***************************************************************************
+ * The following section was copied from arch/mips/include/asm/mipsregs.h in
+ * the 3.14 kernel tree.
+ */
+
+/*
+ * Macros to access the system control coprocessor
+ */
+
+#define __read_32bit_c0_register(source, sel)				\
+({ int __res;								\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mfc0\t%0, " #source "\n\t"			\
+			: "=r" (__res));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mfc0\t%0, " #source ", " #sel "\n\t"		\
+			".set\tmips0\n\t"				\
+			: "=r" (__res));				\
+	__res;								\
+})
+
+#define __write_32bit_c0_register(register, sel, value)			\
+do {									\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mtc0\t%z0, " #register "\n\t"			\
+			: : "Jr" ((unsigned int)(value)));		\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
+			".set\tmips0"					\
+			: : "Jr" ((unsigned int)(value)));		\
+} while (0)
+
+/* Shortcuts to access various internal registers, keep adding as needed. */
+#define read_c0_index()		__read_32bit_c0_register($0, 0)
+#define write_c0_index(val)	__write_32bit_c0_register($0, 0, (val))
+
+#define read_c0_entrylo0()	__read_32bit_c0_register($2, 0)
+#define write_c0_entrylo0(val)	__write_32bit_c0_register($2, 0, (val))
+
+#define read_c0_entrylo1()	__read_32bit_c0_register($3, 0)
+#define write_c0_entrylo1(val)	__write_32bit_c0_register($3, 0, (val))
+
+#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, (val))
+
+#define read_c0_wired()		__read_32bit_c0_register($6, 0)
+#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, (val))
+
+#define read_c0_count()		__read_32bit_c0_register($9, 0)
+#define write_c0_count(val)	__write_32bit_c0_register($9, 0, (val))
+
+#define read_c0_entryhi()	__read_32bit_c0_register($10, 0)
+#define write_c0_entryhi(val)	__write_32bit_c0_register($10, 0, (val))
+
+#define read_c0_cause()		__read_32bit_c0_register($13, 0)
+#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, (val))
+
+#define read_c0_config1()	__read_32bit_c0_register($16, 1)
+#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, (val))
+
+#define read_c0_config2()	__read_32bit_c0_register($16, 2)
+#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, (val))
+
+#define read_c0_l23taglo()	__read_32bit_c0_register($28, 4)
+#define write_c0_l23taglo(val)	__write_32bit_c0_register($28, 4, (val))
+
+
+#define C0_ENTRYLO_PFN_SHIFT 6
+#define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */
+#define C0_ENTRYLO_D (0x1 << 2) /* Writeable */
+#define C0_ENTRYLO_V (0x1 << 1) /* Valid */
+#define C0_ENTRYLO_G (0x1 << 0) /* Global */
+
+#define C0_PAGEMASK_SHIFT 13
+#define C0_PAGEMASK_MASK 0xffff
+
+#define C0_WIRED_MASK 0x3f
+
+#define C0_CAUSE_DC (1 << 27)
+
+#define C0_CONFIG1_MMUSIZE_SHIFT 25
+#define C0_CONFIG1_MMUSIZE_MASK 0x3f
+
+/* Hazard handling */
+static inline void __nop(void)
+{
+	__asm__ __volatile__("nop");
+}
+
+static inline void __ssnop(void)
+{
+	__asm__ __volatile__("sll\t$0, $0, 1");
+}
+
+#define mtc0_tlbw_hazard()						\
+do {									\
+	__nop();							\
+	__nop();							\
+} while (0)
+
+#define tlbw_use_hazard()						\
+do {									\
+	__nop();							\
+	__nop();							\
+	__nop();							\
+} while (0)
+
+#define tlb_probe_hazard()						\
+do {									\
+	__nop();							\
+	__nop();							\
+	__nop();							\
+} while (0)
+
+#define back_to_back_c0_hazard()					\
+do {									\
+	__ssnop();							\
+	__ssnop();							\
+	__ssnop();							\
+} while (0)
+/**************************************************************************/
+
+#endif /* __MIPS_ARCH_CPU_H */
diff --git a/src/arch/mipseb/include/arch/early_variables.h b/src/arch/mipseb/include/arch/early_variables.h
new file mode 100644
index 0000000..c21fa8c
--- /dev/null
+++ b/src/arch/mipseb/include/arch/early_variables.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_EARLY_VARIABLES_H
+#define __MIPS_ARCH_EARLY_VARIABLES_H
+
+#define CAR_GLOBAL
+#define CAR_MIGRATE(migrate_fn_)
+
+static inline void *car_get_var_ptr(void *var) { return var; }
+#define car_get_var(var) (var)
+#define car_sync_var(var) (var)
+#define car_set_var(var, val) { (var) = (val); }
+
+#endif /* __MIPS_ARCH_EARLY_VARIABLES_H */
diff --git a/src/arch/mipseb/include/arch/exception.h b/src/arch/mipseb/include/arch/exception.h
new file mode 100644
index 0000000..a872c04
--- /dev/null
+++ b/src/arch/mipseb/include/arch/exception.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_EXCEPTION_H
+#define __MIPS_ARCH_EXCEPTION_H
+
+static inline void exception_init(void) {}
+
+#endif /* __MIPS_ARCH_EXCEPTION_H */
diff --git a/src/arch/mipseb/include/arch/header.ld b/src/arch/mipseb/include/arch/header.ld
new file mode 100644
index 0000000..9310e33
--- /dev/null
+++ b/src/arch/mipseb/include/arch/header.ld
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_ARCH(mips)
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+#ifdef __BOOTBLOCK__
+ENTRY(_start)
+#else
+ENTRY(stage_entry)
+#endif
diff --git a/src/arch/mipseb/include/arch/hlt.h b/src/arch/mipseb/include/arch/hlt.h
new file mode 100644
index 0000000..3d66beb
--- /dev/null
+++ b/src/arch/mipseb/include/arch/hlt.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_HLT_H
+#define __MIPS_ARCH_HLT_H
+
+static inline __attribute__((always_inline)) void hlt(void)
+{
+	for (;;)
+		;
+}
+
+#endif /* __MIPS_ARCH_HLT_H */
diff --git a/src/arch/mipseb/include/arch/io.h b/src/arch/mipseb/include/arch/io.h
new file mode 100644
index 0000000..95c40d8
--- /dev/null
+++ b/src/arch/mipseb/include/arch/io.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * Based on arch/armv7/include/arch/io.h:
+ *   Copyright 2013 Google Inc.
+ *   Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_IO_H
+#define __MIPS_ARCH_IO_H
+
+#include <types.h>
+#include <arch/cache.h>
+#include <endian.h>
+
+static inline uint8_t read8(unsigned long addr)
+{
+	asm("sync");
+	return *(volatile uint8_t *)addr;
+}
+
+static inline uint16_t read16(unsigned long addr)
+{
+	asm("sync");
+	return *(volatile uint16_t *)addr;
+}
+
+static inline uint32_t read32(unsigned long addr)
+{
+	asm("sync");
+	return *(volatile uint32_t *)addr;
+}
+
+static inline void write8(unsigned long addr, uint8_t val)
+{
+	asm("sync");
+	*(volatile uint8_t *)addr = val;
+	asm("sync");
+}
+
+static inline void write16(unsigned long addr, uint16_t val)
+{
+	asm("sync");
+	*(volatile uint16_t *)addr = val;
+	asm("sync");
+}
+
+static inline void write32(unsigned long addr, uint32_t val)
+{
+	asm("sync");
+	*(volatile uint32_t *)addr = val;
+	asm("sync");
+}
+
+#endif	/* __MIPS_ARCH_IO_H */
diff --git a/src/arch/mipseb/include/arch/memlayout.h b/src/arch/mipseb/include/arch/memlayout.h
new file mode 100644
index 0000000..946fcf3
--- /dev/null
+++ b/src/arch/mipseb/include/arch/memlayout.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file contains macro definitions for memlayout.ld linker scripts. */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */
+/* TODO: Double-check that that's the correct alignment for our ABI. */
+#define STACK(addr, size) \
+	REGION(stack, addr, size, 8) \
+	_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc");
+
+#define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K)
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/mipseb/include/arch/mmu.h b/src/arch/mipseb/include/arch/mmu.h
new file mode 100644
index 0000000..e931ad9
--- /dev/null
+++ b/src/arch/mipseb/include/arch/mmu.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_MMU_H
+#define __MIPS_ARCH_MMU_H
+
+#include <arch/cpu.h>
+#include <stddef.h>
+#include <stdint.h>
+
+static inline void tlb_write_indexed(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbwi\n\t"
+		".set reorder");
+}
+
+static inline uint32_t get_max_pagesize(void)
+{
+	uint32_t max_pgsize;
+
+	write_c0_pagemask(C0_PAGEMASK_MASK << C0_PAGEMASK_SHIFT);
+	back_to_back_c0_hazard();
+	max_pgsize = (((read_c0_pagemask() >> C0_PAGEMASK_SHIFT) &
+		       C0_PAGEMASK_MASK) + 1) * 4 * KiB;
+
+	return max_pgsize;
+}
+
+static inline uint32_t get_tlb_size(void)
+{
+	uint32_t tlbsize;
+
+	tlbsize = ((read_c0_config1() >> C0_CONFIG1_MMUSIZE_SHIFT) &
+		   C0_CONFIG1_MMUSIZE_MASK) + 1;
+
+	return tlbsize;
+}
+
+int identity_map(uint32_t start, size_t len);
+
+#endif /* __MIPS_ARCH_MMU_H */
diff --git a/src/arch/mipseb/include/arch/pci_ops.h b/src/arch/mipseb/include/arch/pci_ops.h
new file mode 100644
index 0000000..df51a5a
--- /dev/null
+++ b/src/arch/mipseb/include/arch/pci_ops.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef ARCH_MIPS_PCI_OPS_H
+#define ARCH_MIPS_PCI_OPS_H
+
+#include <stddef.h>
+
+static inline const struct pci_bus_operations *pci_config_default(void)
+{
+	return NULL;
+}
+
+#endif
diff --git a/src/arch/mipseb/include/arch/stages.h b/src/arch/mipseb/include/arch/stages.h
new file mode 100644
index 0000000..17115cb
--- /dev/null
+++ b/src/arch/mipseb/include/arch/stages.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_STAGES_H
+#define __MIPS_ARCH_STAGES_H
+
+extern void main(void);
+
+void stage_entry(void);
+void stage_exit(void *);
+
+#endif /* __MIPS_ARCH_STAGES_H */
diff --git a/src/arch/mipseb/include/arch/types.h b/src/arch/mipseb/include/arch/types.h
new file mode 100644
index 0000000..4e12181
--- /dev/null
+++ b/src/arch/mipseb/include/arch/types.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * Based on src/arch/armv7/include/arch/types.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_TYPES_H
+#define __MIPS_ARCH_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __MIPS_ARCH_TYPES_H */
diff --git a/src/arch/mipseb/include/bootblock_common.h b/src/arch/mipseb/include/bootblock_common.h
new file mode 100644
index 0000000..4b2fd08
--- /dev/null
+++ b/src/arch/mipseb/include/bootblock_common.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifdef CONFIG_BOOTBLOCK_CPU_INIT
+#include CONFIG_BOOTBLOCK_CPU_INIT
+#endif
+
+#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
+#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
+#else
+static void bootblock_mainboard_init(void)
+{
+}
+#endif
diff --git a/src/arch/mipseb/include/stdint.h b/src/arch/mipseb/include/stdint.h
new file mode 100644
index 0000000..a9579f5
--- /dev/null
+++ b/src/arch/mipseb/include/stdint.h
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Based on src/arch/armv7/include/stdint.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_STDINT_H
+#define __MIPS_STDINT_H
+
+#if defined(__GNUC__)
+#define __HAVE_LONG_LONG__ 1
+#else
+#define __HAVE_LONG_LONG__ 0
+#endif
+
+/* Exact integral types */
+typedef unsigned char      uint8_t;
+typedef signed char        int8_t;
+
+typedef unsigned short     uint16_t;
+typedef signed short       int16_t;
+
+typedef unsigned int       uint32_t;
+typedef signed int         int32_t;
+
+#if __HAVE_LONG_LONG__
+typedef unsigned long long uint64_t;
+typedef signed long long   int64_t;
+#endif
+
+/* Small types */
+typedef unsigned char      uint_least8_t;
+typedef signed char        int_least8_t;
+
+typedef unsigned short     uint_least16_t;
+typedef signed short       int_least16_t;
+
+typedef unsigned int       uint_least32_t;
+typedef signed int         int_least32_t;
+
+#if __HAVE_LONG_LONG__
+typedef unsigned long long uint_least64_t;
+typedef signed long long   int_least64_t;
+#endif
+
+/* Fast Types */
+typedef unsigned char      uint_fast8_t;
+typedef signed char        int_fast8_t;
+
+typedef unsigned int       uint_fast16_t;
+typedef signed int         int_fast16_t;
+
+typedef unsigned int       uint_fast32_t;
+typedef signed int         int_fast32_t;
+
+#if __HAVE_LONG_LONG__
+typedef unsigned long long uint_fast64_t;
+typedef signed long long   int_fast64_t;
+#endif
+
+/* Types for `void *' pointers.  */
+typedef int                intptr_t;
+typedef unsigned int       uintptr_t;
+
+/* Largest integral types */
+#if __HAVE_LONG_LONG__
+typedef long long int      intmax_t;
+typedef unsigned long long uintmax_t;
+#else
+typedef long int           intmax_t;
+typedef unsigned long int  uintmax_t;
+#endif
+
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#if __HAVE_LONG_LONG__
+typedef uint64_t u64;
+#endif
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+
+typedef uint8_t bool;
+#define true	1
+#define false	0
+
+
+#undef __HAVE_LONG_LONG__
+
+#endif /* __MIPS_STDINT_H */
diff --git a/src/arch/mipseb/mmu.c b/src/arch/mipseb/mmu.c
new file mode 100644
index 0000000..706d05e
--- /dev/null
+++ b/src/arch/mipseb/mmu.c
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cpu.h>
+#include <arch/mmu.h>
+#include <console/console.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#define MIN_PAGE_SIZE (4 * KiB)
+
+static int add_wired_tlb_entry(uint32_t entrylo0, uint32_t entrylo1,
+			       uint32_t entryhi, uint32_t pgsize)
+{
+	uint32_t tlbindex;
+
+	tlbindex = read_c0_wired();
+	if (tlbindex >= get_tlb_size() || tlbindex >= C0_WIRED_MASK) {
+		printk(BIOS_ERR, "Ran out of TLB entries\n");
+		return -1;
+	}
+	write_c0_wired(tlbindex + 1);
+	write_c0_index(tlbindex);
+	write_c0_pagemask(((pgsize / MIN_PAGE_SIZE) - 1) << C0_PAGEMASK_SHIFT);
+	write_c0_entryhi(entryhi);
+	write_c0_entrylo0(entrylo0);
+	write_c0_entrylo1(entrylo1);
+	mtc0_tlbw_hazard();
+	tlb_write_indexed();
+	tlbw_use_hazard();
+
+	return 0;
+}
+
+static uint32_t pick_pagesize(uint32_t start, uint32_t len)
+{
+	uint32_t pgsize, max_pgsize;
+
+	max_pgsize = get_max_pagesize();
+	for (pgsize = max_pgsize;
+	     pgsize >= MIN_PAGE_SIZE;
+	     pgsize = pgsize / 4) {
+		/*
+		 * Each TLB entry maps a pair of virtual pages.  To avoid
+		 * aliasing, pick the largest page size that is at most
+		 * half the size of the region we're trying to map.
+		 */
+		if (IS_ALIGNED(start, 2 * pgsize) && (2 * pgsize <= len))
+			break;
+	}
+
+	return pgsize;
+}
+
+/*
+ * Identity map the memory from [start,start+len] in the TLB using the
+ * largest suitable page size so as to conserve TLB entries.
+ */
+int identity_map(uint32_t start, size_t len)
+{
+	uint32_t pgsize, pfn, entryhi, entrylo0, entrylo1;
+
+	while (len > 0) {
+		pgsize = pick_pagesize(start, len);
+		entryhi = start;
+		pfn = start >> 12;
+		entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | C0_ENTRYLO_WB |
+			C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G;
+		start += pgsize;
+		len -= MIN(len, pgsize);
+		if (len >= pgsize) {
+			pfn = start >> 12;
+			entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) |
+				C0_ENTRYLO_WB | C0_ENTRYLO_D | C0_ENTRYLO_V |
+				C0_ENTRYLO_G;
+			start += pgsize;
+			len -= MIN(len, pgsize);
+		} else {
+			entrylo1 = 0;
+		}
+		if (add_wired_tlb_entry(entrylo0, entrylo1, entryhi, pgsize))
+			return -1;
+	}
+
+	return 0;
+}
diff --git a/src/arch/mipseb/stages.c b/src/arch/mipseb/stages.c
new file mode 100644
index 0000000..f6cefbb
--- /dev/null
+++ b/src/arch/mipseb/stages.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/stages.h>
+#include <arch/cache.h>
+
+void stage_entry(void)
+{
+	main();
+}
+
+void stage_exit(void *addr)
+{
+	void (*doit)(void) = addr;
+	doit();
+}
diff --git a/src/arch/mipseb/tables.c b/src/arch/mipseb/tables.c
new file mode 100644
index 0000000..3d6d701
--- /dev/null
+++ b/src/arch/mipseb/tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Based on src/arch/armv7/tables.c:
+ *   Copyright (C) 2003 Eric Biederman
+ *   Copyright (C) 2005 Steve Magnani
+ *   Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <boot/coreboot_tables.h>
+#include <string.h>
+#include <cbmem.h>
+#include <lib.h>
+
+#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+
+void write_tables(void)
+{
+	unsigned long table_pointer, new_table_pointer;
+
+	post_code(0x9d);
+
+	table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
+						 MAX_COREBOOT_TABLE_SIZE);
+	if (!table_pointer) {
+		printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
+		return;
+	}
+
+	new_table_pointer = write_coreboot_table(0UL, 0UL, table_pointer,
+						 table_pointer);
+
+	if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE))
+		printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n",
+		       new_table_pointer - table_pointer,
+		       MAX_COREBOOT_TABLE_SIZE);
+
+	printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+	       new_table_pointer - table_pointer);
+
+	post_code(0x9e);
+
+	/* Print CBMEM sections */
+	cbmem_list();
+}
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 7d6fa0e..60d9ce0 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -2,7 +2,7 @@ menu "Console"
 
 config BOOTBLOCK_CONSOLE
 	bool "Enable early (bootblock) console output."
-	depends on ARCH_ARM || ARCH_RISCV || ARCH_MIPS
+	depends on ARCH_ARM || ARCH_RISCV || ARCH_MIPS || ARCH_MIPSEB
 	default n
 	help
 	  Use console during the bootblock if supported
diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
index 2fcefd2..4213baa 100644
--- a/src/console/vtxprintf.c
+++ b/src/console/vtxprintf.c
@@ -11,8 +11,10 @@
 #define call_tx(x) tx_byte(x, data)
 
 #if !CONFIG_ARCH_MIPS
+#if !CONFIG_ARCH_MIPSEB
 #define SUPPORT_64BIT_INTS
 #endif
+#endif
 
 /* haha, don't need ctype.c */
 #define isdigit(c)	((c) >= '0' && (c) <= '9')
diff --git a/src/cpu/mips/Kconfig b/src/cpu/mips/Kconfig
index d0fa1ac..c8e02f0 100644
--- a/src/cpu/mips/Kconfig
+++ b/src/cpu/mips/Kconfig
@@ -24,3 +24,10 @@ config CPU_MIPS
 	select ARCH_VERSTAGE_MIPS
 	select ARCH_ROMSTAGE_MIPS
 	select ARCH_RAMSTAGE_MIPS
+
+config CPU_MIPSEB
+	bool
+	select ARCH_BOOTBLOCK_MIPSEB
+	select ARCH_VERSTAGE_MIPSEB
+	select ARCH_ROMSTAGE_MIPSEB
+	select ARCH_RAMSTAGE_MIPSEB
diff --git a/src/mainboard/ubiquity/Kconfig b/src/mainboard/ubiquity/Kconfig
new file mode 100644
index 0000000..6f82401
--- /dev/null
+++ b/src/mainboard/ubiquity/Kconfig
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 The ChromiumOS Authors
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+if VENDOR_UBIQUITY
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/ubiquity/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/ubiquity/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string "Mainboard Vendor"
+	default "ubiquity"
+
+endif # VENDOR_UBIQUITY
diff --git a/src/mainboard/ubiquity/Kconfig.name b/src/mainboard/ubiquity/Kconfig.name
new file mode 100644
index 0000000..94aa98f
--- /dev/null
+++ b/src/mainboard/ubiquity/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_UBIQUITY
+	bool "Ubiquity"
diff --git a/src/mainboard/ubiquity/nanostation_xm/Kconfig b/src/mainboard/ubiquity/nanostation_xm/Kconfig
new file mode 100644
index 0000000..2a6d3f7
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/Kconfig
@@ -0,0 +1,61 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+if BOARD_UBIQUITY_NANOSTATION_XM
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_512
+	select BOOTBLOCK_CONSOLE
+	select SPI_FLASH_WINBOND
+	select CPU_ATHEROS_AR7240
+	select COMMON_CBFS_SPI_WRAPPER
+	select SPI_FLASH
+
+config MAINBOARD_DIR
+	string
+	default "ubiquity/nanostation_xm"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Ubiquity Nanostation"
+
+config BOOTBLOCK_MAINBOARD_INIT
+	string
+	default "mainboard/ubiquity/nanostation_xm/bootblock.c"
+
+config DRAM_SIZE_MB
+	int
+	default 32
+
+config TTYS0_LCS
+	int
+	default 3
+
+config CONSOLE_SERIAL_UART_ADDRESS
+	hex
+	depends on DRIVERS_UART
+	default 0xB8101500
+
+config BOOT_MEDIA_SPI_BUS
+	int
+	default 1
+
+endif
diff --git a/src/mainboard/ubiquity/nanostation_xm/Kconfig.name b/src/mainboard/ubiquity/nanostation_xm/Kconfig.name
new file mode 100644
index 0000000..9f75675
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_UBIQUITY_NANOSTATION_XM
+	bool "Nanostation XM"
diff --git a/src/mainboard/ubiquity/nanostation_xm/Makefile.inc b/src/mainboard/ubiquity/nanostation_xm/Makefile.inc
new file mode 100644
index 0000000..47206e4
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/Makefile.inc
@@ -0,0 +1,29 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2015 Alexander Couzens <lynxis at fe80.eu>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+bootblock-y += clocks.c
+romstage-y += clocks.c
+ramstage-y += clocks.c
+
+ramstage-y += mainboard.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/ubiquity/nanostation_xm/bootblock.c b/src/mainboard/ubiquity/nanostation_xm/bootblock.c
new file mode 100644
index 0000000..edd017f
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/bootblock.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <stdint.h>
+#include <soc/clocks.h>
+#include <assert.h>
+#include <boardid.h>
+
+static void bootblock_mainboard_init(void)
+{
+}
+
+
+static int init_extra_hardware(void)
+{
+	return 0;
+}
diff --git a/src/mainboard/ubiquity/nanostation_xm/clocks.c b/src/mainboard/ubiquity/nanostation_xm/clocks.c
new file mode 100644
index 0000000..d7ed892
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/clocks.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <soc/clocks.h>
+
+int ar71xx_get_ref_clock_mhz()
+{
+	return 40;
+}
diff --git a/src/mainboard/ubiquity/nanostation_xm/devicetree.cb b/src/mainboard/ubiquity/nanostation_xm/devicetree.cb
new file mode 100644
index 0000000..7b74d7e
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/devicetree.cb
@@ -0,0 +1,23 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+chip soc/atheros/ar7240
+	device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/ubiquity/nanostation_xm/mainboard.c b/src/mainboard/ubiquity/nanostation_xm/mainboard.c
new file mode 100644
index 0000000..c02e833
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/mainboard.c
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
diff --git a/src/mainboard/ubiquity/nanostation_xm/memlayout.ld b/src/mainboard/ubiquity/nanostation_xm/memlayout.ld
new file mode 100644
index 0000000..ead7f47
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/memlayout.ld>
diff --git a/src/soc/atheros/ar7240/Kconfig b/src/soc/atheros/ar7240/Kconfig
new file mode 100644
index 0000000..17d29ec
--- /dev/null
+++ b/src/soc/atheros/ar7240/Kconfig
@@ -0,0 +1,40 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+config CPU_ATHEROS_AR7240
+	select CPU_MIPSEB
+	select GENERIC_UDELAY
+	select HAVE_MONOTONIC_TIMER
+	select HAVE_UART_SPECIAL
+	select GENERIC_GPIO_LIB
+	bool
+
+if CPU_ATHEROS_AR7240
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "soc/atheros/ar7240/bootblock.c"
+
+config CONSOLE_SERIAL_UART_ADDRESS
+        hex
+        depends on DRIVERS_UART
+        default 0xB8020000
+
+endif
diff --git a/src/soc/atheros/ar7240/Makefile.inc b/src/soc/atheros/ar7240/Makefile.inc
new file mode 100644
index 0000000..94a06e0
--- /dev/null
+++ b/src/soc/atheros/ar7240/Makefile.inc
@@ -0,0 +1,60 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+ifeq ($(CONFIG_CPU_ATHEROS_AR7240),y)
+
+# We enable CBFS_SPI_WRAPPER for Pistachio targets.
+bootblock-y += clocks.c
+bootblock-y += spi.c
+romstage-y += spi.c
+ramstage-y += spi.c
+
+ifeq ($(CONFIG_DRIVERS_UART),y)
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
+romstage-y += uart.c
+ramstage-y += uart.c
+endif
+
+bootblock-y += monotonic_timer.c
+
+ramstage-y += cbmem.c
+ramstage-y += monotonic_timer.c
+
+romstage-y += cbmem.c
+romstage-y += ddr1_init.c
+romstage-y += ddr2_init.c
+romstage-y += romstage.c
+romstage-y += monotonic_timer.c
+
+CPPFLAGS_common += -Isrc/soc/atheros/ar7240/include/
+CPPFLAGS_common += -Isrc/soc/atheros/common/include/
+
+# Generate the actual coreboot bootblock code
+$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
+	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
+	$(OBJCOPY_bootblock) -O binary $< $@.tmp
+	@mv $@.tmp $@
+
+# Create a complete bootblock which will start up the system
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+	@printf "    BIMGTOOL   $(subst $(obj)/,,$(@))\n"
+	$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
+
+endif
diff --git a/src/soc/atheros/ar7240/bootblock.c b/src/soc/atheros/ar7240/bootblock.c
new file mode 100644
index 0000000..a047954
--- /dev/null
+++ b/src/soc/atheros/ar7240/bootblock.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cpu.h>
+#include <arch/mmu.h>
+#include <assert.h>
+#include <stdint.h>
+#include <symbols.h>
+
+static void bootblock_cpu_init(void)
+{
+	uint32_t cause;
+
+	/*
+	 * Make sure the count register is counting by clearing the "Disable
+	 * Counter" bit, in case it is set.
+	 */
+	cause = read_c0_cause();
+	if (cause & C0_CAUSE_DC)
+		write_c0_cause(cause & ~(C0_CAUSE_DC));
+
+	/* And make sure that it starts from zero. */
+	write_c0_count(0);
+}
+
+static void bootblock_mmu_init(void)
+{
+	uint32_t null_guard_size =  1 * MiB;
+	uint32_t dram_base, dram_size;
+
+	write_c0_wired(0);
+
+	dram_base = (uint32_t)_dram;
+	dram_size = CONFIG_DRAM_SIZE_MB * MiB;
+
+	/*
+	 * To be able to catch NULL pointer dereference attempts, lets not map
+	 * memory close to zero.
+	 */
+	if (dram_base < null_guard_size) {
+		dram_base += null_guard_size;
+		dram_size -= null_guard_size;
+	}
+
+	/* use config ifdef when something doesnt have sram? */
+	assert(!identity_map(dram_base, dram_size));
+	//assert(!identity_map((uint32_t)_sram, _sram_size));
+}
diff --git a/src/soc/atheros/ar7240/cbmem.c b/src/soc/atheros/ar7240/cbmem.c
new file mode 100644
index 0000000..227fd74
--- /dev/null
+++ b/src/soc/atheros/ar7240/cbmem.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbmem.h>
+#include <stdlib.h>
+#include <symbols.h>
+
+void *cbmem_top(void)
+{
+	/* the stack lives on the end */
+	return _dram + (CONFIG_DRAM_SIZE_MB << 20) - 8 * 1024;
+}
diff --git a/src/soc/atheros/ar7240/clocks.c b/src/soc/atheros/ar7240/clocks.c
new file mode 100644
index 0000000..631b2dd
--- /dev/null
+++ b/src/soc/atheros/ar7240/clocks.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <soc/ar71xx_regs.h>
+#include <assert.h>
+#include <delay.h>
+#include <soc/clocks.h>
+#include <timer.h>
+
+#include <soc/clocks.h>
+
+/* read, modify with mask + val and write it back */
+static inline void rmw32(unsigned long addr, uint32_t mask, uint32_t val) {
+	uint32_t value = read32(addr);
+	value &= ~mask;
+	value |= val;
+	write32(addr, value);
+}
+
+int ath7240_set_pll(struct pll_parameters *params) {
+	uint32_t cpu_config = 0;
+	uint32_t bypass = AR724X_CPU_PLL_BYPASS | AR724X_CPU_PLL_RESET | AR724X_CPU_PLL_NOPWD;
+
+	/* check if pll params are valid */
+	if(params->div_multiplier >= (1 << 10))
+		return 1;
+
+	if(params->refdiv >= (1 << 4))
+		return 1;
+
+	/* check if we already initilized the pll
+	 * the cpu will reset when we setup our plls and this code aren't allowed to run again
+	 * otherwise we get into a endless loop
+	 */
+	//if (read32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL)
+	//		& AR724X_CPU_PLL_RESET_SWITCH) {
+	//	return 0;
+	//}
+
+	/* bypass cpu pll, reset pll, pretend powerdown of pll */
+	rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CONFIG,
+			bypass,
+			bypass);
+
+	/* set plls */
+	cpu_config = (params->div_multiplier & AR724X_PLL_FB_MASK) << AR724X_PLL_FB_SHIFT;
+	cpu_config |= (params->refdiv & AR724X_PLL_REF_DIV_MASK) << AR724X_PLL_REF_DIV_SHIFT;
+	cpu_config |= (params->divisor_ahb & AR724X_AHB_DIV_MASK) << AR724X_AHB_DIV_SHIFT;
+	cpu_config |= (params->divisor_ddr & AR724X_DDR_DIV_MASK) << AR724X_DDR_DIV_SHIFT;
+
+	write32(AR724X_PLL_REG_CPU_CONFIG, cpu_config | bypass);
+
+	/* take pll out of reset */
+	bypass &= ~AR724X_CPU_PLL_RESET;
+	write32(AR724X_PLL_REG_CPU_CONFIG, cpu_config | bypass);
+
+	/* wait until pll is done updateing */
+	while ((read32(AR724X_PLL_REG_CPU_CONFIG) & AR724X_CPU_PLL_UPDATING) == 0)
+		;
+
+	/* disable bypass */
+	write32(AR724X_PLL_REG_CPU_CONFIG, cpu_config);
+
+	/* setting and clearing reset clock switch is taken from u-boot source GPL */
+	/* TODO: check if this is really needed. why do we need to reset the cpu ? */
+	/* cause the reset of the cpu using reset switch */
+/*	rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL,
+			AR724X_CPU_PLL_CTRL_RESET_SWITCH,
+			AR724X_CPU_PLL_CTRL_RESET_SWITCH);
+
+	rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL,
+			AR724X_CPU_PLL_CTRL_CLOCK_SWITCH,
+			AR724X_CPU_PLL_CTRL_CLOCK_SWITCH); */
+
+	/* clear AR724X_CPU_PLL_CTRL_RESET_SWITCH & AR724X_CPU_PLL_CTRL_CLOCK_SWITCH */
+/*	rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL,
+			AR724X_CPU_PLL_CTRL_RESET_SWITCH,,
+			0);
+	rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL,
+			AR724X_CPU_PLL_CTRL_CLOCK_SWITCH,,
+			0); */
+	return 0;
+}
diff --git a/src/soc/atheros/ar7240/ddr1_init.c b/src/soc/atheros/ar7240/ddr1_init.c
new file mode 100644
index 0000000..e69de29
diff --git a/src/soc/atheros/ar7240/ddr2_init.c b/src/soc/atheros/ar7240/ddr2_init.c
new file mode 100644
index 0000000..e69de29
diff --git a/src/soc/atheros/ar7240/include/soc/clocks.h b/src/soc/atheros/ar7240/include/soc/clocks.h
new file mode 100644
index 0000000..640fb4b
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/clocks.h
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_ATHEROS_AR7240_CLOCKS_H__
+#define __SOC_ATHEROS_AR7240_CLOCKS_H__
+
+/* atheros has 4 main clock source
+ * all clocks are derived from the external crystal (ref clock) via PLL.
+ *
+ * taken from Atheros Datasheet AR7242 April 2011, p 20, Figure 2-4 Basic Clocking Diagram
+ *
+ *   | Ref Clk
+ * -----
+ * |PLL|
+ * -----
+ *   |
+ * ----------
+ * \        /-- PLL Bypass
+ *  \------/
+ *    |
+ *    |---------------------------------------------------
+ *    |            |                               |
+ *    |        |----------|                  |-----------|
+ *    |        |  DIV     |                  |  DIV      |
+ *    |        | by 1 or 2| Ref Clk          | by 2 or 4 | Ref Clk
+ *    |        |----------|  |               |-----------|  |
+ *    |           |          |                   |          |
+ *    |        ----------------                ---------------
+ *    |        \              /-- PLL Bypass   \             /-- PLL Bypass
+ *    |         \------------/                  \-----------/
+ *    |              |                               |
+ *    |              |                               |
+ *    |             DDR Clock                     AHB Clock
+ *    |
+ *    |
+ *    CPU Clock
+ *
+ * Ref clock - the external crystal. 25mhz or 40mhz
+ * CPU clock
+ * DDR clock
+ * AHB clock - from this clock most subsystem will derive it's clocksa
+ *
+ */
+
+enum ref_clock {
+	REF_CLOCK25MHZ = 0,
+	REF_CLOCK40MHZ,
+};
+
+enum divisor_ddr {
+	DIV_DDR_BY_1 = 0,
+	DIV_DDR_BY_2 = 1,
+};
+
+enum divisor_ahb {
+	DIV_AHB_BY_2 = 0,
+	DIV_AHB_BY_4 = 1,
+};
+
+/* cpu clock freq calculation
+ * freq = (div_multiplier / refclock_div) * ref_clock /2
+ *
+ */
+struct pll_parameters {
+	enum ref_clock refclock;
+	enum divisor_ddr divisor_ddr;
+	enum divisor_ahb divisor_ahb;
+	int div_multiplier; /* primary multiplier - named DIV in datasheet. p51 CPU_PLL_CONFIG (AR71XX_PLL_REG_CPU_CONFIG) */
+	int refdiv; /* reference clock divider */
+};
+
+int ath7240_set_pll(struct pll_parameters *params);
+
+int get_count_mhz_freq(void);
+int ar71xx_get_ref_clock_mhz(void);
+
+#endif
diff --git a/src/soc/atheros/ar7240/include/soc/ddr_init.h b/src/soc/atheros/ar7240/include/soc/ddr_init.h
new file mode 100644
index 0000000..48bbf4e
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/ddr_init.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_IMGTEC_AR7240_DDR_INIT_H__
+#define __SOC_IMGTEC_AR7240_DDR_INIT_H__
+
+#define DDR_TIMEOUT			-1
+
+int init_ddr1(void);
+int init_ddr2(void);
+
+#endif
diff --git a/src/soc/atheros/ar7240/include/soc/ddr_private_reg.h b/src/soc/atheros/ar7240/include/soc/ddr_private_reg.h
new file mode 100644
index 0000000..5d04922
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/ddr_private_reg.h
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_IMGTEC_AR7240_DDR_PRIVATE_REG_H__
+#define __SOC_IMGTEC_AR7240_DDR_PRIVATE_REG_H__
+
+#include <timer.h>
+
+#define MAX_WAIT_MICROS			100000
+
+#define TOPLEVEL_REGS			0xB8149000
+
+#define DDR_CTRL_OFFSET			(0x0020)
+#define DDR_CLK_EN_MASK			(0x00000002)
+#define DDR_CLK_EN_SHIFT		(1)
+#define DDR_CLK_EN_LENGTH		(1)
+
+#define DDR_PCTL			0xB8180000
+#define DDR_PCTL_SCFG_OFFSET		(0x0000)
+#define DDR_PCTL_SCTL_OFFSET		(0x0004)
+#define DDR_PCTL_STAT_OFFSET		(0x0008)
+#define DDR_PCTL_MCMD_OFFSET		(0x0040)
+#define DDR_PCTL_POWCTL_OFFSET		(0x0044)
+#define DDR_PCTL_POWSTAT_OFFSET		(0x0048)
+#define DDR_PCTL_CMDTSTAT_OFFSET	(0x004C)
+#define DDR_PCTL_CMDTSTATEN_OFFSET	(0x0050)
+#define DDR_PCTL_MCFG1_OFFSET		(0x007C)
+#define DDR_PCTL_MCFG_OFFSET		(0x0080)
+#define DDR_PCTL_MSTAT_OFFSET		(0x0088)
+#define DDR_PCTL_DTUAWDT_OFFSET		(0x00B0)
+#define DDR_PCTL_TOGCNT1U_OFFSET	(0x00C0)
+#define DDR_PCTL_TINIT_OFFSET		(0x00C4)
+#define DDR_PCTL_TRSTH_OFFSET		(0x00C8)
+#define DDR_PCTL_TOGG_CNTR_100NS_OFFSET	(0x00CC)
+#define DDR_PCTL_TREFI_OFFSET		(0x00D0)
+#define DDR_PCTL_TMRD_OFFSET		(0x00D4)
+#define DDR_PCTL_TRFC_OFFSET		(0x00D8)
+#define DDR_PCTL_TRP_OFFSET		(0x00DC)
+#define DDR_PCTL_TRTW_OFFSET		(0x00E0)
+#define DDR_PCTL_TAL_OFFSET		(0x00E4)
+#define DDR_PCTL_TCL_OFFSET		(0x00E8)
+#define DDR_PCTL_TCWL_OFFSET		(0x00EC)
+#define DDR_PCTL_TRAS_OFFSET		(0x00F0)
+#define DDR_PCTL_TRC_OFFSET		(0x00F4)
+#define DDR_PCTL_TRCD_OFFSET		(0x00F8)
+#define DDR_PCTL_TRRD_OFFSET		(0x00FC)
+#define DDR_PCTL_TRTP_OFFSET		(0x0100)
+#define DDR_PCTL_TWR_OFFSET		(0x0104)
+#define DDR_PCTL_TWTR_OFFSET		(0x0108)
+#define DDR_PCTL_TEXSR_OFFSET		(0x010C)
+#define DDR_PCTL_TXP_OFFSET		(0x0110)
+#define DDR_PCTL_TXPDLL_OFFSET		(0x0114)
+#define DDR_PCTL_TZQCS_OFFSET		(0x0118)
+#define DDR_PCTL_TDQS_OFFSET		(0x0120)
+#define DDR_PCTL_TCKE_OFFSET		(0x012C)
+#define DDR_PCTL_TMOD_OFFSET		(0x0130)
+#define DDR_PCTL_TZQCL_OFFSET		(0x0138)
+#define DDR_PCTL_TCKESR_OFFSET		(0x0140)
+#define DDR_PCTL_TREFI_MEM_DDR3_OFFSET	(0x0148)
+#define DDR_PCTL_DTUWACTL_OFFSET	(0x0200)
+#define DDR_PCTL_DTURACTL_OFFSET	(0x0204)
+#define DDR_PCTL_DTUCFG_OFFSET		(0x0208)
+#define DDR_PCTL_DTUECTL_OFFSET		(0x020C)
+#define DDR_PCTL_DTUWD0_OFFSET		(0x0210)
+#define DDR_PCTL_DTUWD1_OFFSET		(0x0214)
+#define DDR_PCTL_DTUWD2_OFFSET		(0x0218)
+#define DDR_PCTL_DTUWD3_OFFSET		(0x021C)
+#define DDR_PCTL_DFIODTCFG_OFFSET	(0x0244)
+#define DDR_PCTL_DFIODTCFG1_OFFSET	(0x0248)
+#define DDR_PCTL_DFITPHYWRDATA_OFFSET	(0x0250)
+#define DDR_PCTL_DFIWRLAT_OFFSET	(0x0254)
+#define DDR_PCTL_DFITRDDATAEN_OFFSET	(0x0260)
+#define DDR_PCTL_DFITPHYRDLAT_OFFSET	(0x0264)
+#define DDR_PCTL_DFIUPDCFG_OFFSET	(0x0290)
+#define DDR_PCTL_DFISTAT0_OFFSET	(0x02C0)
+#define DDR_PCTL_DFISTCFG0_OFFSET	(0x02C4)
+#define DDR_PCTL_DFISTCFG1_OFFSET	(0x02C8)
+#define DDR_PCTL_DFISTCFG2_OFFSET	(0x02D8)
+#define DDR_PCTL_DFILPCFG0_OFFSET	(0x02F0)
+#define DDR_PCTL_PCFG0_OFFSET		(0x0400)
+#define DDR_PCTL_CCFG_OFFSET		(0x0480)
+#define DDR_PCTL_DCFG_OFFSET		(0x0484)
+#define DDR_PCTL_CCFG1_OFFSET		(0x048C)
+
+#define DDR_PHY				0xB8180800
+#define DDRPHY_PIR_OFFSET		(0x0004)
+#define DDRPHY_PGCR_OFFSET		(0x0008)
+#define DDRPHY_PGSR_OFFSET		(0x000C)
+#define DDRPHY_DLLGCR_OFFSET		(0x0010)
+#define DDRPHY_PTR0_OFFSET		(0x0018)
+#define DDRPHY_PTR1_OFFSET		(0x001C)
+#define DDRPHY_DSGCR_OFFSET		(0x002C)
+#define DDRPHY_DCR_OFFSET		(0x0030)
+#define DDRPHY_DTPR0_OFFSET		(0x0034)
+#define DDRPHY_DTPR1_OFFSET		(0x0038)
+#define DDRPHY_DTPR2_OFFSET		(0x003C)
+#define DDRPHY_MR_OFFSET		(0x0040)
+#define DDRPHY_EMR_OFFSET		(0x0044)
+#define DDRPHY_EMR2_OFFSET		(0x0048)
+#define DDRPHY_EMR3_OFFSET		(0x004C)
+#define DDRPHY_DTAR_OFFSET		(0x0054)
+#define DDRPHY_BISTRR_OFFSET		(0x0100)
+#define DDRPHY_BISTWCR_OFFSET		(0x010C)
+#define DDRPHY_BISTAR0_OFFSET		(0x0114)
+#define DDRPHY_BISTAR1_OFFSET		(0x0118)
+#define DDRPHY_BISTAR2_OFFSET		(0x011C)
+#define DDRPHY_BISTUDPR_OFFSET		(0x0120)
+#define DDRPHY_BISTGSR_OFFSET		(0x0124)
+
+#define DDR_TIMEOUT_VALUE_US		100000
+
+static int wait_for_completion(u32 reg, u32 exp_val)
+{
+	struct stopwatch sw;
+
+	stopwatch_init_usecs_expire(&sw, DDR_TIMEOUT_VALUE_US);
+	while (read32(reg) != exp_val) {
+		if (stopwatch_expired(&sw))
+			return DDR_TIMEOUT;
+	}
+	return 0;
+}
+
+#endif
diff --git a/src/soc/atheros/ar7240/include/soc/gpio.h b/src/soc/atheros/ar7240/include/soc/gpio.h
new file mode 100644
index 0000000..ec31e43
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/gpio.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __SOC_ATHEROS_AR7240_GPIO_H__
+#define __SOC_ATHEROS_AR7240_GPIO_H__
+
+typedef unsigned gpio_t;
+
+#endif // __SOC_ATHEROS_AR7240_GPIO_H__
diff --git a/src/soc/atheros/ar7240/include/soc/memlayout.ld b/src/soc/atheros/ar7240/include/soc/memlayout.ld
new file mode 100644
index 0000000..00c17f4
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/memlayout.ld
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <vendorcode/google/chromeos/memlayout.h>
+
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * All of DRAM (other than the DMA coherent area) is accessed through
+	 * the identity mapping.
+	 */
+	DRAM_START(0x00000000)
+	/* DMA coherent area: accessed via KSEG1. */
+	DMA_COHERENT(0x00100000, 1M)
+	POSTRAM_CBFS_CACHE(0x00200000, 192K)
+	PRERAM_CBFS_CACHE(0x00230000, 56K)
+	RAMSTAGE(0x0023e000, 128K)
+	STACK(0x00ffd000, 8K)
+
+	/*
+	 * GRAM becomes the SRAM.  Accessed through KSEG0 in the bootblock
+	 * and then through the identity mapping in ROM stage.
+	 */
+/*	SRAM_START(0x1a000000)
+	ROMSTAGE(0x1a005000, 40K)
+	PRERAM_CBFS_CACHE(0x1a012000, 56K)
+	SRAM_END(0x1a020000) */
+
+	/* Bootblock executes out of KSEG0 and sets up the identity mapping.
+	 * This is identical to SRAM above, and thus also limited 64K and
+	 * needs to avoid conflicts with items set up above.
+	 */
+	BOOTBLOCK(0xbfc00000, 32K)
+	ROMSTAGE(0xbfc08000, 32K)
+
+	/*
+	 * Let's use SRAM for stack and CBMEM console.  Always accessed
+	 * through KSEG0.
+	 */
+/*	PRERAM_CBMEM_CONSOLE(0x9b002000, 8K) */
+}
diff --git a/src/soc/atheros/ar7240/include/soc/spi.h b/src/soc/atheros/ar7240/include/soc/spi.h
new file mode 100644
index 0000000..fb24f2b
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/spi.h
@@ -0,0 +1,358 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __SOC_ATHEROS_AR7240_SPI_H__
+#define __SOC_ATHEROS_AR7240_SPI_H__
+
+#include <arch/io.h>
+#include <arch/types.h>
+
+#define spi_read_reg_field(regval, field)		\
+(							\
+	((field##_MASK) == 0xFFFFFFFF) ?		\
+	(regval) :					\
+	(((regval) & (field##_MASK)) >> (field##_SHIFT))\
+)
+
+#define spi_write_reg_field(regval, field, val)		\
+(							\
+	((field##_MASK) == 0xFFFFFFFF) ?		\
+	(val) :						\
+	(((regval) & ~(field##_MASK)) |			\
+	(((val) << (field##_SHIFT)) & (field##_MASK)))	\
+)
+
+/*
+ * Parameter register
+ * Each of these corresponds to a single port (ie CS line) in the interface
+ * Fields	Name		Description
+ * ======	====		===========
+ * b31:24	CLK_RATE	Bit Clock rate = (24.576 * value / 512) MHz
+ * b23:16	CS_SETUP	Chip Select setup = (40 * value) ns
+ * b15:8	CS_HOLD		Chip Select hold = (40 * value) ns
+ * b7:0		CS_DELAY	Chip Select delay = (40 * value) ns
+ */
+
+#define SPIM_CLK_DIVIDE_MASK     (0xFF000000)
+#define SPIM_CS_SETUP_MASK       (0x00FF0000)
+#define SPIM_CS_HOLD_MASK        (0x0000FF00)
+#define SPIM_CS_DELAY_MASK       (0x000000FF)
+#define SPIM_CS_PARAM_MASK      (SPIM_CS_SETUP_MASK \
+				| SPIM_CS_HOLD_MASK \
+				| SPIM_CS_DELAY_MASK)
+
+#define SPIM_CLK_DIVIDE_SHIFT            (24)
+#define SPIM_CS_SETUP_SHIFT              (16)
+#define SPIM_CS_HOLD_SHIFT                (8)
+#define SPIM_CS_DELAY_SHIFT               (0)
+#define SPIM_CS_PARAM_SHIFT               (0)
+
+/* Control register */
+
+#define SPFI_DRIBBLE_COUNT_MASK  (0x000e0000)
+#define SPFI_MEMORY_IF_MASK      (0x00008000)
+#define SPIM_BYTE_DELAY_MASK     (0x00004000)
+#define SPIM_CS_DEASSERT_MASK    (0x00002000)
+#define SPIM_CONTINUE_MASK       (0x00001000)
+#define SPIM_SOFT_RESET_MASK     (0x00000800)
+#define SPIM_SEND_DMA_MASK       (0x00000400)
+#define SPIM_GET_DMA_MASK        (0x00000200)
+#define SPIM_EDGE_TX_RX_MASK     (0x00000100)
+#define SPFI_TRNSFR_MODE_MASK    (0x000000e0)
+#define SPFI_TRNSFR_MODE_DQ_MASK (0x0000001c)
+#define SPFI_TX_RX_MASK          (0x00000002)
+#define SPFI_EN_MASK             (0x00000001)
+
+#define SPFI_DRIBBLE_COUNT_SHIFT         (17)
+#define SPFI_MEMORY_IF_SHIFT             (15)
+#define SPIM_BYTE_DELAY_SHIFT            (14)
+#define SPIM_CS_DEASSERT_SHIFT           (13)
+#define SPIM_CONTINUE_SHIFT              (12)
+#define SPIM_SOFT_RESET_SHIFT            (11)
+#define SPIM_SEND_DMA_SHIFT              (10)
+#define   SPIM_GET_DMA_SHIFT              (9)
+#define SPIM_EDGE_TX_RX_SHIFT             (8)
+#define SPFI_TRNSFR_MODE_SHIFT            (5)
+#define SPFI_TRNSFR_MODE_DQ_SHIFT         (2)
+#define SPFI_TX_RX_SHIFT                  (1)
+#define SPFI_EN_SHIFT                     (0)
+
+/* Transaction register */
+
+#define SPFI_TSIZE_MASK           (0xffff0000)
+#define SPFI_CMD_LENGTH_MASK      (0x0000e000)
+#define SPFI_ADDR_LENGTH_MASK     (0x00001c00)
+#define SPFI_DUMMY_LENGTH_MASK    (0x000003e0)
+#define SPFI_PI_LENGTH_MASK       (0x0000001c)
+
+#define SPFI_TSIZE_SHIFT                  (16)
+#define SPFI_CMD_LENGTH_SHIFT             (13)
+#define SPFI_ADDR_LENGTH_SHIFT            (10)
+#define SPFI_DUMMY_LENGTH_SHIFT            (5)
+#define SPFI_PI_LENGTH_SHIFT               (2)
+
+/* Port state register */
+
+#define SPFI_PORT_SELECT_MASK    (0x00700000)
+/* WARNING the following bits are reversed */
+#define SPFI_CLOCK0_IDLE_MASK    (0x000f8000)
+#define SPFI_CLOCK0_PHASE_MASK   (0x00007c00)
+#define SPFI_CS0_IDLE_MASK       (0x000003e0)
+#define SPFI_DATA0_IDLE_MASK     (0x0000001f)
+
+#define SPIM_CLOCK0_IDLE_MASK    (0x000f8000)
+#define SPIM_CLOCK0_PHASE_MASK   (0x00007c00)
+#define SPIM_CS0_IDLE_MASK       (0x000003e0)
+#define SPIM_DATA0_IDLE_MASK     (0x0000001f)
+
+#define SPIM_PORT0_MASK          (0x00084210)
+
+#define SPFI_PORT_SELECT_SHIFT           (20)
+/* WARNING the following bits are reversed, bit 0 is highest */
+#define SPFI_CLOCK0_IDLE_SHIFT           (19)
+#define SPFI_CLOCK0_PHASE_SHIFT          (14)
+#define SPFI_CS0_IDLE_SHIFT               (9)
+#define SPFI_DATA0_IDLE_SHIFT             (4)
+
+#define SPIM_CLOCK0_IDLE_SHIFT           (19)
+#define SPIM_CLOCK0_PHASE_SHIFT          (14)
+#define SPIM_CS0_IDLE_SHIFT               (9)
+#define SPIM_DATA0_IDLE_SHIFT             (4)
+
+
+/*
+ * Interrupt registers
+ * SPFI_GDOF_MASK means Rx buffer full, not an overflow, because clock stalls
+ * SPFI_SDUF_MASK means Tx buffer empty, not an underflow, because clock stalls
+ */
+#define SPFI_IACCESS_MASK        (0x00001000)
+#define SPFI_GDEX8BIT_MASK       (0x00000800)
+#define SPFI_ALLDONE_MASK        (0x00000200)
+#define SPFI_GDFUL_MASK          (0x00000100)
+#define SPFI_GDHF_MASK           (0x00000080)
+#define SPFI_GDEX32BIT_MASK      (0x00000040)
+#define SPFI_GDTRIG_MASK         (0x00000020)
+#define SPFI_SDFUL_MASK          (0x00000008)
+#define SPFI_SDHF_MASK           (0x00000004)
+#define SPFI_SDE_MASK            (0x00000002)
+#define SPFI_SDTRIG_MASK         (0x00000001)
+
+#define SPFI_IACCESS_SHIFT               (12)
+#define SPFI_GDEX8BIT_SHIFT              (11)
+#define SPFI_ALLDONE_SHIFT                (9)
+#define SPFI_GDFUL_SHIFT                  (8)
+#define SPFI_GDHF_SHIFT                   (7)
+#define SPFI_GDEX32BIT_SHIFT              (6)
+#define SPFI_GDTRIG_SHIFT                 (5)
+#define SPFI_SDFUL_SHIFT                  (3)
+#define SPFI_SDHF_SHIFT                   (2)
+#define SPFI_SDE_SHIFT                    (1)
+#define SPFI_SDTRIG_SHIFT                 (0)
+
+
+/* SPFI register block */
+
+#define SPFI_PORT_0_PARAM_REG_OFFSET             (0x00)
+#define SPFI_PORT_1_PARAM_REG_OFFSET             (0x04)
+#define SPFI_PORT_2_PARAM_REG_OFFSET             (0x08)
+#define SPFI_PORT_3_PARAM_REG_OFFSET             (0x0C)
+#define SPFI_PORT_4_PARAM_REG_OFFSET             (0x10)
+#define SPFI_CONTROL_REG_OFFSET                  (0x14)
+#define SPFI_TRANSACTION_REG_OFFSET              (0x18)
+#define SPFI_PORT_STATE_REG_OFFSET               (0x1C)
+
+#define SPFI_SEND_LONG_REG_OFFSET                (0x20)
+#define SPFI_SEND_BYTE_REG_OFFSET                (0x24)
+#define SPFI_GET_LONG_REG_OFFSET                 (0x28)
+#define SPFI_GET_BYTE_REG_OFFSET                 (0x2C)
+
+#define SPFI_INT_STATUS_REG_OFFSET               (0x30)
+#define SPFI_INT_ENABLE_REG_OFFSET               (0x34)
+#define SPFI_INT_CLEAR_REG_OFFSET                (0x38)
+
+#define SPFI_IMMEDIATE_STATUS_REG_OFFSET         (0x3c)
+
+#define SPFI_FLASH_BASE_ADDRESS_REG_OFFSET       (0x48)
+#define SPFI_FLASH_STATUS_REG_OFFSET             (0x4C)
+
+#define IMG_FALSE				0
+#define IMG_TRUE				1
+
+/* Number of SPIM interfaces*/
+#define SPIM_NUM_BLOCKS				2
+/* Number of chip select lines supported by the SPI master port. */
+#define SPIM_NUM_PORTS_PER_BLOCK		(SPIM_DUMMY_CS)
+/* Maximum transfer size (in bytes) for the SPI master port. */
+#define SPIM_MAX_TRANSFER_BYTES			(0xFFFF)
+/* Maximum size of a flash command: command bytes+address_bytes. */
+#define SPIM_MAX_FLASH_COMMAND_BYTES		(0x8)
+/* Write operation to fifo done in blocks of 16 words (64 bytes) */
+#define SPIM_MAX_BLOCK_BYTES			(0x40)
+/* Number of tries until timeout error is returned*/
+#define SPI_TIMEOUT_VALUE_US			500000
+
+/* SPIM initialisation function return value.*/
+enum spim_return {
+	/* Initialisation parameters are valid. */
+	SPIM_OK = 0,
+	/* Mode parameter is invalid. */
+	SPIM_INVALID_SPI_MODE,
+	/* Chip select idle level is invalid. */
+	SPIM_INVALID_CS_IDLE_LEVEL,
+	/* Data idle level is invalid. */
+	SPIM_INVALID_DATA_IDLE_LEVEL,
+	/* Chip select line parameter is invalid. */
+	SPIM_INVALID_CS_LINE,
+	/* Transfer size parameter is invalid. */
+	SPIM_INVALID_SIZE,
+	/* Read/write parameter is invalid. */
+	SPIM_INVALID_READ_WRITE,
+	/* Continue parameter is invalid. */
+	SPIM_INVALID_CONTINUE,
+	/* Invalid block index */
+	SPIM_INVALID_BLOCK_INDEX,
+	/* Extended error values */
+	/* Invalid bit rate */
+	SPIM_INVALID_BIT_RATE,
+	/* Invalid CS hold value */
+	SPIM_INVALID_CS_HOLD_VALUE,
+	/* API function called before API is initialised */
+	SPIM_API_NOT_INITIALISED,
+	/* SPI driver initialisation failed */
+	SPIM_DRIVER_INIT_ERROR,
+	/* Invalid transfer description */
+	SPIM_INVALID_TRANSFER_DESC,
+	/* Timeout */
+	SPIM_TIMEOUT
+
+};
+
+/* This type defines the SPI Mode.*/
+enum spim_mode {
+	/* Mode 0 (clock idle low, data valid on first clock transition). */
+	SPIM_MODE_0 = 0,
+	/* Mode 1 (clock idle low, data valid on second clock transition). */
+	SPIM_MODE_1,
+	/* Mode 2 (clock idle high, data valid on first clock transition). */
+	SPIM_MODE_2,
+	/* Mode 3 (clock idle high, data valid on second clock transition). */
+	SPIM_MODE_3
+
+};
+
+/* This type defines the SPIM device numbers (chip select lines). */
+enum spim_device {
+	/* Device 0 (CS0). */
+	SPIM_DEVICE0 = 0,
+	/* Device 1 (CS1). */
+	SPIM_DEVICE1,
+	/* Device 2 (CS2). */
+	SPIM_DEVICE2,
+	/* Device 3 (CS3). */
+	SPIM_DEVICE3,
+	/* Device 4 (CS4). */
+	SPIM_DEVICE4,
+	/* Dummy chip select. */
+	SPIM_DUMMY_CS
+
+};
+
+/* This structure defines communication parameters for a slave device */
+struct spim_device_parameters {
+	/* Bit rate value.*/
+	unsigned char bitrate;
+	/*
+	 * Chip select set up time.
+	 * Time taken between chip select going active and activity occurring
+	 * on the clock, calculated by dividing the desired set up time in ns
+	 * by the Input clock period. (setup time / Input clock freq)
+	 */
+	unsigned char cs_setup;
+	/*
+	 * Chip select hold time.
+	 * Time after the last clock pulse before chip select goes inactive,
+	 * calculated by dividing the desired hold time in ns by the
+	 * Input clock period (hold time / Input clock freq).
+	 */
+	unsigned char cs_hold;
+	/*
+	 * Chip select delay time (CS minimum inactive time).
+	 * Minimum time after chip select goes inactive before chip select
+	 * can go active again, calculated by dividing the desired delay time
+	 * in ns by the Input clock period (delay time / Input clock freq).
+	 */
+	unsigned char cs_delay;
+	/* SPI Mode. */
+	enum spim_mode spi_mode;
+	/* Chip select idle level (0=low, 1=high, Others=invalid). */
+	unsigned int cs_idle_level;
+	/* Data idle level (0=low, 1=high, Others=invalid). */
+	unsigned int data_idle_level;
+
+};
+
+/* Command transfer mode */
+enum command_mode {
+	/* Command, address, dummy and PI cycles are transferred on sio0 */
+	SPIM_CMD_MODE_0 = 0,
+	/*
+	 * Command and Address are transferred on sio0 port only but dummy
+	 * cycles and PI is transferred on all the interface ports.
+	 */
+	SPIM_CMD_MODE_1,
+	/*
+	 * Command is transferred on sio0 port only but address, dummy
+	 * and PI is transferred on all the interface portS
+	 */
+	SPIM_CMD_MODE_2,
+	/*
+	 * Command, address, dummy and PI bytes are transferred on all
+	 * the interfaces
+	 */
+	SPIM_CMD_MODE_3
+};
+
+/* Data transfer mode */
+enum transfer_mode {
+	/* Transfer data in single mode */
+	SPIM_DMODE_SINGLE = 0,
+	/* Transfer data in dual mode */
+	SPIM_DMODE_DUAL,
+	/* Transfer data in quad mode */
+	SPIM_DMODE_QUAD
+};
+
+/* This structure contains parameters that describe an SPIM operation. */
+struct spim_buffer {
+	/* The buffer to read from or write to. */
+	unsigned char *buffer;
+
+	/* Number of bytes to read/write. Valid range is 0 to 65536 bytes. */
+	unsigned int size;
+
+	/* Read/write select. TRUE for read, FALSE for write, Others-invalid.*/
+	int isread;
+
+	/*
+	 * ByteDelay select.
+	 * Selects whether or not a delay is inserted between bytes.
+	 * 0 - Minimum inter-byte delay
+	 * 1 - Inter-byte delay of (cs_hold/master_clk half period)*master_clk.
+	 */
+	int inter_byte_delay;
+};
+
+#endif /* __SOC_ATHEROS_AR7240_SPI_H__ */
diff --git a/src/soc/atheros/ar7240/monotonic_timer.c b/src/soc/atheros/ar7240/monotonic_timer.c
new file mode 100644
index 0000000..eba7868
--- /dev/null
+++ b/src/soc/atheros/ar7240/monotonic_timer.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cpu.h>
+#include <soc/clocks.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <timer.h>
+#include <timestamp.h>
+
+#include <soc/ar71xx_regs.h>
+
+int get_count_mhz_freq(void)
+{
+	uint32_t cpu_config;
+
+	uint32_t div_multiplier;
+	uint32_t ref_div;
+	
+	cpu_config = read32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CONFIG);
+
+	if (cpu_config & AR724X_CPU_PLL_BYPASS) {
+		return ar71xx_get_ref_clock_mhz();
+	}
+
+	div_multiplier = cpu_config & AR724X_PLL_FB_MASK;
+	ref_div = (cpu_config >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK;
+
+	return ((div_multiplier / ref_div) * ar71xx_get_ref_clock_mhz()) / 2;
+}
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+	mono_time_set_usecs(mt, read_c0_count() / get_count_mhz_freq());
+}
diff --git a/src/soc/atheros/ar7240/romstage.c b/src/soc/atheros/ar7240/romstage.c
new file mode 100644
index 0000000..f2eb78a
--- /dev/null
+++ b/src/soc/atheros/ar7240/romstage.c
@@ -0,0 +1,10 @@
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <halt.h>
+#include <program_loading.h>
+#include <soc/ddr_init.h>
+
+void main(void)
+{
+}
diff --git a/src/soc/atheros/ar7240/spi.c b/src/soc/atheros/ar7240/spi.c
new file mode 100644
index 0000000..cb3e178
--- /dev/null
+++ b/src/soc/atheros/ar7240/spi.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ar71xx_regs.h>
+#include <soc/spi.h>
+#include <spi_flash.h>
+#include <spi-generic.h>
+#include <stdlib.h>
+#include <string.h>
+#include <timer.h>
+
+
+/* based on u-boot sources (GPL) */
+
+#define AR7240_SPI_FS           0x1f000000
+#define AR7240_SPI_CLOCK        0x1f000004
+#define AR7240_SPI_WRITE        0x1f000008
+#define AR7240_SPI_READ         0x1f000000
+#define AR7240_SPI_RD_STATUS    0x1f00000c
+
+#define AR7240_SPI_CS_DIS       0x70000
+#define AR7240_SPI_CE_LOW       0x60000
+#define AR7240_SPI_CE_HIGH      0x60100
+
+#define AR7240_SPI_CMD_WREN         0x06
+#define AR7240_SPI_CMD_RD_STATUS    0x05
+#define AR7240_SPI_CMD_FAST_READ    0x0b
+#define AR7240_SPI_CMD_PAGE_PROG    0x02
+#define AR7240_SPI_CMD_SECTOR_ERASE 0xd8
+
+#define AR7240_SPI_SECTOR_SIZE      (1024*64)
+#define AR7240_SPI_PAGE_SIZE        256
+
+#define ar7240_be_msb(_val, _i) (((_val) & (1 << (7 - _i))) >> (7 - _i))
+
+#define ar7240_spi_bit_banger(_byte)  do {        \
+    int i;                                      \
+    for(i = 0; i < 8; i++) {                    \
+        ar7240_reg_wr_nf(AR7240_SPI_WRITE,      \
+                        AR7240_SPI_CE_LOW | ar7240_be_msb(_byte, i));  \
+        ar7240_reg_wr_nf(AR7240_SPI_WRITE,      \
+                        AR7240_SPI_CE_HIGH | ar7240_be_msb(_byte, i)); \
+    }       \
+}while(0);
+
+#define ar7240_spi_go() do {        \
+    ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CE_LOW); \
+    ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS); \
+}while(0);
+
+#define ar7240_spi_send_addr(_addr) do {                    \
+    ar7240_spi_bit_banger(((addr & 0xff0000) >> 16));                 \
+    ar7240_spi_bit_banger(((addr & 0x00ff00) >> 8));                 \
+    ar7240_spi_bit_banger(addr & 0x0000ff);                 \
+}while(0);
+
+#define ar7240_spi_delay_8()    ar7240_spi_bit_banger(0)
+#define ar7240_spi_done()       ar7240_reg_wr_nf(AR7240_SPI_FS, 0)
+
+#define ATHEROS_MAX_SPI_SLAVE 3
+
+static struct spi_slave slaves[ATHEROS_MAX_SPI_SLAVE];
+static int spi_initialized;
+
+static inline void ath79_spi_wr(unsigned long addr, uint32_t val)
+{
+	write32(AR71XX_SPI_BASE + addr, val);
+}
+
+static inline uint32_t ath79_spi_rr(unsigned long addr)
+{
+	return read32(AR71XX_SPI_BASE + addr);
+}
+
+void spi_init(void)
+{
+	spi_initialized = 0;
+	memset(slaves, 0, sizeof(slaves));
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
+{
+	if (bus != 0 || cs >= ATHEROS_MAX_SPI_SLAVE) {
+		printk(BIOS_ERR, "%s: Invalid spi settings bus 0x%x cs 0x%x\n",
+				__func__, bus, cs);
+		return NULL;
+	}
+
+	slaves[cs].bus = bus;
+	slaves[cs].cs = cs;
+	slaves[cs].rw = SPI_READ_FLAG & SPI_WRITE_FLAG;
+
+	return &slaves[cs];
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	
+	if (!spi_initialized) {
+		spi_initialized = 1;
+
+		/* enable gpio mode */
+		ath79_spi_wr(AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+
+		/* disable remap (0x40) + set up clock divider 0x3
+		* freq = AHB_CLK / ((CLOCK_DIVIDE +1) * 2)
+		*/
+		ath79_spi_wr(AR71XX_SPI_REG_CTRL, 0x43);
+	}
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout,
+		void *din, unsigned int bytesin)
+{
+	int csbit = slave->cs + 16;
+	int transfer_max = max(bytesin, bytesout);
+	int readed = 0;
+	uint8_t data = 0;
+	
+	ath79_spi_wr(AR71XX_SPI_REG_IOC, csbit);
+
+	for(int i=0; i<transfer_max; i++) {
+		if(bytesout <= i)
+			data = 0; /* dummy write to read data */
+		else
+			data = *(((uint8_t *)dout) + i);
+
+		/* write data 8 bit data */
+		for(int j=0; j<8; j++) {
+			ath79_spi_wr(AR71XX_SPI_REG_IOC,
+					csbit | ar7240_be_msb(data, j));
+			ath79_spi_wr(AR71XX_SPI_REG_IOC,
+					csbit | AR71XX_SPI_IOC_CLK | ar7240_be_msb(data, j));
+		}
+
+		/* read data in from data register */
+		if(i % 4 == 0 && i > 0) {
+			if(bytesin == readed) {
+				/* do nothing */
+			} else if(bytesin-readed >= 4) {
+				*(((uint32_t *)din) + (readed % 4)) = ath79_spi_rr(AR71XX_SPI_REG_RDS);
+				readed += 4;
+			} else {
+				/* partial read until full. max 3 bytes are read */
+				for (int j=0; bytesin != readed; j++) {
+					*(((uint32_t *)din) + readed) = (readed >> (24 - j*8));
+					readed++;
+				}
+			}
+		}
+	}
+
+	/* check if we have to read_data once more */
+	if (bytesin != readed) {
+		/* partial read until full. max 3 bytes are read */
+		for (int j=0; bytesin != readed; j++) {
+			*(((uint32_t *)din) + readed) = (readed >> (24 - j*8));
+			readed++;
+		}
+	}
+
+
+	return 0;
+}
+
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+	return buf_len;
+}
+
diff --git a/src/soc/atheros/ar7240/uart.c b/src/soc/atheros/ar7240/uart.c
new file mode 100644
index 0000000..3f99cfb
--- /dev/null
+++ b/src/soc/atheros/ar7240/uart.c
@@ -0,0 +1,162 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <console/uart.h>
+#include <device/device.h>
+#include <delay.h>
+#include <drivers/uart/uart8250reg.h>
+
+/* Should support 8250, 16450, 16550, 16550A type UARTs */
+
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ */
+#define SINGLE_CHAR_TIMEOUT	(50 * 1000)
+#define FIFO_TIMEOUT		(16 * SINGLE_CHAR_TIMEOUT)
+#define UART_SHIFT		2
+
+#define GEN_ACCESSOR(name, idx)						\
+static inline uint8_t read_##name(unsigned base_port)			\
+{									\
+	return read8(base_port + (idx << UART_SHIFT));			\
+}									\
+									\
+static inline void write_##name(unsigned base_port, uint8_t val)	\
+{									\
+	write8(base_port + (idx << UART_SHIFT), val);			\
+}
+
+GEN_ACCESSOR(rbr, UART8250_RBR)
+GEN_ACCESSOR(tbr, UART8250_TBR)
+GEN_ACCESSOR(ier, UART8250_IER)
+GEN_ACCESSOR(fcr, UART8250_FCR)
+GEN_ACCESSOR(lcr, UART8250_LCR)
+GEN_ACCESSOR(mcr, UART8250_MCR)
+GEN_ACCESSOR(lsr, UART8250_LSR)
+GEN_ACCESSOR(dll, UART8250_DLL)
+GEN_ACCESSOR(dlm, UART8250_DLM)
+
+static int uart8250_mem_can_tx_byte(unsigned base_port)
+{
+	return read_lsr(base_port) & UART8250_LSR_THRE;
+}
+
+static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
+{
+	unsigned long int i = SINGLE_CHAR_TIMEOUT;
+	while (i-- && !uart8250_mem_can_tx_byte(base_port))
+		udelay(1);
+	write_tbr(base_port, data);
+}
+
+static void uart8250_mem_tx_flush(unsigned base_port)
+{
+	unsigned long int i = FIFO_TIMEOUT;
+	while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT))
+		udelay(1);
+}
+
+static int uart8250_mem_can_rx_byte(unsigned base_port)
+{
+	return read_lsr(base_port) & UART8250_LSR_DR;
+}
+
+static unsigned char uart8250_mem_rx_byte(unsigned base_port)
+{
+	unsigned long int i = SINGLE_CHAR_TIMEOUT;
+	while (i-- && !uart8250_mem_can_rx_byte(base_port))
+		udelay(1);
+	if (i)
+		return read_rbr(base_port);
+	else
+		return 0x0;
+}
+
+static void uart8250_mem_init(unsigned base_port, unsigned divisor)
+{
+	/* Disable interrupts */
+	write_ier(base_port, 0x0);
+	/* Enable FIFOs */
+	write_fcr(base_port, UART8250_FCR_FIFO_EN);
+
+	/* Assert DTR and RTS so the other end is happy */
+	write_mcr(base_port, UART8250_MCR_DTR | UART8250_MCR_RTS);
+
+	/* DLAB on */
+	write_lcr(base_port, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS);
+
+	write_dll(base_port, divisor & 0xFF);
+	write_dlm(base_port, (divisor >> 8) & 0xFF);
+
+	/* Set to 3 for 8N1 */
+	write_lcr(base_port, CONFIG_TTYS0_LCS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+	/* TODO: for now this is hardcoded */
+	/* uart uses AHB as base clock */
+	return 195 * 1000 * 1000;
+}
+
+void uart_init(int idx)
+{
+	u32 base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+	if (!base)
+		return;
+
+	unsigned int div;
+	div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,
+				    uart_platform_refclk(), 16);
+	uart8250_mem_init(base, div);
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+	uart8250_mem_tx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS, data);
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+	return uart8250_mem_rx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS);
+}
+
+void uart_tx_flush(int idx)
+{
+	uart8250_mem_tx_flush(CONFIG_CONSOLE_SERIAL_UART_ADDRESS);
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+	struct lb_serial serial;
+	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+	serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+	serial.baud = default_baudrate();
+	serial.regwidth = 1 << UART_SHIFT;
+	lb_add_serial(&serial, data);
+
+	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif
diff --git a/src/soc/atheros/common/include/soc/ar71xx_regs.h b/src/soc/atheros/common/include/soc/ar71xx_regs.h
new file mode 100644
index 0000000..3f0cfbe
--- /dev/null
+++ b/src/soc/atheros/common/include/soc/ar71xx_regs.h
@@ -0,0 +1,559 @@
+/*
+ *  Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan at atheros.com>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg at openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz at openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#define AR71XX_APB_BASE		0x18000000
+#define AR71XX_EHCI_BASE	0x1b000000
+#define AR71XX_EHCI_SIZE	0x1000
+#define AR71XX_OHCI_BASE	0x1c000000
+#define AR71XX_OHCI_SIZE	0x1000
+#define AR71XX_SPI_BASE		0x1f000000
+#define AR71XX_SPI_SIZE		0x01000000
+
+#define AR71XX_DDR_CTRL_BASE	(AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE	0x100
+#define AR71XX_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE	0x100
+#define AR71XX_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE	0x100
+#define AR71XX_GPIO_BASE	(AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE	0x100
+#define AR71XX_PLL_BASE		(AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE		0x100
+#define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE	0x100
+
+#define AR71XX_PCI_MEM_BASE	0x10000000
+#define AR71XX_PCI_MEM_SIZE	0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS	0x10000000
+#define AR71XX_PCI_WIN1_OFFS	0x11000000
+#define AR71XX_PCI_WIN2_OFFS	0x12000000
+#define AR71XX_PCI_WIN3_OFFS	0x13000000
+#define AR71XX_PCI_WIN4_OFFS	0x14000000
+#define AR71XX_PCI_WIN5_OFFS	0x15000000
+#define AR71XX_PCI_WIN6_OFFS	0x16000000
+#define AR71XX_PCI_WIN7_OFFS	0x07000000
+
+#define AR71XX_PCI_CFG_BASE	\
+	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE	0x100
+
+#define AR7240_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE	0x100
+#define AR7240_OHCI_BASE	0x1b000000
+#define AR7240_OHCI_SIZE	0x1000
+
+#define AR724X_PCI_MEM_BASE	0x10000000
+#define AR724X_PCI_MEM_SIZE	0x04000000
+
+#define AR724X_PCI_CFG_BASE	0x14000000
+#define AR724X_PCI_CFG_SIZE	0x1000
+#define AR724X_PCI_CRP_BASE	(AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE	0x1000
+#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE	0x100
+
+#define AR724X_EHCI_BASE	0x1b000000
+#define AR724X_EHCI_SIZE	0x1000
+
+#define AR913X_EHCI_BASE	0x1b000000
+#define AR913X_EHCI_SIZE	0x1000
+#define AR913X_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE	0x30000
+
+#define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE	0x14
+#define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE	0x20000
+#define AR933X_EHCI_BASE	0x1b000000
+#define AR933X_EHCI_SIZE	0x1000
+
+#define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE	0x20000
+#define AR934X_EHCI_BASE	0x1b000000
+#define AR934X_EHCI_SIZE	0x200
+#define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE	0x1000
+
+#define QCA955X_PCI_MEM_BASE0	0x10000000
+#define QCA955X_PCI_MEM_BASE1	0x12000000
+#define QCA955X_PCI_MEM_SIZE	0x02000000
+#define QCA955X_PCI_CFG_BASE0	0x14000000
+#define QCA955X_PCI_CFG_BASE1	0x16000000
+#define QCA955X_PCI_CFG_SIZE	0x1000
+#define QCA955X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE	0x1000
+#define QCA955X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE	0x100
+
+#define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE	0x20000
+#define QCA955X_EHCI0_BASE	0x1b000000
+#define QCA955X_EHCI1_BASE	0x1b400000
+#define QCA955X_EHCI_SIZE	0x1000
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_PCI_WIN0		0x7c
+#define AR71XX_DDR_REG_PCI_WIN1		0x80
+#define AR71XX_DDR_REG_PCI_WIN2		0x84
+#define AR71XX_DDR_REG_PCI_WIN3		0x88
+#define AR71XX_DDR_REG_PCI_WIN4		0x8c
+#define AR71XX_DDR_REG_PCI_WIN5		0x90
+#define AR71XX_DDR_REG_PCI_WIN6		0x94
+#define AR71XX_DDR_REG_PCI_WIN7		0x98
+#define AR71XX_DDR_REG_FLUSH_GE0	0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1	0xa0
+#define AR71XX_DDR_REG_FLUSH_USB	0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI	0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0	0x7c
+#define AR724X_DDR_REG_FLUSH_GE1	0x80
+#define AR724X_DDR_REG_FLUSH_USB	0x84
+#define AR724X_DDR_REG_FLUSH_PCIE	0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0	0x7c
+#define AR913X_DDR_REG_FLUSH_GE1	0x80
+#define AR913X_DDR_REG_FLUSH_USB	0x84
+#define AR913X_DDR_REG_FLUSH_WMAC	0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0	0x7c
+#define AR933X_DDR_REG_FLUSH_GE1	0x80
+#define AR933X_DDR_REG_FLUSH_USB	0x84
+#define AR933X_DDR_REG_FLUSH_WMAC	0x88
+
+#define AR934X_DDR_REG_FLUSH_GE0	0x9c
+#define AR934X_DDR_REG_FLUSH_GE1	0xa0
+#define AR934X_DDR_REG_FLUSH_USB	0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE	0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC	0xac
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG	0x00
+#define AR71XX_PLL_REG_SEC_CONFIG	0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK	0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK	0x14
+
+#define AR71XX_PLL_FB_SHIFT		3
+#define AR71XX_PLL_FB_MASK		0x1f
+#define AR71XX_CPU_DIV_SHIFT		16
+#define AR71XX_CPU_DIV_MASK		0x3
+#define AR71XX_DDR_DIV_SHIFT		18
+#define AR71XX_DDR_DIV_MASK		0x3
+#define AR71XX_AHB_DIV_SHIFT		20
+#define AR71XX_AHB_DIV_MASK		0x7
+
+#define AR724X_PLL_REG_CPU_CONFIG	0x00
+#define AR724X_PLL_REG_CPU_CLOCK_CTRL	0x08
+#define AR724X_PLL_REG_PCIE_CONFIG	0x18
+
+#define AR724X_PLL_FB_SHIFT		0
+#define AR724X_PLL_FB_MASK		0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT	10
+#define AR724X_PLL_REF_DIV_MASK		0xf
+#define AR724X_AHB_DIV_SHIFT		19
+#define AR724X_AHB_DIV_MASK		0x1
+#define AR724X_DDR_DIV_SHIFT		22
+#define AR724X_DDR_DIV_MASK		0x3
+#define AR724X_CPU_PLL_BYPASS		BIT(16)
+#define AR724X_CPU_PLL_UPDATING		BIT(17) /* is 0 when PLL update is pendig */
+#define AR724X_CPU_PLL_NOPWD		BIT(19)
+#define AR724X_CPU_PLL_RESET		BIT(25)
+
+#define AR724X_CPU_PLL_CTRL_CLOCK_SWITCH	0x1
+#define AR724X_CPU_PLL_CTRL_RESET_SWITCH	0x2
+
+#define AR913X_PLL_REG_CPU_CONFIG	0x00
+#define AR913X_PLL_REG_ETH_CONFIG	0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK	0x18
+
+#define AR913X_PLL_FB_SHIFT		0
+#define AR913X_PLL_FB_MASK		0x3ff
+#define AR913X_DDR_DIV_SHIFT		22
+#define AR913X_DDR_DIV_MASK		0x3
+#define AR913X_AHB_DIV_SHIFT		19
+#define AR913X_AHB_DIV_MASK		0x1
+
+#define AR933X_PLL_CPU_CONFIG_REG	0x00
+#define AR933X_PLL_CLOCK_CTRL_REG	0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT	10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT	16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT	23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS		BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT	5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK	0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT	10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK	0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG		0x00
+#define AR934X_PLL_DDR_CONFIG_REG		0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
+
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	BIT(2)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	BIT(3)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	BIT(4)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	BIT(20)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+
+#define QCA955X_PLL_CPU_CONFIG_REG		0x00
+#define QCA955X_PLL_DDR_CONFIG_REG		0x04
+#define QCA955X_PLL_CLK_CTRL_REG		0x08
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT	6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK	0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT	10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK	0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ	0x00
+#define AR71XX_USB_CTRL_REG_CONFIG	0x04
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER			0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD		0x04
+#define AR71XX_RESET_REG_WDOG_CTRL		0x08
+#define AR71XX_RESET_REG_WDOG			0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS	0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE	0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS		0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE		0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS	0x20
+#define AR71XX_RESET_REG_RESET_MODULE		0x24
+#define AR71XX_RESET_REG_PERFC_CTRL		0x2c
+#define AR71XX_RESET_REG_PERFC0			0x30
+#define AR71XX_RESET_REG_PERFC1			0x34
+#define AR71XX_RESET_REG_REV_ID			0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS	0x18
+#define AR913X_RESET_REG_RESET_MODULE		0x1c
+#define AR913X_RESET_REG_PERF_CTRL		0x20
+#define AR913X_RESET_REG_PERFC0			0x24
+#define AR913X_RESET_REG_PERFC1			0x28
+
+#define AR724X_RESET_REG_RESET_MODULE		0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE		0x1c
+#define AR933X_RESET_REG_BOOTSTRAP		0xac
+
+#define AR934X_RESET_REG_RESET_MODULE		0x1c
+#define AR934X_RESET_REG_BOOTSTRAP		0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE		0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP		0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
+
+#define MISC_INT_ETHSW			BIT(12)
+#define MISC_INT_TIMER4			BIT(10)
+#define MISC_INT_TIMER3			BIT(9)
+#define MISC_INT_TIMER2			BIT(8)
+#define MISC_INT_DMA			BIT(7)
+#define MISC_INT_OHCI			BIT(6)
+#define MISC_INT_PERFC			BIT(5)
+#define MISC_INT_WDOG			BIT(4)
+#define MISC_INT_UART			BIT(3)
+#define MISC_INT_GPIO			BIT(2)
+#define MISC_INT_ERROR			BIT(1)
+#define MISC_INT_TIMER			BIT(0)
+
+#define AR71XX_RESET_EXTERNAL		BIT(28)
+#define AR71XX_RESET_FULL_CHIP		BIT(24)
+#define AR71XX_RESET_CPU_NMI		BIT(21)
+#define AR71XX_RESET_CPU_COLD		BIT(20)
+#define AR71XX_RESET_DMA		BIT(19)
+#define AR71XX_RESET_SLIC		BIT(18)
+#define AR71XX_RESET_STEREO		BIT(17)
+#define AR71XX_RESET_DDR		BIT(16)
+#define AR71XX_RESET_GE1_MAC		BIT(13)
+#define AR71XX_RESET_GE1_PHY		BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE	BIT(10)
+#define AR71XX_RESET_GE0_MAC		BIT(9)
+#define AR71XX_RESET_GE0_PHY		BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL	BIT(6)
+#define AR71XX_RESET_USB_HOST		BIT(5)
+#define AR71XX_RESET_USB_PHY		BIT(4)
+#define AR71XX_RESET_PCI_BUS		BIT(1)
+#define AR71XX_RESET_PCI_CORE		BIT(0)
+
+#define AR7240_RESET_USB_HOST		BIT(5)
+#define AR7240_RESET_OHCI_DLL		BIT(3)
+
+#define AR724X_RESET_GE1_MDIO		BIT(23)
+#define AR724X_RESET_GE0_MDIO		BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL	BIT(10)
+#define AR724X_RESET_PCIE_PHY		BIT(7)
+#define AR724X_RESET_PCIE		BIT(6)
+#define AR724X_RESET_USB_HOST		BIT(5)
+#define AR724X_RESET_USB_PHY		BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE	BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC		BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE	BIT(10)
+#define AR913X_RESET_USB_HOST		BIT(5)
+#define AR913X_RESET_USB_PHY		BIT(4)
+
+#define AR933X_RESET_WMAC		BIT(11)
+#define AR933X_RESET_USB_HOST		BIT(5)
+#define AR933X_RESET_USB_PHY		BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE	BIT(3)
+
+#define AR934X_RESET_USB_PHY_ANALOG	BIT(11)
+#define AR934X_RESET_USB_HOST		BIT(5)
+#define AR934X_RESET_USB_PHY		BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE	BIT(3)
+
+#define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7	BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6	BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5	BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4	BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3	BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2	BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1	BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC	BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE	BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40	BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI	BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define AR934X_BOOTSTRAP_DDR1		BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+	(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX			BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP		BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1		BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0		BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1		BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2		BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3		BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2		BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0		BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1		BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2		BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3		BIT(16)
+#define QCA955X_EXT_INT_USB1			BIT(24)
+#define QCA955X_EXT_INT_USB2			BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+	 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+	(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+	 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+	 QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+	(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+	 QCA955X_EXT_INT_PCIE_RC2_INT3)
+
+#define REV_ID_MAJOR_MASK		0xfff0
+#define REV_ID_MAJOR_AR71XX		0x00a0
+#define REV_ID_MAJOR_AR913X		0x00b0
+#define REV_ID_MAJOR_AR7240		0x00c0
+#define REV_ID_MAJOR_AR7241		0x0100
+#define REV_ID_MAJOR_AR7242		0x1100
+#define REV_ID_MAJOR_AR9330		0x0110
+#define REV_ID_MAJOR_AR9331		0x1110
+#define REV_ID_MAJOR_AR9341		0x0120
+#define REV_ID_MAJOR_AR9342		0x1120
+#define REV_ID_MAJOR_AR9344		0x2120
+#define REV_ID_MAJOR_QCA9556		0x0130
+#define REV_ID_MAJOR_QCA9558		0x1130
+
+#define AR71XX_REV_ID_MINOR_MASK	0x3
+#define AR71XX_REV_ID_MINOR_AR7130	0x0
+#define AR71XX_REV_ID_MINOR_AR7141	0x1
+#define AR71XX_REV_ID_MINOR_AR7161	0x2
+#define AR71XX_REV_ID_REVISION_MASK	0x3
+#define AR71XX_REV_ID_REVISION_SHIFT	2
+
+#define AR913X_REV_ID_MINOR_MASK	0x3
+#define AR913X_REV_ID_MINOR_AR9130	0x0
+#define AR913X_REV_ID_MINOR_AR9132	0x1
+#define AR913X_REV_ID_REVISION_MASK	0x3
+#define AR913X_REV_ID_REVISION_SHIFT	2
+
+#define AR933X_REV_ID_REVISION_MASK	0x3
+
+#define AR724X_REV_ID_REVISION_MASK	0x3
+
+#define AR934X_REV_ID_REVISION_MASK	0xf
+
+#define QCA955X_REV_ID_REVISION_MASK	0xf
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS	0x00	/* Function Select */
+#define AR71XX_SPI_REG_CTRL	0x04	/* SPI Control */
+#define AR71XX_SPI_REG_IOC	0x08	/* SPI I/O Control */
+#define AR71XX_SPI_REG_RDS	0x0c	/* Read Data Shift */
+
+#define AR71XX_SPI_FS_GPIO	BIT(0)	/* Enable GPIO mode */
+
+#define AR71XX_SPI_CTRL_RD	BIT(6)	/* Remap Disable */
+#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
+
+#define AR71XX_SPI_IOC_DO	BIT(0)	/* Data Out pin */
+#define AR71XX_SPI_IOC_CLK	BIT(8)	/* CLK pin */
+#define AR71XX_SPI_IOC_CS(n)	BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0	AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1	AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2	AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL	(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
+				 AR71XX_SPI_IOC_CS2)
+
+/*
+ * GPIO block
+ */
+#define AR71XX_GPIO_REG_OE		0x00
+#define AR71XX_GPIO_REG_IN		0x04
+#define AR71XX_GPIO_REG_OUT		0x08
+#define AR71XX_GPIO_REG_SET		0x0c
+#define AR71XX_GPIO_REG_CLEAR		0x10
+#define AR71XX_GPIO_REG_INT_MODE	0x14
+#define AR71XX_GPIO_REG_INT_TYPE	0x18
+#define AR71XX_GPIO_REG_INT_POLARITY	0x1c
+#define AR71XX_GPIO_REG_INT_PENDING	0x20
+#define AR71XX_GPIO_REG_INT_ENABLE	0x24
+#define AR71XX_GPIO_REG_FUNC		0x28
+
+#define AR934X_GPIO_REG_FUNC		0x6c
+
+#define AR71XX_GPIO_COUNT		16
+#define AR7240_GPIO_COUNT		18
+#define AR7241_GPIO_COUNT		20
+#define AR913X_GPIO_COUNT		22
+#define AR933X_GPIO_COUNT		30
+#define AR934X_GPIO_COUNT		23
+#define QCA955X_GPIO_COUNT		24
+
+/*
+ * SRIF block
+ */
+#define AR934X_SRIF_CPU_DPLL1_REG	0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG	0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG	0x1c8
+
+#define AR934X_SRIF_DDR_DPLL1_REG	0x240
+#define AR934X_SRIF_DDR_DPLL2_REG	0x244
+#define AR934X_SRIF_DDR_DPLL3_REG	0x248
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT	27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK	0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT	18
+#define AR934X_SRIF_DPLL1_NINT_MASK	0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
+
+#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..3e4b7e3 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -61,10 +61,12 @@ ARCHDIR-arm	:= arm
 ARCHDIR-arm64	:= arm64
 ARCHDIR-riscv	:= riscv
 ARCHDIR-mips	:= mips
+ARCHDIR-mipseb	:= mipseb
 
 CFLAGS_arm      +=
 CFLAGS_arm64    += -mgeneral-regs-only
 CFLAGS_mips	+= -mips32r2 -G 0 -mno-abicalls -fno-pic
+CFLAGS_mipseb	+= -mips32r2 -G 0 -mno-abicalls -fno-pic
 CFLAGS_riscv	+=
 CFLAGS_x86_32	+=
 CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
@@ -85,6 +87,7 @@ CFLAGS_x86_64   += -mcmodel=large -mno-red-zone
 CFLAGS_arm	+= -Wstack-usage=1536
 CFLAGS_arm64	+= -Wstack-usage=1536
 CFLAGS_mips	+= -Wstack-usage=1536
+CFLAGS_mipseb	+= -Wstack-usage=1536
 CFLAGS_riscv	+= -Wstack-usage=1536
 
 toolchain_to_dir = \
@@ -139,6 +142,7 @@ endef
 # initialize standard toolchain (CC,AS and others) for give stage
 # @1 : stage for which the toolchain is to be initialized
 init_standard_toolchain = \
+	$(echo $(1) >> /tmp/fa ) \
 	$(eval $(call set_stage_toolchain,$(1))) \
 	$(eval $(call create_class_compiler,$(1),$(ARCH-$(1)-y)))
 
diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile
index b1fba4a..885dbfa 100644
--- a/util/crossgcc/Makefile
+++ b/util/crossgcc/Makefile
@@ -2,13 +2,13 @@
 BUILD_PLATFORM ?= i386-elf
 
 all:
-	$(MAKE) BUILDGCC_OPTIONS=-t build-i386 build-x64 build-armv7a build-mips build-riscv build-aarch64 \
+	$(MAKE) BUILDGCC_OPTIONS=-t build-i386 build-x64 build-armv7a build-mips build-mipseb build-riscv build-aarch64 \
 	        build_clang
 	$(MAKE) clean_tempfiles
 
 all_without_gdb:
 	$(MAKE) BUILDGCC_OPTIONS=-t build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \
-	        build-mips-without-gdb build-riscv-without-gdb build-aarch64-without-gdb build_clang
+	        build-mips-without-gdb build-mipseb-without-gdb build-riscv-without-gdb build-aarch64-without-gdb build_clang
 	$(MAKE) clean_tempfiles
 
 build_tools: build_gcc build_iasl build_gdb
@@ -47,6 +47,9 @@ build-aarch64:
 build-mips:
 	@$(MAKE) build_tools BUILD_PLATFORM=mipsel-elf
 
+build-mipseb:
+	@$(MAKE) build_tools BUILD_PLATFORM=mipseb-elf
+
 build-riscv:
 	@$(MAKE) build_tools BUILD_PLATFORM=riscv-elf
 
@@ -67,6 +70,9 @@ build-aarch64-without-gdb:
 build-mips-without-gdb:
 	@$(MAKE) build_tools_without_gdb BUILD_PLATFORM=mipsel-elf
 
+build-mipseb-without-gdb:
+	@$(MAKE) build_tools_without_gdb BUILD_PLATFORM=mipseb-elf
+
 build-riscv-without-gdb:
 	@$(MAKE) build_tools_without_gdb BUILD_PLATFORM=riscv-elf
 
@@ -86,5 +92,6 @@ distclean: clean
 
 .PHONY: build_gcc build_iasl build_gdb build_tools build_tools_without_gdb \
 	build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \
-	build-aarch64-without-gdb build-mips-without-gdb build-riscv-without-gdb \
+	build-aarch64-without-gdb build-mips-without-gdb build-mipseb-without-gdb \
+	build-riscv-without-gdb \
 	all build clean distclean clean_tempfiles all_without_gdb
diff --git a/util/crossgcc/README b/util/crossgcc/README
index 5ce9304..89fb2c9 100644
--- a/util/crossgcc/README
+++ b/util/crossgcc/README
@@ -7,6 +7,7 @@ known working:
   i386-elf
   x86_64-elf
   powerpc-elf
+  mipseb-elf
   mipsel-elf
   arm-elf
   armv7a-eabi
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 49e41e5..c7cd41b 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -315,7 +315,7 @@ myhelp()
 	printf "                                  (defaults to $TARGETARCH)\n"
 	printf "    [-S|--scripting]              build scripting support for GDB\n\n"
 	printf "Platforms for GCC & GDB:\n"
-	printf "    x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n\n"
+	printf "    x86_64 i386-elf i386-mingw32 mipseb-elf mipsel-elf riscv-elf arm aarch64\n\n"
 }
 
 myversion()
@@ -545,6 +545,7 @@ case "$TARGETARCH" in
 	x86_64*)	TARGETARCH=x86_64-elf;;
 	i386-elf)	;;
 	i386-mingw32)	;;
+	mipseb-elf)	TARGETARCH=mips-elf;;
 	mipsel-elf)	;;
 	riscv-elf)	;;
 	i386*)		TARGETARCH=i386-elf;;
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 46a30d1..bf8e08aa 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -180,6 +180,14 @@ detect_special_flags() {
 		  "$LDFLAGS --fix-cortex-a53-843419" && \
 		  LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419"
 		;;
+	mipseb)
+		testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \
+		  CFLAGS_GCC+=" -mno-abicalls -fno-pic"
+
+                # Enforce big endian mode.
+		testcc "$GCC" "$CFLAGS_GCC -EB" && \
+		  CFLAGS_GCC+=" -EB"
+		;;
 	mipsel)
 		testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \
 		  CFLAGS_GCC+=" -mno-abicalls -fno-pic"
@@ -235,7 +243,7 @@ EOF
 }
 
 # Architecture definitions
-SUPPORTED_ARCHITECTURES="arm arm64 mipsel riscv x64 x86"
+SUPPORTED_ARCHITECTURES="arm arm64 mipseb mipsel riscv x64 x86"
 
 arch_config_arm() {
 	TARCH="arm"
@@ -280,6 +288,16 @@ arch_config_x86() {
 	CC_RT_EXTRA_GCC="--wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3"
 }
 
+arch_config_mipseb() {
+	TARCH="mipseb"
+	TBFDARCHS="tradbigmips bigmips"
+	TCLIST="mips"
+	TWIDTH="32"
+	TSUPP="mips mipseb"
+	TABI="elf"
+	TENDIAN="EB"
+}
+
 arch_config_mipsel() {
 	TARCH="mips"
 	TBFDARCHS="tradlittlemips littlemips"


From gerrit at coreboot.org  Mon Sep 21 18:12:19 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 21 Sep 2015 18:12:19 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool: don't
	use endian to fix BSD hosts
References: <I84a88f6882b6c8f14fb089e4b629e916386afe4d+0@gerrit.coreboot.org>
Message-ID: <I84a88f6882b6c8f14fb089e4b629e916386afe4d+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11695

-gerrit

commit 28ea67f1f8993a7c3f875d75888d3b220fef2bd2
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Sep 21 13:10:13 2015 -0500

    cbfstool: don't use endian to fix BSD hosts
    
    endian.h lives in under sys on the BSDs. Replace htole32() with
    swab32(htonl(..)) as a proxy for little endian operations.
    
    Change-Id: I84a88f6882b6c8f14fb089e4b629e916386afe4d
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 util/cbfstool/cbfstool.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index ed6e898..5194061 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -19,7 +19,6 @@
  * Foundation, Inc.
  */
 
-#include <endian.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
@@ -272,7 +271,7 @@ static int cbfs_add_master_header(void)
 	// TODO: when we have a BE target, we'll need to store this as BE
 	*(uint32_t *)(buffer_get(&image.buffer) +
 		buffer_size(&image.buffer) - 4) =
-		htole32(header_offset);
+		swab32(htonl(header_offset));
 
 	ret = 0;
 


From gerrit at coreboot.org  Mon Sep 21 18:19:34 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Mon, 21 Sep 2015 18:19:34 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Revert
	"coreboot_table: don't add CMOS checksum twice."
References: <I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db+0@gerrit.coreboot.org>
Message-ID: <I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11696

-gerrit

commit 4362be15f019599c49e15df5c012a3edffe9c8c7
Author: Nico Huber <nico.h at gmx.de>
Date:   Mon Sep 21 20:11:47 2015 +0200

    Revert "coreboot_table: don't add CMOS checksum twice."
    
    This reverts commit e6606518243d9beda31693d40493b5f7a1a3e2e0.
    
    After some discussion on IRC we decided to revert it as libpayload can
    only read the copy that was removed (and other users like nvramtool can
    only read the other copy). So we need both copies at this time.
    
    Conflicts:
    	3rdparty/arm-trusted-firmware
    	3rdparty/blobs
    	3rdparty/vboot
    	src/lib/coreboot_table.c
    
    Signed-off-by: Nico Huber <nico.h at gmx.de>
    Change-Id: I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db
---
 src/lib/coreboot_table.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6859bf2..35341ab 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -34,6 +34,9 @@
 #include <cbmem.h>
 #include <bootmem.h>
 #include <spi_flash.h>
+#if CONFIG_USE_OPTION_TABLE
+#include <option_table.h>
+#endif
 #if CONFIG_CHROMEOS
 #if CONFIG_HAVE_ACPI_TABLES
 #include <arch/acpi.h>
@@ -333,6 +336,26 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 	return mainboard;
 }
 
+#if CONFIG_USE_OPTION_TABLE
+static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
+{
+	struct lb_record *rec;
+	struct cmos_checksum *cmos_checksum;
+	rec = lb_new_record(header);
+	cmos_checksum = (struct cmos_checksum *)rec;
+	cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM;
+
+	cmos_checksum->size = (sizeof(*cmos_checksum));
+
+	cmos_checksum->range_start = LB_CKS_RANGE_START * 8;
+	cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7;
+	cmos_checksum->location = LB_CKS_LOC * 8;
+	cmos_checksum->type = CHECKSUM_PCBIOS;
+
+	return cmos_checksum;
+}
+#endif
+
 static void lb_strings(struct lb_header *header)
 {
 	static const struct {
@@ -435,6 +458,8 @@ unsigned long write_coreboot_table(
 			struct lb_record *rec_dest = lb_new_record(head);
 			/* Copy the option config table, it's already a lb_record... */
 			memcpy(rec_dest,  option_table, option_table->size);
+			/* Create cmos checksum entry in coreboot table */
+			lb_cmos_checksum(head);
 		} else {
 			printk(BIOS_ERR, "cmos_layout.bin could not be found!\n");
 		}


From gerrit at coreboot.org  Mon Sep 21 19:10:30 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 21 Sep 2015 19:10:30 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	don't use endian to fix BSD hosts
References: <I84a88f6882b6c8f14fb089e4b629e916386afe4d+0@gerrit.coreboot.org>
Message-ID: <E1Ze6Tu-0002g6-3A@mail.coreboot.org>

the following patch was just integrated into master:
commit 4b93a4f47a7457162d1be20eeffe57f81d5cd6af
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Sep 21 13:10:13 2015 -0500

    cbfstool: don't use endian to fix BSD hosts
    
    endian.h lives in under sys on the BSDs. Replace htole32() with
    swab32(htonl(..)) as a proxy for little endian operations.
    
    Change-Id: I84a88f6882b6c8f14fb089e4b629e916386afe4d
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11695
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer at gmail.com>
    Reviewed-by: Jonathan A. Kollasch <jakllsch at kollasch.net>


See http://review.coreboot.org/11695 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 21 20:30:32 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 21 Sep 2015 20:30:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: link
	bootblock.elf with .data and .bss sections again
References: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+0@gerrit.coreboot.org>
Message-ID: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11680

-gerrit

commit a8637e5421de5a7f2c1f668a71ce14ee3051fe05
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 17:02:53 2015 -0500

    linking: link bootblock.elf with .data and .bss sections again
    
    Currently coreboot expects the loader to clear the bss section
    for all stages. i.e. stages don't clear their own bss. On ARM
    SoCs the BootROM would be responsible for this. To do that
    one needs to include the bss section data (all zeros) in the
    bootblock.bin file. This was previously being attempted by
    keeping the .bss info in the .data section because objcopy
    happened zero out non-file allocated data section data.
    
    Instead go back to linking bootblock with the bss section
    but mark the bss section as loadable allocatable data. That
    way it will be included in the binary properly when objcopy
    -O binary is emplyed. Also do the same for the data section
    in the case of no non-zero object values are in the data
    section.
    
    Without this change the trick of including .bss in .data
    was not working when there wasn't a non-zero value object
    in the data section.
    
    BUG=None
    BRANCH=None
    TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
         the cleared bss.
    
    Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                            | 17 +++++++++++++----
 src/lib/program.ld                      |  7 -------
 src/soc/broadcom/cygnus/Makefile.inc    |  6 +-----
 src/soc/imgtec/pistachio/Makefile.inc   |  8 +-------
 src/soc/marvell/bg4cd/Makefile.inc      |  3 ---
 src/soc/nvidia/tegra124/Makefile.inc    |  3 ---
 src/soc/nvidia/tegra132/Makefile.inc    |  3 ---
 src/soc/qualcomm/ipq806x/Makefile.inc   |  8 +-------
 src/soc/rockchip/rk3288/Makefile.inc    |  3 ---
 src/soc/samsung/exynos5250/Makefile.inc |  3 ---
 src/soc/samsung/exynos5420/Makefile.inc |  3 ---
 11 files changed, 16 insertions(+), 48 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 81c149d..069de39 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -531,10 +531,19 @@ find-substr = $(word 1,$(subst _, ,$(1)))
 # and remove .x the next time and finally return romstage
 find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call find-substr,$(1))),$(call find-class,$(basename $(1))))
 
-$(objcbfs)/%.bin: $(objcbfs)/%.elf
-	$(eval class := $(call find-class,$(@F)))
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_$(class)) -O binary $< $@
+# Bootblocks are not CBFS stages. coreboot is currently expecting the bss to
+# be cleared by the loader of the stage. For ARM SoCs that means one needs to
+# include the bss section in the binary so the BootROM clears the bss on
+# loading of the bootblock stage. Achieve this by marking the bss section
+# loadable,allocatable, and data. Do the same for the .data section in case
+# it's marked as NOBITS.
+$(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.elf
+	@printf "    OBJCOPY    $(notdir $(@))\n"
+	$(OBJCOPY_bootblock) --set-section-flags .bss=load,alloc,data --set-section-flags .data=loa,alloc,data $< $<.tmp
+	$(OBJCOPY_bootblock) -O binary $<.tmp $@
+
+$(objcbfs)/%.bin: $(objcbfs)/%.raw.bin
+	cp $< $@
 
 $(objcbfs)/%.elf: $(objcbfs)/%.debug
 	$(eval class := $(call find-class,$(@F)))
diff --git a/src/lib/program.ld b/src/lib/program.ld
index c8ce5ee..ab36239 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -111,14 +111,7 @@
 #endif
 
 #if ARCH_STAGE_HAS_BSS_SECTION
-#if ENV_BOOTBLOCK
-/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
- * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
- * the BSS into the .data section so those zeroes get loaded explicitly. */
-.data . : {
-#else
 .bss . : {
-#endif
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bss = .;
 	*(.bss)
diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc
index ff231f7..8bad15f 100644
--- a/src/soc/broadcom/cygnus/Makefile.inc
+++ b/src/soc/broadcom/cygnus/Makefile.inc
@@ -62,10 +62,6 @@ ramstage-y += usb.c
 
 CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
 
-$(objcbfs)/bootblock.tmp: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@
-
 ifneq ($(V),1)
 redirect := > /dev/null
 endif
@@ -96,7 +92,7 @@ endif
 #   SLEEP		1
 #   DEEP_SLEEP		2
 #   EXCEPTION		4
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.tmp \
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
 		$(objutil)/broadcom/secimage/secimage \
 		util/broadcom/unauth.cfg \
 		util/broadcom/khmacsha256
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index df9fbcf..7f06db5 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -46,14 +46,8 @@ romstage-y += monotonic_timer.c
 
 CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/
 
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@.tmp
-	@mv $@.tmp $@
-
 # Create a complete bootblock which will start up the system
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BIMGTOOL)
 	@printf "    BIMGTOOL   $(subst $(obj)/,,$(@))\n"
 	$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
 
diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc
index 1a801c0..ded1917 100644
--- a/src/soc/marvell/bg4cd/Makefile.inc
+++ b/src/soc/marvell/bg4cd/Makefile.inc
@@ -45,9 +45,6 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c
 
 CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "Generating: $(subst $(obj)/,,$(@))\n"
 	@mkdir -p $(dir $@)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 46ce59d..38ba4f6 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -84,9 +84,6 @@ CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/
 # package up the image pull in bootblock.bin, it will be this wrapped version
 # instead of the raw bootblock.
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
 	@printf "    CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
 	$(CBOOTIMAGE) -gbct --soc tegra124 $< $@
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index c192055..bdd8074 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -121,9 +121,6 @@ CBOOTIMAGE_OPTS = --soc tegra132
 # package up the image pull in bootblock.bin, it will be this wrapped version
 # instead of the raw bootblock.
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
 	@printf "    CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
 	$(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 84eae0b..83b5e06 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -56,14 +56,8 @@ ramstage-y += tz_wrapper.S
 
 ifeq ($(CONFIG_USE_BLOBS),y)
 
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@.tmp
-	@mv $@.tmp $@
-
 # Add MBN header to allow SBL3 to start coreboot bootblock
-$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
+$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin
 	@printf "    ADD MBN    $(subst $(obj)/,,$(@))\n"
 	./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
 	@mv $@.tmp $@
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index cd523b0..830ae1e 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -75,9 +75,6 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "Generating: $(subst $(obj)/,,$(@))\n"
 	@mkdir -p $(dir $@)
diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc
index 9f49134..2731f17 100644
--- a/src/soc/samsung/exynos5250/Makefile.inc
+++ b/src/soc/samsung/exynos5250/Makefile.inc
@@ -46,9 +46,6 @@ ramstage-y += cbmem.c
 
 CPPFLAGS_common += -Isrc/soc/samsung/exynos5250/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "    BL1, CKSUM $(subst $(obj)/,,$(@))\n"
 	util/exynos/fixed_cksum.py $< $<.cksum 32768
diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc
index 753e6d0..498e8d1 100644
--- a/src/soc/samsung/exynos5420/Makefile.inc
+++ b/src/soc/samsung/exynos5420/Makefile.inc
@@ -48,9 +48,6 @@ rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c
 
 CPPFLAGS_common += -Isrc/soc/samsung/exynos5420/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "    BL1, CKSUM $(subst $(obj)/,,$(@))\n"
 	util/exynos/variable_cksum.py $< $<.cksum


From gerrit at coreboot.org  Mon Sep 21 20:30:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 21 Sep 2015 20:30:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: coreboot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <I9e46a279569733336bc0a018aed96bc924c07cdd+14@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592

-gerrit

commit 338fcd7207d30f6ea79e07ef2924caae804b75f4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    coreboot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                                       |   4 +-
 src/arch/x86/include/arch/cbfs.h                   |   2 +-
 src/arch/x86/romcc_console.c                       |   2 +-
 src/commonlib/Makefile.inc                         |  10 +
 src/commonlib/include/commonlib/cbfs_serialized.h  | 190 ++++++++++
 src/commonlib/include/commonlib/cbmem_id.h         | 113 ++++++
 src/commonlib/include/commonlib/coreboot_tables.h  | 387 +++++++++++++++++++++
 src/commonlib/include/commonlib/fmap_serialized.h  |  73 ++++
 src/commonlib/include/commonlib/helpers.h          |  51 +++
 src/commonlib/include/commonlib/loglevel.h         | 178 ++++++++++
 src/commonlib/include/commonlib/mem_pool.h         |  73 ++++
 src/commonlib/include/commonlib/region.h           | 157 +++++++++
 src/commonlib/include/commonlib/rmodule-defs.h     |  63 ++++
 .../include/commonlib/timestamp_serialized.h       |  92 +++++
 src/commonlib/mem_pool.c                           |  51 +++
 src/commonlib/region.c                             | 196 +++++++++++
 src/drivers/intel/fsp1_1/include/fsp/util.h        |   2 +-
 src/include/assets.h                               |   2 +-
 src/include/boot/coreboot_tables.h                 | 384 +-------------------
 src/include/boot_device.h                          |   2 +-
 src/include/cbfs.h                                 |   4 +-
 src/include/cbfs_serialized.h                      | 190 ----------
 src/include/cbmem.h                                |   2 +-
 src/include/cbmem_id.h                             | 113 ------
 src/include/console/console.h                      |   2 +-
 src/include/console/early_print.h                  |   2 +-
 src/include/console/loglevel.h                     | 178 ----------
 src/include/fmap.h                                 |   4 +-
 src/include/fmap_serialized.h                      |  73 ----
 src/include/mem_pool.h                             |  73 ----
 src/include/region.h                               | 157 ---------
 src/include/rmodule-defs.h                         |  63 ----
 src/include/rmodule.h                              |   2 +-
 src/include/stddef.h                               |  34 +-
 src/include/stdlib.h                               |  14 -
 src/include/timestamp.h                            |  69 +---
 src/lib/Makefile.inc                               |   9 -
 src/lib/cbfs_boot_props.c                          |   2 +-
 src/lib/fmap.c                                     |   2 +-
 src/lib/mem_pool.c                                 |  51 ---
 src/lib/region.c                                   | 196 -----------
 src/mainboard/advansus/a785e-i/romstage.c          |   2 +-
 src/mainboard/amd/bimini_fam10/romstage.c          |   2 +-
 src/mainboard/amd/dinar/romstage.c                 |   2 +-
 src/mainboard/amd/inagua/romstage.c                |   2 +-
 src/mainboard/amd/lamar/romstage.c                 |   2 +-
 src/mainboard/amd/mahogany_fam10/romstage.c        |   2 +-
 src/mainboard/amd/olivehill/romstage.c             |   2 +-
 src/mainboard/amd/olivehillplus/romstage.c         |   2 +-
 src/mainboard/amd/parmer/romstage.c                |   2 +-
 src/mainboard/amd/persimmon/romstage.c             |   2 +-
 .../amd/serengeti_cheetah_fam10/romstage.c         |   2 +-
 src/mainboard/amd/south_station/romstage.c         |   2 +-
 src/mainboard/amd/thatcher/romstage.c              |   2 +-
 src/mainboard/amd/tilapia_fam10/romstage.c         |   2 +-
 src/mainboard/amd/torpedo/romstage.c               |   2 +-
 src/mainboard/amd/union_station/romstage.c         |   2 +-
 src/mainboard/asrock/e350m1/romstage.c             |   2 +-
 src/mainboard/asrock/imb-a180/romstage.c           |   2 +-
 src/mainboard/asus/m4a78-em/romstage.c             |   2 +-
 src/mainboard/asus/m4a785-m/romstage.c             |   2 +-
 src/mainboard/asus/m5a88-v/romstage.c              |   2 +-
 src/mainboard/avalue/eax-785e/romstage.c           |   2 +-
 src/mainboard/bap/ode_e20XX/romstage.c             |   2 +-
 src/mainboard/biostar/am1ml/romstage.c             |   2 +-
 src/mainboard/gigabyte/ma785gm/romstage.c          |   2 +-
 src/mainboard/gigabyte/ma785gmt/romstage.c         |   2 +-
 src/mainboard/gigabyte/ma78gm/romstage.c           |   2 +-
 src/mainboard/gizmosphere/gizmo/romstage.c         |   2 +-
 src/mainboard/gizmosphere/gizmo2/romstage.c        |   2 +-
 src/mainboard/google/peach_pit/romstage.c          |   2 +-
 src/mainboard/hp/abm/romstage.c                    |   2 +-
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |   2 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |   2 +-
 src/mainboard/jetway/pa78vm5/romstage.c            |   2 +-
 src/mainboard/lippert/frontrunner-af/romstage.c    |   2 +-
 src/mainboard/lippert/toucan-af/romstage.c         |   2 +-
 src/mainboard/pcengines/apu1/romstage.c            |   2 +-
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |   2 +-
 src/soc/intel/broadwell/include/soc/me.h           |   2 +-
 src/southbridge/amd/cimx/sb700/Platform.h          |   2 +-
 src/southbridge/amd/cimx/sb700/early.c             |   2 +-
 src/southbridge/amd/cimx/sb900/early.c             |   2 +-
 src/vendorcode/amd/agesa/common/Porting.h          |   2 +-
 src/vendorcode/amd/pi/00630F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c    |   2 +-
 src/vendorcode/amd/pi/00730F01/Porting.h           |   2 +-
 src/vendorcode/amd/pi/Makefile.inc                 |   1 +
 src/vendorcode/google/chromeos/vboot_common.h      |   2 +-
 util/cbfstool/Makefile.inc                         |   1 +
 util/cbfstool/rmodule.c                            |   2 +-
 util/cbmem/Makefile                                |   2 +-
 util/cbmem/cbmem.c                                 |   9 +-
 94 files changed, 1710 insertions(+), 1673 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 46d6eb2..81c149d 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
 export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 endif
 
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
 CPPFLAGS_common += -Isrc/device/oprom/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
 #ifndef __INCLUDE_ARCH_CBFS__
 #define __INCLUDE_ARCH_CBFS__
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
 #include <endian.h>
 
 #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
 #include <build.h>
 #include <console/streams.h>
 #include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* Include the sources. */
 #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_PAYLOAD    0x20
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t checksum;
+	uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+	uint32_t compression;  /** Compression type */
+	uint64_t entry;  /** entry point */
+	uint64_t load;   /** Where to load in memory */
+	uint32_t len;          /** length of data to load */
+	uint32_t memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
+#define CBMEM_ID_CBTABLE	0x43425442
+#define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_COVERAGE	0x47434f56
+#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
+#define CBMEM_ID_ELOG		0x454c4f47
+#define CBMEM_ID_FREESPACE	0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME	0x52505346
+#define CBMEM_ID_GDT		0x4c474454
+#define CBMEM_ID_HOB_POINTER	0x484f4221
+#define CBMEM_ID_IGD_OPREGION	0x4f444749
+#define CBMEM_ID_IMD_ROOT	0xff4017ff
+#define CBMEM_ID_IMD_SMALL	0x53a11439
+#define CBMEM_ID_MEMINFO	0x494D454D
+#define CBMEM_ID_MPTABLE	0x534d5054
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
+#define CBMEM_ID_NONE		0x00000000
+#define CBMEM_ID_PIRQ		0x49525154
+#define CBMEM_ID_POWER_STATE	0x50535454
+#define CBMEM_ID_RAM_OOPS	0x05430095
+#define CBMEM_ID_RAMSTAGE	0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
+#define CBMEM_ID_REFCODE	0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
+#define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH	0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT		0xff4007ff
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
+#define CBMEM_ID_SPINTABLE	0x59175917
+#define CBMEM_ID_STAGEx_META	0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
+#define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE				 \
+	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
+	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
+	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
+	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
+	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
+	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
+	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
+	{ CBMEM_ID_ELOG,		"ELOG       " }, \
+	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
+	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
+	{ CBMEM_ID_GDT,			"GDT        " }, \
+	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
+	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
+	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
+	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
+	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
+	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
+	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
+	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
+	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
+	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
+	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
+	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
+	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
+	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
+	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
+	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
+	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
+	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
+	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
+	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
+	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
+	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
+	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
+	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image.  Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing.   For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed.  This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ *   a particular motherboard is constructed? (Assuming the kernel
+ *   has drivers for all of the hardware but it does not have
+ *   assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not.  This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped.  Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+	uint64_t result;
+	result = value.hi;
+	result = (result << 32) + value.lo;
+	return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+	struct lb_uint64 result;
+	result.lo = (value >> 0) & 0xffffffff;
+	result.hi = (value >> 32) & 0xffffffff;
+	return result;
+}
+
+struct lb_header
+{
+	uint8_t  signature[4]; /* LBIO */
+	uint32_t header_bytes;
+	uint32_t header_checksum;
+	uint32_t table_bytes;
+	uint32_t table_checksum;
+	uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record.  Encoding both type and size.  The type is obviously
+ * so you can tell what it is.  The size allows you to skip that
+ * boot environment record if you don't know what it is.  This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+	uint32_t tag;		/* tag ID */
+	uint32_t size;		/* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED		0x0000
+
+#define LB_TAG_MEMORY		0x0001
+
+struct lb_memory_range {
+	struct lb_uint64 start;
+	struct lb_uint64 size;
+	uint32_t type;
+#define LB_MEM_RAM		 1	/* Memory anyone can use */
+#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
+#define LB_MEM_ACPI		 3	/* ACPI Tables */
+#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
+#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
+#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+	uint32_t tag;
+	uint32_t size;
+	struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB		0x0002
+struct lb_hwrpb {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
+#define LB_TAG_VERSION		0x0004
+#define LB_TAG_EXTRA_VERSION	0x0005
+#define LB_TAG_BUILD		0x0006
+#define LB_TAG_COMPILE_TIME	0x0007
+#define LB_TAG_COMPILE_BY	0x0008
+#define LB_TAG_COMPILE_HOST	0x0009
+#define LB_TAG_COMPILE_DOMAIN	0x000a
+#define LB_TAG_COMPILER		0x000b
+#define LB_TAG_LINKER		0x000c
+#define LB_TAG_ASSEMBLER	0x000d
+struct lb_string {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP	0x0026
+struct lb_timestamp {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL		0x000f
+struct lb_serial {
+	uint32_t tag;
+	uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
+	uint32_t baud;
+	uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE		0x0010
+struct lb_console {
+	uint32_t tag;
+	uint32_t size;
+	uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250	0
+#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI		5
+#define LB_TAG_CONSOLE_SERIAL8250MEM	6
+
+#define LB_TAG_FORWARD		0x0011
+struct lb_forward {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER	0x0012
+struct lb_framebuffer {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t physical_address;
+	uint32_t x_resolution;
+	uint32_t y_resolution;
+	uint32_t bytes_per_line;
+	uint8_t bits_per_pixel;
+	uint8_t red_mask_pos;
+	uint8_t red_mask_size;
+	uint8_t green_mask_pos;
+	uint8_t green_mask_size;
+	uint8_t blue_mask_pos;
+	uint8_t blue_mask_size;
+	uint8_t reserved_mask_pos;
+	uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT		0x0015
+#define LB_TAG_VBNV		0x0019
+#define LB_TAB_VBOOT_HANDOFF	0x0020
+#define LB_TAB_DMA		0x0022
+#define LB_TAG_RAM_OOPS		0x0023
+#define LB_TAG_MTC		0x002b
+struct lb_range {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t range_start;
+	uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+#define LB_TAG_ACPI_GNVS	0x0024
+#define LB_TAG_WIFI_CALIBRATION	0x0027
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR	0x0021
+struct lb_x86_rom_mtrr {
+	uint32_t tag;
+	uint32_t size;
+	/* The variable range MTRR index covering the ROM. */
+	uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID		0x0025
+struct lb_board_id {
+	uint32_t tag;
+	uint32_t size;
+	/* Board ID as retrieved from the board revision GPIOs. */
+	uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS	0x0026
+struct mac_address {
+	uint8_t mac_addr[6];
+	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t count;
+	struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE		0x0028
+struct lb_ram_code {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH	0x0029
+struct lb_spi_flash {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t flash_size;
+	uint32_t sector_size;
+	uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+	uint32_t tag;
+	uint32_t size;
+	/* offsets are relative to start of boot media */
+	uint64_t fmap_offset;
+	uint64_t cbfs_offset;
+	uint64_t cbfs_size;
+	uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO		0x002a
+#define MAX_SERIALNO_LENGTH	32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+	uint32_t tag;               /* CMOS definitions table type */
+	uint32_t size;               /* size of the entire table */
+	uint32_t header_length;      /* length of header */
+};
+
+/* cmos entry record
+        This record is variable length.  The name field may be
+        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+        anywhere in the byte, but can not span bytes unless it
+        starts at the beginning of the byte and the length is
+        fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+	uint32_t tag;                /* entry type */
+	uint32_t size;               /* length of this record */
+	uint32_t bit;                /* starting bit from start of image */
+	uint32_t length;             /* length of field in bits */
+	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
+	uint32_t config_id;          /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+					       variable length int aligned */
+};
+
+
+/* cmos enumerations record
+        This record is variable length.  The text field may be
+        shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+	uint32_t tag;		     /* enumeration type */
+	uint32_t size; 		     /* length of this record */
+	uint32_t config_id;          /* a number identifying the config id */
+	uint32_t value;              /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+						variable length int aligned */
+};
+
+/* cmos defaults record
+        This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+	uint32_t tag;                /* default type */
+	uint32_t size;               /* length of this record */
+	uint32_t name_length;        /* length of the following name field */
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct	cmos_checksum {
+	uint32_t tag;
+	uint32_t size;
+	/* In practice everything is byte aligned, but things are measured
+	 * in bits to be consistent.
+	 */
+	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
+	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
+	uint32_t location;	/* First bit of the checksum (byte aligned) */
+	uint32_t type;		/* Checksum algorithm that is used */
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __attribute__((packed));
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG      0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT      1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT       2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR        3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING    4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE     5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO       6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG      7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW       8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER	9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+	uint8_t *buf;
+	size_t size;
+	uint8_t *last_alloc;
+	size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_)	\
+	{				\
+		.buf = (buf_),		\
+		.size = (size_),	\
+		.last_alloc = NULL,	\
+		.free_offset = 0,	\
+	}
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+	mp->last_alloc = NULL;
+	mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+	mp->buf = buf;
+	mp->size = sz;
+	mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device.  Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size);
+
+
+/****************************************
+ *  Implementation of a region device   *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+	void *(*mmap)(const struct region_device *, size_t, size_t);
+	int (*munmap)(const struct region_device *, void *);
+	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+	size_t offset;
+	size_t size;
+};
+
+struct region_device {
+	const struct region_device *root;
+	const struct region_device_ops *ops;
+	struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_)		\
+	{						\
+		.root = NULL,				\
+		.ops = (ops_),				\
+		.region = {				\
+			.offset = (offset_),		\
+			.size = (size_),		\
+		},					\
+	}
+
+static inline size_t region_offset(const struct region *r)
+{
+	return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+	return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+	return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+	return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+	return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+	char *base;
+	struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_)				\
+	{								\
+		.base = (void *)(base_),				\
+		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
+	}
+
+struct mmap_helper_region_device {
+	struct mem_pool pool;
+	struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+	{								\
+		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
+	}
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.  */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t  version;
+	uint8_t  type;
+	/* The payload represents the program's loadable code and data. */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module. */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/* The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/* The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory. */
+	uint32_t module_program_size;
+	/* This is program's execution entry point. */
+	uint32_t module_entry_point;
+	/* Optional parameter structure that can be used to pass data into
+	 * the module. */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss. */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth. */
+	uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint16_t	max_entries;
+	uint16_t	tick_freq_mhz;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_VBOOT = 5,
+	TS_END_VBOOT = 6,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_START_BOOTBLOCK = 11,
+	TS_END_BOOTBLOCK = 12,
+	TS_START_COPYROM = 13,
+	TS_END_COPYROM = 14,
+	TS_START_ULZMA = 15,
+	TS_END_ULZMA = 16,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+
+	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+	TS_START_COPYVER = 501,
+	TS_END_COPYVER = 502,
+	TS_START_TPMINIT = 503,
+	TS_END_TPMINIT = 504,
+	TS_START_VERIFY_SLOT = 505,
+	TS_END_VERIFY_SLOT = 506,
+	TS_START_HASH_BODY = 507,
+	TS_DONE_LOADING = 508,
+	TS_DONE_HASHING = 509,
+	TS_END_HASH_BODY = 510,
+
+	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+	TS_FSP_MEMORY_INIT_START = 950,
+	TS_FSP_MEMORY_INIT_END = 951,
+	TS_FSP_TEMP_RAM_EXIT_START = 952,
+	TS_FSP_TEMP_RAM_EXIT_END = 953,
+	TS_FSP_SILICON_INIT_START = 954,
+	TS_FSP_SILICON_INIT_END = 955,
+	TS_FSP_BEFORE_ENUMERATE = 956,
+	TS_FSP_AFTER_ENUMERATE = 957,
+	TS_FSP_BEFORE_FINALIZE = 958,
+	TS_FSP_AFTER_FINALIZE = 959,
+
+	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+	void *p;
+
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
+
+	/* Determine if any space available. */
+	if ((mp->size - mp->free_offset) < sz)
+		return NULL;
+
+	p = &mp->buf[mp->free_offset];
+
+	mp->free_offset += sz;
+	mp->last_alloc = p;
+
+	return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+	/* Determine if p was the most recent allocation. */
+	if (p == NULL || mp->last_alloc != p)
+		return;
+
+	mp->free_offset = mp->last_alloc - mp->buf;
+	/* No way to track allocation before this one. */
+	mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+	return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+	if (region_offset(c) < region_offset(p))
+		return 0;
+
+	if (region_sz(c) > region_sz(p))
+		return 0;
+
+	if (region_end(c) > region_end(p))
+		return 0;
+
+	return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+	inner->offset += region_offset(outer);
+	return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+	if (rdev->root == NULL)
+		return rdev;
+	return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return NULL;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	const struct region_device *rdev;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+			size_t size)
+{
+	const struct region_device *rdev;
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&rd->region, &req))
+		return -1;
+
+	rdev = rdev_root(rd);
+
+	return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+		size_t offset, size_t size)
+{
+	struct region req = {
+		.offset = offset,
+		.size = size,
+	};
+
+	if (!normalize_and_ok(&parent->region, &req))
+		return -1;
+
+	/* Keep track of root region device. Note the offsets are relative
+	 * to the root device. */
+	child->root = rdev_root(parent);
+	child->ops = NULL;
+	child->region.offset = req.offset;
+	child->region.size = req.size;
+
+	return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+				size_t size)
+{
+	memset(mdev, 0, sizeof(*mdev));
+	mdev->base = base;
+	mdev->rdev.ops = &mem_rdev_ops;
+	mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+			size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+	return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	const struct mem_region_device *mdev;
+
+	mdev = container_of(rd, typeof(*mdev), rdev);
+
+	memcpy(b, &mdev->base[offset], size);
+
+	return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+	.mmap = mdev_mmap,
+	.munmap = mdev_munmap,
+	.readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+				void *cache, size_t cache_size)
+{
+	mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+				size_t size)
+{
+	struct mmap_helper_region_device *mdev;
+	void *mapping;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mapping = mem_pool_alloc(&mdev->pool, size);
+
+	if (mapping == NULL)
+		return NULL;
+
+	if (rd->ops->readat(rd, mapping, offset, size) != size) {
+		mem_pool_free(&mdev->pool, mapping);
+		return NULL;
+	}
+
+	return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+	struct mmap_helper_region_device *mdev;
+
+	mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+	mem_pool_free(&mdev->pool, mapping);
+
+	return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 041c0f1..79c348a 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
 #include <fsp/soc_binding.h>
 #include <fsp/gop.h>
 #include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
 #ifndef ASSETS_H
 #define ASSETS_H
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* An asset represents data used to boot the system. It can be found within
  * CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
 #ifndef COREBOOT_TABLES_H
 #define COREBOOT_TABLES_H
 
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image.  Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing.   For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed.  This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- *   a particular motherboard is constructed? (Assuming the kernel
- *   has drivers for all of the hardware but it does not have
- *   assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not.  This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped.  Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
-	uint32_t lo;
-	uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
-	uint64_t result;
-	result = value.hi;
-	result = (result << 32) + value.lo;
-	return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
-	struct lb_uint64 result;
-	result.lo = (value >> 0) & 0xffffffff;
-	result.hi = (value >> 32) & 0xffffffff;
-	return result;
-}
-
-struct lb_header
-{
-	uint8_t  signature[4]; /* LBIO */
-	uint32_t header_bytes;
-	uint32_t header_checksum;
-	uint32_t table_bytes;
-	uint32_t table_checksum;
-	uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record.  Encoding both type and size.  The type is obviously
- * so you can tell what it is.  The size allows you to skip that
- * boot environment record if you don't know what it is.  This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
-	uint32_t tag;		/* tag ID */
-	uint32_t size;		/* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED		0x0000
-
-#define LB_TAG_MEMORY		0x0001
-
-struct lb_memory_range {
-	struct lb_uint64 start;
-	struct lb_uint64 size;
-	uint32_t type;
-#define LB_MEM_RAM		 1	/* Memory anyone can use */
-#define LB_MEM_RESERVED		 2	/* Don't use this memory region */
-#define LB_MEM_ACPI		 3	/* ACPI Tables */
-#define LB_MEM_NVS		 4	/* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE		 5	/* Unusable address space */
-#define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
-#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
-	uint32_t tag;
-	uint32_t size;
-	struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB		0x0002
-struct lb_hwrpb {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD	0x0003
-struct lb_mainboard {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  vendor_idx;
-	uint8_t  part_number_idx;
-	uint8_t  strings[0];
-};
-
-#define LB_TAG_VERSION		0x0004
-#define LB_TAG_EXTRA_VERSION	0x0005
-#define LB_TAG_BUILD		0x0006
-#define LB_TAG_COMPILE_TIME	0x0007
-#define LB_TAG_COMPILE_BY	0x0008
-#define LB_TAG_COMPILE_HOST	0x0009
-#define LB_TAG_COMPILE_DOMAIN	0x000a
-#define LB_TAG_COMPILER		0x000b
-#define LB_TAG_LINKER		0x000c
-#define LB_TAG_ASSEMBLER	0x000d
-struct lb_string {
-	uint32_t tag;
-	uint32_t size;
-	uint8_t  string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP	0x0026
-struct lb_timestamp {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL		0x000f
-struct lb_serial {
-	uint32_t tag;
-	uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED     1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
-	uint32_t type;
-	uint32_t baseaddr;
-	uint32_t baud;
-	uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE		0x0010
-struct lb_console {
-	uint32_t tag;
-	uint32_t size;
-	uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250	0
-#define LB_TAG_CONSOLE_VGA		1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT		2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF		3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM		4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI		5
-#define LB_TAG_CONSOLE_SERIAL8250MEM	6
-
-#define LB_TAG_FORWARD		0x0011
-struct lb_forward {
-	uint32_t tag;
-	uint32_t size;
-	uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER	0x0012
-struct lb_framebuffer {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t physical_address;
-	uint32_t x_resolution;
-	uint32_t y_resolution;
-	uint32_t bytes_per_line;
-	uint8_t bits_per_pixel;
-	uint8_t red_mask_pos;
-	uint8_t red_mask_size;
-	uint8_t green_mask_pos;
-	uint8_t green_mask_size;
-	uint8_t blue_mask_pos;
-	uint8_t blue_mask_size;
-	uint8_t reserved_mask_pos;
-	uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO	0x0013
-
-struct lb_gpio {
-	uint32_t port;
-	uint32_t polarity;
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-	uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
-        uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
-	uint32_t tag;
-	uint32_t size;
-
-	uint32_t count;
-	struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT		0x0015
-#define LB_TAG_VBNV		0x0019
-#define LB_TAB_VBOOT_HANDOFF	0x0020
-#define LB_TAB_DMA		0x0022
-#define LB_TAG_RAM_OOPS		0x0023
-#define LB_TAG_MTC		0x002b
-struct lb_range {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t range_start;
-	uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS	0x0016
-#define LB_TAG_CBMEM_CONSOLE	0x0017
-#define LB_TAG_MRC_CACHE	0x0018
-#define LB_TAG_ACPI_GNVS	0x0024
-#define LB_TAG_WIFI_CALIBRATION	0x0027
-struct lb_cbmem_ref {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR	0x0021
-struct lb_x86_rom_mtrr {
-	uint32_t tag;
-	uint32_t size;
-	/* The variable range MTRR index covering the ROM. */
-	uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID		0x0025
-struct lb_board_id {
-	uint32_t tag;
-	uint32_t size;
-	/* Board ID as retrieved from the board revision GPIOs. */
-	uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS	0x0026
-struct mac_address {
-	uint8_t mac_addr[6];
-	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t count;
-	struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE		0x0028
-struct lb_ram_code {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH	0x0029
-struct lb_spi_flash {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t flash_size;
-	uint32_t sector_size;
-	uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
-	uint32_t tag;
-	uint32_t size;
-	/* offsets are relative to start of boot media */
-	uint64_t fmap_offset;
-	uint64_t cbfs_offset;
-	uint64_t cbfs_size;
-	uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO		0x002a
-#define MAX_SERIALNO_LENGTH	32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
-	uint32_t tag;               /* CMOS definitions table type */
-	uint32_t size;               /* size of the entire table */
-	uint32_t header_length;      /* length of header */
-};
-
-/* cmos entry record
-        This record is variable length.  The name field may be
-        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
-        anywhere in the byte, but can not span bytes unless it
-        starts at the beginning of the byte and the length is
-        fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
-	uint32_t tag;                /* entry type */
-	uint32_t size;               /* length of this record */
-	uint32_t bit;                /* starting bit from start of image */
-	uint32_t length;             /* length of field in bits */
-	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
-	uint32_t config_id;          /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
-					       variable length int aligned */
-};
-
-
-/* cmos enumerations record
-        This record is variable length.  The text field may be
-        shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
-	uint32_t tag;		     /* enumeration type */
-	uint32_t size; 		     /* length of this record */
-	uint32_t config_id;          /* a number identifying the config id */
-	uint32_t value;              /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
-	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
-						variable length int aligned */
-};
-
-/* cmos defaults record
-        This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
-	uint32_t tag;                /* default type */
-	uint32_t size;               /* length of this record */
-	uint32_t name_length;        /* length of the following name field */
-	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
-	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct	cmos_checksum {
-	uint32_t tag;
-	uint32_t size;
-	/* In practice everything is byte aligned, but things are measured
-	 * in bits to be consistent.
-	 */
-	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
-	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
-	uint32_t location;	/* First bit of the checksum (byte aligned) */
-	uint32_t type;		/* Checksum algorithm that is used */
-#define CHECKSUM_NONE	0
-#define CHECKSUM_PCBIOS	1
-};
-
+#include <commonlib/coreboot_tables.h>
 /* function prototypes for building the coreboot table */
 
 unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
 #ifndef _BOOT_DEVICE_H_
 #define _BOOT_DEVICE_H_
 
-#include <region.h>
+#include <commonlib/region.h>
 
 /* Return the region_device for the read-only boot device. */
 const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
 #include <program_loading.h>
-#include <region.h>
 
 /*
  * CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
-    algorithms that coreboot knows about for stages and
-    payloads.  Of course, other CBFS users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE      0x10
-#define CBFS_TYPE_PAYLOAD    0x20
-#define CBFS_TYPE_OPTIONROM  0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW        0x50
-#define CBFS_TYPE_VSA        0x51
-#define CBFS_TYPE_MBI        0x52
-#define CBFS_TYPE_MICROCODE  0x53
-#define CBFS_TYPE_FSP        0x60
-#define CBFS_TYPE_MRC        0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD          0xab
-#define CBFS_TYPE_MRC_CACHE    0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
-	uint32_t magic;
-	uint32_t version;
-	uint32_t romsize;
-	uint32_t bootblocksize;
-	uint32_t align; /* fixed to 64 bytes */
-	uint32_t offset;
-	uint32_t architecture;
-	uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86      0x00000001
-#define CBFS_ARCHITECTURE_ARM      0x00000010
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	uint32_t len;
-	uint32_t type;
-	uint32_t checksum;
-	uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	uint32_t compression;  /** Compression type */
-	uint64_t entry;  /** entry point */
-	uint64_t load;   /** Where to load in memory */
-	uint32_t len;          /** length of data to load */
-	uint32_t memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	uint32_t type;
-	uint32_t compression;
-	uint32_t offset;
-	uint64_t load_addr;
-	uint32_t len;
-	uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	uint32_t compression;
-	uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
 #include <rules.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME	0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
-#define CBMEM_ID_CBTABLE	0x43425442
-#define CBMEM_ID_CONSOLE	0x434f4e53
-#define CBMEM_ID_COVERAGE	0x47434f56
-#define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
-#define CBMEM_ID_ELOG		0x454c4f47
-#define CBMEM_ID_FREESPACE	0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME	0x52505346
-#define CBMEM_ID_GDT		0x4c474454
-#define CBMEM_ID_HOB_POINTER	0x484f4221
-#define CBMEM_ID_IGD_OPREGION	0x4f444749
-#define CBMEM_ID_IMD_ROOT	0xff4017ff
-#define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MEMINFO	0x494D454D
-#define CBMEM_ID_MPTABLE	0x534d5054
-#define CBMEM_ID_MRCDATA	0x4d524344
-#define CBMEM_ID_MTC		0xcb31d31c
-#define CBMEM_ID_NONE		0x00000000
-#define CBMEM_ID_PIRQ		0x49525154
-#define CBMEM_ID_POWER_STATE	0x50535454
-#define CBMEM_ID_RAM_OOPS	0x05430095
-#define CBMEM_ID_RAMSTAGE	0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE	0x9a3ca54e
-#define CBMEM_ID_REFCODE	0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE	0x4efc0de5
-#define CBMEM_ID_RESUME		0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH	0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO	0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
-#define CBMEM_ID_SPINTABLE	0x59175917
-#define CBMEM_ID_STAGEx_META	0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE	0x57a9e100
-#define CBMEM_ID_TCPA_LOG	0x54435041
-#define CBMEM_ID_TIMESTAMP	0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF	0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE				 \
-	{ CBMEM_ID_ACPI,		"ACPI       " }, \
-	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
-	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
-	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
-	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
-	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \
-	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
-	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
-	{ CBMEM_ID_ELOG,		"ELOG       " }, \
-	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
-	{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
-	{ CBMEM_ID_FSP_RUNTIME,		"FSP RUNTIME" }, \
-	{ CBMEM_ID_GDT,			"GDT        " }, \
-	{ CBMEM_ID_IMD_ROOT,		"IMD ROOT   " }, \
-	{ CBMEM_ID_IMD_SMALL,		"IMD SMALL  " }, \
-	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
-	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
-	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_MTC,			"MTC        " }, \
-	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
-	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
-	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \
-	{ CBMEM_ID_RAMSTAGE_CACHE,	"RAMSTAGE $ " }, \
-	{ CBMEM_ID_RAMSTAGE,		"RAMSTAGE   " }, \
-	{ CBMEM_ID_REFCODE_CACHE,	"REFCODE $  " }, \
-	{ CBMEM_ID_REFCODE,		"REFCODE    " }, \
-	{ CBMEM_ID_RESUME,		"ACPI RESUME" }, \
-	{ CBMEM_ID_RESUME_SCRATCH,	"ACPISCRATCH" }, \
-	{ CBMEM_ID_ROMSTAGE_INFO,	"ROMSTAGE   " }, \
-	{ CBMEM_ID_ROMSTAGE_RAM_STACK,	"ROMSTG STCK" }, \
-	{ CBMEM_ID_ROOT,		"CBMEM ROOT " }, \
-	{ CBMEM_ID_SMBIOS,		"SMBIOS     " }, \
-	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
-	{ CBMEM_ID_SPINTABLE,		"SPIN TABLE " }, \
-	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
-	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
-	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
-	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
-	{ CBMEM_ID_WIFI_CALIBRATION,	"WIFI CLBR  " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <rules.h>
 #include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef __ROMCC__
 struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
 
 #include <console/console.h>
 #include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 /* While in romstage, console loglevel is built-time constant.
  * With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG      0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT      1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT       2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR        3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING    4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE     5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO       6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG      7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW       8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER	9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
 #ifndef _FMAP_H_
 #define _FMAP_H_
 
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
 
 /* Locate the fmap directory. Return 0 on success, < 0 on error. */
 int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *    * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE		"__FMAP__"
-#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
-#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
-#define FMAP_STRLEN		32	/* maximum length for strings, */
-					/* including null-terminator */
-
-enum fmap_flags {
-	FMAP_AREA_STATIC	= 1 << 0,
-	FMAP_AREA_COMPRESSED	= 1 << 1,
-	FMAP_AREA_RO		= 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
-	uint32_t offset;                /* offset relative to base */
-	uint32_t size;                  /* size in bytes */
-	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
-	uint16_t flags;                 /* flags for this area */
-}  __attribute__((packed));
-
-struct fmap {
-	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
-	uint8_t  ver_major;		/* major version */
-	uint8_t  ver_minor;		/* minor version */
-	uint64_t base;			/* address of the firmware binary */
-	uint32_t size;			/* size of firmware binary in bytes */
-	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
-	uint16_t nareas;		/* number of areas described by
-					   fmap_areas[] below */
-	struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif	/* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
-	uint8_t *buf;
-	size_t size;
-	uint8_t *last_alloc;
-	size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_)	\
-	{				\
-		.buf = (buf_),		\
-		.size = (size_),	\
-		.last_alloc = NULL,	\
-		.free_offset = 0,	\
-	}
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
-	mp->last_alloc = NULL;
-	mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
-	mp->buf = buf;
-	mp->size = sz;
-	mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device.  Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size);
-
-
-/****************************************
- *  Implementation of a region device   *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
-	void *(*mmap)(const struct region_device *, size_t, size_t);
-	int (*munmap)(const struct region_device *, void *);
-	ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
-	size_t offset;
-	size_t size;
-};
-
-struct region_device {
-	const struct region_device *root;
-	const struct region_device_ops *ops;
-	struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_)		\
-	{						\
-		.root = NULL,				\
-		.ops = (ops_),				\
-		.region = {				\
-			.offset = (offset_),		\
-			.size = (size_),		\
-		},					\
-	}
-
-static inline size_t region_offset(const struct region *r)
-{
-	return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
-	return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
-	return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
-	return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
-	return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
-	char *base;
-	struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_)				\
-	{								\
-		.base = (void *)(base_),				\
-		.rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)),	\
-	}
-
-struct mmap_helper_region_device {
-	struct mem_pool pool;
-	struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
-	{								\
-		.rdev = REGION_DEV_INIT((ops_), (offset_), (size_)),	\
-	}
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values.  */
-struct rmodule_header {
-	uint16_t magic;
-	uint8_t  version;
-	uint8_t  type;
-	/* The payload represents the program's loadable code and data. */
-	uint32_t payload_begin_offset;
-	uint32_t payload_end_offset;
-	/* Begin and of relocation information about the program module. */
-	uint32_t relocations_begin_offset;
-	uint32_t relocations_end_offset;
-	/* The starting address of the linked program. This address is vital
-	 * for determining relocation offsets as the relocation info and other
-	 * symbols (bss, entry point) need this value as a basis to calculate
-	 * the offsets.
-	 */
-	uint32_t module_link_start_address;
-	/* The module_program_size is the size of memory used while running
-	 * the program. The program is assumed to consume a contiguous amount
-	 * of memory. */
-	uint32_t module_program_size;
-	/* This is program's execution entry point. */
-	uint32_t module_entry_point;
-	/* Optional parameter structure that can be used to pass data into
-	 * the module. */
-	uint32_t parameters_begin;
-	uint32_t parameters_end;
-	/* BSS section information so the loader can clear the bss. */
-	uint32_t bss_begin;
-	uint32_t bss_end;
-	/* Add some room for growth. */
-	uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
 
 enum {
 	RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
 #ifndef STDDEF_H
 #define STDDEF_H
 
+#include <commonlib/helpers.h>
+
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
 #define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
-	offsetof(struct structure, member) == offset, \
-	"`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr:    the pointer to the member.
- * @param type:   the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
 
 #include <stddef.h>
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a)           ALIGN((x),(a))
-#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-
 #define min(a,b) MIN((a),(b))
 #define max(a,b) MAX((a),(b))
 
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
 #ifndef __TIMESTAMP_H__
 #define __TIMESTAMP_H__
 
-#include <stdint.h>
-
-struct timestamp_entry {
-	uint32_t	entry_id;
-	uint64_t	entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
-	uint64_t	base_time;
-	uint16_t	max_entries;
-	uint16_t	tick_freq_mhz;
-	uint32_t	num_entries;
-	struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
-	TS_START_ROMSTAGE = 1,
-	TS_BEFORE_INITRAM = 2,
-	TS_AFTER_INITRAM = 3,
-	TS_END_ROMSTAGE = 4,
-	TS_START_VBOOT = 5,
-	TS_END_VBOOT = 6,
-	TS_START_COPYRAM = 8,
-	TS_END_COPYRAM = 9,
-	TS_START_RAMSTAGE = 10,
-	TS_START_BOOTBLOCK = 11,
-	TS_END_BOOTBLOCK = 12,
-	TS_START_COPYROM = 13,
-	TS_END_COPYROM = 14,
-	TS_START_ULZMA = 15,
-	TS_END_ULZMA = 16,
-	TS_DEVICE_ENUMERATE = 30,
-	TS_DEVICE_CONFIGURE = 40,
-	TS_DEVICE_ENABLE = 50,
-	TS_DEVICE_INITIALIZE = 60,
-	TS_DEVICE_DONE = 70,
-	TS_CBMEM_POST = 75,
-	TS_WRITE_TABLES = 80,
-	TS_LOAD_PAYLOAD = 90,
-	TS_ACPI_WAKE_JUMP = 98,
-	TS_SELFBOOT_JUMP = 99,
-
-	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
-	TS_START_COPYVER = 501,
-	TS_END_COPYVER = 502,
-	TS_START_TPMINIT = 503,
-	TS_END_TPMINIT = 504,
-	TS_START_VERIFY_SLOT = 505,
-	TS_END_VERIFY_SLOT = 506,
-	TS_START_HASH_BODY = 507,
-	TS_DONE_LOADING = 508,
-	TS_DONE_HASHING = 509,
-	TS_END_HASH_BODY = 510,
-
-	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
-	TS_FSP_MEMORY_INIT_START = 950,
-	TS_FSP_MEMORY_INIT_END = 951,
-	TS_FSP_TEMP_RAM_EXIT_START = 952,
-	TS_FSP_TEMP_RAM_EXIT_END = 953,
-	TS_FSP_SILICON_INIT_START = 954,
-	TS_FSP_SILICON_INIT_END = 955,
-	TS_FSP_BEFORE_ENUMERATE = 956,
-	TS_FSP_AFTER_ENUMERATE = 957,
-	TS_FSP_BEFORE_FINALIZE = 958,
-	TS_FSP_AFTER_FINALIZE = 959,
-
-	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
 
 #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
 /*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 bootblock-$(CONFIG_I2C_TPM) += delay.c
 bootblock-y += memchr.c
 bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
 bootblock-y += boot_device.c
 bootblock-y += fmap.c
 
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
 verstage-y += libgcc.c
 verstage-y += memcmp.c
 verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
 
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
 
 romstage-y += assets.c
 romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
 endif
 
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
 
-romstage-y += region.c
-ramstage-y += region.c
 romstage-y += boot_device.c
 ramstage-y += boot_device.c
 
-smm-y += region.c
 smm-y += boot_device.c
 smm-y += fmap.c
 smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* This function is marked as weak to allow a particular platform to
  * override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
 #include <stddef.h>
 #include <string.h>
 
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
-	void *p;
-
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
-
-	/* Determine if any space available. */
-	if ((mp->size - mp->free_offset) < sz)
-		return NULL;
-
-	p = &mp->buf[mp->free_offset];
-
-	mp->free_offset += sz;
-	mp->last_alloc = p;
-
-	return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
-	/* Determine if p was the most recent allocation. */
-	if (p == NULL || mp->last_alloc != p)
-		return;
-
-	mp->free_offset = mp->last_alloc - mp->buf;
-	/* No way to track allocation before this one. */
-	mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
-	return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
-	if (region_offset(c) < region_offset(p))
-		return 0;
-
-	if (region_sz(c) > region_sz(p))
-		return 0;
-
-	if (region_end(c) > region_end(p))
-		return 0;
-
-	return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
-	inner->offset += region_offset(outer);
-	return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
-	if (rdev->root == NULL)
-		return rdev;
-	return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return NULL;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	const struct region_device *rdev;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
-			size_t size)
-{
-	const struct region_device *rdev;
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&rd->region, &req))
-		return -1;
-
-	rdev = rdev_root(rd);
-
-	return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
-		size_t offset, size_t size)
-{
-	struct region req = {
-		.offset = offset,
-		.size = size,
-	};
-
-	if (!normalize_and_ok(&parent->region, &req))
-		return -1;
-
-	/* Keep track of root region device. Note the offsets are relative
-	 * to the root device. */
-	child->root = rdev_root(parent);
-	child->ops = NULL;
-	child->region.offset = req.offset;
-	child->region.size = req.size;
-
-	return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
-				size_t size)
-{
-	memset(mdev, 0, sizeof(*mdev));
-	mdev->base = base;
-	mdev->rdev.ops = &mem_rdev_ops;
-	mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
-	return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
-				size_t offset, size_t size)
-{
-	const struct mem_region_device *mdev;
-
-	mdev = container_of(rd, typeof(*mdev), rdev);
-
-	memcpy(b, &mdev->base[offset], size);
-
-	return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
-	.mmap = mdev_mmap,
-	.munmap = mdev_munmap,
-	.readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
-				void *cache, size_t cache_size)
-{
-	mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
-				size_t size)
-{
-	struct mmap_helper_region_device *mdev;
-	void *mapping;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mapping = mem_pool_alloc(&mdev->pool, size);
-
-	if (mapping == NULL)
-		return NULL;
-
-	if (rd->ops->readat(rd, mapping, offset, size) != size) {
-		mem_pool_free(&mdev->pool, mapping);
-		return NULL;
-	}
-
-	return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
-	struct mmap_helper_region_device *mdev;
-
-	mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
-	mem_pool_free(&mdev->pool, mapping);
-
-	return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
 #include <spd.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <commonlib/region.h>
 #include <console/console.h>
 #include <device/i2c.h>
 #include <drivers/maxim/max77802/max77802.h>
 #include <program_loading.h>
-#include <region.h>
 #include <soc/clk.h>
 #include <soc/cpu.h>
 #include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
 #include <lib.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
 #define ME_DELAY		10	/* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
 
 #include <cpu/amd/common/cbtypes.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #ifdef NULL
 #undef NULL
 #endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
 #include "sb_cimx.h"
 #include "sb700_cfg.h"                /*sb700_cimx_config*/
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
 #include "SbPlatform.h"
 #include "sb_cimx.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 #include "smbus.h"
 
 /**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
 
 #include <assert.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
 #include "amdlib.h"
 #include "cbfs.h"
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 // TODO Add a kconfig option to name the AGESA ROM file in CBFS
 #define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
 #include <assert.h>
 #include <config.h>
 #include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
 
 #ifndef NULL
   #define NULL              ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
 
 AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
 CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
 #define VBOOT_COMMON_H
 
 #include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
 
 /* The FW areas consist of multiple components. At the beginning of
  * each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 2a3dedf..0938ea9 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -50,6 +50,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
 
 #include "elfparsing.h"
 #include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
 
 /*
  * Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
 CC     ?= $(CROSS_COMPILE)gcc
 CFLAGS ?= -O2
 CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
 
 OBJS = $(PROGRAM).o
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
 #include <sys/mman.h>
 #include <libgen.h>
 #include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
 
 #ifdef __OpenBSD__
 #include <sys/param.h>
@@ -42,18 +45,12 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
 
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
 typedef uint64_t u64;
 
-#include "cbmem_id.h"
-#include "timestamp.h"
-
 #define CBMEM_VERSION "1.1"
 
 /* verbose output? */


From gerrit at coreboot.org  Mon Sep 21 20:30:41 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 21 Sep 2015 20:30:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: commonlib: add
	endian related accessor functions
References: <If44c4d489f0dab86a73b73580c039e364c7e517d+0@gerrit.coreboot.org>
Message-ID: <If44c4d489f0dab86a73b73580c039e364c7e517d+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11677

-gerrit

commit 2094eeef838545e46b76b32497a0ef5cde380fd9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 11:24:08 2015 -0500

    commonlib: add endian related accessor functions
    
    This commit adds read/write functions for both big and
    little endian interpretations. Additionally there are
    variants that allow an offset to be provided into the
    source buffer.
    
    BUG=None
    TEST=Wrote test harness for functions.  Also booted ARM QEMU
         through end of payload.
    
    Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/commonlib/include/commonlib/endian.h | 261 +++++++++++++++++++++++++++++++
 1 file changed, 261 insertions(+)

diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h
new file mode 100644
index 0000000..bcd3b39
--- /dev/null
+++ b/src/commonlib/include/commonlib/endian.h
@@ -0,0 +1,261 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _COMMONLIB_ENDIAN_H_
+#define _COMMONLIB_ENDIAN_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* Endian agnostic functions working on single byte. */
+
+static inline uint8_t read_ble8(const void *src)
+{
+	const uint8_t *s = src;
+	return *s;
+}
+
+static inline uint8_t read_at_ble8(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_ble8(s);
+}
+
+static inline void write_ble8(void *dest, uint8_t val)
+{
+	*(uint8_t *)dest = val;
+}
+
+static inline void write_at_ble8(void *dest, uint8_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_ble8(d, val);
+}
+
+/* Big Endian functions. */
+
+static inline uint8_t read_be8(const void *src)
+{
+	return read_ble8(src);
+}
+
+static inline uint8_t read_at_be8(const void *src, size_t offset)
+{
+	return read_at_ble8(src, offset);
+}
+
+static inline void write_be8(void *dest, uint8_t val)
+{
+	write_ble8(dest, val);
+}
+
+static inline void write_at_be8(void *dest, uint8_t val, size_t offset)
+{
+	write_at_ble8(dest, val, offset);
+}
+
+static inline uint16_t read_be16(const void *src)
+{
+	const uint8_t *s = src;
+	return (((uint16_t)s[0]) << 8) | (((uint16_t)s[1]) << 0);
+}
+
+static inline uint16_t read_at_be16(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_be16(s);
+}
+
+static inline void write_be16(void *dest, uint16_t val)
+{
+	write_be8(dest, val >> 8);
+	write_at_be8(dest, val >> 0, sizeof(uint8_t));
+}
+
+static inline void write_at_be16(void *dest, uint16_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_be16(d, val);
+}
+
+static inline uint32_t read_be32(const void *src)
+{
+	const uint8_t *s = src;
+	return (((uint32_t)s[0]) << 24) | (((uint32_t)s[1]) << 16) |
+		(((uint32_t)s[2]) << 8) | (((uint32_t)s[3]) << 0);
+}
+
+static inline uint32_t read_at_be32(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_be32(s);
+}
+
+static inline void write_be32(void *dest, uint32_t val)
+{
+	write_be16(dest, val >> 16);
+	write_at_be16(dest, val >> 0, sizeof(uint16_t));
+}
+
+static inline void write_at_be32(void *dest, uint32_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_be32(d, val);
+}
+
+static inline uint64_t read_be64(const void *src)
+{
+	uint64_t val;
+	val = read_be32(src);
+	val <<= 32;
+	val |= read_at_be32(src, sizeof(uint32_t));
+	return val;
+}
+
+static inline uint64_t read_at_be64(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_be64(s);
+}
+
+static inline void write_be64(void *dest, uint64_t val)
+{
+	write_be32(dest, val >> 32);
+	write_at_be32(dest, val >> 0, sizeof(uint32_t));
+}
+
+static inline void write_at_be64(void *dest, uint64_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_be64(d, val);
+}
+
+/* Little Endian functions. */
+
+static inline uint8_t read_le8(const void *src)
+{
+	return read_ble8(src);
+}
+
+static inline uint8_t read_at_le8(const void *src, size_t offset)
+{
+	return read_at_ble8(src, offset);
+}
+
+static inline void write_le8(void *dest, uint8_t val)
+{
+	write_ble8(dest, val);
+}
+
+static inline void write_at_le8(void *dest, uint8_t val, size_t offset)
+{
+	write_at_ble8(dest, val, offset);
+}
+
+static inline uint16_t read_le16(const void *src)
+{
+	const uint8_t *s = src;
+	return (((uint16_t)s[1]) << 8) | (((uint16_t)s[0]) << 0);
+}
+
+static inline uint16_t read_at_le16(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_le16(s);
+}
+
+static inline void write_le16(void *dest, uint16_t val)
+{
+	write_le8(dest, val >> 0);
+	write_at_le8(dest, val >> 8, sizeof(uint8_t));
+}
+
+static inline void write_at_le16(void *dest, uint16_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_le16(d, val);
+}
+
+static inline uint32_t read_le32(const void *src)
+{
+	const uint8_t *s = src;
+	return (((uint32_t)s[3]) << 24) | (((uint32_t)s[2]) << 16) |
+		(((uint32_t)s[1]) << 8) | (((uint32_t)s[0]) << 0);
+}
+
+static inline uint32_t read_at_le32(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_le32(s);
+}
+
+static inline void write_le32(void *dest, uint32_t val)
+{
+	write_le16(dest, val >> 0);
+	write_at_le16(dest, val >> 16, sizeof(uint16_t));
+}
+
+static inline void write_at_le32(void *dest, uint32_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_le32(d, val);
+}
+
+static inline uint64_t read_le64(const void *src)
+{
+	uint64_t val;
+	val = read_at_le32(src, sizeof(uint32_t));
+	val <<= 32;
+	val |= read_le32(src);
+	return val;
+}
+
+static inline uint64_t read_at_le64(const void *src, size_t offset)
+{
+	const uint8_t *s = src;
+	s += offset;
+	return read_le64(s);
+}
+
+static inline void write_le64(void *dest, uint64_t val)
+{
+	write_le32(dest, val >> 0);
+	write_at_le32(dest, val >> 32, sizeof(uint32_t));
+}
+
+static inline void write_at_le64(void *dest, uint64_t val, size_t offset)
+{
+	uint8_t *d = dest;
+	d += offset;
+	write_le64(d, val);
+}
+
+#endif


From gerrit at coreboot.org  Tue Sep 22 14:40:17 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 22 Sep 2015 14:40:17 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: prefer
	fmap data over cbfs master header if it exists
References: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+0@gerrit.coreboot.org>
Message-ID: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11629

-gerrit

commit 1994fdd136d169980652c0e1c259549ea7a3deca
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 18:34:39 2015 +0200

    cbfstool: prefer fmap data over cbfs master header if it exists
    
    Up to now, if both fmap and a master header existed, the master header
    was used. Now, use the master header only if no fmap is found.
    
    Change-Id: Iafbf2c9dc325597e23a9780b495549b5d912e9ad
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfs_image.c       | 12 +++++++-----
 util/cbfstool/cbfstool.c         |  9 +--------
 util/cbfstool/partitioned_file.c | 15 +--------------
 util/cbfstool/partitioned_file.h | 24 +++++-------------------
 4 files changed, 14 insertions(+), 46 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 55f8084..24ab0c4 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -343,20 +343,22 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in,
 	buffer_clone(&out->buffer, in);
 	out->has_header = false;
 
+	if (cbfs_is_valid_cbfs(out)) {
+		return 0;
+	}
+
 	void *header_loc = cbfs_find_header(in->data, in->size, offset);
 	if (header_loc) {
 		cbfs_get_header(&out->header, header_loc);
 		out->has_header = true;
 		cbfs_fix_legacy_size(out, header_loc);
+		return 0;
 	} else if (offset != ~0u) {
 		ERROR("The -H switch is only valid on legacy images having CBFS master headers.\n");
 		return 1;
-	} else if (!cbfs_is_valid_cbfs(out)) {
-		ERROR("Selected image region is not a valid CBFS.\n");
-		return 1;
 	}
-
-	return 0;
+	ERROR("Selected image region is not a valid CBFS.\n");
+	return 1;
 }
 
 int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset,
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index bf589a5..35747d3 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -881,12 +881,6 @@ static int cbfs_copy(void)
 	return cbfs_copy_instance(&image, param.copyoffset, param.size);
 }
 
-static bool cbfs_is_legacy_format(struct buffer *buffer)
-{
-	// Legacy CBFSes are those containing the deprecated CBFS master header.
-	return cbfs_find_header(buffer->data, buffer->size, -1);
-}
-
 static const struct command commands[] = {
 	{"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true},
 	{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
@@ -1250,8 +1244,7 @@ int main(int argc, char **argv)
 			}
 		} else {
 			param.image_file =
-				partitioned_file_reopen(image_name,
-							cbfs_is_legacy_format);
+				partitioned_file_reopen(image_name);
 		}
 		if (!param.image_file)
 			return 1;
diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c
index 9d67832..041ef11 100644
--- a/util/cbfstool/partitioned_file.c
+++ b/util/cbfstool/partitioned_file.c
@@ -165,8 +165,7 @@ partitioned_file_t *partitioned_file_create(const char *filename,
 	return file;
 }
 
-partitioned_file_t *partitioned_file_reopen(const char *filename,
-				partitioned_file_flat_decider_t flat_override)
+partitioned_file_t *partitioned_file_reopen(const char *filename)
 {
 	assert(filename);
 
@@ -174,11 +173,6 @@ partitioned_file_t *partitioned_file_reopen(const char *filename,
 	if (!file)
 		return NULL;
 
-	if (flat_override && flat_override(&file->buffer)) {
-		INFO("Opening image as a flat file in response to explicit request\n");
-		return file;
-	}
-
 	long fmap_region_offset = fmap_find((const uint8_t *)file->buffer.data,
 							file->buffer.size);
 	if (fmap_region_offset < 0) {
@@ -365,10 +359,3 @@ static bool select_parents_of(const struct fmap_area *parent, const void *arg)
 }
 const partitioned_file_fmap_selector_t partitioned_file_fmap_select_parents_of =
 							select_parents_of;
-
-static bool open_as_flat(unused struct buffer *buffer)
-{
-	return true;
-}
-const partitioned_file_flat_decider_t partitioned_file_open_as_flat =
-								open_as_flat;
diff --git a/util/cbfstool/partitioned_file.h b/util/cbfstool/partitioned_file.h
index 4583316..3698a19 100644
--- a/util/cbfstool/partitioned_file.h
+++ b/util/cbfstool/partitioned_file.h
@@ -28,15 +28,6 @@
 
 typedef struct partitioned_file partitioned_file_t;
 
-/** @return Whether the specific existing file should be opened in flat mode. */
-typedef bool (*partitioned_file_flat_decider_t)(struct buffer *buffer);
-
-/** Pass to partitioned_file_reopen() to force opening as a partitioned file. */
-#define partitioned_file_open_as_partitioned NULL
-
-/** Pass to partitioned_file_reopen() to force opening as a flat file. */
-extern const partitioned_file_flat_decider_t partitioned_file_open_as_flat;
-
 /**
  * Create a new filesystem-backed flat buffer.
  * This backwards-compatibility function creates a new in-memory buffer and
@@ -76,22 +67,17 @@ partitioned_file_t *partitioned_file_create(const char *filename,
 
 /**
  * Read a file back in from the disk.
- * An in-memory buffer is created and populated with the file's contents. If
- * flat_override is NULL and the image contains an FMAP, it will be opened as a
- * full partitioned file; otherwise, it will be opened as a flat file as if it
- * had been created by partitioned_file_create_flat(). This selection behavior
- * is extensible: if a flat_override function is provided, it is invoked before
- * searching for an FMAP, and has the option of explicitly instructing the
- * module to open the image as a flat file based on its contents.
+ * An in-memory buffer is created and populated with the file's
+ * contents. If the image contains an FMAP, it will be opened as a
+ * full partitioned file; otherwise, it will be opened as a flat file as
+ * if it had been created by partitioned_file_create_flat().
  * The partitioned_file_t returned from this function is separately owned by the
  * caller, and must later be passed to partitioned_file_close();
  *
  * @param filename      Name of the file to read in
- * @param flat_override Callback that can decide to open it as flat, or NULL
  * @return              Caller-owned partitioned file, or NULL on error
  */
-partitioned_file_t *partitioned_file_reopen(const char *filename,
-				partitioned_file_flat_decider_t flat_override);
+partitioned_file_t *partitioned_file_reopen(const char *filename);
 
 /**
  * Write a buffer's contents to its original region within a segmented file.


From gerrit at coreboot.org  Tue Sep 22 14:40:23 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 22 Sep 2015 14:40:23 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: have
	update-fit always work from CBFS
References: <Ie139215b73e01027bc0586701361e9a0afa9150e+0@gerrit.coreboot.org>
Message-ID: <Ie139215b73e01027bc0586701361e9a0afa9150e+3@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11691

-gerrit

commit 0f2ba029b643d53f7609c50bcbfd69e5350482ca
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Sat Sep 19 14:04:45 2015 +0200

    cbfstool: have update-fit always work from CBFS
    
    On x86, the bootblock can (and will) become part of the regular file
    system, so there's no distinct fixed-size region for the bootblock
    there.
    
    Change-Id: Ie139215b73e01027bc0586701361e9a0afa9150e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 util/cbfstool/cbfstool.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 5194061..bf589a5 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -838,16 +838,9 @@ static int cbfs_update_fit(void)
 		return 1;
 	}
 
-	// Decide which region to read/write the FIT table from/to.
 	struct buffer bootblock;
-	if (partitioned_file_is_partitioned(param.image_file)) {
-		if (!partitioned_file_read_region(&bootblock, param.image_file,
-							SECTION_WITH_FIT_TABLE))
-			return 1;
-	} else {
-		// In legacy images, the bootblock is part of the CBFS.
-		buffer_clone(&bootblock, param.image_region);
-	}
+	// The bootblock is part of the CBFS on x86
+	buffer_clone(&bootblock, param.image_region);
 
 	struct cbfs_image image;
 	if (cbfs_image_from_buffer(&image, param.image_region,


From gerrit at coreboot.org  Tue Sep 22 14:40:31 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 22 Sep 2015 14:40:31 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Switch to fmap
	based firmware layout
References: <Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c+0@gerrit.coreboot.org>
Message-ID: <Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c+3@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11692

-gerrit

commit 8b34927b806681c30d2dedc4dfa19774730db116
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Sep 16 18:10:52 2015 +0200

    Switch to fmap based firmware layout
    
    We still add a master header for compatibility purposes, and the default
    layouts don't cover anything non-coreboot (eg. IFD regions) yet.
    
    The default layouts can be overridden by specifying an fmd file, from
    which the fmap is generated.
    
    Future work:
    - map IFD regions to fmap regions
    - non-x86: build minimalistic trampolines that jump into the first cbfs
      file, so the bootblock can be part of CBFS instead of reserving a
      whole 64K for it.
    - teach coreboot's cbfs code to work without the master header
    - teach coreboot's cbfs code to work on different fmap regions
    
    Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 Makefile.inc                  | 75 +++++++++++++++++++++++++++++++++++++++++--
 util/cbfstool/default-x86.fmd | 15 +++++++++
 util/cbfstool/default.fmd     | 17 ++++++++++
 3 files changed, 104 insertions(+), 3 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 46d6eb2..606d081 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -566,10 +566,79 @@ prebuild-files = \
 	       $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&))
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
+ifeq ($(CONFIG_ARCH_X86),y)
+DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd
+# entire flash
+FMAP_ROM_BASE := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE))
+FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
+# entire "BIOS" region (everything directly of concern to the host system)
+# relative to ROM_BASE
+FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE))
+FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
+# position and size of flashmap, relative to BIOS_BASE
+FMAP_FMAP_BASE := 0
+FMAP_FMAP_SIZE := 0x100
+# position and size of CBFS, relative to BIOS_BASE
+FMAP_CBFS_BASE := $(FMAP_FMAP_SIZE)
+FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_FMAP_SIZE))
+else
+DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
+# entire flash
+FMAP_ROM_BASE := 0
+FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
+# entire "BIOS" region (everything directly of concern to the host system)
+# relative to ROM_BASE
+FMAP_BIOS_BASE := 0
+FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
+# position and size of flashmap, relative to BIOS_BASE
+FMAP_FMAP_BASE := 0x10000
+FMAP_FMAP_SIZE := 0x100
+# position and size of CBFS, relative to BIOS_BASE
+FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
+FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
+endif
+
 $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
-	$(CBFSTOOL) $@.tmp create \
-	-B $(objcbfs)/bootblock.bin \
-	$(CBFSTOOL_PRE1_OPTS)
+ifeq ($(CONFIG_FMDFILE),)
+	sed -e "s,##ROM_BASE##,$(FMAP_ROM_BASE)," \
+	    -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \
+	    -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \
+	    -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \
+	    -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \
+	    -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \
+	    -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
+	    -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
+		$(DEFAULT_FLASHMAP) > $@.tmp.fmd
+	$(FMAPTOOL) $@.tmp.fmd $@.tmp.fmap
+else
+	$(FMAPTOOL) $(CONFIG_FMDFILE) $@.tmp.fmap
+endif
+	$(CBFSTOOL) $@.tmp create -M $@.tmp.fmap
+ifeq ($(CONFIG_ARCH_X86),y)
+	$(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock \
+		-t bootblock \
+		-b -$(call file-size,$(objcbfs)/bootblock.bin)
+else
+	# don't add bootblock to cbfs yet, it's just a waste of space
+	true $(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock \
+		-t bootblock \
+		-b 0
+	$(CBFSTOOL) $@.tmp write -u \
+		-r BOOTBLOCK \
+		-f $(objcbfs)/bootblock.bin
+	printf "ptr_" > $@.tmp.2 # 4 characters
+	$(CBFSTOOL) $@.tmp add \
+		-f $@.tmp.2 \
+		-n "header pointer" \
+		-t "cbfs header" \
+		-b -4
+	rm -f $@.tmp.2
+endif
+	$(CBFSTOOL) $@.tmp add-master-header
 	$(prebuild-files) true
 	mv $@.tmp $@
 else
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
new file mode 100644
index 0000000..d7d0326
--- /dev/null
+++ b/util/cbfstool/default-x86.fmd
@@ -0,0 +1,15 @@
+# layout for firmware residing at top of 4GB address space
+# 4GB - ROM_SIZE:	start of flash
+# 4GB - CBFS_SIZE:	start of fmap
+#  + 0x100:		start of CBFS
+# 4GB			end of flash
+
+# ##CBFS_SIZE## differs from the CBFS_SIZE specified above in that it already
+# excludes the fmap size. CONFIG_CBFS_SIZE contains it.
+
+FLASH@##ROM_BASE## ##ROM_SIZE## {
+	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
+		FMAP@##FMAP_BASE## ##FMAP_SIZE##
+		COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
+	}
+}
diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd
new file mode 100644
index 0000000..21617d5
--- /dev/null
+++ b/util/cbfstool/default.fmd
@@ -0,0 +1,17 @@
+# layout for firmware when flash address space matches used address layout
+# 0:			start of flash, start of bootblock region
+# 0x10000:		start of fmap
+# 0x10100:		start of cbfs
+# CBFS_SIZE		end of fmap, end of used flash space
+# ROM_SIZE		end of flash
+
+# ##CBFS_SIZE## differs from the CBFS_SIZE specified above in that it already
+# excludes the fmap size. CONFIG_CBFS_SIZE contains it.
+
+FLASH@##ROM_BASE## ##ROM_SIZE## {
+	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
+		BOOTBLOCK 64K
+		FMAP@##FMAP_BASE## ##FMAP_SIZE##
+		COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
+	}
+}


From gerrit at coreboot.org  Tue Sep 22 15:11:37 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 22 Sep 2015 15:11:37 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: linking: link
	bootblock.elf with .data and .bss sections again
References: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+0@gerrit.coreboot.org>
Message-ID: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+6@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11680

-gerrit

commit 8eecebdc51101100b6a090f65ea9065cdacd672e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 17:02:53 2015 -0500

    linking: link bootblock.elf with .data and .bss sections again
    
    Currently coreboot expects the loader to clear the bss section
    for all stages. i.e. stages don't clear their own bss. On ARM
    SoCs the BootROM would be responsible for this. To do that
    one needs to include the bss section data (all zeros) in the
    bootblock.bin file. This was previously being attempted by
    keeping the .bss info in the .data section because objcopy
    happened zero out non-file allocated data section data.
    
    Instead go back to linking bootblock with the bss section
    but mark the bss section as loadable allocatable data. That
    way it will be included in the binary properly when objcopy
    -O binary is emplyed. Also do the same for the data section
    in the case of no non-zero object values are in the data
    section.
    
    Without this change the trick of including .bss in .data
    was not working when there wasn't a non-zero value object
    in the data section.
    
    BUG=None
    BRANCH=None
    TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
         the cleared bss.
    
    Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc                            | 17 +++++++++++++----
 src/lib/program.ld                      |  7 -------
 src/soc/broadcom/cygnus/Makefile.inc    |  6 +-----
 src/soc/imgtec/pistachio/Makefile.inc   |  8 +-------
 src/soc/marvell/bg4cd/Makefile.inc      |  3 ---
 src/soc/nvidia/tegra124/Makefile.inc    |  3 ---
 src/soc/nvidia/tegra132/Makefile.inc    |  3 ---
 src/soc/qualcomm/ipq806x/Makefile.inc   |  8 +-------
 src/soc/rockchip/rk3288/Makefile.inc    |  3 ---
 src/soc/samsung/exynos5250/Makefile.inc |  3 ---
 src/soc/samsung/exynos5420/Makefile.inc |  3 ---
 11 files changed, 16 insertions(+), 48 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 81c149d..ac6ce0b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -531,10 +531,19 @@ find-substr = $(word 1,$(subst _, ,$(1)))
 # and remove .x the next time and finally return romstage
 find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call find-substr,$(1))),$(call find-class,$(basename $(1))))
 
-$(objcbfs)/%.bin: $(objcbfs)/%.elf
-	$(eval class := $(call find-class,$(@F)))
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_$(class)) -O binary $< $@
+# Bootblocks are not CBFS stages. coreboot is currently expecting the bss to
+# be cleared by the loader of the stage. For ARM SoCs that means one needs to
+# include the bss section in the binary so the BootROM clears the bss on
+# loading of the bootblock stage. Achieve this by marking the bss section
+# loadable,allocatable, and data. Do the same for the .data section in case
+# it's marked as NOBITS.
+$(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.elf
+	@printf "    OBJCOPY    $(notdir $(@))\n"
+	$(OBJCOPY_bootblock) --set-section-flags .bss=load,alloc,data --set-section-flags .data=load,alloc,data $< $<.tmp
+	$(OBJCOPY_bootblock) -O binary $<.tmp $@
+
+$(objcbfs)/%.bin: $(objcbfs)/%.raw.bin
+	cp $< $@
 
 $(objcbfs)/%.elf: $(objcbfs)/%.debug
 	$(eval class := $(call find-class,$(@F)))
diff --git a/src/lib/program.ld b/src/lib/program.ld
index c8ce5ee..ab36239 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -111,14 +111,7 @@
 #endif
 
 #if ARCH_STAGE_HAS_BSS_SECTION
-#if ENV_BOOTBLOCK
-/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
- * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
- * the BSS into the .data section so those zeroes get loaded explicitly. */
-.data . : {
-#else
 .bss . : {
-#endif
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 	_bss = .;
 	*(.bss)
diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc
index ff231f7..8bad15f 100644
--- a/src/soc/broadcom/cygnus/Makefile.inc
+++ b/src/soc/broadcom/cygnus/Makefile.inc
@@ -62,10 +62,6 @@ ramstage-y += usb.c
 
 CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
 
-$(objcbfs)/bootblock.tmp: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@
-
 ifneq ($(V),1)
 redirect := > /dev/null
 endif
@@ -96,7 +92,7 @@ endif
 #   SLEEP		1
 #   DEEP_SLEEP		2
 #   EXCEPTION		4
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.tmp \
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
 		$(objutil)/broadcom/secimage/secimage \
 		util/broadcom/unauth.cfg \
 		util/broadcom/khmacsha256
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index df9fbcf..7f06db5 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -46,14 +46,8 @@ romstage-y += monotonic_timer.c
 
 CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/
 
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@.tmp
-	@mv $@.tmp $@
-
 # Create a complete bootblock which will start up the system
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BIMGTOOL)
 	@printf "    BIMGTOOL   $(subst $(obj)/,,$(@))\n"
 	$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
 
diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc
index 1a801c0..ded1917 100644
--- a/src/soc/marvell/bg4cd/Makefile.inc
+++ b/src/soc/marvell/bg4cd/Makefile.inc
@@ -45,9 +45,6 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c
 
 CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "Generating: $(subst $(obj)/,,$(@))\n"
 	@mkdir -p $(dir $@)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 46ce59d..38ba4f6 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -84,9 +84,6 @@ CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/
 # package up the image pull in bootblock.bin, it will be this wrapped version
 # instead of the raw bootblock.
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
 	@printf "    CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
 	$(CBOOTIMAGE) -gbct --soc tegra124 $< $@
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index c192055..bdd8074 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -121,9 +121,6 @@ CBOOTIMAGE_OPTS = --soc tegra132
 # package up the image pull in bootblock.bin, it will be this wrapped version
 # instead of the raw bootblock.
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
 	@printf "    CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
 	$(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 84eae0b..83b5e06 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -56,14 +56,8 @@ ramstage-y += tz_wrapper.S
 
 ifeq ($(CONFIG_USE_BLOBS),y)
 
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
-	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_bootblock) -O binary $< $@.tmp
-	@mv $@.tmp $@
-
 # Add MBN header to allow SBL3 to start coreboot bootblock
-$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
+$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin
 	@printf "    ADD MBN    $(subst $(obj)/,,$(@))\n"
 	./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
 	@mv $@.tmp $@
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index cd523b0..830ae1e 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -75,9 +75,6 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "Generating: $(subst $(obj)/,,$(@))\n"
 	@mkdir -p $(dir $@)
diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc
index 9f49134..2731f17 100644
--- a/src/soc/samsung/exynos5250/Makefile.inc
+++ b/src/soc/samsung/exynos5250/Makefile.inc
@@ -46,9 +46,6 @@ ramstage-y += cbmem.c
 
 CPPFLAGS_common += -Isrc/soc/samsung/exynos5250/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "    BL1, CKSUM $(subst $(obj)/,,$(@))\n"
 	util/exynos/fixed_cksum.py $< $<.cksum 32768
diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc
index 753e6d0..498e8d1 100644
--- a/src/soc/samsung/exynos5420/Makefile.inc
+++ b/src/soc/samsung/exynos5420/Makefile.inc
@@ -48,9 +48,6 @@ rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c
 
 CPPFLAGS_common += -Isrc/soc/samsung/exynos5420/include/
 
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
-	cp $< $@
-
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "    BL1, CKSUM $(subst $(obj)/,,$(@))\n"
 	util/exynos/variable_cksum.py $< $<.cksum


From gerrit at coreboot.org  Tue Sep 22 16:52:11 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Tue, 22 Sep 2015 16:52:11 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: WIP: ifdtool: Do
	proper ser/deser of descriptor
References: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+0@gerrit.coreboot.org>
Message-ID: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+3@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11635

-gerrit

commit 25c5784854bb7c9827636a33ea6c071b810be358
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 14 09:47:24 2015 -0700

    WIP: ifdtool: Do proper ser/deser of descriptor
    
    Change-Id: Iccc063d08beb2fcafe9af910a0b1b984fcbc134f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/ifdtool/Makefile      |  5 ++-
 util/ifdtool/ifd_drv_bin.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++
 util/ifdtool/ifdtool.c     | 56 +++++++++++++++++++++----------
 util/ifdtool/ifdtool.h     | 22 +++++++++++++
 4 files changed, 146 insertions(+), 19 deletions(-)

diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
index 02a02c4..9036952 100644
--- a/util/ifdtool/Makefile
+++ b/util/ifdtool/Makefile
@@ -25,7 +25,10 @@ PREFIX  = /usr/local
 CFLAGS  = -O2 -g -Wall -W -Werror
 LDFLAGS =
 
-OBJS = ifdtool.o
+OBJS = ifdtool.o ifd_drv_bin.o
+
+# Until we have a better way to pull in commonlib, her it goes:
+CFLAGS += -I../../src/commonlib/include
 
 all: dep $(PROGRAM)
 
diff --git a/util/ifdtool/ifd_drv_bin.c b/util/ifdtool/ifd_drv_bin.c
new file mode 100644
index 0000000..62f8548
--- /dev/null
+++ b/util/ifdtool/ifd_drv_bin.c
@@ -0,0 +1,82 @@
+
+#include "ifdtool.h"
+#include "commonlib/endian.h"
+
+#include <stdlib.h>
+
+static void des_flmap0(struct flash_descriptor *desc, uint32_t flmap0)
+{
+	desc->num_regions = (flmap0 >> 24) & 7;
+	desc->frba_offset = ((flmap0 >> 16) & 0xff) << 4;
+	desc->num_components = ((flmap0 >> 8) & 0x3) + 1;
+	desc->fcba_offset = ((flmap0 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap0(const struct flash_descriptor *desc)
+{
+	uint32_t flmap0;
+
+	flmap0 = (desc->num_regions & 0x7) << 24;
+	flmap0 |= ((desc->frba_offset >> 4) & 0xff)  << 16;
+	flmap0 |= ((desc->num_components - 1) & 0x3) << 8;
+	flmap0 |= ((desc->fcba_offset >> 4) & 0xff) << 0;
+
+	return flmap0;
+}
+
+static void des_flmap1(struct flash_descriptor *desc, uint32_t flmap1)
+{
+	desc->num_pch_straps = (flmap1 >> 24) & 0xff;
+	desc->fpsba_offset = ((flmap1 >> 16) & 0xff) << 4;
+	desc->num_masters = (flmap1 >> 8) & 3;
+	desc->fmba_offset = ((flmap1 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap1(const struct flash_descriptor *desc)
+{
+	uint32_t flmap1;
+
+	flmap1 = (desc->num_pch_straps & 0xff) << 24;
+	flmap1 |= ((desc->fpsba_offset >> 4) & 0xff)  << 16;
+	flmap1 |= (desc->num_masters & 0x3) << 8;
+	flmap1 |= ((desc->fmba_offset >> 4) & 0xff) << 0;
+
+	return flmap1;
+}
+
+static void des_flmap2(struct flash_descriptor *desc, uint32_t flmap2)
+{
+	desc->iccriba_offset = ((flmap2 >> 16) & 0xff) << 4;
+	desc->num_pch_straps = (flmap2 >> 8) & 0xff;
+	desc->fmsba_offset = ((flmap2 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap2(const struct flash_descriptor *desc)
+{
+	uint32_t flmap2;
+
+	flmap2 = ((desc->iccriba_offset >> 4) & 0xff)  << 16;
+	flmap2 |= (desc->num_pch_straps & 0x3) << 8;
+	flmap2 |= ((desc->fmsba_offset >> 4) & 0xff) << 0;
+
+	return flmap2;
+}
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud)
+{
+	const uint8_t *ifd_regs = fud;
+
+	des_flmap0(desc, read_le32(ifd_regs + 0x04));
+	des_flmap1(desc, read_le32(ifd_regs + 0x08));
+	des_flmap2(desc, read_le32(ifd_regs + 0x0C));
+}
+
+void dont_compile_fail_me(void)
+{
+	des_flmap0(NULL, 0);
+	ser_flmap0(NULL);
+	des_flmap1(NULL, 0);
+	ser_flmap1(NULL);
+	des_flmap2(NULL, 0);
+	ser_flmap2(NULL);
+}
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index feaffa8..4aebe35 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -18,6 +18,7 @@
  */
 
 #include <unistd.h>
+#include <stdbool.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -25,6 +26,8 @@
 #include <fcntl.h>
 #include <sys/types.h>
 #include <sys/stat.h>
+
+#include "commonlib/endian.h"
 #include "ifdtool.h"
 
 #ifndef O_BINARY
@@ -33,7 +36,7 @@
 
 static int ifd_version;
 
-static const struct region_name region_names[MAX_REGIONS] = {
+static const struct region_name region_names_old_yester_years[9] = {
 	{ "Flash Descriptor", "fd" },
 	{ "BIOS", "bios" },
 	{ "Intel ME", "me" },
@@ -45,15 +48,29 @@ static const struct region_name region_names[MAX_REGIONS] = {
 	{ "EC", "ec" },
 };
 
-static fdbar_t *find_fd(char *image, int size)
+static const struct region_name region_names[9] = {
+	{ "Flash Descriptor", "fd" },
+	{ "IFWI", "bios" },
+	{ "TXE", "me" },
+	{ "Platform Data", "pd" },
+	{ "Device Expansion", "bs0" },
+	{ "Reserved", "res1" },
+	{ "Reserved", "res2" },
+	{ "Reserved", "res3" },
+	{ "Reserved", "res4" },
+};
+
+static void *find_fd(void *image, size_t size)
 {
-	int i, found = 0;
+	size_t i;
+	bool found = false;
+	uint8_t *base = image;
 
 	/* Scan for FD signature */
 	for (i = 0; i < (size - 4); i += 4) {
-		if (*(uint32_t *) (image + i) == 0x0FF0A55A) {
-			found = 1;
-			break;	// signature found.
+		if (read_le32(base + i) == 0x0FF0A55A) {
+			found = true;
+			break;	/* signature found. */
 		}
 	}
 
@@ -62,7 +79,7 @@ static fdbar_t *find_fd(char *image, int size)
 		return NULL;
 	}
 
-	return (fdbar_t *) (image + i);
+	return base + i;
 }
 
 /*
@@ -221,7 +238,7 @@ static int region_num(const char *name)
 
 static const char *region_filename(int region_type)
 {
-	static const char *region_filenames[MAX_REGIONS] = {
+	static const char *region_filenames[9] = {
 		"flashregion_0_flashdescriptor.bin",
 		"flashregion_1_bios.bin",
 		"flashregion_2_intel_me.bin",
@@ -604,25 +621,28 @@ static void dump_oem(uint8_t *oem)
 
 static void dump_fd(char *image, int size)
 {
+	struct flash_descriptor desc;
 	fdbar_t *fdb = find_fd(image, size);
 	if (!fdb)
 		exit(EXIT_FAILURE);
 
+	read_flash_descriptor(&desc,fdb);
+
 	printf("FLMAP0:    0x%08x\n", fdb->flmap0);
-	printf("  NR:      %d\n", (fdb->flmap0 >> 24) & 7);
-	printf("  FRBA:    0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
-	printf("  NC:      %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
-	printf("  FCBA:    0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+	printf("  NR:      %d\n", desc.num_regions);
+	printf("  FRBA:    0x%x\n", desc.frba_offset);
+	printf("  NC:      %d\n", desc.num_components);
+	printf("  FCBA:    0x%x\n", desc.fcba_offset);
 
 	printf("FLMAP1:    0x%08x\n", fdb->flmap1);
-	printf("  ISL:     0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
-	printf("  FPSBA:   0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
-	printf("  NM:      %d\n", (fdb->flmap1 >> 8) & 3);
-	printf("  FMBA:    0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+	printf("  ISL:     0x%02x\n", desc.num_pch_straps);
+	printf("  FPSBA:   0x%x\n", desc.fpsba_offset);
+	printf("  NM:      %d\n", desc.num_masters);
+	printf("  FMBA:    0x%x\n", desc.fmba_offset);
 
 	printf("FLMAP2:    0x%08x\n", fdb->flmap2);
-	printf("  PSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
-	printf("  FMSBA:   0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+	printf("  PSL:     0x%04x\n", desc.num_cpu_straps);
+	printf("  FMSBA:   0x%x\n", desc.fmsba_offset);
 
 	printf("FLUMAP1:   0x%08x\n", fdb->flumap1);
 	printf("  Intel ME VSCC Table Length (VTL):        %d\n",
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index 195d91c..29141c7 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -143,3 +143,25 @@ struct region_name {
 	char *pretty;
 	char *terse;
 };
+
+struct flash_descriptor
+{
+	/* FLMAP0 */
+	uint8_t num_regions;
+	uint16_t frba_offset;
+	uint8_t num_components;
+	uint16_t fcba_offset;
+
+	/* FLMAP1 */
+	uint8_t num_pch_straps;
+	uint16_t fpsba_offset;
+	uint8_t num_masters;
+	uint16_t fmba_offset;
+
+	/* FLMAP2 */
+	uint16_t iccriba_offset;
+	uint8_t num_cpu_straps;
+	uint16_t fmsba_offset;
+};
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud);


From gerrit at coreboot.org  Tue Sep 22 19:42:05 2015
From: gerrit at coreboot.org (Daisuke Nojiri (dnojiri@chromium.org))
Date: Tue, 22 Sep 2015 19:42:05 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: push test
References: <Ia7c4f3e88b9bb9ae220a633f2e3266500cb1f999+0@gerrit.coreboot.org>
Message-ID: <Ia7c4f3e88b9bb9ae220a633f2e3266500cb1f999+1@gerrit.coreboot.org>

Daisuke Nojiri (dnojiri at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11697

-gerrit

commit 92e2d4d5f7d261ef540a27ba6582ff77a82c755a
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Tue Sep 22 12:40:36 2015 -0700

    push test
    
    Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Change-Id: Ia7c4f3e88b9bb9ae220a633f2e3266500cb1f999
---
 push_test | 0
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/push_test b/push_test
new file mode 100644
index 0000000..e69de29


From gerrit at coreboot.org  Tue Sep 22 20:17:44 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Tue, 22 Sep 2015 20:17:44 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: armv7:
	Word-sized memory operations for 32 bit read/write
References: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+0@gerrit.coreboot.org>
Message-ID: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+1@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698

-gerrit

commit f0e12cde71595b828e2a1ccb0438177dee66d606
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Tue Sep 22 22:16:33 2015 +0200

    armv7: Word-sized memory operations for 32 bit read/write
    
    Some registers only allow word-sized operations and will cause a data fault when
    accessed with byte-sized operations. However, the compiler may or may not break
    a 32 bit operation into smaller (byte-sized) chunks. Thus, we need to reliably
    perform word-sized operations for 32 bit read/write.
    
    This is particularly the case on the rk3288 SRAM registers, where the watchdog
    tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
    compiler, where a 32 bit read would be broken into byte-sized chunks, which
    caused a data fault when accessing the watchdog tombstone register.
    
    Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/arch/arm/include/armv7/arch/io.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..8983a66 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -41,8 +41,11 @@ static inline uint16_t read16(const void *addr)
 
 static inline uint32_t read32(const void *addr)
 {
+	uint32_t val = 0;
+
 	dmb();
-	return *(volatile uint32_t *)addr;
+	asm volatile ("ldr %0, [%1, #0]" : "=r" (val) : "r" (addr) : "memory");
+	return val;
 }
 
 static inline void write8(void *addr, uint8_t val)
@@ -62,7 +65,7 @@ static inline void write16(void *addr, uint16_t val)
 static inline void write32(void *addr, uint32_t val)
 {
 	dmb();
-	*(volatile uint32_t *)addr = val;
+	asm volatile ("str %0, [%1, #0]" : : "r" (val), "r" (addr) : "memory");
 	dmb();
 }
 


From gerrit at coreboot.org  Tue Sep 22 21:21:38 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 22 Sep 2015 21:21:38 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: coreboot:
	introduce commonlib
References: <I9e46a279569733336bc0a018aed96bc924c07cdd+0@gerrit.coreboot.org>
Message-ID: <E1ZeV0M-0006Ji-FM@mail.coreboot.org>

the following patch was just integrated into master:
commit dc9f5cd54661e5ba3fffee7af0ba17dde9367b95
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 8 13:34:43 2015 -0500

    coreboot: introduce commonlib
    
    Instead of reaching into src/include and re-writing code
    allow for cleaner code sharing within coreboot and its
    utilities. The additional thing needed at this point is
    for the utilities to provide a printk() declaration within
    a <console/console.h> file. That way code which uses printk()
    can than be mapped properly to verbosity of utility parameters.
    
    Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11592
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/11592 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 22 21:22:02 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 22 Sep 2015 21:22:02 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: commonlib: add
	endian related accessor functions
References: <If44c4d489f0dab86a73b73580c039e364c7e517d+0@gerrit.coreboot.org>
Message-ID: <E1ZeV0k-0006N1-4p@mail.coreboot.org>

the following patch was just integrated into master:
commit f66a026d70961832164ca4edd701d762384786b3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 11:24:08 2015 -0500

    commonlib: add endian related accessor functions
    
    This commit adds read/write functions for both big and
    little endian interpretations. Additionally there are
    variants that allow an offset to be provided into the
    source buffer.
    
    BUG=None
    TEST=Wrote test harness for functions.  Also booted ARM QEMU
         through end of payload.
    
    Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11677
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/11677 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 22 21:22:50 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 22 Sep 2015 21:22:50 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: linking: link
	bootblock.elf with .data and .bss sections again
References: <I94bd404c2c4a8b9332393e6224e98940a9cad4a2+0@gerrit.coreboot.org>
Message-ID: <E1ZeV1V-0006Pv-Qv@mail.coreboot.org>

the following patch was just integrated into master:
commit d972f78e759ffccf9187ab3f3b00b567c7f30f53
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 17 17:02:53 2015 -0500

    linking: link bootblock.elf with .data and .bss sections again
    
    Currently coreboot expects the loader to clear the bss section
    for all stages. i.e. stages don't clear their own bss. On ARM
    SoCs the BootROM would be responsible for this. To do that
    one needs to include the bss section data (all zeros) in the
    bootblock.bin file. This was previously being attempted by
    keeping the .bss info in the .data section because objcopy
    happened zero out non-file allocated data section data.
    
    Instead go back to linking bootblock with the bss section
    but mark the bss section as loadable allocatable data. That
    way it will be included in the binary properly when objcopy
    -O binary is emplyed. Also do the same for the data section
    in the case of no non-zero object values are in the data
    section.
    
    Without this change the trick of including .bss in .data
    was not working when there wasn't a non-zero value object
    in the data section.
    
    BUG=None
    BRANCH=None
    TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
         the cleared bss.
    
    Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11680
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11680 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 22 22:55:49 2015
From: gerrit at coreboot.org (Ronald G. Minnich (rminnich@gmail.com))
Date: Tue, 22 Sep 2015 22:55:49 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: RISCV: use a
	different prog_run for the payload.
References: <Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1+0@gerrit.coreboot.org>
Message-ID: <Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1+1@gerrit.coreboot.org>

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11699

-gerrit

commit 18118044bc5281281e8135de977e9d7d1c6230de
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Tue Sep 22 15:53:32 2015 -0700

    RISCV: use a different prog_run for the payload.
    
    Unlike the other stages, the payload requires virtual memory to be set up
    and also a privelege level change.
    
    Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/arch/riscv/Makefile.inc  |  2 +-
 src/arch/riscv/bootpayload.c | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index de6eb91..b7f2592 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -91,7 +91,7 @@ ramstage-y += virtual_memory.c
 ramstage-y += rom_media.c
 ramstage-y += stages.c
 ramstage-y += misc.c
-ramstage-y += boot.c
+ramstage-y += bootpayload.c
 ramstage-y += tables.c
 ramstage-y += \
 	$(top)/src/lib/memchr.c \
diff --git a/src/arch/riscv/bootpayload.c b/src/arch/riscv/bootpayload.c
new file mode 100644
index 0000000..a6e9767
--- /dev/null
+++ b/src/arch/riscv/bootpayload.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <program_loading.h>
+#include <vm.h>
+#include <arch/encoding.h>
+
+void arch_prog_run(struct prog *prog)
+{
+	initVirtualMemory();
+	write_csr(mepc, prog_entry(prog));
+    	asm volatile("eret");
+}


From gerrit at coreboot.org  Wed Sep 23 16:12:47 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Wed, 23 Sep 2015 16:12:47 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: WIP: ifdtool: Do
	proper ser/deser of descriptor
References: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+0@gerrit.coreboot.org>
Message-ID: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+4@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11635

-gerrit

commit 6f295f3f5ee2c51c3e90210024c1854366e85f27
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 14 09:47:24 2015 -0700

    WIP: ifdtool: Do proper ser/deser of descriptor
    
    Change-Id: Iccc063d08beb2fcafe9af910a0b1b984fcbc134f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/ifdtool/Makefile      |   5 +-
 util/ifdtool/ifd_drv_bin.c | 126 +++++++++++++++++++++++++++++++++++++++++++++
 util/ifdtool/ifdtool.c     |  87 ++++++++++++++++++-------------
 util/ifdtool/ifdtool.h     |  36 +++++++++++++
 4 files changed, 218 insertions(+), 36 deletions(-)

diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
index 02a02c4..9036952 100644
--- a/util/ifdtool/Makefile
+++ b/util/ifdtool/Makefile
@@ -25,7 +25,10 @@ PREFIX  = /usr/local
 CFLAGS  = -O2 -g -Wall -W -Werror
 LDFLAGS =
 
-OBJS = ifdtool.o
+OBJS = ifdtool.o ifd_drv_bin.o
+
+# Until we have a better way to pull in commonlib, her it goes:
+CFLAGS += -I../../src/commonlib/include
 
 all: dep $(PROGRAM)
 
diff --git a/util/ifdtool/ifd_drv_bin.c b/util/ifdtool/ifd_drv_bin.c
new file mode 100644
index 0000000..c9ca743
--- /dev/null
+++ b/util/ifdtool/ifd_drv_bin.c
@@ -0,0 +1,126 @@
+
+#include "ifdtool.h"
+#include "commonlib/endian.h"
+
+#include <stdlib.h>
+
+static void des_flmap0(struct flash_descriptor *desc, uint32_t flmap0)
+{
+	desc->num_regions = (flmap0 >> 24) & 7;
+	desc->frba_offset = ((flmap0 >> 16) & 0xff) << 4;
+	desc->num_components = ((flmap0 >> 8) & 0x3) + 1;
+	desc->fcba_offset = ((flmap0 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap0(const struct flash_descriptor *desc)
+{
+	uint32_t flmap0;
+
+	flmap0 = (desc->num_regions & 0x7) << 24;
+	flmap0 |= ((desc->frba_offset >> 4) & 0xff)  << 16;
+	flmap0 |= ((desc->num_components - 1) & 0x3) << 8;
+	flmap0 |= ((desc->fcba_offset >> 4) & 0xff) << 0;
+
+	return flmap0;
+}
+
+static void des_flmap1(struct flash_descriptor *desc, uint32_t flmap1)
+{
+	desc->num_pch_straps = (flmap1 >> 24) & 0xff;
+	desc->fpsba_offset = ((flmap1 >> 16) & 0xff) << 4;
+	desc->num_masters = (flmap1 >> 8) & 3;
+	desc->fmba_offset = ((flmap1 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap1(const struct flash_descriptor *desc)
+{
+	uint32_t flmap1;
+
+	flmap1 = (desc->num_pch_straps & 0xff) << 24;
+	flmap1 |= ((desc->fpsba_offset >> 4) & 0xff)  << 16;
+	flmap1 |= (desc->num_masters & 0x3) << 8;
+	flmap1 |= ((desc->fmba_offset >> 4) & 0xff) << 0;
+
+	return flmap1;
+}
+
+static void des_flmap2(struct flash_descriptor *desc, uint32_t flmap2)
+{
+	desc->iccriba_offset = ((flmap2 >> 16) & 0xff) << 4;
+	desc->num_pch_straps = (flmap2 >> 8) & 0xff;
+	desc->fmsba_offset = ((flmap2 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap2(const struct flash_descriptor *desc)
+{
+	uint32_t flmap2;
+
+	flmap2 = ((desc->iccriba_offset >> 4) & 0xff)  << 16;
+	flmap2 |= (desc->num_pch_straps & 0x3) << 8;
+	flmap2 |= ((desc->fmsba_offset >> 4) & 0xff) << 0;
+
+	return flmap2;
+}
+
+static void des_flumap1(struct flash_descriptor *desc, uint32_t flumap1)
+{
+	desc->vtba_len = ((flumap1 >> 8) & 0xff) / 2;
+	desc->vtba_offset = ((flumap1 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flumap1(const struct flash_descriptor *desc)
+{
+	uint32_t flumap1;
+
+	flumap1 = ((desc->vtba_len * 2) & 0xff) << 8;
+	flumap1 |= ((desc->vtba_offset >> 4) & 0xff) << 0;
+
+	return flumap1;
+}
+
+static void vscc_deserialize_jid(struct vscc_entry *vscc, uint32_t jid)
+{
+	vscc->spi_device_id[1] = (jid >> 16) & 0xff;
+	vscc->spi_device_id[0] = (jid >> 8) & 0xff;
+	vscc->spi_vendor_id = jid & 0xff;
+}
+
+static void deserialize_vtba(struct vscc_entry *vtba, uint8_t num_entries,
+			     const void *stream)
+{
+	size_t i;
+	const uint8_t *base = stream;
+
+	for (i = 0; i < num_entries; i++, base += 8) {
+		vtba[i].vscc = read_le32(base + 0);
+		vscc_deserialize_jid(vtba + i, read_le32(base + 4));
+	}
+}
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud)
+{
+	const uint8_t *ifd_regs = fud;
+
+	des_flmap0(desc, read_le32(ifd_regs + 0x04));
+	des_flmap1(desc, read_le32(ifd_regs + 0x08));
+	des_flmap2(desc, read_le32(ifd_regs + 0x0C));
+	des_flumap1(desc, read_le32(ifd_regs + 0xeec));
+
+	/* FIXME: check malloc result */
+	desc->vtba = malloc(desc->vtba_len * sizeof(*desc->vtba));
+	deserialize_vtba(desc->vtba, desc->vtba_len, ifd_regs + desc->vtba_offset);
+}
+
+void dont_compile_fail_me(void)
+{
+	des_flmap0(NULL, 0);
+	ser_flmap0(NULL);
+	des_flmap1(NULL, 0);
+	ser_flmap1(NULL);
+	des_flmap2(NULL, 0);
+	ser_flmap2(NULL);
+	des_flumap1(NULL, 0);
+	ser_flumap1(NULL);
+
+	vscc_deserialize_jid(NULL, 0);
+}
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index feaffa8..a69d83e 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -18,6 +18,7 @@
  */
 
 #include <unistd.h>
+#include <stdbool.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -25,6 +26,8 @@
 #include <fcntl.h>
 #include <sys/types.h>
 #include <sys/stat.h>
+
+#include "commonlib/endian.h"
 #include "ifdtool.h"
 
 #ifndef O_BINARY
@@ -33,7 +36,7 @@
 
 static int ifd_version;
 
-static const struct region_name region_names[MAX_REGIONS] = {
+static const struct region_name region_names_old_yester_years[9] = {
 	{ "Flash Descriptor", "fd" },
 	{ "BIOS", "bios" },
 	{ "Intel ME", "me" },
@@ -45,15 +48,29 @@ static const struct region_name region_names[MAX_REGIONS] = {
 	{ "EC", "ec" },
 };
 
-static fdbar_t *find_fd(char *image, int size)
+static const struct region_name region_names[9] = {
+	{ "Flash Descriptor", "fd" },
+	{ "IFWI", "bios" },
+	{ "TXE", "me" },
+	{ "Platform Data", "pd" },
+	{ "Device Expansion", "bs0" },
+	{ "Reserved", "res1" },
+	{ "Reserved", "res2" },
+	{ "Reserved", "res3" },
+	{ "Reserved", "res4" },
+};
+
+static void *find_fd(void *image, size_t size)
 {
-	int i, found = 0;
+	size_t i;
+	bool found = false;
+	uint8_t *base = image;
 
 	/* Scan for FD signature */
 	for (i = 0; i < (size - 4); i += 4) {
-		if (*(uint32_t *) (image + i) == 0x0FF0A55A) {
-			found = 1;
-			break;	// signature found.
+		if (read_le32(base + i) == 0x0FF0A55A) {
+			found = true;
+			break;	/* signature found. */
 		}
 	}
 
@@ -62,7 +79,7 @@ static fdbar_t *find_fd(char *image, int size)
 		return NULL;
 	}
 
-	return (fdbar_t *) (image + i);
+	return base + i;
 }
 
 /*
@@ -221,7 +238,7 @@ static int region_num(const char *name)
 
 static const char *region_filename(int region_type)
 {
-	static const char *region_filenames[MAX_REGIONS] = {
+	static const char *region_filenames[9] = {
 		"flashregion_0_flashdescriptor.bin",
 		"flashregion_1_bios.bin",
 		"flashregion_2_intel_me.bin",
@@ -513,14 +530,14 @@ static void dump_fmsba(fmsba_t * fmsba)
 	printf("????:      0x%08x\n", fmsba->data[3]);
 }
 
-static void dump_jid(uint32_t jid)
+static void dump_jid(const struct vscc_entry *vscc)
 {
 	printf("    SPI Componend Device ID 1:          0x%02x\n",
-		(jid >> 16) & 0xff);
+		vscc->spi_device_id[1]);
 	printf("    SPI Componend Device ID 0:          0x%02x\n",
-		(jid >> 8) & 0xff);
+		vscc->spi_device_id[0]);
 	printf("    SPI Componend Vendor ID:            0x%02x\n",
-		jid & 0xff);
+		vscc->spi_vendor_id);
 }
 
 static void dump_vscc(uint32_t vscc)
@@ -574,17 +591,17 @@ static void dump_vscc(uint32_t vscc)
 	}
 }
 
-static void dump_vtba(vtba_t *vtba, int vtl)
+static void dump_vtba(struct vscc_entry *vtba, size_t vtba_len)
 {
 	int i;
-	int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8;
+	int num = vtba_len;
 
 	printf("ME VSCC table:\n");
 	for (i = 0; i < num; i++) {
-		printf("  JID%d:  0x%08x\n", i, vtba->entry[i].jid);
-		dump_jid(vtba->entry[i].jid);
-		printf("  VSCC%d: 0x%08x\n", i, vtba->entry[i].vscc);
-		dump_vscc(vtba->entry[i].vscc);
+		//printf("  JID%d:  0x%08x\n", i, vtba->entry[i].jid);
+		dump_jid(vtba + i);
+		printf("  VSCC%d: 0x%08x\n", i, vtba[i].vscc);
+		dump_vscc(vtba[i].vscc);
 	}
 	printf("\n");
 }
@@ -604,34 +621,34 @@ static void dump_oem(uint8_t *oem)
 
 static void dump_fd(char *image, int size)
 {
+	struct flash_descriptor desc;
 	fdbar_t *fdb = find_fd(image, size);
 	if (!fdb)
 		exit(EXIT_FAILURE);
 
+	read_flash_descriptor(&desc,fdb);
+
 	printf("FLMAP0:    0x%08x\n", fdb->flmap0);
-	printf("  NR:      %d\n", (fdb->flmap0 >> 24) & 7);
-	printf("  FRBA:    0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
-	printf("  NC:      %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
-	printf("  FCBA:    0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+	printf("  NR:      %d\n", desc.num_regions);
+	printf("  FRBA:    0x%x\n", desc.frba_offset);
+	printf("  NC:      %d\n", desc.num_components);
+	printf("  FCBA:    0x%x\n", desc.fcba_offset);
 
 	printf("FLMAP1:    0x%08x\n", fdb->flmap1);
-	printf("  ISL:     0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
-	printf("  FPSBA:   0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
-	printf("  NM:      %d\n", (fdb->flmap1 >> 8) & 3);
-	printf("  FMBA:    0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+	printf("  ISL:     0x%02x\n", desc.num_pch_straps);
+	printf("  FPSBA:   0x%x\n", desc.fpsba_offset);
+	printf("  NM:      %d\n", desc.num_masters);
+	printf("  FMBA:    0x%x\n", desc.fmba_offset);
 
 	printf("FLMAP2:    0x%08x\n", fdb->flmap2);
-	printf("  PSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
-	printf("  FMSBA:   0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+	printf("  PSL:     0x%04x\n", desc.num_cpu_straps);
+	printf("  FMSBA:   0x%x\n", desc.fmsba_offset);
 
 	printf("FLUMAP1:   0x%08x\n", fdb->flumap1);
-	printf("  Intel ME VSCC Table Length (VTL):        %d\n",
-		(fdb->flumap1 >> 8) & 0xff);
-	printf("  Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n",
-		(fdb->flumap1 & 0xff) << 4);
-	dump_vtba((vtba_t *)
-			(image + ((fdb->flumap1 & 0xff) << 4)),
-			(fdb->flumap1 >> 8) & 0xff);
+	printf("  Intel ME VSCC Table Length (VTL):        %d\n", desc.vtba_len);
+	printf("  Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n", desc.vtba_offset);
+
+	dump_vtba(desc.vtba, desc.vtba_len);
 	dump_oem((uint8_t *)image + 0xf00);
 	dump_frba((frba_t *)
 			(image + (((fdb->flmap0 >> 16) & 0xff) << 4)));
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index 195d91c..6bafd0d 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -130,6 +130,14 @@ typedef struct {
 	uint32_t vscc;
 } vscc_t;
 
+struct vscc_entry {
+	uint32_t vscc;
+	/* Jid */
+	uint8_t spi_device_id[2];
+	uint8_t spi_vendor_id;
+};
+
+
 typedef struct {
 	// Actual number of entries specified in vtl
 	vscc_t entry[8];
@@ -143,3 +151,31 @@ struct region_name {
 	char *pretty;
 	char *terse;
 };
+
+struct flash_descriptor
+{
+	/* FLMAP0 */
+	uint8_t num_regions;
+	uint16_t frba_offset;
+	uint8_t num_components;
+	uint16_t fcba_offset;
+
+	/* FLMAP1 */
+	uint8_t num_pch_straps;
+	uint16_t fpsba_offset;
+	uint8_t num_masters;
+	uint16_t fmba_offset;
+
+	/* FLMAP2 */
+	uint16_t iccriba_offset;
+	uint8_t num_cpu_straps;
+	uint16_t fmsba_offset;
+
+	/* FLUMAP1 */
+	uint8_t vtba_len;
+	uint16_t vtba_offset;
+
+	struct vscc_entry *vtba;
+};
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud);


From gerrit at coreboot.org  Wed Sep 23 16:20:20 2015
From: gerrit at coreboot.org (Ronald G. Minnich (rminnich@gmail.com))
Date: Wed, 23 Sep 2015 16:20:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: RISCV: modify
	arch_prog_run to handle payloads correctly.
References: <Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1+0@gerrit.coreboot.org>
Message-ID: <Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1+2@gerrit.coreboot.org>

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11699

-gerrit

commit 37cd07ad1a305b87360cf49b643b67201d62e638
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Tue Sep 22 15:53:32 2015 -0700

    RISCV: modify arch_prog_run to handle payloads correctly.
    
    Unlike the other stages, the payload requires virtual memory to be set up
    and also a privelege level change.
    
    Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/arch/riscv/boot.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index d07d825..ab4ae95 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -18,11 +18,19 @@
  */
 
 #include <program_loading.h>
+#include <vm.h>
+#include <arch/encoding.h>
+#include <rules.h>
 
 void arch_prog_run(struct prog *prog)
 {
-	void (*doit)(void *);
+	void (*doit)(void *) = prog_entry(prog);
 
-	doit = prog_entry(prog);
-	doit(prog_entry_arg(prog));
+	if (ENV_RAMSTAGE && prog_type(prog) == ASSET_PAYLOAD) {
+		initVirtualMemory();
+		write_csr(mepc, doit);
+		asm volatile("eret");
+	} else {
+		doit(prog_entry_arg(prog));
+	}
 }


From gerrit at coreboot.org  Wed Sep 23 17:02:21 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 23 Sep 2015 17:02:21 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: RISCV: modify
	arch_prog_run to handle payloads correctly.
References: <Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1+0@gerrit.coreboot.org>
Message-ID: <E1ZenQz-0001MB-C1@mail.coreboot.org>

the following patch was just integrated into master:
commit f47f5fb4f138d234ac0ea62a2420873afa8b86dc
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Tue Sep 22 15:53:32 2015 -0700

    RISCV: modify arch_prog_run to handle payloads correctly.
    
    Unlike the other stages, the payload requires virtual memory to be set up
    and also a privelege level change.
    
    Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
    Reviewed-on: http://review.coreboot.org/11699
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11699 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 23 19:35:13 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 23 Sep 2015 19:35:13 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: google:
	veyron: CBFS_SIZE to match the available size for Coreboot in
	ChromeOS
References: <I168386a5011222866654a496d8d054faff7a9406+0@gerrit.coreboot.org>
Message-ID: <E1Zepov-0007kE-PN@mail.coreboot.org>

the following patch was just integrated into master:
commit d738b1459788590e9ab21d09f32fbf2eca324412
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Wed Sep 16 18:23:23 2015 +0200

    google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOS
    
    When building for ChromeOS, it is expected that Coreboot will only occupy the
    first MiB of the SPI flash, according to the veyron fmap description.
    Otherwise, it makes sense to use the full ROM size.
    
    Change-Id: I168386a5011222866654a496d8d054faff7a9406
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
    Reviewed-on: http://review.coreboot.org/11117
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11117 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 23 19:35:37 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 23 Sep 2015 19:35:37 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: chromeos:
	vboot and chromeos dependency removal for sw write protect state
References: <I47ce31530a03f6749e0f370e5d868466318b3bb6+0@gerrit.coreboot.org>
Message-ID: <E1ZeppJ-0007lt-5C@mail.coreboot.org>

the following patch was just integrated into master:
commit a40032780fe4da7d95b203fb3d05a25183590952
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:27:27 2015 +0200

    chromeos: vboot and chromeos dependency removal for sw write protect state
    
    This removes the dependency on chromeos and vboot for the sw write protect state
    function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to
    both reflect this change and become consistent with the definition of
    get_write_protect_state that is already in use.
    
    Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
    Reviewed-on: http://review.coreboot.org/11496
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11496 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 23 19:37:46 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 23 Sep 2015 19:37:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: armv7:
	Word-sized/half-word-sized memory operations for 32/16 bit
	read/write
References: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+0@gerrit.coreboot.org>
Message-ID: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+2@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698

-gerrit

commit 600b852808ade3e7387a7aa16ddd006f41afad68
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Tue Sep 22 22:16:33 2015 +0200

    armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
    
    Some registers only allow word-sized or half-word-sized operations and will
    cause a data fault when accessed with byte-sized operations.
    However, the compiler may or may not break such an operation into smaller
    (byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
    32 bit read/write and half-word-sized operations for 16 bit read/write.
    
    This is particularly the case on the rk3288 SRAM registers, where the watchdog
    tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
    compiler, where a 32 bit read would be broken into byte-sized chunks, which
    caused a data fault when accessing the watchdog tombstone register.
    
    The definitions for byte-sized memory operations are also adapted to stay
    consistent with the rest.
    
    Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/arch/arm/include/armv7/arch/io.h | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..276cfb3 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -29,40 +29,49 @@
 
 static inline uint8_t read8(const void *addr)
 {
+	uint8_t val = 0;
+
 	dmb();
-	return *(volatile uint8_t *)addr;
+	asm volatile ("ldrb %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
+	return val;
 }
 
 static inline uint16_t read16(const void *addr)
 {
+	uint16_t val = 0;
+
 	dmb();
-	return *(volatile uint16_t *)addr;
+	asm volatile ("ldrh %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
+	return val;
 }
 
 static inline uint32_t read32(const void *addr)
 {
+	uint32_t val = 0;
+
 	dmb();
-	return *(volatile uint32_t *)addr;
+	asm volatile ("ldr %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
+	return val;
 }
 
 static inline void write8(void *addr, uint8_t val)
 {
 	dmb();
-	*(volatile uint8_t *)addr = val;
+	asm volatile ("strb %0, [%1]" : : "r" (val), "r" (addr) : "memory");
 	dmb();
 }
 
 static inline void write16(void *addr, uint16_t val)
 {
 	dmb();
-	*(volatile uint16_t *)addr = val;
+	asm volatile ("strh %0, [%1]" : : "r" (val), "r" (addr) : "memory");
 	dmb();
 }
 
 static inline void write32(void *addr, uint32_t val)
 {
 	dmb();
-	*(volatile uint32_t *)addr = val;
+	asm volatile ("str %0, [%1]" : : "r" (val), "r" (addr) : "memory");
 	dmb();
 }
 


From gerrit at coreboot.org  Wed Sep 23 19:42:54 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 23 Sep 2015 19:42:54 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos:
	vboot-related functions move to common vboot code
References: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+0@gerrit.coreboot.org>
Message-ID: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+4@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11497

-gerrit

commit 6644b6d5d59d6f3db78574c96148c05b34e28dff
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:41:14 2015 +0200

    chromeos: vboot-related functions move to common vboot code
    
    This moves a few vboot-prefixed functions that were defined in chromeos.c to
    vboot_common.c, since those are only relevant to vboot and depend on the vboot
    handoff data. This allows more separation between CONFIG_CHROMEOS and what
    CONFIG_CHROMEOS selects, so that each separate option (such as
    CONFIG_VBOOT_VERIFY_FIRMWARE) can be enabled separately.
    
    Thus, the actual definitions of these functions will only be declared when
    CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling
    vboot_skip_display_init in bootmode was also adapted.
    
    Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/vendorcode/google/chromeos/chromeos.c     | 32 ---------------------------
 src/vendorcode/google/chromeos/chromeos.h     | 16 --------------
 src/vendorcode/google/chromeos/vboot_common.c | 27 ++++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot_common.h |  7 ++++++
 4 files changed, 34 insertions(+), 48 deletions(-)

diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index c2190b7..4864b8c 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -20,38 +20,6 @@
 #include <stddef.h>
 #include <string.h>
 #include "chromeos.h"
-#include <boot/coreboot_tables.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include "vboot_handoff.h"
-
-static int vboot_handoff_flag(uint32_t flag)
-{
-	struct vboot_handoff *vbho;
-
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
-
-	if (vbho == NULL)
-		return 0;
-
-	return !!(vbho->init_params.out_flags & flag);
-}
-
-int vboot_skip_display_init(void)
-{
-	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
-}
-
-int vboot_enable_developer(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
-}
-
-int vboot_enable_recovery(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
-}
 
 int __attribute__((weak)) clear_recovery_mode_switch(void)
 {
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index 798ab3e..bdc9435 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -45,29 +45,14 @@ void elog_add_boot_reason(void);
 /* functions implemented in watchdog.c */
 void elog_add_watchdog_reset(void);
 void reboot_from_watchdog(void);
-
-int vboot_enable_developer(void);
-int vboot_enable_recovery(void);
-int vboot_skip_display_init(void);
 #else
 static inline void elog_add_boot_reason(void) { return; }
 static inline void elog_add_watchdog_reset(void) { return; }
 static inline void reboot_from_watchdog(void) { return; }
-static inline int vboot_skip_display_init(void) { return 0; }
 #endif /* CONFIG_CHROMEOS */
 
 struct romstage_handoff;
 
-#if CONFIG_VBOOT_VERIFY_FIRMWARE
-/* Returns 0 on success < 0 on error. */
-int vboot_get_handoff_info(void **addr, uint32_t *size);
-#else /* CONFIG_VBOOT_VERIFY_FIRMWARE */
-static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
-{
-	return -1;
-}
-#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
-
 #include "gnvs.h"
 struct device;
 
@@ -84,6 +69,5 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {}
 #endif /* CONFIG_CHROMEOS_RAMOOPS */
 
 void cbmem_add_vpd_calibration_data(void);
-void vboot_reboot(void);
 
 #endif /* __CHROMEOS_H__ */
diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 2fd29b6..1c216d0 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -55,6 +55,33 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 	return 0;
 }
 
+static int vboot_handoff_flag(uint32_t flag)
+{
+	struct vboot_handoff *vbho;
+
+	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
+
+	if (vbho == NULL)
+		return 0;
+
+	return !!(vbho->init_params.out_flags & flag);
+}
+
+int vboot_skip_display_init(void)
+{
+	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
+}
+
+int vboot_enable_developer(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
+}
+
+int vboot_enable_recovery(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
+}
+
 void vboot_reboot(void)
 {
 	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index 088cd1e..d7f14d0 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -40,4 +40,11 @@ struct vboot_components {
 int vboot_named_region_device(const char *name, struct region_device *rdev);
 int vboot_region_device(const struct region *reg, struct region_device *rdev);
 
+int vboot_get_handoff_info(void **addr, uint32_t *size);
+int vboot_skip_display_init(void);
+int vboot_enable_recovery(void);
+int vboot_enable_developer(void);
+
+void vboot_reboot(void);
+
 #endif /* VBOOT_COMMON_H */


From gerrit at coreboot.org  Wed Sep 23 19:43:00 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 23 Sep 2015 19:43:00 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos:
	vboot_common: Avoid code duplication when grabbing the handoff info
References: <I28f1decce98f988f90c446a3a0dbe7409d714527+0@gerrit.coreboot.org>
Message-ID: <I28f1decce98f988f90c446a3a0dbe7409d714527+4@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11498

-gerrit

commit ae95b235a8fd17d6358de32c3b0cbcb6a2e32ce1
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:44:56 2015 +0200

    chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
    
    vboot_handoff_flag was duplicating the logic to grab the handoff info, that is
    already made available with vboot_get_handoff_info.
    This uses vboot_get_handoff_info in vboot_handoff_flag instead.
    
    Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/vendorcode/google/chromeos/vboot_common.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 1c216d0..6184b0d 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -58,10 +58,9 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 static int vboot_handoff_flag(uint32_t flag)
 {
 	struct vboot_handoff *vbho;
+	uint32_t size;
 
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
-
-	if (vbho == NULL)
+	if (vboot_get_handoff_info((void **)&vbho, &size))
 		return 0;
 
 	return !!(vbho->init_params.out_flags & flag);


From gerrit at coreboot.org  Wed Sep 23 20:35:59 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Wed, 23 Sep 2015 20:35:59 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: WIP: ifdtool: Do
	proper ser/deser of descriptor
References: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+0@gerrit.coreboot.org>
Message-ID: <Iccc063d08beb2fcafe9af910a0b1b984fcbc134f+5@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11635

-gerrit

commit b1e36c38b40dff1c180c82dd5ba55edc1a59b214
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Sep 14 09:47:24 2015 -0700

    WIP: ifdtool: Do proper ser/deser of descriptor
    
    Change-Id: Iccc063d08beb2fcafe9af910a0b1b984fcbc134f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 util/ifdtool/Makefile      |   5 +-
 util/ifdtool/ifd_drv_bin.c | 126 +++++++++++++++++++++++++++++++++++++++++++++
 util/ifdtool/ifdtool.c     |  73 ++++++++++++++------------
 util/ifdtool/ifdtool.h     |  36 +++++++++++++
 4 files changed, 205 insertions(+), 35 deletions(-)

diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
index 02a02c4..c333e21 100644
--- a/util/ifdtool/Makefile
+++ b/util/ifdtool/Makefile
@@ -25,7 +25,10 @@ PREFIX  = /usr/local
 CFLAGS  = -O2 -g -Wall -W -Werror
 LDFLAGS =
 
-OBJS = ifdtool.o
+OBJS = ifdtool.o ifd_drv_bin.o
+
+# Until we have a better way to pull in commonlib, here it goes:
+CFLAGS += -I../../src/commonlib/include
 
 all: dep $(PROGRAM)
 
diff --git a/util/ifdtool/ifd_drv_bin.c b/util/ifdtool/ifd_drv_bin.c
new file mode 100644
index 0000000..04a7fe5
--- /dev/null
+++ b/util/ifdtool/ifd_drv_bin.c
@@ -0,0 +1,126 @@
+
+#include "ifdtool.h"
+
+#include <commonlib/endian.h>
+#include <stdlib.h>
+
+static void des_flmap0(struct flash_descriptor *desc, uint32_t flmap0)
+{
+	desc->num_regions = (flmap0 >> 24) & 7;
+	desc->frba_offset = ((flmap0 >> 16) & 0xff) << 4;
+	desc->num_components = ((flmap0 >> 8) & 0x3) + 1;
+	desc->fcba_offset = ((flmap0 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap0(const struct flash_descriptor *desc)
+{
+	uint32_t flmap0;
+
+	flmap0 = (desc->num_regions & 0x7) << 24;
+	flmap0 |= ((desc->frba_offset >> 4) & 0xff)  << 16;
+	flmap0 |= ((desc->num_components - 1) & 0x3) << 8;
+	flmap0 |= ((desc->fcba_offset >> 4) & 0xff) << 0;
+
+	return flmap0;
+}
+
+static void des_flmap1(struct flash_descriptor *desc, uint32_t flmap1)
+{
+	desc->num_pch_straps = (flmap1 >> 24) & 0xff;
+	desc->fpsba_offset = ((flmap1 >> 16) & 0xff) << 4;
+	desc->num_masters = (flmap1 >> 8) & 3;
+	desc->fmba_offset = ((flmap1 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap1(const struct flash_descriptor *desc)
+{
+	uint32_t flmap1;
+
+	flmap1 = (desc->num_pch_straps & 0xff) << 24;
+	flmap1 |= ((desc->fpsba_offset >> 4) & 0xff)  << 16;
+	flmap1 |= (desc->num_masters & 0x3) << 8;
+	flmap1 |= ((desc->fmba_offset >> 4) & 0xff) << 0;
+
+	return flmap1;
+}
+
+static void des_flmap2(struct flash_descriptor *desc, uint32_t flmap2)
+{
+	desc->iccriba_offset = ((flmap2 >> 16) & 0xff) << 4;
+	desc->num_pch_straps = (flmap2 >> 8) & 0xff;
+	desc->fmsba_offset = ((flmap2 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flmap2(const struct flash_descriptor *desc)
+{
+	uint32_t flmap2;
+
+	flmap2 = ((desc->iccriba_offset >> 4) & 0xff)  << 16;
+	flmap2 |= (desc->num_pch_straps & 0x3) << 8;
+	flmap2 |= ((desc->fmsba_offset >> 4) & 0xff) << 0;
+
+	return flmap2;
+}
+
+static void des_flumap1(struct flash_descriptor *desc, uint32_t flumap1)
+{
+	desc->vtba_len = ((flumap1 >> 8) & 0xff) / 2;
+	desc->vtba_offset = ((flumap1 >> 0) & 0xff) << 4;
+}
+
+static uint32_t ser_flumap1(const struct flash_descriptor *desc)
+{
+	uint32_t flumap1;
+
+	flumap1 = ((desc->vtba_len * 2) & 0xff) << 8;
+	flumap1 |= ((desc->vtba_offset >> 4) & 0xff) << 0;
+
+	return flumap1;
+}
+
+static void vscc_deserialize_jid(struct vscc_entry *vscc, uint32_t jid)
+{
+	vscc->spi_device_id[1] = (jid >> 16) & 0xff;
+	vscc->spi_device_id[0] = (jid >> 8) & 0xff;
+	vscc->spi_vendor_id = jid & 0xff;
+}
+
+static void deserialize_vtba(struct vscc_entry *vtba, uint8_t num_entries,
+			     const void *stream)
+{
+	size_t i;
+	const uint8_t *base = stream;
+
+	for (i = 0; i < num_entries; i++, base += 8) {
+		vtba[i].vscc = read_le32(base + 0);
+		vscc_deserialize_jid(vtba + i, read_le32(base + 4));
+	}
+}
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud)
+{
+	const uint8_t *ifd_regs = fud;
+
+	des_flmap0(desc, read_le32(ifd_regs + 0x04));
+	des_flmap1(desc, read_le32(ifd_regs + 0x08));
+	des_flmap2(desc, read_le32(ifd_regs + 0x0C));
+	des_flumap1(desc, read_le32(ifd_regs + 0xeec));
+
+	/* FIXME: check malloc result */
+	desc->vtba = malloc(desc->vtba_len * sizeof(*desc->vtba));
+	deserialize_vtba(desc->vtba, desc->vtba_len, ifd_regs + desc->vtba_offset);
+}
+
+void dont_compile_fail_me(void)
+{
+	des_flmap0(NULL, 0);
+	ser_flmap0(NULL);
+	des_flmap1(NULL, 0);
+	ser_flmap1(NULL);
+	des_flmap2(NULL, 0);
+	ser_flmap2(NULL);
+	des_flumap1(NULL, 0);
+	ser_flumap1(NULL);
+
+	vscc_deserialize_jid(NULL, 0);
+}
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index feaffa8..780c0ef 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -17,7 +17,9 @@
  * Foundation, Inc.
  */
 
+#include <commonlib/endian.h>
 #include <unistd.h>
+#include <stdbool.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -25,6 +27,7 @@
 #include <fcntl.h>
 #include <sys/types.h>
 #include <sys/stat.h>
+
 #include "ifdtool.h"
 
 #ifndef O_BINARY
@@ -45,15 +48,17 @@ static const struct region_name region_names[MAX_REGIONS] = {
 	{ "EC", "ec" },
 };
 
-static fdbar_t *find_fd(char *image, int size)
+static void *find_fd(void *image, size_t size)
 {
-	int i, found = 0;
+	size_t i;
+	bool found = false;
+	uint8_t *base = image;
 
 	/* Scan for FD signature */
 	for (i = 0; i < (size - 4); i += 4) {
-		if (*(uint32_t *) (image + i) == 0x0FF0A55A) {
-			found = 1;
-			break;	// signature found.
+		if (read_le32(base + i) == 0x0FF0A55A) {
+			found = true;
+			break;	/* signature found. */
 		}
 	}
 
@@ -62,7 +67,7 @@ static fdbar_t *find_fd(char *image, int size)
 		return NULL;
 	}
 
-	return (fdbar_t *) (image + i);
+	return base + i;
 }
 
 /*
@@ -221,7 +226,7 @@ static int region_num(const char *name)
 
 static const char *region_filename(int region_type)
 {
-	static const char *region_filenames[MAX_REGIONS] = {
+	static const char *region_filenames[9] = {
 		"flashregion_0_flashdescriptor.bin",
 		"flashregion_1_bios.bin",
 		"flashregion_2_intel_me.bin",
@@ -513,14 +518,14 @@ static void dump_fmsba(fmsba_t * fmsba)
 	printf("????:      0x%08x\n", fmsba->data[3]);
 }
 
-static void dump_jid(uint32_t jid)
+static void dump_jid(const struct vscc_entry *vscc)
 {
 	printf("    SPI Componend Device ID 1:          0x%02x\n",
-		(jid >> 16) & 0xff);
+		vscc->spi_device_id[1]);
 	printf("    SPI Componend Device ID 0:          0x%02x\n",
-		(jid >> 8) & 0xff);
+		vscc->spi_device_id[0]);
 	printf("    SPI Componend Vendor ID:            0x%02x\n",
-		jid & 0xff);
+		vscc->spi_vendor_id);
 }
 
 static void dump_vscc(uint32_t vscc)
@@ -574,17 +579,17 @@ static void dump_vscc(uint32_t vscc)
 	}
 }
 
-static void dump_vtba(vtba_t *vtba, int vtl)
+static void dump_vtba(struct vscc_entry *vtba, size_t vtba_len)
 {
 	int i;
-	int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8;
+	int num = vtba_len;
 
 	printf("ME VSCC table:\n");
 	for (i = 0; i < num; i++) {
-		printf("  JID%d:  0x%08x\n", i, vtba->entry[i].jid);
-		dump_jid(vtba->entry[i].jid);
-		printf("  VSCC%d: 0x%08x\n", i, vtba->entry[i].vscc);
-		dump_vscc(vtba->entry[i].vscc);
+		//printf("  JID%d:  0x%08x\n", i, vtba->entry[i].jid);
+		dump_jid(vtba + i);
+		printf("  VSCC%d: 0x%08x\n", i, vtba[i].vscc);
+		dump_vscc(vtba[i].vscc);
 	}
 	printf("\n");
 }
@@ -604,34 +609,34 @@ static void dump_oem(uint8_t *oem)
 
 static void dump_fd(char *image, int size)
 {
+	struct flash_descriptor desc;
 	fdbar_t *fdb = find_fd(image, size);
 	if (!fdb)
 		exit(EXIT_FAILURE);
 
+	read_flash_descriptor(&desc, fdb);
+
 	printf("FLMAP0:    0x%08x\n", fdb->flmap0);
-	printf("  NR:      %d\n", (fdb->flmap0 >> 24) & 7);
-	printf("  FRBA:    0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
-	printf("  NC:      %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
-	printf("  FCBA:    0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+	printf("  NR:      %d\n", desc.num_regions);
+	printf("  FRBA:    0x%x\n", desc.frba_offset);
+	printf("  NC:      %d\n", desc.num_components);
+	printf("  FCBA:    0x%x\n", desc.fcba_offset);
 
 	printf("FLMAP1:    0x%08x\n", fdb->flmap1);
-	printf("  ISL:     0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
-	printf("  FPSBA:   0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
-	printf("  NM:      %d\n", (fdb->flmap1 >> 8) & 3);
-	printf("  FMBA:    0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+	printf("  ISL:     0x%02x\n", desc.num_pch_straps);
+	printf("  FPSBA:   0x%x\n", desc.fpsba_offset);
+	printf("  NM:      %d\n", desc.num_masters);
+	printf("  FMBA:    0x%x\n", desc.fmba_offset);
 
 	printf("FLMAP2:    0x%08x\n", fdb->flmap2);
-	printf("  PSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
-	printf("  FMSBA:   0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+	printf("  PSL:     0x%04x\n", desc.num_cpu_straps);
+	printf("  FMSBA:   0x%x\n", desc.fmsba_offset);
 
 	printf("FLUMAP1:   0x%08x\n", fdb->flumap1);
-	printf("  Intel ME VSCC Table Length (VTL):        %d\n",
-		(fdb->flumap1 >> 8) & 0xff);
-	printf("  Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n",
-		(fdb->flumap1 & 0xff) << 4);
-	dump_vtba((vtba_t *)
-			(image + ((fdb->flumap1 & 0xff) << 4)),
-			(fdb->flumap1 >> 8) & 0xff);
+	printf("  Intel ME VSCC Table Length (VTL):        %d\n", desc.vtba_len);
+	printf("  Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n", desc.vtba_offset);
+
+	dump_vtba(desc.vtba, desc.vtba_len);
 	dump_oem((uint8_t *)image + 0xf00);
 	dump_frba((frba_t *)
 			(image + (((fdb->flmap0 >> 16) & 0xff) << 4)));
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index 195d91c..6bafd0d 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -130,6 +130,14 @@ typedef struct {
 	uint32_t vscc;
 } vscc_t;
 
+struct vscc_entry {
+	uint32_t vscc;
+	/* Jid */
+	uint8_t spi_device_id[2];
+	uint8_t spi_vendor_id;
+};
+
+
 typedef struct {
 	// Actual number of entries specified in vtl
 	vscc_t entry[8];
@@ -143,3 +151,31 @@ struct region_name {
 	char *pretty;
 	char *terse;
 };
+
+struct flash_descriptor
+{
+	/* FLMAP0 */
+	uint8_t num_regions;
+	uint16_t frba_offset;
+	uint8_t num_components;
+	uint16_t fcba_offset;
+
+	/* FLMAP1 */
+	uint8_t num_pch_straps;
+	uint16_t fpsba_offset;
+	uint8_t num_masters;
+	uint16_t fmba_offset;
+
+	/* FLMAP2 */
+	uint16_t iccriba_offset;
+	uint8_t num_cpu_straps;
+	uint16_t fmsba_offset;
+
+	/* FLUMAP1 */
+	uint8_t vtba_len;
+	uint16_t vtba_offset;
+
+	struct vscc_entry *vtba;
+};
+
+void read_flash_descriptor(struct flash_descriptor *desc, const void *fud);


From gerrit at coreboot.org  Thu Sep 24 01:03:01 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Thu, 24 Sep 2015 01:03:01 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: coreboot: move
	TS_END_ROMSTAGE to one spot
References: <I4b584e274ce2107e83ca6425491fdc71a138e82c+0@gerrit.coreboot.org>
Message-ID: <I4b584e274ce2107e83ca6425491fdc71a138e82c+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11700

-gerrit

commit f3d72499988331d669ba87ceafaea45c646b994e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 23 19:54:12 2015 -0500

    coreboot: move TS_END_ROMSTAGE to one spot
    
    While the romstage code flow is not consistent across all
    mainboards/chipsets there is only one way of running ramstage
    from romstage -- run_ramstage(). Move the
    timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados. TS_END_ROMSTAGE still present in
         timestamp table.
    
    Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/intel/haswell/romstage.c                     | 1 -
 src/lib/prog_loaders.c                               | 2 ++
 src/mainboard/advansus/a785e-i/romstage.c            | 2 --
 src/mainboard/amd/bimini_fam10/romstage.c            | 2 --
 src/mainboard/amd/mahogany_fam10/romstage.c          | 2 --
 src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 2 --
 src/mainboard/amd/tilapia_fam10/romstage.c           | 2 --
 src/mainboard/apple/macbook21/romstage.c             | 3 ---
 src/mainboard/asus/kfsn4-dre/romstage.c              | 2 --
 src/mainboard/asus/m4a78-em/romstage.c               | 2 --
 src/mainboard/asus/m4a785-m/romstage.c               | 2 --
 src/mainboard/asus/m5a88-v/romstage.c                | 2 --
 src/mainboard/avalue/eax-785e/romstage.c             | 2 --
 src/mainboard/gigabyte/ma785gm/romstage.c            | 2 --
 src/mainboard/gigabyte/ma785gmt/romstage.c           | 2 --
 src/mainboard/gigabyte/ma78gm/romstage.c             | 2 --
 src/mainboard/google/cosmos/romstage.c               | 2 --
 src/mainboard/google/daisy/romstage.c                | 2 --
 src/mainboard/google/link/romstage.c                 | 2 --
 src/mainboard/google/parrot/romstage.c               | 1 -
 src/mainboard/google/peach_pit/romstage.c            | 2 --
 src/mainboard/google/stout/romstage.c                | 1 -
 src/mainboard/google/veyron/romstage.c               | 2 --
 src/mainboard/google/veyron_brain/romstage.c         | 2 --
 src/mainboard/google/veyron_danger/romstage.c        | 2 --
 src/mainboard/google/veyron_mickey/romstage.c        | 2 --
 src/mainboard/google/veyron_rialto/romstage.c        | 2 --
 src/mainboard/google/veyron_romy/romstage.c          | 2 --
 src/mainboard/hp/dl165_g6_fam10/romstage.c           | 2 --
 src/mainboard/iei/kino-780am2-fam10/romstage.c       | 2 --
 src/mainboard/intel/cougar_canyon2/romstage.c        | 2 --
 src/mainboard/intel/emeraldlake2/romstage.c          | 1 -
 src/mainboard/jetway/pa78vm5/romstage.c              | 2 --
 src/mainboard/kontron/ktqm77/romstage.c              | 1 -
 src/mainboard/lenovo/t60/romstage.c                  | 2 --
 src/mainboard/lenovo/x201/romstage.c                 | 2 --
 src/mainboard/lenovo/x60/romstage.c                  | 3 ---
 src/mainboard/msi/ms9652_fam10/romstage.c            | 2 --
 src/mainboard/packardbell/ms2290/romstage.c          | 2 --
 src/mainboard/samsung/lumpy/romstage.c               | 1 -
 src/mainboard/samsung/stumpy/romstage.c              | 1 -
 src/mainboard/supermicro/h8dmr_fam10/romstage.c      | 2 --
 src/mainboard/supermicro/h8qme_fam10/romstage.c      | 2 --
 src/mainboard/supermicro/h8scm_fam10/romstage.c      | 2 --
 src/mainboard/tyan/s2912_fam10/romstage.c            | 2 --
 src/mainboard/via/epia-m850/romstage.c               | 1 -
 src/northbridge/intel/sandybridge/romstage_native.c  | 1 -
 src/soc/intel/baytrail/romstage/romstage.c           | 2 --
 src/soc/intel/broadwell/romstage/romstage.c          | 2 --
 src/soc/intel/common/romstage.c                      | 2 --
 src/soc/intel/fsp_baytrail/romstage/romstage.c       | 2 --
 src/southbridge/intel/fsp_rangeley/romstage.c        | 2 --
 52 files changed, 2 insertions(+), 95 deletions(-)

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 6adb8be..9c238ca 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -274,7 +274,6 @@ void romstage_common(const struct romstage_params *params)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(wake_from_s3);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
 
 static inline void prepare_for_resume(struct romstage_handoff *handoff)
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 2f4a2c1..e53fca5 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -96,6 +96,8 @@ void run_ramstage(void)
 	struct prog ramstage =
 		PROG_INIT(ASSET_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");
 
+	timestamp_add_now(TS_END_ROMSTAGE);
+
 	/* Only x86 systems currently take the same firmware path on resume. */
 	if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
 		run_ramstage_from_resume(romstage_handoff_find_or_add(),
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 2987db1..dfda22e 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 372074c..9e2e904 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -225,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb800_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 2836d67..c01ccf0 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 631534e..3d7c168 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -333,8 +333,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //	die("After MCT init before CAR disabled.");
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 12c9244..924345d 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 526d518..3f252ab 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -344,7 +344,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 }
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index cf36a72..b35473c 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -368,8 +368,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Restore default SuperIO access */
 	outb(0xaa, port);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 6e3f709..bcff9e4 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index c3bb1ca..e49c9b9 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index ca9d1b1..35e9e94 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -223,8 +223,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 71b2d5f..bace1d0 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -227,8 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 06b8d60..8ac24f9 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -221,8 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index c213d16..cd9b790 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -221,8 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 1cc2b11..6cb4227 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c
index e10b3ac..0f07354 100644
--- a/src/mainboard/google/cosmos/romstage.c
+++ b/src/mainboard/google/cosmos/romstage.c
@@ -53,7 +53,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c
index 6f3cb77..b559c85 100644
--- a/src/mainboard/google/daisy/romstage.c
+++ b/src/mainboard/google/daisy/romstage.c
@@ -179,7 +179,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index e9b4a09..aa36bc5 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -247,6 +247,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index a947c48..582d9e0 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -198,5 +198,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 635877b..d5fdfb1 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -278,7 +278,5 @@ void main(void)
 
 	simple_spi_test();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 31b61e2..3d18f18 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -252,5 +252,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
index 5ccbe3e..a8d8f7d 100644
--- a/src/mainboard/google/veyron/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
@@ -111,7 +111,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c
index f243235..e946cc6 100644
--- a/src/mainboard/google/veyron_brain/romstage.c
+++ b/src/mainboard/google/veyron_brain/romstage.c
@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c
index e9857b8..0c1bb31 100644
--- a/src/mainboard/google/veyron_danger/romstage.c
+++ b/src/mainboard/google/veyron_danger/romstage.c
@@ -106,7 +106,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c
index f243235..e946cc6 100644
--- a/src/mainboard/google/veyron_mickey/romstage.c
+++ b/src/mainboard/google/veyron_mickey/romstage.c
@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index 9cdacc3..e845a42 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -112,7 +112,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c
index f243235..e946cc6 100644
--- a/src/mainboard/google/veyron_romy/romstage.c
+++ b/src/mainboard/google/veyron_romy/romstage.c
@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index ff2ed10..62fd6cb 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -218,8 +218,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	bcm5785_early_setup();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();
 }
 
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index f822922..6df828b 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 92d0518..45da7d1 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -306,8 +306,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	*(u32*)cbmem_hob_ptr = (u32)HobListPtr;
 	post_code(0x4f);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index bcf498b..5bdbdc6 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -256,5 +256,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 3559642..ac66ada 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -229,8 +229,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 869e020..57f8542 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -243,5 +243,4 @@ void main(unsigned long bist)
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 280722f..16fa871 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -284,6 +284,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 1e335d3..4be1ead 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -310,6 +310,4 @@ void main(unsigned long bist)
 #if CONFIG_LPC_TPM
 	init_tpm(s3resume);
 #endif
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index e9cd80d..7765812 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -284,7 +284,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 }
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index ef35fc9..b8fca64 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -243,8 +243,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 82bacfe..074b31c 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -297,6 +297,4 @@ void main(unsigned long bist)
 		quick_ram_check();
 	}
 #endif
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 015ae08..f2d5f4c 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -274,5 +274,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 161c8d1..7fa93b8 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -284,5 +284,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 405ec2e..d94d917 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -240,8 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
 	post_code(0x42);     // Should never see this post code.
 }
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index f74decb..c79c2b1 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -304,8 +304,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();  /* BSP switch stack to ram, copy then execute CB. */
 	post_code(0x42);  /* Should never see this post code. */
 }
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 1c9fc8d..b3174ae 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sr5650_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 5f49a35..1049014 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 8912d13..b38cd71 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -96,7 +96,6 @@ void main(unsigned long bist)
 #if CONFIG_EARLY_CBMEM_INIT
 	cbmem_recovery(0);
 #endif
-	timestamp_add_now(TS_END_ROMSTAGE);
 	/* FIXME: See if this is needed or take this out please */
 	/* Disable Memcard and SDIO */
 	pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4));
diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c
index 45f671c..a18c480 100644
--- a/src/northbridge/intel/sandybridge/romstage_native.c
+++ b/src/northbridge/intel/sandybridge/romstage_native.c
@@ -135,5 +135,4 @@ void main(unsigned long bist)
 #endif
 
 	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 1b93eb6..8df022b 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -250,8 +250,6 @@ void romstage_common(struct romstage_params *params)
 
 void asmlinkage romstage_after_car(void)
 {
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 27fb0f2..bfda862 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -132,8 +132,6 @@ void romstage_common(struct romstage_params *params)
 
 void asmlinkage romstage_after_car(void)
 {
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index ee9c975..0d5e85f 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -207,8 +207,6 @@ asmlinkage void romstage_after_car(void *chipset_context)
 	soc_after_temp_ram_exit();
 	soc_display_mtrrs();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	die("ERROR - Failed to load ramstage!");
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index c40f163..b5384fa 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -267,8 +267,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x4f);
 
 	/* Load the ramstage. */
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 3500dfd..bc58b48 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -130,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
 	post_code(0x4e);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x4f);
 
 	/* Load the ramstage. */


From gerrit at coreboot.org  Thu Sep 24 14:03:47 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Thu, 24 Sep 2015 14:03:47 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Revert
	"coreboot_table: don't add CMOS checksum twice."
References: <I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db+0@gerrit.coreboot.org>
Message-ID: <I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db+2@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11696

-gerrit

commit be9e6455f4b8d6b37af68ec663bd245f0e82af82
Author: Nico Huber <nico.h at gmx.de>
Date:   Mon Sep 21 20:11:47 2015 +0200

    Revert "coreboot_table: don't add CMOS checksum twice."
    
    This reverts commit e6606518243d9beda31693d40493b5f7a1a3e2e0.
    
    After some discussion on IRC we decided to revert it as libpayload can
    only read the copy that was removed (and other users like nvramtool can
    only read the other copy). So we need both copies at this time.
    
    Signed-off-by: Nico Huber <nico.h at gmx.de>
    Change-Id: I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db
---
 src/lib/coreboot_table.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6859bf2..35341ab 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -34,6 +34,9 @@
 #include <cbmem.h>
 #include <bootmem.h>
 #include <spi_flash.h>
+#if CONFIG_USE_OPTION_TABLE
+#include <option_table.h>
+#endif
 #if CONFIG_CHROMEOS
 #if CONFIG_HAVE_ACPI_TABLES
 #include <arch/acpi.h>
@@ -333,6 +336,26 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 	return mainboard;
 }
 
+#if CONFIG_USE_OPTION_TABLE
+static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
+{
+	struct lb_record *rec;
+	struct cmos_checksum *cmos_checksum;
+	rec = lb_new_record(header);
+	cmos_checksum = (struct cmos_checksum *)rec;
+	cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM;
+
+	cmos_checksum->size = (sizeof(*cmos_checksum));
+
+	cmos_checksum->range_start = LB_CKS_RANGE_START * 8;
+	cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7;
+	cmos_checksum->location = LB_CKS_LOC * 8;
+	cmos_checksum->type = CHECKSUM_PCBIOS;
+
+	return cmos_checksum;
+}
+#endif
+
 static void lb_strings(struct lb_header *header)
 {
 	static const struct {
@@ -435,6 +458,8 @@ unsigned long write_coreboot_table(
 			struct lb_record *rec_dest = lb_new_record(head);
 			/* Copy the option config table, it's already a lb_record... */
 			memcpy(rec_dest,  option_table, option_table->size);
+			/* Create cmos checksum entry in coreboot table */
+			lb_cmos_checksum(head);
 		} else {
 			printk(BIOS_ERR, "cmos_layout.bin could not be found!\n");
 		}


From gerrit at coreboot.org  Thu Sep 24 15:00:39 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 24 Sep 2015 15:00:39 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos:
	vboot-related functions move to common vboot code
References: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+0@gerrit.coreboot.org>
Message-ID: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+5@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11497

-gerrit

commit 55ab32acfa234c042250f7324d388ffb5ca41b37
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:41:14 2015 +0200

    chromeos: vboot-related functions move to common vboot code
    
    This moves a few vboot-prefixed functions that were defined in chromeos.c to
    vboot_common.c, since those are only relevant to vboot and depend on the vboot
    handoff data. This allows more separation between CONFIG_CHROMEOS and what
    CONFIG_CHROMEOS selects, so that each separate option (such as
    CONFIG_VBOOT_VERIFY_FIRMWARE) can be enabled separately.
    
    Thus, the actual definitions of these functions will only be declared when
    CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling
    vboot_skip_display_init in bootmode was also adapted.
    
    Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/vendorcode/google/chromeos/chromeos.c     | 32 ---------------------------
 src/vendorcode/google/chromeos/chromeos.h     | 16 --------------
 src/vendorcode/google/chromeos/vboot_common.c | 27 ++++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot_common.h |  8 +++++++
 4 files changed, 35 insertions(+), 48 deletions(-)

diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index c2190b7..4864b8c 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -20,38 +20,6 @@
 #include <stddef.h>
 #include <string.h>
 #include "chromeos.h"
-#include <boot/coreboot_tables.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include "vboot_handoff.h"
-
-static int vboot_handoff_flag(uint32_t flag)
-{
-	struct vboot_handoff *vbho;
-
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
-
-	if (vbho == NULL)
-		return 0;
-
-	return !!(vbho->init_params.out_flags & flag);
-}
-
-int vboot_skip_display_init(void)
-{
-	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
-}
-
-int vboot_enable_developer(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
-}
-
-int vboot_enable_recovery(void)
-{
-	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
-}
 
 int __attribute__((weak)) clear_recovery_mode_switch(void)
 {
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index 798ab3e..bdc9435 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -45,29 +45,14 @@ void elog_add_boot_reason(void);
 /* functions implemented in watchdog.c */
 void elog_add_watchdog_reset(void);
 void reboot_from_watchdog(void);
-
-int vboot_enable_developer(void);
-int vboot_enable_recovery(void);
-int vboot_skip_display_init(void);
 #else
 static inline void elog_add_boot_reason(void) { return; }
 static inline void elog_add_watchdog_reset(void) { return; }
 static inline void reboot_from_watchdog(void) { return; }
-static inline int vboot_skip_display_init(void) { return 0; }
 #endif /* CONFIG_CHROMEOS */
 
 struct romstage_handoff;
 
-#if CONFIG_VBOOT_VERIFY_FIRMWARE
-/* Returns 0 on success < 0 on error. */
-int vboot_get_handoff_info(void **addr, uint32_t *size);
-#else /* CONFIG_VBOOT_VERIFY_FIRMWARE */
-static inline int vboot_get_handoff_info(void **addr, uint32_t *size)
-{
-	return -1;
-}
-#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
-
 #include "gnvs.h"
 struct device;
 
@@ -84,6 +69,5 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {}
 #endif /* CONFIG_CHROMEOS_RAMOOPS */
 
 void cbmem_add_vpd_calibration_data(void);
-void vboot_reboot(void);
 
 #endif /* __CHROMEOS_H__ */
diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 2fd29b6..1c216d0 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -55,6 +55,33 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 	return 0;
 }
 
+static int vboot_handoff_flag(uint32_t flag)
+{
+	struct vboot_handoff *vbho;
+
+	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
+
+	if (vbho == NULL)
+		return 0;
+
+	return !!(vbho->init_params.out_flags & flag);
+}
+
+int vboot_skip_display_init(void)
+{
+	return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
+}
+
+int vboot_enable_developer(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
+}
+
+int vboot_enable_recovery(void)
+{
+	return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
+}
+
 void vboot_reboot(void)
 {
 	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index 088cd1e..f4d5e11 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -39,5 +39,13 @@ struct vboot_components {
 /* The following functions return 0 on success, < 0 on error. */
 int vboot_named_region_device(const char *name, struct region_device *rdev);
 int vboot_region_device(const struct region *reg, struct region_device *rdev);
+int vboot_get_handoff_info(void **addr, uint32_t *size);
+
+/* The following functions return 1 for true and 0 for false. */
+int vboot_skip_display_init(void);
+int vboot_enable_recovery(void);
+int vboot_enable_developer(void);
+
+void vboot_reboot(void);
 
 #endif /* VBOOT_COMMON_H */


From gerrit at coreboot.org  Thu Sep 24 15:33:01 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 24 Sep 2015 15:33:01 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: armv7:
	Word-sized/half-word-sized memory operations for 32/16 bit
	read/write
References: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+0@gerrit.coreboot.org>
Message-ID: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+3@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698

-gerrit

commit 37e8c260792a9d3e6c158b0d5e09b10d044a0447
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Tue Sep 22 22:16:33 2015 +0200

    armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
    
    Some registers only allow word-sized or half-word-sized operations and will
    cause a data fault when accessed with byte-sized operations.
    However, the compiler may or may not break such an operation into smaller
    (byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
    32 bit read/write and half-word-sized operations for 16 bit read/write.
    
    This is particularly the case on the rk3288 SRAM registers, where the watchdog
    tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
    compiler, where a 32 bit read would be broken into byte-sized chunks, which
    caused a data fault when accessing the watchdog tombstone register.
    
    The definitions for byte-sized memory operations are also adapted to stay
    consistent with the rest.
    
    Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/arch/arm/include/armv7/arch/io.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..eb9e1b7 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -30,39 +30,39 @@
 static inline uint8_t read8(const void *addr)
 {
 	dmb();
-	return *(volatile uint8_t *)addr;
+	return *(_Atomic volatile uint8_t *)addr;
 }
 
 static inline uint16_t read16(const void *addr)
 {
 	dmb();
-	return *(volatile uint16_t *)addr;
+	return *(_Atomic volatile uint16_t *)addr;
 }
 
 static inline uint32_t read32(const void *addr)
 {
 	dmb();
-	return *(volatile uint32_t *)addr;
+	return *(_Atomic volatile uint32_t *)addr;
 }
 
 static inline void write8(void *addr, uint8_t val)
 {
 	dmb();
-	*(volatile uint8_t *)addr = val;
+	*(_Atomic volatile uint8_t *)addr = val;
 	dmb();
 }
 
 static inline void write16(void *addr, uint16_t val)
 {
 	dmb();
-	*(volatile uint16_t *)addr = val;
+	*(_Atomic volatile uint16_t *)addr = val;
 	dmb();
 }
 
 static inline void write32(void *addr, uint32_t val)
 {
 	dmb();
-	*(volatile uint32_t *)addr = val;
+	*(_Atomic volatile uint32_t *)addr = val;
 	dmb();
 }
 


From gerrit at coreboot.org  Thu Sep 24 16:12:48 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 24 Sep 2015 16:12:48 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: coreboot: move
	TS_END_ROMSTAGE to one spot
References: <I4b584e274ce2107e83ca6425491fdc71a138e82c+0@gerrit.coreboot.org>
Message-ID: <E1Zf98a-0005ID-Hq@mail.coreboot.org>

the following patch was just integrated into master:
commit 9796f60c62f57ac512f225809c10b5b09ef80f5a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 23 19:54:12 2015 -0500

    coreboot: move TS_END_ROMSTAGE to one spot
    
    While the romstage code flow is not consistent across all
    mainboards/chipsets there is only one way of running ramstage
    from romstage -- run_ramstage(). Move the
    timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados. TS_END_ROMSTAGE still present in
         timestamp table.
    
    Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11700
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11700 for details.

-gerrit


From gerrit at coreboot.org  Thu Sep 24 16:16:55 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Thu, 24 Sep 2015 16:16:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+5@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit f59bbe0027147f9ca02763d1b4130e91083cd29f
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                               | 23 ++++++-------
 src/cpu/amd/model_10xxx/Makefile.inc               |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c           |  3 --
 src/cpu/amd/model_fxx/Makefile.inc                 |  2 +-
 src/cpu/intel/ep80579/Makefile.inc                 |  2 --
 src/cpu/intel/ep80579/microcode_blob.c             |  8 -----
 src/cpu/intel/fsp_model_206ax/Kconfig              |  5 ---
 src/cpu/intel/fsp_model_206ax/Makefile.inc         |  9 ++---
 src/cpu/intel/fsp_model_206ax/microcode_blob.c     | 22 -------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h     | 33 -------------------
 src/cpu/intel/fsp_model_406dx/Kconfig              |  4 ---
 src/cpu/intel/fsp_model_406dx/Makefile.inc         | 10 ++----
 src/cpu/intel/fsp_model_406dx/microcode_blob.c     | 29 -----------------
 src/cpu/intel/haswell/Makefile.inc                 |  5 +--
 src/cpu/intel/haswell/microcode_blob.c             | 30 -----------------
 src/cpu/intel/model_1067x/Makefile.inc             |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c         |  3 --
 src/cpu/intel/model_106cx/Makefile.inc             |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c         |  3 --
 src/cpu/intel/model_2065x/Makefile.inc             |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c         | 22 -------------
 src/cpu/intel/model_206ax/Makefile.inc             |  3 +-
 src/cpu/intel/model_206ax/microcode_blob.c         | 23 -------------
 src/cpu/intel/model_65x/Makefile.inc               |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c           |  3 --
 src/cpu/intel/model_67x/Makefile.inc               |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c           |  3 --
 src/cpu/intel/model_68x/Makefile.inc               |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c           |  3 --
 src/cpu/intel/model_69x/Makefile.inc               |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c           |  3 --
 src/cpu/intel/model_6bx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6dx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6ex/Makefile.inc               |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c           |  3 --
 src/cpu/intel/model_6fx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6xx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c           |  3 --
 src/cpu/intel/model_f0x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f1x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f2x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f3x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c           |  3 --
 src/cpu/intel/model_f4x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c           |  3 --
 src/cpu/via/nano/Makefile.inc                      |  4 +--
 src/soc/intel/baytrail/Makefile.inc                |  3 +-
 src/soc/intel/baytrail/microcode/Makefile.inc      |  1 -
 src/soc/intel/baytrail/microcode/microcode_blob.c  |  3 --
 src/soc/intel/braswell/Makefile.inc                |  3 +-
 src/soc/intel/braswell/microcode/Makefile.inc      |  2 --
 src/soc/intel/braswell/microcode/microcode_blob.c  | 22 -------------
 src/soc/intel/broadwell/Makefile.inc               |  3 +-
 src/soc/intel/broadwell/microcode/Makefile.inc     |  1 -
 src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
 src/soc/intel/fsp_baytrail/Makefile.inc            |  3 +-
 src/soc/intel/fsp_baytrail/microcode/Makefile.inc  | 26 ---------------
 .../intel/fsp_baytrail/microcode/microcode_blob.c  | 38 ----------------------
 .../intel/fsp_baytrail/microcode/microcode_size.h  |  6 ----
 src/soc/intel/skylake/Makefile.inc                 |  3 +-
 src/soc/intel/skylake/microcode/Makefile.inc       |  2 --
 src/soc/intel/skylake/microcode/microcode_blob.c   | 24 --------------
 68 files changed, 50 insertions(+), 436 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e8c5022..ce1112c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -54,6 +53,8 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index eda9f76..cf1fa50 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -52,6 +51,8 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 183c40f..b354e8c 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -74,6 +73,8 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 45ea3e4..ebc2cc5 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
 
 ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -60,6 +59,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
 ramstage-y += placeholders.c
 ramstage-y += i2c.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
-		/*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
-	#include "M0230672228.h"  // M0230672: Bay Trail "Super SKU" B0/B1
-	#include "M0130673322.h"  // M0130673: Bay Trail I B2 / B3
-	#include "M0130679901.h"  // M0130679: Bay Trail I D0
-#else
-	/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
-	#include "M0C30678829.h"  // M0C30678: Bay Trail M D Stepping
-#endif	/* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif	/* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	#define MICROCODE_REGION_LENGTH 0x30000
-#else
-	#define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 38668da..b74f353 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-


From gerrit at coreboot.org  Thu Sep 24 16:17:01 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Thu, 24 Sep 2015 16:17:01 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: 3dparty/blobs:
	Advance to pull in binary microcode
References: <I2071586e1f3b4464464928c11475f9283084dbcd+0@gerrit.coreboot.org>
Message-ID: <I2071586e1f3b4464464928c11475f9283084dbcd+2@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11693

-gerrit

commit 95bb6a9011567a03908d3e22737b461ac1c20f5d
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sun Sep 20 21:08:05 2015 -0700

    3dparty/blobs: Advance to pull in binary microcode
    
    Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 3rdparty/blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index b4ade40..df1f219 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7
+Subproject commit df1f21931c75aae9ee14cdc52da57783a6e0a9ad


From gerrit at coreboot.org  Thu Sep 24 16:44:30 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Thu, 24 Sep 2015 16:44:30 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: gma:
	Consolidate Intel IGD ACPI code some more
References: <Id3663bf588458e1e71920b96a3149f96947921e9+0@gerrit.coreboot.org>
Message-ID: <Id3663bf588458e1e71920b96a3149f96947921e9+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11702

-gerrit

commit 3f240162bdc69e06955309df6df542d1cdff60d2
Author: Nico Huber <nico.huber at secunet.com>
Date:   Thu Aug 27 15:07:03 2015 +0200

    gma: Consolidate Intel IGD ACPI code some more
    
    Consolidate some common (and mostly broken) code. Will try to fix things
    in separate commits.
    
    Maybe, igd.asl taken from gm45 (the non-PCH case) could also be used for
    i945 and sch. But this needs further investigation.
    
    Change-Id: Id3663bf588458e1e71920b96a3149f96947921e9
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/drivers/intel/gma/acpi/common.asl              | 112 +++++++++++++++++++++
 src/drivers/intel/gma/acpi/non-pch.asl             |  77 ++++++++++++++
 src/drivers/intel/gma/acpi/pch.asl                 |  78 ++++++++++++++
 src/drivers/intel/gma/igd.asl                      | 112 ---------------------
 src/northbridge/intel/fsp_sandybridge/acpi/igd.asl |  78 --------------
 .../intel/fsp_sandybridge/acpi/sandybridge.asl     |   2 +-
 src/northbridge/intel/gm45/acpi/gm45.asl           |   2 +-
 src/northbridge/intel/gm45/acpi/igd.asl            |  77 --------------
 src/northbridge/intel/haswell/acpi/haswell.asl     |   2 +-
 src/northbridge/intel/haswell/acpi/igd.asl         |  78 --------------
 src/northbridge/intel/i945/acpi/igd.asl            |   4 +-
 src/northbridge/intel/nehalem/acpi/igd.asl         |  78 --------------
 src/northbridge/intel/nehalem/acpi/nehalem.asl     |   2 +-
 src/northbridge/intel/sandybridge/acpi/igd.asl     |  78 --------------
 .../intel/sandybridge/acpi/sandybridge.asl         |   2 +-
 src/northbridge/intel/sch/acpi/igd.asl             |   2 +-
 16 files changed, 275 insertions(+), 509 deletions(-)

diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl
new file mode 100644
index 0000000..88cc2cd
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/common.asl
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+	External(LCD0, DeviceObj)
+
+	Name (BRCT, 0)
+
+	Method(BRID, 1, NotSerialized)
+	{
+		Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
+		If (LEqual (Local0, Ones))
+		{
+			Return (Subtract(SizeOf(BRIG), One))
+		}
+		Return (Local0)
+	}
+
+	Method (XBCL, 0, NotSerialized)
+	{
+		Store (1, BRCT)
+		Return (BRIG)
+	}
+
+	/* Display Output Switching */
+	Method (_DOS, 1)
+	{
+		/* Windows 2000 and Windows XP call _DOS to enable/disable
+		 * Display Output Switching during init and while a switch
+		 * is already active
+		 */
+		Store (And(Arg0, 7), DSEN)
+	}
+
+	/* Using Notify is the right way. But Windows doesn't handle
+	   it well. So use both method in a way to avoid double action.
+	 */
+	Method (DECB, 0, NotSerialized)
+	{
+		If (BRCT)
+		{
+			Notify (LCD0, 0x87)
+		} Else {
+			Store (BRID (XBQC ()), Local0)
+			If (LNotEqual (Local0, 2))
+			{
+				Decrement (Local0)
+			}
+			XBCM (DerefOf (Index (BRIG, Local0)))
+		}
+	}
+
+	Method (INCB, 0, NotSerialized)
+	{
+		If (BRCT)
+		{
+			Notify (LCD0, 0x86)
+		} Else {
+			Store (BRID (XBQC ()), Local0)
+			If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One)))
+			{
+				Increment (Local0)
+			}
+			XBCM (DerefOf (Index (BRIG, Local0)))
+		}
+	}
+
+	/* Device Current Status */
+	Method(XDCS, 1)
+	{
+		TRAP(1)
+		If (And(CSTE, ShiftLeft (1, Arg0))) {
+			Return (0x1f)
+		}
+		Return(0x1d)
+	}
+
+	/* Query Device Graphics State */
+	Method(XDGS, 1)
+	{
+		If (And(NSTE, ShiftLeft (1, Arg0))) {
+			Return(1)
+		}
+		Return(0)
+	}
+
+	/* Device Set State */
+	Method(XDSS, 2)
+	{
+		/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+		 * display switch was completed
+		 */
+		If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+			Store (NSTE, CSTE)
+		}
+	}
diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl
new file mode 100644
index 0000000..4c9e1ed
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/non-pch.asl
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device (GFX0)
+{
+	Name (_ADR, 0x00020000)
+
+	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+	Field (GFXC, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x10),
+		BAR0, 64
+	}
+
+	OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
+	Field (GFRG, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x61250),
+			CR1, 32,
+			BCLV, 16,
+			BCLM, 16,
+	}
+
+	Name (BRIG, Package (0x12)
+	{
+		0x61,
+		0x61,
+		0x2,
+		0x4,
+		0x5,
+		0x7,
+		0x9,
+		0xb,
+		0xd,
+		0x11,
+		0x14,
+		0x17,
+		0x1c,
+		0x20,
+		0x27,
+		0x31,
+		0x41,
+		0x61,
+	})
+
+	Method (XBCM, 1, NotSerialized)
+	{
+		Store (ShiftLeft (Arg0, 4), BCLV)
+		Store (0x80000000, CR1)
+		Store (0x0610, BCLM)
+	}
+
+	Method (XBQC, 0, NotSerialized)
+	{
+		Store (BCLV, Local0)
+		ShiftRight (Local0, 4, Local0)
+		Return (Local0)
+	}
+#include "common.asl"
+}
diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl
new file mode 100644
index 0000000..70ab6f6
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/pch.asl
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device (GFX0)
+{
+	Name (_ADR, 0x00020000)
+
+	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+	Field (GFXC, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x10),
+			BAR0, 64
+	}
+
+	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+	Field (GFRG, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x48254),
+			BCLV, 16,
+		Offset (0xc8250),
+			CR1, 32,
+			CR2, 32
+	}
+
+	Name (BRIG, Package (0x12)
+	{
+		0x61,
+		0x61,
+		0x2,
+		0x4,
+		0x5,
+		0x7,
+		0x9,
+		0xb,
+		0xd,
+		0x11,
+		0x14,
+		0x17,
+		0x1c,
+		0x20,
+		0x27,
+		0x31,
+		0x41,
+		0x61,
+	})
+
+	Method (XBCM, 1, NotSerialized)
+	{
+		Store (ShiftLeft (Arg0, 4), BCLV)
+		Store (0x80000000, CR1)
+		Store (0x061a061a, CR2)
+	}
+
+	Method (XBQC, 0, NotSerialized)
+	{
+		Store (BCLV, Local0)
+		ShiftRight (Local0, 4, Local0)
+		Return (Local0)
+	}
+#include "common.asl"
+}
diff --git a/src/drivers/intel/gma/igd.asl b/src/drivers/intel/gma/igd.asl
deleted file mode 100644
index 88cc2cd..0000000
--- a/src/drivers/intel/gma/igd.asl
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-	External(LCD0, DeviceObj)
-
-	Name (BRCT, 0)
-
-	Method(BRID, 1, NotSerialized)
-	{
-		Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
-		If (LEqual (Local0, Ones))
-		{
-			Return (Subtract(SizeOf(BRIG), One))
-		}
-		Return (Local0)
-	}
-
-	Method (XBCL, 0, NotSerialized)
-	{
-		Store (1, BRCT)
-		Return (BRIG)
-	}
-
-	/* Display Output Switching */
-	Method (_DOS, 1)
-	{
-		/* Windows 2000 and Windows XP call _DOS to enable/disable
-		 * Display Output Switching during init and while a switch
-		 * is already active
-		 */
-		Store (And(Arg0, 7), DSEN)
-	}
-
-	/* Using Notify is the right way. But Windows doesn't handle
-	   it well. So use both method in a way to avoid double action.
-	 */
-	Method (DECB, 0, NotSerialized)
-	{
-		If (BRCT)
-		{
-			Notify (LCD0, 0x87)
-		} Else {
-			Store (BRID (XBQC ()), Local0)
-			If (LNotEqual (Local0, 2))
-			{
-				Decrement (Local0)
-			}
-			XBCM (DerefOf (Index (BRIG, Local0)))
-		}
-	}
-
-	Method (INCB, 0, NotSerialized)
-	{
-		If (BRCT)
-		{
-			Notify (LCD0, 0x86)
-		} Else {
-			Store (BRID (XBQC ()), Local0)
-			If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One)))
-			{
-				Increment (Local0)
-			}
-			XBCM (DerefOf (Index (BRIG, Local0)))
-		}
-	}
-
-	/* Device Current Status */
-	Method(XDCS, 1)
-	{
-		TRAP(1)
-		If (And(CSTE, ShiftLeft (1, Arg0))) {
-			Return (0x1f)
-		}
-		Return(0x1d)
-	}
-
-	/* Query Device Graphics State */
-	Method(XDGS, 1)
-	{
-		If (And(NSTE, ShiftLeft (1, Arg0))) {
-			Return(1)
-		}
-		Return(0)
-	}
-
-	/* Device Set State */
-	Method(XDSS, 2)
-	{
-		/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
-		 * display switch was completed
-		 */
-		If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
-			Store (NSTE, CSTE)
-		}
-	}
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl
deleted file mode 100644
index df8a389..0000000
--- a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
-	Name (_ADR, 0x00020000)
-
-	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
-	Field (GFXC, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-		BAR0, 64
-	}
-
-	OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
-	Field (GFRG, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x48254),
-			BCLV, 16,
-		Offset (0xc8250),
-			CR1, 32,
-			CR2, 32
-	}
-
-	Name (BRIG, Package (0x12)
-	{
-		0x61,
-		0x61,
-		0x2,
-		0x4,
-		0x5,
-		0x7,
-		0x9,
-		0xb,
-		0xd,
-		0x11,
-		0x14,
-		0x17,
-		0x1c,
-		0x20,
-		0x27,
-		0x31,
-		0x41,
-		0x61,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (ShiftLeft (Arg0, 4), BCLV)
-		Store (0x80000000, CR1)
-		Store (0x061a061a, CR2)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		Store (BCLV, Local0)
-		ShiftRight (Local0, 4, Local0)
-		Return (Local0)
-	}
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
index 1c853e1..b7595f2 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
@@ -55,4 +55,4 @@ Device (PDRC)
 }
 
 // Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/pch.asl>
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index 5181866..8885f0e 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -79,4 +79,4 @@ Device (PDRC)
 #include "peg.asl"
 
 // Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/non-pch.asl>
diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl
deleted file mode 100644
index 696cc2b..0000000
--- a/src/northbridge/intel/gm45/acpi/igd.asl
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
-	Name (_ADR, 0x00020000)
-
-	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
-	Field (GFXC, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-		BAR0, 64
-	}
-
-	OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
-	Field (GFRG, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x61250),
-			CR1, 32,
-			BCLV, 16,
-			BCLM, 16,
-	}
-
-	Name (BRIG, Package (0x12)
-	{
-		0x61,
-		0x61,
-		0x2,
-		0x4,
-		0x5,
-		0x7,
-		0x9,
-		0xb,
-		0xd,
-		0x11,
-		0x14,
-		0x17,
-		0x1c,
-		0x20,
-		0x27,
-		0x31,
-		0x41,
-		0x61,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (ShiftLeft (Arg0, 4), BCLV)
-		Store (0x80000000, CR1)
-		Store (0x0610, BCLM)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		Store (BCLV, Local0)
-		ShiftRight (Local0, 4, Local0)
-		Return (Local0)
-	}
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl
index b9e2c8a..0d4f923 100644
--- a/src/northbridge/intel/haswell/acpi/haswell.asl
+++ b/src/northbridge/intel/haswell/acpi/haswell.asl
@@ -51,4 +51,4 @@ Device (PDRC)
 }
 
 // Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/pch.asl>
diff --git a/src/northbridge/intel/haswell/acpi/igd.asl b/src/northbridge/intel/haswell/acpi/igd.asl
deleted file mode 100644
index df8a389..0000000
--- a/src/northbridge/intel/haswell/acpi/igd.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
-	Name (_ADR, 0x00020000)
-
-	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
-	Field (GFXC, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-		BAR0, 64
-	}
-
-	OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
-	Field (GFRG, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x48254),
-			BCLV, 16,
-		Offset (0xc8250),
-			CR1, 32,
-			CR2, 32
-	}
-
-	Name (BRIG, Package (0x12)
-	{
-		0x61,
-		0x61,
-		0x2,
-		0x4,
-		0x5,
-		0x7,
-		0x9,
-		0xb,
-		0xd,
-		0x11,
-		0x14,
-		0x17,
-		0x1c,
-		0x20,
-		0x27,
-		0x31,
-		0x41,
-		0x61,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (ShiftLeft (Arg0, 4), BCLV)
-		Store (0x80000000, CR1)
-		Store (0x061a061a, CR2)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		Store (BCLV, Local0)
-		ShiftRight (Local0, 4, Local0)
-		Return (Local0)
-	}
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl
index fb89e55..079d3ab 100644
--- a/src/northbridge/intel/i945/acpi/igd.asl
+++ b/src/northbridge/intel/i945/acpi/igd.asl
@@ -58,7 +58,7 @@ Device (GFX0)
 		ShiftRight (Local0, 4, Local0)
 		Return (Local0)
 	}
-#include <drivers/intel/gma/igd.asl>
+#include <drivers/intel/gma/acpi/common.asl>
 }
 
 Device (DSPC)
@@ -70,4 +70,4 @@ Device (DSPC)
 		Offset (0xf4),
 		       BRTC, 8
 	}
-}
\ No newline at end of file
+}
diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl
deleted file mode 100644
index df8a389..0000000
--- a/src/northbridge/intel/nehalem/acpi/igd.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
-	Name (_ADR, 0x00020000)
-
-	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
-	Field (GFXC, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-		BAR0, 64
-	}
-
-	OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
-	Field (GFRG, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x48254),
-			BCLV, 16,
-		Offset (0xc8250),
-			CR1, 32,
-			CR2, 32
-	}
-
-	Name (BRIG, Package (0x12)
-	{
-		0x61,
-		0x61,
-		0x2,
-		0x4,
-		0x5,
-		0x7,
-		0x9,
-		0xb,
-		0xd,
-		0x11,
-		0x14,
-		0x17,
-		0x1c,
-		0x20,
-		0x27,
-		0x31,
-		0x41,
-		0x61,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (ShiftLeft (Arg0, 4), BCLV)
-		Store (0x80000000, CR1)
-		Store (0x061a061a, CR2)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		Store (BCLV, Local0)
-		ShiftRight (Local0, 4, Local0)
-		Return (Local0)
-	}
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl
index 4e1a593..bb9d78d 100644
--- a/src/northbridge/intel/nehalem/acpi/nehalem.asl
+++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl
@@ -55,4 +55,4 @@ Device (PDRC)
 }
 
 // Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/pch.asl>
diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl
deleted file mode 100644
index 6b02765..0000000
--- a/src/northbridge/intel/sandybridge/acpi/igd.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
-	Name (_ADR, 0x00020000)
-
-	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
-	Field (GFXC, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-			BAR0, 64
-	}
-
-	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
-	Field (GFRG, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x48254),
-			BCLV, 16,
-		Offset (0xc8250),
-			CR1, 32,
-			CR2, 32
-	}
-
-	Name (BRIG, Package (0x12)
-	{
-		0x61,
-		0x61,
-		0x2,
-		0x4,
-		0x5,
-		0x7,
-		0x9,
-		0xb,
-		0xd,
-		0x11,
-		0x14,
-		0x17,
-		0x1c,
-		0x20,
-		0x27,
-		0x31,
-		0x41,
-		0x61,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (ShiftLeft (Arg0, 4), BCLV)
-		Store (0x80000000, CR1)
-		Store (0x061a061a, CR2)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		Store (BCLV, Local0)
-		ShiftRight (Local0, 4, Local0)
-		Return (Local0)
-	}
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 742b0f1..5aafcc1 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -55,4 +55,4 @@ Device (PDRC)
 }
 
 // Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/pch.asl>
diff --git a/src/northbridge/intel/sch/acpi/igd.asl b/src/northbridge/intel/sch/acpi/igd.asl
index 696cc2b..dfb567b 100644
--- a/src/northbridge/intel/sch/acpi/igd.asl
+++ b/src/northbridge/intel/sch/acpi/igd.asl
@@ -73,5 +73,5 @@ Device (GFX0)
 		ShiftRight (Local0, 4, Local0)
 		Return (Local0)
 	}
-#include <drivers/intel/gma/igd.asl>
+#include <drivers/intel/gma/acpi/common.asl>
 }


From gerrit at coreboot.org  Thu Sep 24 16:44:31 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Thu, 24 Sep 2015 16:44:31 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: gma ACPI:
	Consolidate non-PCH and PCH brightness levels
References: <I9216a953bb89458ed102c39194ea370cbf463d5e+0@gerrit.coreboot.org>
Message-ID: <I9216a953bb89458ed102c39194ea370cbf463d5e+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11703

-gerrit

commit 6f2fb307f074bdc7bbb8c8e0709f434ea6ab8eed
Author: Nico Huber <nico.huber at secunet.com>
Date:   Thu Sep 24 17:45:45 2015 +0200

    gma ACPI: Consolidate non-PCH and PCH brightness levels
    
    The two cases only differ in the register locations.
    
    As the values in BRIG were all the same, consolidate them. They also
    got normalized to percentages as the ACPI spec wants that (0x61 was 100%
    before).
    
    Change-Id: I9216a953bb89458ed102c39194ea370cbf463d5e
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/drivers/intel/gma/acpi/brightness_levels.asl | 35 ++++++++++++++++++
 src/drivers/intel/gma/acpi/non-pch.asl           | 45 ++++--------------------
 src/drivers/intel/gma/acpi/pch.asl               | 45 ++++--------------------
 3 files changed, 47 insertions(+), 78 deletions(-)

diff --git a/src/drivers/intel/gma/acpi/brightness_levels.asl b/src/drivers/intel/gma/acpi/brightness_levels.asl
new file mode 100644
index 0000000..c186989
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/brightness_levels.asl
@@ -0,0 +1,35 @@
+	Name (BRIG, Package (0x12)
+	{
+		100, /* default AC */
+		100, /* default Battery */
+		  2,
+		  4,
+		  5,
+		  7,
+		  9,
+		 11,
+		 13,
+		 18,
+		 20,
+		 24,
+		 29,
+		 33,
+		 40,
+		 50,
+		 67,
+		100,
+	})
+
+	Method (XBCM, 1, NotSerialized)
+	{
+		Store (ShiftLeft (Arg0, 4), BCLV)
+		Store (0x80000000, CR1)
+		Store (0x0610, BCLM)
+	}
+
+	Method (XBQC, 0, NotSerialized)
+	{
+		Store (BCLV, Local0)
+		ShiftRight (Local0, 4, Local0)
+		Return (Local0)
+	}
diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl
index 4c9e1ed..c445c97 100644
--- a/src/drivers/intel/gma/acpi/non-pch.asl
+++ b/src/drivers/intel/gma/acpi/non-pch.asl
@@ -29,49 +29,16 @@ Device (GFX0)
 		BAR0, 64
 	}
 
-	OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
+	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
 	Field (GFRG, DWordAcc, NoLock, Preserve)
 	{
 		Offset (0x61250),
-			CR1, 32,
-			BCLV, 16,
-			BCLM, 16,
+		CR1, 32,
+		Offset (0x61254),
+		BCLV, 16,
+		BCLM, 16,
 	}
 
-	Name (BRIG, Package (0x12)
-	{
-		0x61,
-		0x61,
-		0x2,
-		0x4,
-		0x5,
-		0x7,
-		0x9,
-		0xb,
-		0xd,
-		0x11,
-		0x14,
-		0x17,
-		0x1c,
-		0x20,
-		0x27,
-		0x31,
-		0x41,
-		0x61,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (ShiftLeft (Arg0, 4), BCLV)
-		Store (0x80000000, CR1)
-		Store (0x0610, BCLM)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		Store (BCLV, Local0)
-		ShiftRight (Local0, 4, Local0)
-		Return (Local0)
-	}
+#include "brightness_levels.asl"
 #include "common.asl"
 }
diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl
index 70ab6f6..0a6b583 100644
--- a/src/drivers/intel/gma/acpi/pch.asl
+++ b/src/drivers/intel/gma/acpi/pch.asl
@@ -26,53 +26,20 @@ Device (GFX0)
 	Field (GFXC, DWordAcc, NoLock, Preserve)
 	{
 		Offset (0x10),
-			BAR0, 64
+		BAR0, 64
 	}
 
 	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
 	Field (GFRG, DWordAcc, NoLock, Preserve)
 	{
 		Offset (0x48254),
-			BCLV, 16,
+		BCLV, 16,
 		Offset (0xc8250),
-			CR1, 32,
-			CR2, 32
+		CR1, 32,
+		Offset (0xc8256),
+		BCLM, 16
 	}
 
-	Name (BRIG, Package (0x12)
-	{
-		0x61,
-		0x61,
-		0x2,
-		0x4,
-		0x5,
-		0x7,
-		0x9,
-		0xb,
-		0xd,
-		0x11,
-		0x14,
-		0x17,
-		0x1c,
-		0x20,
-		0x27,
-		0x31,
-		0x41,
-		0x61,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (ShiftLeft (Arg0, 4), BCLV)
-		Store (0x80000000, CR1)
-		Store (0x061a061a, CR2)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		Store (BCLV, Local0)
-		ShiftRight (Local0, 4, Local0)
-		Return (Local0)
-	}
+#include "brightness_levels.asl"
 #include "common.asl"
 }


From gerrit at coreboot.org  Thu Sep 24 16:44:32 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Thu, 24 Sep 2015 16:44:32 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: gma ACPI: Do
	not overwrite backlight configuration
References: <I35419993c8250c95fc69ba4db30db9dba9e6f8ff+0@gerrit.coreboot.org>
Message-ID: <I35419993c8250c95fc69ba4db30db9dba9e6f8ff+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11704

-gerrit

commit 315315ec6d4495d613b87e6271400b3dedffd933
Author: Nico Huber <nico.huber at secunet.com>
Date:   Thu Aug 27 13:31:46 2015 +0200

    gma ACPI: Do not overwrite backlight configuration
    
    Changes to CR1 and CR2 were effectively overwriting the backlight
    configuration from the devicetree with static values.
    
    Instead read the maximum brightness value from BCLM (backlight
    modulation frequency) and calculate the target level (Arg0 is the
    target level as percentage).
    
    Turned out that _BQC has to return a value from the list returned by
    _BCL. So XBQC got a little heavier to search for the correct value.
    
    Change-Id: I35419993c8250c95fc69ba4db30db9dba9e6f8ff
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/drivers/intel/gma/acpi/brightness_levels.asl | 23 +++++++++++++++++------
 src/drivers/intel/gma/acpi/non-pch.asl           |  2 --
 src/drivers/intel/gma/acpi/pch.asl               |  2 --
 3 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/src/drivers/intel/gma/acpi/brightness_levels.asl b/src/drivers/intel/gma/acpi/brightness_levels.asl
index c186989..d0e70a9 100644
--- a/src/drivers/intel/gma/acpi/brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/brightness_levels.asl
@@ -22,14 +22,25 @@
 
 	Method (XBCM, 1, NotSerialized)
 	{
-		Store (ShiftLeft (Arg0, 4), BCLV)
-		Store (0x80000000, CR1)
-		Store (0x0610, BCLM)
+		Store (Divide (Multiply (Arg0, BCLM), 100), BCLV)
 	}
 
 	Method (XBQC, 0, NotSerialized)
 	{
-		Store (BCLV, Local0)
-		ShiftRight (Local0, 4, Local0)
-		Return (Local0)
+		/* Find value close to BCLV in BRIG (which must be ordered) */
+		Store (BCLV, Local0)			// Current value
+		Store (BCLM, Local1)			// For calculations
+		Store (2, Local2)			// Loop index
+		While (LLess (Local2, Subtract (SizeOf (BRIG), 1))) {
+			Store (DeRefOf (Index (BRIG, Local2)), Local3)
+			/* Use same calculation as XBCM, to get exact matches */
+			Store (Divide (Multiply (Local3, Local1), 100), Local3)
+
+			If (LLessEqual (Local0, Local3)) {
+				Return (DeRefOf (Index (BRIG, Local2)))
+			}
+			Add (Local2, 1, Local2)
+		}
+		/* Didn't find greater/equal value: use the last */
+		Return (DeRefOf (Index (BRIG, Local2)))
 	}
diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl
index c445c97..0e15627 100644
--- a/src/drivers/intel/gma/acpi/non-pch.asl
+++ b/src/drivers/intel/gma/acpi/non-pch.asl
@@ -32,8 +32,6 @@ Device (GFX0)
 	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
 	Field (GFRG, DWordAcc, NoLock, Preserve)
 	{
-		Offset (0x61250),
-		CR1, 32,
 		Offset (0x61254),
 		BCLV, 16,
 		BCLM, 16,
diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl
index 0a6b583..98746e8 100644
--- a/src/drivers/intel/gma/acpi/pch.asl
+++ b/src/drivers/intel/gma/acpi/pch.asl
@@ -34,8 +34,6 @@ Device (GFX0)
 	{
 		Offset (0x48254),
 		BCLV, 16,
-		Offset (0xc8250),
-		CR1, 32,
 		Offset (0xc8256),
 		BCLM, 16
 	}


From gerrit at coreboot.org  Thu Sep 24 16:44:34 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Thu, 24 Sep 2015 16:44:34 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: gma ACPI: Make
	backlight levels overwritable
References: <Ib865c7b4274f2ea3181a89fc52701b740f9bab7d+0@gerrit.coreboot.org>
Message-ID: <Ib865c7b4274f2ea3181a89fc52701b740f9bab7d+1@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11705

-gerrit

commit b112943a57ede408d52c678d341414abdcd46c4c
Author: Nico Huber <nico.huber at secunet.com>
Date:   Thu Aug 27 13:31:46 2015 +0200

    gma ACPI: Make backlight levels overwritable
    
    Those are actually board specific. Keep the old value as defaults,
    though.
    
    Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/drivers/intel/gma/acpi/brightness_levels.asl | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/gma/acpi/brightness_levels.asl b/src/drivers/intel/gma/acpi/brightness_levels.asl
index d0e70a9..9f3cb35 100644
--- a/src/drivers/intel/gma/acpi/brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/brightness_levels.asl
@@ -1,5 +1,8 @@
-	Name (BRIG, Package (0x12)
+	Name (BRIG, Package ()
 	{
+#ifdef INTEL_GMA_BRIGHTNESS_LEVELS
+		INTEL_GMA_BRIGHTNESS_LEVELS
+#else
 		100, /* default AC */
 		100, /* default Battery */
 		  2,
@@ -18,6 +21,7 @@
 		 50,
 		 67,
 		100,
+#endif
 	})
 
 	Method (XBCM, 1, NotSerialized)


From gerrit at coreboot.org  Thu Sep 24 16:47:43 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Thu, 24 Sep 2015 16:47:43 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: gma ACPI: Make
	brightness levels overwritable
References: <Ib865c7b4274f2ea3181a89fc52701b740f9bab7d+0@gerrit.coreboot.org>
Message-ID: <Ib865c7b4274f2ea3181a89fc52701b740f9bab7d+2@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11705

-gerrit

commit 3e9adfaeee94449d3e4e1a4d6d34102ec5b5c241
Author: Nico Huber <nico.huber at secunet.com>
Date:   Thu Aug 27 13:31:46 2015 +0200

    gma ACPI: Make brightness levels overwritable
    
    Those are actually board specific. Keep the old value as defaults,
    though.
    
    Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/drivers/intel/gma/acpi/brightness_levels.asl | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/gma/acpi/brightness_levels.asl b/src/drivers/intel/gma/acpi/brightness_levels.asl
index d0e70a9..9f3cb35 100644
--- a/src/drivers/intel/gma/acpi/brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/brightness_levels.asl
@@ -1,5 +1,8 @@
-	Name (BRIG, Package (0x12)
+	Name (BRIG, Package ()
 	{
+#ifdef INTEL_GMA_BRIGHTNESS_LEVELS
+		INTEL_GMA_BRIGHTNESS_LEVELS
+#else
 		100, /* default AC */
 		100, /* default Battery */
 		  2,
@@ -18,6 +21,7 @@
 		 50,
 		 67,
 		100,
+#endif
 	})
 
 	Method (XBCM, 1, NotSerialized)


From gerrit at coreboot.org  Thu Sep 24 17:02:44 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Thu, 24 Sep 2015 17:02:44 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfstool:
	Proper commonlib include path with no dependency on $(src)
References: <I72e80b030d4a156ec653ded5ab1457b16f612526+0@gerrit.coreboot.org>
Message-ID: <I72e80b030d4a156ec653ded5ab1457b16f612526+1@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11706

-gerrit

commit 1cfbcefac7613c3bb73fd07ad842e8c4cf5a538b
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 24 19:00:47 2015 +0200

    cbfstool: Proper commonlib include path with no dependency on $(src)
    
    $(src) is not defined when building directly from the cbfs directory (that is,
    when building cbfs as standalone, running make in the cbfs directory), so we
    need to define the path to the commonlib include path relative to $(top).
    
    Change-Id: I72e80b030d4a156ec653ded5ab1457b16f612526
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 util/cbfstool/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 0938ea9..a1dbfc3 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -50,7 +50,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
 TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
 TOOLCPPFLAGS += -I$(top)/util/cbfstool
 TOOLCPPFLAGS += -I$(objutil)/cbfstool
-TOOLCPPFLAGS += -I$(src)/commonlib/include
+TOOLCPPFLAGS += -I$(top)/src/commonlib/include
 TOOLLDFLAGS ?=
 
 ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)


From gerrit at coreboot.org  Thu Sep 24 17:08:23 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 24 Sep 2015 17:08:23 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	Proper commonlib include path with no dependency on $(src)
References: <I72e80b030d4a156ec653ded5ab1457b16f612526+0@gerrit.coreboot.org>
Message-ID: <E1ZfA0N-0007bt-Qn@mail.coreboot.org>

the following patch was just integrated into master:
commit 34ce438e6fc6ccab926141e462216e0430097507
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 24 19:00:47 2015 +0200

    cbfstool: Proper commonlib include path with no dependency on $(src)
    
    $(src) is not defined when building directly from the cbfs directory (that is,
    when building cbfs as standalone, running make in the cbfs directory), so we
    need to define the path to the commonlib include path relative to $(top).
    
    Change-Id: I72e80b030d4a156ec653ded5ab1457b16f612526
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
    Reviewed-on: http://review.coreboot.org/11706
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11706 for details.

-gerrit


From gerrit at coreboot.org  Fri Sep 25 05:06:16 2015
From: gerrit at coreboot.org (WANG Siyuan (wangsiyuanbuaa@gmail.com))
Date: Fri, 25 Sep 2015 05:06:16 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: AMD Bettong:
	read board version
References: <I3874020e0f0f87edc57ee1378d5c6d4a292a92ef+0@gerrit.coreboot.org>
Message-ID: <I3874020e0f0f87edc57ee1378d5c6d4a292a92ef+1@gerrit.coreboot.org>

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11707

-gerrit

commit 568f51b4e5b3110c188c01cdb80ed1259ff0ba1e
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Fri Jul 3 20:29:56 2015 +0800

    AMD Bettong: read board version
    
    Bettong use 3 GPIO ports to identify board.
    The GPIO are mapped to MMIO space.
    
    Change-Id: I3874020e0f0f87edc57ee1378d5c6d4a292a92ef
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/mainboard/amd/bettong/Makefile.inc |  2 ++
 src/mainboard/amd/bettong/board_rev.c  | 45 ++++++++++++++++++++++++++++++++++
 src/mainboard/amd/bettong/board_rev.h  | 25 +++++++++++++++++++
 3 files changed, 72 insertions(+)

diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc
index 70722ee..513826c 100644
--- a/src/mainboard/amd/bettong/Makefile.inc
+++ b/src/mainboard/amd/bettong/Makefile.inc
@@ -19,9 +19,11 @@
 
 romstage-y += BiosCallOuts.c
 romstage-y += PlatformGnbPcie.c
+romstage-y += board_rev.c
 
 ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
 ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
 ramstage-y += fchec.c
 endif
+ramstage-y += board_rev.c
diff --git a/src/mainboard/amd/bettong/board_rev.c b/src/mainboard/amd/bettong/board_rev.c
new file mode 100644
index 0000000..be9dbbc
--- /dev/null
+++ b/src/mainboard/amd/bettong/board_rev.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <reset.h>
+#include "board_rev.h"
+
+char get_board_id(void)
+{
+	u32 gpiommioaddr;
+	u8  value = 0;
+	u8  boardrev = 0;
+	char boardid = 'u';
+
+	gpiommioaddr = 0xfed80000ul + 0x1500;
+	value = *(volatile u8 *) (gpiommioaddr + (7 << 2) + 2); //agpio7 //board_id2
+	boardrev = value & 1;
+	value = *(volatile u8 *) (gpiommioaddr + (6 << 2) + 2); //agpio6 //board_id1
+	boardrev |= (value & 1) << 1;
+	value = *(volatile u8 *) (gpiommioaddr + (5 << 2) + 2); //agpio5 //board_id0
+	boardrev |= (value & 1) << 2;
+
+	boardid = 'A' + boardrev;
+
+	return boardid;
+}
diff --git a/src/mainboard/amd/bettong/board_rev.h b/src/mainboard/amd/bettong/board_rev.h
new file mode 100644
index 0000000..ea7a0f3
--- /dev/null
+++ b/src/mainboard/amd/bettong/board_rev.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _BOARD_REV_H
+#define _BOARD_REV_H
+
+char get_board_id(void);
+
+#endif


From gerrit at coreboot.org  Fri Sep 25 05:58:40 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Fri, 25 Sep 2015 05:58:40 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: AMD Merlin
	Falcon: Disable UMA if external graphics is used
References: <If7031b74583a2b9805d16fcf669fe8be3b58ed40+0@gerrit.coreboot.org>
Message-ID: <If7031b74583a2b9805d16fcf669fe8be3b58ed40+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10904

-gerrit

commit 538b3e18b23553b443c2535b00bec797ee9fd813
Author: zbao <fishbaozi at gmail.com>
Date:   Thu Jun 25 16:58:02 2015 -0400

    AMD Merlin Falcon: Disable UMA if external graphics is used
    
    For Carrizo, if the external is used as primary graphics, the
    internal graphics can not be used. so we let the GFXUMA be
    depended on ONBOARD_VGA_IS_PRIMARY.
    
    Change-Id: If7031b74583a2b9805d16fcf669fe8be3b58ed40
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/mainboard/amd/bettong/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 1f2d888..7877499 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_8192
-	select GFXUMA
+	select GFXUMA if ONBOARD_VGA_IS_PRIMARY
 
 config MAINBOARD_DIR
 	string


From gerrit at coreboot.org  Fri Sep 25 06:06:30 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Fri, 25 Sep 2015 06:06:30 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+6@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit c60785d75b82705376d96f6bac600332750320df
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                               | 23 ++++++-------
 src/cpu/amd/model_10xxx/Makefile.inc               |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c           |  3 --
 src/cpu/amd/model_fxx/Makefile.inc                 |  2 +-
 src/cpu/intel/ep80579/Makefile.inc                 |  2 --
 src/cpu/intel/ep80579/microcode_blob.c             |  8 -----
 src/cpu/intel/fsp_model_206ax/Kconfig              |  5 ---
 src/cpu/intel/fsp_model_206ax/Makefile.inc         |  9 ++---
 src/cpu/intel/fsp_model_206ax/microcode_blob.c     | 22 -------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h     | 33 -------------------
 src/cpu/intel/fsp_model_406dx/Kconfig              |  4 ---
 src/cpu/intel/fsp_model_406dx/Makefile.inc         | 10 ++----
 src/cpu/intel/fsp_model_406dx/microcode_blob.c     | 29 -----------------
 src/cpu/intel/haswell/Makefile.inc                 |  5 +--
 src/cpu/intel/haswell/microcode_blob.c             | 30 -----------------
 src/cpu/intel/model_1067x/Makefile.inc             |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c         |  3 --
 src/cpu/intel/model_106cx/Makefile.inc             |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c         |  3 --
 src/cpu/intel/model_2065x/Makefile.inc             |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c         | 22 -------------
 src/cpu/intel/model_206ax/Makefile.inc             |  3 +-
 src/cpu/intel/model_206ax/microcode_blob.c         | 23 -------------
 src/cpu/intel/model_65x/Makefile.inc               |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c           |  3 --
 src/cpu/intel/model_67x/Makefile.inc               |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c           |  3 --
 src/cpu/intel/model_68x/Makefile.inc               |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c           |  3 --
 src/cpu/intel/model_69x/Makefile.inc               |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c           |  3 --
 src/cpu/intel/model_6bx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6dx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6ex/Makefile.inc               |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c           |  3 --
 src/cpu/intel/model_6fx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6xx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c           |  3 --
 src/cpu/intel/model_f0x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f1x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f2x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f3x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c           |  3 --
 src/cpu/intel/model_f4x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c           |  3 --
 src/cpu/via/nano/Makefile.inc                      |  4 +--
 src/soc/intel/baytrail/Makefile.inc                |  3 +-
 src/soc/intel/baytrail/microcode/Makefile.inc      |  1 -
 src/soc/intel/baytrail/microcode/microcode_blob.c  |  3 --
 src/soc/intel/braswell/Makefile.inc                |  3 +-
 src/soc/intel/braswell/microcode/Makefile.inc      |  2 --
 src/soc/intel/braswell/microcode/microcode_blob.c  | 22 -------------
 src/soc/intel/broadwell/Makefile.inc               |  3 +-
 src/soc/intel/broadwell/microcode/Makefile.inc     |  1 -
 src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
 src/soc/intel/fsp_baytrail/Makefile.inc            |  3 +-
 src/soc/intel/fsp_baytrail/microcode/Makefile.inc  | 26 ---------------
 .../intel/fsp_baytrail/microcode/microcode_blob.c  | 38 ----------------------
 .../intel/fsp_baytrail/microcode/microcode_size.h  |  6 ----
 src/soc/intel/skylake/Makefile.inc                 |  3 +-
 src/soc/intel/skylake/microcode/Makefile.inc       |  2 --
 src/soc/intel/skylake/microcode/microcode_blob.c   | 24 --------------
 68 files changed, 50 insertions(+), 436 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e8c5022..ce1112c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -54,6 +53,8 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index eda9f76..cf1fa50 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -52,6 +51,8 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 183c40f..b354e8c 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -74,6 +73,8 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 45ea3e4..ebc2cc5 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
 
 ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -60,6 +59,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
 ramstage-y += placeholders.c
 ramstage-y += i2c.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
-		/*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
-	#include "M0230672228.h"  // M0230672: Bay Trail "Super SKU" B0/B1
-	#include "M0130673322.h"  // M0130673: Bay Trail I B2 / B3
-	#include "M0130679901.h"  // M0130679: Bay Trail I D0
-#else
-	/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
-	#include "M0C30678829.h"  // M0C30678: Bay Trail M D Stepping
-#endif	/* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif	/* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	#define MICROCODE_REGION_LENGTH 0x30000
-#else
-	#define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 38668da..b74f353 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-


From gerrit at coreboot.org  Fri Sep 25 06:06:32 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Fri, 25 Sep 2015 06:06:32 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: 3dparty/blobs:
	Advance to pull in binary microcode
References: <I2071586e1f3b4464464928c11475f9283084dbcd+0@gerrit.coreboot.org>
Message-ID: <I2071586e1f3b4464464928c11475f9283084dbcd+3@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11693

-gerrit

commit 5e410366464ba1ea975169afb19e6f84ccf5d362
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sun Sep 20 21:08:05 2015 -0700

    3dparty/blobs: Advance to pull in binary microcode
    
    Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 3rdparty/blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index b4ade40..df1f219 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7
+Subproject commit df1f21931c75aae9ee14cdc52da57783a6e0a9ad


From gerrit at coreboot.org  Fri Sep 25 06:06:33 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Fri, 25 Sep 2015 06:06:33 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: soc/intel:
	Store microcode in binary format
References: <I0020f3dc90e22d0ce443f7d4888272ac805ac84f+0@gerrit.coreboot.org>
Message-ID: <I0020f3dc90e22d0ce443f7d4888272ac805ac84f+1@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11708

-gerrit

commit 94aad6d3913d57e11079a4161f67752b7c4bbeab
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Thu Sep 24 08:23:10 2015 -0700

    soc/intel: Store microcode in binary format
    
    Change-Id: I0020f3dc90e22d0ce443f7d4888272ac805ac84f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 soc/intel/baytrail/microcode.bin  | Bin 0 -> 104512 bytes
 soc/intel/broadwell/microcode.bin | Bin 0 -> 70720 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/soc/intel/baytrail/microcode.bin b/soc/intel/baytrail/microcode.bin
new file mode 100755
index 0000000..42c63b4
Binary files /dev/null and b/soc/intel/baytrail/microcode.bin differ
diff --git a/soc/intel/broadwell/microcode.bin b/soc/intel/broadwell/microcode.bin
new file mode 100755
index 0000000..7fc2096
Binary files /dev/null and b/soc/intel/broadwell/microcode.bin differ


From gerrit at coreboot.org  Fri Sep 25 06:06:35 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Fri, 25 Sep 2015 06:06:35 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+1@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 9a655bfe92e283b17c21e2a6c69e127372dd91bf
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    fsp1.0:  Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be get during build time and
    microcode_size.h will be generated. In this way, the size do
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/arch/x86/Makefile.inc             | 2 +-
 src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
 # the right order. Make sure the auto generated romstage.inc is a proper
 # dependency.
 romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
 
 ifneq ($(CONFIG_ROMCC),y)
 
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Fri Sep 25 06:18:24 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Fri, 25 Sep 2015 06:18:24 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: soc/intel: Store
	microcode in binary format
References: <I0020f3dc90e22d0ce443f7d4888272ac805ac84f+0@gerrit.coreboot.org>
Message-ID: <I0020f3dc90e22d0ce443f7d4888272ac805ac84f+2@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11708

-gerrit

commit aa31e03ff2824608fc59a8dbdc35519f33393b75
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Thu Sep 24 08:23:10 2015 -0700

    soc/intel: Store microcode in binary format
    
    Change-Id: I0020f3dc90e22d0ce443f7d4888272ac805ac84f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 soc/intel/baytrail/microcode.bin  | Bin 0 -> 104512 bytes
 soc/intel/broadwell/microcode.bin | Bin 0 -> 70720 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/soc/intel/baytrail/microcode.bin b/soc/intel/baytrail/microcode.bin
new file mode 100755
index 0000000..42c63b4
Binary files /dev/null and b/soc/intel/baytrail/microcode.bin differ
diff --git a/soc/intel/broadwell/microcode.bin b/soc/intel/broadwell/microcode.bin
new file mode 100755
index 0000000..7fc2096
Binary files /dev/null and b/soc/intel/broadwell/microcode.bin differ


From gerrit at coreboot.org  Fri Sep 25 06:19:16 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Fri, 25 Sep 2015 06:19:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: fsp1.0: Get size
	of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+2@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 86029be458ccc3955370d872659736c9d12dfa00
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    fsp1.0:  Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be get during build time and
    microcode_size.h will be generated. In this way, the size do
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/arch/x86/Makefile.inc             | 2 +-
 src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
 # the right order. Make sure the auto generated romstage.inc is a proper
 # dependency.
 romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
 
 ifneq ($(CONFIG_ROMCC),y)
 
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Fri Sep 25 07:02:15 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Fri, 25 Sep 2015 07:02:15 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+3@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 692d12ed54f9e620e79991fb7a50e2da4601eb2d
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/arch/x86/Makefile.inc             | 2 +-
 src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
 # the right order. Make sure the auto generated romstage.inc is a proper
 # dependency.
 romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
 
 ifneq ($(CONFIG_ROMCC),y)
 
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Fri Sep 25 07:04:54 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Fri, 25 Sep 2015 07:04:54 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: armv7:
	Word-sized/half-word-sized memory operations for 32/16 bit
	read/write
References: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+0@gerrit.coreboot.org>
Message-ID: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+4@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698

-gerrit

commit 0815c0aa0f7650522512052c335a5d9eb16507de
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Tue Sep 22 22:16:33 2015 +0200

    armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
    
    Some registers only allow word-sized or half-word-sized operations and will
    cause a data fault when accessed with byte-sized operations.
    However, the compiler may or may not break such an operation into smaller
    (byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
    32 bit read/write and half-word-sized operations for 16 bit read/write.
    
    This is particularly the case on the rk3288 SRAM registers, where the watchdog
    tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
    compiler, where a 32 bit read would be broken into byte-sized chunks, which
    caused a data fault when accessing the watchdog tombstone register.
    
    The definitions for byte-sized memory operations are also adapted to stay
    consistent with the rest.
    
    Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/arch/arm/include/armv7/arch/io.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..53c700d 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -30,39 +30,39 @@
 static inline uint8_t read8(const void *addr)
 {
 	dmb();
-	return *(volatile uint8_t *)addr;
+	return *(volatile uint8_t *)__builtin_assume_aligned(addr, 1);
 }
 
 static inline uint16_t read16(const void *addr)
 {
 	dmb();
-	return *(volatile uint16_t *)addr;
+	return *(volatile uint16_t *)__builtin_assume_aligned(addr, 2);
 }
 
 static inline uint32_t read32(const void *addr)
 {
 	dmb();
-	return *(volatile uint32_t *)addr;
+	return *(volatile uint32_t *)__builtin_assume_aligned(addr, 4);
 }
 
 static inline void write8(void *addr, uint8_t val)
 {
 	dmb();
-	*(volatile uint8_t *)addr = val;
+	*(volatile uint8_t *)__builtin_assume_aligned(addr, 1) = val;
 	dmb();
 }
 
 static inline void write16(void *addr, uint16_t val)
 {
 	dmb();
-	*(volatile uint16_t *)addr = val;
+	*(volatile uint16_t *)__builtin_assume_aligned(addr, 2) = val;
 	dmb();
 }
 
 static inline void write32(void *addr, uint32_t val)
 {
 	dmb();
-	*(volatile uint32_t *)addr = val;
+	*(volatile uint32_t *)__builtin_assume_aligned(addr, 4) = val;
 	dmb();
 }
 


From gerrit at coreboot.org  Fri Sep 25 07:08:38 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Fri, 25 Sep 2015 07:08:38 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+4@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 73cbdfc495d6e32cb2bcfb5f54693db922d7347b
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/arch/x86/Makefile.inc             | 2 +-
 src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
 # the right order. Make sure the auto generated romstage.inc is a proper
 # dependency.
 romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
 
 ifneq ($(CONFIG_ROMCC),y)
 
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Fri Sep 25 07:22:30 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Fri, 25 Sep 2015 07:22:30 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Makefile.inc:
	Align paths in CBFS add messages
References: <Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972+0@gerrit.coreboot.org>
Message-ID: <Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972+1@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11710

-gerrit

commit a4560cc350369b36f25bf585936848fa2fddbe13
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Fri Sep 25 09:18:43 2015 +0200

    Makefile.inc: Align paths in CBFS add messages
    
    Building coreboot with the SeaBIOS or FILO payload selected, their config and
    revision are added to CBFS.
    
    ```
      Creating out/bios.bin.elf
        CBFS       coreboot.rom
        PAYLOAD    payloads/external/SeaBIOS/seabios/out/bios.bin.elf (compression: LZMA)
        CONFIG     .config
        REVISION   build.h
        CONFIG      payloads/external/SeaBIOS/seabios/.config
        REVISION   payloads/external/SeaBIOS/seabios/out/version.c
        CBFSPRINT  coreboot.rom
    ```
    
    Align, the path of the payload config by removing one space.
    
    Change-Id: Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile.inc b/Makefile.inc
index ac6ce0b..3c4848e 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -659,7 +659,7 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y)
 endif
 endif
 ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y)
-	@printf "    CONFIG      $(PAYLOAD_CONFIG)\n"
+	@printf "    CONFIG     $(PAYLOAD_CONFIG)\n"
 	if [ -f "$(PAYLOAD_CONFIG)" ]; then \
 		$(CBFSTOOL) $@.tmp add -f  "$(PAYLOAD_CONFIG)" -n payload_config -t raw; \
 	fi


From gerrit at coreboot.org  Fri Sep 25 11:46:51 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Fri, 25 Sep 2015 11:46:51 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: gma ACPI: Make
	brightness levels a per board setting
References: <Ib865c7b4274f2ea3181a89fc52701b740f9bab7d+0@gerrit.coreboot.org>
Message-ID: <Ib865c7b4274f2ea3181a89fc52701b740f9bab7d+3@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11705

-gerrit

commit e1b978caa32ebe617196161a4b508c61e3bf6fe5
Author: Nico Huber <nico.huber at secunet.com>
Date:   Thu Aug 27 13:31:46 2015 +0200

    gma ACPI: Make brightness levels a per board setting
    
    Those are actually board specific. Keep the old value as defaults,
    though. The defaults are included by all affected boards that specify
    an integrated display in the devicetree through `gfx.did`.
    
    Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/drivers/intel/gma/acpi/brightness_levels.asl   | 46 ----------------------
 .../intel/gma/acpi/configure_brightness_levels.asl | 24 +++++++++++
 .../intel/gma/acpi/default_brightness_levels.asl   | 24 +++++++++++
 src/drivers/intel/gma/acpi/non-pch.asl             |  2 +-
 src/drivers/intel/gma/acpi/pch.asl                 |  2 +-
 src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl        |  2 +
 src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl        |  2 +
 src/mainboard/google/bolt/dsdt.asl                 |  2 +
 src/mainboard/google/butterfly/dsdt.asl            |  2 +
 src/mainboard/google/falco/dsdt.asl                |  2 +
 src/mainboard/google/panther/dsdt.asl              |  2 +
 src/mainboard/google/parrot/dsdt.asl               |  2 +
 src/mainboard/google/peppy/dsdt.asl                |  2 +
 src/mainboard/google/slippy/dsdt.asl               |  2 +
 src/mainboard/google/stout/dsdt.asl                |  2 +
 src/mainboard/intel/baskingridge/dsdt.asl          |  2 +
 src/mainboard/intel/cougar_canyon2/dsdt.asl        |  2 +
 src/mainboard/intel/emeraldlake2/dsdt.asl          |  2 +
 src/mainboard/kontron/ktqm77/dsdt.asl              |  2 +
 src/mainboard/lenovo/t400/dsdt.asl                 |  2 +
 src/mainboard/lenovo/t420s/dsdt.asl                |  2 +
 src/mainboard/lenovo/t430s/dsdt.asl                |  2 +
 src/mainboard/lenovo/t520/dsdt.asl                 |  2 +
 src/mainboard/lenovo/t530/dsdt.asl                 |  2 +
 src/mainboard/lenovo/x200/dsdt.asl                 |  2 +
 src/mainboard/lenovo/x201/dsdt.asl                 |  2 +
 src/mainboard/lenovo/x220/dsdt.asl                 |  2 +
 src/mainboard/lenovo/x230/dsdt.asl                 |  2 +
 src/mainboard/packardbell/ms2290/dsdt.asl          |  2 +
 src/mainboard/roda/rk9/dsdt.asl                    |  2 +
 src/mainboard/samsung/lumpy/dsdt.asl               |  2 +
 src/mainboard/samsung/stumpy/dsdt.asl              |  2 +
 32 files changed, 104 insertions(+), 48 deletions(-)

diff --git a/src/drivers/intel/gma/acpi/brightness_levels.asl b/src/drivers/intel/gma/acpi/brightness_levels.asl
deleted file mode 100644
index d0e70a9..0000000
--- a/src/drivers/intel/gma/acpi/brightness_levels.asl
+++ /dev/null
@@ -1,46 +0,0 @@
-	Name (BRIG, Package (0x12)
-	{
-		100, /* default AC */
-		100, /* default Battery */
-		  2,
-		  4,
-		  5,
-		  7,
-		  9,
-		 11,
-		 13,
-		 18,
-		 20,
-		 24,
-		 29,
-		 33,
-		 40,
-		 50,
-		 67,
-		100,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (Divide (Multiply (Arg0, BCLM), 100), BCLV)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		/* Find value close to BCLV in BRIG (which must be ordered) */
-		Store (BCLV, Local0)			// Current value
-		Store (BCLM, Local1)			// For calculations
-		Store (2, Local2)			// Loop index
-		While (LLess (Local2, Subtract (SizeOf (BRIG), 1))) {
-			Store (DeRefOf (Index (BRIG, Local2)), Local3)
-			/* Use same calculation as XBCM, to get exact matches */
-			Store (Divide (Multiply (Local3, Local1), 100), Local3)
-
-			If (LLessEqual (Local0, Local3)) {
-				Return (DeRefOf (Index (BRIG, Local2)))
-			}
-			Add (Local2, 1, Local2)
-		}
-		/* Didn't find greater/equal value: use the last */
-		Return (DeRefOf (Index (BRIG, Local2)))
-	}
diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
new file mode 100644
index 0000000..38eb116
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -0,0 +1,24 @@
+	Method (XBCM, 1, NotSerialized)
+	{
+		Store (Divide (Multiply (Arg0, BCLM), 100), BCLV)
+	}
+
+	Method (XBQC, 0, NotSerialized)
+	{
+		/* Find value close to BCLV in BRIG (which must be ordered) */
+		Store (BCLV, Local0)			// Current value
+		Store (BCLM, Local1)			// For calculations
+		Store (2, Local2)			// Loop index
+		While (LLess (Local2, Subtract (SizeOf (BRIG), 1))) {
+			Store (DeRefOf (Index (BRIG, Local2)), Local3)
+			/* Use same calculation as XBCM, to get exact matches */
+			Store (Divide (Multiply (Local3, Local1), 100), Local3)
+
+			If (LLessEqual (Local0, Local3)) {
+				Return (DeRefOf (Index (BRIG, Local2)))
+			}
+			Add (Local2, 1, Local2)
+		}
+		/* Didn't find greater/equal value: use the last */
+		Return (DeRefOf (Index (BRIG, Local2)))
+	}
diff --git a/src/drivers/intel/gma/acpi/default_brightness_levels.asl b/src/drivers/intel/gma/acpi/default_brightness_levels.asl
new file mode 100644
index 0000000..6c6f35e
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/default_brightness_levels.asl
@@ -0,0 +1,24 @@
+Scope (GFX0)
+{
+	Name (BRIG, Package (0x12)
+	{
+		100, /* default AC */
+		100, /* default Battery */
+		  2,
+		  4,
+		  5,
+		  7,
+		  9,
+		 11,
+		 13,
+		 18,
+		 20,
+		 24,
+		 29,
+		 33,
+		 40,
+		 50,
+		 67,
+		100,
+	})
+}
diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl
index 0e15627..983dc01 100644
--- a/src/drivers/intel/gma/acpi/non-pch.asl
+++ b/src/drivers/intel/gma/acpi/non-pch.asl
@@ -37,6 +37,6 @@ Device (GFX0)
 		BCLM, 16,
 	}
 
-#include "brightness_levels.asl"
+#include "configure_brightness_levels.asl"
 #include "common.asl"
 }
diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl
index 98746e8..bd59a43 100644
--- a/src/drivers/intel/gma/acpi/pch.asl
+++ b/src/drivers/intel/gma/acpi/pch.asl
@@ -38,6 +38,6 @@ Device (GFX0)
 		BCLM, 16
 	}
 
-#include "brightness_levels.asl"
+#include "configure_brightness_levels.asl"
 #include "common.asl"
 }
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
index 9350dea..10faccd 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
@@ -22,6 +22,8 @@ DefinitionBlock(
 		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 		#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 }
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
index 9350dea..10faccd 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
@@ -22,6 +22,8 @@ DefinitionBlock(
 		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 		#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 }
diff --git a/src/mainboard/google/bolt/dsdt.asl b/src/mainboard/google/bolt/dsdt.asl
index 76998ba..597f1a3 100644
--- a/src/mainboard/google/bolt/dsdt.asl
+++ b/src/mainboard/google/bolt/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl
index 0a2f37d..e538cd6 100644
--- a/src/mainboard/google/butterfly/dsdt.asl
+++ b/src/mainboard/google/butterfly/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/falco/dsdt.asl b/src/mainboard/google/falco/dsdt.asl
index c9e9bb0..fcb7a3f 100644
--- a/src/mainboard/google/falco/dsdt.asl
+++ b/src/mainboard/google/falco/dsdt.asl
@@ -46,6 +46,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl
index e108717..b77a401 100644
--- a/src/mainboard/google/panther/dsdt.asl
+++ b/src/mainboard/google/panther/dsdt.asl
@@ -46,6 +46,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl
index 0a2f37d..e538cd6 100644
--- a/src/mainboard/google/parrot/dsdt.asl
+++ b/src/mainboard/google/parrot/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/peppy/dsdt.asl b/src/mainboard/google/peppy/dsdt.asl
index 76998ba..597f1a3 100644
--- a/src/mainboard/google/peppy/dsdt.asl
+++ b/src/mainboard/google/peppy/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl
index 76998ba..597f1a3 100644
--- a/src/mainboard/google/slippy/dsdt.asl
+++ b/src/mainboard/google/slippy/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl
index 01e4001..ca8640b 100644
--- a/src/mainboard/google/stout/dsdt.asl
+++ b/src/mainboard/google/stout/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl
index b586e34..7e37428 100644
--- a/src/mainboard/intel/baskingridge/dsdt.asl
+++ b/src/mainboard/intel/baskingridge/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/intel/cougar_canyon2/dsdt.asl b/src/mainboard/intel/cougar_canyon2/dsdt.asl
index 82d6ee5..494e72f 100644
--- a/src/mainboard/intel/cougar_canyon2/dsdt.asl
+++ b/src/mainboard/intel/cougar_canyon2/dsdt.asl
@@ -45,6 +45,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/fsp_bd82x6x/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl
index b545838..b4afa3d 100644
--- a/src/mainboard/intel/emeraldlake2/dsdt.asl
+++ b/src/mainboard/intel/emeraldlake2/dsdt.asl
@@ -48,6 +48,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl
index 9dbe7e5..7a4b9b1 100644
--- a/src/mainboard/kontron/ktqm77/dsdt.asl
+++ b/src/mainboard/kontron/ktqm77/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl
index 6274755..1d62057 100644
--- a/src/mainboard/lenovo/t400/dsdt.asl
+++ b/src/mainboard/lenovo/t400/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/gm45/acpi/gm45.asl>
 			#include <southbridge/intel/i82801ix/acpi/ich9.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl
index 64e4e9f..fb653ea 100644
--- a/src/mainboard/lenovo/t420s/dsdt.asl
+++ b/src/mainboard/lenovo/t420s/dsdt.asl
@@ -51,6 +51,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl
index 64e4e9f..fb653ea 100644
--- a/src/mainboard/lenovo/t430s/dsdt.asl
+++ b/src/mainboard/lenovo/t430s/dsdt.asl
@@ -51,6 +51,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl
index f5f3ace..9a75807 100644
--- a/src/mainboard/lenovo/t520/dsdt.asl
+++ b/src/mainboard/lenovo/t520/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl
index f5f3ace..9a75807 100644
--- a/src/mainboard/lenovo/t530/dsdt.asl
+++ b/src/mainboard/lenovo/t530/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl
index 5545c94..110cada 100644
--- a/src/mainboard/lenovo/x200/dsdt.asl
+++ b/src/mainboard/lenovo/x200/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/gm45/acpi/gm45.asl>
 			#include <southbridge/intel/i82801ix/acpi/ich9.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
index f2f0a89..15e85b2 100644
--- a/src/mainboard/lenovo/x201/dsdt.asl
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/nehalem/acpi/nehalem.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 		Device (UNCR)
 		{
diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl
index f5f3ace..9a75807 100644
--- a/src/mainboard/lenovo/x220/dsdt.asl
+++ b/src/mainboard/lenovo/x220/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
index 1c71c3c..1ef9f11 100644
--- a/src/mainboard/lenovo/x230/dsdt.asl
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 /*
diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl
index c2d96f3..b36f909 100644
--- a/src/mainboard/packardbell/ms2290/dsdt.asl
+++ b/src/mainboard/packardbell/ms2290/dsdt.asl
@@ -44,6 +44,8 @@ DefinitionBlock(
 			#include <northbridge/intel/nehalem/acpi/nehalem.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 		Device (UNCR)
 		{
diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl
index c955c86..1a86440 100644
--- a/src/mainboard/roda/rk9/dsdt.asl
+++ b/src/mainboard/roda/rk9/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/gm45/acpi/gm45.asl>
 			#include <southbridge/intel/i82801ix/acpi/ich9.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
index 1ab6322..13d8593 100644
--- a/src/mainboard/samsung/lumpy/dsdt.asl
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -51,6 +51,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl
index 0a2f37d..e538cd6 100644
--- a/src/mainboard/samsung/stumpy/dsdt.asl
+++ b/src/mainboard/samsung/stumpy/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 


From gerrit at coreboot.org  Fri Sep 25 13:27:27 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Fri, 25 Sep 2015 13:27:27 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: util/kconfig:
	fill glob_t with 0 before calling glob
References: <I03110c4cdda70578828d6499262a085a81d26313+0@gerrit.coreboot.org>
Message-ID: <I03110c4cdda70578828d6499262a085a81d26313+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11711

-gerrit

commit 78f9e25f58d45c55a185d4dd40d2a29963aefd19
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 25 09:26:54 2015 -0400

    util/kconfig: fill glob_t with 0 before calling glob
    
    On mingw, the function glob has some default options setting
    which is not compliant with manual.
    
    If gl_offs is not set as 0, there may be some slots which
    is reserved.
    If gl_pathc or gl_pathv is not set as 0, the returning value
    is not correct.
    
    Change-Id: I03110c4cdda70578828d6499262a085a81d26313
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/kconfig/zconf.lex.c_shipped | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/util/kconfig/zconf.lex.c_shipped b/util/kconfig/zconf.lex.c_shipped
index cf05b19..99a437b 100644
--- a/util/kconfig/zconf.lex.c_shipped
+++ b/util/kconfig/zconf.lex.c_shipped
@@ -2421,6 +2421,9 @@ void zconf_nextfiles(const char *wildcard)
 	char **w;
 	int i;
 
+	g.gl_pathc = 0;
+	g.gl_pathv = NULL;
+	g.gl_offs = 0;
 	if (glob(wildcard, 0, NULL, &g) != 0) {
 		return;
 	}


From gerrit at coreboot.org  Fri Sep 25 13:43:55 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Fri, 25 Sep 2015 13:43:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: armv7:
	Word-sized/half-word-sized memory operations for 32/16 bit
	read/write
References: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+0@gerrit.coreboot.org>
Message-ID: <I1fb3fc139e0a813acf9d70f14386a9603c9f9ede+5@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698

-gerrit

commit bc91a54bd5198da1fe399d88546e50f059ed4b42
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Tue Sep 22 22:16:33 2015 +0200

    armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
    
    Some registers only allow word-sized or half-word-sized operations and will
    cause a data fault when accessed with byte-sized operations.
    However, the compiler may or may not break such an operation into smaller
    (byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
    32 bit read/write and half-word-sized operations for 16 bit read/write.
    
    This is particularly the case on the rk3288 SRAM registers, where the watchdog
    tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
    compiler, where a 32 bit read would be broken into byte-sized chunks, which
    caused a data fault when accessing the watchdog tombstone register.
    
    The definitions for byte-sized memory operations are also adapted to stay
    consistent with the rest.
    
    Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/arch/arm/include/armv7/arch/io.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..2901ac2 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -30,39 +30,39 @@
 static inline uint8_t read8(const void *addr)
 {
 	dmb();
-	return *(volatile uint8_t *)addr;
+	return *(volatile uint8_t *)__builtin_assume_aligned(addr, sizeof(uint8_t));
 }
 
 static inline uint16_t read16(const void *addr)
 {
 	dmb();
-	return *(volatile uint16_t *)addr;
+	return *(volatile uint16_t *)__builtin_assume_aligned(addr, sizeof(uint16_t));
 }
 
 static inline uint32_t read32(const void *addr)
 {
 	dmb();
-	return *(volatile uint32_t *)addr;
+	return *(volatile uint32_t *)__builtin_assume_aligned(addr, sizeof(uint32_t));
 }
 
 static inline void write8(void *addr, uint8_t val)
 {
 	dmb();
-	*(volatile uint8_t *)addr = val;
+	*(volatile uint8_t *)__builtin_assume_aligned(addr, sizeof(uint8_t)) = val;
 	dmb();
 }
 
 static inline void write16(void *addr, uint16_t val)
 {
 	dmb();
-	*(volatile uint16_t *)addr = val;
+	*(volatile uint16_t *)__builtin_assume_aligned(addr, sizeof(uint16_t)) = val;
 	dmb();
 }
 
 static inline void write32(void *addr, uint32_t val)
 {
 	dmb();
-	*(volatile uint32_t *)addr = val;
+	*(volatile uint32_t *)__builtin_assume_aligned(addr, sizeof(uint32_t)) = val;
 	dmb();
 }
 


From gerrit at coreboot.org  Fri Sep 25 14:28:04 2015
From: gerrit at coreboot.org (Nico Huber (nico.h@gmx.de))
Date: Fri, 25 Sep 2015 14:28:04 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: gma ACPI: Make
	brightness levels a per board setting
References: <Ib865c7b4274f2ea3181a89fc52701b740f9bab7d+0@gerrit.coreboot.org>
Message-ID: <Ib865c7b4274f2ea3181a89fc52701b740f9bab7d+4@gerrit.coreboot.org>

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11705

-gerrit

commit 336e93d011ac3976e200c74c3194e2c962b52c35
Author: Nico Huber <nico.huber at secunet.com>
Date:   Thu Aug 27 13:31:46 2015 +0200

    gma ACPI: Make brightness levels a per board setting
    
    Those are actually board specific. Keep the old value as defaults,
    though. The defaults are included by all affected boards.
    
    Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/drivers/intel/gma/acpi/brightness_levels.asl   | 46 ----------------------
 .../intel/gma/acpi/configure_brightness_levels.asl | 24 +++++++++++
 .../intel/gma/acpi/default_brightness_levels.asl   | 24 +++++++++++
 src/drivers/intel/gma/acpi/non-pch.asl             |  2 +-
 src/drivers/intel/gma/acpi/pch.asl                 |  2 +-
 src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl        |  2 +
 src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl        |  2 +
 src/mainboard/google/bolt/dsdt.asl                 |  2 +
 src/mainboard/google/butterfly/dsdt.asl            |  2 +
 src/mainboard/google/falco/dsdt.asl                |  2 +
 src/mainboard/google/link/dsdt.asl                 |  2 +
 src/mainboard/google/panther/dsdt.asl              |  2 +
 src/mainboard/google/parrot/dsdt.asl               |  2 +
 src/mainboard/google/peppy/dsdt.asl                |  2 +
 src/mainboard/google/slippy/dsdt.asl               |  2 +
 src/mainboard/google/stout/dsdt.asl                |  2 +
 src/mainboard/intel/baskingridge/dsdt.asl          |  2 +
 src/mainboard/intel/cougar_canyon2/dsdt.asl        |  2 +
 src/mainboard/intel/emeraldlake2/dsdt.asl          |  2 +
 src/mainboard/kontron/ktqm77/dsdt.asl              |  2 +
 src/mainboard/lenovo/t400/dsdt.asl                 |  2 +
 src/mainboard/lenovo/t420s/dsdt.asl                |  2 +
 src/mainboard/lenovo/t430s/dsdt.asl                |  2 +
 src/mainboard/lenovo/t520/dsdt.asl                 |  2 +
 src/mainboard/lenovo/t530/dsdt.asl                 |  2 +
 src/mainboard/lenovo/x200/dsdt.asl                 |  2 +
 src/mainboard/lenovo/x201/dsdt.asl                 |  2 +
 src/mainboard/lenovo/x220/dsdt.asl                 |  2 +
 src/mainboard/lenovo/x230/dsdt.asl                 |  2 +
 src/mainboard/packardbell/ms2290/dsdt.asl          |  2 +
 src/mainboard/roda/rk9/dsdt.asl                    |  2 +
 src/mainboard/samsung/lumpy/dsdt.asl               |  2 +
 src/mainboard/samsung/stumpy/dsdt.asl              |  2 +
 33 files changed, 106 insertions(+), 48 deletions(-)

diff --git a/src/drivers/intel/gma/acpi/brightness_levels.asl b/src/drivers/intel/gma/acpi/brightness_levels.asl
deleted file mode 100644
index d0e70a9..0000000
--- a/src/drivers/intel/gma/acpi/brightness_levels.asl
+++ /dev/null
@@ -1,46 +0,0 @@
-	Name (BRIG, Package (0x12)
-	{
-		100, /* default AC */
-		100, /* default Battery */
-		  2,
-		  4,
-		  5,
-		  7,
-		  9,
-		 11,
-		 13,
-		 18,
-		 20,
-		 24,
-		 29,
-		 33,
-		 40,
-		 50,
-		 67,
-		100,
-	})
-
-	Method (XBCM, 1, NotSerialized)
-	{
-		Store (Divide (Multiply (Arg0, BCLM), 100), BCLV)
-	}
-
-	Method (XBQC, 0, NotSerialized)
-	{
-		/* Find value close to BCLV in BRIG (which must be ordered) */
-		Store (BCLV, Local0)			// Current value
-		Store (BCLM, Local1)			// For calculations
-		Store (2, Local2)			// Loop index
-		While (LLess (Local2, Subtract (SizeOf (BRIG), 1))) {
-			Store (DeRefOf (Index (BRIG, Local2)), Local3)
-			/* Use same calculation as XBCM, to get exact matches */
-			Store (Divide (Multiply (Local3, Local1), 100), Local3)
-
-			If (LLessEqual (Local0, Local3)) {
-				Return (DeRefOf (Index (BRIG, Local2)))
-			}
-			Add (Local2, 1, Local2)
-		}
-		/* Didn't find greater/equal value: use the last */
-		Return (DeRefOf (Index (BRIG, Local2)))
-	}
diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
new file mode 100644
index 0000000..38eb116
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -0,0 +1,24 @@
+	Method (XBCM, 1, NotSerialized)
+	{
+		Store (Divide (Multiply (Arg0, BCLM), 100), BCLV)
+	}
+
+	Method (XBQC, 0, NotSerialized)
+	{
+		/* Find value close to BCLV in BRIG (which must be ordered) */
+		Store (BCLV, Local0)			// Current value
+		Store (BCLM, Local1)			// For calculations
+		Store (2, Local2)			// Loop index
+		While (LLess (Local2, Subtract (SizeOf (BRIG), 1))) {
+			Store (DeRefOf (Index (BRIG, Local2)), Local3)
+			/* Use same calculation as XBCM, to get exact matches */
+			Store (Divide (Multiply (Local3, Local1), 100), Local3)
+
+			If (LLessEqual (Local0, Local3)) {
+				Return (DeRefOf (Index (BRIG, Local2)))
+			}
+			Add (Local2, 1, Local2)
+		}
+		/* Didn't find greater/equal value: use the last */
+		Return (DeRefOf (Index (BRIG, Local2)))
+	}
diff --git a/src/drivers/intel/gma/acpi/default_brightness_levels.asl b/src/drivers/intel/gma/acpi/default_brightness_levels.asl
new file mode 100644
index 0000000..6c6f35e
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/default_brightness_levels.asl
@@ -0,0 +1,24 @@
+Scope (GFX0)
+{
+	Name (BRIG, Package (0x12)
+	{
+		100, /* default AC */
+		100, /* default Battery */
+		  2,
+		  4,
+		  5,
+		  7,
+		  9,
+		 11,
+		 13,
+		 18,
+		 20,
+		 24,
+		 29,
+		 33,
+		 40,
+		 50,
+		 67,
+		100,
+	})
+}
diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl
index 0e15627..983dc01 100644
--- a/src/drivers/intel/gma/acpi/non-pch.asl
+++ b/src/drivers/intel/gma/acpi/non-pch.asl
@@ -37,6 +37,6 @@ Device (GFX0)
 		BCLM, 16,
 	}
 
-#include "brightness_levels.asl"
+#include "configure_brightness_levels.asl"
 #include "common.asl"
 }
diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl
index 98746e8..bd59a43 100644
--- a/src/drivers/intel/gma/acpi/pch.asl
+++ b/src/drivers/intel/gma/acpi/pch.asl
@@ -38,6 +38,6 @@ Device (GFX0)
 		BCLM, 16
 	}
 
-#include "brightness_levels.asl"
+#include "configure_brightness_levels.asl"
 #include "common.asl"
 }
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
index 9350dea..10faccd 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
@@ -22,6 +22,8 @@ DefinitionBlock(
 		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 		#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 }
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
index 9350dea..10faccd 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
@@ -22,6 +22,8 @@ DefinitionBlock(
 		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 		#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 }
diff --git a/src/mainboard/google/bolt/dsdt.asl b/src/mainboard/google/bolt/dsdt.asl
index 76998ba..597f1a3 100644
--- a/src/mainboard/google/bolt/dsdt.asl
+++ b/src/mainboard/google/bolt/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl
index 0a2f37d..e538cd6 100644
--- a/src/mainboard/google/butterfly/dsdt.asl
+++ b/src/mainboard/google/butterfly/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/falco/dsdt.asl b/src/mainboard/google/falco/dsdt.asl
index c9e9bb0..fcb7a3f 100644
--- a/src/mainboard/google/falco/dsdt.asl
+++ b/src/mainboard/google/falco/dsdt.asl
@@ -46,6 +46,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl
index a01533f..03ffb9e 100644
--- a/src/mainboard/google/link/dsdt.asl
+++ b/src/mainboard/google/link/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl
index e108717..b77a401 100644
--- a/src/mainboard/google/panther/dsdt.asl
+++ b/src/mainboard/google/panther/dsdt.asl
@@ -46,6 +46,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl
index 0a2f37d..e538cd6 100644
--- a/src/mainboard/google/parrot/dsdt.asl
+++ b/src/mainboard/google/parrot/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/peppy/dsdt.asl b/src/mainboard/google/peppy/dsdt.asl
index 76998ba..597f1a3 100644
--- a/src/mainboard/google/peppy/dsdt.asl
+++ b/src/mainboard/google/peppy/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl
index 76998ba..597f1a3 100644
--- a/src/mainboard/google/slippy/dsdt.asl
+++ b/src/mainboard/google/slippy/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl
index 01e4001..ca8640b 100644
--- a/src/mainboard/google/stout/dsdt.asl
+++ b/src/mainboard/google/stout/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl
index b586e34..7e37428 100644
--- a/src/mainboard/intel/baskingridge/dsdt.asl
+++ b/src/mainboard/intel/baskingridge/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/haswell/acpi/haswell.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/intel/cougar_canyon2/dsdt.asl b/src/mainboard/intel/cougar_canyon2/dsdt.asl
index 82d6ee5..494e72f 100644
--- a/src/mainboard/intel/cougar_canyon2/dsdt.asl
+++ b/src/mainboard/intel/cougar_canyon2/dsdt.asl
@@ -45,6 +45,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/fsp_bd82x6x/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl
index b545838..b4afa3d 100644
--- a/src/mainboard/intel/emeraldlake2/dsdt.asl
+++ b/src/mainboard/intel/emeraldlake2/dsdt.asl
@@ -48,6 +48,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl
index 9dbe7e5..7a4b9b1 100644
--- a/src/mainboard/kontron/ktqm77/dsdt.asl
+++ b/src/mainboard/kontron/ktqm77/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl
index 6274755..1d62057 100644
--- a/src/mainboard/lenovo/t400/dsdt.asl
+++ b/src/mainboard/lenovo/t400/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/gm45/acpi/gm45.asl>
 			#include <southbridge/intel/i82801ix/acpi/ich9.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl
index 64e4e9f..fb653ea 100644
--- a/src/mainboard/lenovo/t420s/dsdt.asl
+++ b/src/mainboard/lenovo/t420s/dsdt.asl
@@ -51,6 +51,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl
index 64e4e9f..fb653ea 100644
--- a/src/mainboard/lenovo/t430s/dsdt.asl
+++ b/src/mainboard/lenovo/t430s/dsdt.asl
@@ -51,6 +51,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl
index f5f3ace..9a75807 100644
--- a/src/mainboard/lenovo/t520/dsdt.asl
+++ b/src/mainboard/lenovo/t520/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl
index f5f3ace..9a75807 100644
--- a/src/mainboard/lenovo/t530/dsdt.asl
+++ b/src/mainboard/lenovo/t530/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl
index 5545c94..110cada 100644
--- a/src/mainboard/lenovo/x200/dsdt.asl
+++ b/src/mainboard/lenovo/x200/dsdt.asl
@@ -47,6 +47,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/gm45/acpi/gm45.asl>
 			#include <southbridge/intel/i82801ix/acpi/ich9.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
index f2f0a89..15e85b2 100644
--- a/src/mainboard/lenovo/x201/dsdt.asl
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/nehalem/acpi/nehalem.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 		Device (UNCR)
 		{
diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl
index f5f3ace..9a75807 100644
--- a/src/mainboard/lenovo/x220/dsdt.asl
+++ b/src/mainboard/lenovo/x220/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
index 1c71c3c..1ef9f11 100644
--- a/src/mainboard/lenovo/x230/dsdt.asl
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -50,6 +50,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 /*
diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl
index c2d96f3..b36f909 100644
--- a/src/mainboard/packardbell/ms2290/dsdt.asl
+++ b/src/mainboard/packardbell/ms2290/dsdt.asl
@@ -44,6 +44,8 @@ DefinitionBlock(
 			#include <northbridge/intel/nehalem/acpi/nehalem.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 		Device (UNCR)
 		{
diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl
index c955c86..1a86440 100644
--- a/src/mainboard/roda/rk9/dsdt.asl
+++ b/src/mainboard/roda/rk9/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/gm45/acpi/gm45.asl>
 			#include <southbridge/intel/i82801ix/acpi/ich9.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
index 1ab6322..13d8593 100644
--- a/src/mainboard/samsung/lumpy/dsdt.asl
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -51,6 +51,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 
diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl
index 0a2f37d..e538cd6 100644
--- a/src/mainboard/samsung/stumpy/dsdt.asl
+++ b/src/mainboard/samsung/stumpy/dsdt.asl
@@ -49,6 +49,8 @@ DefinitionBlock(
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
 


From gerrit at coreboot.org  Fri Sep 25 14:38:34 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:34 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfs: read cbfs
	offset and size from sysinfo
References: <I86434fd249467e7c90d59d6b82f0e6c514bc2d05+0@gerrit.coreboot.org>
Message-ID: <I86434fd249467e7c90d59d6b82f0e6c514bc2d05+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11557

-gerrit

commit df4b2eb0856b67d072386d6b5dc4e616f0d9be6d
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Sep 2 10:53:13 2015 -0700

    cbfs: read cbfs offset and size from sysinfo
    
    This change allows libpayload to read cbfs offset and size from sysinfo.
    Legacy way of locating cbfs reagion is still supported in case sysinfo
    doesn't store the offset and the size.
    
    BUG=none
    BRANCH=master
    TEST=tested on samus and smaug
    
    Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c
    Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296993
    Original-Commit-Ready: Daisuke Nojiri <dnojiri at google.com>
    Original-Tested-by: Daisuke Nojiri <dnojiri at google.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 payloads/libpayload/libcbfs/cbfs_core.c | 70 +++++++++++++++++++++------------
 1 file changed, 45 insertions(+), 25 deletions(-)

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 153dc8a..f85006c 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -47,6 +47,7 @@
 
 #include <cbfs.h>
 #include <string.h>
+#include <sysinfo.h>
 
 /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS
  *  on failure */
@@ -94,52 +95,71 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
 	return header;
 }
 
-/* public API starts here*/
-struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end,
+			  struct cbfs_media *media)
 {
-	const char *vardata;
-	uint32_t offset, romsize, vardata_len;
 	const struct cbfs_header *header;
-	struct cbfs_file file, *file_ptr;
-	struct cbfs_media default_media;
 
-	if (media == CBFS_DEFAULT_MEDIA) {
-		media = &default_media;
-		if (init_default_cbfs_media(media) != 0) {
-			ERROR("Failed to initialize default media.\n");
-			return NULL;
-		}
+	if (lib_sysinfo.cbfs_offset && lib_sysinfo.cbfs_size) {
+		*offset = lib_sysinfo.cbfs_offset;
+		*cbfs_end = *offset + lib_sysinfo.cbfs_size;
+		return 0;
 	}
 
-	if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media)))
-		return NULL;
-
+	/*
+	 * If sysinfo doesn't have offset or size, we read them from
+	 * a master header.
+	 */
+	DEBUG("CBFS offset & size not found in sysinfo\n");
+	header = cbfs_get_header(media);
+	if (header == CBFS_HEADER_INVALID_ADDRESS)
+		return -1;
 	// Logical offset (for source media) of first file.
-	offset = ntohl(header->offset);
-	romsize = ntohl(header->romsize);
-
-	// TODO Add a "size" in CBFS header for a platform independent way to
-	// determine the end of CBFS data.
+	*offset = ntohl(header->offset);
+	*cbfs_end = ntohl(header->romsize);
 #if IS_ENABLED(CONFIG_LP_ARCH_X86)
 	// resolve actual length of ROM used for CBFS components
 	// the bootblock size was not taken into account
-	romsize -= ntohl(header->bootblocksize);
+	*cbfs_end -= ntohl(header->bootblocksize);
 
 	// fine tune the length to handle alignment positioning.
 	// using (bootblock size) % align, to derive the
 	// number of bytes the bootblock is off from the alignment size.
 	if ((ntohl(header->bootblocksize) % CBFS_ALIGNMENT))
-		romsize -= (CBFS_ALIGNMENT -
+		*cbfs_end -= (CBFS_ALIGNMENT -
 			(ntohl(header->bootblocksize) % CBFS_ALIGNMENT));
 	else
-		romsize -= 1;
+		*cbfs_end -= 1;
 #endif
+	return 0;
+}
+
+/* public API starts here*/
+struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+{
+	const char *vardata;
+	uint32_t offset, cbfs_end, vardata_len;
+	struct cbfs_file file, *file_ptr;
+	struct cbfs_media default_media;
+
+	if (media == CBFS_DEFAULT_MEDIA) {
+		media = &default_media;
+		if (init_default_cbfs_media(media) != 0) {
+			ERROR("Failed to initialize default media.\n");
+			return NULL;
+		}
+	}
+
+	if (get_cbfs_range(&offset, &cbfs_end, media)) {
+		ERROR("Failed to find cbfs range\n");
+		return NULL;
+	}
 
-	DEBUG("CBFS location: 0x%x~0x%x\n", offset, romsize);
+	DEBUG("CBFS location: 0x%x~0x%x\n", offset, cbfs_end);
 	DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset);
 
 	media->open(media);
-	while (offset < romsize &&
+	while (offset < cbfs_end &&
 	       media->read(media, &file, offset, sizeof(file)) == sizeof(file)) {
 		if (memcmp(CBFS_FILE_MAGIC, file.magic,
 			   sizeof(file.magic)) != 0) {


From gerrit at coreboot.org  Fri Sep 25 14:38:36 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:36 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: ec: superio:
	Report keyboard IRQ as wake capable
References: <I7175d2ea98f8a671765897de295df7b933151fc4+0@gerrit.coreboot.org>
Message-ID: <I7175d2ea98f8a671765897de295df7b933151fc4+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11712

-gerrit

commit 5a598e2bdb90a95047dced0fd84af35503525f8b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Sep 21 15:00:20 2015 -0700

    ec: superio: Report keyboard IRQ as wake capable
    
    In order to wake from S0ix the kernel needs to know that the
    keyboard interrupt is wake capable.  Using IRQNoFlags does not
    allow the wake capability to be reported.
    
    For normal S3 this does not matter as the EC is the one handling
    the keyboard wake event.  For S0ix the EC does not need to be
    involved in this particular wake event.
    
    BUG=chrome-os-partner:43079
    BRANCH=none
    TEST=echo freeze > /sys/power/state and wake from keyboard
    
    Change-Id: I7175d2ea98f8a671765897de295df7b933151fc4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 645f1cd96c35f42aa7c40ff473b15feb619b0373
    Original-Change-Id: Ia89c30c51be9db7b814b81261463d938885325fd
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/301441
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/ec/google/chromeec/acpi/superio.asl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl
index 39e60a3..b27f6d6 100644
--- a/src/ec/google/chromeec/acpi/superio.asl
+++ b/src/ec/google/chromeec/acpi/superio.asl
@@ -155,7 +155,7 @@ Device (SIO) {
 #ifdef SIO_EC_PS2K_IRQ
 			SIO_EC_PS2K_IRQ
 #else
-			IRQNoFlags () {1}
+			IRQ (Edge, ActiveHigh, ExclusiveAndWake) {1}
 #endif
 		})
 
@@ -167,7 +167,7 @@ Device (SIO) {
 #ifdef SIO_EC_PS2K_IRQ
 				SIO_EC_PS2K_IRQ
 #else
-				IRQNoFlags () {1}
+				IRQ (Edge, ActiveHigh, ExclusiveAndWake) {1}
 #endif
 			}
 			EndDependentFn ()


From gerrit at coreboot.org  Fri Sep 25 14:38:38 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:38 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfs: fix debug
	message
References: <I0b555d018f8c2eb1b51519a6227298c8d5d58a42+0@gerrit.coreboot.org>
Message-ID: <I0b555d018f8c2eb1b51519a6227298c8d5d58a42+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11713

-gerrit

commit d49004eb90de7f638f5c161d144394f737749ac0
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Sep 23 13:01:14 2015 -0700

    cbfs: fix debug message
    
    BUG=none
    BRANCH=tot
    TEST=built for Samus with debugging enabled
    
    Change-Id: I0b555d018f8c2eb1b51519a6227298c8d5d58a42
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5908e4b8ffc66e6ecc7cae78cf10055fbd727c81
    Original-Change-Id: Ifd049111fee540789dabb1d7653568b80405b77d
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302131
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 payloads/libpayload/libcbfs/cbfs_core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index f85006c..2e057b0 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -240,7 +240,8 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 		struct cbfs_file_attr_compression *comp =
 			(struct cbfs_file_attr_compression *)attr;
 		compression_algo = ntohl(comp->compression);
-		DEBUG("File '%s' is compressed (alg=%d)\n", compression_algo);
+		DEBUG("File '%s' is compressed (alg=%d)\n",
+		      name, compression_algo);
 		*sz = ntohl(comp->decompressed_size);
 	}
 


From gerrit at coreboot.org  Fri Sep 25 14:38:40 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:40 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbfs: allow
	cbfs-files to use compression
References: <I29ba0c6f8290b500072a0b17460ee590d6bb6efa+0@gerrit.coreboot.org>
Message-ID: <I29ba0c6f8290b500072a0b17460ee590d6bb6efa+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11714

-gerrit

commit 44aaac9c3c0b297d8ef4da1f514a5bbd225bd4ab
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Tue Sep 22 15:21:36 2015 -0700

    cbfs: allow cbfs-files to use compression
    
    This change allows files added to cbfs-files-y to specify compression
    algorithm.
    
    BUG=none
    BRANCH=tot
    TEST=Tested on Samus
    
    Change-Id: I29ba0c6f8290b500072a0b17460ee590d6bb6efa
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4284160bdbbc54ed1da8b5477b02ee315061206b
    Original-Change-Id: Idf81e1cc0a1030449da632f6d89cdc87c624f9f3
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302132
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 Makefile.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Makefile.inc b/Makefile.inc
index ac6ce0b..b56d0a4 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -566,7 +566,9 @@ cbfs-add-cmd = \
 	       $(CBFSTOOL) $@.tmp \
 	       add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage)$(if $(filter payload,$(call extract_nth,3,$(file))),-payload) \
 	       -f $(call extract_nth,1,$(file)) \
-	       -n $(call extract_nth,2,$(file)) $(if $(filter-out stage,$(call extract_nth,3,$(file))),-t $(call extract_nth,3,$(file)))
+	       -n $(call extract_nth,2,$(file)) \
+	       $(if $(filter-out stage,$(call extract_nth,3,$(file))),-t $(call extract_nth,3,$(file))) \
+	       $(if $(call extract_nth,4,$(file)),-c $(call extract_nth,4,$(file)))
 
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 prebuild-files = \


From gerrit at coreboot.org  Fri Sep 25 14:38:43 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:43 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: tpm: acpi: Make
	_CRS method serialized
References: <I59a52552ab24b7d9c9928331aa8c8d19f54fd1b7+0@gerrit.coreboot.org>
Message-ID: <I59a52552ab24b7d9c9928331aa8c8d19f54fd1b7+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11715

-gerrit

commit d9d1e3e3e451f4fc1248b4bb3d59f3c1e07d0073
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 22 09:39:23 2015 -0700

    tpm: acpi: Make _CRS method serialized
    
    Since the TPM _CRS method creates named objects it needs
    to be serialized to prevent a warning in recent iasl.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build glados with iasl-20150717
    
    Change-Id: I59a52552ab24b7d9c9928331aa8c8d19f54fd1b7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 2a5c474c94980661573a99eb94d5f661f2d0114b
    Original-Change-Id: Ie9d164ea8781304dd0bf1833d182d7c601b8e18d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302162
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/pc80/tpm/acpi/tpm.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl
index ece63e2..489fec7 100644
--- a/src/drivers/pc80/tpm/acpi/tpm.asl
+++ b/src/drivers/pc80/tpm/acpi/tpm.asl
@@ -47,7 +47,7 @@ Device (TPM)
 		Memory32Fixed (ReadWrite, CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000)
 	})
 
-	Method (_CRS, 0, NotSerialized)
+	Method (_CRS, 0, Serialized)
 	{
 		OperationRegion (TREG, SystemMemory,
 				 CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000)


From gerrit at coreboot.org  Fri Sep 25 14:38:45 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:45 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: chromeec: Fix
	ACPI compile warnings
References: <I1d4535205426dd9a6346f53ff159221cf5cd899a+0@gerrit.coreboot.org>
Message-ID: <I1d4535205426dd9a6346f53ff159221cf5cd899a+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11716

-gerrit

commit 24ca616f3dd6f55b9b9756ded797cf4ff5dffcf4
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 22 09:40:37 2015 -0700

    chromeec: Fix ACPI compile warnings
    
    Recent version of iasl are flagging more things as warnings.
    Remove unused Local0 uses and make _CRS method serialized to
    fix these warnings.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build glados with iasl-20150717
    
    Change-Id: I1d4535205426dd9a6346f53ff159221cf5cd899a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8b43f8f24bb7cb33ad0411c24616da66663c2e3e
    Original-Change-Id: I71eafd91d30d5f50e6211368f0bbc517c8085892
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302163
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/ec/google/chromeec/acpi/battery.asl |  8 ++++----
 src/ec/google/chromeec/acpi/ec.asl      | 12 ++++++------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl
index 6c083ae..e3a4c2e 100644
--- a/src/ec/google/chromeec/acpi/battery.asl
+++ b/src/ec/google/chromeec/acpi/battery.asl
@@ -110,11 +110,11 @@ Device (BAT0)
 		Store (Local0, Index (PBIF, 1))
 
 		// Design Capacity of Warning
-		Divide (Multiply (Local0, DWRN), 100, Local1, Local2)
+		Divide (Multiply (Local0, DWRN), 100, , Local2)
 		Store (Local2, Index (PBIF, 5))
 
 		// Design Capacity of Low
-		Divide (Multiply (Local0, DLOW), 100, Local1, Local2)
+		Divide (Multiply (Local0, DLOW), 100, , Local2)
 		Store (Local2, Index (PBIF, 6))
 
 		// Get battery info from mainboard
@@ -138,11 +138,11 @@ Device (BAT0)
 		Store (Local0, Index (PBIX, 2))
 
 		// Design Capacity of Warning
-		Divide (Multiply (Local0, DWRN), 100, Local1, Local2)
+		Divide (Multiply (Local0, DWRN), 100, , Local2)
 		Store (Local2, Index (PBIX, 6))
 
 		// Design Capacity of Low
-		Divide (Multiply (Local0, DLOW), 100, Local1, Local2)
+		Divide (Multiply (Local0, DLOW), 100, , Local2)
 		Store (Local2, Index (PBIX, 7))
 
 		// Cycle Count
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 8b4f91d..4afb1bc 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -86,7 +86,7 @@ Device (EC0)
 		}
 	}
 
-	Method (_CRS, 0, NotSerialized)
+	Method (_CRS, 0, Serialized)
 	{
 		Name (ECMD, ResourceTemplate()
 		{
@@ -257,7 +257,7 @@ Device (EC0)
 	Method (_Q12, 0, NotSerialized)
 	{
 		Store ("EC: THROTTLE START", Debug)
-		If (CondRefOf (\_TZ.THRT, Local0)) {
+		If (CondRefOf (\_TZ.THRT)) {
 			\_TZ.THRT (1)
 		}
 	}
@@ -266,7 +266,7 @@ Device (EC0)
 	Method (_Q13, 0, NotSerialized)
 	{
 		Store ("EC: THROTTLE STOP", Debug)
-		If (CondRefOf (\_TZ.THRT, Local0)) {
+		If (CondRefOf (\_TZ.THRT)) {
 			\_TZ.THRT (0)
 		}
 	}
@@ -309,7 +309,7 @@ Device (EC0)
 		Store (ToInteger (Arg0), ^PATI)
 
 		/* Temperature is passed in 1/10 Kelvin */
-		Divide (ToInteger (Arg1), 10, Local0, Local1)
+		Divide (ToInteger (Arg1), 10, , Local1)
 
 		/* Adjust by EC temperature offset */
 		Subtract (Local1, ^TOFS, ^PATT)
@@ -336,7 +336,7 @@ Device (EC0)
 		Store (ToInteger (Arg0), ^PATI)
 
 		/* Temperature is passed in 1/10 Kelvin */
-		Divide (ToInteger (Arg1), 10, Local0, Local1)
+		Divide (ToInteger (Arg1), 10, , Local1)
 
 		/* Adjust by EC temperature offset */
 		Subtract (Local1, ^TOFS, ^PATT)
@@ -385,7 +385,7 @@ Device (EC0)
 		/* When sensor ID returns 0xFF then no more events */
 		While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT))
 		{
-			If (CondRefOf (\_SB.DPTF.TEVT, Local1)) {
+			If (CondRefOf (\_SB.DPTF.TEVT)) {
 				\_SB.DPTF.TEVT (Local0)
 			}
 


From gerrit at coreboot.org  Fri Sep 25 14:38:49 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:49 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Fix
	typo for WLAN ACPI device name
References: <I8d61a6653c3109890d04e54f0d694703b9c9f2bf+0@gerrit.coreboot.org>
Message-ID: <I8d61a6653c3109890d04e54f0d694703b9c9f2bf+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11717

-gerrit

commit d22636f27ac324bcf385ee0712ad42ca2d270d49
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 22 09:41:37 2015 -0700

    glados: Fix typo for WLAN ACPI device name
    
    Fix the typo of _DDR to be _DDN.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build glados with iasl-20150717
    
    Change-Id: I8d61a6653c3109890d04e54f0d694703b9c9f2bf
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d4a2b2583bdbf9afd7b306359338d4c49bbb44ad
    Original-Change-Id: I7b7905a217d34a8a78b8280c898f1074ecbe3cf6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302164
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi/mainboard.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
index 038a4ef..eba18a7 100644
--- a/src/mainboard/google/glados/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -65,7 +65,7 @@ Scope (\_SB.PCI0.RP01)
 	Device (WLAN)
 	{
 		Name (_ADR, 0x00000000)
-		Name (_DDR, "Wireless LAN")
+		Name (_DDN, "Wireless LAN")
 		Name (_PRW, Package () { GPE_WLAN_WAKE, 3 })
 	}
 }


From gerrit at coreboot.org  Fri Sep 25 14:38:54 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:54 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kunimitsu: Fix
	typo for WLAN ACPI device name
References: <I1e7c20d450ea897bfd24506d10a5f466b03610e4+0@gerrit.coreboot.org>
Message-ID: <I1e7c20d450ea897bfd24506d10a5f466b03610e4+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11718

-gerrit

commit 9dc7ec1a5ab4971e52de877747b07fa08fb24e3e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 22 09:41:50 2015 -0700

    kunimitsu: Fix typo for WLAN ACPI device name
    
    Fix the typo of _DDR to be _DDN.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build kunimitsu with iasl-20150717
    
    Change-Id: I1e7c20d450ea897bfd24506d10a5f466b03610e4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f136581b653bfb63aac24065c8837307e3fc5432
    Original-Change-Id: I3358e6d3d05bcfc291199e8ef12ff92c66f5b74f
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302165
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
index 73193dd..22f8403 100644
--- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
+++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
@@ -66,7 +66,7 @@ Scope (\_SB.PCI0.RP01)
 	Device (WLAN)
 	{
 		Name (_ADR, 0x00000000)
-		Name (_DDR, "Wireless LAN")
+		Name (_DDN, "Wireless LAN")
 		Name (_PRW, Package () { GPE_WLAN_WAKE, 3 })
 	}
 }


From gerrit at coreboot.org  Fri Sep 25 14:38:59 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:38:59 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: ACPI:
	Remove Configurable TDP support code
References: <I81e356ddf564a5253458b82bc3327bfb573ab16d+0@gerrit.coreboot.org>
Message-ID: <I81e356ddf564a5253458b82bc3327bfb573ab16d+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11719

-gerrit

commit 95accdfefbdb56dcb96551f95ea95734bebc7a04
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Sep 23 17:53:31 2015 -0700

    skylake: ACPI: Remove Configurable TDP support code
    
    Remove the CTDP support code that is in ACPI.  It has been ported
    from haswell and while the MCHBAR register interface does seem to
    still exist the calculations for determining PL2 is no longer
    straightforward.
    
    Additionally nothing is using this interface and the expectation
    is that DPTF will be used for throttling with PL[1234] and having
    ACPI interfere with the configuration would not be good.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I81e356ddf564a5253458b82bc3327bfb573ab16d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 884ee9a764bad0b3b4bcaeb5a3f46c5f090a116c
    Original-Change-Id: I284ab52a305cee25c88df5228b01ff1e9544efe3
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302166
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/ctdp.asl        | 239 -----------------------------
 src/soc/intel/skylake/acpi/systemagent.asl |   3 -
 2 files changed, 242 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/ctdp.asl b/src/soc/intel/skylake/acpi/ctdp.asl
deleted file mode 100644
index 1668b4c..0000000
--- a/src/soc/intel/skylake/acpi/ctdp.asl
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Scope (\_SB.PCI0.MCHC)
-{
-	Mutex (CTCM, 1)		/* CTDP Switch Mutex (sync level 1) */
-	Name (CTCC, 0)		/* CTDP Current Selection */
-	Name (CTCN, 0)		/* CTDP Nominal Select */
-	Name (CTCD, 1)		/* CTDP Down Select */
-	Name (CTCU, 2)		/* CTDP Up Select */
-	Name (SPL1, 0)		/* Saved PL1 value */
-
-	OperationRegion (MCHB, SystemMemory,
-			Add (MCH_BASE_ADDRESS, 0x5000), 0x1000)
-	Field (MCHB, DWordAcc, Lock, Preserve)
-	{
-		Offset (0x930),	/* PACKAGE_POWER_SKU */
-		CTDN, 15,	/* CTDP Nominal PL1 */
-		Offset (0x938),	/* PACKAGE_POWER_SKU_UNIT */
-		PUNI, 4,	/* Power Units */
-		,     4,
-		EUNI, 5,	/* Energy Units */
-		,     3,
-		TUNI, 4,	/* Time Units */
-		Offset (0x958),	/* PLATFORM_INFO */
-		,     32,
-		LPMS, 1,	/* LPM Support */
-		CTNL, 2,	/* Config TDP Number level */
-		,     5,
-		LFM_, 8,	/* Maximum Efficiency Ratio (LFM) */
-		Offset (0x9a0),	/* TURBO_POWER_LIMIT1 */
-		PL1V, 15,	/* Power Limit 1 Value */
-		PL1E, 1,	/* Power Limit 1 Enable */
-		PL1C, 1,	/* Power Limit 1 Clamp */
-		PL1T, 7,	/* Power Limit 1 Time */
-		Offset (0x9a4),	/* TURBO_POWER_LIMIT2 */
-		PL2V, 15,	/* Power Limit 2 Value */
-		PL2E, 1,	/* Power Limit 2 Enable */
-		PL2C, 1,	/* Power Limit 2 Clamp */
-		PL2T, 7,	/* Power Limit 2 Time */
-		Offset (0xf3c),	/* CONFIG_TDP_NOMINAL */
-		TARN, 8,	/* CTDP Nominal Turbo Activation Ratio */
-		Offset (0xf40),	/* CONFIG_TDP_LEVEL1 */
-		CTDD, 15,	/* CTDP Down PL1 */
-		,     1,
-		TARD, 8,	/* CTDP Down Turbo Activation Ratio */
-		Offset (0xf48),	/* MSR_CONFIG_TDP_LEVEL2 */
-		CTDU, 15,	/* CTDP Up PL1 */
-		,     1,
-		TARU, 8,	/* CTDP Up Turbo Activation Ratio */
-		Offset (0xf50),	/* CONFIG_TDP_CONTROL */
-		CTCS, 2,	/* CTDP Select */
-		Offset (0xf54),	/* TURBO_ACTIVATION_RATIO */
-		TARS, 8,	/* Turbo Activation Ratio Select */
-	}
-
-	/*
-	 * Search CPU0 _PSS looking for control=arg0 and then
-	 * return previous P-state entry number for new _PPC
-	 *
-	 * Format of _PSS:
-	 *   Name (_PSS, Package () {
-	 *     Package (6) { freq, power, tlat, blat, control, status }
-	 *   }
-	 */
-	External (\_PR.CP00._PSS)
-	Method (PSSS, 1, NotSerialized)
-	{
-		Store (One, Local0) /* Start at P1 */
-		Store (SizeOf (\_PR.CP00._PSS), Local1)
-
-		While (LLess (Local0, Local1)) {
-			/* Store _PSS entry Control value to Local2 */
-			ShiftRight (DeRefOf (Index (DeRefOf (Index
-				(\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
-			If (LEqual (Local2, Arg0)) {
-				Return (Subtract (Local0, 1))
-			}
-			Increment (Local0)
-		}
-
-		Return (0)
-	}
-
-	/* Calculate PL2 based on chip type */
-	Method (CPL2, 1, NotSerialized)
-	{
-		Return (Multiply (25, 8))
-	}
-
-	/* Set Config TDP Down */
-	Method (STND, 0, Serialized)
-	{
-		If (Acquire (CTCM, 100)) {
-			Return (0)
-		}
-		If (LEqual (CTCD, CTCC)) {
-			Release (CTCM)
-			Return (0)
-		}
-
-		Store ("Set TDP Down", Debug)
-
-		/* Set CTC */
-		Store (CTCD, CTCS)
-
-		/* Set TAR */
-		Store (TARD, TARS)
-
-		/* Set PPC limit and notify OS */
-		Store (PSSS (TARD), PPCM)
-		PPCN ()
-
-		/* Set PL2 */
-		Store (CPL2 (CTDD), PL2V)
-
-		/* Set PL1 */
-		Store (CTDD, PL1V)
-
-		/* Store the new TDP Down setting */
-		Store (CTCD, CTCC)
-
-		Release (CTCM)
-		Return (1)
-	}
-
-	/* Set Config TDP Nominal from Down */
-	Method (STDN, 0, Serialized)
-	{
-		If (Acquire (CTCM, 100)) {
-			Return (0)
-		}
-		If (LEqual (CTCN, CTCC)) {
-			Release (CTCM)
-			Return (0)
-		}
-
-		Store ("Set TDP Nominal", Debug)
-
-		/* Set PL1 */
-		Store (CTDN, PL1V)
-
-		/* Set PL2 */
-		Store (CPL2 (CTDN), PL2V)
-
-		/* Set PPC limit and notify OS */
-		Store (PSSS (TARN), PPCM)
-		PPCN ()
-
-		/* Set TAR */
-		Store (TARN, TARS)
-
-		/* Set CTC */
-		Store (CTCN, CTCS)
-
-		/* Store the new TDP Nominal setting */
-		Store (CTCN, CTCC)
-
-		Release (CTCM)
-		Return (1)
-	}
-
-	/* Calculate PL1 value based on requested TDP */
-	Method (TDPP, 1, NotSerialized)
-	{
-		Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0))
-	}
-
-	/* Enable Controllable TDP to limit PL1 to requested value */
-	Method (CTLE, 1, Serialized)
-	{
-		If (Acquire (CTCM, 100)) {
-			Return (0)
-		}
-
-		Store ("Enable PL1 Limit", Debug)
-
-		/* Set _PPC to LFM */
-		Store (PSSS (LFM_), Local0)
-		Add (Local0, 1, PPCM)
-		\PPCN ()
-
-		/* Set TAR to LFM-1 */
-		Subtract (LFM_, 1, TARS)
-
-		/* Set PL1 to desired value */
-		Store (PL1V, SPL1)
-		Store (TDPP (Arg0), PL1V)
-
-		/* Set PL1 CLAMP bit */
-		Store (One, PL1C)
-
-		Release (CTCM)
-		Return (1)
-	}
-
-	/* Disable Controllable TDP */
-	Method (CTLD, 0, Serialized)
-	{
-		If (Acquire (CTCM, 100)) {
-			Return (0)
-		}
-
-		Store ("Disable PL1 Limit", Debug)
-
-		/* Clear PL1 CLAMP bit */
-		Store (Zero, PL1C)
-
-		/* Set PL1 to normal value */
-		Store (SPL1, PL1V)
-
-		/* Set TAR to 0 */
-		Store (Zero, TARS)
-
-		/* Set _PPC to 0 */
-		Store (Zero, PPCM)
-		\PPCN ()
-
-		Release (CTCM)
-		Return (1)
-	}
-}
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 9c9fc17..dd19fa1 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -374,6 +374,3 @@ Device (PDRC)
 
 /* PCI IRQ assignment */
 #include "pci_irqs.asl"
-
-/* Configurable TDP */
-#include "ctdp.asl"


From gerrit at coreboot.org  Fri Sep 25 14:39:02 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:39:02 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: glados: Provide
	nau8825 platform data via _DSD
References: <I813a985b4a39249a2cdbe45117acbdb7710bfa29+0@gerrit.coreboot.org>
Message-ID: <I813a985b4a39249a2cdbe45117acbdb7710bfa29+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11720

-gerrit

commit 525c9541da4b9654df89631f3329434c3da3194e
Author: Ben Zhang <benzh at chromium.org>
Date:   Tue Aug 4 22:02:53 2015 -0700

    glados: Provide nau8825 platform data via _DSD
    
    BUG=chrome-os-partner:41280
    BRANCH=none
    TEST=Audio jack insert/eject detection and headset buttons work
    on glados with the nau8825 driver in chromeos-3.18 and the
    staging kernel skl2.
    
    Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb
    Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80
    Original-Signed-off-by: Ben Zhang <benzh at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/293610
    Original-Reviewed-by: Anatol Pomazau <anatol at google.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/glados/acpi/mainboard.asl | 37 ++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
index eba18a7..b449ec4 100644
--- a/src/mainboard/google/glados/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -143,6 +143,43 @@ Scope (\_SB.PCI0.I2C4)
 		Name (_DDN, "NAU88L25 Codec")
 		Name (_UID, 1)
 
+		/*
+		 * Add DT style bindings with _DSD
+		 * Device property values are documented in kernel doc
+		 * Documentation/devicetree/bindings/sound/nau8825.txt
+		 */
+		Name (_DSD, Package () {
+			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+				/* Enable jack detection via JKDET pin */
+				Package () {"nuvoton,jkdet-enable", 1},
+				/*
+				 * JKDET pin is pulled up by R389 on board.
+				 * JKDET pin polarity = active low
+				 */
+				Package () {"nuvoton,jkdet-polarity", 1},
+				/* VREF Impedance = 125 kOhm */
+				Package () {"nuvoton,vref-impedance", 2},
+				/* VDDA(1.8) * 1.53 = 2.754 */
+				Package () {"nuvoton,micbias-voltage", 6},
+				/*
+				 * Setup 4 buttons impedance according to
+				 * Android specification
+				 */
+				Package () {"nuvoton,sar-threshold-num", 4},
+				Package () {"nuvoton,sar-threshold",
+					Package () {0xc, 0x1e, 0x38, 0x60}},
+				Package () {"nuvoton,sar-hysteresis", 1},
+				/* VDDA for button impedance measurement */
+				Package () {"nuvoton,sar-voltage", 0},
+				/* 100ms short key press debounce */
+				Package () {"nuvoton,short-key-debounce", 2},
+				/* 2^(7+2) = 512 ms insert/eject debounce */
+				Package () {"nuvoton,jack-insert-debounce", 7},
+				Package () {"nuvoton,jack-eject-debounce", 7},
+			}
+		})
+
 		Name (_CRS, ResourceTemplate()
 		{
 			I2cSerialBus (


From gerrit at coreboot.org  Fri Sep 25 14:39:04 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:39:04 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: Work
	around issue in ACPI interpreter
References: <I7b6a3b792f79755db0ea7b9f2ef6ee7f5000e018+0@gerrit.coreboot.org>
Message-ID: <I7b6a3b792f79755db0ea7b9f2ef6ee7f5000e018+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11721

-gerrit

commit e32c202418dc312173da844e1892a474d280e20b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Sep 23 17:57:20 2015 -0700

    skylake: Work around issue in ACPI interpreter
    
    There appears to be an issue that is causing this particular bit of
    ACPI code to be incorrectly interpreted by the kernel and the IASL
    disassembler.
    
    Ensuring the PCRB() method is defined in the DSDT before any uses of
    it appears to fix the problem, but that relies on specific ordering
    of the ASL files included by pch.asl and may break again in the future
    if the includes were re-ordered.  (they are alphabetic now)
    
    So in this case to work around the issue unroll the function call so
    the admittedly messy calculation is reduced to a constant when compiled.
    
    Note this issue was observed with both iasl-20130117 and
    iasl-20150717.
    
    ACPICA bug: https://bugs.acpica.org/show_bug.cgi?id=1201
    
    BUG=chrome-os-partner:45760
    BRANCH=none
    TEST=verify disassembled AML is correct
    
    Change-Id: I7b6a3b792f79755db0ea7b9f2ef6ee7f5000e018
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: ecacc340d6e1068ea649f0859657bb3208695730
    Original-Change-Id: I232523f5b6ce290da6e7d99405a53b9437b10e0d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302167
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/irqlinks.asl | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl
index b7a78f0..3c74257 100644
--- a/src/soc/intel/skylake/acpi/irqlinks.asl
+++ b/src/soc/intel/skylake/acpi/irqlinks.asl
@@ -19,9 +19,19 @@
  * Foundation, Inc.
  */
 
-/* PIRQ routing control is in PCR ITSS region */
+/*
+ * PIRQ routing control is in PCR ITSS region.
+ *
+ * Due to what appears to be an ACPI interpreter bug we do not use
+ * the PCRB() method here as it may not be defined yet because the method
+ * definiton depends on the order of the include files in pch.asl.
+ *
+ * https://bugs.acpica.org/show_bug.cgi?id=1201
+ */
 OperationRegion (ITSS, SystemMemory,
-		 Add (PCRB (PID_ITSS), R_PCH_PCR_ITSS_PIRQA_ROUT), 8)
+		 Add (R_PCH_PCR_ITSS_PIRQA_ROUT,
+		      Add (PCH_PCR_BASE_ADDRESS,
+		           ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8)
 Field (ITSS, ByteAcc, NoLock, Preserve)
 {
 	PIRA, 8,	/* PIRQA Routing Control */


From gerrit at coreboot.org  Fri Sep 25 14:39:07 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Fri, 25 Sep 2015 14:39:07 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: arm64: mmu:
	Prevent CPU prefetch instructions from device memory
References: <I52ac7d7c84220624aaf6a48d64b9110d7afeb293+0@gerrit.coreboot.org>
Message-ID: <I52ac7d7c84220624aaf6a48d64b9110d7afeb293+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11722

-gerrit

commit 5d78f70ff7bbe0b8886b2410f72b051683093a60
Author: Jimmy Huang <jimmy.huang at mediatek.com>
Date:   Tue Sep 15 15:29:10 2015 +0800

    arm64: mmu: Prevent CPU prefetch instructions from device memory
    
    Set XN bit of block upper attribute to device memory in mmu. CPU may
    speculatively prefetch instructions from device memory, but the IO
    subsystem of some implementation may not support this operation. Set
    this attribute to device memory mmu entries can prevent CPU from
    prefetching device memory.
    
    BRANCH=none
    BUG=none
    TEST=build and booted to kernel on oak-rev3 with dcm enabled.
    
    Change-Id: I52ac7d7c84220624aaf6a48d64b9110d7afeb293
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7b01a4157cb046a5e75ea7625060a602e7a63c3c
    Original-Change-Id: Id535e990a23b6c89123b5a4e64d7ed21eebed607
    Original-Signed-off-by: Jimmy Huang <jimmy.huang at mediatek.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302301
    Original-Commit-Ready: Yidi Lin <yidi.lin at mediatek.com>
    Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 payloads/libpayload/arch/arm64/mmu.c         | 1 +
 payloads/libpayload/include/arm64/arch/mmu.h | 2 ++
 src/arch/arm64/armv8/mmu.c                   | 1 +
 src/arch/arm64/include/armv8/arch/mmu.h      | 2 ++
 4 files changed, 6 insertions(+)

diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c
index e2a0cb1..f07e4c4 100644
--- a/payloads/libpayload/arch/arm64/mmu.c
+++ b/payloads/libpayload/arch/arm64/mmu.c
@@ -91,6 +91,7 @@ static uint64_t get_block_attr(unsigned long tag)
 		break;
 	case TYPE_DEV_MEM:
 		attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
+		attr |= BLOCK_XN;
 		break;
 	case TYPE_DMA_MEM:
 		attr |= BLOCK_INDEX_MEM_NORMAL_NC << BLOCK_INDEX_SHIFT;
diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h
index 30a1973..2f87d09 100644
--- a/payloads/libpayload/include/arm64/arch/mmu.h
+++ b/payloads/libpayload/include/arm64/arch/mmu.h
@@ -72,6 +72,8 @@ extern char _start[], _end[];
 
 #define BLOCK_ACCESS               (1 << 10)
 
+#define BLOCK_XN                   (1UL << 54)
+
 #define BLOCK_SH_SHIFT                 (8)
 #define BLOCK_SH_NON_SHAREABLE         (0 << BLOCK_SH_SHIFT)
 #define BLOCK_SH_UNPREDICTABLE         (1 << BLOCK_SH_SHIFT)
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index a3e8d77..5c95e96 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -76,6 +76,7 @@ static uint64_t get_block_attr(unsigned long tag)
 			attr |= BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT;
 	} else {
 		attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
+		attr |= BLOCK_XN;
 	}
 
 	return attr;
diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h
index f5111ae..f697ddb 100644
--- a/src/arch/arm64/include/armv8/arch/mmu.h
+++ b/src/arch/arm64/include/armv8/arch/mmu.h
@@ -56,6 +56,8 @@
 
 #define BLOCK_ACCESS               (1 << 10)
 
+#define BLOCK_XN                   (1UL << 54)
+
 #define BLOCK_SH_SHIFT                 (8)
 #define BLOCK_SH_NON_SHAREABLE         (0 << BLOCK_SH_SHIFT)
 #define BLOCK_SH_UNPREDICTABLE         (1 << BLOCK_SH_SHIFT)


From gerrit at coreboot.org  Sat Sep 26 10:24:48 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Sat, 26 Sep 2015 10:24:48 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: util/kconfig:
	Set parameter of mkdir to only one for mingw.
References: <I88e317f075e8a39f0a280b3dd6e597d119f0f741+0@gerrit.coreboot.org>
Message-ID: <I88e317f075e8a39f0a280b3dd6e597d119f0f741+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11723

-gerrit

commit 95bbe14cc6f48aadbaa5da4ebd372584effeb807
Author: zbao <fishbaozi at gmail.com>
Date:   Sat Sep 26 06:20:53 2015 -0400

    util/kconfig: Set parameter of mkdir to only one for mingw.
    
    Change-Id: I88e317f075e8a39f0a280b3dd6e597d119f0f741
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/kconfig/confdata.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c
index 5804b29..02e3ac3 100644
--- a/util/kconfig/confdata.c
+++ b/util/kconfig/confdata.c
@@ -27,6 +27,10 @@ static int conf_lineno, conf_warnings, conf_unsaved;
 
 const char conf_defname[] = "arch/$ARCH/defconfig";
 
+#ifdef __MINGW32__
+#define mkdir(_n,_p) mkdir((_n))
+#endif
+
 static void conf_warning(const char *fmt, ...)
 {
 	va_list ap;


From gerrit at coreboot.org  Sat Sep 26 10:24:51 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Sat, 26 Sep 2015 10:24:51 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: util/kconfig:
	Remove utsname for mingw
References: <I640ea61ff24fba812e3f10771dd7e468dcfc63dd+0@gerrit.coreboot.org>
Message-ID: <I640ea61ff24fba812e3f10771dd7e468dcfc63dd+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11724

-gerrit

commit 0a0d0a154090c8c1acb19593085cdc43a85d499d
Author: zbao <fishbaozi at gmail.com>
Date:   Sat Sep 26 06:22:11 2015 -0400

    util/kconfig: Remove utsname for mingw
    
    Change-Id: I640ea61ff24fba812e3f10771dd7e468dcfc63dd
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/kconfig/symbol.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/util/kconfig/symbol.c b/util/kconfig/symbol.c
index 7caabdb..29ba0a9 100644
--- a/util/kconfig/symbol.c
+++ b/util/kconfig/symbol.c
@@ -7,7 +7,9 @@
 #include <stdlib.h>
 #include <string.h>
 #include <regex.h>
+#ifndef __MINGW32__
 #include <sys/utsname.h>
+#endif
 
 #include "lkc.h"
 
@@ -45,19 +47,27 @@ static void sym_add_default(struct symbol *sym, const char *def)
 void sym_init(void)
 {
 	struct symbol *sym;
+#ifndef __MINGW32__
 	struct utsname uts;
+#endif
 	static bool inited = false;
 
 	if (inited)
 		return;
 	inited = true;
 
+#ifndef __MINGW32__
 	uname(&uts);
+#endif
 
 	sym = sym_lookup("UNAME_RELEASE", 0);
 	sym->type = S_STRING;
 	sym->flags |= SYMBOL_AUTO;
+#ifndef __MINGW32__
 	sym_add_default(sym, uts.release);
+#else
+	sym_add_default(sym, "mingw-unknow");
+#endif
 }
 
 enum symbol_type sym_get_type(struct symbol *sym)


From gerrit at coreboot.org  Sat Sep 26 10:24:55 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Sat, 26 Sep 2015 10:24:55 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kconfig: Some
	terms or curses libraries treat backspace as 0x08
References: <I8e4ea493afa88019fd299651af1df2fb992ab97b+0@gerrit.coreboot.org>
Message-ID: <I8e4ea493afa88019fd299651af1df2fb992ab97b+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11725

-gerrit

commit 719e295d8fdde1f93c31ad13b3e5f3bf031a4766
Author: zbao <fishbaozi at gmail.com>
Date:   Sat Sep 26 06:24:09 2015 -0400

    kconfig: Some terms or curses libraries treat backspace as 0x08
    
    Change-Id: I8e4ea493afa88019fd299651af1df2fb992ab97b
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/kconfig/lxdialog/inputbox.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/kconfig/lxdialog/inputbox.c b/util/kconfig/lxdialog/inputbox.c
index d58de1d..2ec124e 100644
--- a/util/kconfig/lxdialog/inputbox.c
+++ b/util/kconfig/lxdialog/inputbox.c
@@ -127,6 +127,7 @@ do_resize:
 				break;
 			case KEY_BACKSPACE:
 			case 127:
+			case '\b':
 				if (pos) {
 					wattrset(dialog, dlg.inputbox.atr);
 					if (input_x == 0) {


From gerrit at coreboot.org  Sat Sep 26 10:34:15 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Sat, 26 Sep 2015 10:34:15 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	libpayload/configs: Add default configuration with TinyCurses
	enabled
References: <Ib057e2b5f15b8d5bcdf45666f8761614317d25ee+0@gerrit.coreboot.org>
Message-ID: <Ib057e2b5f15b8d5bcdf45666f8761614317d25ee+1@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11726

-gerrit

commit 6fc4d02c7ff6f21ec87f8b623ca810a476ceb9e0
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Sat Sep 26 12:27:41 2015 +0200

    libpayload/configs: Add default configuration with TinyCurses enabled
    
    Change-Id: Ib057e2b5f15b8d5bcdf45666f8761614317d25ee
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 payloads/libpayload/configs/defconfig-tinycurses | 80 ++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/payloads/libpayload/configs/defconfig-tinycurses b/payloads/libpayload/configs/defconfig-tinycurses
new file mode 100644
index 0000000..f876903
--- /dev/null
+++ b/payloads/libpayload/configs/defconfig-tinycurses
@@ -0,0 +1,80 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Libpayload Configuration
+#
+
+#
+# Generic Options
+#
+# CONFIG_LP_GPL is not set
+# CONFIG_LP_EXPERIMENTAL is not set
+# CONFIG_LP_DEVELOPER is not set
+CONFIG_LP_COMPILER_GCC=y
+# CONFIG_LP_COMPILER_LLVM_CLANG is not set
+# CONFIG_LP_CHROMEOS is not set
+
+#
+# Architecture Options
+#
+# CONFIG_LP_ARCH_ARM is not set
+CONFIG_LP_ARCH_X86=y
+# CONFIG_LP_ARCH_ARM64 is not set
+# CONFIG_LP_ARCH_MIPS is not set
+# CONFIG_LP_MEMMAP_RAM_ONLY is not set
+CONFIG_LP_MULTIBOOT=y
+
+#
+# Standard Libraries
+#
+CONFIG_LP_LIBC=y
+CONFIG_LP_CURSES=y
+CONFIG_LP_TINYCURSES=y
+# CONFIG_LP_PDCURSES is not set
+CONFIG_LP_CBFS=y
+CONFIG_LP_LZMA=y
+CONFIG_LP_LZ4=y
+
+#
+# Console Options
+#
+# CONFIG_LP_SKIP_CONSOLE_INIT is not set
+CONFIG_LP_CBMEM_CONSOLE=y
+CONFIG_LP_SERIAL_CONSOLE=y
+CONFIG_LP_8250_SERIAL_CONSOLE=y
+# CONFIG_LP_S5P_SERIAL_CONSOLE is not set
+# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set
+# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set
+# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set
+# CONFIG_LP_PL011_SERIAL_CONSOLE is not set
+CONFIG_LP_SERIAL_IOBASE=0x3f8
+# CONFIG_LP_SERIAL_SET_SPEED is not set
+# CONFIG_LP_SERIAL_ACS_FALLBACK is not set
+CONFIG_LP_VIDEO_CONSOLE=y
+CONFIG_LP_VGA_VIDEO_CONSOLE=y
+# CONFIG_LP_GEODELX_VIDEO_CONSOLE is not set
+# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set
+CONFIG_LP_PC_KEYBOARD=y
+CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y
+# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set
+
+#
+# Drivers
+#
+CONFIG_LP_PCI=y
+CONFIG_LP_NVRAM=y
+# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set
+CONFIG_LP_SPEAKER=y
+CONFIG_LP_STORAGE=y
+# CONFIG_LP_STORAGE_64BIT_LBA is not set
+CONFIG_LP_STORAGE_ATA=y
+CONFIG_LP_STORAGE_ATAPI=y
+CONFIG_LP_STORAGE_AHCI=y
+CONFIG_LP_STORAGE_AHCI_ONLY_TESTED=y
+CONFIG_LP_TIMER_RDTSC=y
+# CONFIG_LP_USB is not set
+# CONFIG_LP_USB_GEN_HUB is not set
+# CONFIG_LP_UDC is not set
+# CONFIG_LP_BIG_ENDIAN is not set
+CONFIG_LP_LITTLE_ENDIAN=y
+CONFIG_LP_IO_ADDRESS_SPACE=y
+CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y


From gerrit at coreboot.org  Sat Sep 26 10:34:16 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Sat, 26 Sep 2015 10:34:16 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	libpayload/Kconfig: Use official spelling for TinyCurses
References: <I7e0aa5af54140796a981c0f4c58950b25fdd67ba+0@gerrit.coreboot.org>
Message-ID: <I7e0aa5af54140796a981c0f4c58950b25fdd67ba+1@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11727

-gerrit

commit 6b1bd82b7055c17b5ccfcae8fbf44a0ba15ce70a
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Sat Sep 26 12:30:08 2015 +0200

    libpayload/Kconfig: Use official spelling for TinyCurses
    
    TinyCursess is officially spelled in CamelCase [1].
    
    [1] https://github.com/tommyettinger/TinyCurses
    
    Change-Id: I7e0aa5af54140796a981c0f4c58950b25fdd67ba
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 payloads/libpayload/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index 64289b3..024fa15 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -143,9 +143,9 @@ choice
 	depends on CURSES
 
 config TINYCURSES
-	bool "Tinycurses"
+	bool "TinyCurses"
 	help
-	  Tinycurses was the first curses implementation for libpayload.
+	  TinyCurses was the first curses implementation for libpayload.
 	  It features low memory consumption, static allocation of larger
 	  data structures (so few or no memory allocation calls) and a
 	  reduced feature set.


From gerrit at coreboot.org  Sat Sep 26 10:50:13 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Sat, 26 Sep 2015 10:50:13 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: util/kconfig:
	fill glob_t with 0 before calling glob
References: <I03110c4cdda70578828d6499262a085a81d26313+0@gerrit.coreboot.org>
Message-ID: <I03110c4cdda70578828d6499262a085a81d26313+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11711

-gerrit

commit 13a2325d800b1a0aeacf96ac730bdef97a4c62ab
Author: zbao <fishbaozi at gmail.com>
Date:   Sat Sep 26 06:49:47 2015 -0400

    util/kconfig: fill glob_t with 0 before calling glob
    
    On mingw, the function glob has some default options
    which are not compliant with man page.
    
    If gl_offs is not set as 0, there may be some slots which
    is reserved.
    If gl_pathc or gl_pathv is not set as 0, the result might
    be appended to the list instead of being added as new ones.
    
    Change-Id: I03110c4cdda70578828d6499262a085a81d26313
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/kconfig/zconf.l             | 3 +++
 util/kconfig/zconf.lex.c_shipped | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/util/kconfig/zconf.l b/util/kconfig/zconf.l
index b6bed02..54c48ff 100644
--- a/util/kconfig/zconf.l
+++ b/util/kconfig/zconf.l
@@ -343,6 +343,9 @@ void zconf_nextfiles(const char *wildcard)
 	char **w;
 	int i;
 
+	g.gl_pathc = 0;
+	g.gl_pathv = NULL;
+	g.gl_offs = 0;
 	if (glob(wildcard, 0, NULL, &g) != 0) {
 		return;
 	}
diff --git a/util/kconfig/zconf.lex.c_shipped b/util/kconfig/zconf.lex.c_shipped
index cf05b19..99a437b 100644
--- a/util/kconfig/zconf.lex.c_shipped
+++ b/util/kconfig/zconf.lex.c_shipped
@@ -2421,6 +2421,9 @@ void zconf_nextfiles(const char *wildcard)
 	char **w;
 	int i;
 
+	g.gl_pathc = 0;
+	g.gl_pathv = NULL;
+	g.gl_offs = 0;
 	if (glob(wildcard, 0, NULL, &g) != 0) {
 		return;
 	}


From gerrit at coreboot.org  Sat Sep 26 11:16:12 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Sat, 26 Sep 2015 11:16:12 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: [NOTFORMERGE]
	src/Kconfig: Enable code coverage by default
References: <I3f1860004ccdaa429cfa0b531764e7e9027f0044+0@gerrit.coreboot.org>
Message-ID: <I3f1860004ccdaa429cfa0b531764e7e9027f0044+1@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11728

-gerrit

commit 4a2c5c1c8182d77f79501fc41833efc8b87ebfff
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Sat Sep 26 13:15:15 2015 +0200

    [NOTFORMERGE] src/Kconfig: Enable code coverage by default
    
    Change-Id: I3f1860004ccdaa429cfa0b531764e7e9027f0044
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Kconfig b/src/Kconfig
index 2c75750..fa74050 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1028,7 +1028,7 @@ config TRACE
 
 config DEBUG_COVERAGE
 	bool "Debug code coverage"
-	default n
+	default y
 	depends on COVERAGE
 	help
 	  If enabled, the code coverage hooks in coreboot will output some


From gerrit at coreboot.org  Sun Sep 27 11:45:47 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Sun, 27 Sep 2015 11:45:47 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: program.ld:
	terminate ALIGN statement
References: <I5128ae0ef0d4f71e3ede7bcb3ee7ed7e265d1bb7+0@gerrit.coreboot.org>
Message-ID: <I5128ae0ef0d4f71e3ede7bcb3ee7ed7e265d1bb7+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11729

-gerrit

commit d3760c573f38da7d01b6b5545197465c36d28f68
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sun Sep 27 13:45:17 2015 +0200

    program.ld: terminate ALIGN statement
    
    This fixes building with CONFIG_COVERAGE=y
    
    Change-Id: I5128ae0ef0d4f71e3ede7bcb3ee7ed7e265d1bb7
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/lib/program.ld | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib/program.ld b/src/lib/program.ld
index ab36239..4c24231 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -69,7 +69,7 @@
 
 #if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
 .ctors . : {
-	. = ALIGN(0x100)
+	. = ALIGN(0x100);
 	__CTOR_LIST__ = .;
 	KEEP(*(.ctors));
 	LONG(0);


From gerrit at coreboot.org  Sun Sep 27 11:56:29 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Sun, 27 Sep 2015 11:56:29 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: [NOTFORMERGE]
	src/Kconfig: Enable code coverage by default
References: <I3f1860004ccdaa429cfa0b531764e7e9027f0044+0@gerrit.coreboot.org>
Message-ID: <I3f1860004ccdaa429cfa0b531764e7e9027f0044+2@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11728

-gerrit

commit 437fc2efcc2f692002d9de8fcdf42efd140fde68
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Sat Sep 26 13:15:15 2015 +0200

    [NOTFORMERGE] src/Kconfig: Enable code coverage by default
    
    Change-Id: I3f1860004ccdaa429cfa0b531764e7e9027f0044
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 2c75750..74a032e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -210,7 +210,7 @@ config USE_BLOBS
 config COVERAGE
 	bool "Code coverage support"
 	depends on COMPILER_GCC
-	default n
+	default y
 	help
 	  Add code coverage support for coreboot. This will store code
 	  coverage information in CBMEM for extraction from user space.
@@ -1028,7 +1028,7 @@ config TRACE
 
 config DEBUG_COVERAGE
 	bool "Debug code coverage"
-	default n
+	default y
 	depends on COVERAGE
 	help
 	  If enabled, the code coverage hooks in coreboot will output some


From gerrit at coreboot.org  Sun Sep 27 13:50:39 2015
From: gerrit at coreboot.org (Maxime de Roucy (maxime.deroucy@gmail.com))
Date: Sun, 27 Sep 2015 13:50:39 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: add cmos/nvram
	support for pcengines apu1
References: <I4864923166efb200882d895c572d1ee060c71951+0@gerrit.coreboot.org>
Message-ID: <I4864923166efb200882d895c572d1ee060c71951+1@gerrit.coreboot.org>

Maxime de Roucy (maxime.deroucy at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730

-gerrit

commit ebe678d866fd38021c051dc634b1bb47d12d3604
Author: Maxime de Roucy <maxime.deroucy at gmail.com>
Date:   Sun Sep 27 15:45:35 2015 +0200

    add cmos/nvram support for pcengines apu1
    
    Inspired by the Sage code provided here :
    http://www.pcengines.ch/howto.php#CoreBoot
    
    Change-Id: I4864923166efb200882d895c572d1ee060c71951
    Signed-off-by: Maxime de Roucy <maxime.deroucy at gmail.com>
---
 src/mainboard/pcengines/apu1/Kconfig      |  2 +
 src/mainboard/pcengines/apu1/cmos.default | 16 +++++++
 src/mainboard/pcengines/apu1/cmos.layout  | 79 +++++++++++++++++++++++++++++++
 3 files changed, 97 insertions(+)

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index b1b19c9..7ea1821 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 	select BOARD_ROMSIZE_KB_2048
 	select SPD_CACHE
 
diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default
new file mode 100644
index 0000000..8022b63
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.default
@@ -0,0 +1,16 @@
+boot_option=Fallback
+last_boot=Fallback
+ECC_memory=Disable
+baud_rate=115200
+hw_scrubber=Disable
+interleave_chip_selects=Disable
+max_mem_clock=DDR3-1066
+multi_core=Enable
+power_on_after_fail=Disable
+debug_level=Emerg
+boot_first=Network
+boot_second=Network
+boot_third=Network
+slow_cpu=off
+nmi=Disable
+iommu=Disable
diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
new file mode 100644
index 0000000..2f8d26b
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.layout
@@ -0,0 +1,79 @@
+entries
+
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     0     Emerg
+6     1     Alert
+6     2     Crit
+6     3     Err
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+8     0     DDR3-1600
+8     1     DDR3-1333
+8     2     DDR3-1066
+8     3     DDR3-800
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+


From gerrit at coreboot.org  Sun Sep 27 13:57:17 2015
From: gerrit at coreboot.org (Maxime de Roucy (maxime.deroucy@gmail.com))
Date: Sun, 27 Sep 2015 13:57:17 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: coreinfo :
	reboot when done
References: <I00b1f859f76e693e8d49a38c1e02f4f49add85b7+0@gerrit.coreboot.org>
Message-ID: <I00b1f859f76e693e8d49a38c1e02f4f49add85b7+1@gerrit.coreboot.org>

Maxime de Roucy (maxime.deroucy at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11731

-gerrit

commit 032859460d6951637a5edb930537adf89464d10f
Author: Maxime de Roucy <maxime.deroucy at gmail.com>
Date:   Sun Sep 27 15:53:40 2015 +0200

    coreinfo : reboot when done
    
    Whithout this I got a "General Protection Fault Exception" when I leave
    coreinfo.
    http://www.coreboot.org/pipermail/coreboot/2015-September/080336.html
    
    Change-Id: I00b1f859f76e693e8d49a38c1e02f4f49add85b7
    Signed-off-by: Maxime de Roucy <maxime.deroucy at gmail.com>
---
 payloads/coreinfo/coreinfo.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c
index 5bd1068..df52056 100644
--- a/payloads/coreinfo/coreinfo.c
+++ b/payloads/coreinfo/coreinfo.c
@@ -301,6 +301,9 @@ int main(void)
 
 	loop();
 
+	/* reboot */
+	outb(0x6, 0xcf9);
+	halt();
 	return 0;
 }
 


From gerrit at coreboot.org  Sun Sep 27 18:39:01 2015
From: gerrit at coreboot.org (Maxime de Roucy (maxime.deroucy@gmail.com))
Date: Sun, 27 Sep 2015 18:39:01 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: pcengines/apu1:
	Add CMOS/NVRAM support
References: <I4864923166efb200882d895c572d1ee060c71951+0@gerrit.coreboot.org>
Message-ID: <I4864923166efb200882d895c572d1ee060c71951+2@gerrit.coreboot.org>

Maxime de Roucy (maxime.deroucy at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730

-gerrit

commit 989192df637b107c2f9e0e40fcf159acdaaad272
Author: Maxime de Roucy <maxime.deroucy at gmail.com>
Date:   Sun Sep 27 15:45:35 2015 +0200

    pcengines/apu1: Add CMOS/NVRAM support
    
    Inspired by the Sage code provided here :
    http://www.pcengines.ch/howto.php#CoreBoot
    
    Change-Id: I4864923166efb200882d895c572d1ee060c71951
    Signed-off-by: Maxime de Roucy <maxime.deroucy at gmail.com>
---
 src/mainboard/pcengines/apu1/Kconfig      |  2 +
 src/mainboard/pcengines/apu1/cmos.default | 16 +++++++
 src/mainboard/pcengines/apu1/cmos.layout  | 77 +++++++++++++++++++++++++++++++
 3 files changed, 95 insertions(+)

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index b1b19c9..7ea1821 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 	select BOARD_ROMSIZE_KB_2048
 	select SPD_CACHE
 
diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default
new file mode 100644
index 0000000..8022b63
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.default
@@ -0,0 +1,16 @@
+boot_option=Fallback
+last_boot=Fallback
+ECC_memory=Disable
+baud_rate=115200
+hw_scrubber=Disable
+interleave_chip_selects=Disable
+max_mem_clock=DDR3-1066
+multi_core=Enable
+power_on_after_fail=Disable
+debug_level=Emerg
+boot_first=Network
+boot_second=Network
+boot_third=Network
+slow_cpu=off
+nmi=Disable
+iommu=Disable
diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
new file mode 100644
index 0000000..885bc63
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.layout
@@ -0,0 +1,77 @@
+entries
+
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     0     Emerg
+6     1     Alert
+6     2     Crit
+6     3     Err
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+8     0     DDR3-1600
+8     1     DDR3-1333
+8     2     DDR3-1066
+8     3     DDR3-800
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984


From gerrit at coreboot.org  Mon Sep 28 04:32:55 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Mon, 28 Sep 2015 04:32:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+5@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit e51b062f2f02b33622abaecfae931a22a8deb762
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/arch/x86/Makefile.inc             | 2 +-
 src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
 # the right order. Make sure the auto generated romstage.inc is a proper
 # dependency.
 romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
 
 ifneq ($(CONFIG_ROMCC),y)
 
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Mon Sep 28 04:42:57 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Mon, 28 Sep 2015 04:42:57 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+6@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 4880774a4320d4cec21b536f37f2bd6349a51a08
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..a1ce02b 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
+cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)
@@ -45,3 +46,7 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Mon Sep 28 04:44:41 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Mon, 28 Sep 2015 04:44:41 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+7@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 162fb1e3e5ff356b576114540d8730cacb2fe50d
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..a1ce02b 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
+cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)
@@ -45,3 +46,7 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Mon Sep 28 04:59:03 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Mon, 28 Sep 2015 04:59:03 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+8@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 66049bcb2ba5b65f59d93fa6d00b0792249af15c
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/drivers/intel/fsp1_0/Makefile.inc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..7e970c1 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
+cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)
@@ -45,3 +46,8 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
+	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Mon Sep 28 05:25:14 2015
From: gerrit at coreboot.org (Werner Zeh (werner.zeh@siemens.com))
Date: Mon, 28 Sep 2015 05:25:14 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+9@gerrit.coreboot.org>

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 8cdec5d8c30aaa0cd3450f4aa8c6e1a5b6d4a0d1
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/drivers/intel/fsp1_0/Makefile.inc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..7e970c1 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
+cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)
@@ -45,3 +46,8 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
+	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+


From gerrit at coreboot.org  Mon Sep 28 09:32:54 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:32:54 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: ec: superio:
	Report keyboard IRQ as wake capable
References: <I7175d2ea98f8a671765897de295df7b933151fc4+0@gerrit.coreboot.org>
Message-ID: <E1ZgUnm-0002nq-6Y@mail.coreboot.org>

the following patch was just integrated into master:
commit f611fcfacac5be14a51e04ae4d0b1e25cd5439c0
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Sep 21 15:00:20 2015 -0700

    ec: superio: Report keyboard IRQ as wake capable
    
    In order to wake from S0ix the kernel needs to know that the
    keyboard interrupt is wake capable.  Using IRQNoFlags does not
    allow the wake capability to be reported.
    
    For normal S3 this does not matter as the EC is the one handling
    the keyboard wake event.  For S0ix the EC does not need to be
    involved in this particular wake event.
    
    BUG=chrome-os-partner:43079
    BRANCH=none
    TEST=echo freeze > /sys/power/state and wake from keyboard
    
    Change-Id: I7175d2ea98f8a671765897de295df7b933151fc4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 645f1cd96c35f42aa7c40ff473b15feb619b0373
    Original-Change-Id: Ia89c30c51be9db7b814b81261463d938885325fd
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/301441
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11712
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11712 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:33:26 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:33:26 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfs: fix
	debug message
References: <I0b555d018f8c2eb1b51519a6227298c8d5d58a42+0@gerrit.coreboot.org>
Message-ID: <E1ZgUoI-0002rp-Jr@mail.coreboot.org>

the following patch was just integrated into master:
commit 9dcf4577075a7dea44fbfcefaa7555ac5ba5beb1
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Wed Sep 23 13:01:14 2015 -0700

    cbfs: fix debug message
    
    BUG=none
    BRANCH=tot
    TEST=built for Samus with debugging enabled
    
    Change-Id: I0b555d018f8c2eb1b51519a6227298c8d5d58a42
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5908e4b8ffc66e6ecc7cae78cf10055fbd727c81
    Original-Change-Id: Ifd049111fee540789dabb1d7653568b80405b77d
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302131
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11713
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11713 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:33:43 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:33:43 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfs: allow
	cbfs-files to use compression
References: <I29ba0c6f8290b500072a0b17460ee590d6bb6efa+0@gerrit.coreboot.org>
Message-ID: <E1ZgUoZ-0002u6-Rn@mail.coreboot.org>

the following patch was just integrated into master:
commit bf84cf93cc67721adb3ee85165fe4aac29e1c556
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date:   Tue Sep 22 15:21:36 2015 -0700

    cbfs: allow cbfs-files to use compression
    
    This change allows files added to cbfs-files-y to specify compression
    algorithm.
    
    BUG=none
    BRANCH=tot
    TEST=Tested on Samus
    
    Change-Id: I29ba0c6f8290b500072a0b17460ee590d6bb6efa
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4284160bdbbc54ed1da8b5477b02ee315061206b
    Original-Change-Id: Idf81e1cc0a1030449da632f6d89cdc87c624f9f3
    Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302132
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11714
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11714 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:34:01 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:34:01 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: tpm: acpi:
	Make _CRS method serialized
References: <I59a52552ab24b7d9c9928331aa8c8d19f54fd1b7+0@gerrit.coreboot.org>
Message-ID: <E1ZgUor-0002wO-HS@mail.coreboot.org>

the following patch was just integrated into master:
commit 16ea5191207cb14d5fce3e763f18e046701d215b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 22 09:39:23 2015 -0700

    tpm: acpi: Make _CRS method serialized
    
    Since the TPM _CRS method creates named objects it needs
    to be serialized to prevent a warning in recent iasl.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build glados with iasl-20150717
    
    Change-Id: I59a52552ab24b7d9c9928331aa8c8d19f54fd1b7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 2a5c474c94980661573a99eb94d5f661f2d0114b
    Original-Change-Id: Ie9d164ea8781304dd0bf1833d182d7c601b8e18d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302162
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11715
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11715 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:34:18 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:34:18 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: chromeec: Fix
	ACPI compile warnings
References: <I1d4535205426dd9a6346f53ff159221cf5cd899a+0@gerrit.coreboot.org>
Message-ID: <E1ZgUp8-0002zI-8Y@mail.coreboot.org>

the following patch was just integrated into master:
commit 20373c03a84f92d9c19d780a84a9bc380015c3de
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 22 09:40:37 2015 -0700

    chromeec: Fix ACPI compile warnings
    
    Recent version of iasl are flagging more things as warnings.
    Remove unused Local0 uses and make _CRS method serialized to
    fix these warnings.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build glados with iasl-20150717
    
    Change-Id: I1d4535205426dd9a6346f53ff159221cf5cd899a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8b43f8f24bb7cb33ad0411c24616da66663c2e3e
    Original-Change-Id: I71eafd91d30d5f50e6211368f0bbc517c8085892
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302163
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11716
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11716 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:34:31 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:34:31 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados: Fix
	typo for WLAN ACPI device name
References: <I8d61a6653c3109890d04e54f0d694703b9c9f2bf+0@gerrit.coreboot.org>
Message-ID: <E1ZgUpL-00031a-Kp@mail.coreboot.org>

the following patch was just integrated into master:
commit 41f0a30ea3553ed88bfe1e41a7c1a786aa024847
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 22 09:41:37 2015 -0700

    glados: Fix typo for WLAN ACPI device name
    
    Fix the typo of _DDR to be _DDN.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build glados with iasl-20150717
    
    Change-Id: I8d61a6653c3109890d04e54f0d694703b9c9f2bf
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d4a2b2583bdbf9afd7b306359338d4c49bbb44ad
    Original-Change-Id: I7b7905a217d34a8a78b8280c898f1074ecbe3cf6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302164
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11717
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11717 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:34:45 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:34:45 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kunimitsu: Fix
	typo for WLAN ACPI device name
References: <I1e7c20d450ea897bfd24506d10a5f466b03610e4+0@gerrit.coreboot.org>
Message-ID: <E1ZgUpZ-00034w-Sp@mail.coreboot.org>

the following patch was just integrated into master:
commit 36ad827b68f4f0659339742e0c1ac0bb5fcee753
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Sep 22 09:41:50 2015 -0700

    kunimitsu: Fix typo for WLAN ACPI device name
    
    Fix the typo of _DDR to be _DDN.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build kunimitsu with iasl-20150717
    
    Change-Id: I1e7c20d450ea897bfd24506d10a5f466b03610e4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f136581b653bfb63aac24065c8837307e3fc5432
    Original-Change-Id: I3358e6d3d05bcfc291199e8ef12ff92c66f5b74f
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302165
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11718
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11718 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:34:57 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:34:57 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI:
	Remove Configurable TDP support code
References: <I81e356ddf564a5253458b82bc3327bfb573ab16d+0@gerrit.coreboot.org>
Message-ID: <E1ZgUpl-00036o-Di@mail.coreboot.org>

the following patch was just integrated into master:
commit 4a399c2bae3695708a931146a4aab92b56491561
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Sep 23 17:53:31 2015 -0700

    skylake: ACPI: Remove Configurable TDP support code
    
    Remove the CTDP support code that is in ACPI.  It has been ported
    from haswell and while the MCHBAR register interface does seem to
    still exist the calculations for determining PL2 is no longer
    straightforward.
    
    Additionally nothing is using this interface and the expectation
    is that DPTF will be used for throttling with PL[1234] and having
    ACPI interfere with the configuration would not be good.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I81e356ddf564a5253458b82bc3327bfb573ab16d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 884ee9a764bad0b3b4bcaeb5a3f46c5f090a116c
    Original-Change-Id: I284ab52a305cee25c88df5228b01ff1e9544efe3
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302166
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11719
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11719 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:35:19 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:35:19 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: glados:
	Provide nau8825 platform data via _DSD
References: <I813a985b4a39249a2cdbe45117acbdb7710bfa29+0@gerrit.coreboot.org>
Message-ID: <E1ZgUq7-0003MW-PZ@mail.coreboot.org>

the following patch was just integrated into master:
commit 98a4431b99b77c20b583199b3a587cd5cd05bbd5
Author: Ben Zhang <benzh at chromium.org>
Date:   Tue Aug 4 22:02:53 2015 -0700

    glados: Provide nau8825 platform data via _DSD
    
    BUG=chrome-os-partner:41280
    BRANCH=none
    TEST=Audio jack insert/eject detection and headset buttons work
    on glados with the nau8825 driver in chromeos-3.18 and the
    staging kernel skl2.
    
    Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb
    Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80
    Original-Signed-off-by: Ben Zhang <benzh at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/293610
    Original-Reviewed-by: Anatol Pomazau <anatol at google.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11720
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11720 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:35:58 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:35:58 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake: Work
	around issue in ACPI interpreter
References: <I7b6a3b792f79755db0ea7b9f2ef6ee7f5000e018+0@gerrit.coreboot.org>
Message-ID: <E1ZgUqk-0003Q2-A7@mail.coreboot.org>

the following patch was just integrated into master:
commit bf7b5bc64a6f4cef485f2c78607835d20e7f2e5d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Sep 23 17:57:20 2015 -0700

    skylake: Work around issue in ACPI interpreter
    
    There appears to be an issue that is causing this particular bit of
    ACPI code to be incorrectly interpreted by the kernel and the IASL
    disassembler.
    
    Ensuring the PCRB() method is defined in the DSDT before any uses of
    it appears to fix the problem, but that relies on specific ordering
    of the ASL files included by pch.asl and may break again in the future
    if the includes were re-ordered.  (they are alphabetic now)
    
    So in this case to work around the issue unroll the function call so
    the admittedly messy calculation is reduced to a constant when compiled.
    
    Note this issue was observed with both iasl-20130117 and
    iasl-20150717.
    
    ACPICA bug: https://bugs.acpica.org/show_bug.cgi?id=1201
    
    BUG=chrome-os-partner:45760
    BRANCH=none
    TEST=verify disassembled AML is correct
    
    Change-Id: I7b6a3b792f79755db0ea7b9f2ef6ee7f5000e018
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: ecacc340d6e1068ea649f0859657bb3208695730
    Original-Change-Id: I232523f5b6ce290da6e7d99405a53b9437b10e0d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302167
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11721
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11721 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:36:37 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:36:37 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: arm64: mmu:
	Prevent CPU prefetch instructions from device memory
References: <I52ac7d7c84220624aaf6a48d64b9110d7afeb293+0@gerrit.coreboot.org>
Message-ID: <E1ZgUrN-0003Up-Fn@mail.coreboot.org>

the following patch was just integrated into master:
commit c159a0ec4a41a4243df60a1a94c1d4848f6492c5
Author: Jimmy Huang <jimmy.huang at mediatek.com>
Date:   Tue Sep 15 15:29:10 2015 +0800

    arm64: mmu: Prevent CPU prefetch instructions from device memory
    
    Set XN bit of block upper attribute to device memory in mmu. CPU may
    speculatively prefetch instructions from device memory, but the IO
    subsystem of some implementation may not support this operation. Set
    this attribute to device memory mmu entries can prevent CPU from
    prefetching device memory.
    
    BRANCH=none
    BUG=none
    TEST=build and booted to kernel on oak-rev3 with dcm enabled.
    
    Change-Id: I52ac7d7c84220624aaf6a48d64b9110d7afeb293
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7b01a4157cb046a5e75ea7625060a602e7a63c3c
    Original-Change-Id: Id535e990a23b6c89123b5a4e64d7ed21eebed607
    Original-Signed-off-by: Jimmy Huang <jimmy.huang at mediatek.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302301
    Original-Commit-Ready: Yidi Lin <yidi.lin at mediatek.com>
    Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: http://review.coreboot.org/11722
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11722 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 09:36:54 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 09:36:54 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: program.ld:
	terminate ALIGN statement
References: <I5128ae0ef0d4f71e3ede7bcb3ee7ed7e265d1bb7+0@gerrit.coreboot.org>
Message-ID: <E1ZgUre-0003XX-VI@mail.coreboot.org>

the following patch was just integrated into master:
commit 9cc8e92b6c2445ef7664ba20d9cf94b49fdbb972
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sun Sep 27 13:45:17 2015 +0200

    program.ld: terminate ALIGN statement
    
    This fixes building with CONFIG_COVERAGE=y
    
    Change-Id: I5128ae0ef0d4f71e3ede7bcb3ee7ed7e265d1bb7
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/11729
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11729 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 10:13:26 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 10:13:26 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool: have
	update-fit always work from CBFS
References: <Ie139215b73e01027bc0586701361e9a0afa9150e+0@gerrit.coreboot.org>
Message-ID: <E1ZgVR0-0005Ii-1i@mail.coreboot.org>

the following patch was just integrated into master:
commit 6dd99fcafe83fed2632a90821de6373516c14a0c
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Sat Sep 19 14:04:45 2015 +0200

    cbfstool: have update-fit always work from CBFS
    
    On x86, the bootblock can (and will) become part of the regular file
    system, so there's no distinct fixed-size region for the bootblock
    there.
    
    Change-Id: Ie139215b73e01027bc0586701361e9a0afa9150e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11691
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11691 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 10:13:39 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 10:13:39 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cbfstool:
	prefer fmap data over cbfs master header if it exists
References: <Iafbf2c9dc325597e23a9780b495549b5d912e9ad+0@gerrit.coreboot.org>
Message-ID: <E1ZgVRD-0005KT-OR@mail.coreboot.org>

the following patch was just integrated into master:
commit 2f953d304e02be9a2f4f6fbd86b41dd6c86ec5db
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Fri Sep 11 18:34:39 2015 +0200

    cbfstool: prefer fmap data over cbfs master header if it exists
    
    Up to now, if both fmap and a master header existed, the master header
    was used. Now, use the master header only if no fmap is found.
    
    Change-Id: Iafbf2c9dc325597e23a9780b495549b5d912e9ad
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: http://review.coreboot.org/11629
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11629 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 11:29:20 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 28 Sep 2015 11:29:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Make common
	macros double-evaluation-safe
References: <I948ac39a307a2f0703b3a5c611c6eccd1559ca1f+0@gerrit.coreboot.org>
Message-ID: <I948ac39a307a2f0703b3a5c611c6eccd1559ca1f+5@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10395

-gerrit

commit 5bc00b2cc0a71f1c94646b00cef9d3a3fbe254ee
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Mon Jun 1 10:27:02 2015 +0200

    Make common macros double-evaluation-safe
    
    In the style of I4cc368a2f996, adapt more macros.
    
    Change-Id: I948ac39a307a2f0703b3a5c611c6eccd1559ca1f
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/commonlib/include/commonlib/helpers.h | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
index 8f06093..966c6bd 100644
--- a/src/commonlib/include/commonlib/helpers.h
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -24,9 +24,19 @@
 	typeof(b) _b = b; \
 	_a > _b ? _a : _b; \
 })
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
+#define ABS(a) ({ \
+	typeof(a) _a = a; \
+	_a < 0 ? -_a : _a; \
+})
+#define CEIL_DIV(a, b) ({ \
+	typeof(a) _a = a; \
+	typeof(b) _b = b; \
+	(((_a) + (_b) - 1) / (_b)); \
+})
+#define IS_POWER_OF_2(x) ({ \
+	typeof(x) _x = x; \
+	(((_x) & ((_x) - 1)) == 0); \
+})
 
 /* Standard units. */
 #define KiB (1<<10)


From gerrit at coreboot.org  Mon Sep 28 11:29:27 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Mon, 28 Sep 2015 11:29:27 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Make common
	macros double-evaluation-safe
References: <I4cc368a2f9966139c988257afc013151cd90c7ab+0@gerrit.coreboot.org>
Message-ID: <I4cc368a2f9966139c988257afc013151cd90c7ab+5@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10393

-gerrit

commit 48be337f5db52c569d668623e19e0ca248d4c37a
Author: Julius Werner <jwerner at chromium.org>
Date:   Fri May 22 18:09:48 2015 -0700

    Make common macros double-evaluation-safe
    
    Our MIN(), MAX() and ALIGN*() macros are currently vulnerable to
    double-evaluation (e.g. x = ALIGN_UP(y, big_func_with_side_effects(y));
    doesn't do what you'd think it should). GCC (and mostly GCC-compatible
    compilers like clang) long had the statement expression and typeof()
    extensions to deal with problems like this. We should use them.
    
    BRANCH=None
    BUG=None
    TEST=None
    
    Change-Id: I4cc368a2f9966139c988257afc013151cd90c7ab
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 985abba1a9b8fa659a9f40e224f81266d7e542bb
    Original-Change-Id: I2519d552b67096c9277c5206964f83dda97c8d01
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/273009
    Original-Reviewed-by: Patrick Georgi <pgeorgi at chromium.org>
---
 payloads/libpayload/include/libpayload.h  | 12 ++++++++++--
 payloads/libpayload/include/stdlib.h      |  6 +++++-
 src/commonlib/include/commonlib/helpers.h | 18 +++++++++++++++---
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 470aafa..bb5c0db 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -61,8 +61,16 @@
 #include <sysinfo.h>
 #include <pci.h>
 
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ({ \
+	typeof(a) _a = a; \
+	typeof(b) _b = b; \
+	_a < _b ? _a : _b; \
+})
+#define MAX(a, b) ({ \
+	typeof(a) _a = a; \
+	typeof(b) _b = b; \
+	_a > _b ? _a : _b; \
+})
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
 static inline u32 div_round_up(u32 n, u32 d) { return (n + d - 1) / d; }
diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h
index 689bf01..9ab4802 100644
--- a/payloads/libpayload/include/stdlib.h
+++ b/payloads/libpayload/include/stdlib.h
@@ -35,8 +35,12 @@
 #include <stddef.h>
 #include <string.h>
 
+#define __ALIGN_MASK(x, mask)    ({ \
+	typeof(mask) _mask = mask; \
+	((x) + _mask) & ~_mask; \
+})
+
 #define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
 #define ALIGN_UP(x,a)           ALIGN((x),(a))
 #define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
 #define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
index 6ad767e..8f06093 100644
--- a/src/commonlib/include/commonlib/helpers.h
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -4,14 +4,26 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
+#define __ALIGN_MASK(x, mask)    ({ \
+	typeof(mask) _mask = mask; \
+	((x) + _mask) & ~_mask; \
+})
+
 #define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
 #define ALIGN_UP(x,a)           ALIGN((x),(a))
 #define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
 #define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
 
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ({ \
+	typeof(a) _a = a; \
+	typeof(b) _b = b; \
+	_a < _b ? _a : _b; \
+})
+#define MAX(a, b) ({ \
+	typeof(a) _a = a; \
+	typeof(b) _b = b; \
+	_a > _b ? _a : _b; \
+})
 #define ABS(a) (((a) < 0) ? (-(a)) : (a))
 #define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
 #define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)


From gerrit at coreboot.org  Mon Sep 28 17:04:24 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 28 Sep 2015 17:04:24 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: intel: auto
	include intel/common/firmare
References: <I166db67c41b16c4d9f0116abce00940514539fa5+0@gerrit.coreboot.org>
Message-ID: <I166db67c41b16c4d9f0116abce00940514539fa5+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11734

-gerrit

commit 58a76d364161dad295f40a85ebf01b499332e442
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 30 16:50:21 2015 -0500

    intel: auto include intel/common/firmare
    
    Instead of selecting the Kconfig option and adding the subdir
    entry within each chipset auto include the common/firmware
    directory as it's guarded by HAVE_INTEL_FIRMWARE.
    
    BUG=chrome-os-partner:43462
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I166db67c41b16c4d9f0116abce00940514539fa5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/baytrail/Makefile.inc             | 1 -
 src/soc/intel/braswell/Makefile.inc             | 1 -
 src/soc/intel/broadwell/Makefile.inc            | 1 -
 src/soc/intel/fsp_baytrail/Makefile.inc         | 1 -
 src/southbridge/intel/bd82x6x/Makefile.inc      | 2 --
 src/southbridge/intel/common/Makefile.inc       | 3 +++
 src/southbridge/intel/fsp_bd82x6x/Makefile.inc  | 2 --
 src/southbridge/intel/fsp_rangeley/Makefile.inc | 2 --
 src/southbridge/intel/ibexpeak/Makefile.inc     | 2 --
 src/southbridge/intel/lynxpoint/Makefile.inc    | 2 --
 10 files changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e8c5022..085a45e 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += memmap.c
 romstage-y += memmap.c
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index eda9f76..e5ac640 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../southbridge/intel/common/firmware
 
 romstage-y += gpio_support.c
 romstage-y += iosf.c
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 183c40f..fdd064d 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += acpi.c
 ramstage-y += adsp.c
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 45ea3e4..39a253f 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -30,7 +30,6 @@ subdirs-y += ../../../cpu/x86/cache
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../lib/fsp
 subdirs-y += fsp
-subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += memmap.c
 romstage-y += memmap.c
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 9214450..a1256df 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -19,8 +19,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 86823a1..36dc432 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -17,6 +17,9 @@
 ## Foundation, Inc.
 ##
 
+# CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build.
+subdirs-y += firmware
+
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
 
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
index 228b6eb..d14d303 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
@@ -20,8 +20,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc
index 1d35b54..2a66b90 100644
--- a/src/southbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc
@@ -20,8 +20,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += soc.c
 ramstage-y += lpc.c
 ramstage-y += sata.c
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 57c498d..77f2797 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -19,8 +19,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += ../bd82x6x/pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index a42fe39..7cff6b8 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -19,8 +19,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c


From gerrit at coreboot.org  Mon Sep 28 17:04:26 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 28 Sep 2015 17:04:26 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: skylake: select
	HAVE_INTEL_FIRMWARE
References: <I7196f587b92fd26129b30e2cd73f4caf5f4ebef8+0@gerrit.coreboot.org>
Message-ID: <I7196f587b92fd26129b30e2cd73f4caf5f4ebef8+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11735

-gerrit

commit 17949b16d51d025641506bf08c213a799fdc3e18
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 30 13:41:01 2015 -0500

    skylake: select HAVE_INTEL_FIRMWARE
    
    Use the common ME and descriptor code.
    
    BUG=chrome-os-partner:43462
    BRANCH=None
    TEST=Built glados
    
    Change-Id: I7196f587b92fd26129b30e2cd73f4caf5f4ebef8
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/Kconfig      | 58 +-------------------------------------
 src/soc/intel/skylake/Makefile.inc | 36 -----------------------
 2 files changed, 1 insertion(+), 93 deletions(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 1ccde4a..ae50bd2 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS
 	select GENERIC_GPIO_LIB
 	select HAS_PRECBMEM_TIMESTAMP_REGION
 	select HAVE_HARD_RESET
+	select HAVE_INTEL_FIRMWARE
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
 	select IOAPIC
@@ -85,38 +86,6 @@ config DCACHE_RAM_SIZE
 	  The size of the cache-as-ram region required during bootblock
 	  and/or romstage.
 
-config HAVE_IFD_BIN
-	bool "Use Intel Firmware Descriptor from existing binary"
-	default n
-
-config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-		   was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
-
 config HEAP_SIZE
 	hex
 	default 0x80000
@@ -125,31 +94,6 @@ config IED_REGION_SIZE
 	hex
 	default 0x400000
 
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
-
 config MMCONF_BASE_ADDRESS
 	hex "MMIO Base Address"
 	default 0xe0000000
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 38668da..d6bc839 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -67,40 +67,4 @@ CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 # Currently used for microcode path.
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE := pch_add_me
-
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += pch_add_me
-
 endif


From gerrit at coreboot.org  Mon Sep 28 19:46:38 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Mon, 28 Sep 2015 19:46:38 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel: auto
	include intel/common/firmware
References: <I166db67c41b16c4d9f0116abce00940514539fa5+0@gerrit.coreboot.org>
Message-ID: <I166db67c41b16c4d9f0116abce00940514539fa5+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11734

-gerrit

commit d6fea682c7dd7de27be11db1f7ac984204be2df9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 30 16:50:21 2015 -0500

    intel: auto include intel/common/firmware
    
    Instead of selecting the Kconfig option and adding the subdir
    entry within each chipset auto include the common/firmware
    directory as it's guarded by HAVE_INTEL_FIRMWARE.
    
    BUG=chrome-os-partner:43462
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I166db67c41b16c4d9f0116abce00940514539fa5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/baytrail/Makefile.inc             | 1 -
 src/soc/intel/braswell/Makefile.inc             | 1 -
 src/soc/intel/broadwell/Makefile.inc            | 1 -
 src/soc/intel/fsp_baytrail/Makefile.inc         | 1 -
 src/southbridge/intel/bd82x6x/Makefile.inc      | 2 --
 src/southbridge/intel/common/Makefile.inc       | 3 +++
 src/southbridge/intel/fsp_bd82x6x/Makefile.inc  | 2 --
 src/southbridge/intel/fsp_rangeley/Makefile.inc | 2 --
 src/southbridge/intel/ibexpeak/Makefile.inc     | 2 --
 src/southbridge/intel/lynxpoint/Makefile.inc    | 2 --
 10 files changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e8c5022..085a45e 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += memmap.c
 romstage-y += memmap.c
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index eda9f76..e5ac640 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../southbridge/intel/common/firmware
 
 romstage-y += gpio_support.c
 romstage-y += iosf.c
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 183c40f..fdd064d 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += acpi.c
 ramstage-y += adsp.c
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 45ea3e4..39a253f 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -30,7 +30,6 @@ subdirs-y += ../../../cpu/x86/cache
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../lib/fsp
 subdirs-y += fsp
-subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += memmap.c
 romstage-y += memmap.c
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 9214450..a1256df 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -19,8 +19,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 86823a1..36dc432 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -17,6 +17,9 @@
 ## Foundation, Inc.
 ##
 
+# CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build.
+subdirs-y += firmware
+
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
 
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
index 228b6eb..d14d303 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
@@ -20,8 +20,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc
index 1d35b54..2a66b90 100644
--- a/src/southbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc
@@ -20,8 +20,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += soc.c
 ramstage-y += lpc.c
 ramstage-y += sata.c
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 57c498d..77f2797 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -19,8 +19,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += ../bd82x6x/pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index a42fe39..7cff6b8 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -19,8 +19,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
 
-subdirs-y += ../common/firmware
-
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c


From gerrit at coreboot.org  Mon Sep 28 20:05:19 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 28 Sep 2015 20:05:19 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: .gitignore:
	adapt to new buildgcc version
References: <I6c752f08aa545d8878fddd373e5acbfade317ad5+0@gerrit.coreboot.org>
Message-ID: <E1Zgefn-00050H-2h@mail.coreboot.org>

the following patch was just integrated into master:
commit bebef2133eb842603b207c4e324f1bac7183757f
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 11 09:15:40 2015 -0400

    .gitignore: adapt to new buildgcc version
    
    1. The build folders are capitalized.
    2. Add folders for build LLVM and IASL.
    
    Change-Id: I6c752f08aa545d8878fddd373e5acbfade317ad5
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
    Reviewed-on: http://review.coreboot.org/11602
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11602 for details.

-gerrit


From gerrit at coreboot.org  Mon Sep 28 20:26:27 2015
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 28 Sep 2015 20:26:27 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: vgabios: fix
	compilation after x86emu changes
References: <If3e4399b1b0e947433b97caa29962ef66ea2993d+0@gerrit.coreboot.org>
Message-ID: <If3e4399b1b0e947433b97caa29962ef66ea2993d+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11736

-gerrit

commit aed4d716674819363f660796a3892c27529efed1
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Sep 28 13:12:04 2015 -0700

    vgabios: fix compilation after x86emu changes
    
    This utility links in coreboot code, and has been broken for a while
    again after removing some hacks from coreboot. I hadn't realized how
    bad it was broken last time, and since most of this stuff is still
    in a pretty bad shape, I decided to throw all of the changes together.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    
    Change-Id: If3e4399b1b0e947433b97caa29962ef66ea2993d
---
 util/vgabios/Makefile                  | 52 ++++++++++++------
 util/vgabios/helper_exec.c             | 22 ++++----
 util/vgabios/helper_exec.h             | 30 +++++++++++
 util/vgabios/include/console/console.h |  2 +
 util/vgabios/int10.c                   |  8 ++-
 util/vgabios/int15.c                   |  7 ++-
 util/vgabios/int16.c                   |  2 +
 util/vgabios/int1a.c                   | 11 ++--
 util/vgabios/inte6.c                   |  4 +-
 util/vgabios/pci-userspace.c           |  3 +-
 util/vgabios/pci-userspace.h           | 13 +++--
 util/vgabios/pci.h                     |  2 -
 util/vgabios/test.h                    | 89 ------------------------------
 util/vgabios/testbios.c                | 56 +++++++++----------
 util/vgabios/testbios.h                | 98 ++++++++++++++++++++++++++++++++++
 15 files changed, 230 insertions(+), 169 deletions(-)

diff --git a/util/vgabios/Makefile b/util/vgabios/Makefile
index 366606c..520779c 100644
--- a/util/vgabios/Makefile
+++ b/util/vgabios/Makefile
@@ -6,35 +6,57 @@
 # /usr/lib/...
 #
 
-CC       =  gcc
-CFLAGS   = -O2 -g -fomit-frame-pointer
+TOP     ?= ../..
+
+CC      ?=  gcc
+CFLAGS  ?= -O2 -g -fomit-frame-pointer
+
 CFLAGS  += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
-CFLAGS  += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
-CFLAGS  += -Wstrict-aliasing -Wshadow -Wextra
+CFLAGS  += -Wwrite-strings -Wredundant-decls -Wstrict-aliasing -Wshadow -Wextra
+
+# TODO check host architecture
+CBCFLAGS  = -DCONFIG_ARCH_X86=1 -Wno-sign-compare -Wno-unused-but-set-variable -Wno-unused-parameter
 
-INCLUDES = -Iinclude -I../../src/device/oprom/include/ -I../../src --include include/stdtypes.h
+INCLUDES  = -Iinclude -I$(TOP)/src/device/oprom/include/
+CBINCLUDES = -I$(TOP)/src --include include/stdtypes.h
+CBINCLUDES += --include $(TOP)/src/commonlib/include/commonlib/loglevel.h
+CBINCLUDES += -include stdio.h
 
-INTOBJS  = int10.o int15.o int16.o int1a.o inte6.o
-X86EMUOBJS  = sys.o decode.o ops.o ops2.o prim_ops.o fpu.o debug.o
-OBJS  =  testbios.o helper_exec.o helper_mem.o $(INTOBJS) $(X86EMUOBJS)
+SOURCE  = int10.c int15.c int16.c int1a.c inte6.c testbios.c
+SOURCE += helper_exec.c helper_mem.c pci-userspace.c
 
-# user space pci is the only option right now.
-OBJS += pci-userspace.o
+X86EMU  = sys.c decode.c ops.c ops2.c prim_ops.c fpu.c debug.c
+X86EMU_DIR = $(TOP)/src/device/oprom/x86emu
+X86EMU_SOURCE = $(addprefix $(X86EMU_DIR)/, $(X86EMU))
+OBJECTS:=$(SOURCE:.c=.o) $(X86EMU:.c=.o)
 
 LIBS=-lpci
 
-all: testbios
+all: dep testbios
 
-testbios: $(OBJS)
+testbios: $(OBJECTS)
+	printf "    LINK  $(notdir $@)\n"
 	$(CC) $(CFLAGS) -o $@ $^ $(LIBS)
 
-helper_exec.o: helper_exec.c test.h
+dep: $(SOURCE) $(X86EMU_SOURCE) Makefile
+	$(CC) $(CFLAGS) $(INCLUDES) -MM $(SOURCE) > .dependencies
+	$(CC) $(CFLAGS) $(INCLUDES) $(CBCFLAGS) $(CBINCLUDES) -MM $(X86EMU_SOURCE) >> .dependencies
 
 clean:
 	rm -f *.o *~ testbios
 
-%.o: ../../src/device/oprom/x86emu/%.c
-	$(CC) $(CFLAGS) $(INCLUDES) -include stdio.h -c -o $@ $^
+distclean: clean
+	rm -f .dependencies
+
+%.o: $(X86EMU_DIR)/%.c
+	printf "    CC    (x86emu) $(notdir $<)\n"
+	$(CC) $(CFLAGS) $(CBCFLAGS) $(INCLUDES) $(CBINCLUDES) -c -o $@ $<
 
 %.o: %.c
+	printf "    CC    $(notdir $<)\n"
 	$(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
+
+.PHONY: all clean distclean
+.SILENT:
+
+-include .dependencies
diff --git a/util/vgabios/helper_exec.c b/util/vgabios/helper_exec.c
index 73100d9..4d6aae5 100644
--- a/util/vgabios/helper_exec.c
+++ b/util/vgabios/helper_exec.c
@@ -14,21 +14,13 @@
  * in xf86EnableIO(). Otherwise we won't trap
  * on PIO.
  */
-#include <x86emu/x86emu.h>
-#include "helper_exec.h"
-#include "test.h"
 #include <sys/io.h>
 #include <sys/time.h>
 #include <stdio.h>
-
-
-int port_rep_inb(u16 port, u32 base, int d_f, u32 count);
-u8 x_inb(u16 port);
-u16 x_inw(u16 port);
-void x_outb(u16 port, u8 val);
-void x_outw(u16 port, u16 val);
-u32 x_inl(u16 port);
-void x_outl(u16 port, u32 val);
+#include <stdtypes.h>
+#include <x86emu/x86emu.h>
+#include "helper_exec.h"
+#include "testbios.h"
 
 /* general software interrupt handler */
 u32 getIntVect(int num)
@@ -59,6 +51,8 @@ int run_bios_int(int num)
 	return 1;
 }
 
+#if 0
+
 int port_rep_inb(u16 port, u32 base, int d_f, u32 count)
 {
 	register int inc = d_f ? -1 : 1;
@@ -125,6 +119,8 @@ int port_rep_outl(u16 port, u32 base, int d_f, u32 count)
 	return dst - base;
 }
 
+#endif
+
 u8 x_inb(u16 port)
 {
 	u8 val;
@@ -175,6 +171,7 @@ void x_outl(u16 port, u32 val)
 	outl(val, port);
 }
 
+#if 0
 u8 Mem_rb(int addr)
 {
 	return (*current->mem->rb) (current, addr);
@@ -204,6 +201,7 @@ void Mem_wl(int addr, u32 val)
 {
 	(*current->mem->wl) (current, addr, val);
 }
+#endif
 
 void getsecs(unsigned long *sec, unsigned long *usec)
 {
diff --git a/util/vgabios/helper_exec.h b/util/vgabios/helper_exec.h
index 2657b6e..7115ffb 100644
--- a/util/vgabios/helper_exec.h
+++ b/util/vgabios/helper_exec.h
@@ -1,2 +1,32 @@
+#ifndef __HELPER_EXEC_H__
+#define __HELPER_EXEC_H__
+
 u32 getIntVect(int num);
 int run_bios_int(int num);
+void pushw(u16 val);
+
+int port_rep_inb(u16 port, u32 base, int d_f, u32 count);
+int port_rep_inw(u16 port, u32 base, int d_f, u32 count);
+int port_rep_inl(u16 port, u32 base, int d_f, u32 count);
+int port_rep_outb(u16 port, u32 base, int d_f, u32 count);
+int port_rep_outw(u16 port, u32 base, int d_f, u32 count);
+int port_rep_outl(u16 port, u32 base, int d_f, u32 count);
+
+u8 x_inb(u16 port);
+u16 x_inw(u16 port);
+void x_outb(u16 port, u8 val);
+void x_outw(u16 port, u16 val);
+u32 x_inl(u16 port);
+void x_outl(u16 port, u32 val);
+
+u8 Mem_rb(int addr);
+u16 Mem_rw(int addr);
+u32 Mem_rl(int addr);
+
+void Mem_wb(int addr, u8 val);
+void Mem_ww(int addr, u16 val);
+void Mem_wl(int addr, u32 val);
+void getsecs(unsigned long *sec, unsigned long *usec);
+u8 bios_checksum(u8 * start, int size);
+
+#endif
diff --git a/util/vgabios/include/console/console.h b/util/vgabios/include/console/console.h
index e74cbb3..e52dbf7 100644
--- a/util/vgabios/include/console/console.h
+++ b/util/vgabios/include/console/console.h
@@ -1,4 +1,6 @@
 #ifndef _CONSOLE_CONSOLE_H
 #define _CONSOLE_CONSOLE_H
 #define CONFIG_X86EMU_DEBUG 1
+
+int printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
 #endif
diff --git a/util/vgabios/int10.c b/util/vgabios/int10.c
index bccb3d9..21ba7fb 100644
--- a/util/vgabios/int10.c
+++ b/util/vgabios/int10.c
@@ -1,9 +1,7 @@
 #include <stdio.h>
-#include "test.h"
-#include "pci.h"
+#include <stdtypes.h>
+#include "testbios.h"
 
-void x86emu_dump_xregs(void);
-extern ptr current;
 extern int verbose;
 
 
@@ -16,7 +14,7 @@ extern int verbose;
  * arise.  What are "Not Implemented" throughout are video memory accesses.
  * Also, very little input validity checking is done here.
  */
-int int42_handler()
+int int42_handler(void)
 {
 #if 0
 	if (verbose && X86_AH != 0x0e) {
diff --git a/util/vgabios/int15.c b/util/vgabios/int15.c
index 239b6be..a1235bb 100644
--- a/util/vgabios/int15.c
+++ b/util/vgabios/int15.c
@@ -1,12 +1,11 @@
 #include <stdio.h>
-#include "test.h"
-
-void x86emu_dump_xregs();
+#include <stdtypes.h>
+#include "testbios.h"
 
 int int15_handler(void)
 {
 	printf("\nint15 encountered.\n");
-	//x86emu_dump_xregs();
+	x86emu_dump_xregs();
 	X86_EAX = 0;
 	return 1;
 }
diff --git a/util/vgabios/int16.c b/util/vgabios/int16.c
index f3a9719..06df826 100644
--- a/util/vgabios/int16.c
+++ b/util/vgabios/int16.c
@@ -1,7 +1,9 @@
 #include <stdio.h>
+#include "testbios.h"
 
 int int16_handler(void)
 {
 	printf("\nint16: keyboard not supported right now.\n");
+	x86emu_dump_xregs();
 	return 1;
 }
diff --git a/util/vgabios/int1a.c b/util/vgabios/int1a.c
index bd9a24c..9fcff8a 100644
--- a/util/vgabios/int1a.c
+++ b/util/vgabios/int1a.c
@@ -1,5 +1,6 @@
 #include <stdio.h>
-#include "test.h"
+#include <stdtypes.h>
+#include "testbios.h"
 #include "pci-userspace.h"
 
 #define DEBUG_INT1A
@@ -8,13 +9,11 @@
 #define DEVICE_NOT_FOUND        0x86
 #define BAD_REGISTER_NUMBER     0x87
 
-void x86emu_dump_xregs(void);
 extern int verbose;
 
-
-int int1A_handler()
+int int1A_handler(void)
 {
-	PCITAG tag;
+	PCITAG tag = NULL;
 	pciVideoPtr pvp = NULL;
 
 	if (verbose) {
@@ -40,7 +39,7 @@ int int1A_handler()
 		if (X86_DX == pvp->vendor_id && X86_CX == pvp->device_id && X86_ESI == 0) {
 			X86_EAX = X86_AL | (SUCCESSFUL << 8);
 			X86_EFLAGS &= ~((unsigned long) 0x01);	/* clear carry flag */
-			X86_EBX = pciSlotBX(pvp);
+			X86_EBX = pciSlotBX(tag); // XXX used to be pvp, but both are NULL
 		}
 #ifdef SHOW_ALL_DEVICES
 		else if ((pvp = xf86FindPciDeviceVendor(X86_EDX, X86_ECX, X86_ESI, pvp))) {
diff --git a/util/vgabios/inte6.c b/util/vgabios/inte6.c
index 0f6a578..19b6110 100644
--- a/util/vgabios/inte6.c
+++ b/util/vgabios/inte6.c
@@ -1,6 +1,7 @@
 #include <stdio.h>
+#include "testbios.h"
 
-int intE6_handler()
+int intE6_handler(void)
 {
 #if 0
 	pciVideoPtr pvp;
@@ -14,5 +15,6 @@ int intE6_handler()
 	X86_ES = 0;		/* standard pc es */
 #endif
 	printf("intE6 not supported right now.\n");
+	x86emu_dump_xregs();
 	return 1;
 }
diff --git a/util/vgabios/pci-userspace.c b/util/vgabios/pci-userspace.c
index bc71a61..796933e 100644
--- a/util/vgabios/pci-userspace.c
+++ b/util/vgabios/pci-userspace.c
@@ -1,6 +1,5 @@
 #include <stdio.h>
-#include <pci/pci.h>
-#include "pci.h"
+#include "pci-userspace.h"
 
 #ifdef PCI_LIB_VERSION
 #define LIBPCI_CHECK_VERSION(major,minor,micro) \
diff --git a/util/vgabios/pci-userspace.h b/util/vgabios/pci-userspace.h
index 0944330..103a9ef 100644
--- a/util/vgabios/pci-userspace.h
+++ b/util/vgabios/pci-userspace.h
@@ -1,9 +1,13 @@
-#include "pci.h"
+#ifndef __PCI_USERSPACE_H__
+#define __PCI_USERSPACE_H__
+
+#include <pci/pci.h>
 
 typedef unsigned long pciaddr_t;
 typedef u8 byte;
 typedef u16 word;
 
+#if 0
 struct pci_dev {
 	struct pci_dev *next;	/* Next device in the chain */
 	word bus;		/* Higher byte can select host bridges */
@@ -32,7 +36,7 @@ struct pci_filter {
 	int bus, slot, func;	/* -1 = ANY */
 	int vendor, device;
 };
-
+#endif
 
 #define PCITAG struct pci_filter *
 #define pciVideoPtr struct pci_dev *
@@ -44,7 +48,8 @@ int pciExit(void);
 
 
 PCITAG findPci(unsigned short bx);
-u32 pciSlotBX(pciVideoPtr pvp);
+//u32 pciSlotBX(pciVideoPtr pvp);
+u32 pciSlotBX(PCITAG tag);
 
 void pciWriteLong(PCITAG tag, u32 idx, u32 data);
 void pciWriteWord(PCITAG tag, u32 idx, u16 data);
@@ -53,3 +58,5 @@ void pciWriteByte(PCITAG tag, u32 idx, u8 data);
 u32 pciReadLong(PCITAG tag, u32 idx);
 u16 pciReadWord(PCITAG tag, u32 idx);
 u8 pciReadByte(PCITAG tag, u32 idx);
+
+#endif
diff --git a/util/vgabios/pci.h b/util/vgabios/pci.h
deleted file mode 100644
index e51ebe4..0000000
--- a/util/vgabios/pci.h
+++ /dev/null
@@ -1,2 +0,0 @@
-void x_outb(u16 port, u8 val);
-#define outb x_outb
diff --git a/util/vgabios/test.h b/util/vgabios/test.h
deleted file mode 100644
index 7804ac2..0000000
--- a/util/vgabios/test.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/int10/xf86x86emu.h,v 1.2 2001/01/06 20:19:13 tsi Exp $ */
-/*
- *                   XFree86 int10 module
- *   execute BIOS int 10h calls in x86 real mode environment
- *                 Copyright 1999 Egbert Eich
- */
-#ifndef XF86X86EMU_H_
-#define XF86X86EMU_H_
-#include <x86emu/x86emu.h>
-
-#define M _X86EMU_env
-
-#define X86_EAX M.x86.R_EAX
-#define X86_EBX M.x86.R_EBX
-#define X86_ECX M.x86.R_ECX
-#define X86_EDX M.x86.R_EDX
-#define X86_ESI M.x86.R_ESI
-#define X86_EDI M.x86.R_EDI
-#define X86_EBP M.x86.R_EBP
-#define X86_EIP M.x86.R_EIP
-#define X86_ESP M.x86.R_ESP
-#define X86_EFLAGS M.x86.R_EFLG
-
-#define X86_FLAGS M.x86.R_FLG
-#define X86_AX M.x86.R_AX
-#define X86_BX M.x86.R_BX
-#define X86_CX M.x86.R_CX
-#define X86_DX M.x86.R_DX
-#define X86_SI M.x86.R_SI
-#define X86_DI M.x86.R_DI
-#define X86_BP M.x86.R_BP
-#define X86_IP M.x86.R_IP
-#define X86_SP M.x86.R_SP
-#define X86_CS M.x86.R_CS
-#define X86_DS M.x86.R_DS
-#define X86_ES M.x86.R_ES
-#define X86_SS M.x86.R_SS
-#define X86_FS M.x86.R_FS
-#define X86_GS M.x86.R_GS
-
-#define X86_AL M.x86.R_AL
-#define X86_BL M.x86.R_BL
-#define X86_CL M.x86.R_CL
-#define X86_DL M.x86.R_DL
-
-#define X86_AH M.x86.R_AH
-#define X86_BH M.x86.R_BH
-#define X86_CH M.x86.R_CH
-#define X86_DH M.x86.R_DH
-
-
-/* int10 info structure */
-typedef struct {
-	u16 BIOSseg;
-	u16 inb40time;
-	struct _mem *mem;
-	int num;
-	int ax;
-	int bx;
-	int cx;
-	int dx;
-	int si;
-	int di;
-	int es;
-	int bp;
-	int flags;
-	int stackseg;
-} _ptr, *ptr;
-
-typedef struct _mem {
-	u8(*rb) (ptr, int);
-	u16(*rw) (ptr, int);
-	u32(*rl) (ptr, int);
-	void (*wb) (ptr, int, u8);
-	void (*ww) (ptr, int, u16);
-	void (*wl) (ptr, int, u32);
-} mem;
-
-#define MEM_WB(where, what) wrb(where,what)
-#define MEM_WW(where, what) wrw(where, what)
-#define MEM_WL(where, what) wrl(where, what)
-
-#define MEM_RB(where) rdb(where)
-#define MEM_RW(where) rdw(where)
-#define MEM_RL(where) rdl(where)
-
-extern ptr current;
-
-#endif
diff --git a/util/vgabios/testbios.c b/util/vgabios/testbios.c
index a6e121e..8c9783f 100644
--- a/util/vgabios/testbios.c
+++ b/util/vgabios/testbios.c
@@ -6,26 +6,18 @@
 #include <fcntl.h>
 #include <getopt.h>
 #include <string.h>
+#include <stdarg.h>
 
+#include <stdtypes.h>
 #define die(x) { perror(x); exit(1); }
 #define warn(x) { perror(x);  }
 
 #include <x86emu/x86emu.h>
+#include <console/console.h>
 #include "helper_exec.h"
-#include "test.h"
+#include "testbios.h"
 #include "pci-userspace.h"
-
-void x86emu_dump_xregs(void);
-int int15_handler(void);
-int int16_handler(void);
-int int1A_handler(void);
-#ifndef _PC
-int int42_handler(void);
-#endif
-int intE6_handler(void);
-
-void pushw(u16 val);
-
+int X86EMU_set_debug(int debug);
 unsigned short get_device(char *arg_val);
 
 extern int teststart, testend;
@@ -39,7 +31,7 @@ int verbose = 0;
 
 /* Interrupt multiplexer */
 
-void do_int(int num)
+static void do_int(int num)
 {
 	int ret = 0;
 
@@ -84,7 +76,7 @@ void do_int(int num)
 	}
 }
 
-unsigned char *mapitin(char *file, off_t where, size_t size)
+static unsigned char *mapitin(char *file, off_t where, size_t size)
 {
 	void *z;
 
@@ -101,21 +93,13 @@ unsigned char *mapitin(char *file, off_t where, size_t size)
 
 }
 
-u8 x_inb(u16 port);
-u16 x_inw(u16 port);
-void x_outb(u16 port, u8 val);
-void x_outw(u16 port, u16 val);
-u32 x_inl(u16 port);
-void x_outl(u16 port, u32 val);
-
-
 X86EMU_pioFuncs myfuncs = {
 	x_inb, x_inw, x_inl,
 	x_outb, x_outw, x_outl
 };
 
 
-void usage(char *name)
+static void usage(char *name)
 {
 	printf
 	    ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ... \n",
@@ -129,7 +113,7 @@ int main(int argc, char **argv)
 	int i, c, trace = 0;
 	unsigned char *cp;
 	char *filename;
-	size_t size = 0;
+	ssize_t size = 0;
 	int base = 0;
 	int have_size = 0, have_base = 0, have_ip = 0, have_cs = 0;
 	int have_devfn = 0;
@@ -138,9 +122,6 @@ int main(int argc, char **argv)
 	unsigned char *fsegptr;
 	unsigned short initialip = 0, initialcs = 0, devfn = 0;
 	X86EMU_intrFuncs intFuncs[256];
-	void X86EMU_setMemBase(void *base, size_t size);
-	void x86emu_dump_xregs(void);
-	int X86EMU_set_debug(int debug);
 	int debugflag = 0;
 
 	const char *optstring = "vh?b:i:c:s:tpd:";
@@ -192,7 +173,6 @@ int main(int argc, char **argv)
 			have_size = 1;
 			break;
 		case 'p':
-			printf("Parsing rom images not implemented.\n");
 			parse_rom = 1;
 			break;
 		case 'f':
@@ -250,6 +230,9 @@ int main(int argc, char **argv)
 		initialip = 0x0003;
 	}
 
+	if (parse_rom)
+		printf("Parsing rom images not implemented.\n");
+
 	//printf("Point 1 int%x vector at %x\n", 0x42, getIntVect(0x42));
 
 	if (initialip == 0x0003) {
@@ -314,7 +297,7 @@ int main(int argc, char **argv)
 		for (i = 0; i < 0x10000; i++)
 			wrb(0xf0000 + i, fsegptr[i]);
 	} else {
-		char *date = "01/01/99";
+		const char *date = "01/01/99";
 		for (i = i; date[i]; i++)
 			wrb(0xffff5 + i, date[i]);
 		wrb(0xffff7, '/');
@@ -391,3 +374,16 @@ unsigned short get_device(char *arg_val)
 
 	return devfn;
 }
+
+int printk(int msg_level, const char *fmt, ...)
+{
+	va_list args;
+	int i;
+
+	printf ("<%d> ", msg_level);
+	va_start(args, fmt);
+	i = vprintf(fmt, args);
+	va_end(args);
+
+	return i;
+}
diff --git a/util/vgabios/testbios.h b/util/vgabios/testbios.h
new file mode 100644
index 0000000..a5a8b0d
--- /dev/null
+++ b/util/vgabios/testbios.h
@@ -0,0 +1,98 @@
+/* Derived from:
+ *                   XFree86 int10 module
+ *   execute BIOS int 10h calls in x86 real mode environment
+ *                 Copyright 1999 Egbert Eich
+ */
+
+#ifndef __TESTBIOS_H__
+#define __TESTBIOS_H__
+
+void x86emu_dump_xregs(void);
+int int15_handler(void);
+int int16_handler(void);
+int int1A_handler(void);
+int int42_handler(void);
+int intE6_handler(void);
+
+#include <stdtypes.h>
+#include <x86emu/x86emu.h>
+
+#define M _X86EMU_env
+
+#define X86_EAX M.x86.R_EAX
+#define X86_EBX M.x86.R_EBX
+#define X86_ECX M.x86.R_ECX
+#define X86_EDX M.x86.R_EDX
+#define X86_ESI M.x86.R_ESI
+#define X86_EDI M.x86.R_EDI
+#define X86_EBP M.x86.R_EBP
+#define X86_EIP M.x86.R_EIP
+#define X86_ESP M.x86.R_ESP
+#define X86_EFLAGS M.x86.R_EFLG
+
+#define X86_FLAGS M.x86.R_FLG
+#define X86_AX M.x86.R_AX
+#define X86_BX M.x86.R_BX
+#define X86_CX M.x86.R_CX
+#define X86_DX M.x86.R_DX
+#define X86_SI M.x86.R_SI
+#define X86_DI M.x86.R_DI
+#define X86_BP M.x86.R_BP
+#define X86_IP M.x86.R_IP
+#define X86_SP M.x86.R_SP
+#define X86_CS M.x86.R_CS
+#define X86_DS M.x86.R_DS
+#define X86_ES M.x86.R_ES
+#define X86_SS M.x86.R_SS
+#define X86_FS M.x86.R_FS
+#define X86_GS M.x86.R_GS
+
+#define X86_AL M.x86.R_AL
+#define X86_BL M.x86.R_BL
+#define X86_CL M.x86.R_CL
+#define X86_DL M.x86.R_DL
+
+#define X86_AH M.x86.R_AH
+#define X86_BH M.x86.R_BH
+#define X86_CH M.x86.R_CH
+#define X86_DH M.x86.R_DH
+
+
+/* int10 info structure */
+typedef struct {
+	u16 BIOSseg;
+	u16 inb40time;
+	struct _mem *mem;
+	int num;
+	int ax;
+	int bx;
+	int cx;
+	int dx;
+	int si;
+	int di;
+	int es;
+	int bp;
+	int flags;
+	int stackseg;
+} _ptr, *ptr;
+
+typedef struct _mem {
+	u8(*rb) (ptr, int);
+	u16(*rw) (ptr, int);
+	u32(*rl) (ptr, int);
+	void (*wb) (ptr, int, u8);
+	void (*ww) (ptr, int, u16);
+	void (*wl) (ptr, int, u32);
+} mem;
+
+#define MEM_WB(where, what) wrb(where,what)
+#define MEM_WW(where, what) wrw(where, what)
+#define MEM_WL(where, what) wrl(where, what)
+
+#define MEM_RB(where) rdb(where)
+#define MEM_RW(where) rdw(where)
+#define MEM_RL(where) rdl(where)
+
+extern ptr current;
+
+#endif


From gerrit at coreboot.org  Tue Sep 29 02:03:55 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Tue, 29 Sep 2015 02:03:55 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+7@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit d1a046882da65c4849cc5306e10629dbd3e6b1b9
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                               | 23 ++++++-------
 src/cpu/amd/model_10xxx/Makefile.inc               |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c           |  3 --
 src/cpu/amd/model_fxx/Makefile.inc                 |  2 +-
 src/cpu/intel/ep80579/Makefile.inc                 |  2 --
 src/cpu/intel/ep80579/microcode_blob.c             |  8 -----
 src/cpu/intel/fsp_model_206ax/Kconfig              |  5 ---
 src/cpu/intel/fsp_model_206ax/Makefile.inc         |  9 ++---
 src/cpu/intel/fsp_model_206ax/microcode_blob.c     | 22 -------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h     | 33 -------------------
 src/cpu/intel/fsp_model_406dx/Kconfig              |  4 ---
 src/cpu/intel/fsp_model_406dx/Makefile.inc         | 10 ++----
 src/cpu/intel/fsp_model_406dx/microcode_blob.c     | 29 -----------------
 src/cpu/intel/haswell/Makefile.inc                 |  5 +--
 src/cpu/intel/haswell/microcode_blob.c             | 30 -----------------
 src/cpu/intel/model_1067x/Makefile.inc             |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c         |  3 --
 src/cpu/intel/model_106cx/Makefile.inc             |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c         |  3 --
 src/cpu/intel/model_2065x/Makefile.inc             |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c         | 22 -------------
 src/cpu/intel/model_206ax/Makefile.inc             |  3 +-
 src/cpu/intel/model_206ax/microcode_blob.c         | 23 -------------
 src/cpu/intel/model_65x/Makefile.inc               |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c           |  3 --
 src/cpu/intel/model_67x/Makefile.inc               |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c           |  3 --
 src/cpu/intel/model_68x/Makefile.inc               |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c           |  3 --
 src/cpu/intel/model_69x/Makefile.inc               |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c           |  3 --
 src/cpu/intel/model_6bx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6dx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6ex/Makefile.inc               |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c           |  3 --
 src/cpu/intel/model_6fx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6xx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c           |  3 --
 src/cpu/intel/model_f0x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f1x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f2x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f3x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c           |  3 --
 src/cpu/intel/model_f4x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c           |  3 --
 src/cpu/via/nano/Makefile.inc                      |  4 +--
 src/soc/intel/baytrail/Makefile.inc                |  3 +-
 src/soc/intel/baytrail/microcode/Makefile.inc      |  1 -
 src/soc/intel/baytrail/microcode/microcode_blob.c  |  3 --
 src/soc/intel/braswell/Makefile.inc                |  3 +-
 src/soc/intel/braswell/microcode/Makefile.inc      |  2 --
 src/soc/intel/braswell/microcode/microcode_blob.c  | 22 -------------
 src/soc/intel/broadwell/Makefile.inc               |  3 +-
 src/soc/intel/broadwell/microcode/Makefile.inc     |  1 -
 src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
 src/soc/intel/fsp_baytrail/Makefile.inc            |  3 +-
 src/soc/intel/fsp_baytrail/microcode/Makefile.inc  | 26 ---------------
 .../intel/fsp_baytrail/microcode/microcode_blob.c  | 38 ----------------------
 .../intel/fsp_baytrail/microcode/microcode_size.h  |  6 ----
 src/soc/intel/skylake/Makefile.inc                 |  3 +-
 src/soc/intel/skylake/microcode/Makefile.inc       |  2 --
 src/soc/intel/skylake/microcode/microcode_blob.c   | 24 --------------
 68 files changed, 50 insertions(+), 436 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e8c5022..ce1112c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -54,6 +53,8 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index eda9f76..cf1fa50 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -52,6 +51,8 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 183c40f..b354e8c 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -74,6 +73,8 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 45ea3e4..ebc2cc5 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
 
 ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -60,6 +59,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
 ramstage-y += placeholders.c
 ramstage-y += i2c.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
-		/*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
-	#include "M0230672228.h"  // M0230672: Bay Trail "Super SKU" B0/B1
-	#include "M0130673322.h"  // M0130673: Bay Trail I B2 / B3
-	#include "M0130679901.h"  // M0130679: Bay Trail I D0
-#else
-	/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
-	#include "M0C30678829.h"  // M0C30678: Bay Trail M D Stepping
-#endif	/* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif	/* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	#define MICROCODE_REGION_LENGTH 0x30000
-#else
-	#define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 38668da..b74f353 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-


From gerrit at coreboot.org  Tue Sep 29 02:04:00 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Tue, 29 Sep 2015 02:04:00 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: 3dparty/blobs:
	Advance to pull in binary microcode
References: <I2071586e1f3b4464464928c11475f9283084dbcd+0@gerrit.coreboot.org>
Message-ID: <I2071586e1f3b4464464928c11475f9283084dbcd+4@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11693

-gerrit

commit 8834f0baed7d6204426396e99daaa3770f746adf
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sun Sep 20 21:08:05 2015 -0700

    3dparty/blobs: Advance to pull in binary microcode
    
    Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 3rdparty/blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index b4ade40..230923c 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7
+Subproject commit 230923c2b028f8048b0023754d1c73f4760f4b8d


From gerrit at coreboot.org  Tue Sep 29 02:51:41 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 29 Sep 2015 02:51:41 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: Makefile:
	Replace the way to test if a string is empty
References: <Ie4b8fe1fb26df092e2985937251a49feadc61eb0+0@gerrit.coreboot.org>
Message-ID: <E1Zgl13-0002fp-CV@mail.coreboot.org>

the following patch was just integrated into master:
commit 46a7c82bcf9418bc12972eb1c54d19c9a98a9e2b
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 11 08:49:38 2015 -0400

    Makefile: Replace the way to test if a string is empty
    
    The output of command below,
    # i386-elf-nm build/cbfs/fallback/romstage_null.offenders | \
                         grep -q "" ; echo $?
    has different result on MacOS, OS X Mavericks, which outputs 0.
    On linux, it outputs 1.
    
    I assume it is misleading to search an empty string in a empty
    string. Change it to testing if the string is empty.
    
    Change-Id: Ie4b8fe1fb26df092e2985937251a49feadc61eb0
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
    Reviewed-on: http://review.coreboot.org/11600
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11600 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 29 04:49:49 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 29 Sep 2015 04:49:49 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: 3dparty/blobs:
	Advance to pull in binary microcode
References: <I2071586e1f3b4464464928c11475f9283084dbcd+0@gerrit.coreboot.org>
Message-ID: <E1ZgmrN-000399-Op@mail.coreboot.org>

the following patch was just integrated into master:
commit 321402bfced59bd241711ed8ee4a6d8e46f9f081
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sun Sep 20 21:08:05 2015 -0700

    3dparty/blobs: Advance to pull in binary microcode
    
    Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11693
    Tested-by: build bot (Jenkins)
    Reviewed-by: Werner Zeh <werner.zeh at siemens.com>


See http://review.coreboot.org/11693 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 29 05:36:20 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Tue, 29 Sep 2015 05:36:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+8@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit eb2618a44a31bc361b25b53b421a4e56793090fd
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                               | 23 ++++++-------
 src/cpu/amd/model_10xxx/Makefile.inc               |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c           |  3 --
 src/cpu/amd/model_fxx/Makefile.inc                 |  2 +-
 src/cpu/intel/ep80579/Makefile.inc                 |  2 --
 src/cpu/intel/ep80579/microcode_blob.c             |  8 -----
 src/cpu/intel/fsp_model_206ax/Kconfig              |  5 ---
 src/cpu/intel/fsp_model_206ax/Makefile.inc         |  9 ++---
 src/cpu/intel/fsp_model_206ax/microcode_blob.c     | 22 -------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h     | 33 -------------------
 src/cpu/intel/fsp_model_406dx/Kconfig              |  4 ---
 src/cpu/intel/fsp_model_406dx/Makefile.inc         | 10 ++----
 src/cpu/intel/fsp_model_406dx/microcode_blob.c     | 29 -----------------
 src/cpu/intel/haswell/Makefile.inc                 |  5 +--
 src/cpu/intel/haswell/microcode_blob.c             | 30 -----------------
 src/cpu/intel/model_1067x/Makefile.inc             |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c         |  3 --
 src/cpu/intel/model_106cx/Makefile.inc             |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c         |  3 --
 src/cpu/intel/model_2065x/Makefile.inc             |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c         | 22 -------------
 src/cpu/intel/model_206ax/Makefile.inc             |  3 +-
 src/cpu/intel/model_206ax/microcode_blob.c         | 23 -------------
 src/cpu/intel/model_65x/Makefile.inc               |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c           |  3 --
 src/cpu/intel/model_67x/Makefile.inc               |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c           |  3 --
 src/cpu/intel/model_68x/Makefile.inc               |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c           |  3 --
 src/cpu/intel/model_69x/Makefile.inc               |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c           |  3 --
 src/cpu/intel/model_6bx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6dx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6ex/Makefile.inc               |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c           |  3 --
 src/cpu/intel/model_6fx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6xx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c           |  3 --
 src/cpu/intel/model_f0x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f1x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f2x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f3x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c           |  3 --
 src/cpu/intel/model_f4x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c           |  3 --
 src/cpu/via/nano/Makefile.inc                      |  4 +--
 src/soc/intel/baytrail/Makefile.inc                |  3 +-
 src/soc/intel/baytrail/microcode/Makefile.inc      |  1 -
 src/soc/intel/baytrail/microcode/microcode_blob.c  |  3 --
 src/soc/intel/braswell/Makefile.inc                |  3 +-
 src/soc/intel/braswell/microcode/Makefile.inc      |  2 --
 src/soc/intel/braswell/microcode/microcode_blob.c  | 22 -------------
 src/soc/intel/broadwell/Makefile.inc               |  3 +-
 src/soc/intel/broadwell/microcode/Makefile.inc     |  1 -
 src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
 src/soc/intel/fsp_baytrail/Makefile.inc            |  3 +-
 src/soc/intel/fsp_baytrail/microcode/Makefile.inc  | 26 ---------------
 .../intel/fsp_baytrail/microcode/microcode_blob.c  | 38 ----------------------
 .../intel/fsp_baytrail/microcode/microcode_size.h  |  6 ----
 src/soc/intel/fsp_baytrail/microcode_size.h        |  6 ++++
 src/soc/intel/skylake/Makefile.inc                 |  3 +-
 src/soc/intel/skylake/microcode/Makefile.inc       |  2 --
 src/soc/intel/skylake/microcode/microcode_blob.c   | 24 --------------
 69 files changed, 56 insertions(+), 436 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e8c5022..ce1112c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -54,6 +53,8 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index eda9f76..cf1fa50 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -52,6 +51,8 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 183c40f..b354e8c 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -74,6 +73,8 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 45ea3e4..ebc2cc5 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
 
 ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -60,6 +59,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
 ramstage-y += placeholders.c
 ramstage-y += i2c.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
-		/*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
-	#include "M0230672228.h"  // M0230672: Bay Trail "Super SKU" B0/B1
-	#include "M0130673322.h"  // M0130673: Bay Trail I B2 / B3
-	#include "M0130679901.h"  // M0130679: Bay Trail I D0
-#else
-	/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
-	#include "M0C30678829.h"  // M0C30678: Bay Trail M D Stepping
-#endif	/* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif	/* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	#define MICROCODE_REGION_LENGTH 0x30000
-#else
-	#define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/fsp_baytrail/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode_size.h
new file mode 100644
index 0000000..2af2201
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/microcode_size.h
@@ -0,0 +1,6 @@
+/* Maximum size of the area that the FSP will search for the correct microcode */
+#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
+	#define MICROCODE_REGION_LENGTH 0x30000
+#else
+	#define MICROCODE_REGION_LENGTH 0x10000
+#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 38668da..b74f353 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-


From gerrit at coreboot.org  Tue Sep 29 09:10:02 2015
From: gerrit at coreboot.org (WANG Siyuan (wangsiyuanbuaa@gmail.com))
Date: Tue, 29 Sep 2015 09:10:02 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: AMD Bettong:
	add memory configuration for DDR3 and DDR4
References: <Ia0d35ebf1b65c399abc3777ee6bdb107437a4345+0@gerrit.coreboot.org>
Message-ID: <Ia0d35ebf1b65c399abc3777ee6bdb107437a4345+1@gerrit.coreboot.org>

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11733

-gerrit

commit d49159f819ece1b51be6fca89ea4043de6705083
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Fri Jul 3 22:15:31 2015 +0800

    AMD Bettong: add memory configuration for DDR3 and DDR4
    
    1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4.
    Rev F's SPD address is different from DDR3.
    
                0   1
    Channel A  A0  A2
    Channel B  A4  AC
    
    2. DDR4 uses different memory configuration in AGESA.
    Pass memory configuration parameters in agesawrapper_amdinitpost.
    
    3. Tested on Rev C and Rev F.
    Both of them can boot to Windows 8 and have the correct memory size.
    
    Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/northbridge/amd/pi/00660F01/dimmSpd.c | 19 ++++++++++++++++-
 src/northbridge/amd/pi/agesawrapper.c     | 35 +++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c
index 6996f83..0244f3e 100644
--- a/src/northbridge/amd/pi/00660F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c
@@ -20,6 +20,7 @@
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <stdlib.h>
+#include <string.h>
 
 /* warning: Porting.h includes an open #pragma pack(1) */
 #include "Porting.h"
@@ -27,12 +28,28 @@
 #include "amdlib.h"
 #include "chip.h"
 #include "northbridge/amd/pi/dimmSpd.h"
+#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG)
+#include "board_rev.h"
+#endif
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
 	int spdAddress;
 	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
+	struct northbridge_amd_pi_00660F01_config *config, user_config;
+	memcpy(&user_config, dev->chip_info, sizeof(user_config));
+
+#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG)
+	char boardid = get_board_id();
+	if (boardid == 'F') {
+		user_config.spdAddrLookup[0][0][0] = 0xA0;
+		user_config.spdAddrLookup[0][0][1] = 0xA2;
+		user_config.spdAddrLookup[0][1][0] = 0xA4;
+		user_config.spdAddrLookup[0][1][1] = 0xAC;
+	}
+#endif
+
+	config = &user_config;
 
 	if ((dev == 0) || (config == 0))
 		return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 9bdf340..8a72660 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -26,6 +26,10 @@
 #include <heapManager.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/BiosCallOuts.h>
+#include <PlatformMemoryConfiguration.h>
+#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG)
+#include "board_rev.h"
+#endif
 
 VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
 VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -136,6 +140,37 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	AmdCreateStruct (&AmdParamStruct);
 	PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
 
+	PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
+		DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
+		NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+		NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+		MOTHER_BOARD_LAYERS (LAYERS_6),
+		MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		PSO_END
+	};
+
+	PSO_ENTRY DDR3PlatformMemoryConfiguration[] = {
+		DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY),
+		NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+		NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+		MOTHER_BOARD_LAYERS (LAYERS_6),
+		MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		PSO_END
+	};
+
+#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG)
+	char boardid = get_board_id();
+	if (boardid == 'F')
+		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
+	else
+		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR3PlatformMemoryConfiguration;
+#endif
 	// Do not use IS_ENABLED here.  CONFIG_GFXUMA should always have a value.  Allow
 	// the compiler to flag the error if CONFIG_GFXUMA is not set.
 	PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;


From gerrit at coreboot.org  Tue Sep 29 13:55:56 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 29 Sep 2015 13:55:56 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel: auto
	include intel/common/firmware
References: <I166db67c41b16c4d9f0116abce00940514539fa5+0@gerrit.coreboot.org>
Message-ID: <E1ZgvNs-0006X1-Is@mail.coreboot.org>

the following patch was just integrated into master:
commit 7dcb545ee2770f3a27d57c2d69cfa140af2d0348
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 30 16:50:21 2015 -0500

    intel: auto include intel/common/firmware
    
    Instead of selecting the Kconfig option and adding the subdir
    entry within each chipset auto include the common/firmware
    directory as it's guarded by HAVE_INTEL_FIRMWARE.
    
    BUG=chrome-os-partner:43462
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I166db67c41b16c4d9f0116abce00940514539fa5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11734
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11734 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 29 13:56:11 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 29 Sep 2015 13:56:11 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: skylake:
	select HAVE_INTEL_FIRMWARE
References: <I7196f587b92fd26129b30e2cd73f4caf5f4ebef8+0@gerrit.coreboot.org>
Message-ID: <E1ZgvO7-0006ab-Ar@mail.coreboot.org>

the following patch was just integrated into master:
commit 387084cfb4e202af048f51842c24d443a8a0b927
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 30 13:41:01 2015 -0500

    skylake: select HAVE_INTEL_FIRMWARE
    
    Use the common ME and descriptor code.
    
    BUG=chrome-os-partner:43462
    BRANCH=None
    TEST=Built glados
    
    Change-Id: I7196f587b92fd26129b30e2cd73f4caf5f4ebef8
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11735
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11735 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 29 16:16:16 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Tue, 29 Sep 2015 16:16:16 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+10@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit be5129449a635321e8d776d4316a502d2ad478e2
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/drivers/intel/fsp1_0/Makefile.inc | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..0ec52ec 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,8 +23,15 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
+ifneq ($(cpu_microcode-objs),)
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
+	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+
+cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h
+endif
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)
@@ -45,3 +52,4 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+


From gerrit at coreboot.org  Tue Sep 29 16:33:58 2015
From: gerrit at coreboot.org (WANG Siyuan (wangsiyuanbuaa@gmail.com))
Date: Tue, 29 Sep 2015 16:33:58 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: add
	README
References: <Ie8b761096fd1850afb9363ebb761aa4992b47643+0@gerrit.coreboot.org>
Message-ID: <Ie8b761096fd1850afb9363ebb761aa4992b47643+2@gerrit.coreboot.org>

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11737

-gerrit

commit 64daad064db528b6cb4ca9759f81fe0b08307af5
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Tue Sep 29 11:12:03 2015 +0800

    AMD Bettong: add README
    
    AMD provide stable Bettong code in github.
    
    Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/mainboard/amd/bettong/README | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/mainboard/amd/bettong/README b/src/mainboard/amd/bettong/README
new file mode 100644
index 0000000..acbe0bb
--- /dev/null
+++ b/src/mainboard/amd/bettong/README
@@ -0,0 +1,23 @@
+coreboot is changing all the time and the patches are reabsed when push to
+community, so it is a little difficult to provide stable Bettong code.
+From now on, AMD provide souce code which is validated by QA team.
+The code is push to github https://github.com/BTDC/coreboot
+The version is identified by tag. All the changes will be push to coreboot
+community.
+
+=====
+TCMEF1F0:
+1. Fix external graphics issue.
+2. Add board ID support.
+3. Support DDR4.
+4. Support SD 2.0.
+5. Fix Windows 7 S4 issue.
+6. Add GPIO, I2C and UART support.
+7. Fix the interrupt routine.
+8. Restruct PCI interrupt table (C00/C01).
+9. Fix DSDT issue.
+10. Fix the PCIe lane map.
+11. Lower the TOM to give more MMIO space.
+12. Add USB device.
+13. Set the USB3 port as unremoveable.
+14. Update AGESA to CarrizoPI 1.1.0.1.


From gerrit at coreboot.org  Tue Sep 29 16:34:10 2015
From: gerrit at coreboot.org (WANG Siyuan (wangsiyuanbuaa@gmail.com))
Date: Tue, 29 Sep 2015 16:34:10 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: add
	get_board_id to read board version
References: <I72df28043057d8c4ccc4a2e645011ca5379e9928+0@gerrit.coreboot.org>
Message-ID: <I72df28043057d8c4ccc4a2e645011ca5379e9928+2@gerrit.coreboot.org>

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11732

-gerrit

commit 3dca48afd5a754696bdabedc90220d60cef36ffd
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Fri Jul 3 20:29:56 2015 +0800

    AMD Bettong: add get_board_id to read board version
    
    Bettong use 3 GPIO(5-7) ports to identify board.
    The GPIO ports are mapped to MMIO space.
    The GPIO value and board version are mapped as follow:
    GPIO5 GPIO6 GPIO7 Version
      0     0     0      A
      0     0     1      B
      ......
      1     1     1      H
    
    Change-Id: I72df28043057d8c4ccc4a2e645011ca5379e9928
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/mainboard/amd/bettong/Makefile.inc |  2 ++
 src/mainboard/amd/bettong/boardid.c    | 45 ++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+)

diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc
index 70722ee..197da03 100644
--- a/src/mainboard/amd/bettong/Makefile.inc
+++ b/src/mainboard/amd/bettong/Makefile.inc
@@ -19,9 +19,11 @@
 
 romstage-y += BiosCallOuts.c
 romstage-y += PlatformGnbPcie.c
+romstage-y += boardid.c
 
 ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
 ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
 ramstage-y += fchec.c
 endif
+ramstage-y += boardid.c
diff --git a/src/mainboard/amd/bettong/boardid.c b/src/mainboard/amd/bettong/boardid.c
new file mode 100644
index 0000000..30343d7
--- /dev/null
+++ b/src/mainboard/amd/bettong/boardid.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <reset.h>
+#include <boardid.h>
+
+uint8_t board_id(void)
+{
+	u32 gpiommioaddr;
+	u8  value = 0;
+	u8  boardrev = 0;
+	char boardid;
+
+	gpiommioaddr = 0xfed80000ul + 0x1500;
+	value = *(volatile u8 *) (gpiommioaddr + (7 << 2) + 2); //agpio7 //board_id2
+	boardrev = value & 1;
+	value = *(volatile u8 *) (gpiommioaddr + (6 << 2) + 2); //agpio6 //board_id1
+	boardrev |= (value & 1) << 1;
+	value = *(volatile u8 *) (gpiommioaddr + (5 << 2) + 2); //agpio5 //board_id0
+	boardrev |= (value & 1) << 2;
+
+	boardid = 'A' + boardrev;
+
+	return boardid;
+}


From gerrit at coreboot.org  Tue Sep 29 17:58:05 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Tue, 29 Sep 2015 17:58:05 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: intel/fsp1.0: Get
	size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <I868f02b0cc03af12464a6a87c59761c200eb2502+11@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709

-gerrit

commit 47d4cb3b2db9944e85038d20b9486ceb7b0293b8
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/drivers/intel/fsp1_0/Makefile.inc | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..0ec52ec 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,8 +23,15 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
+ifneq ($(cpu_microcode-objs),)
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
+	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+
+cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h
+endif
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)
@@ -45,3 +52,4 @@ mrc.cache-file := $(obj)/mrc.cache
 mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
+


From gerrit at coreboot.org  Tue Sep 29 18:07:28 2015
From: gerrit at coreboot.org (Audrey Pearson (apearson@raptorengineeringinc.com))
Date: Tue, 29 Sep 2015 18:07:28 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	northbridge/intel/gm45: Fixed FTBFS on Lenovo X200
References: <Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25+0@gerrit.coreboot.org>
Message-ID: <Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25+1@gerrit.coreboot.org>

Audrey Pearson (apearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11738

-gerrit

commit 953e2a1630fe606edf92c9bfcd5e1eebebe77dea
Author: Audrey Pearson <apearson at raptorengineeringinc.com>
Date:   Tue Sep 29 12:36:52 2015 -0500

    northbridge/intel/gm45: Fixed FTBFS on Lenovo X200
    
    Change-Id: Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25
    Signed-off-by: Audrey Pearson <apearson at raptorengineeringinc.com>
---
 src/northbridge/intel/gm45/gma.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index f29b9b1..ffe3019 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -161,19 +161,19 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 
 	hactive = edid.x_resolution;
 	vactive = edid.y_resolution;
-	right_border = edid.hborder;
-	bottom_border = edid.vborder;
-	hpolarity = (edid.phsync == '-');
-	vpolarity = (edid.pvsync == '-');
-	vsync = edid.vspw;
-	hsync = edid.hspw;
-	vblank = edid.vbl;
-	hblank = edid.hbl;
-	hfront_porch = edid.hso;
-	vfront_porch = edid.vso;
-
-	target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
-		: (2 * edid.pixel_clock);
+	right_border = edid.mode.hborder;
+	bottom_border = edid.mode.vborder;
+	hpolarity = (edid.mode.phsync == '-');
+	vpolarity = (edid.mode.pvsync == '-');
+	vsync = edid.mode.vspw;
+	hsync = edid.mode.hspw;
+	vblank = edid.mode.vbl;
+	hblank = edid.mode.hbl;
+	hfront_porch = edid.mode.hso;
+	vfront_porch = edid.mode.vso;
+
+	target_frequency = info->gfx.lvds_dual_channel ? edid.mode.pixel_clock
+		: (2 * edid.mode.pixel_clock);
 #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_sr_write(1, 1);
 	vga_sr_write(0x2, 0xf);
@@ -240,8 +240,8 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 		return;
 	}
 
-	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
-	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
+	link_m1 = ((uint64_t)link_n1 * edid.mode.pixel_clock) / link_frequency;
+	data_m1 = ((uint64_t)data_n1 * 18 * edid.mode.pixel_clock)
 		/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",


From gerrit at coreboot.org  Tue Sep 29 19:44:49 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Tue, 29 Sep 2015 19:44:49 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: [NOTFORMERGE]
	src/Kconfig: Enable code coverage by default
References: <I3f1860004ccdaa429cfa0b531764e7e9027f0044+0@gerrit.coreboot.org>
Message-ID: <I3f1860004ccdaa429cfa0b531764e7e9027f0044+3@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11728

-gerrit

commit d5e885e86cfe861f98d419fb2fb5f9ac58ecf9c1
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Sat Sep 26 13:15:15 2015 +0200

    [NOTFORMERGE] src/Kconfig: Enable code coverage by default
    
    Change-Id: I3f1860004ccdaa429cfa0b531764e7e9027f0044
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 2c75750..74a032e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -210,7 +210,7 @@ config USE_BLOBS
 config COVERAGE
 	bool "Code coverage support"
 	depends on COMPILER_GCC
-	default n
+	default y
 	help
 	  Add code coverage support for coreboot. This will store code
 	  coverage information in CBMEM for extraction from user space.
@@ -1028,7 +1028,7 @@ config TRACE
 
 config DEBUG_COVERAGE
 	bool "Debug code coverage"
-	default n
+	default y
 	depends on COVERAGE
 	help
 	  If enabled, the code coverage hooks in coreboot will output some


From gerrit at coreboot.org  Tue Sep 29 20:17:05 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 29 Sep 2015 20:17:05 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: provide
	common macro for linking early stages
References: <I12f4872df09fff6715829de68fc374e230350c2e+0@gerrit.coreboot.org>
Message-ID: <I12f4872df09fff6715829de68fc374e230350c2e+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11739

-gerrit

commit 2fe6e8dd907fb0019b41a4e8f2e9d12ca979cb13
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 14:54:25 2015 -0500

    x86: provide common macro for linking early stages
    
    In order to support verstage on x86 one needs to link verstage
    like romstage since it needs all the cache-as-ram goodies. Therefore,
    provide a macro that one can invoke that provides the necessary
    recipes for linking that particular stage in such an environment.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I12f4872df09fff6715829de68fc374e230350c2e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc     | 49 ++++++++++++++++++++++++-------------------
 src/arch/x86/assembly_entry.S | 37 ++++++++++++++++++++++++++++++++
 src/arch/x86/romstage.S       | 37 --------------------------------
 3 files changed, 65 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 1779099..f16edcd 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -115,27 +115,44 @@ endif
 endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ###############################################################################
-# romstage
+# common support for early assembly includes
 ###############################################################################
 
-ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
-
-romstage-y += memlayout.ld
-
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
 # into a single generated file.
 crt0s = $(cpu_incs-y)
 
-$(objgenerated)/romstage.inc: $$(crt0s)
+$(objgenerated)/assembly.inc: $$(crt0s)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
+define early_x86_stage
+# $1 stage name
+# $2 oformat
+$(1)-y += memlayout.ld
 # Add the assembly file that pulls in the rest of the dependencies in
-# the right order. Make sure the auto generated romstage.inc is a proper
+# the right order. Make sure the auto generated assembly.inc is a proper
 # dependency.
-romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(1)-y += assembly_entry.S
+$$(obj)/arch/x86/assembly_entry.$(1).o: $(objgenerated)/assembly.inc
+
+$$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs)
+	@printf "    LINK       $$(subst $$(obj)/,,$$(@))\n"
+	$$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $$(obj)/arch/x86/memlayout.$(1).ld --oformat $(2)
+	LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders 2>&1 | \
+	grep -v "Empty loadable segment detected" && \
+	$$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders | grep -q ""; if [ $$$$? -eq 0 ]; then \
+		echo "Forbidden global variables in "$(1)":"; \
+		$$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders; false; \
+		else true; fi
+endef
+
+###############################################################################
+# romstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -180,21 +197,11 @@ endif
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
-romstage-oformat=elf32-i386
+$(eval $(call early_x86_stage,romstage,elf32-i386))
 else
-romstage-oformat=elf64-x86-64
+$(eval $(call early_x86_stage,romstage,elf64-x86-64))
 endif
 
-$(objcbfs)/romstage.debug: $$(romstage-objs) $$(romstage-libs)
-	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(obj)/arch/x86/memlayout.romstage.ld --oformat $(romstage-oformat)
-	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
-	grep -v "Empty loadable segment detected" && \
-	if [ -n "`$(NM_romstage) $(objcbfs)/romstage_null.offenders 2>/dev/null`" ]; then \
-		echo "Forbidden global variables in romstage:"; \
-		$(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \
-		else true; fi
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
new file mode 100644
index 0000000..c23d177
--- /dev/null
+++ b/src/arch/x86/assembly_entry.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The assembly.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/assembly.inc>
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
deleted file mode 100644
index b19b954..0000000
--- a/src/arch/x86/romstage.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file assembles the start of the romstage program by the order of the
- * includes. Thus, it's extremely important that one pays very careful
- * attention to the order of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/32bit/entry32.inc>
-#include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
-
-/*
- * The romstage.inc is generated based on the requirements of the mainboard.
- * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
- * processed by ROMCC and added. In non-ROMCC boards the chipsets'
- * cache-as-ram setup files would be here.
- */
-#include <generated/romstage.inc>


From gerrit at coreboot.org  Tue Sep 29 20:19:27 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Tue, 29 Sep 2015 20:19:27 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: x86: prepare
	cache-as-ram to allow multiple stages
References: <I15e9f6b0c632ee5a2369da0709535d6cb0d94f61+0@gerrit.coreboot.org>
Message-ID: <I15e9f6b0c632ee5a2369da0709535d6cb0d94f61+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11740

-gerrit

commit aa3e6ab0b12ce7b6fee96c8655d81fa682fa2c8f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 24 12:18:07 2015 -0500

    x86: prepare cache-as-ram to allow multiple stages
    
    In order to do a verification of romstage on x86 one needs to
    run verstage which verifies romstage (and the memory init code).
    However, x86 doesn't have SRAM like every other modern SoC so
    managing the cache-as-ram region is especially critical.
    
    First move all of the "shared" objects to the beginning of
    the .car.data section. This change then ensures that each stage
    using car.ld to link has the same consistent view of the addresses
    of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can
    be unique per stage. However, these variables are expected to have
    a value of zero at the start of each stage. In order to allow a
    stage to provide those semantics outside of the initial cache-as-arm
    setup routine add _car_global_start and _car_global_end symbols.
    Those symbols can be used to clear the CAR_GLOBALs for that stage.
    
    Note that the timestamp region can't be moved out similarly to the
    pre-ram cbmem console because the object storage of the timestamp
    cache is used *after* cache-as-ram is torn down to indicate if the
    cache should be used or not. Therefore, that timestamp needs to
    migrated to ram. A logic change in src/lib/timestamp.c could
    alleviate this requirement, but that task wasn't tackled in this
    patch.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/car.ld | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index c30c802..5da9dcf 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -22,15 +22,29 @@
 /* This file is included inside a SECTIONS block */
 . = CONFIG_DCACHE_RAM_BASE;
 .car.data . (NOLOAD) : {
+	/* The pre-ram cbmem console as well as the timestamp region are fixed
+	 * in size. Therefore place them at the beginning .car.data section
+	 * so that multiple stages (romstage and verstage) have a consistent
+	 * link address of these shared objects. */
+	PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	_car_data_start = .;
+	/* The timestamp implementation relies on this storage to be around
+	 * after migration. One of the fields indicates not to use it as the
+	 * backing store once cbmem comes online. Therefore, this data needs
+	 * to reside in the migrated area (between _car_data_start and
+	 * _car_data_end). */
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
 	TIMESTAMP(., 0x100)
 #endif
+	/* _car_global_start and _car_global_end provide symbols to per-stage
+	 * variables that are not shared like the timestamp and the pre-ram
+	 * cbmem console. This is useful for clearing this area on a per-stage
+	 * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
+	_car_global_start = .;
 	*(.car.global_data);
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_car_global_end = .;
 	_car_data_end = .;
-
-	PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 }
 
 /* Global variables are not allowed in romstage
@@ -48,4 +62,4 @@
 	*(.sbss.*)
 }
 
-_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
+_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");


From gerrit at coreboot.org  Tue Sep 29 20:54:23 2015
From: gerrit at coreboot.org (Martin Roth (martinroth@google.com))
Date: Tue, 29 Sep 2015 20:54:23 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: Add EM100
	'hyper term' spi console support in ramstage & smm
References: <Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b+0@gerrit.coreboot.org>
Message-ID: <Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b+1@gerrit.coreboot.org>

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11743

-gerrit

commit cb6af20fab9ab254b673a41334b8677919fc1d21
Author: Martin Roth <martinroth at google.com>
Date:   Mon Sep 28 15:27:24 2015 -0600

    Add EM100 'hyper term' spi console support in ramstage & smm
    
    The EM100Pro allows the debug console to be sent over the SPI bus.
    This is not yet working in romstage due to the use of static variables
    in the SPI driver code.  It is also not working on chipsets that have
    SPI write buffers of less than 10 characters due to the 9 byte
    command/header length specified by the EM100 protocol.
    
    While this currently works only with the EM100, it seems like it would
    be useful on any logic analyzer with SPI debug - just filter on command
    bytes of 0x11.
    
    Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b
    Signed-off-by: Martin Roth <martinroth at google.com>
---
 src/Kconfig                             |  1 +
 src/console/Kconfig                     |  8 ++++
 src/console/console.c                   |  3 ++
 src/drivers/spi/Kconfig                 |  4 ++
 src/drivers/spi/Makefile.inc            |  5 +++
 src/drivers/spi/spiconsole.c            | 71 ++++++++++++++++++++++++++++++++
 src/include/console/spi.h               | 72 +++++++++++++++++++++++++++++++++
 src/soc/intel/baytrail/Kconfig          |  1 +
 src/soc/intel/braswell/Kconfig          |  1 +
 src/soc/intel/broadwell/Kconfig         |  1 +
 src/soc/intel/fsp_baytrail/Kconfig      |  1 +
 src/southbridge/intel/lynxpoint/Kconfig |  1 +
 12 files changed, 169 insertions(+)

diff --git a/src/Kconfig b/src/Kconfig
index 2c75750..868ed08 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -777,6 +777,7 @@ config DEBUG_SMI
 	bool "Output verbose SMI debug messages"
 	default n
 	depends on HAVE_SMI_HANDLER
+	select SPI_FLASH_SMM if SPI_CONSOLE
 	help
 	  This option enables additional SMI related debug messages.
 
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 7d6fa0e..d9a5521 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -211,6 +211,14 @@ config CONSOLE_QEMU_DEBUGCON_PORT
 	depends on CONSOLE_QEMU_DEBUGCON
 	default 0x402
 
+config SPI_CONSOLE
+	bool "SPI debug console output"
+	depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH
+	help
+	  Enable support for the debug console on the dediprog EM100Pro.
+	  This is currently working only in ramstage due to how the spi
+	  drivers are written.
+
 choice
 	prompt "Default console log level"
 	default DEFAULT_CONSOLE_LOGLEVEL_8
diff --git a/src/console/console.c b/src/console/console.c
index 00c0f1c..855de64 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -24,6 +24,7 @@
 #include <console/streams.h>
 #include <console/uart.h>
 #include <console/usb.h>
+#include <console/spi.h>
 #include <rules.h>
 
 void console_hw_init(void)
@@ -35,6 +36,7 @@ void console_hw_init(void)
 	__uart_init();
 	__ne2k_init();
 	__usbdebug_init();
+	__spiconsole_init();
 }
 
 void console_tx_byte(unsigned char byte)
@@ -54,6 +56,7 @@ void console_tx_byte(unsigned char byte)
 	__uart_tx_byte(byte);
 	__ne2k_tx_byte(byte);
 	__usb_tx_byte(byte);
+	__spiconsole_tx_byte(byte);
 }
 
 void console_tx_flush(void)
diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig
index 4052bb4..dedb88f 100644
--- a/src/drivers/spi/Kconfig
+++ b/src/drivers/spi/Kconfig
@@ -137,3 +137,7 @@ config SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
 	  to the chip on MOSI and data is received on both MOSI and MISO.
 
 endif # SPI_FLASH
+
+config HAVE_SPI_CONSOLE_SUPPORT
+	def_bool n
+
diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc
index ade34a2..6697c70 100644
--- a/src/drivers/spi/Makefile.inc
+++ b/src/drivers/spi/Makefile.inc
@@ -1,5 +1,10 @@
 # SPI flash driver interface
 
+ifeq ($(CONFIG_SPI_CONSOLE),y)
+ramstage-y += spiconsole.c
+smm-$(CONFIG_DEBUG_SMI) += spiconsole.c
+endif
+
 ifeq ($(CONFIG_COMMON_CBFS_SPI_WRAPPER),y)
 bootblock-y += spi_flash.c
 bootblock-$(CONFIG_SPI_FLASH_EON) += eon.c
diff --git a/src/drivers/spi/spiconsole.c b/src/drivers/spi/spiconsole.c
new file mode 100644
index 0000000..39a574c
--- /dev/null
+++ b/src/drivers/spi/spiconsole.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <spi-generic.h>
+#include <spi_flash.h>
+#include <console/spi.h>
+
+void spiconsole_init(void) {
+	spi_init();
+	return;
+}
+
+/*
+ * The EM100 'hyper terminal' specification defines a header of 9 characters.
+ * Because of this, devices with a spi_crop_chunk of less than 10 characters
+ * can't be supported by this standard.
+ *
+ * To add support in romstage, the static struct here and the ones used by
+ * spi_xfer will need to be modified - removed, or mapped into cbmem.
+ *
+ * Because the Dediprog software expects strings, not single characters, and
+ * because of the header overhead, this builds up a buffer to send.
+ */
+void spiconsole_tx_byte(unsigned char c) {
+	static struct em100_msg msg = {
+		.header.spi_command = EM100_DEDICATED_CMD,
+		.header.em100_command = EM100_UFIFO_CMD,
+		.header.msg_signature = EM100_MSG_SIGNATURE,
+		.header.msg_type = EM100_MSG_ASCII,
+		.header.msg_length = 0
+	};
+
+	/* Verify the spi buffer is big enough to send even a single byte */
+	if (spi_crop_chunk(0,MAX_MSG_LENGTH) <
+			sizeof(struct em100_msg_header) + 1)
+		return;
+
+	msg.data[msg.header.msg_length] = c;
+	msg.header.msg_length++;
+
+	/* Send the data on newline or when the max spi length is reached */
+	if (c == '\n' || (sizeof(struct em100_msg_header) +
+			msg.header.msg_length == spi_crop_chunk(0,
+			MAX_MSG_LENGTH))) {
+		struct spi_slave spi = {.rw = SPI_READ_FLAG};
+
+		spi_xfer(&spi, &msg, sizeof(struct em100_msg_header) +
+				msg.header.msg_length, NULL, 0);
+
+		msg.header.msg_length = 0;
+	}
+
+	return;
+}
+
diff --git a/src/include/console/spi.h b/src/include/console/spi.h
new file mode 100644
index 0000000..c47fec5
--- /dev/null
+++ b/src/include/console/spi.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef CONSOLE_SPI_H
+#define CONSOLE_SPI_H 1
+
+#include <rules.h>
+#include <stdint.h>
+
+void spiconsole_init(void);
+void spiconsole_tx_byte(unsigned char c);
+
+#define __CONSOLE_SPI_ENABLE__	CONFIG_SPI_CONSOLE && \
+	(ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI))
+
+#if __CONSOLE_SPI_ENABLE__
+static inline void __spiconsole_init(void)	{ spiconsole_init(); }
+static inline void __spiconsole_tx_byte(u8 data)	{ spiconsole_tx_byte(data); }
+#else
+static inline void __spiconsole_init(void)	{}
+static inline void __spiconsole_tx_byte(u8 data)	{}
+#endif /* __CONSOLE_SPI_ENABLE__ */
+
+#define MAX_MSG_LENGTH	128
+
+#define EM100_DEDICATED_CMD	0x11
+#define EM100_UFIFO_CMD		0xC0
+#define EM100_MSG_SIGNATURE	0x47364440
+
+enum em100_message_types {
+	EM100_MSG_CHECKPOINT_1B = 0x01,
+	EM100_MSG_CHECKPOINT_2B,
+	EM100_MSG_CHECKPOINT_4B,
+	EM100_MSG_HEX,
+	EM100_MSG_ASCII,
+	EM100_MSG_TIMESTAMP,
+	EM100_MSG_LOOKUP
+};
+
+struct em100_msg_header {
+	uint8_t		spi_command;
+	uint8_t		reserved;
+	uint8_t		em100_command;
+	uint32_t	msg_signature;
+	uint8_t		msg_type;
+	uint8_t		msg_length;
+} __attribute__ ((packed));
+
+struct em100_msg {
+	struct em100_msg_header header;
+	char data[MAX_MSG_LENGTH];
+} __attribute__ ((packed));
+
+
+
+#endif /* CONSOLE_SPI_H */
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 921f568..8de32de 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select SOC_INTEL_COMMON
 	select HAVE_INTEL_FIRMWARE
+	select HAVE_SPI_CONSOLE_SUPPORT
 
 config BOOTBLOCK_CPU_INIT
 	string
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index f76b9b2..5a41056 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select USE_GENERIC_FSP_CAR_INC
 	select HAVE_INTEL_FIRMWARE
+	select HAVE_SPI_CONSOLE_SUPPORT
 
 config BOOTBLOCK_CPU_INIT
 	string
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 6561fe2..33644e8 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON
 	select HAVE_INTEL_FIRMWARE
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+	select HAVE_SPI_CONSOLE_SUPPORT
 
 config BOOTBLOCK_CPU_INIT
 	string
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index d51a238..cc09e1f 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select HAVE_INTEL_FIRMWARE
+	select HAVE_SPI_CONSOLE_SUPPORT
 
 config SOC_INTEL_FSP_BAYTRAIL_MD
 	bool
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 3c8ae11..3221cff 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
 	select HAVE_INTEL_FIRMWARE
+	select HAVE_SPI_CONSOLE_SUPPORT
 
 config INTEL_LYNXPOINT_LP
 	bool


From gerrit at coreboot.org  Tue Sep 29 20:54:55 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 29 Sep 2015 20:54:55 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel/fsp1.0:
	Get size of microcode during build time
References: <I868f02b0cc03af12464a6a87c59761c200eb2502+0@gerrit.coreboot.org>
Message-ID: <E1Zh1vL-00067p-9O@mail.coreboot.org>

the following patch was just integrated into master:
commit c947fee4791a8274ebb9128c43b0052d5cabe1b4
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Sep 25 07:54:59 2015 +0200

    intel/fsp1.0: Get size of microcode during build time
    
    Avoid specifying the size of the microcode in microcode_size.h.
    Instead, the size will be determined during build time and
    microcode_size.h will be generated. This way, the size does
    not need to be adjusted by hand.
    
    Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
    Reviewed-on: http://review.coreboot.org/11709
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/11709 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 29 22:35:50 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 29 Sep 2015 22:35:50 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: chromeos:
	vboot-related functions move to common vboot code
References: <I52f8a408645566dac0a2100e819c8ed5d3d88ea5+0@gerrit.coreboot.org>
Message-ID: <E1Zh3V1-00078o-1o@mail.coreboot.org>

the following patch was just integrated into master:
commit 115360fdb36be77e86dfa1208f3c1e3dca649685
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:41:14 2015 +0200

    chromeos: vboot-related functions move to common vboot code
    
    This moves a few vboot-prefixed functions that were defined in chromeos.c to
    vboot_common.c, since those are only relevant to vboot and depend on the vboot
    handoff data. This allows more separation between CONFIG_CHROMEOS and what
    CONFIG_CHROMEOS selects, so that each separate option (such as
    CONFIG_VBOOT_VERIFY_FIRMWARE) can be enabled separately.
    
    Thus, the actual definitions of these functions will only be declared when
    CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling
    vboot_skip_display_init in bootmode was also adapted.
    
    Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
    Reviewed-on: http://review.coreboot.org/11497
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11497 for details.

-gerrit


From gerrit at coreboot.org  Tue Sep 29 23:15:12 2015
From: gerrit at coreboot.org (Maxime de Roucy (maxime.deroucy@gmail.com))
Date: Tue, 29 Sep 2015 23:15:12 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: pcengines/apu1:
	Add CMOS/NVRAM support
References: <I4864923166efb200882d895c572d1ee060c71951+0@gerrit.coreboot.org>
Message-ID: <I4864923166efb200882d895c572d1ee060c71951+3@gerrit.coreboot.org>

Maxime de Roucy (maxime.deroucy at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730

-gerrit

commit 956be703463a66bd4d153c31888a67ba7dd8cc5c
Author: Maxime de Roucy <maxime.deroucy at gmail.com>
Date:   Sun Sep 27 15:45:35 2015 +0200

    pcengines/apu1: Add CMOS/NVRAM support
    
    Inspired by the Sage source code (itself from coreboot).
    
    Change-Id: I4864923166efb200882d895c572d1ee060c71951
    Signed-off-by: Maxime de Roucy <maxime.deroucy at gmail.com>
---
 src/mainboard/pcengines/apu1/Kconfig      |  2 ++
 src/mainboard/pcengines/apu1/cmos.default |  5 ++++
 src/mainboard/pcengines/apu1/cmos.layout  | 44 +++++++++++++++++++++++++++++++
 3 files changed, 51 insertions(+)

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index b1b19c9..7ea1821 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 	select BOARD_ROMSIZE_KB_2048
 	select SPD_CACHE
 
diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default
new file mode 100644
index 0000000..bca3115
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.default
@@ -0,0 +1,5 @@
+last_boot=Fallback
+boot_option=Fallback
+multi_core=Enable
+debug_level=Emerg
+baud_rate=115200
diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
new file mode 100644
index 0000000..6172f35
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.layout
@@ -0,0 +1,44 @@
+entries
+
+# <start-bit> <bit-length> <config> <config-id> <parameter-name>
+0             384          r        0           reserved_memory
+384           4            r        0           reboot_bits
+388           1            e        2           last_boot
+389           1            e        2           boot_option
+390           1            e        1           multi_core
+391           3            e        3           baud_rate
+394           4            e        4           debug_level
+398           16           h        0           check_sum
+
+enumerations
+
+#<config-id>  <value>  <label>
+## for multi_core
+1             0        Enable
+1             1        Disable
+## for last_boot, boot_option
+2             0        Fallback
+2             1        Normal
+## for baud_rate
+3             0        115200
+3             1        57600
+3             2        38400
+3             3        19200
+3             4        9600
+3             5        4800
+3             6        2400
+3             7        1200
+## for debug_level
+4             0        Emerg
+4             1        Alert
+4             2        Crit
+4             3        Err
+4             4        Warning
+4             5        Notice
+4             6        Info
+4             7        Debug
+4             8        Spew
+
+checksums
+
+checksum 389 397 398


From gerrit at coreboot.org  Tue Sep 29 23:41:05 2015
From: gerrit at coreboot.org (Maxime de Roucy (maxime.deroucy@gmail.com))
Date: Tue, 29 Sep 2015 23:41:05 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: pcengines/apu1:
	Add CMOS/NVRAM support
References: <I4864923166efb200882d895c572d1ee060c71951+0@gerrit.coreboot.org>
Message-ID: <I4864923166efb200882d895c572d1ee060c71951+4@gerrit.coreboot.org>

Maxime de Roucy (maxime.deroucy at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730

-gerrit

commit e93a8f5531a1ce0eff56de6b6b664d8c65099759
Author: Maxime de Roucy <maxime.deroucy at gmail.com>
Date:   Sun Sep 27 15:45:35 2015 +0200

    pcengines/apu1: Add CMOS/NVRAM support
    
    Inspired by the Sage source code (itself from coreboot).
    
    Change-Id: I4864923166efb200882d895c572d1ee060c71951
    Signed-off-by: Maxime de Roucy <maxime.deroucy at gmail.com>
---
 src/mainboard/pcengines/apu1/Kconfig      |  2 ++
 src/mainboard/pcengines/apu1/cmos.default |  5 ++++
 src/mainboard/pcengines/apu1/cmos.layout  | 46 +++++++++++++++++++++++++++++++
 3 files changed, 53 insertions(+)

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index b1b19c9..7ea1821 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 	select BOARD_ROMSIZE_KB_2048
 	select SPD_CACHE
 
diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default
new file mode 100644
index 0000000..bca3115
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.default
@@ -0,0 +1,5 @@
+last_boot=Fallback
+boot_option=Fallback
+multi_core=Enable
+debug_level=Emerg
+baud_rate=115200
diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
new file mode 100644
index 0000000..0cf145f
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.layout
@@ -0,0 +1,46 @@
+entries
+
+# <start-bit> <bit-length> <config> <config-id> <parameter-name>
+0             384          r        0           reserved_memory
+384           4            r        0           reboot_bits
+388           1            e        2           last_boot
+# leave 3 bits to make checksummed area start byte-aligned
+392           1            e        2           boot_option
+393           1            e        1           multi_core
+394           3            e        3           baud_rate
+397           4            e        4           debug_level
+# leave 7 bits to make checksummed area end byte-aligned
+408           16           h        0           check_sum
+
+enumerations
+
+#<config-id>  <value>  <label>
+## for multi_core
+1             0        Enable
+1             1        Disable
+## for last_boot, boot_option
+2             0        Fallback
+2             1        Normal
+## for baud_rate
+3             0        115200
+3             1        57600
+3             2        38400
+3             3        19200
+3             4        9600
+3             5        4800
+3             6        2400
+3             7        1200
+## for debug_level
+4             0        Emerg
+4             1        Alert
+4             2        Crit
+4             3        Err
+4             4        Warning
+4             5        Notice
+4             6        Info
+4             7        Debug
+4             8        Spew
+
+checksums
+
+checksum 392 407 408


From gerrit at coreboot.org  Tue Sep 29 23:47:37 2015
From: gerrit at coreboot.org (Maxime de Roucy (maxime.deroucy@gmail.com))
Date: Tue, 29 Sep 2015 23:47:37 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: pcengines/apu1:
	Add CMOS/NVRAM support
References: <I4864923166efb200882d895c572d1ee060c71951+0@gerrit.coreboot.org>
Message-ID: <I4864923166efb200882d895c572d1ee060c71951+5@gerrit.coreboot.org>

Maxime de Roucy (maxime.deroucy at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730

-gerrit

commit 2fb229c8038bd3ee824f9f2f9f12a2f1fe67acfc
Author: Maxime de Roucy <maxime.deroucy at gmail.com>
Date:   Sun Sep 27 15:45:35 2015 +0200

    pcengines/apu1: Add CMOS/NVRAM support
    
    Inspired by the Sage source code (itself from coreboot).
    
    Change-Id: I4864923166efb200882d895c572d1ee060c71951
    Signed-off-by: Maxime de Roucy <maxime.deroucy at gmail.com>
---
 src/mainboard/pcengines/apu1/Kconfig      |  2 ++
 src/mainboard/pcengines/apu1/cmos.default |  5 ++++
 src/mainboard/pcengines/apu1/cmos.layout  | 46 +++++++++++++++++++++++++++++++
 3 files changed, 53 insertions(+)

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index b1b19c9..7ea1821 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 	select BOARD_ROMSIZE_KB_2048
 	select SPD_CACHE
 
diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default
new file mode 100644
index 0000000..35e0365
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.default
@@ -0,0 +1,5 @@
+last_boot=Fallback
+boot_option=Fallback
+multi_core=Enable
+debug_level=Spew
+baud_rate=115200
diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
new file mode 100644
index 0000000..0cf145f
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/cmos.layout
@@ -0,0 +1,46 @@
+entries
+
+# <start-bit> <bit-length> <config> <config-id> <parameter-name>
+0             384          r        0           reserved_memory
+384           4            r        0           reboot_bits
+388           1            e        2           last_boot
+# leave 3 bits to make checksummed area start byte-aligned
+392           1            e        2           boot_option
+393           1            e        1           multi_core
+394           3            e        3           baud_rate
+397           4            e        4           debug_level
+# leave 7 bits to make checksummed area end byte-aligned
+408           16           h        0           check_sum
+
+enumerations
+
+#<config-id>  <value>  <label>
+## for multi_core
+1             0        Enable
+1             1        Disable
+## for last_boot, boot_option
+2             0        Fallback
+2             1        Normal
+## for baud_rate
+3             0        115200
+3             1        57600
+3             2        38400
+3             3        19200
+3             4        9600
+3             5        4800
+3             6        2400
+3             7        1200
+## for debug_level
+4             0        Emerg
+4             1        Alert
+4             2        Crit
+4             3        Err
+4             4        Warning
+4             5        Notice
+4             6        Info
+4             7        Debug
+4             8        Spew
+
+checksums
+
+checksum 392 407 408


From gerrit at coreboot.org  Wed Sep 30 01:24:10 2015
From: gerrit at coreboot.org (WANG Siyuan (wangsiyuanbuaa@gmail.com))
Date: Wed, 30 Sep 2015 01:24:10 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: add
	README
References: <Ie8b761096fd1850afb9363ebb761aa4992b47643+0@gerrit.coreboot.org>
Message-ID: <Ie8b761096fd1850afb9363ebb761aa4992b47643+3@gerrit.coreboot.org>

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11737

-gerrit

commit a000c294cd06c17ad8945ee7064e17de9d76f32d
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Tue Sep 29 11:12:03 2015 +0800

    AMD Bettong: add README
    
    AMD provide stable Bettong code in github.
    
    Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/mainboard/amd/bettong/README | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/src/mainboard/amd/bettong/README b/src/mainboard/amd/bettong/README
new file mode 100644
index 0000000..b13c985
--- /dev/null
+++ b/src/mainboard/amd/bettong/README
@@ -0,0 +1,24 @@
+coreboot is changing all the time and the patches are reabsed when pushed to
+community, so it is a little difficult to provide stable Bettong code.
+From now on, AMD provides source code which is validated by QA team.
+The code is pushed to github https://github.com/BTDC/coreboot
+The version is identified by a tag. All the changes will be pushed to coreboot
+community.
+
+=====
+Version: TCMEF1F0:
+Changes from last version:
+1. Fix external graphics issue.
+2. Add board ID support.
+3. Support DDR4.
+4. Support SD 2.0.
+5. Fix Windows 7 S4 issue.
+6. Add GPIO, I2C and UART support.
+7. Fix the interrupt routine.
+8. Restruct PCI interrupt table (C00/C01).
+9. Fix DSDT issue.
+10. Fix the PCIe lane map.
+11. Lower the TOM to give more MMIO space.
+12. Add USB device.
+13. Set the USB3 port as unremoveable.
+14. Update AGESA to CarrizoPI 1.1.0.1.


From gerrit at coreboot.org  Wed Sep 30 01:34:22 2015
From: gerrit at coreboot.org (WANG Siyuan (wangsiyuanbuaa@gmail.com))
Date: Wed, 30 Sep 2015 01:34:22 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: add
	README
References: <Ie8b761096fd1850afb9363ebb761aa4992b47643+0@gerrit.coreboot.org>
Message-ID: <Ie8b761096fd1850afb9363ebb761aa4992b47643+4@gerrit.coreboot.org>

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11737

-gerrit

commit 4e4ec380acc318f65d21dea776ccd42c4536df1a
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Tue Sep 29 11:12:03 2015 +0800

    AMD Bettong: add README
    
    This is the initial version of README.
    AMD provides stable Bettong code in github. Add the link and bug fixed
    list to README.
    
    Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/mainboard/amd/bettong/README | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/src/mainboard/amd/bettong/README b/src/mainboard/amd/bettong/README
new file mode 100644
index 0000000..d834af4
--- /dev/null
+++ b/src/mainboard/amd/bettong/README
@@ -0,0 +1,25 @@
+coreboot is changing all the time and the patches are reabsed when pushed to
+community, so it is a little difficult to provide stable Bettong code.
+From now on, AMD provides source code which is validated by QA team.
+The code is pushed to github https://github.com/BTDC/coreboot
+The version is identified by a tag. All the changes will be pushed to coreboot
+community.
+
+=====
+Version: TCMEF1F0        Release Date: 09/29/2015
+
+Changes from last version:
+1. Fix external graphics issue.
+2. Add board ID support.
+3. Support DDR4.
+4. Support SD 2.0.
+5. Fix Windows 7 S4 issue.
+6. Add GPIO, I2C and UART support.
+7. Fix the interrupt routine.
+8. Restruct PCI interrupt table (C00/C01).
+9. Fix DSDT issue.
+10. Fix the PCIe lane map.
+11. Lower the TOM to give more MMIO space.
+12. Add USB device.
+13. Set the USB3 port as unremoveable.
+14. Update AGESA to CarrizoPI 1.1.0.1.


From gerrit at coreboot.org  Wed Sep 30 01:39:46 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Wed, 30 Sep 2015 01:39:46 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+9@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit a669c130714df138a1194464d52107b1104f4539
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                               | 23 ++++++-------
 src/cpu/amd/model_10xxx/Makefile.inc               |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c           |  3 --
 src/cpu/amd/model_fxx/Makefile.inc                 |  2 +-
 src/cpu/intel/ep80579/Makefile.inc                 |  2 --
 src/cpu/intel/ep80579/microcode_blob.c             |  8 -----
 src/cpu/intel/fsp_model_206ax/Kconfig              |  5 ---
 src/cpu/intel/fsp_model_206ax/Makefile.inc         |  9 ++---
 src/cpu/intel/fsp_model_206ax/microcode_blob.c     | 22 -------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h     | 33 -------------------
 src/cpu/intel/fsp_model_206ax/microcode_size.h     |  7 ----
 src/cpu/intel/fsp_model_406dx/Kconfig              |  4 ---
 src/cpu/intel/fsp_model_406dx/Makefile.inc         | 10 ++----
 src/cpu/intel/fsp_model_406dx/microcode_blob.c     | 29 -----------------
 src/cpu/intel/fsp_model_406dx/microcode_size.h     |  7 ----
 src/cpu/intel/haswell/Makefile.inc                 |  5 +--
 src/cpu/intel/haswell/microcode_blob.c             | 30 -----------------
 src/cpu/intel/model_1067x/Makefile.inc             |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c         |  3 --
 src/cpu/intel/model_106cx/Makefile.inc             |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c         |  3 --
 src/cpu/intel/model_2065x/Makefile.inc             |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c         | 22 -------------
 src/cpu/intel/model_206ax/Makefile.inc             |  3 +-
 src/cpu/intel/model_206ax/microcode_blob.c         | 23 -------------
 src/cpu/intel/model_65x/Makefile.inc               |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c           |  3 --
 src/cpu/intel/model_67x/Makefile.inc               |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c           |  3 --
 src/cpu/intel/model_68x/Makefile.inc               |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c           |  3 --
 src/cpu/intel/model_69x/Makefile.inc               |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c           |  3 --
 src/cpu/intel/model_6bx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6dx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6ex/Makefile.inc               |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c           |  3 --
 src/cpu/intel/model_6fx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6xx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c           |  3 --
 src/cpu/intel/model_f0x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f1x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f2x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f3x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c           |  3 --
 src/cpu/intel/model_f4x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c           |  3 --
 src/cpu/via/nano/Makefile.inc                      |  4 +--
 src/soc/intel/baytrail/Makefile.inc                |  3 +-
 src/soc/intel/baytrail/microcode/Makefile.inc      |  1 -
 src/soc/intel/baytrail/microcode/microcode_blob.c  |  3 --
 src/soc/intel/braswell/Makefile.inc                |  3 +-
 src/soc/intel/braswell/microcode/Makefile.inc      |  2 --
 src/soc/intel/braswell/microcode/microcode_blob.c  | 22 -------------
 src/soc/intel/broadwell/Makefile.inc               |  3 +-
 src/soc/intel/broadwell/microcode/Makefile.inc     |  1 -
 src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
 src/soc/intel/fsp_baytrail/Makefile.inc            |  3 +-
 src/soc/intel/fsp_baytrail/microcode/Makefile.inc  | 26 ---------------
 .../intel/fsp_baytrail/microcode/microcode_blob.c  | 38 ----------------------
 .../intel/fsp_baytrail/microcode/microcode_size.h  |  6 ----
 src/soc/intel/skylake/Makefile.inc                 |  3 +-
 src/soc/intel/skylake/microcode/Makefile.inc       |  2 --
 src/soc/intel/skylake/microcode/microcode_blob.c   | 24 --------------
 70 files changed, 50 insertions(+), 450 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_size.h b/src/cpu/intel/fsp_model_206ax/microcode_size.h
deleted file mode 100644
index 0b0364c..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_size.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	#define MICROCODE_REGION_LENGTH 0xC000
-#elif IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	#define MICROCODE_REGION_LENGTH 0x2800
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_size.h b/src/cpu/intel/fsp_model_406dx/microcode_size.h
deleted file mode 100644
index b638ae5..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_size.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-	#define MICROCODE_REGION_LENGTH 0x14400
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-	#define MICROCODE_REGION_LENGTH 0x14800
-#endif
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 085a45e..edc77af 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -53,6 +52,8 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index e5ac640..426f359 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -51,6 +50,8 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index fdd064d..a9004ac 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -73,6 +72,8 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 39a253f..7370830 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
 
 ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -59,6 +58,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
 ramstage-y += placeholders.c
 ramstage-y += i2c.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
-		/*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
-	#include "M0230672228.h"  // M0230672: Bay Trail "Super SKU" B0/B1
-	#include "M0130673322.h"  // M0130673: Bay Trail I B2 / B3
-	#include "M0130679901.h"  // M0130679: Bay Trail I D0
-#else
-	/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
-	#include "M0C30678829.h"  // M0C30678: Bay Trail M D Stepping
-#endif	/* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif	/* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	#define MICROCODE_REGION_LENGTH 0x30000
-#else
-	#define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index d6bc839..b80767b 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-


From gerrit at coreboot.org  Wed Sep 30 02:34:17 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 02:34:17 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: prepare
	cache-as-ram to allow multiple stages
References: <I15e9f6b0c632ee5a2369da0709535d6cb0d94f61+0@gerrit.coreboot.org>
Message-ID: <I15e9f6b0c632ee5a2369da0709535d6cb0d94f61+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11740

-gerrit

commit 5d05f04a589e4a32067edb251cd20f1535607798
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 24 12:18:07 2015 -0500

    x86: prepare cache-as-ram to allow multiple stages
    
    In order to do a verification of romstage on x86 one needs to
    run verstage which verifies romstage (and the memory init code).
    However, x86 doesn't have SRAM like every other modern SoC so
    managing the cache-as-ram region is especially critical.
    
    First move all of the "shared" objects to the beginning of
    the .car.data section. This change then ensures that each stage
    using car.ld to link has the same consistent view of the addresses
    of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can
    be unique per stage. However, these variables are expected to have
    a value of zero at the start of each stage. In order to allow a
    stage to provide those semantics outside of the initial cache-as-arm
    setup routine add _car_global_start and _car_global_end symbols.
    Those symbols can be used to clear the CAR_GLOBALs for that stage.
    
    Note that the timestamp region can't be moved out similarly to the
    pre-ram cbmem console because the object storage of the timestamp
    cache is used *after* cache-as-ram is torn down to indicate if the
    cache should be used or not. Therefore, that timestamp needs to
    migrated to ram. A logic change in src/lib/timestamp.c could
    alleviate this requirement, but that task wasn't tackled in this
    patch.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/car.ld | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index c30c802..5da9dcf 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -22,15 +22,29 @@
 /* This file is included inside a SECTIONS block */
 . = CONFIG_DCACHE_RAM_BASE;
 .car.data . (NOLOAD) : {
+	/* The pre-ram cbmem console as well as the timestamp region are fixed
+	 * in size. Therefore place them at the beginning .car.data section
+	 * so that multiple stages (romstage and verstage) have a consistent
+	 * link address of these shared objects. */
+	PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	_car_data_start = .;
+	/* The timestamp implementation relies on this storage to be around
+	 * after migration. One of the fields indicates not to use it as the
+	 * backing store once cbmem comes online. Therefore, this data needs
+	 * to reside in the migrated area (between _car_data_start and
+	 * _car_data_end). */
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
 	TIMESTAMP(., 0x100)
 #endif
+	/* _car_global_start and _car_global_end provide symbols to per-stage
+	 * variables that are not shared like the timestamp and the pre-ram
+	 * cbmem console. This is useful for clearing this area on a per-stage
+	 * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
+	_car_global_start = .;
 	*(.car.global_data);
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_car_global_end = .;
 	_car_data_end = .;
-
-	PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 }
 
 /* Global variables are not allowed in romstage
@@ -48,4 +62,4 @@
 	*(.sbss.*)
 }
 
-_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
+_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");


From gerrit at coreboot.org  Wed Sep 30 02:34:22 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 02:34:22 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: x86: provide
	common macro for linking early stages
References: <I12f4872df09fff6715829de68fc374e230350c2e+0@gerrit.coreboot.org>
Message-ID: <I12f4872df09fff6715829de68fc374e230350c2e+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11739

-gerrit

commit 19f8af68692e7915f7b595a2bcae95273a881f01
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 14:54:25 2015 -0500

    x86: provide common macro for linking early stages
    
    In order to support verstage on x86 one needs to link verstage
    like romstage since it needs all the cache-as-ram goodies. Therefore,
    provide a macro that one can invoke that provides the necessary
    recipes for linking that particular stage in such an environment.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I12f4872df09fff6715829de68fc374e230350c2e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/Makefile.inc     | 49 ++++++++++++++++++++++++-------------------
 src/arch/x86/assembly_entry.S | 37 ++++++++++++++++++++++++++++++++
 src/arch/x86/romstage.S       | 37 --------------------------------
 3 files changed, 65 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 1779099..f16edcd 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -115,27 +115,44 @@ endif
 endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ###############################################################################
-# romstage
+# common support for early assembly includes
 ###############################################################################
 
-ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
-
-romstage-y += memlayout.ld
-
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
 # into a single generated file.
 crt0s = $(cpu_incs-y)
 
-$(objgenerated)/romstage.inc: $$(crt0s)
+$(objgenerated)/assembly.inc: $$(crt0s)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
 
+define early_x86_stage
+# $1 stage name
+# $2 oformat
+$(1)-y += memlayout.ld
 # Add the assembly file that pulls in the rest of the dependencies in
-# the right order. Make sure the auto generated romstage.inc is a proper
+# the right order. Make sure the auto generated assembly.inc is a proper
 # dependency.
-romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(1)-y += assembly_entry.S
+$$(obj)/arch/x86/assembly_entry.$(1).o: $(objgenerated)/assembly.inc
+
+$$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs)
+	@printf "    LINK       $$(subst $$(obj)/,,$$(@))\n"
+	$$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $$(obj)/arch/x86/memlayout.$(1).ld --oformat $(2)
+	LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders 2>&1 | \
+	grep -v "Empty loadable segment detected" && \
+	$$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders | grep -q ""; if [ $$$$? -eq 0 ]; then \
+		echo "Forbidden global variables in "$(1)":"; \
+		$$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders; false; \
+		else true; fi
+endef
+
+###############################################################################
+# romstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
 ifneq ($(CONFIG_ROMCC),y)
 
@@ -180,21 +197,11 @@ endif
 romstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
-romstage-oformat=elf32-i386
+$(eval $(call early_x86_stage,romstage,elf32-i386))
 else
-romstage-oformat=elf64-x86-64
+$(eval $(call early_x86_stage,romstage,elf64-x86-64))
 endif
 
-$(objcbfs)/romstage.debug: $$(romstage-objs) $$(romstage-libs)
-	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(obj)/arch/x86/memlayout.romstage.ld --oformat $(romstage-oformat)
-	LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \
-	grep -v "Empty loadable segment detected" && \
-	if [ -n "`$(NM_romstage) $(objcbfs)/romstage_null.offenders 2>/dev/null`" ]; then \
-		echo "Forbidden global variables in romstage:"; \
-		$(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \
-		else true; fi
-
 # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
 romstage-S-ccopts += -I. -g0
 
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
new file mode 100644
index 0000000..c23d177
--- /dev/null
+++ b/src/arch/x86/assembly_entry.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The assembly.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/assembly.inc>
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
deleted file mode 100644
index b19b954..0000000
--- a/src/arch/x86/romstage.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file assembles the start of the romstage program by the order of the
- * includes. Thus, it's extremely important that one pays very careful
- * attention to the order of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/32bit/entry32.inc>
-#include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
-
-/*
- * The romstage.inc is generated based on the requirements of the mainboard.
- * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
- * processed by ROMCC and added. In non-ROMCC boards the chipsets'
- * cache-as-ram setup files would be here.
- */
-#include <generated/romstage.inc>


From gerrit at coreboot.org  Wed Sep 30 02:34:24 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 02:34:24 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: vboot: provide
	a unified flow for separate verstage
References: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+0@gerrit.coreboot.org>
Message-ID: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11744

-gerrit

commit 6d975f7d4939d61f7dcd46ad42a70360f4b66275
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 17:56:59 2015 -0500

    vboot: provide a unified flow for separate verstage
    
    The vboot verification in a stage proper is unified
    replacing duplicate code in the tegra SoC code. The
    original verstage.c file is renamed to reflect its
    real purpose. The support for a single verstage flow
    is added to the vboot2 directory proper.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/foster/Makefile.inc           |   1 -
 src/mainboard/google/foster/verstage.c             |  29 --
 src/soc/nvidia/tegra132/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra132/verstage.c                 |  48 ---
 src/soc/nvidia/tegra210/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra210/verstage.c                 |  45 ---
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |   3 +-
 src/vendorcode/google/chromeos/vboot2/misc.h       |   2 +
 .../google/chromeos/vboot2/vboot_logic.c           | 352 +++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot2/verstage.c   | 338 +-------------------
 10 files changed, 375 insertions(+), 447 deletions(-)

diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc
index 7b2329e..51208c7 100644
--- a/src/mainboard/google/foster/Makefile.inc
+++ b/src/mainboard/google/foster/Makefile.inc
@@ -32,7 +32,6 @@ bootblock-y += bootblock.c
 bootblock-y += pmic.c
 bootblock-y += reset.c
 
-verstage-y += verstage.c
 verstage-y += chromeos.c
 verstage-y += reset.c
 
diff --git a/src/mainboard/google/foster/verstage.c b/src/mainboard/google/foster/verstage.c
deleted file mode 100644
index d5bcd44..0000000
--- a/src/mainboard/google/foster/verstage.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <soc/addressmap.h>
-#include <soc/funitcfg.h>
-#include <soc/padconfig.h>
-#include <soc/verstage.h>
-#include <soc/nvidia/tegra/i2c.h>
-
-void verstage_mainboard_init(void)
-{
-}
diff --git a/src/soc/nvidia/tegra132/include/soc/verstage.h b/src/soc/nvidia/tegra132/include/soc/verstage.h
index df6a386..d54a111 100644
--- a/src/soc/nvidia/tegra132/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c
deleted file mode 100644
index d6eba9a..0000000
--- a/src/soc/nvidia/tegra132/verstage.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <arch/stages.h>
-#include <console/console.h>
-#include <soc/verstage.h>
-#include <program_loading.h>
-#include <timestamp.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	timestamp_add_now(TS_START_VBOOT);
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h
index 6c37218..d6564c9 100644
--- a/src/soc/nvidia/tegra210/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra210/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra210/verstage.c b/src/soc/nvidia/tegra210/verstage.c
deleted file mode 100644
index 6a4df29..0000000
--- a/src/soc/nvidia/tegra210/verstage.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <soc/verstage.h>
-#include <console/console.h>
-#include <program_loading.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index 21613ba..c2ee868 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -31,8 +31,9 @@ romstage-y += ../vboot_common.c
 ramstage-y += ../vboot_common.c
 
 bootblock-y += common.c
-libverstage-y += verstage.c
+libverstage-y += vboot_logic.c
 verstage-y += common.c
+verstage-y += verstage.c
 ifeq (${CONFIG_VBOOT2_MOCK_SECDATA},y)
 libverstage-y += secdata_mock.c
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/misc.h b/src/vendorcode/google/chromeos/vboot2/misc.h
index d4f9f48..f6f8d7d1a5 100644
--- a/src/vendorcode/google/chromeos/vboot2/misc.h
+++ b/src/vendorcode/google/chromeos/vboot2/misc.h
@@ -24,6 +24,8 @@
 
 void vboot_fill_handoff(void);
 void verstage_main(void);
+void verstage_mainboard_init(void);
+void verstage(void);
 void *vboot_load_stage(int stage_index,
 		       struct region *fw_main,
 		       struct vboot_components *fw_info);
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
new file mode 100644
index 0000000..76355ec
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
@@ -0,0 +1,352 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <antirollback.h>
+#include <arch/exception.h>
+#include <assert.h>
+#include <console/console.h>
+#include <console/vtxprintf.h>
+#include <delay.h>
+#include <string.h>
+#include <timestamp.h>
+#include <vb2_api.h>
+
+#include "../chromeos.h"
+#include "misc.h"
+
+#define TODO_BLOCK_SIZE 1024
+
+static int is_slot_a(struct vb2_context *ctx)
+{
+	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
+}
+
+/* exports */
+
+void vb2ex_printf(const char *func, const char *fmt, ...)
+{
+	va_list args;
+
+	printk(BIOS_INFO, "VB2:%s() ", func);
+	va_start(args, fmt);
+	do_printk_va_list(BIOS_INFO, fmt, args);
+	va_end(args);
+
+	return;
+}
+
+int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
+{
+	uint32_t rv;
+	printk(BIOS_INFO, "Clearing TPM owner\n");
+	rv = tpm_clear_and_reenable();
+	if (rv)
+		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
+	return VB2_SUCCESS;
+}
+
+int vb2ex_read_resource(struct vb2_context *ctx,
+			enum vb2_resource_index index,
+			uint32_t offset,
+			void *buf,
+			uint32_t size)
+{
+	struct region_device rdev;
+	const char *name;
+
+	switch (index) {
+	case VB2_RES_GBB:
+		name = "GBB";
+		break;
+	case VB2_RES_FW_VBLOCK:
+		if (is_slot_a(ctx))
+			name = "VBLOCK_A";
+		else
+			name = "VBLOCK_B";
+		break;
+	default:
+		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
+	}
+
+	if (vboot_named_region_device(name, &rdev))
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	if (rdev_readat(&rdev, buf, offset, size) != size)
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	return VB2_SUCCESS;
+}
+
+/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
+			       uint32_t data_size)
+{
+	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
+{
+	uint64_t load_ts;
+	uint32_t expected_size;
+	uint8_t block[TODO_BLOCK_SIZE];
+	size_t block_size = sizeof(block);
+	size_t offset;
+	int rv;
+
+	/*
+	 * Since loading the firmware and calculating its hash is intertwined,
+	 * we use this little trick to measure them separately and pretend it
+	 * was first loaded and then hashed in one piece with the timestamps.
+	 * (This split won't make sense with memory-mapped media like on x86.)
+	 */
+	load_ts = timestamp_get();
+	timestamp_add(TS_START_HASH_BODY, load_ts);
+
+	expected_size = region_device_sz(fw_main);
+	offset = 0;
+
+	/* Start the body hash */
+	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
+	if (rv)
+		return rv;
+
+	/* Extend over the body */
+	while (expected_size) {
+		uint64_t temp_ts;
+		if (block_size > expected_size)
+			block_size = expected_size;
+
+		temp_ts = timestamp_get();
+		if (rdev_readat(fw_main, block, offset, block_size) < 0)
+			return VB2_ERROR_UNKNOWN;
+		load_ts += timestamp_get() - temp_ts;
+
+		rv = vb2api_extend_hash(ctx, block, block_size);
+		if (rv)
+			return rv;
+
+		expected_size -= block_size;
+		offset += block_size;
+	}
+
+	timestamp_add(TS_DONE_LOADING, load_ts);
+	timestamp_add_now(TS_DONE_HASHING);
+
+	/* Check the result (with RSA signature verification) */
+	rv = vb2api_check_hash(ctx);
+	if (rv)
+		return rv;
+
+	timestamp_add_now(TS_END_HASH_BODY);
+
+	return VB2_SUCCESS;
+}
+
+static int locate_firmware(struct vb2_context *ctx,
+				struct region_device *fw_main)
+{
+	const char *name;
+
+	if (is_slot_a(ctx))
+		name = "FW_MAIN_A";
+	else
+		name = "FW_MAIN_B";
+
+	return vboot_named_region_device(name, fw_main);
+}
+
+/**
+ * Save non-volatile and/or secure data if needed.
+ */
+static void save_if_needed(struct vb2_context *ctx)
+{
+	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving nvdata\n");
+		save_vbnv(ctx->nvdata);
+		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
+	}
+	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving secdata\n");
+		antirollback_write_space_firmware(ctx);
+		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
+	}
+}
+
+static uint32_t extend_pcrs(struct vb2_context *ctx)
+{
+	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
+	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
+}
+
+static void init_vb2_working_data(void)
+{
+	struct vb2_working_data *wd;
+	size_t work_size;
+
+	work_size = vb2_working_data_size();
+	wd = vboot_get_working_data();
+	memset(wd, 0, work_size);
+	/*
+	 * vboot prefers 16-byte alignment. This takes away 16 bytes
+	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
+	 */
+	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
+	wd->buffer_size = work_size - wd->buffer_offset;
+}
+
+/**
+ * Verify and select the firmware in the RW image
+ *
+ * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
+ * when per-stage verification is ready.
+ */
+void verstage_main(void)
+{
+	struct vb2_context ctx;
+	struct region_device fw_main;
+	struct vb2_working_data *wd;
+	int rv;
+	init_vb2_working_data();
+	wd = vboot_get_working_data();
+	timestamp_add_now(TS_START_VBOOT);
+
+	/* Set up context and work buffer */
+	memset(&ctx, 0, sizeof(ctx));
+	ctx.workbuf = vboot_get_work_buffer(wd);
+	ctx.workbuf_size = wd->buffer_size;
+
+	/* Read nvdata from a non-volatile storage */
+	read_vbnv(ctx.nvdata);
+
+	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
+	 * check the return value here because vb2api_fw_phase1 will catch
+	 * invalid secdata and tell us what to do (=reboot). */
+	timestamp_add_now(TS_START_TPMINIT);
+	antirollback_read_space_firmware(&ctx);
+	timestamp_add_now(TS_END_TPMINIT);
+
+	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
+	    get_developer_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
+
+	if (get_recovery_mode_switch()) {
+		clear_recovery_mode_switch();
+		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
+		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
+			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
+	}
+
+	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
+
+	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
+		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
+
+	/* Do early init (set up secdata and NVRAM, load GBB) */
+	printk(BIOS_INFO, "Phase 1\n");
+	rv = vb2api_fw_phase1(&ctx);
+
+	if (rv) {
+		/*
+		 * If vb2api_fw_phase1 fails, check for return value.
+		 * If it is set to VB2_ERROR_API_PHASE1_RECOVERY, then continue
+		 * into recovery mode.
+		 * For any other error code, save context if needed and reboot.
+		 */
+		if (rv == VB2_ERROR_API_PHASE1_RECOVERY) {
+			printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
+			save_if_needed(&ctx);
+			extend_pcrs(&ctx);	/* ignore failures */
+			timestamp_add_now(TS_END_VBOOT);
+			return;
+		}
+
+		printk(BIOS_INFO, "Reboot reqested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Determine which firmware slot to boot (based on NVRAM) */
+	printk(BIOS_INFO, "Phase 2\n");
+	rv = vb2api_fw_phase2(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Try that slot (verify its keyblock and preamble) */
+	printk(BIOS_INFO, "Phase 3\n");
+	timestamp_add_now(TS_START_VERIFY_SLOT);
+	rv = vb2api_fw_phase3(&ctx);
+	timestamp_add_now(TS_END_VERIFY_SLOT);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Phase 4\n");
+	rv = locate_firmware(&ctx, &fw_main);
+	if (rv)
+		die("Failed to read FMAP to locate firmware");
+
+	rv = hash_body(&ctx, &fw_main);
+	save_if_needed(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		vboot_reboot();
+	}
+
+	rv = extend_pcrs(&ctx);
+	if (rv) {
+		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Lock TPM */
+	rv = antirollback_lock_space_firmware();
+	if (rv) {
+		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
+	vb2_set_selected_region(wd, &fw_main);
+	timestamp_add_now(TS_END_VBOOT);
+}
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 7803d39..a421c95 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2014 Google Inc.
+ * Copyright 2015 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,7 +9,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -17,333 +17,29 @@
  * Foundation, Inc.
  */
 
-#include <antirollback.h>
 #include <arch/exception.h>
-#include <assert.h>
+#include <arch/hlt.h>
 #include <console/console.h>
-#include <console/vtxprintf.h>
-#include <delay.h>
-#include <string.h>
-#include <timestamp.h>
-#include <vb2_api.h>
+#include <program_loading.h>
 
-#include "../chromeos.h"
-#include "misc.h"
-
-#define TODO_BLOCK_SIZE 1024
-
-static int is_slot_a(struct vb2_context *ctx)
-{
-	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
-}
-
-/* exports */
-
-void vb2ex_printf(const char *func, const char *fmt, ...)
+void __attribute__((weak)) verstage_mainboard_init(void)
 {
-	va_list args;
-
-	printk(BIOS_INFO, "VB2:%s() ", func);
-	va_start(args, fmt);
-	do_printk_va_list(BIOS_INFO, fmt, args);
-	va_end(args);
-
-	return;
-}
-
-int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
-{
-	uint32_t rv;
-	printk(BIOS_INFO, "Clearing TPM owner\n");
-	rv = tpm_clear_and_reenable();
-	if (rv)
-		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
-	return VB2_SUCCESS;
+	/* Default empty implementation. */
 }
 
-int vb2ex_read_resource(struct vb2_context *ctx,
-			enum vb2_resource_index index,
-			uint32_t offset,
-			void *buf,
-			uint32_t size)
+void verstage_chain_load(void)
 {
-	struct region_device rdev;
-	const char *name;
-
-	switch (index) {
-	case VB2_RES_GBB:
-		name = "GBB";
-		break;
-	case VB2_RES_FW_VBLOCK:
-		if (is_slot_a(ctx))
-			name = "VBLOCK_A";
-		else
-			name = "VBLOCK_B";
-		break;
-	default:
-		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
-	}
-
-	if (vboot_named_region_device(name, &rdev))
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	if (rdev_readat(&rdev, buf, offset, size) != size)
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	return VB2_SUCCESS;
-}
-
-/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
-			       uint32_t data_size)
-{
-	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
-{
-	uint64_t load_ts;
-	uint32_t expected_size;
-	uint8_t block[TODO_BLOCK_SIZE];
-	size_t block_size = sizeof(block);
-	size_t offset;
-	int rv;
-
-	/*
-	 * Since loading the firmware and calculating its hash is intertwined,
-	 * we use this little trick to measure them separately and pretend it
-	 * was first loaded and then hashed in one piece with the timestamps.
-	 * (This split won't make sense with memory-mapped media like on x86.)
-	 */
-	load_ts = timestamp_get();
-	timestamp_add(TS_START_HASH_BODY, load_ts);
-
-	expected_size = region_device_sz(fw_main);
-	offset = 0;
-
-	/* Start the body hash */
-	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
-	if (rv)
-		return rv;
-
-	/* Extend over the body */
-	while (expected_size) {
-		uint64_t temp_ts;
-		if (block_size > expected_size)
-			block_size = expected_size;
-
-		temp_ts = timestamp_get();
-		if (rdev_readat(fw_main, block, offset, block_size) < 0)
-			return VB2_ERROR_UNKNOWN;
-		load_ts += timestamp_get() - temp_ts;
-
-		rv = vb2api_extend_hash(ctx, block, block_size);
-		if (rv)
-			return rv;
-
-		expected_size -= block_size;
-		offset += block_size;
-	}
-
-	timestamp_add(TS_DONE_LOADING, load_ts);
-	timestamp_add_now(TS_DONE_HASHING);
-
-	/* Check the result (with RSA signature verification) */
-	rv = vb2api_check_hash(ctx);
-	if (rv)
-		return rv;
-
-	timestamp_add_now(TS_END_HASH_BODY);
-
-	return VB2_SUCCESS;
-}
-
-static int locate_firmware(struct vb2_context *ctx,
-				struct region_device *fw_main)
-{
-	const char *name;
-
-	if (is_slot_a(ctx))
-		name = "FW_MAIN_A";
-	else
-		name = "FW_MAIN_B";
-
-	return vboot_named_region_device(name, fw_main);
-}
-
-/**
- * Save non-volatile and/or secure data if needed.
- */
-static void save_if_needed(struct vb2_context *ctx)
-{
-	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving nvdata\n");
-		save_vbnv(ctx->nvdata);
-		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
-	}
-	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving secdata\n");
-		antirollback_write_space_firmware(ctx);
-		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
-	}
-}
-
-static uint32_t extend_pcrs(struct vb2_context *ctx)
-{
-	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
-	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
-}
-
-static void init_vb2_working_data(void)
-{
-	struct vb2_working_data *wd;
-	size_t work_size;
-
-	work_size = vb2_working_data_size();
-	wd = vboot_get_working_data();
-	memset(wd, 0, work_size);
-	/*
-	 * vboot prefers 16-byte alignment. This takes away 16 bytes
-	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
-	 */
-	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
-	wd->buffer_size = work_size - wd->buffer_offset;
-}
-
-/**
- * Verify and select the firmware in the RW image
- *
- * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
- * when per-stage verification is ready.
- */
-void verstage_main(void)
-{
-	struct vb2_context ctx;
-	struct region_device fw_main;
-	struct vb2_working_data *wd;
-	int rv;
-	init_vb2_working_data();
-	wd = vboot_get_working_data();
-	timestamp_add_now(TS_START_VBOOT);
-
-	/* Set up context and work buffer */
-	memset(&ctx, 0, sizeof(ctx));
-	ctx.workbuf = vboot_get_work_buffer(wd);
-	ctx.workbuf_size = wd->buffer_size;
-
-	/* Read nvdata from a non-volatile storage */
-	read_vbnv(ctx.nvdata);
-
-	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
-	 * check the return value here because vb2api_fw_phase1 will catch
-	 * invalid secdata and tell us what to do (=reboot). */
-	timestamp_add_now(TS_START_TPMINIT);
-	antirollback_read_space_firmware(&ctx);
-	timestamp_add_now(TS_END_TPMINIT);
-
-	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
-	    get_developer_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
-
-	if (get_recovery_mode_switch()) {
-		clear_recovery_mode_switch();
-		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
-		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
-			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
-	}
-
-	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
-
-	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
-		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
-
-	/* Do early init (set up secdata and NVRAM, load GBB) */
-	printk(BIOS_INFO, "Phase 1\n");
-	rv = vb2api_fw_phase1(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
-		/* If we need recovery mode, leave firmware selection now */
-		save_if_needed(&ctx);
-		extend_pcrs(&ctx);	/* ignore failures */
-		timestamp_add_now(TS_END_VBOOT);
-		return;
-	}
-
-	/* Determine which firmware slot to boot (based on NVRAM) */
-	printk(BIOS_INFO, "Phase 2\n");
-	rv = vb2api_fw_phase2(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	/* Try that slot (verify its keyblock and preamble) */
-	printk(BIOS_INFO, "Phase 3\n");
-	timestamp_add_now(TS_START_VERIFY_SLOT);
-	rv = vb2api_fw_phase3(&ctx);
-	timestamp_add_now(TS_END_VERIFY_SLOT);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	printk(BIOS_INFO, "Phase 4\n");
-	rv = locate_firmware(&ctx, &fw_main);
-	if (rv)
-		die("Failed to read FMAP to locate firmware");
-
-	rv = hash_body(&ctx, &fw_main);
-	save_if_needed(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		vboot_reboot();
-	}
-
-	rv = extend_pcrs(&ctx);
-	if (rv) {
-		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
+	console_init();
+	exception_init();
+	verstage_mainboard_init();
 
-	/* Lock TPM */
-	rv = antirollback_lock_space_firmware();
-	if (rv) {
-		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
-		save_if_needed(&ctx);
-		vboot_reboot();
+	if (IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) {
+		verstage_main();
+	} else {
+		run_romstage();
+		hlt();
 	}
-
-	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
-	vb2_set_selected_region(wd, &fw_main);
-	timestamp_add_now(TS_END_VBOOT);
 }
 
-#if IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)
-void main(void)
-{
-	console_init();
-	exception_init();
-	verstage_main();
-}
-#endif
+/* This is for boards that rely on main() for an entry point of a stage. */
+void main(void) __attribute__((alias ("verstage_chain_load")))


From gerrit at coreboot.org  Wed Sep 30 02:37:37 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 02:37:37 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: vboot: provide a
	unified flow for separate verstage
References: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+0@gerrit.coreboot.org>
Message-ID: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11744

-gerrit

commit 6ad3c15c861b956e6fac8b1d36a67191be8b7563
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 17:56:59 2015 -0500

    vboot: provide a unified flow for separate verstage
    
    The vboot verification in a stage proper is unified
    replacing duplicate code in the tegra SoC code. The
    original verstage.c file is renamed to reflect its
    real purpose. The support for a single verstage flow
    is added to the vboot2 directory proper.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/foster/Makefile.inc           |   1 -
 src/mainboard/google/foster/verstage.c             |  29 --
 src/soc/nvidia/tegra132/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra132/verstage.c                 |  48 ---
 src/soc/nvidia/tegra210/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra210/verstage.c                 |  45 ---
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |   3 +-
 src/vendorcode/google/chromeos/vboot2/misc.h       |   1 -
 .../google/chromeos/vboot2/vboot_logic.c           | 352 +++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot2/verstage.c   | 338 +-------------------
 src/vendorcode/google/chromeos/vboot_common.h      |   6 +
 11 files changed, 379 insertions(+), 448 deletions(-)

diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc
index 7b2329e..51208c7 100644
--- a/src/mainboard/google/foster/Makefile.inc
+++ b/src/mainboard/google/foster/Makefile.inc
@@ -32,7 +32,6 @@ bootblock-y += bootblock.c
 bootblock-y += pmic.c
 bootblock-y += reset.c
 
-verstage-y += verstage.c
 verstage-y += chromeos.c
 verstage-y += reset.c
 
diff --git a/src/mainboard/google/foster/verstage.c b/src/mainboard/google/foster/verstage.c
deleted file mode 100644
index d5bcd44..0000000
--- a/src/mainboard/google/foster/verstage.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <soc/addressmap.h>
-#include <soc/funitcfg.h>
-#include <soc/padconfig.h>
-#include <soc/verstage.h>
-#include <soc/nvidia/tegra/i2c.h>
-
-void verstage_mainboard_init(void)
-{
-}
diff --git a/src/soc/nvidia/tegra132/include/soc/verstage.h b/src/soc/nvidia/tegra132/include/soc/verstage.h
index df6a386..d54a111 100644
--- a/src/soc/nvidia/tegra132/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c
deleted file mode 100644
index d6eba9a..0000000
--- a/src/soc/nvidia/tegra132/verstage.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <arch/stages.h>
-#include <console/console.h>
-#include <soc/verstage.h>
-#include <program_loading.h>
-#include <timestamp.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	timestamp_add_now(TS_START_VBOOT);
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h
index 6c37218..d6564c9 100644
--- a/src/soc/nvidia/tegra210/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra210/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra210/verstage.c b/src/soc/nvidia/tegra210/verstage.c
deleted file mode 100644
index 6a4df29..0000000
--- a/src/soc/nvidia/tegra210/verstage.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <soc/verstage.h>
-#include <console/console.h>
-#include <program_loading.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index 21613ba..c2ee868 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -31,8 +31,9 @@ romstage-y += ../vboot_common.c
 ramstage-y += ../vboot_common.c
 
 bootblock-y += common.c
-libverstage-y += verstage.c
+libverstage-y += vboot_logic.c
 verstage-y += common.c
+verstage-y += verstage.c
 ifeq (${CONFIG_VBOOT2_MOCK_SECDATA},y)
 libverstage-y += secdata_mock.c
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/misc.h b/src/vendorcode/google/chromeos/vboot2/misc.h
index d4f9f48..305d0da 100644
--- a/src/vendorcode/google/chromeos/vboot2/misc.h
+++ b/src/vendorcode/google/chromeos/vboot2/misc.h
@@ -23,7 +23,6 @@
 #include "../vboot_common.h"
 
 void vboot_fill_handoff(void);
-void verstage_main(void);
 void *vboot_load_stage(int stage_index,
 		       struct region *fw_main,
 		       struct vboot_components *fw_info);
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
new file mode 100644
index 0000000..76355ec
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
@@ -0,0 +1,352 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <antirollback.h>
+#include <arch/exception.h>
+#include <assert.h>
+#include <console/console.h>
+#include <console/vtxprintf.h>
+#include <delay.h>
+#include <string.h>
+#include <timestamp.h>
+#include <vb2_api.h>
+
+#include "../chromeos.h"
+#include "misc.h"
+
+#define TODO_BLOCK_SIZE 1024
+
+static int is_slot_a(struct vb2_context *ctx)
+{
+	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
+}
+
+/* exports */
+
+void vb2ex_printf(const char *func, const char *fmt, ...)
+{
+	va_list args;
+
+	printk(BIOS_INFO, "VB2:%s() ", func);
+	va_start(args, fmt);
+	do_printk_va_list(BIOS_INFO, fmt, args);
+	va_end(args);
+
+	return;
+}
+
+int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
+{
+	uint32_t rv;
+	printk(BIOS_INFO, "Clearing TPM owner\n");
+	rv = tpm_clear_and_reenable();
+	if (rv)
+		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
+	return VB2_SUCCESS;
+}
+
+int vb2ex_read_resource(struct vb2_context *ctx,
+			enum vb2_resource_index index,
+			uint32_t offset,
+			void *buf,
+			uint32_t size)
+{
+	struct region_device rdev;
+	const char *name;
+
+	switch (index) {
+	case VB2_RES_GBB:
+		name = "GBB";
+		break;
+	case VB2_RES_FW_VBLOCK:
+		if (is_slot_a(ctx))
+			name = "VBLOCK_A";
+		else
+			name = "VBLOCK_B";
+		break;
+	default:
+		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
+	}
+
+	if (vboot_named_region_device(name, &rdev))
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	if (rdev_readat(&rdev, buf, offset, size) != size)
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	return VB2_SUCCESS;
+}
+
+/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
+			       uint32_t data_size)
+{
+	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
+{
+	uint64_t load_ts;
+	uint32_t expected_size;
+	uint8_t block[TODO_BLOCK_SIZE];
+	size_t block_size = sizeof(block);
+	size_t offset;
+	int rv;
+
+	/*
+	 * Since loading the firmware and calculating its hash is intertwined,
+	 * we use this little trick to measure them separately and pretend it
+	 * was first loaded and then hashed in one piece with the timestamps.
+	 * (This split won't make sense with memory-mapped media like on x86.)
+	 */
+	load_ts = timestamp_get();
+	timestamp_add(TS_START_HASH_BODY, load_ts);
+
+	expected_size = region_device_sz(fw_main);
+	offset = 0;
+
+	/* Start the body hash */
+	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
+	if (rv)
+		return rv;
+
+	/* Extend over the body */
+	while (expected_size) {
+		uint64_t temp_ts;
+		if (block_size > expected_size)
+			block_size = expected_size;
+
+		temp_ts = timestamp_get();
+		if (rdev_readat(fw_main, block, offset, block_size) < 0)
+			return VB2_ERROR_UNKNOWN;
+		load_ts += timestamp_get() - temp_ts;
+
+		rv = vb2api_extend_hash(ctx, block, block_size);
+		if (rv)
+			return rv;
+
+		expected_size -= block_size;
+		offset += block_size;
+	}
+
+	timestamp_add(TS_DONE_LOADING, load_ts);
+	timestamp_add_now(TS_DONE_HASHING);
+
+	/* Check the result (with RSA signature verification) */
+	rv = vb2api_check_hash(ctx);
+	if (rv)
+		return rv;
+
+	timestamp_add_now(TS_END_HASH_BODY);
+
+	return VB2_SUCCESS;
+}
+
+static int locate_firmware(struct vb2_context *ctx,
+				struct region_device *fw_main)
+{
+	const char *name;
+
+	if (is_slot_a(ctx))
+		name = "FW_MAIN_A";
+	else
+		name = "FW_MAIN_B";
+
+	return vboot_named_region_device(name, fw_main);
+}
+
+/**
+ * Save non-volatile and/or secure data if needed.
+ */
+static void save_if_needed(struct vb2_context *ctx)
+{
+	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving nvdata\n");
+		save_vbnv(ctx->nvdata);
+		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
+	}
+	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving secdata\n");
+		antirollback_write_space_firmware(ctx);
+		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
+	}
+}
+
+static uint32_t extend_pcrs(struct vb2_context *ctx)
+{
+	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
+	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
+}
+
+static void init_vb2_working_data(void)
+{
+	struct vb2_working_data *wd;
+	size_t work_size;
+
+	work_size = vb2_working_data_size();
+	wd = vboot_get_working_data();
+	memset(wd, 0, work_size);
+	/*
+	 * vboot prefers 16-byte alignment. This takes away 16 bytes
+	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
+	 */
+	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
+	wd->buffer_size = work_size - wd->buffer_offset;
+}
+
+/**
+ * Verify and select the firmware in the RW image
+ *
+ * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
+ * when per-stage verification is ready.
+ */
+void verstage_main(void)
+{
+	struct vb2_context ctx;
+	struct region_device fw_main;
+	struct vb2_working_data *wd;
+	int rv;
+	init_vb2_working_data();
+	wd = vboot_get_working_data();
+	timestamp_add_now(TS_START_VBOOT);
+
+	/* Set up context and work buffer */
+	memset(&ctx, 0, sizeof(ctx));
+	ctx.workbuf = vboot_get_work_buffer(wd);
+	ctx.workbuf_size = wd->buffer_size;
+
+	/* Read nvdata from a non-volatile storage */
+	read_vbnv(ctx.nvdata);
+
+	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
+	 * check the return value here because vb2api_fw_phase1 will catch
+	 * invalid secdata and tell us what to do (=reboot). */
+	timestamp_add_now(TS_START_TPMINIT);
+	antirollback_read_space_firmware(&ctx);
+	timestamp_add_now(TS_END_TPMINIT);
+
+	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
+	    get_developer_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
+
+	if (get_recovery_mode_switch()) {
+		clear_recovery_mode_switch();
+		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
+		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
+			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
+	}
+
+	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
+
+	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
+		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
+
+	/* Do early init (set up secdata and NVRAM, load GBB) */
+	printk(BIOS_INFO, "Phase 1\n");
+	rv = vb2api_fw_phase1(&ctx);
+
+	if (rv) {
+		/*
+		 * If vb2api_fw_phase1 fails, check for return value.
+		 * If it is set to VB2_ERROR_API_PHASE1_RECOVERY, then continue
+		 * into recovery mode.
+		 * For any other error code, save context if needed and reboot.
+		 */
+		if (rv == VB2_ERROR_API_PHASE1_RECOVERY) {
+			printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
+			save_if_needed(&ctx);
+			extend_pcrs(&ctx);	/* ignore failures */
+			timestamp_add_now(TS_END_VBOOT);
+			return;
+		}
+
+		printk(BIOS_INFO, "Reboot reqested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Determine which firmware slot to boot (based on NVRAM) */
+	printk(BIOS_INFO, "Phase 2\n");
+	rv = vb2api_fw_phase2(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Try that slot (verify its keyblock and preamble) */
+	printk(BIOS_INFO, "Phase 3\n");
+	timestamp_add_now(TS_START_VERIFY_SLOT);
+	rv = vb2api_fw_phase3(&ctx);
+	timestamp_add_now(TS_END_VERIFY_SLOT);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Phase 4\n");
+	rv = locate_firmware(&ctx, &fw_main);
+	if (rv)
+		die("Failed to read FMAP to locate firmware");
+
+	rv = hash_body(&ctx, &fw_main);
+	save_if_needed(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		vboot_reboot();
+	}
+
+	rv = extend_pcrs(&ctx);
+	if (rv) {
+		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Lock TPM */
+	rv = antirollback_lock_space_firmware();
+	if (rv) {
+		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
+	vb2_set_selected_region(wd, &fw_main);
+	timestamp_add_now(TS_END_VBOOT);
+}
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 7803d39..0d78668 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2014 Google Inc.
+ * Copyright 2015 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,7 +9,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -17,333 +17,29 @@
  * Foundation, Inc.
  */
 
-#include <antirollback.h>
 #include <arch/exception.h>
-#include <assert.h>
+#include <arch/hlt.h>
 #include <console/console.h>
-#include <console/vtxprintf.h>
-#include <delay.h>
-#include <string.h>
-#include <timestamp.h>
-#include <vb2_api.h>
+#include <program_loading.h>
 
-#include "../chromeos.h"
-#include "misc.h"
-
-#define TODO_BLOCK_SIZE 1024
-
-static int is_slot_a(struct vb2_context *ctx)
-{
-	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
-}
-
-/* exports */
-
-void vb2ex_printf(const char *func, const char *fmt, ...)
+void __attribute__((weak)) verstage_mainboard_init(void)
 {
-	va_list args;
-
-	printk(BIOS_INFO, "VB2:%s() ", func);
-	va_start(args, fmt);
-	do_printk_va_list(BIOS_INFO, fmt, args);
-	va_end(args);
-
-	return;
-}
-
-int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
-{
-	uint32_t rv;
-	printk(BIOS_INFO, "Clearing TPM owner\n");
-	rv = tpm_clear_and_reenable();
-	if (rv)
-		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
-	return VB2_SUCCESS;
+	/* Default empty implementation. */
 }
 
-int vb2ex_read_resource(struct vb2_context *ctx,
-			enum vb2_resource_index index,
-			uint32_t offset,
-			void *buf,
-			uint32_t size)
+void verstage(void)
 {
-	struct region_device rdev;
-	const char *name;
-
-	switch (index) {
-	case VB2_RES_GBB:
-		name = "GBB";
-		break;
-	case VB2_RES_FW_VBLOCK:
-		if (is_slot_a(ctx))
-			name = "VBLOCK_A";
-		else
-			name = "VBLOCK_B";
-		break;
-	default:
-		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
-	}
-
-	if (vboot_named_region_device(name, &rdev))
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	if (rdev_readat(&rdev, buf, offset, size) != size)
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	return VB2_SUCCESS;
-}
-
-/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
-			       uint32_t data_size)
-{
-	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
-{
-	uint64_t load_ts;
-	uint32_t expected_size;
-	uint8_t block[TODO_BLOCK_SIZE];
-	size_t block_size = sizeof(block);
-	size_t offset;
-	int rv;
-
-	/*
-	 * Since loading the firmware and calculating its hash is intertwined,
-	 * we use this little trick to measure them separately and pretend it
-	 * was first loaded and then hashed in one piece with the timestamps.
-	 * (This split won't make sense with memory-mapped media like on x86.)
-	 */
-	load_ts = timestamp_get();
-	timestamp_add(TS_START_HASH_BODY, load_ts);
-
-	expected_size = region_device_sz(fw_main);
-	offset = 0;
-
-	/* Start the body hash */
-	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
-	if (rv)
-		return rv;
-
-	/* Extend over the body */
-	while (expected_size) {
-		uint64_t temp_ts;
-		if (block_size > expected_size)
-			block_size = expected_size;
-
-		temp_ts = timestamp_get();
-		if (rdev_readat(fw_main, block, offset, block_size) < 0)
-			return VB2_ERROR_UNKNOWN;
-		load_ts += timestamp_get() - temp_ts;
-
-		rv = vb2api_extend_hash(ctx, block, block_size);
-		if (rv)
-			return rv;
-
-		expected_size -= block_size;
-		offset += block_size;
-	}
-
-	timestamp_add(TS_DONE_LOADING, load_ts);
-	timestamp_add_now(TS_DONE_HASHING);
-
-	/* Check the result (with RSA signature verification) */
-	rv = vb2api_check_hash(ctx);
-	if (rv)
-		return rv;
-
-	timestamp_add_now(TS_END_HASH_BODY);
-
-	return VB2_SUCCESS;
-}
-
-static int locate_firmware(struct vb2_context *ctx,
-				struct region_device *fw_main)
-{
-	const char *name;
-
-	if (is_slot_a(ctx))
-		name = "FW_MAIN_A";
-	else
-		name = "FW_MAIN_B";
-
-	return vboot_named_region_device(name, fw_main);
-}
-
-/**
- * Save non-volatile and/or secure data if needed.
- */
-static void save_if_needed(struct vb2_context *ctx)
-{
-	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving nvdata\n");
-		save_vbnv(ctx->nvdata);
-		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
-	}
-	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving secdata\n");
-		antirollback_write_space_firmware(ctx);
-		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
-	}
-}
-
-static uint32_t extend_pcrs(struct vb2_context *ctx)
-{
-	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
-	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
-}
-
-static void init_vb2_working_data(void)
-{
-	struct vb2_working_data *wd;
-	size_t work_size;
-
-	work_size = vb2_working_data_size();
-	wd = vboot_get_working_data();
-	memset(wd, 0, work_size);
-	/*
-	 * vboot prefers 16-byte alignment. This takes away 16 bytes
-	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
-	 */
-	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
-	wd->buffer_size = work_size - wd->buffer_offset;
-}
-
-/**
- * Verify and select the firmware in the RW image
- *
- * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
- * when per-stage verification is ready.
- */
-void verstage_main(void)
-{
-	struct vb2_context ctx;
-	struct region_device fw_main;
-	struct vb2_working_data *wd;
-	int rv;
-	init_vb2_working_data();
-	wd = vboot_get_working_data();
-	timestamp_add_now(TS_START_VBOOT);
-
-	/* Set up context and work buffer */
-	memset(&ctx, 0, sizeof(ctx));
-	ctx.workbuf = vboot_get_work_buffer(wd);
-	ctx.workbuf_size = wd->buffer_size;
-
-	/* Read nvdata from a non-volatile storage */
-	read_vbnv(ctx.nvdata);
-
-	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
-	 * check the return value here because vb2api_fw_phase1 will catch
-	 * invalid secdata and tell us what to do (=reboot). */
-	timestamp_add_now(TS_START_TPMINIT);
-	antirollback_read_space_firmware(&ctx);
-	timestamp_add_now(TS_END_TPMINIT);
-
-	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
-	    get_developer_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
-
-	if (get_recovery_mode_switch()) {
-		clear_recovery_mode_switch();
-		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
-		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
-			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
-	}
-
-	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
-
-	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
-		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
-
-	/* Do early init (set up secdata and NVRAM, load GBB) */
-	printk(BIOS_INFO, "Phase 1\n");
-	rv = vb2api_fw_phase1(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
-		/* If we need recovery mode, leave firmware selection now */
-		save_if_needed(&ctx);
-		extend_pcrs(&ctx);	/* ignore failures */
-		timestamp_add_now(TS_END_VBOOT);
-		return;
-	}
-
-	/* Determine which firmware slot to boot (based on NVRAM) */
-	printk(BIOS_INFO, "Phase 2\n");
-	rv = vb2api_fw_phase2(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	/* Try that slot (verify its keyblock and preamble) */
-	printk(BIOS_INFO, "Phase 3\n");
-	timestamp_add_now(TS_START_VERIFY_SLOT);
-	rv = vb2api_fw_phase3(&ctx);
-	timestamp_add_now(TS_END_VERIFY_SLOT);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	printk(BIOS_INFO, "Phase 4\n");
-	rv = locate_firmware(&ctx, &fw_main);
-	if (rv)
-		die("Failed to read FMAP to locate firmware");
-
-	rv = hash_body(&ctx, &fw_main);
-	save_if_needed(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		vboot_reboot();
-	}
-
-	rv = extend_pcrs(&ctx);
-	if (rv) {
-		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
+	console_init();
+	exception_init();
+	verstage_mainboard_init();
 
-	/* Lock TPM */
-	rv = antirollback_lock_space_firmware();
-	if (rv) {
-		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
-		save_if_needed(&ctx);
-		vboot_reboot();
+	if (IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) {
+		verstage_main();
+	} else {
+		run_romstage();
+		hlt();
 	}
-
-	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
-	vb2_set_selected_region(wd, &fw_main);
-	timestamp_add_now(TS_END_VBOOT);
 }
 
-#if IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)
-void main(void)
-{
-	console_init();
-	exception_init();
-	verstage_main();
-}
-#endif
+/* This is for boards that rely on main() for an entry point of a stage. */
+void main(void) __attribute__((alias ("verstage_chain_load")))
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index f4d5e11..3a9c89b 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -48,4 +48,10 @@ int vboot_enable_developer(void);
 
 void vboot_reboot(void);
 
+/* Main logic for verified boot. verstage() is the stage entry point
+ * while the verstage_main() is just the core logic. */
+void verstage_main(void);
+void verstage_mainboard_init(void);
+void verstage(void);
+
 #endif /* VBOOT_COMMON_H */


From gerrit at coreboot.org  Wed Sep 30 02:47:20 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 02:47:20 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: vboot: provide a
	unified flow for separate verstage
References: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+0@gerrit.coreboot.org>
Message-ID: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11744

-gerrit

commit 23de41a14c53a8f86b7f70f26a195a4ec128e8c9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 17:56:59 2015 -0500

    vboot: provide a unified flow for separate verstage
    
    The vboot verification in a stage proper is unified
    replacing duplicate code in the tegra SoC code. The
    original verstage.c file is renamed to reflect its
    real purpose. The support for a single verstage flow
    is added to the vboot2 directory proper.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/foster/Makefile.inc           |   1 -
 src/mainboard/google/foster/verstage.c             |  29 --
 src/soc/nvidia/tegra132/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra132/verstage.c                 |  48 ---
 src/soc/nvidia/tegra210/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra210/verstage.c                 |  45 ---
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |   3 +-
 src/vendorcode/google/chromeos/vboot2/misc.h       |   1 -
 .../google/chromeos/vboot2/vboot_logic.c           | 352 +++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot2/verstage.c   | 339 ++------------------
 src/vendorcode/google/chromeos/vboot_common.h      |   6 +
 11 files changed, 380 insertions(+), 448 deletions(-)

diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc
index 7b2329e..51208c7 100644
--- a/src/mainboard/google/foster/Makefile.inc
+++ b/src/mainboard/google/foster/Makefile.inc
@@ -32,7 +32,6 @@ bootblock-y += bootblock.c
 bootblock-y += pmic.c
 bootblock-y += reset.c
 
-verstage-y += verstage.c
 verstage-y += chromeos.c
 verstage-y += reset.c
 
diff --git a/src/mainboard/google/foster/verstage.c b/src/mainboard/google/foster/verstage.c
deleted file mode 100644
index d5bcd44..0000000
--- a/src/mainboard/google/foster/verstage.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <soc/addressmap.h>
-#include <soc/funitcfg.h>
-#include <soc/padconfig.h>
-#include <soc/verstage.h>
-#include <soc/nvidia/tegra/i2c.h>
-
-void verstage_mainboard_init(void)
-{
-}
diff --git a/src/soc/nvidia/tegra132/include/soc/verstage.h b/src/soc/nvidia/tegra132/include/soc/verstage.h
index df6a386..d54a111 100644
--- a/src/soc/nvidia/tegra132/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c
deleted file mode 100644
index d6eba9a..0000000
--- a/src/soc/nvidia/tegra132/verstage.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <arch/stages.h>
-#include <console/console.h>
-#include <soc/verstage.h>
-#include <program_loading.h>
-#include <timestamp.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	timestamp_add_now(TS_START_VBOOT);
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h
index 6c37218..d6564c9 100644
--- a/src/soc/nvidia/tegra210/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra210/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra210/verstage.c b/src/soc/nvidia/tegra210/verstage.c
deleted file mode 100644
index 6a4df29..0000000
--- a/src/soc/nvidia/tegra210/verstage.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <soc/verstage.h>
-#include <console/console.h>
-#include <program_loading.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index 21613ba..c2ee868 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -31,8 +31,9 @@ romstage-y += ../vboot_common.c
 ramstage-y += ../vboot_common.c
 
 bootblock-y += common.c
-libverstage-y += verstage.c
+libverstage-y += vboot_logic.c
 verstage-y += common.c
+verstage-y += verstage.c
 ifeq (${CONFIG_VBOOT2_MOCK_SECDATA},y)
 libverstage-y += secdata_mock.c
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/misc.h b/src/vendorcode/google/chromeos/vboot2/misc.h
index d4f9f48..305d0da 100644
--- a/src/vendorcode/google/chromeos/vboot2/misc.h
+++ b/src/vendorcode/google/chromeos/vboot2/misc.h
@@ -23,7 +23,6 @@
 #include "../vboot_common.h"
 
 void vboot_fill_handoff(void);
-void verstage_main(void);
 void *vboot_load_stage(int stage_index,
 		       struct region *fw_main,
 		       struct vboot_components *fw_info);
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
new file mode 100644
index 0000000..76355ec
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
@@ -0,0 +1,352 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <antirollback.h>
+#include <arch/exception.h>
+#include <assert.h>
+#include <console/console.h>
+#include <console/vtxprintf.h>
+#include <delay.h>
+#include <string.h>
+#include <timestamp.h>
+#include <vb2_api.h>
+
+#include "../chromeos.h"
+#include "misc.h"
+
+#define TODO_BLOCK_SIZE 1024
+
+static int is_slot_a(struct vb2_context *ctx)
+{
+	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
+}
+
+/* exports */
+
+void vb2ex_printf(const char *func, const char *fmt, ...)
+{
+	va_list args;
+
+	printk(BIOS_INFO, "VB2:%s() ", func);
+	va_start(args, fmt);
+	do_printk_va_list(BIOS_INFO, fmt, args);
+	va_end(args);
+
+	return;
+}
+
+int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
+{
+	uint32_t rv;
+	printk(BIOS_INFO, "Clearing TPM owner\n");
+	rv = tpm_clear_and_reenable();
+	if (rv)
+		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
+	return VB2_SUCCESS;
+}
+
+int vb2ex_read_resource(struct vb2_context *ctx,
+			enum vb2_resource_index index,
+			uint32_t offset,
+			void *buf,
+			uint32_t size)
+{
+	struct region_device rdev;
+	const char *name;
+
+	switch (index) {
+	case VB2_RES_GBB:
+		name = "GBB";
+		break;
+	case VB2_RES_FW_VBLOCK:
+		if (is_slot_a(ctx))
+			name = "VBLOCK_A";
+		else
+			name = "VBLOCK_B";
+		break;
+	default:
+		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
+	}
+
+	if (vboot_named_region_device(name, &rdev))
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	if (rdev_readat(&rdev, buf, offset, size) != size)
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	return VB2_SUCCESS;
+}
+
+/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
+			       uint32_t data_size)
+{
+	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
+{
+	uint64_t load_ts;
+	uint32_t expected_size;
+	uint8_t block[TODO_BLOCK_SIZE];
+	size_t block_size = sizeof(block);
+	size_t offset;
+	int rv;
+
+	/*
+	 * Since loading the firmware and calculating its hash is intertwined,
+	 * we use this little trick to measure them separately and pretend it
+	 * was first loaded and then hashed in one piece with the timestamps.
+	 * (This split won't make sense with memory-mapped media like on x86.)
+	 */
+	load_ts = timestamp_get();
+	timestamp_add(TS_START_HASH_BODY, load_ts);
+
+	expected_size = region_device_sz(fw_main);
+	offset = 0;
+
+	/* Start the body hash */
+	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
+	if (rv)
+		return rv;
+
+	/* Extend over the body */
+	while (expected_size) {
+		uint64_t temp_ts;
+		if (block_size > expected_size)
+			block_size = expected_size;
+
+		temp_ts = timestamp_get();
+		if (rdev_readat(fw_main, block, offset, block_size) < 0)
+			return VB2_ERROR_UNKNOWN;
+		load_ts += timestamp_get() - temp_ts;
+
+		rv = vb2api_extend_hash(ctx, block, block_size);
+		if (rv)
+			return rv;
+
+		expected_size -= block_size;
+		offset += block_size;
+	}
+
+	timestamp_add(TS_DONE_LOADING, load_ts);
+	timestamp_add_now(TS_DONE_HASHING);
+
+	/* Check the result (with RSA signature verification) */
+	rv = vb2api_check_hash(ctx);
+	if (rv)
+		return rv;
+
+	timestamp_add_now(TS_END_HASH_BODY);
+
+	return VB2_SUCCESS;
+}
+
+static int locate_firmware(struct vb2_context *ctx,
+				struct region_device *fw_main)
+{
+	const char *name;
+
+	if (is_slot_a(ctx))
+		name = "FW_MAIN_A";
+	else
+		name = "FW_MAIN_B";
+
+	return vboot_named_region_device(name, fw_main);
+}
+
+/**
+ * Save non-volatile and/or secure data if needed.
+ */
+static void save_if_needed(struct vb2_context *ctx)
+{
+	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving nvdata\n");
+		save_vbnv(ctx->nvdata);
+		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
+	}
+	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving secdata\n");
+		antirollback_write_space_firmware(ctx);
+		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
+	}
+}
+
+static uint32_t extend_pcrs(struct vb2_context *ctx)
+{
+	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
+	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
+}
+
+static void init_vb2_working_data(void)
+{
+	struct vb2_working_data *wd;
+	size_t work_size;
+
+	work_size = vb2_working_data_size();
+	wd = vboot_get_working_data();
+	memset(wd, 0, work_size);
+	/*
+	 * vboot prefers 16-byte alignment. This takes away 16 bytes
+	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
+	 */
+	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
+	wd->buffer_size = work_size - wd->buffer_offset;
+}
+
+/**
+ * Verify and select the firmware in the RW image
+ *
+ * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
+ * when per-stage verification is ready.
+ */
+void verstage_main(void)
+{
+	struct vb2_context ctx;
+	struct region_device fw_main;
+	struct vb2_working_data *wd;
+	int rv;
+	init_vb2_working_data();
+	wd = vboot_get_working_data();
+	timestamp_add_now(TS_START_VBOOT);
+
+	/* Set up context and work buffer */
+	memset(&ctx, 0, sizeof(ctx));
+	ctx.workbuf = vboot_get_work_buffer(wd);
+	ctx.workbuf_size = wd->buffer_size;
+
+	/* Read nvdata from a non-volatile storage */
+	read_vbnv(ctx.nvdata);
+
+	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
+	 * check the return value here because vb2api_fw_phase1 will catch
+	 * invalid secdata and tell us what to do (=reboot). */
+	timestamp_add_now(TS_START_TPMINIT);
+	antirollback_read_space_firmware(&ctx);
+	timestamp_add_now(TS_END_TPMINIT);
+
+	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
+	    get_developer_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
+
+	if (get_recovery_mode_switch()) {
+		clear_recovery_mode_switch();
+		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
+		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
+			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
+	}
+
+	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
+
+	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
+		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
+
+	/* Do early init (set up secdata and NVRAM, load GBB) */
+	printk(BIOS_INFO, "Phase 1\n");
+	rv = vb2api_fw_phase1(&ctx);
+
+	if (rv) {
+		/*
+		 * If vb2api_fw_phase1 fails, check for return value.
+		 * If it is set to VB2_ERROR_API_PHASE1_RECOVERY, then continue
+		 * into recovery mode.
+		 * For any other error code, save context if needed and reboot.
+		 */
+		if (rv == VB2_ERROR_API_PHASE1_RECOVERY) {
+			printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
+			save_if_needed(&ctx);
+			extend_pcrs(&ctx);	/* ignore failures */
+			timestamp_add_now(TS_END_VBOOT);
+			return;
+		}
+
+		printk(BIOS_INFO, "Reboot reqested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Determine which firmware slot to boot (based on NVRAM) */
+	printk(BIOS_INFO, "Phase 2\n");
+	rv = vb2api_fw_phase2(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Try that slot (verify its keyblock and preamble) */
+	printk(BIOS_INFO, "Phase 3\n");
+	timestamp_add_now(TS_START_VERIFY_SLOT);
+	rv = vb2api_fw_phase3(&ctx);
+	timestamp_add_now(TS_END_VERIFY_SLOT);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Phase 4\n");
+	rv = locate_firmware(&ctx, &fw_main);
+	if (rv)
+		die("Failed to read FMAP to locate firmware");
+
+	rv = hash_body(&ctx, &fw_main);
+	save_if_needed(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		vboot_reboot();
+	}
+
+	rv = extend_pcrs(&ctx);
+	if (rv) {
+		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Lock TPM */
+	rv = antirollback_lock_space_firmware();
+	if (rv) {
+		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
+	vb2_set_selected_region(wd, &fw_main);
+	timestamp_add_now(TS_END_VBOOT);
+}
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 7803d39..d0b75f9 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2014 Google Inc.
+ * Copyright 2015 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,7 +9,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -17,333 +17,30 @@
  * Foundation, Inc.
  */
 
-#include <antirollback.h>
 #include <arch/exception.h>
-#include <assert.h>
+#include <arch/hlt.h>
 #include <console/console.h>
-#include <console/vtxprintf.h>
-#include <delay.h>
-#include <string.h>
-#include <timestamp.h>
-#include <vb2_api.h>
+#include <program_loading.h>
+#include "../vboot_common.h"
 
-#include "../chromeos.h"
-#include "misc.h"
-
-#define TODO_BLOCK_SIZE 1024
-
-static int is_slot_a(struct vb2_context *ctx)
-{
-	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
-}
-
-/* exports */
-
-void vb2ex_printf(const char *func, const char *fmt, ...)
+void __attribute__((weak)) verstage_mainboard_init(void)
 {
-	va_list args;
-
-	printk(BIOS_INFO, "VB2:%s() ", func);
-	va_start(args, fmt);
-	do_printk_va_list(BIOS_INFO, fmt, args);
-	va_end(args);
-
-	return;
-}
-
-int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
-{
-	uint32_t rv;
-	printk(BIOS_INFO, "Clearing TPM owner\n");
-	rv = tpm_clear_and_reenable();
-	if (rv)
-		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
-	return VB2_SUCCESS;
+	/* Default empty implementation. */
 }
 
-int vb2ex_read_resource(struct vb2_context *ctx,
-			enum vb2_resource_index index,
-			uint32_t offset,
-			void *buf,
-			uint32_t size)
+void verstage(void)
 {
-	struct region_device rdev;
-	const char *name;
-
-	switch (index) {
-	case VB2_RES_GBB:
-		name = "GBB";
-		break;
-	case VB2_RES_FW_VBLOCK:
-		if (is_slot_a(ctx))
-			name = "VBLOCK_A";
-		else
-			name = "VBLOCK_B";
-		break;
-	default:
-		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
-	}
-
-	if (vboot_named_region_device(name, &rdev))
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	if (rdev_readat(&rdev, buf, offset, size) != size)
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	return VB2_SUCCESS;
-}
-
-/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
-			       uint32_t data_size)
-{
-	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
-{
-	uint64_t load_ts;
-	uint32_t expected_size;
-	uint8_t block[TODO_BLOCK_SIZE];
-	size_t block_size = sizeof(block);
-	size_t offset;
-	int rv;
-
-	/*
-	 * Since loading the firmware and calculating its hash is intertwined,
-	 * we use this little trick to measure them separately and pretend it
-	 * was first loaded and then hashed in one piece with the timestamps.
-	 * (This split won't make sense with memory-mapped media like on x86.)
-	 */
-	load_ts = timestamp_get();
-	timestamp_add(TS_START_HASH_BODY, load_ts);
-
-	expected_size = region_device_sz(fw_main);
-	offset = 0;
-
-	/* Start the body hash */
-	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
-	if (rv)
-		return rv;
-
-	/* Extend over the body */
-	while (expected_size) {
-		uint64_t temp_ts;
-		if (block_size > expected_size)
-			block_size = expected_size;
-
-		temp_ts = timestamp_get();
-		if (rdev_readat(fw_main, block, offset, block_size) < 0)
-			return VB2_ERROR_UNKNOWN;
-		load_ts += timestamp_get() - temp_ts;
-
-		rv = vb2api_extend_hash(ctx, block, block_size);
-		if (rv)
-			return rv;
-
-		expected_size -= block_size;
-		offset += block_size;
-	}
-
-	timestamp_add(TS_DONE_LOADING, load_ts);
-	timestamp_add_now(TS_DONE_HASHING);
-
-	/* Check the result (with RSA signature verification) */
-	rv = vb2api_check_hash(ctx);
-	if (rv)
-		return rv;
-
-	timestamp_add_now(TS_END_HASH_BODY);
-
-	return VB2_SUCCESS;
-}
-
-static int locate_firmware(struct vb2_context *ctx,
-				struct region_device *fw_main)
-{
-	const char *name;
-
-	if (is_slot_a(ctx))
-		name = "FW_MAIN_A";
-	else
-		name = "FW_MAIN_B";
-
-	return vboot_named_region_device(name, fw_main);
-}
-
-/**
- * Save non-volatile and/or secure data if needed.
- */
-static void save_if_needed(struct vb2_context *ctx)
-{
-	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving nvdata\n");
-		save_vbnv(ctx->nvdata);
-		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
-	}
-	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving secdata\n");
-		antirollback_write_space_firmware(ctx);
-		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
-	}
-}
-
-static uint32_t extend_pcrs(struct vb2_context *ctx)
-{
-	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
-	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
-}
-
-static void init_vb2_working_data(void)
-{
-	struct vb2_working_data *wd;
-	size_t work_size;
-
-	work_size = vb2_working_data_size();
-	wd = vboot_get_working_data();
-	memset(wd, 0, work_size);
-	/*
-	 * vboot prefers 16-byte alignment. This takes away 16 bytes
-	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
-	 */
-	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
-	wd->buffer_size = work_size - wd->buffer_offset;
-}
-
-/**
- * Verify and select the firmware in the RW image
- *
- * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
- * when per-stage verification is ready.
- */
-void verstage_main(void)
-{
-	struct vb2_context ctx;
-	struct region_device fw_main;
-	struct vb2_working_data *wd;
-	int rv;
-	init_vb2_working_data();
-	wd = vboot_get_working_data();
-	timestamp_add_now(TS_START_VBOOT);
-
-	/* Set up context and work buffer */
-	memset(&ctx, 0, sizeof(ctx));
-	ctx.workbuf = vboot_get_work_buffer(wd);
-	ctx.workbuf_size = wd->buffer_size;
-
-	/* Read nvdata from a non-volatile storage */
-	read_vbnv(ctx.nvdata);
-
-	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
-	 * check the return value here because vb2api_fw_phase1 will catch
-	 * invalid secdata and tell us what to do (=reboot). */
-	timestamp_add_now(TS_START_TPMINIT);
-	antirollback_read_space_firmware(&ctx);
-	timestamp_add_now(TS_END_TPMINIT);
-
-	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
-	    get_developer_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
-
-	if (get_recovery_mode_switch()) {
-		clear_recovery_mode_switch();
-		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
-		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
-			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
-	}
-
-	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
-
-	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
-		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
-
-	/* Do early init (set up secdata and NVRAM, load GBB) */
-	printk(BIOS_INFO, "Phase 1\n");
-	rv = vb2api_fw_phase1(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
-		/* If we need recovery mode, leave firmware selection now */
-		save_if_needed(&ctx);
-		extend_pcrs(&ctx);	/* ignore failures */
-		timestamp_add_now(TS_END_VBOOT);
-		return;
-	}
-
-	/* Determine which firmware slot to boot (based on NVRAM) */
-	printk(BIOS_INFO, "Phase 2\n");
-	rv = vb2api_fw_phase2(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	/* Try that slot (verify its keyblock and preamble) */
-	printk(BIOS_INFO, "Phase 3\n");
-	timestamp_add_now(TS_START_VERIFY_SLOT);
-	rv = vb2api_fw_phase3(&ctx);
-	timestamp_add_now(TS_END_VERIFY_SLOT);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	printk(BIOS_INFO, "Phase 4\n");
-	rv = locate_firmware(&ctx, &fw_main);
-	if (rv)
-		die("Failed to read FMAP to locate firmware");
-
-	rv = hash_body(&ctx, &fw_main);
-	save_if_needed(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		vboot_reboot();
-	}
-
-	rv = extend_pcrs(&ctx);
-	if (rv) {
-		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
+	console_init();
+	exception_init();
+	verstage_mainboard_init();
 
-	/* Lock TPM */
-	rv = antirollback_lock_space_firmware();
-	if (rv) {
-		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
-		save_if_needed(&ctx);
-		vboot_reboot();
+	if (IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) {
+		verstage_main();
+	} else {
+		run_romstage();
+		hlt();
 	}
-
-	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
-	vb2_set_selected_region(wd, &fw_main);
-	timestamp_add_now(TS_END_VBOOT);
 }
 
-#if IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)
-void main(void)
-{
-	console_init();
-	exception_init();
-	verstage_main();
-}
-#endif
+/* This is for boards that rely on main() for an entry point of a stage. */
+void main(void) __attribute__((alias ("verstage_chain_load")))
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index f4d5e11..3a9c89b 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -48,4 +48,10 @@ int vboot_enable_developer(void);
 
 void vboot_reboot(void);
 
+/* Main logic for verified boot. verstage() is the stage entry point
+ * while the verstage_main() is just the core logic. */
+void verstage_main(void);
+void verstage_mainboard_init(void);
+void verstage(void);
+
 #endif /* VBOOT_COMMON_H */


From gerrit at coreboot.org  Wed Sep 30 02:57:19 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 02:57:19 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: vboot: provide a
	unified flow for separate verstage
References: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+0@gerrit.coreboot.org>
Message-ID: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11744

-gerrit

commit 37830e40023dd0db030526015a4c482f66ca206f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 17:56:59 2015 -0500

    vboot: provide a unified flow for separate verstage
    
    The vboot verification in a stage proper is unified
    replacing duplicate code in the tegra SoC code. The
    original verstage.c file is renamed to reflect its
    real purpose. The support for a single verstage flow
    is added to the vboot2 directory proper.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/foster/Makefile.inc           |   1 -
 src/mainboard/google/foster/verstage.c             |  29 --
 src/soc/nvidia/tegra132/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra132/verstage.c                 |  48 ---
 src/soc/nvidia/tegra210/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra210/verstage.c                 |  45 ---
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |   3 +-
 src/vendorcode/google/chromeos/vboot2/misc.h       |   1 -
 .../google/chromeos/vboot2/vboot_logic.c           | 352 +++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot2/verstage.c   | 339 ++------------------
 src/vendorcode/google/chromeos/vboot_common.h      |   6 +
 11 files changed, 380 insertions(+), 448 deletions(-)

diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc
index 7b2329e..51208c7 100644
--- a/src/mainboard/google/foster/Makefile.inc
+++ b/src/mainboard/google/foster/Makefile.inc
@@ -32,7 +32,6 @@ bootblock-y += bootblock.c
 bootblock-y += pmic.c
 bootblock-y += reset.c
 
-verstage-y += verstage.c
 verstage-y += chromeos.c
 verstage-y += reset.c
 
diff --git a/src/mainboard/google/foster/verstage.c b/src/mainboard/google/foster/verstage.c
deleted file mode 100644
index d5bcd44..0000000
--- a/src/mainboard/google/foster/verstage.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <soc/addressmap.h>
-#include <soc/funitcfg.h>
-#include <soc/padconfig.h>
-#include <soc/verstage.h>
-#include <soc/nvidia/tegra/i2c.h>
-
-void verstage_mainboard_init(void)
-{
-}
diff --git a/src/soc/nvidia/tegra132/include/soc/verstage.h b/src/soc/nvidia/tegra132/include/soc/verstage.h
index df6a386..d54a111 100644
--- a/src/soc/nvidia/tegra132/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c
deleted file mode 100644
index d6eba9a..0000000
--- a/src/soc/nvidia/tegra132/verstage.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <arch/stages.h>
-#include <console/console.h>
-#include <soc/verstage.h>
-#include <program_loading.h>
-#include <timestamp.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	timestamp_add_now(TS_START_VBOOT);
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h
index 6c37218..d6564c9 100644
--- a/src/soc/nvidia/tegra210/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra210/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra210/verstage.c b/src/soc/nvidia/tegra210/verstage.c
deleted file mode 100644
index 6a4df29..0000000
--- a/src/soc/nvidia/tegra210/verstage.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <soc/verstage.h>
-#include <console/console.h>
-#include <program_loading.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index 21613ba..c2ee868 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -31,8 +31,9 @@ romstage-y += ../vboot_common.c
 ramstage-y += ../vboot_common.c
 
 bootblock-y += common.c
-libverstage-y += verstage.c
+libverstage-y += vboot_logic.c
 verstage-y += common.c
+verstage-y += verstage.c
 ifeq (${CONFIG_VBOOT2_MOCK_SECDATA},y)
 libverstage-y += secdata_mock.c
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/misc.h b/src/vendorcode/google/chromeos/vboot2/misc.h
index d4f9f48..305d0da 100644
--- a/src/vendorcode/google/chromeos/vboot2/misc.h
+++ b/src/vendorcode/google/chromeos/vboot2/misc.h
@@ -23,7 +23,6 @@
 #include "../vboot_common.h"
 
 void vboot_fill_handoff(void);
-void verstage_main(void);
 void *vboot_load_stage(int stage_index,
 		       struct region *fw_main,
 		       struct vboot_components *fw_info);
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
new file mode 100644
index 0000000..76355ec
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
@@ -0,0 +1,352 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <antirollback.h>
+#include <arch/exception.h>
+#include <assert.h>
+#include <console/console.h>
+#include <console/vtxprintf.h>
+#include <delay.h>
+#include <string.h>
+#include <timestamp.h>
+#include <vb2_api.h>
+
+#include "../chromeos.h"
+#include "misc.h"
+
+#define TODO_BLOCK_SIZE 1024
+
+static int is_slot_a(struct vb2_context *ctx)
+{
+	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
+}
+
+/* exports */
+
+void vb2ex_printf(const char *func, const char *fmt, ...)
+{
+	va_list args;
+
+	printk(BIOS_INFO, "VB2:%s() ", func);
+	va_start(args, fmt);
+	do_printk_va_list(BIOS_INFO, fmt, args);
+	va_end(args);
+
+	return;
+}
+
+int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
+{
+	uint32_t rv;
+	printk(BIOS_INFO, "Clearing TPM owner\n");
+	rv = tpm_clear_and_reenable();
+	if (rv)
+		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
+	return VB2_SUCCESS;
+}
+
+int vb2ex_read_resource(struct vb2_context *ctx,
+			enum vb2_resource_index index,
+			uint32_t offset,
+			void *buf,
+			uint32_t size)
+{
+	struct region_device rdev;
+	const char *name;
+
+	switch (index) {
+	case VB2_RES_GBB:
+		name = "GBB";
+		break;
+	case VB2_RES_FW_VBLOCK:
+		if (is_slot_a(ctx))
+			name = "VBLOCK_A";
+		else
+			name = "VBLOCK_B";
+		break;
+	default:
+		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
+	}
+
+	if (vboot_named_region_device(name, &rdev))
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	if (rdev_readat(&rdev, buf, offset, size) != size)
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	return VB2_SUCCESS;
+}
+
+/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
+			       uint32_t data_size)
+{
+	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
+{
+	uint64_t load_ts;
+	uint32_t expected_size;
+	uint8_t block[TODO_BLOCK_SIZE];
+	size_t block_size = sizeof(block);
+	size_t offset;
+	int rv;
+
+	/*
+	 * Since loading the firmware and calculating its hash is intertwined,
+	 * we use this little trick to measure them separately and pretend it
+	 * was first loaded and then hashed in one piece with the timestamps.
+	 * (This split won't make sense with memory-mapped media like on x86.)
+	 */
+	load_ts = timestamp_get();
+	timestamp_add(TS_START_HASH_BODY, load_ts);
+
+	expected_size = region_device_sz(fw_main);
+	offset = 0;
+
+	/* Start the body hash */
+	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
+	if (rv)
+		return rv;
+
+	/* Extend over the body */
+	while (expected_size) {
+		uint64_t temp_ts;
+		if (block_size > expected_size)
+			block_size = expected_size;
+
+		temp_ts = timestamp_get();
+		if (rdev_readat(fw_main, block, offset, block_size) < 0)
+			return VB2_ERROR_UNKNOWN;
+		load_ts += timestamp_get() - temp_ts;
+
+		rv = vb2api_extend_hash(ctx, block, block_size);
+		if (rv)
+			return rv;
+
+		expected_size -= block_size;
+		offset += block_size;
+	}
+
+	timestamp_add(TS_DONE_LOADING, load_ts);
+	timestamp_add_now(TS_DONE_HASHING);
+
+	/* Check the result (with RSA signature verification) */
+	rv = vb2api_check_hash(ctx);
+	if (rv)
+		return rv;
+
+	timestamp_add_now(TS_END_HASH_BODY);
+
+	return VB2_SUCCESS;
+}
+
+static int locate_firmware(struct vb2_context *ctx,
+				struct region_device *fw_main)
+{
+	const char *name;
+
+	if (is_slot_a(ctx))
+		name = "FW_MAIN_A";
+	else
+		name = "FW_MAIN_B";
+
+	return vboot_named_region_device(name, fw_main);
+}
+
+/**
+ * Save non-volatile and/or secure data if needed.
+ */
+static void save_if_needed(struct vb2_context *ctx)
+{
+	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving nvdata\n");
+		save_vbnv(ctx->nvdata);
+		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
+	}
+	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving secdata\n");
+		antirollback_write_space_firmware(ctx);
+		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
+	}
+}
+
+static uint32_t extend_pcrs(struct vb2_context *ctx)
+{
+	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
+	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
+}
+
+static void init_vb2_working_data(void)
+{
+	struct vb2_working_data *wd;
+	size_t work_size;
+
+	work_size = vb2_working_data_size();
+	wd = vboot_get_working_data();
+	memset(wd, 0, work_size);
+	/*
+	 * vboot prefers 16-byte alignment. This takes away 16 bytes
+	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
+	 */
+	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
+	wd->buffer_size = work_size - wd->buffer_offset;
+}
+
+/**
+ * Verify and select the firmware in the RW image
+ *
+ * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
+ * when per-stage verification is ready.
+ */
+void verstage_main(void)
+{
+	struct vb2_context ctx;
+	struct region_device fw_main;
+	struct vb2_working_data *wd;
+	int rv;
+	init_vb2_working_data();
+	wd = vboot_get_working_data();
+	timestamp_add_now(TS_START_VBOOT);
+
+	/* Set up context and work buffer */
+	memset(&ctx, 0, sizeof(ctx));
+	ctx.workbuf = vboot_get_work_buffer(wd);
+	ctx.workbuf_size = wd->buffer_size;
+
+	/* Read nvdata from a non-volatile storage */
+	read_vbnv(ctx.nvdata);
+
+	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
+	 * check the return value here because vb2api_fw_phase1 will catch
+	 * invalid secdata and tell us what to do (=reboot). */
+	timestamp_add_now(TS_START_TPMINIT);
+	antirollback_read_space_firmware(&ctx);
+	timestamp_add_now(TS_END_TPMINIT);
+
+	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
+	    get_developer_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
+
+	if (get_recovery_mode_switch()) {
+		clear_recovery_mode_switch();
+		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
+		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
+			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
+	}
+
+	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
+
+	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
+		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
+
+	/* Do early init (set up secdata and NVRAM, load GBB) */
+	printk(BIOS_INFO, "Phase 1\n");
+	rv = vb2api_fw_phase1(&ctx);
+
+	if (rv) {
+		/*
+		 * If vb2api_fw_phase1 fails, check for return value.
+		 * If it is set to VB2_ERROR_API_PHASE1_RECOVERY, then continue
+		 * into recovery mode.
+		 * For any other error code, save context if needed and reboot.
+		 */
+		if (rv == VB2_ERROR_API_PHASE1_RECOVERY) {
+			printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
+			save_if_needed(&ctx);
+			extend_pcrs(&ctx);	/* ignore failures */
+			timestamp_add_now(TS_END_VBOOT);
+			return;
+		}
+
+		printk(BIOS_INFO, "Reboot reqested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Determine which firmware slot to boot (based on NVRAM) */
+	printk(BIOS_INFO, "Phase 2\n");
+	rv = vb2api_fw_phase2(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Try that slot (verify its keyblock and preamble) */
+	printk(BIOS_INFO, "Phase 3\n");
+	timestamp_add_now(TS_START_VERIFY_SLOT);
+	rv = vb2api_fw_phase3(&ctx);
+	timestamp_add_now(TS_END_VERIFY_SLOT);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Phase 4\n");
+	rv = locate_firmware(&ctx, &fw_main);
+	if (rv)
+		die("Failed to read FMAP to locate firmware");
+
+	rv = hash_body(&ctx, &fw_main);
+	save_if_needed(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		vboot_reboot();
+	}
+
+	rv = extend_pcrs(&ctx);
+	if (rv) {
+		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Lock TPM */
+	rv = antirollback_lock_space_firmware();
+	if (rv) {
+		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
+	vb2_set_selected_region(wd, &fw_main);
+	timestamp_add_now(TS_END_VBOOT);
+}
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 7803d39..3938ebf 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2014 Google Inc.
+ * Copyright 2015 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,7 +9,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -17,333 +17,30 @@
  * Foundation, Inc.
  */
 
-#include <antirollback.h>
 #include <arch/exception.h>
-#include <assert.h>
+#include <arch/hlt.h>
 #include <console/console.h>
-#include <console/vtxprintf.h>
-#include <delay.h>
-#include <string.h>
-#include <timestamp.h>
-#include <vb2_api.h>
+#include <program_loading.h>
+#include "../vboot_common.h"
 
-#include "../chromeos.h"
-#include "misc.h"
-
-#define TODO_BLOCK_SIZE 1024
-
-static int is_slot_a(struct vb2_context *ctx)
-{
-	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
-}
-
-/* exports */
-
-void vb2ex_printf(const char *func, const char *fmt, ...)
+void __attribute__((weak)) verstage_mainboard_init(void)
 {
-	va_list args;
-
-	printk(BIOS_INFO, "VB2:%s() ", func);
-	va_start(args, fmt);
-	do_printk_va_list(BIOS_INFO, fmt, args);
-	va_end(args);
-
-	return;
-}
-
-int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
-{
-	uint32_t rv;
-	printk(BIOS_INFO, "Clearing TPM owner\n");
-	rv = tpm_clear_and_reenable();
-	if (rv)
-		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
-	return VB2_SUCCESS;
+	/* Default empty implementation. */
 }
 
-int vb2ex_read_resource(struct vb2_context *ctx,
-			enum vb2_resource_index index,
-			uint32_t offset,
-			void *buf,
-			uint32_t size)
+void verstage(void)
 {
-	struct region_device rdev;
-	const char *name;
-
-	switch (index) {
-	case VB2_RES_GBB:
-		name = "GBB";
-		break;
-	case VB2_RES_FW_VBLOCK:
-		if (is_slot_a(ctx))
-			name = "VBLOCK_A";
-		else
-			name = "VBLOCK_B";
-		break;
-	default:
-		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
-	}
-
-	if (vboot_named_region_device(name, &rdev))
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	if (rdev_readat(&rdev, buf, offset, size) != size)
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	return VB2_SUCCESS;
-}
-
-/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
-			       uint32_t data_size)
-{
-	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
-{
-	uint64_t load_ts;
-	uint32_t expected_size;
-	uint8_t block[TODO_BLOCK_SIZE];
-	size_t block_size = sizeof(block);
-	size_t offset;
-	int rv;
-
-	/*
-	 * Since loading the firmware and calculating its hash is intertwined,
-	 * we use this little trick to measure them separately and pretend it
-	 * was first loaded and then hashed in one piece with the timestamps.
-	 * (This split won't make sense with memory-mapped media like on x86.)
-	 */
-	load_ts = timestamp_get();
-	timestamp_add(TS_START_HASH_BODY, load_ts);
-
-	expected_size = region_device_sz(fw_main);
-	offset = 0;
-
-	/* Start the body hash */
-	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
-	if (rv)
-		return rv;
-
-	/* Extend over the body */
-	while (expected_size) {
-		uint64_t temp_ts;
-		if (block_size > expected_size)
-			block_size = expected_size;
-
-		temp_ts = timestamp_get();
-		if (rdev_readat(fw_main, block, offset, block_size) < 0)
-			return VB2_ERROR_UNKNOWN;
-		load_ts += timestamp_get() - temp_ts;
-
-		rv = vb2api_extend_hash(ctx, block, block_size);
-		if (rv)
-			return rv;
-
-		expected_size -= block_size;
-		offset += block_size;
-	}
-
-	timestamp_add(TS_DONE_LOADING, load_ts);
-	timestamp_add_now(TS_DONE_HASHING);
-
-	/* Check the result (with RSA signature verification) */
-	rv = vb2api_check_hash(ctx);
-	if (rv)
-		return rv;
-
-	timestamp_add_now(TS_END_HASH_BODY);
-
-	return VB2_SUCCESS;
-}
-
-static int locate_firmware(struct vb2_context *ctx,
-				struct region_device *fw_main)
-{
-	const char *name;
-
-	if (is_slot_a(ctx))
-		name = "FW_MAIN_A";
-	else
-		name = "FW_MAIN_B";
-
-	return vboot_named_region_device(name, fw_main);
-}
-
-/**
- * Save non-volatile and/or secure data if needed.
- */
-static void save_if_needed(struct vb2_context *ctx)
-{
-	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving nvdata\n");
-		save_vbnv(ctx->nvdata);
-		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
-	}
-	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving secdata\n");
-		antirollback_write_space_firmware(ctx);
-		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
-	}
-}
-
-static uint32_t extend_pcrs(struct vb2_context *ctx)
-{
-	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
-	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
-}
-
-static void init_vb2_working_data(void)
-{
-	struct vb2_working_data *wd;
-	size_t work_size;
-
-	work_size = vb2_working_data_size();
-	wd = vboot_get_working_data();
-	memset(wd, 0, work_size);
-	/*
-	 * vboot prefers 16-byte alignment. This takes away 16 bytes
-	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
-	 */
-	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
-	wd->buffer_size = work_size - wd->buffer_offset;
-}
-
-/**
- * Verify and select the firmware in the RW image
- *
- * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
- * when per-stage verification is ready.
- */
-void verstage_main(void)
-{
-	struct vb2_context ctx;
-	struct region_device fw_main;
-	struct vb2_working_data *wd;
-	int rv;
-	init_vb2_working_data();
-	wd = vboot_get_working_data();
-	timestamp_add_now(TS_START_VBOOT);
-
-	/* Set up context and work buffer */
-	memset(&ctx, 0, sizeof(ctx));
-	ctx.workbuf = vboot_get_work_buffer(wd);
-	ctx.workbuf_size = wd->buffer_size;
-
-	/* Read nvdata from a non-volatile storage */
-	read_vbnv(ctx.nvdata);
-
-	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
-	 * check the return value here because vb2api_fw_phase1 will catch
-	 * invalid secdata and tell us what to do (=reboot). */
-	timestamp_add_now(TS_START_TPMINIT);
-	antirollback_read_space_firmware(&ctx);
-	timestamp_add_now(TS_END_TPMINIT);
-
-	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
-	    get_developer_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
-
-	if (get_recovery_mode_switch()) {
-		clear_recovery_mode_switch();
-		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
-		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
-			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
-	}
-
-	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
-
-	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
-		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
-
-	/* Do early init (set up secdata and NVRAM, load GBB) */
-	printk(BIOS_INFO, "Phase 1\n");
-	rv = vb2api_fw_phase1(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
-		/* If we need recovery mode, leave firmware selection now */
-		save_if_needed(&ctx);
-		extend_pcrs(&ctx);	/* ignore failures */
-		timestamp_add_now(TS_END_VBOOT);
-		return;
-	}
-
-	/* Determine which firmware slot to boot (based on NVRAM) */
-	printk(BIOS_INFO, "Phase 2\n");
-	rv = vb2api_fw_phase2(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	/* Try that slot (verify its keyblock and preamble) */
-	printk(BIOS_INFO, "Phase 3\n");
-	timestamp_add_now(TS_START_VERIFY_SLOT);
-	rv = vb2api_fw_phase3(&ctx);
-	timestamp_add_now(TS_END_VERIFY_SLOT);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	printk(BIOS_INFO, "Phase 4\n");
-	rv = locate_firmware(&ctx, &fw_main);
-	if (rv)
-		die("Failed to read FMAP to locate firmware");
-
-	rv = hash_body(&ctx, &fw_main);
-	save_if_needed(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		vboot_reboot();
-	}
-
-	rv = extend_pcrs(&ctx);
-	if (rv) {
-		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
+	console_init();
+	exception_init();
+	verstage_mainboard_init();
 
-	/* Lock TPM */
-	rv = antirollback_lock_space_firmware();
-	if (rv) {
-		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
-		save_if_needed(&ctx);
-		vboot_reboot();
+	if (IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) {
+		verstage_main();
+	} else {
+		run_romstage();
+		hlt();
 	}
-
-	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
-	vb2_set_selected_region(wd, &fw_main);
-	timestamp_add_now(TS_END_VBOOT);
 }
 
-#if IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)
-void main(void)
-{
-	console_init();
-	exception_init();
-	verstage_main();
-}
-#endif
+/* This is for boards that rely on main() for an entry point of a stage. */
+void main(void) __attribute__((alias ("verstage_chain_load")));
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index f4d5e11..3a9c89b 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -48,4 +48,10 @@ int vboot_enable_developer(void);
 
 void vboot_reboot(void);
 
+/* Main logic for verified boot. verstage() is the stage entry point
+ * while the verstage_main() is just the core logic. */
+void verstage_main(void);
+void verstage_mainboard_init(void);
+void verstage(void);
+
 #endif /* VBOOT_COMMON_H */


From gerrit at coreboot.org  Wed Sep 30 03:03:05 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 03:03:05 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: vboot: provide a
	unified flow for separate verstage
References: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+0@gerrit.coreboot.org>
Message-ID: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11744

-gerrit

commit 5a526844a93a9cf5cc24b9a3b8a437f2700144f3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 17:56:59 2015 -0500

    vboot: provide a unified flow for separate verstage
    
    The vboot verification in a stage proper is unified
    replacing duplicate code in the tegra SoC code. The
    original verstage.c file is renamed to reflect its
    real purpose. The support for a single verstage flow
    is added to the vboot2 directory proper.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/foster/Makefile.inc           |   1 -
 src/mainboard/google/foster/verstage.c             |  29 --
 src/soc/nvidia/tegra132/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra132/verstage.c                 |  48 ---
 src/soc/nvidia/tegra210/include/soc/verstage.h     |   2 +-
 src/soc/nvidia/tegra210/verstage.c                 |  45 ---
 src/vendorcode/google/chromeos/vboot2/Makefile.inc |   3 +-
 src/vendorcode/google/chromeos/vboot2/misc.h       |   1 -
 .../google/chromeos/vboot2/vboot_logic.c           | 352 +++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot2/verstage.c   | 339 ++------------------
 src/vendorcode/google/chromeos/vboot_common.h      |   6 +
 11 files changed, 380 insertions(+), 448 deletions(-)

diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc
index 7b2329e..51208c7 100644
--- a/src/mainboard/google/foster/Makefile.inc
+++ b/src/mainboard/google/foster/Makefile.inc
@@ -32,7 +32,6 @@ bootblock-y += bootblock.c
 bootblock-y += pmic.c
 bootblock-y += reset.c
 
-verstage-y += verstage.c
 verstage-y += chromeos.c
 verstage-y += reset.c
 
diff --git a/src/mainboard/google/foster/verstage.c b/src/mainboard/google/foster/verstage.c
deleted file mode 100644
index d5bcd44..0000000
--- a/src/mainboard/google/foster/verstage.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <soc/addressmap.h>
-#include <soc/funitcfg.h>
-#include <soc/padconfig.h>
-#include <soc/verstage.h>
-#include <soc/nvidia/tegra/i2c.h>
-
-void verstage_mainboard_init(void)
-{
-}
diff --git a/src/soc/nvidia/tegra132/include/soc/verstage.h b/src/soc/nvidia/tegra132/include/soc/verstage.h
index df6a386..d54a111 100644
--- a/src/soc/nvidia/tegra132/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c
deleted file mode 100644
index d6eba9a..0000000
--- a/src/soc/nvidia/tegra132/verstage.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <arch/stages.h>
-#include <console/console.h>
-#include <soc/verstage.h>
-#include <program_loading.h>
-#include <timestamp.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	timestamp_add_now(TS_START_VBOOT);
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h
index 6c37218..d6564c9 100644
--- a/src/soc/nvidia/tegra210/include/soc/verstage.h
+++ b/src/soc/nvidia/tegra210/include/soc/verstage.h
@@ -20,6 +20,6 @@
 #ifndef __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 #define __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__
 
-void verstage_mainboard_init(void);
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #endif /* __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra210/verstage.c b/src/soc/nvidia/tegra210/verstage.c
deleted file mode 100644
index 6a4df29..0000000
--- a/src/soc/nvidia/tegra210/verstage.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <soc/verstage.h>
-#include <console/console.h>
-#include <program_loading.h>
-
-void __attribute__((weak)) verstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-static void verstage(void)
-{
-	console_init();
-	exception_init();
-	verstage_mainboard_init();
-
-	run_romstage();
-}
-
-void main(void)
-{
-	verstage();
-	hlt();
-}
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index 21613ba..c2ee868 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -31,8 +31,9 @@ romstage-y += ../vboot_common.c
 ramstage-y += ../vboot_common.c
 
 bootblock-y += common.c
-libverstage-y += verstage.c
+libverstage-y += vboot_logic.c
 verstage-y += common.c
+verstage-y += verstage.c
 ifeq (${CONFIG_VBOOT2_MOCK_SECDATA},y)
 libverstage-y += secdata_mock.c
 else
diff --git a/src/vendorcode/google/chromeos/vboot2/misc.h b/src/vendorcode/google/chromeos/vboot2/misc.h
index d4f9f48..305d0da 100644
--- a/src/vendorcode/google/chromeos/vboot2/misc.h
+++ b/src/vendorcode/google/chromeos/vboot2/misc.h
@@ -23,7 +23,6 @@
 #include "../vboot_common.h"
 
 void vboot_fill_handoff(void);
-void verstage_main(void);
 void *vboot_load_stage(int stage_index,
 		       struct region *fw_main,
 		       struct vboot_components *fw_info);
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
new file mode 100644
index 0000000..76355ec
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
@@ -0,0 +1,352 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <antirollback.h>
+#include <arch/exception.h>
+#include <assert.h>
+#include <console/console.h>
+#include <console/vtxprintf.h>
+#include <delay.h>
+#include <string.h>
+#include <timestamp.h>
+#include <vb2_api.h>
+
+#include "../chromeos.h"
+#include "misc.h"
+
+#define TODO_BLOCK_SIZE 1024
+
+static int is_slot_a(struct vb2_context *ctx)
+{
+	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
+}
+
+/* exports */
+
+void vb2ex_printf(const char *func, const char *fmt, ...)
+{
+	va_list args;
+
+	printk(BIOS_INFO, "VB2:%s() ", func);
+	va_start(args, fmt);
+	do_printk_va_list(BIOS_INFO, fmt, args);
+	va_end(args);
+
+	return;
+}
+
+int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
+{
+	uint32_t rv;
+	printk(BIOS_INFO, "Clearing TPM owner\n");
+	rv = tpm_clear_and_reenable();
+	if (rv)
+		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
+	return VB2_SUCCESS;
+}
+
+int vb2ex_read_resource(struct vb2_context *ctx,
+			enum vb2_resource_index index,
+			uint32_t offset,
+			void *buf,
+			uint32_t size)
+{
+	struct region_device rdev;
+	const char *name;
+
+	switch (index) {
+	case VB2_RES_GBB:
+		name = "GBB";
+		break;
+	case VB2_RES_FW_VBLOCK:
+		if (is_slot_a(ctx))
+			name = "VBLOCK_A";
+		else
+			name = "VBLOCK_B";
+		break;
+	default:
+		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
+	}
+
+	if (vboot_named_region_device(name, &rdev))
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	if (rdev_readat(&rdev, buf, offset, size) != size)
+		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
+
+	return VB2_SUCCESS;
+}
+
+/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
+			       uint32_t data_size)
+{
+	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+__attribute__((weak))
+int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
+{
+	BUG();	/* Should never get called if init() returned an error. */
+	return VB2_ERROR_UNKNOWN;
+}
+
+static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
+{
+	uint64_t load_ts;
+	uint32_t expected_size;
+	uint8_t block[TODO_BLOCK_SIZE];
+	size_t block_size = sizeof(block);
+	size_t offset;
+	int rv;
+
+	/*
+	 * Since loading the firmware and calculating its hash is intertwined,
+	 * we use this little trick to measure them separately and pretend it
+	 * was first loaded and then hashed in one piece with the timestamps.
+	 * (This split won't make sense with memory-mapped media like on x86.)
+	 */
+	load_ts = timestamp_get();
+	timestamp_add(TS_START_HASH_BODY, load_ts);
+
+	expected_size = region_device_sz(fw_main);
+	offset = 0;
+
+	/* Start the body hash */
+	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
+	if (rv)
+		return rv;
+
+	/* Extend over the body */
+	while (expected_size) {
+		uint64_t temp_ts;
+		if (block_size > expected_size)
+			block_size = expected_size;
+
+		temp_ts = timestamp_get();
+		if (rdev_readat(fw_main, block, offset, block_size) < 0)
+			return VB2_ERROR_UNKNOWN;
+		load_ts += timestamp_get() - temp_ts;
+
+		rv = vb2api_extend_hash(ctx, block, block_size);
+		if (rv)
+			return rv;
+
+		expected_size -= block_size;
+		offset += block_size;
+	}
+
+	timestamp_add(TS_DONE_LOADING, load_ts);
+	timestamp_add_now(TS_DONE_HASHING);
+
+	/* Check the result (with RSA signature verification) */
+	rv = vb2api_check_hash(ctx);
+	if (rv)
+		return rv;
+
+	timestamp_add_now(TS_END_HASH_BODY);
+
+	return VB2_SUCCESS;
+}
+
+static int locate_firmware(struct vb2_context *ctx,
+				struct region_device *fw_main)
+{
+	const char *name;
+
+	if (is_slot_a(ctx))
+		name = "FW_MAIN_A";
+	else
+		name = "FW_MAIN_B";
+
+	return vboot_named_region_device(name, fw_main);
+}
+
+/**
+ * Save non-volatile and/or secure data if needed.
+ */
+static void save_if_needed(struct vb2_context *ctx)
+{
+	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving nvdata\n");
+		save_vbnv(ctx->nvdata);
+		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
+	}
+	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
+		printk(BIOS_INFO, "Saving secdata\n");
+		antirollback_write_space_firmware(ctx);
+		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
+	}
+}
+
+static uint32_t extend_pcrs(struct vb2_context *ctx)
+{
+	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
+	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
+}
+
+static void init_vb2_working_data(void)
+{
+	struct vb2_working_data *wd;
+	size_t work_size;
+
+	work_size = vb2_working_data_size();
+	wd = vboot_get_working_data();
+	memset(wd, 0, work_size);
+	/*
+	 * vboot prefers 16-byte alignment. This takes away 16 bytes
+	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
+	 */
+	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
+	wd->buffer_size = work_size - wd->buffer_offset;
+}
+
+/**
+ * Verify and select the firmware in the RW image
+ *
+ * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
+ * when per-stage verification is ready.
+ */
+void verstage_main(void)
+{
+	struct vb2_context ctx;
+	struct region_device fw_main;
+	struct vb2_working_data *wd;
+	int rv;
+	init_vb2_working_data();
+	wd = vboot_get_working_data();
+	timestamp_add_now(TS_START_VBOOT);
+
+	/* Set up context and work buffer */
+	memset(&ctx, 0, sizeof(ctx));
+	ctx.workbuf = vboot_get_work_buffer(wd);
+	ctx.workbuf_size = wd->buffer_size;
+
+	/* Read nvdata from a non-volatile storage */
+	read_vbnv(ctx.nvdata);
+
+	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
+	 * check the return value here because vb2api_fw_phase1 will catch
+	 * invalid secdata and tell us what to do (=reboot). */
+	timestamp_add_now(TS_START_TPMINIT);
+	antirollback_read_space_firmware(&ctx);
+	timestamp_add_now(TS_END_TPMINIT);
+
+	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
+	    get_developer_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
+
+	if (get_recovery_mode_switch()) {
+		clear_recovery_mode_switch();
+		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
+		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
+			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
+	}
+
+	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
+		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
+
+	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
+		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
+
+	/* Do early init (set up secdata and NVRAM, load GBB) */
+	printk(BIOS_INFO, "Phase 1\n");
+	rv = vb2api_fw_phase1(&ctx);
+
+	if (rv) {
+		/*
+		 * If vb2api_fw_phase1 fails, check for return value.
+		 * If it is set to VB2_ERROR_API_PHASE1_RECOVERY, then continue
+		 * into recovery mode.
+		 * For any other error code, save context if needed and reboot.
+		 */
+		if (rv == VB2_ERROR_API_PHASE1_RECOVERY) {
+			printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
+			save_if_needed(&ctx);
+			extend_pcrs(&ctx);	/* ignore failures */
+			timestamp_add_now(TS_END_VBOOT);
+			return;
+		}
+
+		printk(BIOS_INFO, "Reboot reqested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Determine which firmware slot to boot (based on NVRAM) */
+	printk(BIOS_INFO, "Phase 2\n");
+	rv = vb2api_fw_phase2(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Try that slot (verify its keyblock and preamble) */
+	printk(BIOS_INFO, "Phase 3\n");
+	timestamp_add_now(TS_START_VERIFY_SLOT);
+	rv = vb2api_fw_phase3(&ctx);
+	timestamp_add_now(TS_END_VERIFY_SLOT);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Phase 4\n");
+	rv = locate_firmware(&ctx, &fw_main);
+	if (rv)
+		die("Failed to read FMAP to locate firmware");
+
+	rv = hash_body(&ctx, &fw_main);
+	save_if_needed(&ctx);
+	if (rv) {
+		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
+		vboot_reboot();
+	}
+
+	rv = extend_pcrs(&ctx);
+	if (rv) {
+		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	/* Lock TPM */
+	rv = antirollback_lock_space_firmware();
+	if (rv) {
+		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
+		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
+		save_if_needed(&ctx);
+		vboot_reboot();
+	}
+
+	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
+	vb2_set_selected_region(wd, &fw_main);
+	timestamp_add_now(TS_END_VBOOT);
+}
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 7803d39..9556359 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2014 Google Inc.
+ * Copyright 2015 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,7 +9,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -17,333 +17,30 @@
  * Foundation, Inc.
  */
 
-#include <antirollback.h>
 #include <arch/exception.h>
-#include <assert.h>
+#include <arch/hlt.h>
 #include <console/console.h>
-#include <console/vtxprintf.h>
-#include <delay.h>
-#include <string.h>
-#include <timestamp.h>
-#include <vb2_api.h>
+#include <program_loading.h>
+#include "../vboot_common.h"
 
-#include "../chromeos.h"
-#include "misc.h"
-
-#define TODO_BLOCK_SIZE 1024
-
-static int is_slot_a(struct vb2_context *ctx)
-{
-	return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B);
-}
-
-/* exports */
-
-void vb2ex_printf(const char *func, const char *fmt, ...)
+void __attribute__((weak)) verstage_mainboard_init(void)
 {
-	va_list args;
-
-	printk(BIOS_INFO, "VB2:%s() ", func);
-	va_start(args, fmt);
-	do_printk_va_list(BIOS_INFO, fmt, args);
-	va_end(args);
-
-	return;
-}
-
-int vb2ex_tpm_clear_owner(struct vb2_context *ctx)
-{
-	uint32_t rv;
-	printk(BIOS_INFO, "Clearing TPM owner\n");
-	rv = tpm_clear_and_reenable();
-	if (rv)
-		return VB2_ERROR_EX_TPM_CLEAR_OWNER;
-	return VB2_SUCCESS;
+	/* Default empty implementation. */
 }
 
-int vb2ex_read_resource(struct vb2_context *ctx,
-			enum vb2_resource_index index,
-			uint32_t offset,
-			void *buf,
-			uint32_t size)
+void verstage(void)
 {
-	struct region_device rdev;
-	const char *name;
-
-	switch (index) {
-	case VB2_RES_GBB:
-		name = "GBB";
-		break;
-	case VB2_RES_FW_VBLOCK:
-		if (is_slot_a(ctx))
-			name = "VBLOCK_A";
-		else
-			name = "VBLOCK_B";
-		break;
-	default:
-		return VB2_ERROR_EX_READ_RESOURCE_INDEX;
-	}
-
-	if (vboot_named_region_device(name, &rdev))
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	if (rdev_readat(&rdev, buf, offset, size) != size)
-		return VB2_ERROR_EX_READ_RESOURCE_SIZE;
-
-	return VB2_SUCCESS;
-}
-
-/* No-op stubs that can be overridden by SoCs with hardware crypto support. */
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
-			       uint32_t data_size)
-{
-	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-__attribute__((weak))
-int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
-{
-	BUG();	/* Should never get called if init() returned an error. */
-	return VB2_ERROR_UNKNOWN;
-}
-
-static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
-{
-	uint64_t load_ts;
-	uint32_t expected_size;
-	uint8_t block[TODO_BLOCK_SIZE];
-	size_t block_size = sizeof(block);
-	size_t offset;
-	int rv;
-
-	/*
-	 * Since loading the firmware and calculating its hash is intertwined,
-	 * we use this little trick to measure them separately and pretend it
-	 * was first loaded and then hashed in one piece with the timestamps.
-	 * (This split won't make sense with memory-mapped media like on x86.)
-	 */
-	load_ts = timestamp_get();
-	timestamp_add(TS_START_HASH_BODY, load_ts);
-
-	expected_size = region_device_sz(fw_main);
-	offset = 0;
-
-	/* Start the body hash */
-	rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
-	if (rv)
-		return rv;
-
-	/* Extend over the body */
-	while (expected_size) {
-		uint64_t temp_ts;
-		if (block_size > expected_size)
-			block_size = expected_size;
-
-		temp_ts = timestamp_get();
-		if (rdev_readat(fw_main, block, offset, block_size) < 0)
-			return VB2_ERROR_UNKNOWN;
-		load_ts += timestamp_get() - temp_ts;
-
-		rv = vb2api_extend_hash(ctx, block, block_size);
-		if (rv)
-			return rv;
-
-		expected_size -= block_size;
-		offset += block_size;
-	}
-
-	timestamp_add(TS_DONE_LOADING, load_ts);
-	timestamp_add_now(TS_DONE_HASHING);
-
-	/* Check the result (with RSA signature verification) */
-	rv = vb2api_check_hash(ctx);
-	if (rv)
-		return rv;
-
-	timestamp_add_now(TS_END_HASH_BODY);
-
-	return VB2_SUCCESS;
-}
-
-static int locate_firmware(struct vb2_context *ctx,
-				struct region_device *fw_main)
-{
-	const char *name;
-
-	if (is_slot_a(ctx))
-		name = "FW_MAIN_A";
-	else
-		name = "FW_MAIN_B";
-
-	return vboot_named_region_device(name, fw_main);
-}
-
-/**
- * Save non-volatile and/or secure data if needed.
- */
-static void save_if_needed(struct vb2_context *ctx)
-{
-	if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving nvdata\n");
-		save_vbnv(ctx->nvdata);
-		ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED;
-	}
-	if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) {
-		printk(BIOS_INFO, "Saving secdata\n");
-		antirollback_write_space_firmware(ctx);
-		ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED;
-	}
-}
-
-static uint32_t extend_pcrs(struct vb2_context *ctx)
-{
-	return tpm_extend_pcr(ctx, 0, BOOT_MODE_PCR) ||
-	       tpm_extend_pcr(ctx, 1, HWID_DIGEST_PCR);
-}
-
-static void init_vb2_working_data(void)
-{
-	struct vb2_working_data *wd;
-	size_t work_size;
-
-	work_size = vb2_working_data_size();
-	wd = vboot_get_working_data();
-	memset(wd, 0, work_size);
-	/*
-	 * vboot prefers 16-byte alignment. This takes away 16 bytes
-	 * from the VBOOT2_WORK region, but the vboot devs said that's okay.
-	 */
-	wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
-	wd->buffer_size = work_size - wd->buffer_offset;
-}
-
-/**
- * Verify and select the firmware in the RW image
- *
- * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
- * when per-stage verification is ready.
- */
-void verstage_main(void)
-{
-	struct vb2_context ctx;
-	struct region_device fw_main;
-	struct vb2_working_data *wd;
-	int rv;
-	init_vb2_working_data();
-	wd = vboot_get_working_data();
-	timestamp_add_now(TS_START_VBOOT);
-
-	/* Set up context and work buffer */
-	memset(&ctx, 0, sizeof(ctx));
-	ctx.workbuf = vboot_get_work_buffer(wd);
-	ctx.workbuf_size = wd->buffer_size;
-
-	/* Read nvdata from a non-volatile storage */
-	read_vbnv(ctx.nvdata);
-
-	/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
-	 * check the return value here because vb2api_fw_phase1 will catch
-	 * invalid secdata and tell us what to do (=reboot). */
-	timestamp_add_now(TS_START_TPMINIT);
-	antirollback_read_space_firmware(&ctx);
-	timestamp_add_now(TS_END_TPMINIT);
-
-	if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) &&
-	    get_developer_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
-
-	if (get_recovery_mode_switch()) {
-		clear_recovery_mode_switch();
-		ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
-		if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
-			ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
-	}
-
-	if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
-		ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
-
-	if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
-		ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
-
-	/* Do early init (set up secdata and NVRAM, load GBB) */
-	printk(BIOS_INFO, "Phase 1\n");
-	rv = vb2api_fw_phase1(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Recovery requested (%x)\n", rv);
-		/* If we need recovery mode, leave firmware selection now */
-		save_if_needed(&ctx);
-		extend_pcrs(&ctx);	/* ignore failures */
-		timestamp_add_now(TS_END_VBOOT);
-		return;
-	}
-
-	/* Determine which firmware slot to boot (based on NVRAM) */
-	printk(BIOS_INFO, "Phase 2\n");
-	rv = vb2api_fw_phase2(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	/* Try that slot (verify its keyblock and preamble) */
-	printk(BIOS_INFO, "Phase 3\n");
-	timestamp_add_now(TS_START_VERIFY_SLOT);
-	rv = vb2api_fw_phase3(&ctx);
-	timestamp_add_now(TS_END_VERIFY_SLOT);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
-
-	printk(BIOS_INFO, "Phase 4\n");
-	rv = locate_firmware(&ctx, &fw_main);
-	if (rv)
-		die("Failed to read FMAP to locate firmware");
-
-	rv = hash_body(&ctx, &fw_main);
-	save_if_needed(&ctx);
-	if (rv) {
-		printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
-		vboot_reboot();
-	}
-
-	rv = extend_pcrs(&ctx);
-	if (rv) {
-		printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv);
-		save_if_needed(&ctx);
-		vboot_reboot();
-	}
+	console_init();
+	exception_init();
+	verstage_mainboard_init();
 
-	/* Lock TPM */
-	rv = antirollback_lock_space_firmware();
-	if (rv) {
-		printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
-		vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0);
-		save_if_needed(&ctx);
-		vboot_reboot();
+	if (IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) {
+		verstage_main();
+	} else {
+		run_romstage();
+		hlt();
 	}
-
-	printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
-	vb2_set_selected_region(wd, &fw_main);
-	timestamp_add_now(TS_END_VBOOT);
 }
 
-#if IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)
-void main(void)
-{
-	console_init();
-	exception_init();
-	verstage_main();
-}
-#endif
+/* This is for boards that rely on main() for an entry point of a stage. */
+void main(void) __attribute__((alias ("verstage")));
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index f4d5e11..3a9c89b 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -48,4 +48,10 @@ int vboot_enable_developer(void);
 
 void vboot_reboot(void);
 
+/* Main logic for verified boot. verstage() is the stage entry point
+ * while the verstage_main() is just the core logic. */
+void verstage_main(void);
+void verstage_mainboard_init(void);
+void verstage(void);
+
 #endif /* VBOOT_COMMON_H */


From gerrit at coreboot.org  Wed Sep 30 03:19:06 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 30 Sep 2015 03:19:06 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: xcompile:
	Redirect the objdump stderr to /dev/null
References: <I9940f069f66e097973ed6138cf3c696087fa5531+0@gerrit.coreboot.org>
Message-ID: <I9940f069f66e097973ed6138cf3c696087fa5531+3@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11681

-gerrit

commit c592068d979aa718912c97f4a0c47672c40ff7d0
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Sep 18 06:17:09 2015 -0700

    xcompile: Redirect the objdump stderr to /dev/null
    
    On system with clang, "as" is available but "objdump" is not by default.
    So if ${gccprefix} is empty, "as" can run successfully and the "objdump"
    below might report error. Mask that output.
    
    Change-Id: I9940f069f66e097973ed6138cf3c696087fa5531
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/xcompile/xcompile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 46a30d1..d664464 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -115,7 +115,7 @@ testas() {
 		2>/dev/null || return 1
 
 	# Check output content type.
-	local obj_type="$(LANG=C LC_ALL= ${gccprefix}objdump -p $obj_file)"
+	local obj_type="$(LANG=C LC_ALL= ${gccprefix}objdump -p $obj_file 2>/dev/null)"
 	local obj_arch="$(expr "$obj_type" : '.*format \(.[a-z0-9-]*\)')"
 	[ "$obj_arch" = "$full_arch" ] || return 1
 


From gerrit at coreboot.org  Wed Sep 30 03:19:10 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 30 Sep 2015 03:19:10 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbfstool: Add
	header file for ntohl & htonl on Apple
References: <Ia942c58f34637c18222fbf985b93c48abf63c5b8+0@gerrit.coreboot.org>
Message-ID: <Ia942c58f34637c18222fbf985b93c48abf63c5b8+2@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11672

-gerrit

commit e6f2e5f178e78fd6a7f6c2e83b5bb40bc24ace7d
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Sep 16 13:27:22 2015 -0700

    cbfstool: Add header file for ntohl & htonl on Apple
    
    On Apple OS X, the ntohl and htonl need including header,
     #include <arpa/inet.h>
    
    Please refer the manpage for these command on OS X,
    https://developer.apple.com/library/mac/documentation/Darwin/Reference/ManPages/man3/htonl.3.html
    
    Change-Id: Ia942c58f34637c18222fbf985b93c48abf63c5b8
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 util/cbfstool/swab.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/cbfstool/swab.h b/util/cbfstool/swab.h
index 22ae8b4..a45a767 100644
--- a/util/cbfstool/swab.h
+++ b/util/cbfstool/swab.h
@@ -18,7 +18,7 @@
 #if !defined(__APPLE__) && !defined(__NetBSD__)
 #define ntohl(x)	(is_big_endian() ? (uint32_t)(x) : swab32(x))
 #define htonl(x)	(is_big_endian() ? (uint32_t)(x) : swab32(x))
-#elif defined(__NetBSD__)
+#else
 #include <arpa/inet.h>
 #endif
 #define ntohll(x)	(is_big_endian() ? (uint64_t)(x) : swab64(x))


From gerrit at coreboot.org  Wed Sep 30 03:19:12 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 30 Sep 2015 03:19:12 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	hudson/Makefile: Remove the dd args "status"
References: <I7f7bf68967c61524811aa038b064ea706dadd366+0@gerrit.coreboot.org>
Message-ID: <I7f7bf68967c61524811aa038b064ea706dadd366+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11745

-gerrit

commit 5a3ec3c899a193bb54beb2b72a6f0b4773cbb195
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Sep 30 04:22:04 2015 -0700

    hudson/Makefile: Remove the dd args "status"
    
    My dd on Macos doesn't take "status=xx".
    
    Darwin Kernel Version 13.0.0: ???????,  9 ??????
    2013 ?. 02:42:04 (MSK);
    root:xnu-2422.1.72_by_bronya_sinetek_anv_rc7/
    BUILD/obj/RELEASE_X86_64
    
    Change-Id: I7f7bf68967c61524811aa038b064ea706dadd366
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/southbridge/amd/pi/hudson/Makefile.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 00d150f..547ed52 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -136,7 +136,7 @@ $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM
 		$(HUDSON_PSP_DIRECTORY_POSITION); do \
 		echo  $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \
 	done > $@.tmp; \
-	dd if=$@.tmp of=$@ conv=notrunc status=noxfer 2>/dev/null; \
+	dd if=$@.tmp of=$@ conv=notrunc >/dev/null 2>/dev/null; \
 	rm $@.tmp
 
 ifeq ($(CONFIG_HUDSON_FWM), y)
@@ -408,7 +408,7 @@ apu/smuscs-position := $(SMUSCS_POS)
 apu/smuscs-type := raw
 
 #9
-cbfs-files-y += apu/pspsecuredebug
+#cbfs-files-y += apu/pspsecuredebug
 apu/pspsecuredebug-file := $(CONFIG_PSPSECUREDEBUG_FILE)
 apu/pspsecuredebug-position := $(PSPSECUREDEBUG_POS)
 apu/pspsecuredebug-type := raw


From gerrit at coreboot.org  Wed Sep 30 04:21:57 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 30 Sep 2015 04:21:57 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: AMD Bettong:
	Set on-board eMMC as SD 2.0
References: <I9fd913f76535e65c1672924ebdeba3d35dea59cc+0@gerrit.coreboot.org>
Message-ID: <I9fd913f76535e65c1672924ebdeba3d35dea59cc+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11748

-gerrit

commit cc2f6c590067e3a7080a96c982937e6fc663769b
Author: zbao <fishbaozi at gmail.com>
Date:   Mon Jul 6 19:06:41 2015 -0400

    AMD Bettong: Set on-board eMMC as SD 2.0
    
    The on-board eMMC is designed as 2.0. If it is set as 3.0,
    it can not be detected.
    
    Change-Id: I9fd913f76535e65c1672924ebdeba3d35dea59cc
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/mainboard/amd/bettong/BiosCallOuts.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index ad8dc40..83a1f19 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -31,6 +31,7 @@
 #include "hudson.h"
 #include <stdlib.h>
 #include "BiosCallOuts.h"
+#include "board_rev.h"
 
 static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
 
@@ -90,6 +91,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
 		FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */
 
 		/* sata configuration */
+		/* SD configuration */
+		/* Rev F has an on-board eMMC, which only support SD 2.0 */
+		if (get_board_id() == 'F') {
+			FchParams_env->Sd.SdConfig = SdVer2;
+		}
 	}
 	printk(BIOS_DEBUG, "Done\n");
 


From gerrit at coreboot.org  Wed Sep 30 04:25:50 2015
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Wed, 30 Sep 2015 04:25:50 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: AMD bettong:
	Add UART support.
References: <I4cec833cc2ff8069c82886837f7cbd4483ff11bb+0@gerrit.coreboot.org>
Message-ID: <I4cec833cc2ff8069c82886837f7cbd4483ff11bb+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749

-gerrit

commit f01d4f0de638dea2cd9c38e3a6f4da338e09db22
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Jul 17 14:33:16 2015 -0400

    AMD bettong: Add UART support.
    
    Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/drivers/uart/uart8250mem.c              | 12 ++++--
 src/mainboard/amd/bettong/Kconfig           | 12 ++++++
 src/mainboard/amd/bettong/romstage.c        | 26 ++++++++++++
 src/southbridge/amd/pi/hudson/Makefile.inc  |  5 +++
 src/southbridge/amd/pi/hudson/acpi/uart.asl | 66 +++++++++++++++++++++++++++++
 src/southbridge/amd/pi/hudson/uart.c        | 30 +++++++++++++
 6 files changed, 148 insertions(+), 3 deletions(-)

diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index fb7327e..be291f3 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -36,6 +36,12 @@
 #define SINGLE_CHAR_TIMEOUT	(50 * 1000)
 #define FIFO_TIMEOUT		(16 * SINGLE_CHAR_TIMEOUT)
 
+static void my_delay(int delay)
+{
+	while (delay --)
+		outb(0xaa, 0x80);
+}
+
 #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)
 static uint8_t uart8250_read(void *base, uint8_t reg)
 {
@@ -67,7 +73,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data)
 {
 	unsigned long int i = SINGLE_CHAR_TIMEOUT;
 	while(i-- && !uart8250_mem_can_tx_byte(base))
-		udelay(1);
+		 my_delay(1);
 	uart8250_write(base, UART8250_TBR, data);
 }
 
@@ -75,7 +81,7 @@ static void uart8250_mem_tx_flush(void *base)
 {
 	unsigned long int i = FIFO_TIMEOUT;
 	while(i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT))
-		udelay(1);
+		my_delay(1);
 }
 
 static int uart8250_mem_can_rx_byte(void *base)
@@ -87,7 +93,7 @@ static unsigned char uart8250_mem_rx_byte(void *base)
 {
 	unsigned long int i = SINGLE_CHAR_TIMEOUT;
 	while(i-- && !uart8250_mem_can_rx_byte(base))
-		udelay(1);
+		my_delay(1);
 	if (i)
 		return uart8250_read(base, UART8250_RBR);
 	else
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 1f2d888..3fa4ee3 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -55,4 +55,16 @@ config HUDSON_LEGACY_FREE
 	bool
 	default y
 
+config DRIVERS_UART_8250MEM
+	bool
+	default y
+
+config DRIVERS_UART_8250MEM_32
+	bool
+	default y
+
+config DRIVERS_UART_8250IO
+	bool
+	default n
+
 endif # BOARD_AMD_BETTONG
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index a8a2777..1bfa9a3 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -27,6 +27,10 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
+#include <delay.h>
+
+#define ACPI_MMIO_BASE ((void *)0xFED80000)
+#define AOAC_BASE 0x1E00
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -34,6 +38,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if CONFIG_HAVE_ACPI_RESUME
 	void *resume_backup_memory;
 #endif
+#if CONFIG_DRIVERS_UART_8250MEM
+	u8 byte;
+	msr_t msr;
+#endif
 
 	amd_initmmio();
 
@@ -43,6 +51,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		post_code(0x30);
 
 		post_code(0x31);
+#if CONFIG_DRIVERS_UART_8250MEM
+		msr = rdmsr(0x1B);
+		msr.lo |= 1 << 11;
+		wrmsr(0x1B, msr);
+		byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2);
+		byte |= 1 << 3;
+		write8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte);
+		byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x62);
+		byte |= 1 << 3;
+		write8(ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte);
+		write8(ACPI_MMIO_BASE + 0xD00 + 0x89, 0);
+		write8(ACPI_MMIO_BASE + 0xD00 + 0x8A, 0);
+		write8(ACPI_MMIO_BASE + 0xD00 + 0x8E, 0);
+		write8(ACPI_MMIO_BASE + 0xD00 + 0x8F, 0);
+
+		udelay(2000);
+		write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); //reset UART
+#endif
 		console_init();
 	}
 
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 00d150f..138520e 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -50,6 +50,11 @@ romstage-y += imc.c
 ramstage-y += imc.c
 endif
 
+ifeq ($(CONFIG_DRIVERS_UART_8250MEM), y)
+romstage-y	+= uart.c
+ramstage-y	+= uart.c
+endif
+
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c
 
diff --git a/src/southbridge/amd/pi/hudson/acpi/uart.asl b/src/southbridge/amd/pi/hudson/acpi/uart.asl
new file mode 100644
index 0000000..da7817b
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/acpi/uart.asl
@@ -0,0 +1,66 @@
+    Scope(\_SB.FUR0)
+	{
+		Device(UART)
+		{
+			Name(_HID, "UTK0001")
+			Name(_CID, "UARTTest")
+			Name(_UID, Zero)
+			Method(_CRS, 0, NotSerialized)
+			{
+				Name(RBUF, Buffer(0x22)
+				{
+					0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35,
+					0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00,
+					0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F,
+					0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00,
+					0x79, 0x00
+				})
+				Return(RBUF)
+			}
+			Method(_STA, 0, NotSerialized)
+			{
+				If(LEqual(MWTT, Zero))
+				{
+					Return(0x0F)
+				}
+				Else
+				{
+					Return(Zero)
+				}
+			}
+		}
+	}
+/*
+	Scope(\_SB.FUR1)
+	{
+		Device(UART)
+		{
+			Name(_HID, "UTK0001")
+			Name(_CID, "UARTTest")
+			Name(_UID, One)
+			Method(_CRS, 0, NotSerialized)
+			{
+				Name(RBUF, Buffer(0x22)
+				{
+					0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35,
+					0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00,
+					0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F,
+					0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00,
+					0x79, 0x00
+				})
+				Return(RBUF)
+			}
+			Method(_STA, 0, NotSerialized)
+			{
+				If(LEqual(MWTT, Zero))
+				{
+					Return(0x0F)
+				}
+				Else
+				{
+					Return(Zero)
+				}
+			}
+		}
+	}
+*/
diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c
new file mode 100644
index 0000000..523ce73
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/uart.c
@@ -0,0 +1,30 @@
+
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>	/* for __console definition */
+#include <console/uart.h>
+#include <drivers/uart/uart8250reg.h>
+
+#define ACPI_MMIO_BASE 0xFED80000
+#define AOAC_BASE 0x1E00
+uintptr_t uart_platform_base(int idx)
+{
+	return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1));
+}
+
+unsigned int uart_platform_refclk(void)
+{
+	return 48000000;
+}
+
+void uart_fill_lb(void *data)
+{
+	struct lb_serial serial;
+	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+	serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+	serial.baud = default_baudrate();
+	serial.regwidth = 1;
+	lb_add_serial(&serial, data);
+
+	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}


From gerrit at coreboot.org  Wed Sep 30 04:28:47 2015
From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com))
Date: Wed, 30 Sep 2015 04:28:47 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+10@gerrit.coreboot.org>

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit ac81a84d61da9642a39211eefefa92df54d1a366
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                               | 23 ++++++-------
 src/cpu/amd/model_10xxx/Makefile.inc               |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c           |  3 --
 src/cpu/amd/model_fxx/Makefile.inc                 |  2 +-
 src/cpu/intel/ep80579/Makefile.inc                 |  2 --
 src/cpu/intel/ep80579/microcode_blob.c             |  8 -----
 src/cpu/intel/fsp_model_206ax/Kconfig              |  5 ---
 src/cpu/intel/fsp_model_206ax/Makefile.inc         |  9 ++---
 src/cpu/intel/fsp_model_206ax/microcode_blob.c     | 22 -------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h     | 33 -------------------
 src/cpu/intel/fsp_model_206ax/microcode_size.h     |  7 ----
 src/cpu/intel/fsp_model_406dx/Kconfig              |  4 ---
 src/cpu/intel/fsp_model_406dx/Makefile.inc         | 10 ++----
 src/cpu/intel/fsp_model_406dx/microcode_blob.c     | 29 -----------------
 src/cpu/intel/fsp_model_406dx/microcode_size.h     |  7 ----
 src/cpu/intel/haswell/Makefile.inc                 |  5 +--
 src/cpu/intel/haswell/microcode_blob.c             | 30 -----------------
 src/cpu/intel/model_1067x/Makefile.inc             |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c         |  3 --
 src/cpu/intel/model_106cx/Makefile.inc             |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c         |  3 --
 src/cpu/intel/model_2065x/Makefile.inc             |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c         | 22 -------------
 src/cpu/intel/model_206ax/Makefile.inc             |  3 +-
 src/cpu/intel/model_206ax/microcode_blob.c         | 23 -------------
 src/cpu/intel/model_65x/Makefile.inc               |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c           |  3 --
 src/cpu/intel/model_67x/Makefile.inc               |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c           |  3 --
 src/cpu/intel/model_68x/Makefile.inc               |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c           |  3 --
 src/cpu/intel/model_69x/Makefile.inc               |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c           |  3 --
 src/cpu/intel/model_6bx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6dx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6ex/Makefile.inc               |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c           |  3 --
 src/cpu/intel/model_6fx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6xx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c           |  3 --
 src/cpu/intel/model_f0x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f1x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f2x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f3x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c           |  3 --
 src/cpu/intel/model_f4x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c           |  3 --
 src/cpu/via/nano/Makefile.inc                      |  4 +--
 src/drivers/intel/fsp1_0/Makefile.inc              |  2 +-
 src/soc/intel/baytrail/Makefile.inc                |  3 +-
 src/soc/intel/baytrail/microcode/Makefile.inc      |  1 -
 src/soc/intel/baytrail/microcode/microcode_blob.c  |  3 --
 src/soc/intel/braswell/Makefile.inc                |  3 +-
 src/soc/intel/braswell/microcode/Makefile.inc      |  2 --
 src/soc/intel/braswell/microcode/microcode_blob.c  | 22 -------------
 src/soc/intel/broadwell/Makefile.inc               |  3 +-
 src/soc/intel/broadwell/microcode/Makefile.inc     |  1 -
 src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
 src/soc/intel/fsp_baytrail/Makefile.inc            |  3 +-
 src/soc/intel/fsp_baytrail/microcode/Makefile.inc  | 26 ---------------
 .../intel/fsp_baytrail/microcode/microcode_blob.c  | 38 ----------------------
 .../intel/fsp_baytrail/microcode/microcode_size.h  |  6 ----
 src/soc/intel/skylake/Makefile.inc                 |  3 +-
 src/soc/intel/skylake/microcode/Makefile.inc       |  2 --
 src/soc/intel/skylake/microcode/microcode_blob.c   | 24 --------------
 71 files changed, 51 insertions(+), 451 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_size.h b/src/cpu/intel/fsp_model_206ax/microcode_size.h
deleted file mode 100644
index 0b0364c..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_size.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	#define MICROCODE_REGION_LENGTH 0xC000
-#elif IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	#define MICROCODE_REGION_LENGTH 0x2800
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_size.h b/src/cpu/intel/fsp_model_406dx/microcode_size.h
deleted file mode 100644
index b638ae5..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_size.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-	#define MICROCODE_REGION_LENGTH 0x14400
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-	#define MICROCODE_REGION_LENGTH 0x14800
-#endif
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 0ec52ec..1d04699 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -25,7 +25,7 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
 CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
-ifneq ($(cpu_microcode-objs),)
+ifneq ($(cpu_microcode_bins),)
 $(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
 	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
 	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 085a45e..edc77af 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -53,6 +52,8 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index e5ac640..426f359 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -51,6 +50,8 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index fdd064d..a9004ac 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -73,6 +72,8 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 39a253f..7370830 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
 
 ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -59,6 +58,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
 ramstage-y += placeholders.c
 ramstage-y += i2c.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
-		/*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
-	#include "M0230672228.h"  // M0230672: Bay Trail "Super SKU" B0/B1
-	#include "M0130673322.h"  // M0130673: Bay Trail I B2 / B3
-	#include "M0130679901.h"  // M0130679: Bay Trail I D0
-#else
-	/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
-	#include "M0C30678829.h"  // M0C30678: Bay Trail M D Stepping
-#endif	/* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif	/* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	#define MICROCODE_REGION_LENGTH 0x30000
-#else
-	#define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index d6bc839..b80767b 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-


From gerrit at coreboot.org  Wed Sep 30 06:29:12 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 30 Sep 2015 06:29:12 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cpu: microcode:
	Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+11@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607

-gerrit

commit 9f8e196b026008771331956957c1a57aa4de5108
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/Makefile.inc                               | 23 ++++++-------
 src/cpu/amd/model_10xxx/Makefile.inc               |  2 +-
 src/cpu/amd/model_10xxx/microcode_blob.c           |  3 --
 src/cpu/amd/model_fxx/Makefile.inc                 |  2 +-
 src/cpu/intel/ep80579/Makefile.inc                 |  2 --
 src/cpu/intel/ep80579/microcode_blob.c             |  8 -----
 src/cpu/intel/fsp_model_206ax/Kconfig              |  5 ---
 src/cpu/intel/fsp_model_206ax/Makefile.inc         |  9 ++---
 src/cpu/intel/fsp_model_206ax/microcode_blob.c     | 22 -------------
 src/cpu/intel/fsp_model_206ax/microcode_blob.h     | 33 -------------------
 src/cpu/intel/fsp_model_206ax/microcode_size.h     |  7 ----
 src/cpu/intel/fsp_model_406dx/Kconfig              |  4 ---
 src/cpu/intel/fsp_model_406dx/Makefile.inc         | 10 ++----
 src/cpu/intel/fsp_model_406dx/microcode_blob.c     | 29 -----------------
 src/cpu/intel/fsp_model_406dx/microcode_size.h     |  7 ----
 src/cpu/intel/haswell/Makefile.inc                 |  5 +--
 src/cpu/intel/haswell/microcode_blob.c             | 30 -----------------
 src/cpu/intel/model_1067x/Makefile.inc             |  2 +-
 src/cpu/intel/model_1067x/microcode_blob.c         |  3 --
 src/cpu/intel/model_106cx/Makefile.inc             |  2 +-
 src/cpu/intel/model_106cx/microcode_blob.c         |  3 --
 src/cpu/intel/model_2065x/Makefile.inc             |  2 +-
 src/cpu/intel/model_2065x/microcode_blob.c         | 22 -------------
 src/cpu/intel/model_206ax/Makefile.inc             |  3 +-
 src/cpu/intel/model_206ax/microcode_blob.c         | 23 -------------
 src/cpu/intel/model_65x/Makefile.inc               |  2 +-
 src/cpu/intel/model_65x/microcode_blob.c           |  3 --
 src/cpu/intel/model_67x/Makefile.inc               |  2 +-
 src/cpu/intel/model_67x/microcode_blob.c           |  3 --
 src/cpu/intel/model_68x/Makefile.inc               |  2 +-
 src/cpu/intel/model_68x/microcode_blob.c           |  3 --
 src/cpu/intel/model_69x/Makefile.inc               |  2 +-
 src/cpu/intel/model_69x/microcode_blob.c           |  3 --
 src/cpu/intel/model_6bx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6bx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6dx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6dx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6ex/Makefile.inc               |  2 +-
 src/cpu/intel/model_6ex/microcode_blob.c           |  3 --
 src/cpu/intel/model_6fx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6fx/microcode_blob.c           |  3 --
 src/cpu/intel/model_6xx/Makefile.inc               |  2 +-
 src/cpu/intel/model_6xx/microcode_blob.c           |  3 --
 src/cpu/intel/model_f0x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f0x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f1x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f1x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f2x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f2x/microcode_blob.c           |  4 ---
 src/cpu/intel/model_f3x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f3x/microcode_blob.c           |  3 --
 src/cpu/intel/model_f4x/Makefile.inc               |  2 +-
 src/cpu/intel/model_f4x/microcode_blob.c           |  3 --
 src/cpu/via/nano/Makefile.inc                      |  4 +--
 src/drivers/intel/fsp1_0/Makefile.inc              |  2 +-
 src/soc/intel/baytrail/Makefile.inc                |  3 +-
 src/soc/intel/baytrail/microcode/Makefile.inc      |  1 -
 src/soc/intel/baytrail/microcode/microcode_blob.c  |  3 --
 src/soc/intel/braswell/Makefile.inc                |  3 +-
 src/soc/intel/braswell/microcode/Makefile.inc      |  2 --
 src/soc/intel/braswell/microcode/microcode_blob.c  | 22 -------------
 src/soc/intel/broadwell/Makefile.inc               |  3 +-
 src/soc/intel/broadwell/microcode/Makefile.inc     |  1 -
 src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
 src/soc/intel/fsp_baytrail/Makefile.inc            |  3 +-
 src/soc/intel/fsp_baytrail/microcode/Makefile.inc  | 26 ---------------
 .../intel/fsp_baytrail/microcode/microcode_blob.c  | 38 ----------------------
 .../intel/fsp_baytrail/microcode/microcode_size.h  |  6 ----
 src/soc/intel/skylake/Makefile.inc                 |  3 +-
 src/soc/intel/skylake/microcode/Makefile.inc       |  2 --
 src/soc/intel/skylake/microcode/microcode_blob.c   | 24 --------------
 71 files changed, 51 insertions(+), 451 deletions(-)

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@
 
 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_size.h b/src/cpu/intel/fsp_model_206ax/microcode_size.h
deleted file mode 100644
index 0b0364c..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_size.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	#define MICROCODE_REGION_LENGTH 0xC000
-#elif IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	#define MICROCODE_REGION_LENGTH 0x2800
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040
 
-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
 
 ramstage-y += acpi.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_size.h b/src/cpu/intel/fsp_model_406dx/microcode_size.h
deleted file mode 100644
index b638ae5..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_size.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-	#define MICROCODE_REGION_LENGTH 0x14400
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-	#define MICROCODE_REGION_LENGTH 0x14800
-#endif
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c
 
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c
 
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
 
 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 629a60e..deae45b 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -25,7 +25,7 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
 CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
-ifneq ($(cpu_microcode-objs),)
+ifneq ($(cpu_microcode_bins),)
 $(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
 	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
 	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 085a45e..edc77af 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -53,6 +52,8 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index e5ac640..426f359 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -51,6 +50,8 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index fdd064d..a9004ac 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -73,6 +72,8 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 39a253f..7370830 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
 
 ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
@@ -59,6 +58,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
 ramstage-y += placeholders.c
 ramstage-y += i2c.c
 
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
-		/*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
-	#include "M0230672228.h"  // M0230672: Bay Trail "Super SKU" B0/B1
-	#include "M0130673322.h"  // M0130673: Bay Trail I B2 / B3
-	#include "M0130679901.h"  // M0130679: Bay Trail I D0
-#else
-	/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
-	#include "M0C30678829.h"  // M0C30678: Bay Trail M D Stepping
-#endif	/* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif	/* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
-	#define MICROCODE_REGION_LENGTH 0x30000
-#else
-	#define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index d6bc839..b80767b 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
 
-subdirs-y += microcode
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
+# cpu_microcode_bins += ???
+
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-


From gerrit at coreboot.org  Wed Sep 30 06:29:13 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 30 Sep 2015 06:29:13 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: intel/fsp1_0:
	Declare microcode to be size 0 if it doesn't exist
References: <Id2063fb29226dcb55fe84f680b7b9cb10313ef2b+0@gerrit.coreboot.org>
Message-ID: <Id2063fb29226dcb55fe84f680b7b9cb10313ef2b+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11753

-gerrit

commit 06fde43b91b6b43026ea987810412e095125ed8a
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Sep 30 08:24:01 2015 +0200

    intel/fsp1_0: Declare microcode to be size 0 if it doesn't exist
    
    Change-Id: Id2063fb29226dcb55fe84f680b7b9cb10313ef2b
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/drivers/intel/fsp1_0/Makefile.inc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 0ec52ec..629a60e 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -29,9 +29,13 @@ ifneq ($(cpu_microcode-objs),)
 $(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
 	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
 	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+else
+$(objgenerated)/microcode_size.h:
+	printf "#define MICROCODE_REGION_LENGTH 0" > $@.tmp \
+	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+endif
 
 cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h
-endif
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)


From gerrit at coreboot.org  Wed Sep 30 06:53:45 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 06:53:45 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: provide
	common macro for linking early stages
References: <I12f4872df09fff6715829de68fc374e230350c2e+0@gerrit.coreboot.org>
Message-ID: <E1ZhBGr-0000vr-Uh@mail.coreboot.org>

the following patch was just integrated into master:
commit 1bc6a79874bc464167ff27319adc16ec87a7206c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 14:54:25 2015 -0500

    x86: provide common macro for linking early stages
    
    In order to support verstage on x86 one needs to link verstage
    like romstage since it needs all the cache-as-ram goodies. Therefore,
    provide a macro that one can invoke that provides the necessary
    recipes for linking that particular stage in such an environment.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I12f4872df09fff6715829de68fc374e230350c2e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11739
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11739 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 06:54:00 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 06:54:00 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: x86: prepare
	cache-as-ram to allow multiple stages
References: <I15e9f6b0c632ee5a2369da0709535d6cb0d94f61+0@gerrit.coreboot.org>
Message-ID: <E1ZhBH6-0000y0-Sx@mail.coreboot.org>

the following patch was just integrated into master:
commit dd6fa93dedc402cae65a333f5dff3d3c1a12f0c6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 24 12:18:07 2015 -0500

    x86: prepare cache-as-ram to allow multiple stages
    
    In order to do a verification of romstage on x86 one needs to
    run verstage which verifies romstage (and the memory init code).
    However, x86 doesn't have SRAM like every other modern SoC so
    managing the cache-as-ram region is especially critical.
    
    First move all of the "shared" objects to the beginning of
    the .car.data section. This change then ensures that each stage
    using car.ld to link has the same consistent view of the addresses
    of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can
    be unique per stage. However, these variables are expected to have
    a value of zero at the start of each stage. In order to allow a
    stage to provide those semantics outside of the initial cache-as-arm
    setup routine add _car_global_start and _car_global_end symbols.
    Those symbols can be used to clear the CAR_GLOBALs for that stage.
    
    Note that the timestamp region can't be moved out similarly to the
    pre-ram cbmem console because the object storage of the timestamp
    cache is used *after* cache-as-ram is torn down to indicate if the
    cache should be used or not. Therefore, that timestamp needs to
    migrated to ram. A logic change in src/lib/timestamp.c could
    alleviate this requirement, but that task wasn't tackled in this
    patch.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.
    
    Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11740
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11740 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 06:56:58 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 06:56:58 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: intel/fsp1_0:
	Declare microcode to be size 0 if it doesn't exist
References: <Id2063fb29226dcb55fe84f680b7b9cb10313ef2b+0@gerrit.coreboot.org>
Message-ID: <E1ZhBJy-0001Rr-At@mail.coreboot.org>

the following patch was just integrated into master:
commit b20a600ba736d8d7ed3e67a9d4e001ec044faee2
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Sep 30 08:24:01 2015 +0200

    intel/fsp1_0: Declare microcode to be size 0 if it doesn't exist
    
    Change-Id: Id2063fb29226dcb55fe84f680b7b9cb10313ef2b
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/11753
    Tested-by: build bot (Jenkins)
    Reviewed-by: Werner Zeh <werner.zeh at siemens.com>


See http://review.coreboot.org/11753 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 06:57:28 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 06:57:28 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: cpu:
	microcode: Use microcode stored in binary format
References: <Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce+0@gerrit.coreboot.org>
Message-ID: <E1ZhBKS-0001Wx-UV@mail.coreboot.org>

the following patch was just integrated into master:
commit 1d85700503afdb8516ee945e9e294d4a6aa1c759
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Sep 9 22:38:06 2015 -0700

    cpu: microcode: Use microcode stored in binary format
    
    Using a copiler to compile something that's already a binary is pretty
    stupid. Now that Stefan converted most microcode in blobs to a plain
    binary, use the binary version.
    
    Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/11607
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11607 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 06:58:09 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 06:58:09 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: vboot: provide
	a unified flow for separate verstage
References: <I14593e1fc69a1654fa27b512eb4b612395b94ce5+0@gerrit.coreboot.org>
Message-ID: <E1ZhBL7-0001df-6g@mail.coreboot.org>

the following patch was just integrated into master:
commit 588ad7b5db26a88dad36e2dbecf5a4242d8410be
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 17:56:59 2015 -0500

    vboot: provide a unified flow for separate verstage
    
    The vboot verification in a stage proper is unified
    replacing duplicate code in the tegra SoC code. The
    original verstage.c file is renamed to reflect its
    real purpose. The support for a single verstage flow
    is added to the vboot2 directory proper.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built glados.
    
    Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11744
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11744 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 06:59:04 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 06:59:04 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kconfig: Allow
	KCONFIG_STRICT outside of confdata.c
References: <Idf7ee406ce3869941af319219aea16fab826df84+0@gerrit.coreboot.org>
Message-ID: <E1ZhBLz-0001jV-Ty@mail.coreboot.org>

the following patch was just integrated into master:
commit 57a31317a26ff5f55638c4f3dd8d06b8a69b78f2
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Aug 20 11:19:34 2015 -0700

    kconfig: Allow KCONFIG_STRICT outside of confdata.c
    
    To catch dependency errors in symbol.c (such as the ones
    fixed by I51b4ee326f082c6a656a813ee5772e9c34f5c343) we need
    to check for global kconfig warnings before saving config
    files.
    
    This patch will produce errors for wrong dependencies and
    add catching of errors to conf, nconf and mconf. Sorry,
    gconf users, you will have to wait.
    
    Change-Id: Idf7ee406ce3869941af319219aea16fab826df84
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Reviewed-on: http://review.coreboot.org/11291
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11291 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 06:59:31 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 30 Sep 2015 06:59:31 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Enable
	KCONFIG_STRICT mode
References: <I6aa77db1b12a67472302ea39d7433993a6838af6+0@gerrit.coreboot.org>
Message-ID: <I6aa77db1b12a67472302ea39d7433993a6838af6+4@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10978

-gerrit

commit 297da60b1c70f8a6a8afd48cd434ae4a3d747925
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Fri Jul 17 17:29:19 2015 -0700

    Enable KCONFIG_STRICT mode
    
    Change-Id: I6aa77db1b12a67472302ea39d7433993a6838af6
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Makefile b/Makefile
index 421e919..d6dd14f 100644
--- a/Makefile
+++ b/Makefile
@@ -55,6 +55,7 @@ export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
 export KCONFIG_SPLITCONFIG := $(obj)/config
 export KCONFIG_TRISTATE := $(obj)/tristate.conf
 export KCONFIG_NEGATIVES := 1
+export KCONFIG_STRICT := 1
 
 # directory containing the toplevel Makefile.inc
 TOPLEVEL := .


From gerrit at coreboot.org  Wed Sep 30 07:00:35 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 07:00:35 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: AMD Bettong:
	Fix usb device in devicetree for Carrizo
References: <Ieeca06c68fe8c8eef6be4fab43193b898aebf013+0@gerrit.coreboot.org>
Message-ID: <E1ZhBNT-0002oV-EO@mail.coreboot.org>

the following patch was just integrated into master:
commit b0c6817dbecbb7c3bb9dd7436dc15e8846abc037
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Aug 26 22:29:07 2015 -0400

    AMD Bettong: Fix usb device in devicetree for Carrizo
    
    Add some missing devices to device tree and header.
    Remove the obsolete devices.
    
    Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
    Reviewed-on: http://review.coreboot.org/11378
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11378 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 07:02:51 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 07:02:51 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: amd/family14:
	Add k10temp thermal zone.
References: <Id9c5b783ba424246816677099ec6651814e59f21+0@gerrit.coreboot.org>
Message-ID: <E1ZhBPf-0005sr-9A@mail.coreboot.org>

the following patch was just integrated into master:
commit 6a4d6825acf324c02198fa73838c1eeaf4fdffc7
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Sun Jun 21 18:25:38 2015 +0200

    amd/family14: Add k10temp thermal zone.
    
    The thermal sensor interface exposed in function 3 of the northbridge is
    a more convenient and faster way to access the processor-internal
    thermal sensor than using the SMBus/SB-TSI interface from the FCH, see
    the Family14 BKDG: "Tctl is a processor temperature control value used
    for processor thermal management. Tctl is accessible through SB-TSI and
    D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the
    processors cooling requirements"
    
    Also on at least some of these boards the existing thermal zone is
    broken and always returns 40C (the default value if the SMBus read
    failed) because the SMBus muxing register (SmBus0Sel) is not set up
    correctly.
    
    Case in point: The fallback "smbus read failed" temperature is 40 C and
    the the logs taken from the board status repository for the Asrock
    E350M1 board all show: "ACPI: Thermal Zone [TZ00] (40 C)"
    e.g.
    http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-5054-gf584218/2013-12-20T20:56:20Z/kernel_log.txt#l390
    and
    http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-7030-g6d7de4f/2014-10-16T15:34:19Z/kernel_console.txt#l404
    and
    http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-9989-gf2dfef0/2015-06-13T00:22:49Z/kernel_log.txt#l425
    
    Example lm-sensors output with this patch on the pcengines APU1, on
    Linux 4.1.0-rc8+ (wiht both CONFIG_ACPI_THERMAL and
    CONFIG_SENSORS_K10TEMP enabled):
    
    acpitz-virtual-0
    Adapter: Virtual device
    temp1:        +54.0 C  (crit = +100.0 C)
    
    k10temp-pci-00c3
    Adapter: PCI adapter
    temp1:        +54.0 C  (high = +70.0 C)
                           (crit = +100.0 C, hyst = +97.0 C)
    
    Change-Id: Id9c5b783ba424246816677099ec6651814e59f21
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
    Reviewed-on: http://review.coreboot.org/10940
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/10940 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 10:11:36 2015
From: gerrit at coreboot.org (Patrick Georgi (pgeorgi@google.com))
Date: Wed, 30 Sep 2015 10:11:36 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: kconfig:
	kconfig_warnings needs to be defined for all frontends
References: <Iecefdd1e827e4eb8b4da573e4291850d6c47767f+0@gerrit.coreboot.org>
Message-ID: <Iecefdd1e827e4eb8b4da573e4291850d6c47767f+1@gerrit.coreboot.org>

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11754

-gerrit

commit 643f97da8eb2c704f4f4262f426c77ee8104ddd1
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Sep 30 12:01:18 2015 +0200

    kconfig: kconfig_warnings needs to be defined for all frontends
    
    Change-Id: Iecefdd1e827e4eb8b4da573e4291850d6c47767f
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/kconfig/mconf.c | 2 ++
 util/kconfig/nconf.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/util/kconfig/mconf.c b/util/kconfig/mconf.c
index b4a0844..7e5dc76 100644
--- a/util/kconfig/mconf.c
+++ b/util/kconfig/mconf.c
@@ -22,6 +22,8 @@
 #include "lkc.h"
 #include "lxdialog/dialog.h"
 
+int kconfig_warnings = 0;
+
 static const char mconf_readme[] = N_(
 "Overview\n"
 "--------\n"
diff --git a/util/kconfig/nconf.c b/util/kconfig/nconf.c
index bc845fc..f9944a6 100644
--- a/util/kconfig/nconf.c
+++ b/util/kconfig/nconf.c
@@ -13,6 +13,8 @@
 #include "nconf.h"
 #include <ctype.h>
 
+int kconfig_warnings = 0;
+
 static const char nconf_global_help[] = N_(
 "Help windows\n"
 "------------\n"


From gerrit at coreboot.org  Wed Sep 30 10:48:25 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 10:48:25 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: kconfig:
	kconfig_warnings needs to be defined for all frontends
References: <Iecefdd1e827e4eb8b4da573e4291850d6c47767f+0@gerrit.coreboot.org>
Message-ID: <E1ZhEvx-0001jK-Vn@mail.coreboot.org>

the following patch was just integrated into master:
commit 9595ed47315066b8a562d52c22e62a43bbe49bc9
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Sep 30 12:01:18 2015 +0200

    kconfig: kconfig_warnings needs to be defined for all frontends
    
    Change-Id: Iecefdd1e827e4eb8b4da573e4291850d6c47767f
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/11754
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Werner Zeh <werner.zeh at siemens.com>


See http://review.coreboot.org/11754 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 16:37:20 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 16:37:20 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master:
	pcengines/apu1: Add CMOS/NVRAM support
References: <I4864923166efb200882d895c572d1ee060c71951+0@gerrit.coreboot.org>
Message-ID: <E1ZhKNc-00060o-KK@mail.coreboot.org>

the following patch was just integrated into master:
commit 46731237ceca6162302e23f535dc886ac171b6e6
Author: Maxime de Roucy <maxime.deroucy at gmail.com>
Date:   Sun Sep 27 15:45:35 2015 +0200

    pcengines/apu1: Add CMOS/NVRAM support
    
    Inspired by the Sage source code (itself from coreboot).
    
    Change-Id: I4864923166efb200882d895c572d1ee060c71951
    Signed-off-by: Maxime de Roucy <maxime.deroucy at gmail.com>
    Reviewed-on: http://review.coreboot.org/11730
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/11730 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 17:37:09 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 17:37:09 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: verstage to x86
References: <I905dffe8438402667ac60d1ad57f587fd3c002cb+0@gerrit.coreboot.org>
Message-ID: <I905dffe8438402667ac60d1ad57f587fd3c002cb+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11756

-gerrit

commit ccff836d3304fd0704432e15a716bd580a881067
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 29 15:03:58 2015 -0500

    verstage to x86
    
    Change-Id: I905dffe8438402667ac60d1ad57f587fd3c002cb
---
 src/arch/x86/Makefile.inc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f16edcd..6cf288c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -149,6 +149,20 @@ $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs)
 endef
 
 ###############################################################################
+# verstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
+
+ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32),y)
+$(eval $(call early_x86_stage,verstage,elf32-i386))
+else
+$(eval $(call early_x86_stage,verstage,elf64-x86-64))
+endif
+
+endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64
+
+###############################################################################
 # romstage
 ###############################################################################
 


From gerrit at coreboot.org  Wed Sep 30 17:37:12 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 17:37:12 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: cbmem: add
	coreboot table records for each cbmem entry
References: <I125940aa1898c3e99077ead0660eff8aa905b13b+0@gerrit.coreboot.org>
Message-ID: <I125940aa1898c3e99077ead0660eff8aa905b13b+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11757

-gerrit

commit 57dd38d574b3d90377569999a01915763242037d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:26:54 2015 -0500

    cbmem: add coreboot table records for each cbmem entry
    
    In order to not expose the cbmem data structures to usersland
    that are used by coreboot internally add each of the cbmem
    entries to a coreboot table record. The payload ABI uses
    coreboot tables so this just provides a shortcut for cbmem
    entries which were manually added previously by doing the
    work on behalf of all entries.
    
    The imd code added a cursor structure and associated functions
    for walking the entries in order to be placed in the tables.
    Additionally a struct lb_cbmem_entry was added that lists
    the base address, size, and id of the cbmem entry.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Booted glados. View coreboot table entries with cbmem.
    
    Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 13 +++++++
 src/include/cbmem.h                               |  4 +--
 src/include/imd.h                                 | 16 +++++++++
 src/lib/coreboot_table.c                          |  3 ++
 src/lib/imd.c                                     | 44 +++++++++++++++++++++++
 src/lib/imd_cbmem.c                               | 36 +++++++++++++++++--
 6 files changed, 112 insertions(+), 4 deletions(-)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 2ed4d7f..5e0c87c 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -308,6 +308,19 @@ struct lb_boot_media_params {
 	uint64_t boot_media_size;
 };
 
+/*
+ * There can be more than one of these records as there is one per cbmem entry.
+ */
+#define LB_TAG_CBMEM_ENTRY 0x0031
+struct lb_cbmem_entry {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t address;
+	uint32_t entry_size;
+	uint32_t id;
+};
+
 #define LB_TAG_SERIALNO		0x002a
 #define MAX_SERIALNO_LENGTH	32
 
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 60de5a7..810a2a9 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,6 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
+#include <boot/coreboot_tables.h>
 #include <commonlib/cbmem_id.h>
 #include <rules.h>
 
@@ -118,12 +119,11 @@ typedef void (* const cbmem_init_hook_t)(int is_recovery);
 void cbmem_run_init_hooks(int is_recovery);
 void cbmem_fail_resume(void);
 
-#ifndef __PRE_RAM__
 /* Ramstage only functions. */
 /* Add the cbmem memory used to the memory map at boot. */
 void cbmem_add_bootmem(void);
 void cbmem_list(void);
-#endif /* __PRE_RAM__ */
+void cbmem_add_records_to_cbtable(struct lb_header *header);
 
 #if ENV_RAMSTAGE
 #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
diff --git a/src/include/imd.h b/src/include/imd.h
index a444b4f..f55820f 100644
--- a/src/include/imd.h
+++ b/src/include/imd.h
@@ -124,6 +124,9 @@ size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry);
 /* Returns pointer to region described by entry or NULL on failure. */
 void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry);
 
+/* Returns id for the imd entry. */
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry);
+
 /* Attempt to remove entry from imd. */
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry);
 
@@ -136,6 +139,13 @@ struct imd_lookup {
 int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 			size_t size);
 
+struct imd_cursor;
+/* Initialize a imd_cursor object to walk the IMD entries. */
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor);
+
+/* Retrive the next imd entry the cursor is referencing. Returns NULL when
+ * no more entries exist. */
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor);
 
 /*
  * The struct imd is a handle for working with an in-memory directory.
@@ -152,4 +162,10 @@ struct imd {
 	struct imdr sm;
 };
 
+struct imd_cursor {
+	size_t current_imdr;
+	size_t current_entry;
+	const struct imdr *imdr[2];
+};
+
 #endif /* _IMD_H_ */
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6859bf2..1bd356d 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -517,6 +517,9 @@ unsigned long write_coreboot_table(
 
 	lb_boot_media_params(head);
 
+	/* Add all cbmem entries into the coreboot tables. */
+	cbmem_add_records_to_cbtable(head);
+
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head);
 }
diff --git a/src/lib/imd.c b/src/lib/imd.c
index 612e3f1..67a76a4 100644
--- a/src/lib/imd.c
+++ b/src/lib/imd.c
@@ -627,6 +627,11 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry)
 	return imdr_entry_at(imdr, entry);
 }
 
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry)
+{
+	return entry->id;
+}
+
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry)
 {
 	struct imd_root *r;
@@ -702,3 +707,42 @@ int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 
 	return 0;
 }
+
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor)
+{
+	if (imd == NULL || cursor == NULL)
+		return -1;
+
+	memset(cursor, 0, sizeof(*cursor));
+
+	cursor->imdr[0] = &imd->lg;
+	cursor->imdr[1] = &imd->sm;
+
+	return 0;
+}
+
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor)
+{
+	struct imd_root *r;
+	const struct imd_entry *e;
+
+	if (cursor->current_imdr >= ARRAY_SIZE(cursor->imdr))
+		return NULL;
+
+	r = imdr_root(cursor->imdr[cursor->current_imdr]);
+
+	if (r == NULL)
+		return NULL;
+
+	if (cursor->current_entry >= r->num_entries) {
+		/* Try next imdr. */
+		cursor->current_imdr++;
+		cursor->current_entry = 0;
+		return imd_cursor_next(cursor);
+	}
+
+	e = &r->entries[cursor->current_entry];
+	cursor->current_entry++;
+
+	return e;
+}
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index fa65334..82961be 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -267,7 +267,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry)
 	return imd_entry_at(imd, cbmem_to_imd(entry));
 }
 
-#if ENV_RAMSTAGE
 void cbmem_add_bootmem(void)
 {
 	void *base = NULL;
@@ -283,4 +282,37 @@ void cbmem_list(void)
 
 	imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup));
 }
-#endif /* __PRE_RAM__ */
+
+void cbmem_add_records_to_cbtable(struct lb_header *header)
+{
+	struct imd_cursor cursor;
+	struct imd *imd;
+
+	imd = cbmem_get_imd();
+
+	if (imd_cursor_init(imd, &cursor))
+		return;
+
+	while (1) {
+		const struct imd_entry *e;
+		struct lb_cbmem_entry *lbe;
+		uint32_t id;
+
+		e = imd_cursor_next(&cursor);
+
+		if (e == NULL)
+			break;
+
+		id = imd_entry_id(imd, e);
+		/* Don't add these metadata entries. */
+		if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL)
+			continue;
+
+		lbe = (struct lb_cbmem_entry *)lb_new_record(header);
+		lbe->tag = LB_TAG_CBMEM_ENTRY;
+		lbe->size = sizeof(*lbe);
+		lbe->address = (uintptr_t)imd_entry_at(imd, e);
+		lbe->entry_size = imd_entry_size(imd, e);
+		lbe->id = id;
+	}
+}


From gerrit at coreboot.org  Wed Sep 30 17:37:14 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 17:37:14 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot: util/cbmem:
	remove duplicated cbmem data structure logic.
References: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+0@gerrit.coreboot.org>
Message-ID: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11758

-gerrit

commit 3c91084f4ada8cce5d3ca87df4d57d417b571556
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:33:01 2015 -0500

    util/cbmem: remove duplicated cbmem data structure logic.
    
    The cbmem utility shouldn't be using the intra coreboot
    data structures for obtaining the produced data/information.
    Instead use the newly added cbmem records in the coreboot
    tables for pulling out the data one wants by using the
    generic indexing of coreboot table entries.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Interrogated cbmem table of contents with updated code.
    
    Change-Id: I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c
---
 util/cbmem/cbmem.c | 203 +++++++++++++++++++++--------------------------------
 1 file changed, 80 insertions(+), 123 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 74cb52d..3e4b8a0 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -60,8 +60,8 @@ static int verbose = 0;
 /* File handle used to access /dev/mem */
 static int mem_fd;
 
-/* IMD root pointer location */
-static uint64_t rootptr = 0;
+static uint64_t lbtable_address;
+static size_t lbtable_size;
 
 /*
  * calculate ip checksum (16 bit quantities) on a passed in buffer. In case
@@ -171,9 +171,57 @@ static void *map_memory_size(u64 physical, size_t size)
 	return v;
 }
 
-static void *map_memory(u64 physical)
+static void *map_lbtable(void)
 {
-	return map_memory_size(physical, MAP_BYTES);
+	if (lbtable_address == 0 || lbtable_size == 0) {
+		fprintf(stderr, "No coreboot table area found!\n");
+		return NULL;
+	}
+
+	return map_memory_size(lbtable_address, lbtable_size);
+}
+
+static void unmap_lbtable(void)
+{
+	unmap_memory();
+}
+
+/* Find the first cbmem entry filling in the details. */
+static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
+{
+	uint8_t *table;
+	size_t offset;
+	int ret = -1;
+
+	table = map_lbtable();
+
+	if (table == NULL)
+		return -1;
+
+	offset = 0;
+
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
+
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		lbe = (void *)lbr;
+		if (lbe->id != id)
+			continue;
+
+		*addr = lbe->address;
+		*size = lbe->entry_size;
+		ret = 0;
+		break;
+	}
+
+	unmap_lbtable();
+	return ret;
 }
 
 /*
@@ -244,6 +292,11 @@ static int parse_cbtable(u64 address, size_t table_size)
 		found = 1;
 		debug("Found!\n");
 
+		/* Keep reference to lbtable. */
+		lbtable_address = address;
+		lbtable_address += ((uint8_t *)lbtable - (uint8_t *)lbh);
+		lbtable_size = lbh->table_bytes;
+
 		for (j = 0; j < lbh->table_bytes; j += lbr_p->size) {
 			lbr_p = (struct lb_record*) ((char *)lbtable + j);
 			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
@@ -692,44 +745,6 @@ static void dump_cbmem_hex(void)
 	hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size));
 }
 
-/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */
-#define DYN_CBMEM_ALIGN_SIZE (4096)
-#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE
-#define CBMEM_POINTER_MAGIC 0xc0389481
-#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC)
-
-struct cbmem_root_pointer {
-	uint32_t magic;
-	/* Relative to upper limit/offset. */
-	int32_t root_offset;
-} __attribute__((packed));
-
-struct dynamic_cbmem_entry {
-	uint32_t magic;
-	int32_t start_offset;
-	uint32_t size;
-	uint32_t id;
-} __attribute__((packed));
-
-struct cbmem_root {
-	uint32_t max_entries;
-	uint32_t num_entries;
-	uint32_t flags;
-	uint32_t entry_align;
-	int32_t max_offset;
-	struct dynamic_cbmem_entry entries[0];
-} __attribute__((packed));
-
-#define CBMEM_MAGIC 0x434f5245
-#define MAX_CBMEM_ENTRIES 16
-
-struct cbmem_entry {
-	uint32_t magic;
-	uint32_t id;
-	uint64_t base;
-	uint64_t size;
-} __attribute__((packed));
-
 struct cbmem_id_to_name {
 	uint32_t id;
 	const char *name;
@@ -758,74 +773,39 @@ void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 	printf("  %08" PRIx64 "\n", size);
 }
 
-static void dump_static_cbmem_toc(struct cbmem_entry *entries)
+static void dump_cbmem_toc(void)
 {
 	int i;
+	uint8_t *table;
+	size_t offset;
 
-	printf("CBMEM table of contents:\n");
-	printf("    ID           START      LENGTH\n");
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		cbmem_print_entry(i, entries[i].id,
-				entries[i].base, entries[i].size);
-	}
-}
+	table = map_lbtable();
 
-static void dump_dynamic_cbmem_toc(struct cbmem_root *root)
-{
-	int i;
-	debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n",
-		root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset);
+	if (table == NULL)
+		return;
 
 	printf("CBMEM table of contents:\n");
 	printf("    ID           START      LENGTH\n");
 
-	for (i = 0; i < root->num_entries; i++) {
-		if(root->entries[i].magic != CBMEM_ENTRY_MAGIC)
-			break;
-		cbmem_print_entry(i, root->entries[i].id,
-			rootptr + root->entries[i].start_offset, root->entries[i].size);
-	}
-}
-
-static void dump_cbmem_toc(void)
-{
-	uint64_t start;
-	void *cbmem_area;
-	struct cbmem_entry *entries;
+	i = 0;
+	offset = 0;
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot CBMEM area found!\n");
-		return;
-	}
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
 
-	start = unpack_lb64(cbmem.start);
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
 
-	cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size));
-	entries = (struct cbmem_entry *)cbmem_area;
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
 
-	if (entries[0].magic == CBMEM_MAGIC) {
-		dump_static_cbmem_toc(entries);
-	} else {
-		rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size);
-		rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1);
-		rootptr -= sizeof(struct cbmem_root_pointer);
-		unmap_memory();
-		struct cbmem_root_pointer *r =
-			map_memory_size(rootptr, sizeof(*r));
-		if (r->magic == CBMEM_POINTER_MAGIC) {
-			struct cbmem_root *root;
-			uint64_t rootaddr = rootptr + r->root_offset;
-			unmap_memory();
-			root = map_memory_size(rootaddr, ROOT_MIN_SIZE);
-			dump_dynamic_cbmem_toc(root);
-		} else
-			fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n");
+		lbe = (void *)lbr;
+		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
+		i++;
 	}
 
-	unmap_memory();
+	unmap_lbtable();
 }
 
 #define COVERAGE_MAGIC 0x584d4153
@@ -857,42 +837,19 @@ static int mkpath(char *path, mode_t mode)
 
 static void dump_coverage(void)
 {
-	int i, found = 0;
 	uint64_t start;
-	struct cbmem_entry *entries;
+	size_t size;
 	void *coverage;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot table area found!\n");
+	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
+		fprintf(stderr, "No coverage information found\n");
 		return;
 	}
 
-	start = unpack_lb64(cbmem.start);
-
-	entries = (struct cbmem_entry *)map_memory(start);
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		if (entries[i].id == CBMEM_ID_COVERAGE) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (!found) {
-		unmap_memory();
-		fprintf(stderr, "No coverage information found in"
-			" CBMEM area.\n");
-		return;
-	}
-
-	start = entries[i].base;
-	unmap_memory();
 	/* Map coverage area */
-	coverage = map_memory(start);
+	coverage = map_memory_size(start, size);
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
 
 	printf("Dumping coverage data...\n");


From gerrit at coreboot.org  Wed Sep 30 17:38:07 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 17:38:07 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: util/cbmem:
	remove duplicated cbmem data structure logic.
References: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+0@gerrit.coreboot.org>
Message-ID: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11758

-gerrit

commit f0a102bd7c7f07fbbc96767a51bc34f410f7297a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:33:01 2015 -0500

    util/cbmem: remove duplicated cbmem data structure logic.
    
    The cbmem utility shouldn't be using the intra coreboot
    data structures for obtaining the produced data/information.
    Instead use the newly added cbmem records in the coreboot
    tables for pulling out the data one wants by using the
    generic indexing of coreboot table entries.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Interrogated cbmem table of contents with updated code.
    
    Change-Id: I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c
---
 util/cbmem/cbmem.c | 203 +++++++++++++++++++++--------------------------------
 1 file changed, 80 insertions(+), 123 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 74cb52d..3e4b8a0 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -60,8 +60,8 @@ static int verbose = 0;
 /* File handle used to access /dev/mem */
 static int mem_fd;
 
-/* IMD root pointer location */
-static uint64_t rootptr = 0;
+static uint64_t lbtable_address;
+static size_t lbtable_size;
 
 /*
  * calculate ip checksum (16 bit quantities) on a passed in buffer. In case
@@ -171,9 +171,57 @@ static void *map_memory_size(u64 physical, size_t size)
 	return v;
 }
 
-static void *map_memory(u64 physical)
+static void *map_lbtable(void)
 {
-	return map_memory_size(physical, MAP_BYTES);
+	if (lbtable_address == 0 || lbtable_size == 0) {
+		fprintf(stderr, "No coreboot table area found!\n");
+		return NULL;
+	}
+
+	return map_memory_size(lbtable_address, lbtable_size);
+}
+
+static void unmap_lbtable(void)
+{
+	unmap_memory();
+}
+
+/* Find the first cbmem entry filling in the details. */
+static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
+{
+	uint8_t *table;
+	size_t offset;
+	int ret = -1;
+
+	table = map_lbtable();
+
+	if (table == NULL)
+		return -1;
+
+	offset = 0;
+
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
+
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		lbe = (void *)lbr;
+		if (lbe->id != id)
+			continue;
+
+		*addr = lbe->address;
+		*size = lbe->entry_size;
+		ret = 0;
+		break;
+	}
+
+	unmap_lbtable();
+	return ret;
 }
 
 /*
@@ -244,6 +292,11 @@ static int parse_cbtable(u64 address, size_t table_size)
 		found = 1;
 		debug("Found!\n");
 
+		/* Keep reference to lbtable. */
+		lbtable_address = address;
+		lbtable_address += ((uint8_t *)lbtable - (uint8_t *)lbh);
+		lbtable_size = lbh->table_bytes;
+
 		for (j = 0; j < lbh->table_bytes; j += lbr_p->size) {
 			lbr_p = (struct lb_record*) ((char *)lbtable + j);
 			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
@@ -692,44 +745,6 @@ static void dump_cbmem_hex(void)
 	hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size));
 }
 
-/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */
-#define DYN_CBMEM_ALIGN_SIZE (4096)
-#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE
-#define CBMEM_POINTER_MAGIC 0xc0389481
-#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC)
-
-struct cbmem_root_pointer {
-	uint32_t magic;
-	/* Relative to upper limit/offset. */
-	int32_t root_offset;
-} __attribute__((packed));
-
-struct dynamic_cbmem_entry {
-	uint32_t magic;
-	int32_t start_offset;
-	uint32_t size;
-	uint32_t id;
-} __attribute__((packed));
-
-struct cbmem_root {
-	uint32_t max_entries;
-	uint32_t num_entries;
-	uint32_t flags;
-	uint32_t entry_align;
-	int32_t max_offset;
-	struct dynamic_cbmem_entry entries[0];
-} __attribute__((packed));
-
-#define CBMEM_MAGIC 0x434f5245
-#define MAX_CBMEM_ENTRIES 16
-
-struct cbmem_entry {
-	uint32_t magic;
-	uint32_t id;
-	uint64_t base;
-	uint64_t size;
-} __attribute__((packed));
-
 struct cbmem_id_to_name {
 	uint32_t id;
 	const char *name;
@@ -758,74 +773,39 @@ void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 	printf("  %08" PRIx64 "\n", size);
 }
 
-static void dump_static_cbmem_toc(struct cbmem_entry *entries)
+static void dump_cbmem_toc(void)
 {
 	int i;
+	uint8_t *table;
+	size_t offset;
 
-	printf("CBMEM table of contents:\n");
-	printf("    ID           START      LENGTH\n");
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		cbmem_print_entry(i, entries[i].id,
-				entries[i].base, entries[i].size);
-	}
-}
+	table = map_lbtable();
 
-static void dump_dynamic_cbmem_toc(struct cbmem_root *root)
-{
-	int i;
-	debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n",
-		root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset);
+	if (table == NULL)
+		return;
 
 	printf("CBMEM table of contents:\n");
 	printf("    ID           START      LENGTH\n");
 
-	for (i = 0; i < root->num_entries; i++) {
-		if(root->entries[i].magic != CBMEM_ENTRY_MAGIC)
-			break;
-		cbmem_print_entry(i, root->entries[i].id,
-			rootptr + root->entries[i].start_offset, root->entries[i].size);
-	}
-}
-
-static void dump_cbmem_toc(void)
-{
-	uint64_t start;
-	void *cbmem_area;
-	struct cbmem_entry *entries;
+	i = 0;
+	offset = 0;
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot CBMEM area found!\n");
-		return;
-	}
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
 
-	start = unpack_lb64(cbmem.start);
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
 
-	cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size));
-	entries = (struct cbmem_entry *)cbmem_area;
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
 
-	if (entries[0].magic == CBMEM_MAGIC) {
-		dump_static_cbmem_toc(entries);
-	} else {
-		rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size);
-		rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1);
-		rootptr -= sizeof(struct cbmem_root_pointer);
-		unmap_memory();
-		struct cbmem_root_pointer *r =
-			map_memory_size(rootptr, sizeof(*r));
-		if (r->magic == CBMEM_POINTER_MAGIC) {
-			struct cbmem_root *root;
-			uint64_t rootaddr = rootptr + r->root_offset;
-			unmap_memory();
-			root = map_memory_size(rootaddr, ROOT_MIN_SIZE);
-			dump_dynamic_cbmem_toc(root);
-		} else
-			fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n");
+		lbe = (void *)lbr;
+		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
+		i++;
 	}
 
-	unmap_memory();
+	unmap_lbtable();
 }
 
 #define COVERAGE_MAGIC 0x584d4153
@@ -857,42 +837,19 @@ static int mkpath(char *path, mode_t mode)
 
 static void dump_coverage(void)
 {
-	int i, found = 0;
 	uint64_t start;
-	struct cbmem_entry *entries;
+	size_t size;
 	void *coverage;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot table area found!\n");
+	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
+		fprintf(stderr, "No coverage information found\n");
 		return;
 	}
 
-	start = unpack_lb64(cbmem.start);
-
-	entries = (struct cbmem_entry *)map_memory(start);
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		if (entries[i].id == CBMEM_ID_COVERAGE) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (!found) {
-		unmap_memory();
-		fprintf(stderr, "No coverage information found in"
-			" CBMEM area.\n");
-		return;
-	}
-
-	start = entries[i].base;
-	unmap_memory();
 	/* Map coverage area */
-	coverage = map_memory(start);
+	coverage = map_memory_size(start, size);
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
 
 	printf("Dumping coverage data...\n");


From gerrit at coreboot.org  Wed Sep 30 17:38:11 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 17:38:11 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbmem: add
	coreboot table records for each cbmem entry
References: <I125940aa1898c3e99077ead0660eff8aa905b13b+0@gerrit.coreboot.org>
Message-ID: <I125940aa1898c3e99077ead0660eff8aa905b13b+2@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11757

-gerrit

commit c98052d93f0ccb08f173e7670d452323d8f6751b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:26:54 2015 -0500

    cbmem: add coreboot table records for each cbmem entry
    
    In order to not expose the cbmem data structures to usersland
    that are used by coreboot internally add each of the cbmem
    entries to a coreboot table record. The payload ABI uses
    coreboot tables so this just provides a shortcut for cbmem
    entries which were manually added previously by doing the
    work on behalf of all entries.
    
    The imd code added a cursor structure and associated functions
    for walking the entries in order to be placed in the tables.
    Additionally a struct lb_cbmem_entry was added that lists
    the base address, size, and id of the cbmem entry.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Booted glados. View coreboot table entries with cbmem.
    
    Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 13 +++++++
 src/include/cbmem.h                               |  4 +--
 src/include/imd.h                                 | 16 +++++++++
 src/lib/coreboot_table.c                          |  3 ++
 src/lib/imd.c                                     | 44 +++++++++++++++++++++++
 src/lib/imd_cbmem.c                               | 36 +++++++++++++++++--
 6 files changed, 112 insertions(+), 4 deletions(-)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 2ed4d7f..5e0c87c 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -308,6 +308,19 @@ struct lb_boot_media_params {
 	uint64_t boot_media_size;
 };
 
+/*
+ * There can be more than one of these records as there is one per cbmem entry.
+ */
+#define LB_TAG_CBMEM_ENTRY 0x0031
+struct lb_cbmem_entry {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t address;
+	uint32_t entry_size;
+	uint32_t id;
+};
+
 #define LB_TAG_SERIALNO		0x002a
 #define MAX_SERIALNO_LENGTH	32
 
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 60de5a7..810a2a9 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,6 +21,7 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
+#include <boot/coreboot_tables.h>
 #include <commonlib/cbmem_id.h>
 #include <rules.h>
 
@@ -118,12 +119,11 @@ typedef void (* const cbmem_init_hook_t)(int is_recovery);
 void cbmem_run_init_hooks(int is_recovery);
 void cbmem_fail_resume(void);
 
-#ifndef __PRE_RAM__
 /* Ramstage only functions. */
 /* Add the cbmem memory used to the memory map at boot. */
 void cbmem_add_bootmem(void);
 void cbmem_list(void);
-#endif /* __PRE_RAM__ */
+void cbmem_add_records_to_cbtable(struct lb_header *header);
 
 #if ENV_RAMSTAGE
 #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
diff --git a/src/include/imd.h b/src/include/imd.h
index a444b4f..f55820f 100644
--- a/src/include/imd.h
+++ b/src/include/imd.h
@@ -124,6 +124,9 @@ size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry);
 /* Returns pointer to region described by entry or NULL on failure. */
 void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry);
 
+/* Returns id for the imd entry. */
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry);
+
 /* Attempt to remove entry from imd. */
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry);
 
@@ -136,6 +139,13 @@ struct imd_lookup {
 int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 			size_t size);
 
+struct imd_cursor;
+/* Initialize a imd_cursor object to walk the IMD entries. */
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor);
+
+/* Retrive the next imd entry the cursor is referencing. Returns NULL when
+ * no more entries exist. */
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor);
 
 /*
  * The struct imd is a handle for working with an in-memory directory.
@@ -152,4 +162,10 @@ struct imd {
 	struct imdr sm;
 };
 
+struct imd_cursor {
+	size_t current_imdr;
+	size_t current_entry;
+	const struct imdr *imdr[2];
+};
+
 #endif /* _IMD_H_ */
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6859bf2..1bd356d 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -517,6 +517,9 @@ unsigned long write_coreboot_table(
 
 	lb_boot_media_params(head);
 
+	/* Add all cbmem entries into the coreboot tables. */
+	cbmem_add_records_to_cbtable(head);
+
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head);
 }
diff --git a/src/lib/imd.c b/src/lib/imd.c
index 612e3f1..67a76a4 100644
--- a/src/lib/imd.c
+++ b/src/lib/imd.c
@@ -627,6 +627,11 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry)
 	return imdr_entry_at(imdr, entry);
 }
 
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry)
+{
+	return entry->id;
+}
+
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry)
 {
 	struct imd_root *r;
@@ -702,3 +707,42 @@ int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 
 	return 0;
 }
+
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor)
+{
+	if (imd == NULL || cursor == NULL)
+		return -1;
+
+	memset(cursor, 0, sizeof(*cursor));
+
+	cursor->imdr[0] = &imd->lg;
+	cursor->imdr[1] = &imd->sm;
+
+	return 0;
+}
+
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor)
+{
+	struct imd_root *r;
+	const struct imd_entry *e;
+
+	if (cursor->current_imdr >= ARRAY_SIZE(cursor->imdr))
+		return NULL;
+
+	r = imdr_root(cursor->imdr[cursor->current_imdr]);
+
+	if (r == NULL)
+		return NULL;
+
+	if (cursor->current_entry >= r->num_entries) {
+		/* Try next imdr. */
+		cursor->current_imdr++;
+		cursor->current_entry = 0;
+		return imd_cursor_next(cursor);
+	}
+
+	e = &r->entries[cursor->current_entry];
+	cursor->current_entry++;
+
+	return e;
+}
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index fa65334..82961be 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -267,7 +267,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry)
 	return imd_entry_at(imd, cbmem_to_imd(entry));
 }
 
-#if ENV_RAMSTAGE
 void cbmem_add_bootmem(void)
 {
 	void *base = NULL;
@@ -283,4 +282,37 @@ void cbmem_list(void)
 
 	imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup));
 }
-#endif /* __PRE_RAM__ */
+
+void cbmem_add_records_to_cbtable(struct lb_header *header)
+{
+	struct imd_cursor cursor;
+	struct imd *imd;
+
+	imd = cbmem_get_imd();
+
+	if (imd_cursor_init(imd, &cursor))
+		return;
+
+	while (1) {
+		const struct imd_entry *e;
+		struct lb_cbmem_entry *lbe;
+		uint32_t id;
+
+		e = imd_cursor_next(&cursor);
+
+		if (e == NULL)
+			break;
+
+		id = imd_entry_id(imd, e);
+		/* Don't add these metadata entries. */
+		if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL)
+			continue;
+
+		lbe = (struct lb_cbmem_entry *)lb_new_record(header);
+		lbe->tag = LB_TAG_CBMEM_ENTRY;
+		lbe->size = sizeof(*lbe);
+		lbe->address = (uintptr_t)imd_entry_at(imd, e);
+		lbe->entry_size = imd_entry_size(imd, e);
+		lbe->id = id;
+	}
+}


From gerrit at coreboot.org  Wed Sep 30 17:58:05 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 17:58:05 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: util/cbmem:
	remove duplicated cbmem data structure logic.
References: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+0@gerrit.coreboot.org>
Message-ID: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11758

-gerrit

commit 1a4f59b7a121a7d5bd2f4d54bcc4bcd26dda9761
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:33:01 2015 -0500

    util/cbmem: remove duplicated cbmem data structure logic.
    
    The cbmem utility shouldn't be using the intra coreboot
    data structures for obtaining the produced data/information.
    Instead use the newly added cbmem records in the coreboot
    tables for pulling out the data one wants by using the
    generic indexing of coreboot table entries.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Interrogated cbmem table of contents with updated code.
    
    Change-Id: I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c
---
 util/cbmem/cbmem.c | 203 +++++++++++++++++++++--------------------------------
 1 file changed, 80 insertions(+), 123 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 74cb52d..3e4b8a0 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -60,8 +60,8 @@ static int verbose = 0;
 /* File handle used to access /dev/mem */
 static int mem_fd;
 
-/* IMD root pointer location */
-static uint64_t rootptr = 0;
+static uint64_t lbtable_address;
+static size_t lbtable_size;
 
 /*
  * calculate ip checksum (16 bit quantities) on a passed in buffer. In case
@@ -171,9 +171,57 @@ static void *map_memory_size(u64 physical, size_t size)
 	return v;
 }
 
-static void *map_memory(u64 physical)
+static void *map_lbtable(void)
 {
-	return map_memory_size(physical, MAP_BYTES);
+	if (lbtable_address == 0 || lbtable_size == 0) {
+		fprintf(stderr, "No coreboot table area found!\n");
+		return NULL;
+	}
+
+	return map_memory_size(lbtable_address, lbtable_size);
+}
+
+static void unmap_lbtable(void)
+{
+	unmap_memory();
+}
+
+/* Find the first cbmem entry filling in the details. */
+static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
+{
+	uint8_t *table;
+	size_t offset;
+	int ret = -1;
+
+	table = map_lbtable();
+
+	if (table == NULL)
+		return -1;
+
+	offset = 0;
+
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
+
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		lbe = (void *)lbr;
+		if (lbe->id != id)
+			continue;
+
+		*addr = lbe->address;
+		*size = lbe->entry_size;
+		ret = 0;
+		break;
+	}
+
+	unmap_lbtable();
+	return ret;
 }
 
 /*
@@ -244,6 +292,11 @@ static int parse_cbtable(u64 address, size_t table_size)
 		found = 1;
 		debug("Found!\n");
 
+		/* Keep reference to lbtable. */
+		lbtable_address = address;
+		lbtable_address += ((uint8_t *)lbtable - (uint8_t *)lbh);
+		lbtable_size = lbh->table_bytes;
+
 		for (j = 0; j < lbh->table_bytes; j += lbr_p->size) {
 			lbr_p = (struct lb_record*) ((char *)lbtable + j);
 			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
@@ -692,44 +745,6 @@ static void dump_cbmem_hex(void)
 	hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size));
 }
 
-/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */
-#define DYN_CBMEM_ALIGN_SIZE (4096)
-#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE
-#define CBMEM_POINTER_MAGIC 0xc0389481
-#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC)
-
-struct cbmem_root_pointer {
-	uint32_t magic;
-	/* Relative to upper limit/offset. */
-	int32_t root_offset;
-} __attribute__((packed));
-
-struct dynamic_cbmem_entry {
-	uint32_t magic;
-	int32_t start_offset;
-	uint32_t size;
-	uint32_t id;
-} __attribute__((packed));
-
-struct cbmem_root {
-	uint32_t max_entries;
-	uint32_t num_entries;
-	uint32_t flags;
-	uint32_t entry_align;
-	int32_t max_offset;
-	struct dynamic_cbmem_entry entries[0];
-} __attribute__((packed));
-
-#define CBMEM_MAGIC 0x434f5245
-#define MAX_CBMEM_ENTRIES 16
-
-struct cbmem_entry {
-	uint32_t magic;
-	uint32_t id;
-	uint64_t base;
-	uint64_t size;
-} __attribute__((packed));
-
 struct cbmem_id_to_name {
 	uint32_t id;
 	const char *name;
@@ -758,74 +773,39 @@ void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 	printf("  %08" PRIx64 "\n", size);
 }
 
-static void dump_static_cbmem_toc(struct cbmem_entry *entries)
+static void dump_cbmem_toc(void)
 {
 	int i;
+	uint8_t *table;
+	size_t offset;
 
-	printf("CBMEM table of contents:\n");
-	printf("    ID           START      LENGTH\n");
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		cbmem_print_entry(i, entries[i].id,
-				entries[i].base, entries[i].size);
-	}
-}
+	table = map_lbtable();
 
-static void dump_dynamic_cbmem_toc(struct cbmem_root *root)
-{
-	int i;
-	debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n",
-		root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset);
+	if (table == NULL)
+		return;
 
 	printf("CBMEM table of contents:\n");
 	printf("    ID           START      LENGTH\n");
 
-	for (i = 0; i < root->num_entries; i++) {
-		if(root->entries[i].magic != CBMEM_ENTRY_MAGIC)
-			break;
-		cbmem_print_entry(i, root->entries[i].id,
-			rootptr + root->entries[i].start_offset, root->entries[i].size);
-	}
-}
-
-static void dump_cbmem_toc(void)
-{
-	uint64_t start;
-	void *cbmem_area;
-	struct cbmem_entry *entries;
+	i = 0;
+	offset = 0;
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot CBMEM area found!\n");
-		return;
-	}
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
 
-	start = unpack_lb64(cbmem.start);
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
 
-	cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size));
-	entries = (struct cbmem_entry *)cbmem_area;
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
 
-	if (entries[0].magic == CBMEM_MAGIC) {
-		dump_static_cbmem_toc(entries);
-	} else {
-		rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size);
-		rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1);
-		rootptr -= sizeof(struct cbmem_root_pointer);
-		unmap_memory();
-		struct cbmem_root_pointer *r =
-			map_memory_size(rootptr, sizeof(*r));
-		if (r->magic == CBMEM_POINTER_MAGIC) {
-			struct cbmem_root *root;
-			uint64_t rootaddr = rootptr + r->root_offset;
-			unmap_memory();
-			root = map_memory_size(rootaddr, ROOT_MIN_SIZE);
-			dump_dynamic_cbmem_toc(root);
-		} else
-			fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n");
+		lbe = (void *)lbr;
+		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
+		i++;
 	}
 
-	unmap_memory();
+	unmap_lbtable();
 }
 
 #define COVERAGE_MAGIC 0x584d4153
@@ -857,42 +837,19 @@ static int mkpath(char *path, mode_t mode)
 
 static void dump_coverage(void)
 {
-	int i, found = 0;
 	uint64_t start;
-	struct cbmem_entry *entries;
+	size_t size;
 	void *coverage;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot table area found!\n");
+	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
+		fprintf(stderr, "No coverage information found\n");
 		return;
 	}
 
-	start = unpack_lb64(cbmem.start);
-
-	entries = (struct cbmem_entry *)map_memory(start);
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		if (entries[i].id == CBMEM_ID_COVERAGE) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (!found) {
-		unmap_memory();
-		fprintf(stderr, "No coverage information found in"
-			" CBMEM area.\n");
-		return;
-	}
-
-	start = entries[i].base;
-	unmap_memory();
 	/* Map coverage area */
-	coverage = map_memory(start);
+	coverage = map_memory_size(start, size);
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
 
 	printf("Dumping coverage data...\n");


From gerrit at coreboot.org  Wed Sep 30 17:58:11 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 17:58:11 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbmem: add
	coreboot table records for each cbmem entry
References: <I125940aa1898c3e99077ead0660eff8aa905b13b+0@gerrit.coreboot.org>
Message-ID: <I125940aa1898c3e99077ead0660eff8aa905b13b+3@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11757

-gerrit

commit 7ba4a3c14cda44319f25c2de2080b42486c5421c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:26:54 2015 -0500

    cbmem: add coreboot table records for each cbmem entry
    
    In order to not expose the cbmem data structures to usersland
    that are used by coreboot internally add each of the cbmem
    entries to a coreboot table record. The payload ABI uses
    coreboot tables so this just provides a shortcut for cbmem
    entries which were manually added previously by doing the
    work on behalf of all entries.
    
    The imd code added a cursor structure and associated functions
    for walking the entries in order to be placed in the tables.
    Additionally a struct lb_cbmem_entry was added that lists
    the base address, size, and id of the cbmem entry.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Booted glados. View coreboot table entries with cbmem.
    
    Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 13 +++++++
 src/include/cbmem.h                               |  4 +--
 src/include/imd.h                                 | 16 +++++++++
 src/lib/coreboot_table.c                          |  3 ++
 src/lib/imd.c                                     | 44 +++++++++++++++++++++++
 src/lib/imd_cbmem.c                               | 36 +++++++++++++++++--
 6 files changed, 112 insertions(+), 4 deletions(-)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 2ed4d7f..5e0c87c 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -308,6 +308,19 @@ struct lb_boot_media_params {
 	uint64_t boot_media_size;
 };
 
+/*
+ * There can be more than one of these records as there is one per cbmem entry.
+ */
+#define LB_TAG_CBMEM_ENTRY 0x0031
+struct lb_cbmem_entry {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t address;
+	uint32_t entry_size;
+	uint32_t id;
+};
+
 #define LB_TAG_SERIALNO		0x002a
 #define MAX_SERIALNO_LENGTH	32
 
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 60de5a7..b34cf06 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -41,6 +41,7 @@
 #ifndef __ASSEMBLER__
 #include <stddef.h>
 #include <stdint.h>
+#include <boot/coreboot_tables.h>
 
 struct cbmem_entry;
 
@@ -118,12 +119,11 @@ typedef void (* const cbmem_init_hook_t)(int is_recovery);
 void cbmem_run_init_hooks(int is_recovery);
 void cbmem_fail_resume(void);
 
-#ifndef __PRE_RAM__
 /* Ramstage only functions. */
 /* Add the cbmem memory used to the memory map at boot. */
 void cbmem_add_bootmem(void);
 void cbmem_list(void);
-#endif /* __PRE_RAM__ */
+void cbmem_add_records_to_cbtable(struct lb_header *header);
 
 #if ENV_RAMSTAGE
 #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
diff --git a/src/include/imd.h b/src/include/imd.h
index a444b4f..f55820f 100644
--- a/src/include/imd.h
+++ b/src/include/imd.h
@@ -124,6 +124,9 @@ size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry);
 /* Returns pointer to region described by entry or NULL on failure. */
 void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry);
 
+/* Returns id for the imd entry. */
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry);
+
 /* Attempt to remove entry from imd. */
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry);
 
@@ -136,6 +139,13 @@ struct imd_lookup {
 int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 			size_t size);
 
+struct imd_cursor;
+/* Initialize a imd_cursor object to walk the IMD entries. */
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor);
+
+/* Retrive the next imd entry the cursor is referencing. Returns NULL when
+ * no more entries exist. */
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor);
 
 /*
  * The struct imd is a handle for working with an in-memory directory.
@@ -152,4 +162,10 @@ struct imd {
 	struct imdr sm;
 };
 
+struct imd_cursor {
+	size_t current_imdr;
+	size_t current_entry;
+	const struct imdr *imdr[2];
+};
+
 #endif /* _IMD_H_ */
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6859bf2..1bd356d 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -517,6 +517,9 @@ unsigned long write_coreboot_table(
 
 	lb_boot_media_params(head);
 
+	/* Add all cbmem entries into the coreboot tables. */
+	cbmem_add_records_to_cbtable(head);
+
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head);
 }
diff --git a/src/lib/imd.c b/src/lib/imd.c
index 612e3f1..67a76a4 100644
--- a/src/lib/imd.c
+++ b/src/lib/imd.c
@@ -627,6 +627,11 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry)
 	return imdr_entry_at(imdr, entry);
 }
 
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry)
+{
+	return entry->id;
+}
+
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry)
 {
 	struct imd_root *r;
@@ -702,3 +707,42 @@ int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 
 	return 0;
 }
+
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor)
+{
+	if (imd == NULL || cursor == NULL)
+		return -1;
+
+	memset(cursor, 0, sizeof(*cursor));
+
+	cursor->imdr[0] = &imd->lg;
+	cursor->imdr[1] = &imd->sm;
+
+	return 0;
+}
+
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor)
+{
+	struct imd_root *r;
+	const struct imd_entry *e;
+
+	if (cursor->current_imdr >= ARRAY_SIZE(cursor->imdr))
+		return NULL;
+
+	r = imdr_root(cursor->imdr[cursor->current_imdr]);
+
+	if (r == NULL)
+		return NULL;
+
+	if (cursor->current_entry >= r->num_entries) {
+		/* Try next imdr. */
+		cursor->current_imdr++;
+		cursor->current_entry = 0;
+		return imd_cursor_next(cursor);
+	}
+
+	e = &r->entries[cursor->current_entry];
+	cursor->current_entry++;
+
+	return e;
+}
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index fa65334..82961be 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -267,7 +267,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry)
 	return imd_entry_at(imd, cbmem_to_imd(entry));
 }
 
-#if ENV_RAMSTAGE
 void cbmem_add_bootmem(void)
 {
 	void *base = NULL;
@@ -283,4 +282,37 @@ void cbmem_list(void)
 
 	imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup));
 }
-#endif /* __PRE_RAM__ */
+
+void cbmem_add_records_to_cbtable(struct lb_header *header)
+{
+	struct imd_cursor cursor;
+	struct imd *imd;
+
+	imd = cbmem_get_imd();
+
+	if (imd_cursor_init(imd, &cursor))
+		return;
+
+	while (1) {
+		const struct imd_entry *e;
+		struct lb_cbmem_entry *lbe;
+		uint32_t id;
+
+		e = imd_cursor_next(&cursor);
+
+		if (e == NULL)
+			break;
+
+		id = imd_entry_id(imd, e);
+		/* Don't add these metadata entries. */
+		if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL)
+			continue;
+
+		lbe = (struct lb_cbmem_entry *)lb_new_record(header);
+		lbe->tag = LB_TAG_CBMEM_ENTRY;
+		lbe->size = sizeof(*lbe);
+		lbe->address = (uintptr_t)imd_entry_at(imd, e);
+		lbe->entry_size = imd_entry_size(imd, e);
+		lbe->id = id;
+	}
+}


From gerrit at coreboot.org  Wed Sep 30 18:41:09 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 18:41:09 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: util/cbmem:
	remove duplicated cbmem data structure logic.
References: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+0@gerrit.coreboot.org>
Message-ID: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11758

-gerrit

commit 41cc5ebdb8601fc2340588059e4238e1a5356f07
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:33:01 2015 -0500

    util/cbmem: remove duplicated cbmem data structure logic.
    
    The cbmem utility shouldn't be using the intra coreboot
    data structures for obtaining the produced data/information.
    Instead use the newly added cbmem records in the coreboot
    tables for pulling out the data one wants by using the
    generic indexing of coreboot table entries.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Interrogated cbmem table of contents with updated code.
    
    Change-Id: I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c
---
 util/cbmem/cbmem.c | 203 +++++++++++++++++++++--------------------------------
 1 file changed, 80 insertions(+), 123 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 74cb52d..3e4b8a0 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -60,8 +60,8 @@ static int verbose = 0;
 /* File handle used to access /dev/mem */
 static int mem_fd;
 
-/* IMD root pointer location */
-static uint64_t rootptr = 0;
+static uint64_t lbtable_address;
+static size_t lbtable_size;
 
 /*
  * calculate ip checksum (16 bit quantities) on a passed in buffer. In case
@@ -171,9 +171,57 @@ static void *map_memory_size(u64 physical, size_t size)
 	return v;
 }
 
-static void *map_memory(u64 physical)
+static void *map_lbtable(void)
 {
-	return map_memory_size(physical, MAP_BYTES);
+	if (lbtable_address == 0 || lbtable_size == 0) {
+		fprintf(stderr, "No coreboot table area found!\n");
+		return NULL;
+	}
+
+	return map_memory_size(lbtable_address, lbtable_size);
+}
+
+static void unmap_lbtable(void)
+{
+	unmap_memory();
+}
+
+/* Find the first cbmem entry filling in the details. */
+static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
+{
+	uint8_t *table;
+	size_t offset;
+	int ret = -1;
+
+	table = map_lbtable();
+
+	if (table == NULL)
+		return -1;
+
+	offset = 0;
+
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
+
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		lbe = (void *)lbr;
+		if (lbe->id != id)
+			continue;
+
+		*addr = lbe->address;
+		*size = lbe->entry_size;
+		ret = 0;
+		break;
+	}
+
+	unmap_lbtable();
+	return ret;
 }
 
 /*
@@ -244,6 +292,11 @@ static int parse_cbtable(u64 address, size_t table_size)
 		found = 1;
 		debug("Found!\n");
 
+		/* Keep reference to lbtable. */
+		lbtable_address = address;
+		lbtable_address += ((uint8_t *)lbtable - (uint8_t *)lbh);
+		lbtable_size = lbh->table_bytes;
+
 		for (j = 0; j < lbh->table_bytes; j += lbr_p->size) {
 			lbr_p = (struct lb_record*) ((char *)lbtable + j);
 			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
@@ -692,44 +745,6 @@ static void dump_cbmem_hex(void)
 	hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size));
 }
 
-/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */
-#define DYN_CBMEM_ALIGN_SIZE (4096)
-#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE
-#define CBMEM_POINTER_MAGIC 0xc0389481
-#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC)
-
-struct cbmem_root_pointer {
-	uint32_t magic;
-	/* Relative to upper limit/offset. */
-	int32_t root_offset;
-} __attribute__((packed));
-
-struct dynamic_cbmem_entry {
-	uint32_t magic;
-	int32_t start_offset;
-	uint32_t size;
-	uint32_t id;
-} __attribute__((packed));
-
-struct cbmem_root {
-	uint32_t max_entries;
-	uint32_t num_entries;
-	uint32_t flags;
-	uint32_t entry_align;
-	int32_t max_offset;
-	struct dynamic_cbmem_entry entries[0];
-} __attribute__((packed));
-
-#define CBMEM_MAGIC 0x434f5245
-#define MAX_CBMEM_ENTRIES 16
-
-struct cbmem_entry {
-	uint32_t magic;
-	uint32_t id;
-	uint64_t base;
-	uint64_t size;
-} __attribute__((packed));
-
 struct cbmem_id_to_name {
 	uint32_t id;
 	const char *name;
@@ -758,74 +773,39 @@ void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 	printf("  %08" PRIx64 "\n", size);
 }
 
-static void dump_static_cbmem_toc(struct cbmem_entry *entries)
+static void dump_cbmem_toc(void)
 {
 	int i;
+	uint8_t *table;
+	size_t offset;
 
-	printf("CBMEM table of contents:\n");
-	printf("    ID           START      LENGTH\n");
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		cbmem_print_entry(i, entries[i].id,
-				entries[i].base, entries[i].size);
-	}
-}
+	table = map_lbtable();
 
-static void dump_dynamic_cbmem_toc(struct cbmem_root *root)
-{
-	int i;
-	debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n",
-		root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset);
+	if (table == NULL)
+		return;
 
 	printf("CBMEM table of contents:\n");
 	printf("    ID           START      LENGTH\n");
 
-	for (i = 0; i < root->num_entries; i++) {
-		if(root->entries[i].magic != CBMEM_ENTRY_MAGIC)
-			break;
-		cbmem_print_entry(i, root->entries[i].id,
-			rootptr + root->entries[i].start_offset, root->entries[i].size);
-	}
-}
-
-static void dump_cbmem_toc(void)
-{
-	uint64_t start;
-	void *cbmem_area;
-	struct cbmem_entry *entries;
+	i = 0;
+	offset = 0;
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot CBMEM area found!\n");
-		return;
-	}
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
 
-	start = unpack_lb64(cbmem.start);
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
 
-	cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size));
-	entries = (struct cbmem_entry *)cbmem_area;
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
 
-	if (entries[0].magic == CBMEM_MAGIC) {
-		dump_static_cbmem_toc(entries);
-	} else {
-		rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size);
-		rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1);
-		rootptr -= sizeof(struct cbmem_root_pointer);
-		unmap_memory();
-		struct cbmem_root_pointer *r =
-			map_memory_size(rootptr, sizeof(*r));
-		if (r->magic == CBMEM_POINTER_MAGIC) {
-			struct cbmem_root *root;
-			uint64_t rootaddr = rootptr + r->root_offset;
-			unmap_memory();
-			root = map_memory_size(rootaddr, ROOT_MIN_SIZE);
-			dump_dynamic_cbmem_toc(root);
-		} else
-			fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n");
+		lbe = (void *)lbr;
+		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
+		i++;
 	}
 
-	unmap_memory();
+	unmap_lbtable();
 }
 
 #define COVERAGE_MAGIC 0x584d4153
@@ -857,42 +837,19 @@ static int mkpath(char *path, mode_t mode)
 
 static void dump_coverage(void)
 {
-	int i, found = 0;
 	uint64_t start;
-	struct cbmem_entry *entries;
+	size_t size;
 	void *coverage;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot table area found!\n");
+	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
+		fprintf(stderr, "No coverage information found\n");
 		return;
 	}
 
-	start = unpack_lb64(cbmem.start);
-
-	entries = (struct cbmem_entry *)map_memory(start);
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		if (entries[i].id == CBMEM_ID_COVERAGE) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (!found) {
-		unmap_memory();
-		fprintf(stderr, "No coverage information found in"
-			" CBMEM area.\n");
-		return;
-	}
-
-	start = entries[i].base;
-	unmap_memory();
 	/* Map coverage area */
-	coverage = map_memory(start);
+	coverage = map_memory_size(start, size);
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
 
 	printf("Dumping coverage data...\n");


From gerrit at coreboot.org  Wed Sep 30 18:41:18 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 18:41:18 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbmem: add
	coreboot table records for each cbmem entry
References: <I125940aa1898c3e99077ead0660eff8aa905b13b+0@gerrit.coreboot.org>
Message-ID: <I125940aa1898c3e99077ead0660eff8aa905b13b+4@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11757

-gerrit

commit a54e1416b1d48aa33722ff356d04cb4ae4945a01
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:26:54 2015 -0500

    cbmem: add coreboot table records for each cbmem entry
    
    In order to not expose the cbmem data structures to usersland
    that are used by coreboot internally add each of the cbmem
    entries to a coreboot table record. The payload ABI uses
    coreboot tables so this just provides a shortcut for cbmem
    entries which were manually added previously by doing the
    work on behalf of all entries.
    
    The imd code added a cursor structure and associated functions
    for walking the entries in order to be placed in the tables.
    Additionally a struct lb_cbmem_entry was added that lists
    the base address, size, and id of the cbmem entry.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Booted glados. View coreboot table entries with cbmem.
    
    Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 13 +++++++
 src/include/cbmem.h                               |  4 +--
 src/include/imd.h                                 | 16 +++++++++
 src/lib/coreboot_table.c                          |  3 ++
 src/lib/imd.c                                     | 44 +++++++++++++++++++++++
 src/lib/imd_cbmem.c                               | 43 ++++++++++++++++++++--
 6 files changed, 119 insertions(+), 4 deletions(-)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 2ed4d7f..5e0c87c 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -308,6 +308,19 @@ struct lb_boot_media_params {
 	uint64_t boot_media_size;
 };
 
+/*
+ * There can be more than one of these records as there is one per cbmem entry.
+ */
+#define LB_TAG_CBMEM_ENTRY 0x0031
+struct lb_cbmem_entry {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t address;
+	uint32_t entry_size;
+	uint32_t id;
+};
+
 #define LB_TAG_SERIALNO		0x002a
 #define MAX_SERIALNO_LENGTH	32
 
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 60de5a7..b34cf06 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -41,6 +41,7 @@
 #ifndef __ASSEMBLER__
 #include <stddef.h>
 #include <stdint.h>
+#include <boot/coreboot_tables.h>
 
 struct cbmem_entry;
 
@@ -118,12 +119,11 @@ typedef void (* const cbmem_init_hook_t)(int is_recovery);
 void cbmem_run_init_hooks(int is_recovery);
 void cbmem_fail_resume(void);
 
-#ifndef __PRE_RAM__
 /* Ramstage only functions. */
 /* Add the cbmem memory used to the memory map at boot. */
 void cbmem_add_bootmem(void);
 void cbmem_list(void);
-#endif /* __PRE_RAM__ */
+void cbmem_add_records_to_cbtable(struct lb_header *header);
 
 #if ENV_RAMSTAGE
 #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
diff --git a/src/include/imd.h b/src/include/imd.h
index a444b4f..f55820f 100644
--- a/src/include/imd.h
+++ b/src/include/imd.h
@@ -124,6 +124,9 @@ size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry);
 /* Returns pointer to region described by entry or NULL on failure. */
 void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry);
 
+/* Returns id for the imd entry. */
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry);
+
 /* Attempt to remove entry from imd. */
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry);
 
@@ -136,6 +139,13 @@ struct imd_lookup {
 int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 			size_t size);
 
+struct imd_cursor;
+/* Initialize a imd_cursor object to walk the IMD entries. */
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor);
+
+/* Retrive the next imd entry the cursor is referencing. Returns NULL when
+ * no more entries exist. */
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor);
 
 /*
  * The struct imd is a handle for working with an in-memory directory.
@@ -152,4 +162,10 @@ struct imd {
 	struct imdr sm;
 };
 
+struct imd_cursor {
+	size_t current_imdr;
+	size_t current_entry;
+	const struct imdr *imdr[2];
+};
+
 #endif /* _IMD_H_ */
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6859bf2..1bd356d 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -517,6 +517,9 @@ unsigned long write_coreboot_table(
 
 	lb_boot_media_params(head);
 
+	/* Add all cbmem entries into the coreboot tables. */
+	cbmem_add_records_to_cbtable(head);
+
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head);
 }
diff --git a/src/lib/imd.c b/src/lib/imd.c
index 612e3f1..67a76a4 100644
--- a/src/lib/imd.c
+++ b/src/lib/imd.c
@@ -627,6 +627,11 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry)
 	return imdr_entry_at(imdr, entry);
 }
 
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry)
+{
+	return entry->id;
+}
+
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry)
 {
 	struct imd_root *r;
@@ -702,3 +707,42 @@ int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 
 	return 0;
 }
+
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor)
+{
+	if (imd == NULL || cursor == NULL)
+		return -1;
+
+	memset(cursor, 0, sizeof(*cursor));
+
+	cursor->imdr[0] = &imd->lg;
+	cursor->imdr[1] = &imd->sm;
+
+	return 0;
+}
+
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor)
+{
+	struct imd_root *r;
+	const struct imd_entry *e;
+
+	if (cursor->current_imdr >= ARRAY_SIZE(cursor->imdr))
+		return NULL;
+
+	r = imdr_root(cursor->imdr[cursor->current_imdr]);
+
+	if (r == NULL)
+		return NULL;
+
+	if (cursor->current_entry >= r->num_entries) {
+		/* Try next imdr. */
+		cursor->current_imdr++;
+		cursor->current_entry = 0;
+		return imd_cursor_next(cursor);
+	}
+
+	e = &r->entries[cursor->current_entry];
+	cursor->current_entry++;
+
+	return e;
+}
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index fa65334..d60acc9 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -267,7 +267,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry)
 	return imd_entry_at(imd, cbmem_to_imd(entry));
 }
 
-#if ENV_RAMSTAGE
 void cbmem_add_bootmem(void)
 {
 	void *base = NULL;
@@ -277,10 +276,50 @@ void cbmem_add_bootmem(void)
 	bootmem_add_range((uintptr_t)base, size, LB_MEM_TABLE);
 }
 
+#if ENV_RAMSTAGE
+/*
+ * -fdata-sections doesn't work so well on read only strings. They all
+ * get put in the same section even though those strings may never be
+ * referenced in the final binary.
+ */
 void cbmem_list(void)
 {
 	static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE };
 
 	imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup));
 }
-#endif /* __PRE_RAM__ */
+#endif
+
+void cbmem_add_records_to_cbtable(struct lb_header *header)
+{
+	struct imd_cursor cursor;
+	struct imd *imd;
+
+	imd = cbmem_get_imd();
+
+	if (imd_cursor_init(imd, &cursor))
+		return;
+
+	while (1) {
+		const struct imd_entry *e;
+		struct lb_cbmem_entry *lbe;
+		uint32_t id;
+
+		e = imd_cursor_next(&cursor);
+
+		if (e == NULL)
+			break;
+
+		id = imd_entry_id(imd, e);
+		/* Don't add these metadata entries. */
+		if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL)
+			continue;
+
+		lbe = (struct lb_cbmem_entry *)lb_new_record(header);
+		lbe->tag = LB_TAG_CBMEM_ENTRY;
+		lbe->size = sizeof(*lbe);
+		lbe->address = (uintptr_t)imd_entry_at(imd, e);
+		lbe->entry_size = imd_entry_size(imd, e);
+		lbe->id = id;
+	}
+}


From gerrit at coreboot.org  Wed Sep 30 18:41:21 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 18:41:21 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	tegra132/tegra210: remove verstage.c
References: <I5d38c0a87d057622a3706bf3bde1142944c3b17c+0@gerrit.coreboot.org>
Message-ID: <I5d38c0a87d057622a3706bf3bde1142944c3b17c+1@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11759

-gerrit

commit 9f7a083882b39fda8bd5447d6fabd61402d64053
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 13:29:15 2015 -0500

    tegra132/tegra210: remove verstage.c
    
    I missed these Makefile.inc changes. As verstage.c was removed
    remove the references within the Makefile.incs.
    
    Change-Id: I5d38c0a87d057622a3706bf3bde1142944c3b17c
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/nvidia/tegra132/Makefile.inc | 1 -
 src/soc/nvidia/tegra210/Makefile.inc | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index bdd8074..54530b1 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -21,7 +21,6 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 endif
 
-verstage-y += verstage.c
 verstage-y += dma.c
 verstage-y += monotonic_timer.c
 verstage-y += spi.c
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc
index fb38d38..90b60b5e 100644
--- a/src/soc/nvidia/tegra210/Makefile.inc
+++ b/src/soc/nvidia/tegra210/Makefile.inc
@@ -23,7 +23,6 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 endif
 
-verstage-y += verstage.c
 verstage-y += dma.c
 verstage-y += monotonic_timer.c
 verstage-y += spi.c


From gerrit at coreboot.org  Wed Sep 30 19:33:11 2015
From: gerrit at coreboot.org (Paul Kocialkowski (contact@paulk.fr))
Date: Wed, 30 Sep 2015 19:33:11 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: chromeos:
	vboot_common: Avoid code duplication when grabbing the handoff info
References: <I28f1decce98f988f90c446a3a0dbe7409d714527+0@gerrit.coreboot.org>
Message-ID: <I28f1decce98f988f90c446a3a0dbe7409d714527+5@gerrit.coreboot.org>

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11498

-gerrit

commit d24592268b2d08fde103f6a09e21e7600bc7b93e
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:44:56 2015 +0200

    chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
    
    vboot_handoff_flag was duplicating the logic to grab the handoff info, that is
    already made available with vboot_get_handoff_info.
    This uses vboot_get_handoff_info in vboot_handoff_flag instead.
    
    Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/vendorcode/google/chromeos/vboot_common.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 1c216d0..6184b0d 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -58,10 +58,9 @@ int vboot_get_handoff_info(void **addr, uint32_t *size)
 static int vboot_handoff_flag(uint32_t flag)
 {
 	struct vboot_handoff *vbho;
+	uint32_t size;
 
-	vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
-
-	if (vbho == NULL)
+	if (vboot_get_handoff_info((void **)&vbho, &size))
 		return 0;
 
 	return !!(vbho->init_params.out_flags & flag);


From gerrit at coreboot.org  Wed Sep 30 20:05:52 2015
From: gerrit at coreboot.org (Audrey Pearson (apearson@raptorengineeringinc.com))
Date: Wed, 30 Sep 2015 20:05:52 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot:
	northbridge/intel/gm45: Fix native VGA init
References: <Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25+0@gerrit.coreboot.org>
Message-ID: <Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25+2@gerrit.coreboot.org>

Audrey Pearson (apearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11738

-gerrit

commit 44a9388820a437f9239d4246d3c66bcd8e6939aa
Author: Audrey Pearson <apearson at raptorengineeringinc.com>
Date:   Tue Sep 29 12:36:52 2015 -0500

    northbridge/intel/gm45: Fix native VGA init
    
    Building an image for the Lenovo X200 with native graphics
    initialization selected fails due to the changes introduced
    by commit a3b898aa (edid: Clean-up the edid struct).
    
    Change-Id: Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25
    Signed-off-by: Audrey Pearson <apearson at raptorengineeringinc.com>
---
 src/northbridge/intel/gm45/gma.c | 32 +++++++++++++++++---------------
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index f29b9b1..42b340a 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -109,6 +109,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 	int i;
 	u8 edid_data[128];
 	struct edid edid;
+	struct edid_mode *mode;
 	u32 hactive, vactive, right_border, bottom_border;
 	int hpolarity, vpolarity;
 	u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
@@ -155,25 +156,26 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 	intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128);
 	decode_edid(edid_data,
 		    sizeof(edid_data), &edid);
+	mode = &edid.mode;
 
 	/* Disable screen memory to prevent garbage from appearing.  */
 	vga_sr_write(1, vga_sr_read(1) | 0x20);
 
 	hactive = edid.x_resolution;
 	vactive = edid.y_resolution;
-	right_border = edid.hborder;
-	bottom_border = edid.vborder;
-	hpolarity = (edid.phsync == '-');
-	vpolarity = (edid.pvsync == '-');
-	vsync = edid.vspw;
-	hsync = edid.hspw;
-	vblank = edid.vbl;
-	hblank = edid.hbl;
-	hfront_porch = edid.hso;
-	vfront_porch = edid.vso;
-
-	target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
-		: (2 * edid.pixel_clock);
+	right_border = mode->hborder;
+	bottom_border = mode->vborder;
+	hpolarity = (mode->phsync == '-');
+	vpolarity = (mode->pvsync == '-');
+	vsync = mode->vspw;
+	hsync = mode->hspw;
+	vblank = mode->vbl;
+	hblank = mode->hbl;
+	hfront_porch = mode->hso;
+	vfront_porch = mode->vso;
+
+	target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock
+		: (2 * mode->pixel_clock);
 #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_sr_write(1, 1);
 	vga_sr_write(0x2, 0xf);
@@ -240,8 +242,8 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 		return;
 	}
 
-	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
-	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
+	link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
+	data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
 		/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",


From gerrit at coreboot.org  Wed Sep 30 20:05:54 2015
From: gerrit at coreboot.org (Audrey Pearson (apearson@raptorengineeringinc.com))
Date: Wed, 30 Sep 2015 20:05:54 +0000
Subject: [coreboot-gerrit] New patch to review for coreboot:
	northbridge/intel/gm45: Use IS_ENABLED macro to increase
	build coverage
References: <I4bd689af5459b23ebc74c7623fefd56785af96f0+0@gerrit.coreboot.org>
Message-ID: <I4bd689af5459b23ebc74c7623fefd56785af96f0+1@gerrit.coreboot.org>

Audrey Pearson (apearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11760

-gerrit

commit 7e67fcb9a2691b5447a0cbb31e77293667db024e
Author: Audrey Pearson <apearson at raptorengineeringinc.com>
Date:   Wed Sep 30 14:44:13 2015 -0500

    northbridge/intel/gm45: Use IS_ENABLED macro to increase build coverage
    
    Change-Id: I4bd689af5459b23ebc74c7623fefd56785af96f0
    Signed-off-by: Audrey Pearson <apearson at raptorengineeringinc.com>
---
 src/northbridge/intel/gm45/gma.c | 780 +++++++++++++++++++--------------------
 1 file changed, 390 insertions(+), 390 deletions(-)

diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 42b340a..1c47c2a 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -46,392 +46,392 @@ void gtt_write(u32 reg, u32 data)
 	write32(res2mmio(gtt_res, reg, 0), data);
 }
 
-#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-
 static void power_port(u8 *mmio)
 {
-	read32(mmio + 0x00061100); // = 0x00000000
-	write32(mmio + 0x00061100, 0x00000000);
-	write32(mmio + 0x00061100, 0x00010000);
-	read32(mmio + 0x00061100); // = 0x00010000
-	read32(mmio + 0x00061100); // = 0x00010000
-	read32(mmio + 0x00061100); // = 0x00000000
-	write32(mmio + 0x00061100, 0x00000000);
-	read32(mmio + 0x00061100); // = 0x00000000
-	read32(mmio + 0x00064200); // = 0x0000001c
-	write32(mmio + 0x00064210, 0x8004003e);
-	write32(mmio + 0x00064214, 0x80060002);
-	write32(mmio + 0x00064218, 0x01000000);
-	read32(mmio + 0x00064210); // = 0x5144003e
-	write32(mmio + 0x00064210, 0x5344003e);
-	read32(mmio + 0x00064210); // = 0x0144003e
-	write32(mmio + 0x00064210, 0x8074003e);
-	read32(mmio + 0x00064210); // = 0x5144003e
-	read32(mmio + 0x00064210); // = 0x5144003e
-	write32(mmio + 0x00064210, 0x5344003e);
-	read32(mmio + 0x00064210); // = 0x0144003e
-	write32(mmio + 0x00064210, 0x8074003e);
-	read32(mmio + 0x00064210); // = 0x5144003e
-	read32(mmio + 0x00064210); // = 0x5144003e
-	write32(mmio + 0x00064210, 0x5344003e);
-	read32(mmio + 0x00064210); // = 0x0144003e
-	write32(mmio + 0x00064210, 0x8074003e);
-	read32(mmio + 0x00064210); // = 0x5144003e
-	read32(mmio + 0x00064210); // = 0x5144003e
-	write32(mmio + 0x00064210, 0x5344003e);
-	write32(mmio + 0x00064f00, 0x0100030c);
-	write32(mmio + 0x00064f04, 0x00b8230c);
-	write32(mmio + 0x00064f08, 0x06f8930c);
-	write32(mmio + 0x00064f0c, 0x09f8e38e);
-	write32(mmio + 0x00064f10, 0x00b8030c);
-	write32(mmio + 0x00064f14, 0x0b78830c);
-	write32(mmio + 0x00064f18, 0x0ff8d3cf);
-	write32(mmio + 0x00064f1c, 0x01e8030c);
-	write32(mmio + 0x00064f20, 0x0ff863cf);
-	write32(mmio + 0x00064f24, 0x0ff803cf);
-	write32(mmio + 0x000c4030, 0x00001000);
-	read32(mmio + 0x00044000); // = 0x00000000
-	write32(mmio + 0x00044030, 0x00001000);
-	read32(mmio + 0x00061150); // = 0x0000001c
-	write32(mmio + 0x00061150, 0x0000089c);
-	write32(mmio + 0x000fcc00, 0x01986f00);
-	write32(mmio + 0x000fcc0c, 0x01986f00);
-	write32(mmio + 0x000fcc18, 0x01986f00);
-	write32(mmio + 0x000fcc24, 0x01986f00);
-	read32(mmio + 0x00044000); // = 0x00000000
-	read32(mmio + LVDS); // = 0x40000002
+	if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+		read32(mmio + 0x00061100); // = 0x00000000
+		write32(mmio + 0x00061100, 0x00000000);
+		write32(mmio + 0x00061100, 0x00010000);
+		read32(mmio + 0x00061100); // = 0x00010000
+		read32(mmio + 0x00061100); // = 0x00010000
+		read32(mmio + 0x00061100); // = 0x00000000
+		write32(mmio + 0x00061100, 0x00000000);
+		read32(mmio + 0x00061100); // = 0x00000000
+		read32(mmio + 0x00064200); // = 0x0000001c
+		write32(mmio + 0x00064210, 0x8004003e);
+		write32(mmio + 0x00064214, 0x80060002);
+		write32(mmio + 0x00064218, 0x01000000);
+		read32(mmio + 0x00064210); // = 0x5144003e
+		write32(mmio + 0x00064210, 0x5344003e);
+		read32(mmio + 0x00064210); // = 0x0144003e
+		write32(mmio + 0x00064210, 0x8074003e);
+		read32(mmio + 0x00064210); // = 0x5144003e
+		read32(mmio + 0x00064210); // = 0x5144003e
+		write32(mmio + 0x00064210, 0x5344003e);
+		read32(mmio + 0x00064210); // = 0x0144003e
+		write32(mmio + 0x00064210, 0x8074003e);
+		read32(mmio + 0x00064210); // = 0x5144003e
+		read32(mmio + 0x00064210); // = 0x5144003e
+		write32(mmio + 0x00064210, 0x5344003e);
+		read32(mmio + 0x00064210); // = 0x0144003e
+		write32(mmio + 0x00064210, 0x8074003e);
+		read32(mmio + 0x00064210); // = 0x5144003e
+		read32(mmio + 0x00064210); // = 0x5144003e
+		write32(mmio + 0x00064210, 0x5344003e);
+		write32(mmio + 0x00064f00, 0x0100030c);
+		write32(mmio + 0x00064f04, 0x00b8230c);
+		write32(mmio + 0x00064f08, 0x06f8930c);
+		write32(mmio + 0x00064f0c, 0x09f8e38e);
+		write32(mmio + 0x00064f10, 0x00b8030c);
+		write32(mmio + 0x00064f14, 0x0b78830c);
+		write32(mmio + 0x00064f18, 0x0ff8d3cf);
+		write32(mmio + 0x00064f1c, 0x01e8030c);
+		write32(mmio + 0x00064f20, 0x0ff863cf);
+		write32(mmio + 0x00064f24, 0x0ff803cf);
+		write32(mmio + 0x000c4030, 0x00001000);
+		read32(mmio + 0x00044000); // = 0x00000000
+		write32(mmio + 0x00044030, 0x00001000);
+		read32(mmio + 0x00061150); // = 0x0000001c
+		write32(mmio + 0x00061150, 0x0000089c);
+		write32(mmio + 0x000fcc00, 0x01986f00);
+		write32(mmio + 0x000fcc0c, 0x01986f00);
+		write32(mmio + 0x000fcc18, 0x01986f00);
+		write32(mmio + 0x000fcc24, 0x01986f00);
+		read32(mmio + 0x00044000); // = 0x00000000
+		read32(mmio + LVDS); // = 0x40000002
+	}
 }
 
 static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 			   u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
 {
+	if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+		int i;
+		u8 edid_data[128];
+		struct edid edid;
+		struct edid_mode *mode;
+		u32 hactive, vactive, right_border, bottom_border;
+		int hpolarity, vpolarity;
+		u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
+		u32 candp1, candn;
+		u32 best_delta = 0xffffffff;
+		u32 target_frequency;
+		u32 pixel_p1 = 1;
+		u32 pixel_n = 1;
+		u32 pixel_m1 = 1;
+		u32 pixel_m2 = 1;
+		u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
+		u32 data_m1;
+		u32 data_n1 = 0x00800000;
+		u32 link_m1;
+		u32 link_n1 = 0x00080000;
+
+		vga_gr_write(0x18, 0);
+
+		/* Setup GTT.  */
+		for (i = 0; i < 0x2000; i++)
+		{
+			outl((i << 2) | 1, piobase);
+			outl(physbase + (i << 12) + 1, piobase + 4);
+		}
 
-	int i;
-	u8 edid_data[128];
-	struct edid edid;
-	struct edid_mode *mode;
-	u32 hactive, vactive, right_border, bottom_border;
-	int hpolarity, vpolarity;
-	u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
-	u32 candp1, candn;
-	u32 best_delta = 0xffffffff;
-	u32 target_frequency;
-	u32 pixel_p1 = 1;
-	u32 pixel_n = 1;
-	u32 pixel_m1 = 1;
-	u32 pixel_m2 = 1;
-	u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
-	u32 data_m1;
-	u32 data_n1 = 0x00800000;
-	u32 link_m1;
-	u32 link_n1 = 0x00080000;
-
-	vga_gr_write(0x18, 0);
-
-	/* Setup GTT.  */
-	for (i = 0; i < 0x2000; i++)
-	{
-		outl((i << 2) | 1, piobase);
-		outl(physbase + (i << 12) + 1, piobase + 4);
-	}
+		write32(mmio + ADPA, 0x40008c18);
+		write32(mmio + 0x7041c, 0x0);
+		write32(mmio + _DPLL_B_MD, 0x3);
+
+		vga_misc_write(0x67);
+
+		const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+			0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+			0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
+			0xff
+		};
+		vga_cr_write(0x11, 0);
+
+		for (i = 0; i <= 0x18; i++)
+			vga_cr_write(i, cr[i]);
+
+		power_port(mmio);
+
+		intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128);
+		decode_edid(edid_data,
+			sizeof(edid_data), &edid);
+		mode = &edid.mode;
+
+		/* Disable screen memory to prevent garbage from appearing.  */
+		vga_sr_write(1, vga_sr_read(1) | 0x20);
+
+		hactive = edid.x_resolution;
+		vactive = edid.y_resolution;
+		right_border = mode->hborder;
+		bottom_border = mode->vborder;
+		hpolarity = (mode->phsync == '-');
+		vpolarity = (mode->pvsync == '-');
+		vsync = mode->vspw;
+		hsync = mode->hspw;
+		vblank = mode->vbl;
+		hblank = mode->hbl;
+		hfront_porch = mode->hso;
+		vfront_porch = mode->vso;
+
+		target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock
+			: (2 * mode->pixel_clock);
+		if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+			vga_sr_write(1, 1);
+			vga_sr_write(0x2, 0xf);
+			vga_sr_write(0x3, 0x0);
+			vga_sr_write(0x4, 0xe);
+			vga_gr_write(0, 0x0);
+			vga_gr_write(1, 0x0);
+			vga_gr_write(2, 0x0);
+			vga_gr_write(3, 0x0);
+			vga_gr_write(4, 0x0);
+			vga_gr_write(5, 0x0);
+			vga_gr_write(6, 0x5);
+			vga_gr_write(7, 0xf);
+			vga_gr_write(0x10, 0x1);
+			vga_gr_write(0x11, 0);
+
+			edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
+
+			write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
+			write32(mmio + DSPADDR(0), 0);
+			write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
+			write32(mmio + DSPSURF(0), 0);
+			for (i = 0; i < 0x100; i++)
+				write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+		} else {
+			vga_textmode_init();
+		}
 
-	write32(mmio + ADPA, 0x40008c18);
-	write32(mmio + 0x7041c, 0x0);
-	write32(mmio + _DPLL_B_MD, 0x3);
-
-	vga_misc_write(0x67);
-
-	const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
-		    0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
-		    0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
-		    0xff
-	};
-	vga_cr_write(0x11, 0);
-
-	for (i = 0; i <= 0x18; i++)
-		vga_cr_write(i, cr[i]);
-
-	power_port(mmio);
-
-	intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128);
-	decode_edid(edid_data,
-		    sizeof(edid_data), &edid);
-	mode = &edid.mode;
-
-	/* Disable screen memory to prevent garbage from appearing.  */
-	vga_sr_write(1, vga_sr_read(1) | 0x20);
-
-	hactive = edid.x_resolution;
-	vactive = edid.y_resolution;
-	right_border = mode->hborder;
-	bottom_border = mode->vborder;
-	hpolarity = (mode->phsync == '-');
-	vpolarity = (mode->pvsync == '-');
-	vsync = mode->vspw;
-	hsync = mode->hspw;
-	vblank = mode->vbl;
-	hblank = mode->hbl;
-	hfront_porch = mode->hso;
-	vfront_porch = mode->vso;
-
-	target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock
-		: (2 * mode->pixel_clock);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	vga_sr_write(1, 1);
-	vga_sr_write(0x2, 0xf);
-	vga_sr_write(0x3, 0x0);
-	vga_sr_write(0x4, 0xe);
-	vga_gr_write(0, 0x0);
-	vga_gr_write(1, 0x0);
-	vga_gr_write(2, 0x0);
-	vga_gr_write(3, 0x0);
-	vga_gr_write(4, 0x0);
-	vga_gr_write(5, 0x0);
-	vga_gr_write(6, 0x5);
-	vga_gr_write(7, 0xf);
-	vga_gr_write(0x10, 0x1);
-	vga_gr_write(0x11, 0);
-
-	edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
-
-	write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
-	write32(mmio + DSPADDR(0), 0);
-	write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
-	write32(mmio + DSPSURF(0), 0);
-	for (i = 0; i < 0x100; i++)
-		write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
-#else
-	vga_textmode_init();
-#endif
-
-	/* Find suitable divisors.  */
-	for (candp1 = 1; candp1 <= 8; candp1++) {
-		for (candn = 5; candn <= 10; candn++) {
-			u32 cur_frequency;
-			u32 m; /* 77 - 131.  */
-			u32 denom; /* 35 - 560.  */
-			u32 current_delta;
-
-			denom = candn * candp1 * 7;
-			/* Doesnt overflow for up to
-			   5000000 kHz = 5 GHz.  */
-			m = (target_frequency * denom + 60000) / 120000;
-
-			if (m < 77 || m > 131)
-				continue;
-
-			cur_frequency = (120000 * m) / denom;
-			if (target_frequency > cur_frequency)
-				current_delta = target_frequency - cur_frequency;
-			else
-				current_delta = cur_frequency - target_frequency;
-
-
-			if (best_delta > current_delta) {
-				best_delta = current_delta;
-				pixel_n = candn;
-				pixel_p1 = candp1;
-				pixel_m2 = ((m + 3) % 5) + 7;
-				pixel_m1 = (m - pixel_m2) / 5;
+		/* Find suitable divisors.  */
+		for (candp1 = 1; candp1 <= 8; candp1++) {
+			for (candn = 5; candn <= 10; candn++) {
+				u32 cur_frequency;
+				u32 m; /* 77 - 131.  */
+				u32 denom; /* 35 - 560.  */
+				u32 current_delta;
+
+				denom = candn * candp1 * 7;
+				/* Doesnt overflow for up to
+				5000000 kHz = 5 GHz.  */
+				m = (target_frequency * denom + 60000) / 120000;
+
+				if (m < 77 || m > 131)
+					continue;
+
+				cur_frequency = (120000 * m) / denom;
+				if (target_frequency > cur_frequency)
+					current_delta = target_frequency - cur_frequency;
+				else
+					current_delta = cur_frequency - target_frequency;
+
+
+				if (best_delta > current_delta) {
+					best_delta = current_delta;
+					pixel_n = candn;
+					pixel_p1 = candp1;
+					pixel_m2 = ((m + 3) % 5) + 7;
+					pixel_m1 = (m - pixel_m2) / 5;
+				}
 			}
 		}
-	}
 
-	if (best_delta == 0xffffffff) {
-		printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
-		return;
-	}
+		if (best_delta == 0xffffffff) {
+			printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
+			return;
+		}
 
-	link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
-	data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
-		/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
-
-	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
-	       hactive, vactive);
-	printk(BIOS_DEBUG, "Borders %d x %d\n",
-	       right_border, bottom_border);
-	printk(BIOS_DEBUG, "Blank %d x %d\n",
-	       hblank, vblank);
-	printk(BIOS_DEBUG, "Sync %d x %d\n",
-	       hsync, vsync);
-	printk(BIOS_DEBUG, "Front porch %d x %d\n",
-	       hfront_porch, vfront_porch);
-	printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
-			    ? "Spread spectrum clock\n" : "DREF clock\n"));
-	printk(BIOS_DEBUG,
-	       info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
-	printk(BIOS_DEBUG, "Polarities %d, %d\n",
-	       hpolarity, vpolarity);
-	printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
-	       data_m1, data_n1);
-	printk(BIOS_DEBUG, "Link frequency %d kHz\n",
-	       link_frequency);
-	printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
-	       link_m1, link_n1);
-	printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
-	       pixel_n, pixel_m1, pixel_m2, pixel_p1);
-	printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
-	       120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
-	       / (pixel_p1 * 7));
-
-	write32(mmio + LVDS,
-		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
-		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
-		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-	mdelay(1);
-	write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
-		| (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-	write32(mmio + FP0(0),
-		((pixel_n - 2) << 16)
-		| ((pixel_m1 - 2) << 8) | pixel_m2);
-	write32(mmio + DPLL(0),
-		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
-		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
-		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
-		| (0x1 << (pixel_p1 - 1)));
-	mdelay(1);
-	write32(mmio + DPLL(0),
-		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
-		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
-		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
-		| (0x1 << (pixel_p1 - 1)));
-	/* Re-lock the registers.  */
-	write32(mmio + PP_CONTROL,
-		(read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-
-	write32(mmio + LVDS,
-		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
-		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
-		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-
-	write32(mmio + HTOTAL(0),
-		((hactive + right_border + hblank - 1) << 16)
-		| (hactive - 1));
-	write32(mmio + HBLANK(0),
-		((hactive + right_border + hblank - 1) << 16)
-		| (hactive + right_border - 1));
-	write32(mmio + HSYNC(0),
-		((hactive + right_border + hfront_porch + hsync - 1) << 16)
-		| (hactive + right_border + hfront_porch - 1));
-
-	write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
-		| (vactive - 1));
-	write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
-		| (vactive + bottom_border - 1));
-	write32(mmio + VSYNC(0),
-		(vactive + bottom_border + vfront_porch + vsync - 1)
-		| (vactive + bottom_border + vfront_porch - 1));
-
-	write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-
-	write32(mmio + PF_WIN_POS(0), 0);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
-	write32(mmio + PF_CTL(0),0);
-	write32(mmio + PF_WIN_SZ(0), 0);
-	write32(mmio + PFIT_CONTROL, 0x20000000);
-#else
-	write32(mmio + PIPESRC(0), (639 << 16) | 399);
-	write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
-	write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-	write32(mmio + PFIT_CONTROL, 0xa0000000);
-#endif
-
-	mdelay(1);
-
-	write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
-	write32(mmio + PIPE_DATA_N1(0), data_n1);
-	write32(mmio + PIPE_LINK_M1(0), link_m1);
-	write32(mmio + PIPE_LINK_N1(0), link_n1);
-
-	write32(mmio + 0x000f000c, 0x00002040);
-	mdelay(1);
-	write32(mmio + 0x000f000c, 0x00002050);
-	write32(mmio + 0x00060100, 0x00044000);
-	mdelay(1);
-	write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
-	write32(mmio + 0x000f0008, 0x00000040);
-	write32(mmio + 0x000f000c, 0x00022050);
-	write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
-	write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
-
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE);
-	write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-	mdelay(1);
-#else
-	write32(mmio + VGACNTRL, 0x22c4008e);
-#endif
-
-	write32(mmio + TRANS_HTOTAL(0),
-		((hactive + right_border + hblank - 1) << 16)
-		| (hactive - 1));
-	write32(mmio + TRANS_HBLANK(0),
-		((hactive + right_border + hblank - 1) << 16)
-		| (hactive + right_border - 1));
-	write32(mmio + TRANS_HSYNC(0),
-		((hactive + right_border + hfront_porch + hsync - 1) << 16)
-		| (hactive + right_border + hfront_porch - 1));
-
-	write32(mmio + TRANS_VTOTAL(0),
-		((vactive + bottom_border + vblank - 1) << 16)
-		| (vactive - 1));
-	write32(mmio + TRANS_VBLANK(0),
-		((vactive + bottom_border + vblank - 1) << 16)
-		| (vactive + bottom_border - 1));
-	write32(mmio + TRANS_VSYNC(0),
-		(vactive + bottom_border + vfront_porch + vsync - 1)
-		| (vactive + bottom_border + vfront_porch - 1));
-
-	write32(mmio + 0x00060100, 0xb01c4000);
-	write32(mmio + 0x000f000c, 0xb01a2050);
-	mdelay(1);
-	write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
-		);
-	write32(mmio + LVDS,
-		LVDS_PORT_ENABLE
-		| (hpolarity << 20) | (vpolarity << 21)
-		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
-		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
-		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-
-	write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
-	write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
-	mdelay(1);
-	write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
-		| PANEL_POWER_ON | PANEL_POWER_RESET);
-
-	printk (BIOS_DEBUG, "waiting for panel powerup\n");
-	while (1) {
-		u32 reg32;
-		reg32 = read32(mmio + PP_STATUS);
-		if (((reg32 >> 28) & 3) == 0)
-			break;
-	}
-	printk (BIOS_DEBUG, "panel powered up\n");
+		link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
+		data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
+			/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
+
+		printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
+		hactive, vactive);
+		printk(BIOS_DEBUG, "Borders %d x %d\n",
+		right_border, bottom_border);
+		printk(BIOS_DEBUG, "Blank %d x %d\n",
+		hblank, vblank);
+		printk(BIOS_DEBUG, "Sync %d x %d\n",
+		hsync, vsync);
+		printk(BIOS_DEBUG, "Front porch %d x %d\n",
+		hfront_porch, vfront_porch);
+		printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
+				? "Spread spectrum clock\n" : "DREF clock\n"));
+		printk(BIOS_DEBUG,
+		info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
+		printk(BIOS_DEBUG, "Polarities %d, %d\n",
+		hpolarity, vpolarity);
+		printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
+		data_m1, data_n1);
+		printk(BIOS_DEBUG, "Link frequency %d kHz\n",
+		link_frequency);
+		printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
+		link_m1, link_n1);
+		printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
+		pixel_n, pixel_m1, pixel_m2, pixel_p1);
+		printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
+		120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
+		/ (pixel_p1 * 7));
+
+		write32(mmio + LVDS,
+			(hpolarity << 20) | (vpolarity << 21)
+			| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+			| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
+			| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
+		mdelay(1);
+		write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
+			| (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
+		write32(mmio + FP0(0),
+			((pixel_n - 2) << 16)
+			| ((pixel_m1 - 2) << 8) | pixel_m2);
+		write32(mmio + DPLL(0),
+			DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
+			| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+			: DPLLB_LVDS_P2_CLOCK_DIV_14)
+			| (0x10000 << (pixel_p1 - 1))
+			| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
+			| (0x1 << (pixel_p1 - 1)));
+		mdelay(1);
+		write32(mmio + DPLL(0),
+			DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
+			| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+			: DPLLB_LVDS_P2_CLOCK_DIV_14)
+			| (0x10000 << (pixel_p1 - 1))
+			| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
+			| (0x1 << (pixel_p1 - 1)));
+		/* Re-lock the registers.  */
+		write32(mmio + PP_CONTROL,
+			(read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
+
+		write32(mmio + LVDS,
+			(hpolarity << 20) | (vpolarity << 21)
+			| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+			| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
+			| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
+
+		write32(mmio + HTOTAL(0),
+			((hactive + right_border + hblank - 1) << 16)
+			| (hactive - 1));
+		write32(mmio + HBLANK(0),
+			((hactive + right_border + hblank - 1) << 16)
+			| (hactive + right_border - 1));
+		write32(mmio + HSYNC(0),
+			((hactive + right_border + hfront_porch + hsync - 1) << 16)
+			| (hactive + right_border + hfront_porch - 1));
+
+		write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
+			| (vactive - 1));
+		write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
+			| (vactive + bottom_border - 1));
+		write32(mmio + VSYNC(0),
+			(vactive + bottom_border + vfront_porch + vsync - 1)
+			| (vactive + bottom_border + vfront_porch - 1));
+
+		write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
+
+		write32(mmio + PF_WIN_POS(0), 0);
+		if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+			write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
+			write32(mmio + PF_CTL(0),0);
+			write32(mmio + PF_WIN_SZ(0), 0);
+			write32(mmio + PFIT_CONTROL, 0x20000000);
+		} else {
+			write32(mmio + PIPESRC(0), (639 << 16) | 399);
+			write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+			write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+			write32(mmio + PFIT_CONTROL, 0xa0000000);
+		}
+
+		mdelay(1);
+
+		write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
+		write32(mmio + PIPE_DATA_N1(0), data_n1);
+		write32(mmio + PIPE_LINK_M1(0), link_m1);
+		write32(mmio + PIPE_LINK_N1(0), link_n1);
+
+		write32(mmio + 0x000f000c, 0x00002040);
+		mdelay(1);
+		write32(mmio + 0x000f000c, 0x00002050);
+		write32(mmio + 0x00060100, 0x00044000);
+		mdelay(1);
+		write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
+		write32(mmio + 0x000f0008, 0x00000040);
+		write32(mmio + 0x000f000c, 0x00022050);
+		write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+		write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+
+		if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+			write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE);
+			write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+			mdelay(1);
+		} else {
+			write32(mmio + VGACNTRL, 0x22c4008e);
+		}
+
+		write32(mmio + TRANS_HTOTAL(0),
+			((hactive + right_border + hblank - 1) << 16)
+			| (hactive - 1));
+		write32(mmio + TRANS_HBLANK(0),
+			((hactive + right_border + hblank - 1) << 16)
+			| (hactive + right_border - 1));
+		write32(mmio + TRANS_HSYNC(0),
+			((hactive + right_border + hfront_porch + hsync - 1) << 16)
+			| (hactive + right_border + hfront_porch - 1));
+
+		write32(mmio + TRANS_VTOTAL(0),
+			((vactive + bottom_border + vblank - 1) << 16)
+			| (vactive - 1));
+		write32(mmio + TRANS_VBLANK(0),
+			((vactive + bottom_border + vblank - 1) << 16)
+			| (vactive + bottom_border - 1));
+		write32(mmio + TRANS_VSYNC(0),
+			(vactive + bottom_border + vfront_porch + vsync - 1)
+			| (vactive + bottom_border + vfront_porch - 1));
+
+		write32(mmio + 0x00060100, 0xb01c4000);
+		write32(mmio + 0x000f000c, 0xb01a2050);
+		mdelay(1);
+		write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+			);
+		write32(mmio + LVDS,
+			LVDS_PORT_ENABLE
+			| (hpolarity << 20) | (vpolarity << 21)
+			| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+			| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
+			| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
+
+		write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+		write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+		mdelay(1);
+		write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
+			| PANEL_POWER_ON | PANEL_POWER_RESET);
+
+		printk (BIOS_DEBUG, "waiting for panel powerup\n");
+		while (1) {
+			u32 reg32;
+			reg32 = read32(mmio + PP_STATUS);
+			if (((reg32 >> 28) & 3) == 0)
+				break;
+		}
+		printk (BIOS_DEBUG, "panel powered up\n");
 
-	write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+		write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
 
-	/* Enable screen memory.  */
-	vga_sr_write(1, vga_sr_read(1) & ~0x20);
+		/* Enable screen memory.  */
+		vga_sr_write(1, vga_sr_read(1) & ~0x20);
 
-	/* Clear interrupts. */
-	write32(mmio + DEIIR, 0xffffffff);
-	write32(mmio + SDEIIR, 0xffffffff);
+		/* Clear interrupts. */
+		write32(mmio + DEIIR, 0xffffffff);
+		write32(mmio + SDEIIR, 0xffffffff);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
-	set_vbe_mode_info_valid(&edid, lfb);
-#endif
+		if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+			memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
+			set_vbe_mode_info_valid(&edid, lfb);
+		}
+	}
 }
 
-#endif
 
 static void gma_func0_init(struct device *dev)
 {
@@ -447,30 +447,30 @@ static void gma_func0_init(struct device *dev)
 
 	struct northbridge_intel_gm45_config *conf = dev->chip_info;
 
-#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
-	/* PCI Init, will run VBIOS */
-	pci_dev_init(dev);
-#else
-	u32 physbase;
-	struct resource *lfb_res;
-	struct resource *pio_res;
-
-	lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
-	pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
-
-	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
-
-	if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base
-	    && lfb_res && lfb_res->base) {
-		printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
-		       gtt_res->base);
-		intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
-			       pio_res->base, lfb_res->base);
-	}
+	if (!CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) {
+		/* PCI Init, will run VBIOS */
+		pci_dev_init(dev);
+	} else {
+		u32 physbase;
+		struct resource *lfb_res;
+		struct resource *pio_res;
+
+		lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
+		pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
+
+		physbase = pci_read_config32(dev, 0x5c) & ~0xf;
 
-	/* Linux relies on VBT for panel info.  */
-	generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
-#endif
+		if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base
+		&& lfb_res && lfb_res->base) {
+			printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
+			gtt_res->base);
+			intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
+				pio_res->base, lfb_res->base);
+		}
+
+		/* Linux relies on VBT for panel info.  */
+		generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
+	}
 
 	/* Post VBIOS init */
 	/* Enable Backlight  */


From gerrit at coreboot.org  Wed Sep 30 20:23:48 2015
From: gerrit at coreboot.org (Maxime de Roucy (maxime.deroucy@gmail.com))
Date: Wed, 30 Sep 2015 20:23:48 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: coreinfo: reboot
	when finished
References: <I00b1f859f76e693e8d49a38c1e02f4f49add85b7+0@gerrit.coreboot.org>
Message-ID: <I00b1f859f76e693e8d49a38c1e02f4f49add85b7+2@gerrit.coreboot.org>

Maxime de Roucy (maxime.deroucy at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11731

-gerrit

commit 3d533a5f66850cb0e69e472fd1ab90a0ae1a1090
Author: Maxime de Roucy <maxime.deroucy at gmail.com>
Date:   Sun Sep 27 15:53:40 2015 +0200

    coreinfo: reboot when finished
    
    Avoid a "General Protection Fault Exception" when launched by SeaBIOS on
    pcengines APU1
    
    Change-Id: I00b1f859f76e693e8d49a38c1e02f4f49add85b7
    Signed-off-by: Maxime de Roucy <maxime.deroucy at gmail.com>
---
 payloads/coreinfo/coreinfo.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c
index 5bd1068..df52056 100644
--- a/payloads/coreinfo/coreinfo.c
+++ b/payloads/coreinfo/coreinfo.c
@@ -301,6 +301,9 @@ int main(void)
 
 	loop();
 
+	/* reboot */
+	outb(0x6, 0xcf9);
+	halt();
 	return 0;
 }
 


From gerrit at coreboot.org  Wed Sep 30 21:18:07 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 21:18:07 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: util/cbmem:
	remove duplicated cbmem data structure logic.
References: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+0@gerrit.coreboot.org>
Message-ID: <I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11758

-gerrit

commit 55525d89e91fb82177e875099923452d9b429213
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:33:01 2015 -0500

    util/cbmem: remove duplicated cbmem data structure logic.
    
    The cbmem utility shouldn't be using the intra coreboot
    data structures for obtaining the produced data/information.
    Instead use the newly added cbmem records in the coreboot
    tables for pulling out the data one wants by using the
    generic indexing of coreboot table entries.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Interrogated cbmem table of contents with updated code.
    
    Change-Id: I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c
---
 util/cbmem/cbmem.c | 203 +++++++++++++++++++++--------------------------------
 1 file changed, 80 insertions(+), 123 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 74cb52d..3e4b8a0 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -60,8 +60,8 @@ static int verbose = 0;
 /* File handle used to access /dev/mem */
 static int mem_fd;
 
-/* IMD root pointer location */
-static uint64_t rootptr = 0;
+static uint64_t lbtable_address;
+static size_t lbtable_size;
 
 /*
  * calculate ip checksum (16 bit quantities) on a passed in buffer. In case
@@ -171,9 +171,57 @@ static void *map_memory_size(u64 physical, size_t size)
 	return v;
 }
 
-static void *map_memory(u64 physical)
+static void *map_lbtable(void)
 {
-	return map_memory_size(physical, MAP_BYTES);
+	if (lbtable_address == 0 || lbtable_size == 0) {
+		fprintf(stderr, "No coreboot table area found!\n");
+		return NULL;
+	}
+
+	return map_memory_size(lbtable_address, lbtable_size);
+}
+
+static void unmap_lbtable(void)
+{
+	unmap_memory();
+}
+
+/* Find the first cbmem entry filling in the details. */
+static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
+{
+	uint8_t *table;
+	size_t offset;
+	int ret = -1;
+
+	table = map_lbtable();
+
+	if (table == NULL)
+		return -1;
+
+	offset = 0;
+
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
+
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		lbe = (void *)lbr;
+		if (lbe->id != id)
+			continue;
+
+		*addr = lbe->address;
+		*size = lbe->entry_size;
+		ret = 0;
+		break;
+	}
+
+	unmap_lbtable();
+	return ret;
 }
 
 /*
@@ -244,6 +292,11 @@ static int parse_cbtable(u64 address, size_t table_size)
 		found = 1;
 		debug("Found!\n");
 
+		/* Keep reference to lbtable. */
+		lbtable_address = address;
+		lbtable_address += ((uint8_t *)lbtable - (uint8_t *)lbh);
+		lbtable_size = lbh->table_bytes;
+
 		for (j = 0; j < lbh->table_bytes; j += lbr_p->size) {
 			lbr_p = (struct lb_record*) ((char *)lbtable + j);
 			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
@@ -692,44 +745,6 @@ static void dump_cbmem_hex(void)
 	hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size));
 }
 
-/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */
-#define DYN_CBMEM_ALIGN_SIZE (4096)
-#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE
-#define CBMEM_POINTER_MAGIC 0xc0389481
-#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC)
-
-struct cbmem_root_pointer {
-	uint32_t magic;
-	/* Relative to upper limit/offset. */
-	int32_t root_offset;
-} __attribute__((packed));
-
-struct dynamic_cbmem_entry {
-	uint32_t magic;
-	int32_t start_offset;
-	uint32_t size;
-	uint32_t id;
-} __attribute__((packed));
-
-struct cbmem_root {
-	uint32_t max_entries;
-	uint32_t num_entries;
-	uint32_t flags;
-	uint32_t entry_align;
-	int32_t max_offset;
-	struct dynamic_cbmem_entry entries[0];
-} __attribute__((packed));
-
-#define CBMEM_MAGIC 0x434f5245
-#define MAX_CBMEM_ENTRIES 16
-
-struct cbmem_entry {
-	uint32_t magic;
-	uint32_t id;
-	uint64_t base;
-	uint64_t size;
-} __attribute__((packed));
-
 struct cbmem_id_to_name {
 	uint32_t id;
 	const char *name;
@@ -758,74 +773,39 @@ void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 	printf("  %08" PRIx64 "\n", size);
 }
 
-static void dump_static_cbmem_toc(struct cbmem_entry *entries)
+static void dump_cbmem_toc(void)
 {
 	int i;
+	uint8_t *table;
+	size_t offset;
 
-	printf("CBMEM table of contents:\n");
-	printf("    ID           START      LENGTH\n");
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		cbmem_print_entry(i, entries[i].id,
-				entries[i].base, entries[i].size);
-	}
-}
+	table = map_lbtable();
 
-static void dump_dynamic_cbmem_toc(struct cbmem_root *root)
-{
-	int i;
-	debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n",
-		root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset);
+	if (table == NULL)
+		return;
 
 	printf("CBMEM table of contents:\n");
 	printf("    ID           START      LENGTH\n");
 
-	for (i = 0; i < root->num_entries; i++) {
-		if(root->entries[i].magic != CBMEM_ENTRY_MAGIC)
-			break;
-		cbmem_print_entry(i, root->entries[i].id,
-			rootptr + root->entries[i].start_offset, root->entries[i].size);
-	}
-}
-
-static void dump_cbmem_toc(void)
-{
-	uint64_t start;
-	void *cbmem_area;
-	struct cbmem_entry *entries;
+	i = 0;
+	offset = 0;
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot CBMEM area found!\n");
-		return;
-	}
+	while (offset < lbtable_size) {
+		struct lb_record *lbr;
+		struct lb_cbmem_entry *lbe;
 
-	start = unpack_lb64(cbmem.start);
+		lbr = (void *)(table + offset);
+		offset += lbr->size;
 
-	cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size));
-	entries = (struct cbmem_entry *)cbmem_area;
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
 
-	if (entries[0].magic == CBMEM_MAGIC) {
-		dump_static_cbmem_toc(entries);
-	} else {
-		rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size);
-		rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1);
-		rootptr -= sizeof(struct cbmem_root_pointer);
-		unmap_memory();
-		struct cbmem_root_pointer *r =
-			map_memory_size(rootptr, sizeof(*r));
-		if (r->magic == CBMEM_POINTER_MAGIC) {
-			struct cbmem_root *root;
-			uint64_t rootaddr = rootptr + r->root_offset;
-			unmap_memory();
-			root = map_memory_size(rootaddr, ROOT_MIN_SIZE);
-			dump_dynamic_cbmem_toc(root);
-		} else
-			fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n");
+		lbe = (void *)lbr;
+		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
+		i++;
 	}
 
-	unmap_memory();
+	unmap_lbtable();
 }
 
 #define COVERAGE_MAGIC 0x584d4153
@@ -857,42 +837,19 @@ static int mkpath(char *path, mode_t mode)
 
 static void dump_coverage(void)
 {
-	int i, found = 0;
 	uint64_t start;
-	struct cbmem_entry *entries;
+	size_t size;
 	void *coverage;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot table area found!\n");
+	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
+		fprintf(stderr, "No coverage information found\n");
 		return;
 	}
 
-	start = unpack_lb64(cbmem.start);
-
-	entries = (struct cbmem_entry *)map_memory(start);
-
-	for (i=0; i<MAX_CBMEM_ENTRIES; i++) {
-		if (entries[i].magic != CBMEM_MAGIC)
-			break;
-		if (entries[i].id == CBMEM_ID_COVERAGE) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (!found) {
-		unmap_memory();
-		fprintf(stderr, "No coverage information found in"
-			" CBMEM area.\n");
-		return;
-	}
-
-	start = entries[i].base;
-	unmap_memory();
 	/* Map coverage area */
-	coverage = map_memory(start);
+	coverage = map_memory_size(start, size);
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
 
 	printf("Dumping coverage data...\n");


From gerrit at coreboot.org  Wed Sep 30 21:18:11 2015
From: gerrit at coreboot.org (Aaron Durbin (adurbin@chromium.org))
Date: Wed, 30 Sep 2015 21:18:11 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: cbmem: add
	coreboot table records for each cbmem entry
References: <I125940aa1898c3e99077ead0660eff8aa905b13b+0@gerrit.coreboot.org>
Message-ID: <I125940aa1898c3e99077ead0660eff8aa905b13b+5@gerrit.coreboot.org>

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11757

-gerrit

commit 881780957aa9a925f6f81183e77d3bcff3d29f87
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 30 12:26:54 2015 -0500

    cbmem: add coreboot table records for each cbmem entry
    
    In order to not expose the cbmem data structures to userland
    that are used by coreboot internally add each of the cbmem
    entries to a coreboot table record. The payload ABI uses
    coreboot tables so this just provides a shortcut for cbmem
    entries which were manually added previously by doing the
    work on behalf of all entries.
    
    A cursor structure and associated functions are added to
    the imd code for walking the entries in order to be placed
    in the coreboot tables.  Additionally a struct lb_cbmem_entry
    is added that lists the base address, size, and id of the
    cbmem entry.
    
    BUG=chrome-os-partner:43731
    BRANCH=None
    TEST=Booted glados. View coreboot table entries with cbmem.
    
    Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 13 +++++++
 src/include/cbmem.h                               |  4 +--
 src/include/imd.h                                 | 16 +++++++++
 src/lib/coreboot_table.c                          |  3 ++
 src/lib/imd.c                                     | 44 +++++++++++++++++++++++
 src/lib/imd_cbmem.c                               | 43 ++++++++++++++++++++--
 6 files changed, 119 insertions(+), 4 deletions(-)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 2ed4d7f..5e0c87c 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -308,6 +308,19 @@ struct lb_boot_media_params {
 	uint64_t boot_media_size;
 };
 
+/*
+ * There can be more than one of these records as there is one per cbmem entry.
+ */
+#define LB_TAG_CBMEM_ENTRY 0x0031
+struct lb_cbmem_entry {
+	uint32_t tag;
+	uint32_t size;
+
+	uint64_t address;
+	uint32_t entry_size;
+	uint32_t id;
+};
+
 #define LB_TAG_SERIALNO		0x002a
 #define MAX_SERIALNO_LENGTH	32
 
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 60de5a7..b34cf06 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -41,6 +41,7 @@
 #ifndef __ASSEMBLER__
 #include <stddef.h>
 #include <stdint.h>
+#include <boot/coreboot_tables.h>
 
 struct cbmem_entry;
 
@@ -118,12 +119,11 @@ typedef void (* const cbmem_init_hook_t)(int is_recovery);
 void cbmem_run_init_hooks(int is_recovery);
 void cbmem_fail_resume(void);
 
-#ifndef __PRE_RAM__
 /* Ramstage only functions. */
 /* Add the cbmem memory used to the memory map at boot. */
 void cbmem_add_bootmem(void);
 void cbmem_list(void);
-#endif /* __PRE_RAM__ */
+void cbmem_add_records_to_cbtable(struct lb_header *header);
 
 #if ENV_RAMSTAGE
 #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
diff --git a/src/include/imd.h b/src/include/imd.h
index a444b4f..b373ab5 100644
--- a/src/include/imd.h
+++ b/src/include/imd.h
@@ -124,6 +124,9 @@ size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry);
 /* Returns pointer to region described by entry or NULL on failure. */
 void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry);
 
+/* Returns id for the imd entry. */
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry);
+
 /* Attempt to remove entry from imd. */
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry);
 
@@ -136,6 +139,13 @@ struct imd_lookup {
 int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 			size_t size);
 
+struct imd_cursor;
+/* Initialize an imd_cursor object to walk the IMD entries. */
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor);
+
+/* Retrieve the next imd entry the cursor is referencing. Returns NULL when
+ * no more entries exist. */
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor);
 
 /*
  * The struct imd is a handle for working with an in-memory directory.
@@ -152,4 +162,10 @@ struct imd {
 	struct imdr sm;
 };
 
+struct imd_cursor {
+	size_t current_imdr;
+	size_t current_entry;
+	const struct imdr *imdr[2];
+};
+
 #endif /* _IMD_H_ */
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6859bf2..1bd356d 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -517,6 +517,9 @@ unsigned long write_coreboot_table(
 
 	lb_boot_media_params(head);
 
+	/* Add all cbmem entries into the coreboot tables. */
+	cbmem_add_records_to_cbtable(head);
+
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head);
 }
diff --git a/src/lib/imd.c b/src/lib/imd.c
index 612e3f1..67a76a4 100644
--- a/src/lib/imd.c
+++ b/src/lib/imd.c
@@ -627,6 +627,11 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry)
 	return imdr_entry_at(imdr, entry);
 }
 
+uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry)
+{
+	return entry->id;
+}
+
 int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry)
 {
 	struct imd_root *r;
@@ -702,3 +707,42 @@ int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup,
 
 	return 0;
 }
+
+int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor)
+{
+	if (imd == NULL || cursor == NULL)
+		return -1;
+
+	memset(cursor, 0, sizeof(*cursor));
+
+	cursor->imdr[0] = &imd->lg;
+	cursor->imdr[1] = &imd->sm;
+
+	return 0;
+}
+
+const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor)
+{
+	struct imd_root *r;
+	const struct imd_entry *e;
+
+	if (cursor->current_imdr >= ARRAY_SIZE(cursor->imdr))
+		return NULL;
+
+	r = imdr_root(cursor->imdr[cursor->current_imdr]);
+
+	if (r == NULL)
+		return NULL;
+
+	if (cursor->current_entry >= r->num_entries) {
+		/* Try next imdr. */
+		cursor->current_imdr++;
+		cursor->current_entry = 0;
+		return imd_cursor_next(cursor);
+	}
+
+	e = &r->entries[cursor->current_entry];
+	cursor->current_entry++;
+
+	return e;
+}
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index fa65334..d60acc9 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -267,7 +267,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry)
 	return imd_entry_at(imd, cbmem_to_imd(entry));
 }
 
-#if ENV_RAMSTAGE
 void cbmem_add_bootmem(void)
 {
 	void *base = NULL;
@@ -277,10 +276,50 @@ void cbmem_add_bootmem(void)
 	bootmem_add_range((uintptr_t)base, size, LB_MEM_TABLE);
 }
 
+#if ENV_RAMSTAGE
+/*
+ * -fdata-sections doesn't work so well on read only strings. They all
+ * get put in the same section even though those strings may never be
+ * referenced in the final binary.
+ */
 void cbmem_list(void)
 {
 	static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE };
 
 	imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup));
 }
-#endif /* __PRE_RAM__ */
+#endif
+
+void cbmem_add_records_to_cbtable(struct lb_header *header)
+{
+	struct imd_cursor cursor;
+	struct imd *imd;
+
+	imd = cbmem_get_imd();
+
+	if (imd_cursor_init(imd, &cursor))
+		return;
+
+	while (1) {
+		const struct imd_entry *e;
+		struct lb_cbmem_entry *lbe;
+		uint32_t id;
+
+		e = imd_cursor_next(&cursor);
+
+		if (e == NULL)
+			break;
+
+		id = imd_entry_id(imd, e);
+		/* Don't add these metadata entries. */
+		if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL)
+			continue;
+
+		lbe = (struct lb_cbmem_entry *)lb_new_record(header);
+		lbe->tag = LB_TAG_CBMEM_ENTRY;
+		lbe->size = sizeof(*lbe);
+		lbe->address = (uintptr_t)imd_entry_at(imd, e);
+		lbe->entry_size = imd_entry_size(imd, e);
+		lbe->id = id;
+	}
+}


From gerrit at coreboot.org  Wed Sep 30 21:22:25 2015
From: gerrit at coreboot.org (Paul Menzel (paulepanter@users.sourceforge.net))
Date: Wed, 30 Sep 2015 21:22:25 +0000
Subject: [coreboot-gerrit] Patch set updated for coreboot: Makefile.inc:
	Align paths in CBFS add messages
References: <Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972+0@gerrit.coreboot.org>
Message-ID: <Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972+2@gerrit.coreboot.org>

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11710

-gerrit

commit 1b6e5bd33f4d163946767577bfadda9743b2d607
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Fri Sep 25 09:18:43 2015 +0200

    Makefile.inc: Align paths in CBFS add messages
    
    Building coreboot with the SeaBIOS or FILO payload selected, their config and
    revision are added to CBFS.
    
    ```
      Creating out/bios.bin.elf
        CBFS       coreboot.rom
        PAYLOAD    payloads/external/SeaBIOS/seabios/out/bios.bin.elf (compression: LZMA)
        CONFIG     .config
        REVISION   build.h
        CONFIG      payloads/external/SeaBIOS/seabios/.config
        REVISION   payloads/external/SeaBIOS/seabios/out/version.c
        CBFSPRINT  coreboot.rom
    ```
    
    Align the path of the payload config by removing one space.
    
    Change-Id: Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile.inc b/Makefile.inc
index ac6ce0b..3c4848e 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -659,7 +659,7 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y)
 endif
 endif
 ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y)
-	@printf "    CONFIG      $(PAYLOAD_CONFIG)\n"
+	@printf "    CONFIG     $(PAYLOAD_CONFIG)\n"
 	if [ -f "$(PAYLOAD_CONFIG)" ]; then \
 		$(CBFSTOOL) $@.tmp add -f  "$(PAYLOAD_CONFIG)" -n payload_config -t raw; \
 	fi


From gerrit at coreboot.org  Wed Sep 30 21:31:59 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 21:31:59 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: chromeos:
	vboot_common: Avoid code duplication when grabbing the handoff info
References: <I28f1decce98f988f90c446a3a0dbe7409d714527+0@gerrit.coreboot.org>
Message-ID: <E1ZhOyl-0006tm-U4@mail.coreboot.org>

the following patch was just integrated into master:
commit 3faea59e26bc535f0b1827a2249e36abf2d08f6a
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Thu Sep 3 11:44:56 2015 +0200

    chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
    
    vboot_handoff_flag was duplicating the logic to grab the handoff info, that is
    already made available with vboot_get_handoff_info.
    This uses vboot_get_handoff_info in vboot_handoff_flag instead.
    
    Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
    Reviewed-on: http://review.coreboot.org/11498
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11498 for details.

-gerrit


From gerrit at coreboot.org  Wed Sep 30 23:35:40 2015
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 30 Sep 2015 23:35:40 +0000
Subject: [coreboot-gerrit] Patch merged into coreboot/master: Makefile.inc:
	Align paths in CBFS add messages
References: <Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972+0@gerrit.coreboot.org>
Message-ID: <E1ZhQuS-00014P-DQ@mail.coreboot.org>

the following patch was just integrated into master:
commit 16fa8823f8289b74f575243cea277dc8743fd024
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Fri Sep 25 09:18:43 2015 +0200

    Makefile.inc: Align paths in CBFS add messages
    
    Building coreboot with the SeaBIOS or FILO payload selected, their config and
    revision are added to CBFS.
    
    ```
      Creating out/bios.bin.elf
        CBFS       coreboot.rom
        PAYLOAD    payloads/external/SeaBIOS/seabios/out/bios.bin.elf (compression: LZMA)
        CONFIG     .config
        REVISION   build.h
        CONFIG      payloads/external/SeaBIOS/seabios/.config
        REVISION   payloads/external/SeaBIOS/seabios/out/version.c
        CBFSPRINT  coreboot.rom
    ```
    
    Align the path of the payload config by removing one space.
    
    Change-Id: Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/11710
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See http://review.coreboot.org/11710 for details.

-gerrit