[coreboot-gerrit] Patch set updated for coreboot: x86: link ramstage like the other architectures

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508

-gerrit

commit 693dc60b11bb82a616ee2e8191716e40947001d3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 4 10:19:05 2015 -0500

    x86: link ramstage like the other architectures
    
    All the other architectures are using the memlayout
    for linking ramstage. The last piece to align x86 is
    to use arch/header.ld and the macros within memlayout.h
    to automaticaly generate the necessary linker script.
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built a myriad of boards. Analyzed readelf output.
    
    Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
    Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
 src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
 src/arch/x86/ramstage.ld            | 24 +++---------------------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		: text segment
- *				: rodata segment
- *				: data segment
- *				: bss segment
- *				: stack
- *				: heap
- */
-ENTRY(_start)
-
-PHDRS
-{
-	to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
 
 SECTIONS
 {
-	. = CONFIG_RAMBASE;
-
-	INCLUDE "lib/program.ramstage.ld"
-
-	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
 }