[coreboot-gerrit] New patch to review for coreboot: verstage: use common program.ld for linking
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Sat Sep 5 16:13:02 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516
-gerrit
commit a7a39e52530ea4f465a0bdd76fff655f54e56774
Author: Aaron Durbin <adurbin at chromium.org>
Date: Sat Sep 5 11:08:02 2015 -0500
verstage: use common program.ld for linking
There's no reason to have a separate verstage.ld now
that there is a unified stage linking strategy. Moreover
verstage support is throughout the code base as it is
so bring in those link script macros into the common
memlayout.h as that removes one more specific thing a
board/chipset needs to do in order to turn on verstage.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=None
Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
Signed-off-by: Aaron Durbin <adubin at chromium.org>
---
src/include/memlayout.h | 27 ++++++++++
src/lib/Makefile.inc | 1 +
src/soc/broadcom/cygnus/include/soc/memlayout.ld | 1 -
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 1 -
src/soc/marvell/bg4cd/include/soc/memlayout.ld | 1 -
src/soc/nvidia/tegra124/include/soc/memlayout.ld | 1 -
.../tegra132/include/soc/memlayout_vboot2.ld | 1 -
.../tegra210/include/soc/memlayout_vboot2.ld | 1 -
src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 1 -
src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 -
.../samsung/exynos5250/include/soc/memlayout.ld | 1 -
src/vendorcode/google/chromeos/memlayout.h | 54 --------------------
src/vendorcode/google/chromeos/vboot2/Makefile.inc | 2 -
src/vendorcode/google/chromeos/vboot2/verstage.ld | 58 ----------------------
14 files changed, 28 insertions(+), 123 deletions(-)
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 1a38256..02f67db 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -139,6 +139,33 @@
. += sz;
#endif
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
+#define VBOOT2_WORK(addr, size) \
+ REGION(vboot2_work, addr, size, 16) \
+ _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
+
+#if ENV_VERSTAGE
+ #define VERSTAGE(addr, sz) \
+ SET_COUNTER(verstage, addr) \
+ _ = ASSERT(_eprogram - _program <= sz, \
+ STR(Verstage exceeded its allotted size! (sz))); \
+ INCLUDE "lib/program.verstage.ld"
+
+ #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
+#else
+ #define VERSTAGE(addr, sz) \
+ SET_COUNTER(verstage, addr) \
+ . += sz;
+
+ #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
+#endif
+
+#define WATCHDOG_TOMBSTONE(addr, size) \
+ REGION(watchdog_tombstone, addr, size, 4) \
+ _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
#if ENV_RAMSTAGE || ENV_ROMSTAGE
#define CBMEM_INIT_HOOKS \
POINTER_ALIGN \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 464d631..d8cd1d8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -199,6 +199,7 @@ endif
romstage-y += program.ld
ramstage-y += program.ld
+verstage-y += program.ld
ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
ramstage-y += rmodule.c
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index 5e149b4..237ffc6 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 366b20a..59e3017 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
index 15c09d9..45835e2 100644
--- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld
+++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 2312cc9..561833d 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 0f98fd2..a8164a9 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index c140e01..dee6798 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -18,7 +18,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..ad0977a 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -19,7 +19,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 0b75932..b96923e 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 3b5b034..4469078 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -18,7 +18,6 @@
*/
#include <memlayout.h>
-#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
deleted file mode 100644
index e86246f..0000000
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file contains macro definitions for memlayout.ld linker scripts. */
-
-#ifndef __CHROMEOS_MEMLAYOUT_H
-#define __CHROMEOS_MEMLAYOUT_H
-
-/* Careful: required work buffer size depends on RW properties such as key size
- * and algorithm -- what works for you might stop working after an update. Do
- * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
-#define VBOOT2_WORK(addr, size) \
- REGION(vboot2_work, addr, size, 16) \
- _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
-
-#ifdef __VERSTAGE__
- #define VERSTAGE(addr, sz) \
- SET_COUNTER(verstage, addr) \
- _ = ASSERT(_eprogram - _program <= sz, \
- STR(Verstage exceeded its allotted size! (sz))); \
- INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld"
-#else
- #define VERSTAGE(addr, sz) \
- SET_COUNTER(verstage, addr) \
- . += sz;
-#endif
-
-#ifdef __VERSTAGE__
- #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
-#else
- #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
-#endif
-
-#define WATCHDOG_TOMBSTONE(addr, size) \
- REGION(watchdog_tombstone, addr, size, 4) \
- _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
-
-#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index b805993..21613ba 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c
ramstage-y += common.c
-verstage-y += verstage.ld
-
ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
else
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld
deleted file mode 100644
index fcb8af8..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstage.ld
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
- _program = .;
- _verstage = .;
- *(.text._start);
- *(.text.stage_entry);
- *(.text);
- *(.text.*);
-} : to_load
-
-.data . : {
- *(.rodata);
- *(.rodata.*);
- *(.data);
- *(.data.*);
- . = ALIGN(8);
-}
-
-.bss . : {
- . = ALIGN(8);
- _bss = .;
- *(.bss)
- *(.bss.*)
- *(.sbss)
- *(.sbss.*)
- _ebss = .;
- _everstage = .;
- _eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- *(.eh_frame);
-}
More information about the coreboot-gerrit
mailing list