[coreboot-gerrit] New patch to review for coreboot: skylake: ACPI: Move storage controllers to separate file

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11535

-gerrit

commit b554ae8eedfea1c8c961391ea58522eeef253343
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 16:53:45 2015 -0700

    skylake: ACPI: Move storage controllers to separate file
    
    Move the storage controller devices out of serialio.asl
    and into a new scs.asl file and implement the power
    gating workarounds for D0 and D3 transitions.
    
    BUG=chrome-os-partner:44622
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529
    Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295908
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi/pch.asl      |   2 +
 src/soc/intel/skylake/acpi/scs.asl      | 125 ++++++++++++++++++++++++++++++++
 src/soc/intel/skylake/acpi/serialio.asl |  29 --------
 3 files changed, 127 insertions(+), 29 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index c72a704..f2c1a16 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -46,6 +46,8 @@
 /* SMBus 0:1f.3 */
 #include "smbus.asl"
 
+/* Storage Controllers */
+#include "scs.asl"
 
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
new file mode 100644
index 0000000..4eb9683
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* Intel Storage Controllers */
+
+Device (EMMC)
+{
+	Name (_ADR, 0x001E0004)
+	Name (_DDN, "eMMC Controller")
+
+	OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
+	Field (EMCR, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x84),	/* PMECTRLSTATUS */
+		D0D3, 2,	/* POWERSTATE */
+		Offset (0xa2),	/* PG_CONFIG */
+		, 2,
+		PGEN, 1,	/* PG_ENABLE */
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		/* Disable Power Good */
+		Store (0, ^PGEN)
+
+		/* Clear bits 31, 6, 2, 0 */
+		^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA)
+		Sleep (2)
+
+		/* Set bits 31, 6, 2, 0 */
+		^^PCRO (PID_SCS, 0x600, 0x80000045)
+
+		/* Set Power State to D0 */
+		Store (0, ^D0D3)
+		Store (^D0D3, Local0)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		/* Enable Power Good */
+		Store (1, ^PGEN)
+
+		/* Set Power State to D0 */
+		Store (3, ^D0D3)
+		Store (^D0D3, Local0)
+	}
+
+	Device (CARD)
+	{
+		Name (_ADR, 0x00000008)
+		Method (_RMV, 0, NotSerialized)
+		{
+			Return (0)
+		}
+	}
+}
+
+Device (SDXC)
+{
+	Name (_ADR, 0x001E0006)
+	Name (_DDN, "SD Controller")
+
+	OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
+	Field (SDCR, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x84),	/* PMECTRLSTATUS */
+		D0D3, 2,	/* POWERSTATE */
+		Offset (0xa2),	/* PG_CONFIG */
+		, 2,
+		PGEN, 1,	/* PG_ENABLE */
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		/* Disable Power Good */
+		Store (0, ^PGEN)
+
+		/* Clear bits 8, 7, 2, 0 */
+		^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
+		Sleep (2)
+
+		/* Set bits 31, 6, 2, 0 */
+		^^PCRO (PID_SCS, 0x600, 0x00000185)
+
+		/* Set Power State to D0 */
+		Store (0, ^D0D3)
+		Store (^D0D3, Local0)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		/* Enable Power Good */
+		Store (1, ^PGEN)
+
+		/* Set Power State to D0 */
+		Store (3, ^D0D3)
+		Store (^D0D3, Local0)
+	}
+
+	Device (CARD)
+	{
+		Name (_ADR, 0x00000008)
+		Method (_RMV, 0, NotSerialized)
+		{
+			Return (1)
+		}
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl
index e57b937..d3dca7f 100644
--- a/src/soc/intel/skylake/acpi/serialio.asl
+++ b/src/soc/intel/skylake/acpi/serialio.asl
@@ -618,32 +618,3 @@ Device (UAR2)
 		^^LPD3 (\SAB1, \SAEN)
 	}
 }
-
-
-Device (PEMC)
-{
-	Name (_ADR, 0x001E0004)
-	Device (CARD)
-	{
-		Name (_ADR, 0x00000008)
-		Method (_RMV, 0x0, NotSerialized)
-		{
-			Return (0)
-		}
-	}
-}
-
-/* SD controller */
-Device (PSDC)
-{
-	Name (_ADR, 0x001E0006)
-	Device (CARD)
-	{
-		Name (_ADR, 0x00000008)
-		Method (_RMV, 0x0, NotSerialized)
-		{
-			Return (1)
-		}
-	}
-}
-