[coreboot-gerrit] New patch to review for coreboot: kunimitsu: Clean up devicetree.cb
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Sep 7 18:43:06 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11562
-gerrit
commit ff1bc7d2b9dac92a7be1f5fea9c9fafe9f2a35dd
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Thu Sep 3 16:05:00 2015 -0700
kunimitsu: Clean up devicetree.cb
Fix the PCI device list comments to be consistent between
mainboards and remove unused and incorrect register settings.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8
Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9
Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297339
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/intel/kunimitsu/devicetree.cb | 182 ++++++++++++----------------
1 file changed, 79 insertions(+), 103 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 5cc4f2e..f1480f3 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -1,132 +1,104 @@
chip soc/intel/skylake
- # SerialIO device modes
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoPci, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoPci, \
- }"
-
- register "PortUsb20Enable[0]" = "1" # Type-C Port 1
- register "PortUsb20Enable[1]" = "1" # Type-C Port 2
- register "PortUsb20Enable[2]" = "1" # Bluetooth
- register "PortUsb20Enable[4]" = "1" # Type-A Port (card)
- register "PortUsb20Enable[6]" = "1" # Camera
- register "PortUsb20Enable[8]" = "1" # Type-A Port (board)
-
- register "PortUsb30Enable[0]" = "1" # Type-C Port 1
- register "PortUsb30Enable[1]" = "1" # Type-C Port 2
- register "PortUsb30Enable[2]" = "1" # Type-A Port (card)
- register "PortUsb30Enable[3]" = "1" # Type-A Port (board)
-
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
-
- # Pcie RootPort
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpClkReqNumber[0]" = "1"
- register "PcieRpClkReqNumber[4]" = "2"
- register "PcieRpClkReqSupport[0]" = "1"
- register "PcieRpClkReqSupport[4]" = "1"
+ # Enable deep Sx states
+ register "deep_s3_enable" = "1"
+ register "deep_s5_enable" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
# GPE configuration
- register "gpe0_en_1" = "0x00000000"
-
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command range is in 0x800-0x8ff
+ register "gen1_dec" = "0x00fc0801"
- # Memory related
+ # FSP Configuration
register "ProbelessTrace" = "0"
-
- # Lan
register "EnableLan" = "0"
-
- # SATA related
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
- register "SsicPortEnable" = "0"
-
- # Audio related
register "EnableAzalia" = "1"
- register "EnableTraceHub" = "0"
register "DspEnable" = "1"
-
- # I/O Buffer Ownership:
- # 0: HD-A Link
- # 1 Shared, HD-A Link and I2S Port
- # 3: I2S Ports
register "IoBufferOwnership" = "3"
-
- # SMBUS
+ register "EnableTraceHub" = "0"
+ register "XdciEnable" = "0"
+ register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
-
- # Camera
register "Cio2Enable" = "0"
-
- # eMMC
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
-
- # Integrated Sensor
register "IshEnable" = "0"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
- # Enable deep Sx states
- register "deep_s3_enable" = "0"
- register "deep_s5_enable" = "1"
+ # Enable Root port 1 and 5.
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[0]" = "1"
+ register "PcieRpClkReqNumber[4]" = "2"
- # CPU Thermal participant device
- register "Device4Enable" = "1"
+ register "PortUsb20Enable[0]" = "1" # Type-C Port 1
+ register "PortUsb20Enable[1]" = "1" # Type-C Port 2
+ register "PortUsb20Enable[2]" = "1" # Bluetooth
+ register "PortUsb20Enable[4]" = "1" # Type-A Port (card)
+ register "PortUsb20Enable[6]" = "1" # Camera
+ register "PortUsb20Enable[8]" = "1" # Type-A Port (board)
- # XDCI controller
- register "XdciEnable" = "0"
+ register "PortUsb30Enable[0]" = "1" # Type-C Port 1
+ register "PortUsb30Enable[1]" = "1" # Type-C Port 2
+ register "PortUsb30Enable[2]" = "1" # Type-A Port (card)
+ register "PortUsb30Enable[3]" = "1" # Type-A Port (board)
- device cpu_cluster 0 on
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoPci, \
+ }"
+
+ device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
- # Refered from SKL EDS Vol 1 : Page No: 31-32
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
- device pci 14.0 on end # USB 3.0 xHCI Controller
- device pci 14.1 off end # USB Device Controller (OTG)
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
- device pci 15.0 on end # I2C Controller #0
- device pci 15.1 on end # I2C Controller #1
- device pci 15.2 on end # I2C Controller #2
- device pci 15.3 on end # I2C Controller #3
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE Redirection (IDE-R)
- device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection
- device pci 16.4 off end # Management Engine Intel MEI #3
- device pci 17.0 off end # SATA Controller
- device pci 19.0 on end # UART Controller #2
- device pci 19.1 on end # I2C Controller #5
- device pci 19.2 on end # I2C Controller #4
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on end # I2C #4
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
@@ -140,20 +112,24 @@ chip soc/intel/skylake
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
- device pci 1e.1 on end # UART #1
- device pci 1e.2 on end # SPI #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard
device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC Interface
device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
- device pci 1f.4 on end # SMBus Controller
- device pci 1f.5 on end # SPI
- device pci 1f.6 off end # GbE Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
end
end
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