[coreboot-gerrit] New patch to review for coreboot: glados: Enable DPTF

Patrick Georgi (pgeorgi@google.com) gerrit at coreboot.org
Mon Sep 7 18:43:16 CET 2015


Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11569

-gerrit

commit 30bc8ba1e06166c6beb07d513f973b9738b20add
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:22:49 2015 -0700

    glados: Enable DPTF
    
    - Add ACPI code for DPTF support with placeholder thresholds
    - Do not have custom PDL for mainboard
    - Do not have enable charger control for DPTF as there is
    already a complicated charge profile in the EC.  We may still
    want to enable this but it would need to be tuned to work
    well with the EC profile.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a
    Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297745
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi/dptf.asl | 91 +++++++++++++++++++++++++++++++
 src/mainboard/google/glados/devicetree.cb |  3 +
 src/mainboard/google/glados/dsdt.asl      |  3 +
 3 files changed, 97 insertions(+)

diff --git a/src/mainboard/google/glados/acpi/dptf.asl b/src/mainboard/google/glados/acpi/dptf.asl
new file mode 100644
index 0000000..77578f6
--- /dev/null
+++ b/src/mainboard/google/glados/acpi/dptf.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#define DPTF_CPU_PASSIVE        80
+#define DPTF_CPU_CRITICAL       90
+#define DPTF_CPU_ACTIVE_AC0     90
+#define DPTF_CPU_ACTIVE_AC1     80
+#define DPTF_CPU_ACTIVE_AC2     70
+#define DPTF_CPU_ACTIVE_AC3     60
+#define DPTF_CPU_ACTIVE_AC4     50
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"Ambient"
+#define DPTF_TSR0_PASSIVE	55
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"Charger"
+#define DPTF_TSR1_PASSIVE	55
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"DRAM"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_TSR3_SENSOR_ID	4
+#define DPTF_TSR3_SENSOR_NAME	"WiFi"
+#define DPTF_TSR3_PASSIVE	55
+#define DPTF_TSR3_CRITICAL	70
+
+/* SKL-Y EC already has a custom charge profile based on temperature. */
+#undef DPTF_ENABLE_CHARGER
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 3 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		6000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 1d2f8bf..60966c7 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -16,6 +16,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
 	# FSP Configuration
 	register "ProbelessTrace" = "0"
 	register "EnableLan" = "0"
diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl
index 6ac0be4..ba1b263 100644
--- a/src/mainboard/google/glados/dsdt.asl
+++ b/src/mainboard/google/glados/dsdt.asl
@@ -43,6 +43,9 @@ DefinitionBlock(
 			#include <soc/intel/skylake/acpi/systemagent.asl>
 			#include <soc/intel/skylake/acpi/pch.asl>
 		}
+
+		// Dynamic Platform Thermal Framework
+		#include "acpi/dptf.asl"
 	}
 
 	// Chrome OS specific



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