[coreboot-gerrit] Patch set updated for coreboot: x86: bootblock: remove linking and program flow from build system
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Tue Sep 8 04:13:16 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495
-gerrit
commit 2b050b4d3b241484505c8430a71a26d8a32e15c5
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Sep 3 00:41:29 2015 -0500
x86: bootblock: remove linking and program flow from build system
The build system was previously determining the flow
and linking scripts bootblock code by the order of files
added to the bootblock_inc bootblock-y variables.Those
files were then concatenated together and built by a myriad of
make rules.
Now bootblock.S and bootblock.ld is added so that bootblock
can be built and linked using the default build rules.
CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the
chipset code to place include files in the path of the bootblock
program -- a replacement for the chipset_bootblock_inc
make variable.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built vortex, rambi, and some asus boards.
Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/arch/x86/Makefile.inc | 54 +++++++-------------------
src/arch/x86/bootblock.S | 51 ++++++++++++++++++++++++
src/arch/x86/bootblock.ld | 29 ++++++++++++++
src/arch/x86/id.inc | 2 +
src/cpu/dmp/vortex86ex/Kconfig | 4 ++
src/cpu/dmp/vortex86ex/Makefile.inc | 2 -
src/cpu/dmp/vortex86ex/biosdata.inc | 2 +-
src/cpu/dmp/vortex86ex/chipset_bootblock.inc | 2 +
src/northbridge/via/vx800/Kconfig | 8 ++++
src/northbridge/via/vx800/Makefile.inc | 1 -
src/northbridge/via/vx900/Kconfig | 4 ++
src/northbridge/via/vx900/Makefile.inc | 1 -
src/soc/intel/baytrail/Kconfig | 4 ++
src/soc/intel/baytrail/Makefile.inc | 1 -
src/soc/intel/baytrail/bootblock/Makefile.inc | 1 -
src/soc/intel/braswell/Kconfig | 4 ++
src/soc/intel/braswell/Makefile.inc | 1 -
src/soc/intel/braswell/bootblock/Makefile.inc | 1 -
src/soc/intel/broadwell/Kconfig | 4 ++
src/soc/intel/broadwell/Makefile.inc | 1 -
src/soc/intel/broadwell/bootblock/Makefile.inc | 1 -
src/soc/intel/skylake/Kconfig | 4 ++
src/soc/intel/skylake/Makefile.inc | 1 -
src/soc/intel/skylake/bootblock/Makefile.inc | 1 -
src/southbridge/nvidia/ck804/Kconfig | 5 +++
src/southbridge/nvidia/ck804/Makefile.inc | 1 -
src/southbridge/nvidia/mcp55/Kconfig | 4 ++
src/southbridge/nvidia/mcp55/Makefile.inc | 1 -
src/southbridge/sis/sis966/Kconfig | 12 +++++-
src/southbridge/sis/sis966/Makefile.inc | 1 -
src/southbridge/via/k8t890/Kconfig | 4 ++
src/southbridge/via/k8t890/Makefile.inc | 1 -
32 files changed, 155 insertions(+), 58 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index a9d708d..b0546f5 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
-bootblock-srcs += $(src)/arch/x86/failover.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
-bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
-bootblock-srcs += $(src)/arch/x86/id.ld
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
-endif
-
-# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
-bootblock_inc = $(src)/arch/x86/prologue.inc
-bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
-bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
-bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
-bootblock_inc += $(src)/arch/x86/id.inc
-ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_inc += $(src)/cpu/intel/fit/fit.inc
-endif
-bootblock_inc += $(chipset_bootblock_inc)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock.S
+$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
-ifeq ($(CONFIG_SSE),y)
-bootblock_inc += $(src)/cpu/x86/sse_enable.inc
-endif
-bootblock_inc += $(objgenerated)/bootblock.inc
-bootblock_inc += $(src)/arch/x86/walkcbfs.S
+bootblock-y += bootblock.ld
+$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
ifeq ($(CONFIG_SSE),y)
bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
endif
-$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
+# This is a hack in case there are no per chipset linker files.
+$(objgenerated)/empty:
+ touch $@
+
+$(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock.ld, $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
@printf " GEN $(subst $(obj)/,,$(@))\n"
cat $^ >> $@.tmp
mv $@.tmp $@
-$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
- @printf " GEN $(subst $(obj)/,,$(@))\n"
- printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
-
-$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
- @printf " CC $(subst $(obj)/,,$(@))\n"
- $(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $< > $(basename $@).disasm
-
-$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
- @printf " CC $(subst $(obj)/,,$(@))\n"
- $(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-
$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
@printf " ROMCC $(subst $(obj)/,,$(@))\n"
$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
$< > $(objgenerated)/bootblock.inc.d
$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
-$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
- $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+ $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
else
- $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
+ $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
endif
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
new file mode 100644
index 0000000..7276c7a
--- /dev/null
+++ b/src/arch/x86/bootblock.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <arch/x86/id.inc>
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.inc>
+#endif
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generated by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions at the beginning of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
+
+#include <arch/x86/walkcbfs.S>
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
new file mode 100644
index 0000000..6835430
--- /dev/null
+++ b/src/arch/x86/bootblock.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/x86/failover.ld>
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
+
+/* Include generated .ld files. */
+#include <generated/bootblock.ld>
diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc
index f8aba0b..a3df25e 100644
--- a/src/arch/x86/id.inc
+++ b/src/arch/x86/id.inc
@@ -1,3 +1,5 @@
+#include <build.h>
+
.section ".id", "a", @progbits
.globl __id_start
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 2c893ac..3bd6c2c 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -77,4 +77,8 @@ config PLL_500_375_33
endchoice
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
+
endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index 7924ca4..15ea4ea 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
-chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
bootblock-y += biosdata.ld
bootblock-y += biosdata_ex.ld
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
index 5e6a70f..4f408b4 100644
--- a/src/cpu/dmp/vortex86ex/biosdata.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -37,7 +37,7 @@
.section ".dmp_kbd_fw_part1", "a", @progbits
- #include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+ #include "dmp_kbd_fw_part1.inc"
.previous
diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
new file mode 100644
index 0000000..bdcda1d
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc
@@ -0,0 +1,2 @@
+#include "biosdata.inc"
+#include "biosdata_ex.inc"
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 9eb84fb..d7d5349 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
select LATE_CBMEM_INIT
+
+if NORTHBRIDGE_VIA_VX800
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "northbridge/via/vx800/romstrap.inc"
+
+endif
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 90ab0af..d3c4c7b 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -25,7 +25,6 @@ ramstage-y += vga.c
ramstage-y += lpc.c
ramstage-y += ide.c
-chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
bootblock-y += romstrap.ld
endif
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 617074f..335c265 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -42,4 +42,8 @@ config VGA_BIOS_ID
string
default "1106,7122"
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "northbridge/via/vx900/romstrap.inc"
+
endif
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 6178c11..e761f90 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -46,7 +46,6 @@ ramstage-y += lpc.c
ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
-chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
bootblock-y += romstrap.ld
endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5754c15..921f568 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
endif # HAVE_REFCODE_BLOB
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "soc/intel/baytrail/bootblock/timestamp.inc"
+
endif
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 7417526..e8c5022 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
-subdirs-y += bootblock
subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
deleted file mode 100644
index 3a40251..0000000
--- a/src/soc/intel/baytrail/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4c9c8aa..ab99a08 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -198,4 +198,8 @@ config ME_BIN_PATH
depends on HAVE_ME_BIN
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "soc/intel/braswell/bootblock/timestamp.inc"
+
endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 9bf6cb2..755c15a 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
-subdirs-y += bootblock
subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
deleted file mode 100644
index 17d1ee8..0000000
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 30c0093..c2db2a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
If unsure, say N.
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "soc/intel/broadwell/bootblock/timestamp.inc"
+
endif
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4b14ff8..ca295fc 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
-subdirs-y += bootblock
subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
deleted file mode 100644
index 2ca5a45..0000000
--- a/src/soc/intel/broadwell/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d53e67e..843cb8a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,4 +200,8 @@ config UART_DEBUG
select DRIVERS_UART_8250MEM
select DRIVERS_UART_8250MEM_32
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "soc/intel/skylake/bootblock/timestamp.inc"
+
endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index defb945..2e119a1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
-subdirs-y += bootblock
subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
deleted file mode 100644
index a31f588..0000000
--- a/src/soc/intel/skylake/bootblock/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 4126355..42dce07 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -41,4 +41,9 @@ config CK804_NUM
config HPET_MIN_TICKS
hex
default 0xfa
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "southbridge/nvidia/ck804/romstrap.inc"
+
endif
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index de1162a..69dd4b2 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_smbus.c
-chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
bootblock-y += romstrap.ld
endif
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 89aa452..666d3f8 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
int
default 4
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "southbridge/nvidia/mcp55/romstrap.inc"
+
endif
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index fb9c3fb..74ef14c 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
endif
-chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
bootblock-y += romstrap.ld
endif
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 390589c..20f3bff 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
select HAVE_USBDEBUG
select HAVE_HARD_RESET
+if SOUTHBRIDGE_SIS_SIS966
+
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
- default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+ default "southbridge/sis/sis966/bootblock.c"
config EHCI_BAR
hex
- default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+ default 0xfef00000
+
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "southbridge/sis/sis966/romstrap.inc"
+
+endif
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 71fff02..e703e1f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -15,7 +15,6 @@ ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
-chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
bootblock-y += romstrap.ld
endif
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index f6e51dc..76be0c1 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -51,4 +51,8 @@ config VIDEO_MB
default -1 if K8M890_VIDEO_MB_CMOS
depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "southbridge/via/k8t890/romstrap.inc"
+
endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 18cb5aa..2789499 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
ramstage-y += error.c
ramstage-y += chrome.c
-chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
bootblock-y += romstrap.ld
endif
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