[coreboot-gerrit] Patch merged into coreboot/master: skylake: ACPI: Clean up and fix XHCI ACPI Device

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e32da955b3a4e9674c6c5012e895c79c2696032e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Aug 27 17:09:02 2015 -0700

    skylake: ACPI: Clean up and fix XHCI ACPI Device
    
    - Remove the old workarounds for XHCI from broadwell
    - Add PMC device to expose bits needed for XHCI workarounds
    - Implement the new workarounds for XHCI, the first will set
    a bit in the XHCI MMIO and the second will send a message
    to the PMC if a bit is set indicating the workaround is available.
    - Clean up the HS/SS port defines and remove unnecessary
    methods to determine the port count since we only support SPT-LP.
    
    BUG=chrome-os-partner:44622,chrome-os-partner:44518
    BRANCH=none
    TEST=build and boot on glados, verify that D0 and D3 can be
    made to work (by disabling unused USB and the misbehaving camera)
    
    Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88
    Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295950
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11537
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11537 for details.

-gerrit