[coreboot-gerrit] New patch to review for coreboot: fsp1_1: provide binding to UEFI version
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Sep 9 22:26:41 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11606
-gerrit
commit 359c7aa79514aebf972f8fdd07bfe312d4cc0de1
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Sep 9 17:05:06 2015 -0500
fsp1_1: provide binding to UEFI version
FSP has some unique attributes which makes integration
cumbersome:
1. FSP header files do not include the types they need. Like
EDKII development it's expected types are provided by the
build system. Therefore, one needs to include the proper
files to avoid compilation issues.
2. An implementation of FSP for a chipset may use different
versions of the UEFI PI spec implementation. EDKII is a
proxy for all of UEFI specifications. In order to provide
flexibility one needs to binding a set of types and
structures from an UEFI PI implementation.
3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
file which defines it's own types. Commonality between
FSP chipset implementations are only named typedef
structs. The fields within are not consistent. And
because of FSP's insistence on typedefs it makes it
near impossible to forward declare structs.
The above 3 means one needs to include the correct UEFI
type bindings when working with FSP. The current
implementation had the SoC picking include paths in the
edk2 directory and using a bare <uefi_types.h> include.
Also, with the prior fsp_util.h implementation the SoC's
FSP FspUpdVpd.h header file was required since for providing
all the types at once (Generic FSP 1.1 and SoC types).
The binding has been changed in the following manner:
1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
selects. No other bindings are currently available,
but this provides the policy.
2. Based on CONFIG_UEFI_2_4_BINDING the proper include
paths are added to the CPPFLAGS_common.
3. SoC Makefile.inc does not bind UEFI types nor does
it adjust CPPFLAGS_common in any way.
4. Provide a include/fsp directory under fsp1_1 and
expose src/drivers/intel/fsp1_1/include in the
include path. This split can allow a version 2,
for example, FSP to provide its own include files.
Yes, that means there needs to be consistency in
APIs, however that's not this patch.
5. Provide a way for code to differentiate the FSP spec
types (fsp/api.h) from the chipset FSP types
(fsp/soc_binding.h). This allows for code re-use that
doesn't need the chipset types to be defined such as
the FSP relocation code.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted on glados.
Signed-off-by: Aaron Durbin <adubin at chromium.org>
Change-Id: I894165942cfe36936e186af5221efa810be8bb29
---
src/drivers/intel/fsp1_1/Kconfig | 1 +
src/drivers/intel/fsp1_1/Makefile.inc | 4 +-
src/drivers/intel/fsp1_1/fsp_gop.c | 2 +-
src/drivers/intel/fsp1_1/fsp_gop.h | 33 -------
src/drivers/intel/fsp1_1/fsp_relocate.c | 3 +-
src/drivers/intel/fsp1_1/fsp_util.c | 2 +-
src/drivers/intel/fsp1_1/fsp_util.h | 104 ---------------------
src/drivers/intel/fsp1_1/hob.c | 2 +-
src/drivers/intel/fsp1_1/include/fsp/api.h | 41 ++++++++
src/drivers/intel/fsp1_1/include/fsp/gop.h | 33 +++++++
src/drivers/intel/fsp1_1/include/fsp/soc_binding.h | 43 +++++++++
.../intel/fsp1_1/include/fsp/uefi_binding.h | 39 ++++++++
src/drivers/intel/fsp1_1/include/fsp/util.h | 96 +++++++++++++++++++
src/soc/intel/braswell/Makefile.inc | 8 --
src/soc/intel/braswell/acpi.c | 2 +-
src/soc/intel/braswell/chip.c | 2 +-
src/soc/intel/braswell/chip.h | 2 +-
.../intel/braswell/include/soc/chipset_fsp_util.h | 41 --------
src/soc/intel/braswell/include/soc/romstage.h | 2 +-
src/soc/intel/braswell/northcluster.c | 2 +-
src/soc/intel/braswell/ramstage.c | 2 +-
src/soc/intel/braswell/romstage/romstage.c | 2 +-
src/soc/intel/common/fsp_ramstage.c | 2 +-
src/soc/intel/common/raminit.c | 2 +-
src/soc/intel/common/ramstage.h | 2 +-
src/soc/intel/common/romstage.h | 2 +-
src/soc/intel/common/vbt.c | 2 +-
src/soc/intel/skylake/Makefile.inc | 9 +-
src/soc/intel/skylake/chip.c | 2 +-
.../intel/skylake/include/soc/chipset_fsp_util.h | 41 --------
src/soc/intel/skylake/ramstage.c | 3 -
src/vendorcode/intel/Kconfig | 3 +
src/vendorcode/intel/Makefile.inc | 10 ++
src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h | 18 ++--
34 files changed, 296 insertions(+), 266 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 2ffa323..d23d966 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -19,6 +19,7 @@
config PLATFORM_USES_FSP1_1
bool
+ select UEFI_2_4_BINDING
help
Does the code require the Intel Firmware Support Package?
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index f831f9d..bab68e1 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -26,7 +26,9 @@ ramstage-y += fsp_relocate.c
ramstage-y += fsp_util.c
ramstage-y += hob.c
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
+# Where FspUpdVpd.h can be picked up from.
+CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c
index ed1f1b4..c5b515c 100644
--- a/src/drivers/intel/fsp1_1/fsp_gop.c
+++ b/src/drivers/intel/fsp1_1/fsp_gop.c
@@ -19,7 +19,7 @@
#include <cbfs.h>
#include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
#include <lib.h>
/* Reading VBT table from flash */
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.h b/src/drivers/intel/fsp1_1/fsp_gop.h
deleted file mode 100644
index 2999369..0000000
--- a/src/drivers/intel/fsp1_1/fsp_gop.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _FSP_GOP_H_
-#define _FSP_GOP_H_
-
-/* GOP support */
-#if IS_ENABLED(CONFIG_GOP_SUPPORT)
-
-#include <boot/coreboot_tables.h>
-#include <soc/intel/common/gma.h>
-
-const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
-void fsp_gop_framebuffer(struct lb_header *header);
-
-#endif /* CONFIG_GOP_SUPPORT */
-#endif /* _FSP_GOP_H_ */
diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
index 3e52608..2cc2560 100644
--- a/src/drivers/intel/fsp1_1/fsp_relocate.c
+++ b/src/drivers/intel/fsp1_1/fsp_relocate.c
@@ -19,11 +19,10 @@
#include <console/console.h>
#include <cbmem.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
-#include <uefi_types.h>
#define FSP_DBG_LVL BIOS_NEVER
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 1d67e78..455c736 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -21,7 +21,7 @@
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
#include <timestamp.h>
/* Locate the FSP binary in the coreboot filesystem */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h
deleted file mode 100644
index 8f6f77a..0000000
--- a/src/drivers/intel/fsp1_1/fsp_util.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef FSP_UTIL_H
-#define FSP_UTIL_H
-
-#include <types.h>
-#include <arch/cpu.h>
-#include <fsp_gop.h>
-#include <program_loading.h>
-#include <region.h>
-
-/*
- * The following are functions with prototypes defined in the EDK2 headers. The
- * EDK2 headers are included with chipset_fsp_util.h. Define the following
- * names to reduce the use of CamelCase in the other source files.
- */
-#define GetHobList get_hob_list
-#define GetNextHob get_next_hob
-#define GetFirstHob get_first_hob
-#define GetNextGuidHob get_next_guid_hob
-#define GetFirstGuidHob get_first_guid_hob
-
-/* Include the EDK2 headers */
-#include <soc/chipset_fsp_util.h>
-
-/* find_fsp() should only be called from assembly code. */
-FSP_INFO_HEADER *find_fsp(void);
-/* Set FSP's runtime information. */
-void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
-/* Use a new FSP_INFO_HEADER at runtime. */
-void fsp_update_fih(FSP_INFO_HEADER *fih);
-/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
-FSP_INFO_HEADER *fsp_get_fih(void);
-/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
-void *fsp_get_hob_list(void);
-void fsp_early_init(FSP_INFO_HEADER *fsp_info);
-void fsp_notify(u32 phase);
-void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
-void print_fsp_info(FSP_INFO_HEADER *fsp_header);
-void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
- const void *hob_start);
-void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
-void *get_first_resource_hob(const EFI_GUID *guid);
-/*
- * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
- * The FSP source is pointed to by region_device and the relocation information
- * is encoded in a struct prog with its entry point set to the FSP info header.
- */
-int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
-
-/* Additional HOB types not included in the FSP:
- * #define EFI_HOB_TYPE_HANDOFF 0x0001
- * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
- * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
- * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
- * #define EFI_HOB_TYPE_FV 0x0005
- * #define EFI_HOB_TYPE_CPU 0x0006
- * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
- * #define EFI_HOB_TYPE_CV 0x0008
- * #define EFI_HOB_TYPE_UNUSED 0xFFFE
- * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
- */
-#define EFI_HOB_TYPE_HANDOFF 0x0001
-#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
-
-/* The offset in bytes from the start of the info structure */
-#define FSP_IMAGE_SIG_LOC 0
-#define FSP_IMAGE_ID_LOC 16
-#define FSP_IMAGE_BASE_LOC 28
-#define FSP_IMAGE_ATTRIBUTE_LOC 32
-#define GRAPHICS_SUPPORT_BIT (1 << 0)
-
-#define FSP_SIG 0x48505346 /* 'FSPH' */
-
-#define ERROR_NO_FV_SIG 1
-#define ERROR_NO_FFS_GUID 2
-#define ERROR_NO_INFO_HEADER 3
-#define ERROR_IMAGEBASE_MISMATCH 4
-#define ERROR_INFO_HEAD_SIG_MISMATCH 5
-#define ERROR_FSP_SIG_MISMATCH 6
-
-#if ENV_RAMSTAGE
-extern void *FspHobListPtr;
-#endif
-
-#endif /* FSP_UTIL_H */
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
index 05044cb..467d4af 100644
--- a/src/drivers/intel/fsp1_1/hob.c
+++ b/src/drivers/intel/fsp1_1/hob.c
@@ -23,7 +23,7 @@
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
#include <ip_checksum.h>
#include <lib.h> // hexdump
#include <string.h>
diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h
new file mode 100644
index 0000000..414532c
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/api.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_API_H_
+#define _FSP1_1_API_H_
+
+#define FSP_SIG 0x48505346 /* 'FSPH' */
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h>
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h
new file mode 100644
index 0000000..14bada6
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_GOP_H_
+#define _FSP1_1_GOP_H_
+
+/* GOP support */
+#if IS_ENABLED(CONFIG_GOP_SUPPORT)
+
+#include <boot/coreboot_tables.h>
+#include <soc/intel/common/gma.h>
+
+const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
+void fsp_gop_framebuffer(struct lb_header *header);
+
+#endif /* CONFIG_GOP_SUPPORT */
+#endif /* _FSP_GOP_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
new file mode 100644
index 0000000..1625040
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_SOC_BINDING_H_
+#define _FSP1_1_SOC_BINDING_H_
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * This file is found by way of the Kconfig FSP_INCLUDE_PATH option. It is
+ * a per implementation specific header. i.e. different FSP implementations
+ * for different chipsets.
+ */
+#include <FspUpdVpd.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
new file mode 100644
index 0000000..73a8a4a
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_UEFI_BINDING_H_
+#define _FSP1_1_UEFI_BINDING_H_
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * Pull in the UEFI types from 2.4. Smarter decisions can be made on what
+ * version to bind to, but for now 2.4 is standard for FSP 1.1.
+ */
+#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
new file mode 100644
index 0000000..8e61ae8
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef FSP1_1_UTIL_H
+#define FSP1_1_UTIL_H
+
+#include <fsp/api.h>
+/* Current users expect to get the SoC's FSP definitions by including util.h. */
+#include <fsp/soc_binding.h>
+#include <fsp/gop.h>
+#include <program_loading.h>
+#include <region.h>
+
+/* find_fsp() should only be called from assembly code. */
+FSP_INFO_HEADER *find_fsp(void);
+/* Set FSP's runtime information. */
+void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
+/* Use a new FSP_INFO_HEADER at runtime. */
+void fsp_update_fih(FSP_INFO_HEADER *fih);
+/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
+FSP_INFO_HEADER *fsp_get_fih(void);
+/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
+void *fsp_get_hob_list(void);
+void fsp_early_init(FSP_INFO_HEADER *fsp_info);
+void fsp_notify(u32 phase);
+void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
+void print_fsp_info(FSP_INFO_HEADER *fsp_header);
+void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
+ const void *hob_start);
+void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
+void *get_first_resource_hob(const EFI_GUID *guid);
+/*
+ * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
+ * The FSP source is pointed to by region_device and the relocation information
+ * is encoded in a struct prog with its entry point set to the FSP info header.
+ */
+int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
+
+/* Additional HOB types not included in the FSP:
+ * #define EFI_HOB_TYPE_HANDOFF 0x0001
+ * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
+ * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
+ * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
+ * #define EFI_HOB_TYPE_FV 0x0005
+ * #define EFI_HOB_TYPE_CPU 0x0006
+ * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+ * #define EFI_HOB_TYPE_CV 0x0008
+ * #define EFI_HOB_TYPE_UNUSED 0xFFFE
+ * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff
+ */
+#define EFI_HOB_TYPE_HANDOFF 0x0001
+#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+
+/* The offset in bytes from the start of the info structure */
+#define FSP_IMAGE_SIG_LOC 0
+#define FSP_IMAGE_ID_LOC 16
+#define FSP_IMAGE_BASE_LOC 28
+#define FSP_IMAGE_ATTRIBUTE_LOC 32
+#define GRAPHICS_SUPPORT_BIT (1 << 0)
+
+#define ERROR_NO_FV_SIG 1
+#define ERROR_NO_FFS_GUID 2
+#define ERROR_NO_INFO_HEADER 3
+#define ERROR_IMAGEBASE_MISMATCH 4
+#define ERROR_INFO_HEAD_SIG_MISMATCH 5
+#define ERROR_FSP_SIG_MISMATCH 6
+
+#if ENV_RAMSTAGE
+extern void *FspHobListPtr;
+#endif
+
+/* TODO: Remove the EFI types and decorations from coreboot implementations. */
+VOID * EFIAPI get_hob_list(VOID);
+VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
+VOID * EFIAPI get_first_hob(UINT16 type);
+VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
+VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
+
+#endif /* FSP1_1_UTIL_H */
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 755c15a..fae97b8 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -51,19 +51,11 @@ smm-y += smihandler.c
smm-y += spi.c
smm-y += tsc_freq.c
-CPPFLAGS_common += -I$(src)/arch/x86/include/
CPPFLAGS_common += -I$(src)/soc/intel/braswell/
CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index e1065e2..b8be3c6 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -35,7 +35,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <ec/google/chromeec/ec.h>
-#include <fsp_gop.h>
+#include <fsp/gop.h>
#include <rules.h>
#include <soc/acpi.h>
#include <soc/gfx.h>
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index c986507..6f22740 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -22,7 +22,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 191fc01..ff68014 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -27,7 +27,7 @@
#define _SOC_CHIP_H_
#include <stdint.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/pci_devs.h>
#define SVID_CONFIG1 1
diff --git a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
deleted file mode 100644
index c269a61..0000000
--- a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef CHIPSET_FSP_UTIL_H
-#define CHIPSET_FSP_UTIL_H
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h> /* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h> /* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h> /* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h> /* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h> /* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h> /* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h> /* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h> /* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h> /* HOB routine declarations */
-#include <FspUpdVpd.h> /* Vital/updatable product data definitions */
-
-#endif /* CHIPSET_FSP_UTIL_H */
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 770a39d..a735c04 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <arch/cpu.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/pei_data.h>
#include <soc/pm.h>
#include <soc/intel/common/romstage.h>
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 7821a2a..390e050 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -25,7 +25,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/intel/common/memmap.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 3e1e02f..26c23bc 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -29,7 +29,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <romstage_handoff.h>
#include <soc/gpio.h>
#include <soc/lpc.h>
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 1dbff54..2286cd4 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -40,7 +40,7 @@
#include <timestamp.h>
#include <reset.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index 41c0b1c..d1f2e49 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -22,7 +22,7 @@
#include <cbmem.h>
#include <cbfs.h>
#include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <lib.h>
#include <soc/intel/common/memmap.h>
#include <soc/intel/common/ramstage.h>
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
index ddf5675..bdb23e2 100644
--- a/src/soc/intel/common/raminit.c
+++ b/src/soc/intel/common/raminit.c
@@ -19,7 +19,7 @@
#include <cbmem.h>
#include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <lib.h> /* hexdump */
#include <reset.h>
#include <soc/intel/common/memmap.h>
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h
index 414142a..d6cb895 100644
--- a/src/soc/intel/common/ramstage.h
+++ b/src/soc/intel/common/ramstage.h
@@ -21,7 +21,7 @@
#ifndef _INTEL_COMMON_RAMSTAGE_H_
#define _INTEL_COMMON_RAMSTAGE_H_
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <stdint.h>
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index 440cad7..b35ff66 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -24,7 +24,7 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <memory_info.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <soc/pei_data.h>
#include <soc/pm.h> /* chip_power_state */
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index 0e46b70..b12ec04 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -20,7 +20,7 @@
#include <cbfs.h>
#include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <lib.h>
#include <soc/intel/common/ramstage.h>
#include <string.h>
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 32ecb5d..38668da 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -61,19 +61,12 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
smm-y += tsc_freq.c
smm-$(CONFIG_UART_DEBUG) += uart_debug.c
-CPPFLAGS_common += -I$(src)/arch/x86/include/
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
+# Currently used for microcode path.
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 2c49883..afb0ff6 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -23,7 +23,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
diff --git a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h b/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
deleted file mode 100644
index 2c05f01..0000000
--- a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CHIPSET_FSP_UTIL_H_
-#define _CHIPSET_FSP_UTIL_H_
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h> /* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h> /* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h> /* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h> /* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h> /* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h> /* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h> /* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h> /* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h> /* HOB routine declarations */
-#include <FspUpdVpd.h> /* Vital/updatable product data definitions */
-
-#endif /* _CHIPSET_FSP_UTIL_H_ */
diff --git a/src/soc/intel/skylake/ramstage.c b/src/soc/intel/skylake/ramstage.c
index 51e9b31..3646843 100644
--- a/src/soc/intel/skylake/ramstage.c
+++ b/src/soc/intel/skylake/ramstage.c
@@ -18,9 +18,6 @@
* Foundation, Inc.
*/
-#include <bootstate.h>
-#include <console/console.h>
-#include <fsp_util.h>
#include <soc/ramstage.h>
#include <soc/intel/common/ramstage.h>
diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig
index 0da26f0..754c487 100644
--- a/src/vendorcode/intel/Kconfig
+++ b/src/vendorcode/intel/Kconfig
@@ -22,3 +22,6 @@ config FSP_VENDORCODE_HEADER_PATH
default "fsp1_0/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL
default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX
+
+config UEFI_2_4_BINDING
+ def_bool n
diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc
index 2cb486b..b95d4f9 100644
--- a/src/vendorcode/intel/Makefile.inc
+++ b/src/vendorcode/intel/Makefile.inc
@@ -25,3 +25,13 @@ ramstage-y += $(FSP_C_INPUTS)
CFLAGS_x86_32 += -Isrc/vendorcode/intel/$(FSP_PATH)/include
endif
+
+ifeq ($(CONFIG_UEFI_2_4_BINDING),y)
+# ProccessorBind.h provided in Ia32 directory. Types are derived from ia32.
+# It's possible to provide our own ProcessorBind.h using posix types. However,
+# ProcessorBind.h isn't just about types. There's compiler definitions as well
+# as ABI enforcement. Luckily long is not used in Ia32/ProcessorBind.h for
+# a fixed width type.
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+endif
diff --git a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
index e17361e..e68f8c9 100644
--- a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
+++ b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
@@ -37,15 +37,15 @@ are permitted provided that the following conditions are met:
#define __APPLE__ 0
#include <stdlib.h>
#include <Uefi/UefiBaseType.h>
-#include <MdePkg/Include/Pi/PiBootMode.h>
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>
-#include <MdePkg/Include/Pi/PiHob.h>
-#include <MdePkg/Include/Protocol/GraphicsOutput.h>
-#include <MdePkg/Include/Library/HobLib.h>
-#include <MdePkg/Include/Guid/FirmwareFileSystem2.h>
-#include <MdePkg/Include/IndustryStandard/PeImage.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiFirmwareVolume.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiHob.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Library/HobLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <IndustryStandard/PeImage.h>
///
/// For GNU assembly code, .global or .globl can declare global symbols.
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