[coreboot-gerrit] New patch to review for coreboot: WIP: cpu: microcode: Use microcode stored in binary format
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Thu Sep 10 05:51:29 CET 2015
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607
-gerrit
commit 2dc8f5d6402c1af1dbd907f734b7160a6f2aced3
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Wed Sep 9 22:38:06 2015 -0700
WIP: cpu: microcode: Use microcode stored in binary format
Using a copiler to compile something that's already a binary is pretty
stupid. Now that Stefan made converted most microcode in blobs to
binary, use the binary version. Save the poor compiler the wild goose
hunt.
Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/cpu/Makefile.inc | 23 ++++++++++-------------
src/cpu/intel/model_1067x/Makefile.inc | 2 +-
src/cpu/intel/model_1067x/microcode_blob.c | 3 ---
src/cpu/intel/model_106cx/Makefile.inc | 2 +-
src/cpu/intel/model_106cx/microcode_blob.c | 3 ---
src/cpu/intel/model_2065x/Makefile.inc | 2 +-
src/cpu/intel/model_2065x/microcode_blob.c | 22 ----------------------
src/cpu/intel/model_206ax/Makefile.inc | 3 +++
src/cpu/intel/model_206ax/microcode_blob.c | 23 -----------------------
src/cpu/intel/model_65x/Makefile.inc | 2 +-
src/cpu/intel/model_65x/microcode_blob.c | 3 ---
src/cpu/intel/model_67x/Makefile.inc | 2 +-
src/cpu/intel/model_67x/microcode_blob.c | 3 ---
src/cpu/intel/model_68x/Makefile.inc | 2 +-
src/cpu/intel/model_68x/microcode_blob.c | 3 ---
src/cpu/intel/model_69x/Makefile.inc | 2 +-
src/cpu/intel/model_69x/microcode_blob.c | 3 ---
src/cpu/intel/model_6bx/Makefile.inc | 2 +-
src/cpu/intel/model_6bx/microcode_blob.c | 3 ---
src/cpu/intel/model_6dx/Makefile.inc | 2 +-
src/cpu/intel/model_6dx/microcode_blob.c | 3 ---
src/cpu/intel/model_6ex/Makefile.inc | 2 +-
src/cpu/intel/model_6ex/microcode_blob.c | 3 ---
src/cpu/intel/model_6fx/Makefile.inc | 2 +-
src/cpu/intel/model_6fx/microcode_blob.c | 3 ---
src/cpu/intel/model_6xx/Makefile.inc | 2 +-
src/cpu/intel/model_6xx/microcode_blob.c | 3 ---
src/cpu/intel/model_f0x/Makefile.inc | 2 +-
src/cpu/intel/model_f0x/microcode_blob.c | 4 ----
src/cpu/intel/model_f1x/Makefile.inc | 2 +-
src/cpu/intel/model_f1x/microcode_blob.c | 4 ----
src/cpu/intel/model_f2x/Makefile.inc | 2 +-
src/cpu/intel/model_f2x/microcode_blob.c | 4 ----
src/cpu/intel/model_f3x/Makefile.inc | 2 +-
src/cpu/intel/model_f3x/microcode_blob.c | 3 ---
src/cpu/intel/model_f4x/Makefile.inc | 2 +-
src/cpu/intel/model_f4x/microcode_blob.c | 3 ---
src/cpu/via/nano/Makefile.inc | 4 +++-
38 files changed, 33 insertions(+), 127 deletions(-)
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
cbfs_include_ucode = y
endif
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
- @printf " LD $(subst $(obj)/,,$(@))\n"
- $(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+ @echo $(cpu_microcode_bins)
+ cat $+ > $@
cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_1067x_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..4b74ce2 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -8,4 +8,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
+
cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
- #include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..ffedcb8 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
ramstage-y += model_65x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
ramstage-y += model_67x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
ramstage-y += model_68x_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_69x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6bx_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_6dx_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6ex_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6fx_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_6xx_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f0x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f1x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f2x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f3x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f4x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..999b8fa 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -28,6 +28,8 @@ ramstage-y += update_ucode.c
# This microcode is included as a separate CBFS file. It is never linked in to
# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
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