[coreboot-gerrit] Patch set updated for coreboot: riscv-memlayout: fix existing memlayout issues, add sbi interface

Thu Sep 10 17:27:35 CET 2015

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11370

-gerrit

commit 949e74f23463c552d2533fe320ec6801a31d8a23
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Wed Aug 26 15:39:16 2015 -0700

    riscv-memlayout: fix existing memlayout issues, add sbi interface
    
    Existing memlayout code placed sections in overlapping areas, and would
    overwrite the payload if it was large enough. Update memlayout.ld in
    src/mainboard/emulation/spike-riscv to represent the spike emulator, and
    add sbi interface which now has room into src/arch/riscv/bootblock.S.
    Update Makefile to include all the files necessary for sbi interface.
    
    Clean up unused include in src/arch/riscv/include/atomic.h and
    whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld
    
    Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
---
 src/arch/riscv/Makefile.inc                      |   3 +
 src/arch/riscv/bootblock.S                       | 108 ++++++++++++++++++++---
 src/arch/riscv/include/atomic.h                  |   1 -
 src/mainboard/emulation/spike-riscv/memlayout.ld |  10 +--
 4 files changed, 102 insertions(+), 20 deletions(-)

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 6fac99c..de6eb91 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -31,6 +31,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
 bootblock-y = bootblock.S stages.c
 bootblock-y += trap_util.S
 bootblock-y += trap_handler.c
+bootblock-y += virtual_memory.c
 bootblock-y += boot.c
 bootblock-y += rom_media.c
 bootblock-y += \
@@ -85,6 +86,8 @@ endif
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 
 ramstage-y =
+ramstage-y += trap_handler.c
+ramstage-y += virtual_memory.c
 ramstage-y += rom_media.c
 ramstage-y += stages.c
 ramstage-y += misc.c
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index a26b144..4caeea6 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -1,7 +1,7 @@
 /*
  * Early initialization code for aarch64 (a.k.a. armv8)
  *
- * Copyright 2013Google Inc.
+ * Copyright 2013 Google Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -22,34 +22,112 @@
 
 .section ".text._start", "ax", %progbits
 // Maybe there's a better way.
-.space 0x200
+# machine mode handler when in supervisor mode
+.space 0x140
+supervisor_machine_handler:
+  j supervisor_trap_entry
+
+# handler for when
+.space 0x7c
+.globl machine_handler
+machine_handler:
+#  call trap_handler
+  j trap_entry
+
+.space 0x3c
 .globl _start
 _start:
 
 	// pending figuring out this f-ing toolchain. Hardcode what we know works.
-//  la sp, 0x4ef0 // .stacktop
-//  la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv
-  la sp, 0x7FF00 // stack start + stack size
+  la sp, 0x80FFF0 // stack start + stack size
 
-  // make room for HLS
+  # make room for HLS and initialize it
   addi sp, sp, -64 // MENTRY_FRAME_SIZE
-
+  csrr a0, mhartid
+  call hls_init
 
   //poison the stack
-  la t1, 0x40000
+  la t1, 0x800000
   li t0, 0xdeadbeef
   sd t0, 0(t1)
 
-//  la gp, _gp
+  la t0, exception_handler
+  csrw stvec, t0
 
   # clear any pending interrupts
-#if __GNUC__ < 5
-  csrwi clear_ipi, 0
-#else
   csrwi sip, 0
-#endif
 
+  # set up the mstatus register for VM
+  call mstatus_init
   call main
+.=0x2000
+    .space 0x800
+# sbi interface lives here
+
+# hart_id
+.align 5
+li a7, 0
+ecall
+ret
+
+# num_harts
+.align 4
+li a0, 1
+ret
+
+# query_memory
+.align 4
+li a7, 8
+ecall
+ret
+
+# console_putchar
+.align 4
+li a7, 1
+ecall
+ret
+
+# send_device_request
+.align 4
+li a7, 2
+ecall
+ret
+
+# receive_device_response
+.align 4
+li a7, 3
+ecall
+ret
+
+# send ipi
+.align 4
+li a7, 4
+ecall
+ret
+
+# clear ipi
+.align 4
+li a7, 5
+ecall
+ret
+
+# timebase
+.align 4
+li a0, 10000000 # temporary, we should provide the correct answer
+ret
+
+# shutdown
+.align 4
+li a7, 6
+ecall
+
+# set_timer
+.align 4
+li a7, 7
+ecall
+ret
+
+# end of SBI trampolines
 .=0x4000
 .stack:
 .align 8
@@ -59,7 +137,9 @@ _start:
 .align 3
 .stack_size:
 	.quad 0xf00
-
+.globl test_trap
+exception_handler:
+        call trap_handler
 reset:
 init_stack_loop:
 
diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h
index 8d7295d..f63f6e1 100644
--- a/src/arch/riscv/include/atomic.h
+++ b/src/arch/riscv/include/atomic.h
@@ -3,7 +3,6 @@
 #ifndef _RISCV_ATOMIC_H
 #define _RISCV_ATOMIC_H
 
-//#include "config.h"
 #include <arch/encoding.h>
 
 #define disable_irqsave() clear_csr(sstatus, SSTATUS_IE)
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index 8801f35..8e2e7ee 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -23,10 +23,10 @@
 
 SECTIONS
 {
-	DRAM_START(0x0)
+        DRAM_START(0x0)
 	BOOTBLOCK(0x0, 64K)
-	ROMSTAGE(0x20000, 128K)
-	STACK(0x40000, 0x3ff00)
-	PRERAM_CBMEM_CONSOLE(0x80000, 8K)
-	RAMSTAGE(0x100000, 16M)
+        STACK(8M, 64K)
+	ROMSTAGE(8M + 64K, 128K)
+	PRERAM_CBMEM_CONSOLE(8M + 192k, 8K)
+	RAMSTAGE(8M + 200K, 256K)
 }

