[coreboot-gerrit] Patch set updated for coreboot: corebot: introduce commonlib
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Tue Sep 15 14:30:39 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592
-gerrit
commit 095282d91ffcf9a56f3fc1a1f6e034f35625cf27
Author: Aaron Durbin <adurbin at chromium.org>
Date: Tue Sep 8 13:34:43 2015 -0500
corebot: introduce commonlib
Instead of reaching into src/include and re-writing code
allow for cleaner code sharing within coreboot and its
utilities. The additional thing needed at this point is
for the utilities to provide a printk() declaration within
a <console/console.h> file. That way code which uses printk()
can than be mapped properly to verbosity of utility parameters.
Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
Makefile.inc | 4 +-
src/arch/x86/include/arch/cbfs.h | 2 +-
src/arch/x86/romcc_console.c | 2 +-
src/commonlib/Makefile.inc | 10 +
src/commonlib/include/commonlib/cbfs_serialized.h | 190 ++++++++++
src/commonlib/include/commonlib/cbmem_id.h | 113 ++++++
src/commonlib/include/commonlib/coreboot_tables.h | 387 +++++++++++++++++++++
src/commonlib/include/commonlib/fmap_serialized.h | 73 ++++
src/commonlib/include/commonlib/helpers.h | 51 +++
src/commonlib/include/commonlib/loglevel.h | 178 ++++++++++
src/commonlib/include/commonlib/mem_pool.h | 73 ++++
src/commonlib/include/commonlib/region.h | 157 +++++++++
src/commonlib/include/commonlib/rmodule-defs.h | 63 ++++
.../include/commonlib/timestamp_serialized.h | 92 +++++
src/commonlib/mem_pool.c | 51 +++
src/commonlib/region.c | 196 +++++++++++
src/drivers/intel/fsp1_1/include/fsp/util.h | 2 +-
src/include/assets.h | 2 +-
src/include/boot/coreboot_tables.h | 384 +-------------------
src/include/boot_device.h | 2 +-
src/include/cbfs.h | 4 +-
src/include/cbfs_serialized.h | 190 ----------
src/include/cbmem.h | 2 +-
src/include/cbmem_id.h | 113 ------
src/include/console/console.h | 2 +-
src/include/console/early_print.h | 2 +-
src/include/console/loglevel.h | 178 ----------
src/include/fmap.h | 4 +-
src/include/fmap_serialized.h | 73 ----
src/include/mem_pool.h | 73 ----
src/include/region.h | 157 ---------
src/include/rmodule-defs.h | 63 ----
src/include/rmodule.h | 2 +-
src/include/stddef.h | 34 +-
src/include/stdlib.h | 14 -
src/include/timestamp.h | 69 +---
src/lib/Makefile.inc | 9 -
src/lib/cbfs_boot_props.c | 2 +-
src/lib/fmap.c | 2 +-
src/lib/mem_pool.c | 51 ---
src/lib/region.c | 196 -----------
src/mainboard/advansus/a785e-i/romstage.c | 2 +-
src/mainboard/amd/bimini_fam10/romstage.c | 2 +-
src/mainboard/amd/dinar/romstage.c | 2 +-
src/mainboard/amd/inagua/romstage.c | 2 +-
src/mainboard/amd/lamar/romstage.c | 2 +-
src/mainboard/amd/mahogany_fam10/romstage.c | 2 +-
src/mainboard/amd/olivehill/romstage.c | 2 +-
src/mainboard/amd/olivehillplus/romstage.c | 2 +-
src/mainboard/amd/parmer/romstage.c | 2 +-
src/mainboard/amd/persimmon/romstage.c | 2 +-
.../amd/serengeti_cheetah_fam10/romstage.c | 2 +-
src/mainboard/amd/south_station/romstage.c | 2 +-
src/mainboard/amd/thatcher/romstage.c | 2 +-
src/mainboard/amd/tilapia_fam10/romstage.c | 2 +-
src/mainboard/amd/torpedo/romstage.c | 2 +-
src/mainboard/amd/union_station/romstage.c | 2 +-
src/mainboard/asrock/e350m1/romstage.c | 2 +-
src/mainboard/asrock/imb-a180/romstage.c | 2 +-
src/mainboard/asus/m4a78-em/romstage.c | 2 +-
src/mainboard/asus/m4a785-m/romstage.c | 2 +-
src/mainboard/asus/m5a88-v/romstage.c | 2 +-
src/mainboard/avalue/eax-785e/romstage.c | 2 +-
src/mainboard/bap/ode_e20XX/romstage.c | 2 +-
src/mainboard/biostar/am1ml/romstage.c | 2 +-
src/mainboard/gigabyte/ma785gm/romstage.c | 2 +-
src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +-
src/mainboard/gigabyte/ma78gm/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo2/romstage.c | 2 +-
src/mainboard/google/peach_pit/romstage.c | 2 +-
src/mainboard/hp/abm/romstage.c | 2 +-
src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +-
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 +-
src/mainboard/jetway/pa78vm5/romstage.c | 2 +-
src/mainboard/lippert/frontrunner-af/romstage.c | 2 +-
src/mainboard/lippert/toucan-af/romstage.c | 2 +-
src/mainboard/pcengines/apu1/romstage.c | 2 +-
src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +-
src/soc/intel/broadwell/include/soc/me.h | 2 +-
src/southbridge/amd/cimx/sb700/Platform.h | 2 +-
src/southbridge/amd/cimx/sb700/early.c | 2 +-
src/southbridge/amd/cimx/sb900/early.c | 2 +-
src/vendorcode/amd/agesa/common/Porting.h | 2 +-
src/vendorcode/amd/pi/00630F01/Porting.h | 2 +-
src/vendorcode/amd/pi/00660F01/Porting.h | 2 +-
src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c | 2 +-
src/vendorcode/amd/pi/00730F01/Porting.h | 2 +-
src/vendorcode/amd/pi/Makefile.inc | 1 +
src/vendorcode/google/chromeos/vboot_common.h | 2 +-
util/cbfstool/Makefile | 1 +
util/cbfstool/Makefile.inc | 1 +
util/cbfstool/rmodule.c | 2 +-
util/cbmem/Makefile | 2 +-
util/cbmem/cbmem.c | 9 +-
95 files changed, 1711 insertions(+), 1673 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index c0bedda..34f3411 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
#######################################################################
# root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
endif
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
CPPFLAGS_common += -Isrc/device/oprom/include
CPPFLAGS_common += -include $(src)/include/kconfig.h
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
#ifndef __INCLUDE_ARCH_CBFS__
#define __INCLUDE_ARCH_CBFS__
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
#include <endian.h>
#define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
#include <build.h>
#include <console/streams.h>
#include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
/* Include the sources. */
#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ * - The GNU GPL, version 2, as published by the Free Software Foundation
+ * - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+ algorithms that coreboot knows about for stages and
+ payloads. Of course, other CBFS users can use whatever
+ values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE 0
+#define CBFS_COMPRESS_LZMA 1
+
+/** These are standard component types for well known
+ components (i.e - those that coreboot needs to consume.
+ Users are welcome to use any other value for their
+ components */
+
+#define CBFS_TYPE_STAGE 0x10
+#define CBFS_TYPE_PAYLOAD 0x20
+#define CBFS_TYPE_OPTIONROM 0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW 0x50
+#define CBFS_TYPE_VSA 0x51
+#define CBFS_TYPE_MBI 0x52
+#define CBFS_TYPE_MICROCODE 0x53
+#define CBFS_TYPE_FSP 0x60
+#define CBFS_TYPE_MRC 0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD 0xab
+#define CBFS_TYPE_MRC_CACHE 0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC 0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+ uint32_t magic;
+ uint32_t version;
+ uint32_t romsize;
+ uint32_t bootblocksize;
+ uint32_t align; /* fixed to 64 bytes */
+ uint32_t offset;
+ uint32_t architecture;
+ uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86 0x00000001
+#define CBFS_ARCHITECTURE_ARM 0x00000010
+
+/** This is a component header - every entry in the CBFS
+ will have this header.
+
+ This is how the component is arranged in the ROM:
+
+ -------------- <- 0
+ component header
+ -------------- <- sizeof(struct component)
+ component name
+ -------------- <- offset
+ data
+ ...
+ -------------- <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+ char magic[8];
+ uint32_t len;
+ uint32_t type;
+ uint32_t checksum;
+ uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+ component types */
+
+/** This is the sub-header for stage components. Stages are
+ loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+ uint32_t compression; /** Compression type */
+ uint64_t entry; /** entry point */
+ uint64_t load; /** Where to load in memory */
+ uint32_t len; /** length of data to load */
+ uint32_t memlen; /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components. Payloads
+ are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+ uint32_t type;
+ uint32_t compression;
+ uint32_t offset;
+ uint64_t load_addr;
+ uint32_t len;
+ uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+ struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE 0x45444F43
+#define PAYLOAD_SEGMENT_DATA 0x41544144
+#define PAYLOAD_SEGMENT_BSS 0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY 0x52544E45
+
+struct cbfs_optionrom {
+ uint32_t compression;
+ uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI 0x41435049
+#define CBMEM_ID_ACPI_GNVS 0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME 0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
+#define CBMEM_ID_CBTABLE 0x43425442
+#define CBMEM_ID_CONSOLE 0x434f4e53
+#define CBMEM_ID_COVERAGE 0x47434f56
+#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9
+#define CBMEM_ID_ELOG 0x454c4f47
+#define CBMEM_ID_FREESPACE 0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME 0x52505346
+#define CBMEM_ID_GDT 0x4c474454
+#define CBMEM_ID_HOB_POINTER 0x484f4221
+#define CBMEM_ID_IGD_OPREGION 0x4f444749
+#define CBMEM_ID_IMD_ROOT 0xff4017ff
+#define CBMEM_ID_IMD_SMALL 0x53a11439
+#define CBMEM_ID_MEMINFO 0x494D454D
+#define CBMEM_ID_MPTABLE 0x534d5054
+#define CBMEM_ID_MRCDATA 0x4d524344
+#define CBMEM_ID_MTC 0xcb31d31c
+#define CBMEM_ID_NONE 0x00000000
+#define CBMEM_ID_PIRQ 0x49525154
+#define CBMEM_ID_POWER_STATE 0x50535454
+#define CBMEM_ID_RAM_OOPS 0x05430095
+#define CBMEM_ID_RAMSTAGE 0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e
+#define CBMEM_ID_REFCODE 0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE 0x4efc0de5
+#define CBMEM_ID_RESUME 0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH 0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO 0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT 0xff4007ff
+#define CBMEM_ID_SMBIOS 0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
+#define CBMEM_ID_SPINTABLE 0x59175917
+#define CBMEM_ID_STAGEx_META 0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
+#define CBMEM_ID_TCPA_LOG 0x54435041
+#define CBMEM_ID_TIMESTAMP 0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF 0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE \
+ { CBMEM_ID_ACPI, "ACPI " }, \
+ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
+ { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \
+ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
+ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
+ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
+ { CBMEM_ID_CBTABLE, "COREBOOT " }, \
+ { CBMEM_ID_CONSOLE, "CONSOLE " }, \
+ { CBMEM_ID_COVERAGE, "COVERAGE " }, \
+ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \
+ { CBMEM_ID_ELOG, "ELOG " }, \
+ { CBMEM_ID_FREESPACE, "FREE SPACE " }, \
+ { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+ { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \
+ { CBMEM_ID_GDT, "GDT " }, \
+ { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \
+ { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \
+ { CBMEM_ID_MEMINFO, "MEM INFO " }, \
+ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \
+ { CBMEM_ID_MRCDATA, "MRC DATA " }, \
+ { CBMEM_ID_MTC, "MTC " }, \
+ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \
+ { CBMEM_ID_POWER_STATE, "POWER STATE" }, \
+ { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \
+ { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \
+ { CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \
+ { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \
+ { CBMEM_ID_REFCODE, "REFCODE " }, \
+ { CBMEM_ID_RESUME, "ACPI RESUME" }, \
+ { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \
+ { CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \
+ { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \
+ { CBMEM_ID_ROOT, "CBMEM ROOT " }, \
+ { CBMEM_ID_SMBIOS, "SMBIOS " }, \
+ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
+ { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \
+ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \
+ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
+ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
+ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \
+ { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image. Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing. For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed. This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ * a particular motherboard is constructed? (Assuming the kernel
+ * has drivers for all of the hardware but it does not have
+ * assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not. This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped. Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+ uint32_t lo;
+ uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+ uint64_t result;
+ result = value.hi;
+ result = (result << 32) + value.lo;
+ return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+ struct lb_uint64 result;
+ result.lo = (value >> 0) & 0xffffffff;
+ result.hi = (value >> 32) & 0xffffffff;
+ return result;
+}
+
+struct lb_header
+{
+ uint8_t signature[4]; /* LBIO */
+ uint32_t header_bytes;
+ uint32_t header_checksum;
+ uint32_t table_bytes;
+ uint32_t table_checksum;
+ uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record. Encoding both type and size. The type is obviously
+ * so you can tell what it is. The size allows you to skip that
+ * boot environment record if you don't know what it is. This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+ uint32_t tag; /* tag ID */
+ uint32_t size; /* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED 0x0000
+
+#define LB_TAG_MEMORY 0x0001
+
+struct lb_memory_range {
+ struct lb_uint64 start;
+ struct lb_uint64 size;
+ uint32_t type;
+#define LB_MEM_RAM 1 /* Memory anyone can use */
+#define LB_MEM_RESERVED 2 /* Don't use this memory region */
+#define LB_MEM_ACPI 3 /* ACPI Tables */
+#define LB_MEM_NVS 4 /* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE 5 /* Unusable address space */
+#define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */
+#define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+ uint32_t tag;
+ uint32_t size;
+ struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB 0x0002
+struct lb_hwrpb {
+ uint32_t tag;
+ uint32_t size;
+ uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD 0x0003
+struct lb_mainboard {
+ uint32_t tag;
+ uint32_t size;
+ uint8_t vendor_idx;
+ uint8_t part_number_idx;
+ uint8_t strings[0];
+};
+
+#define LB_TAG_VERSION 0x0004
+#define LB_TAG_EXTRA_VERSION 0x0005
+#define LB_TAG_BUILD 0x0006
+#define LB_TAG_COMPILE_TIME 0x0007
+#define LB_TAG_COMPILE_BY 0x0008
+#define LB_TAG_COMPILE_HOST 0x0009
+#define LB_TAG_COMPILE_DOMAIN 0x000a
+#define LB_TAG_COMPILER 0x000b
+#define LB_TAG_LINKER 0x000c
+#define LB_TAG_ASSEMBLER 0x000d
+struct lb_string {
+ uint32_t tag;
+ uint32_t size;
+ uint8_t string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP 0x0026
+struct lb_timestamp {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL 0x000f
+struct lb_serial {
+ uint32_t tag;
+ uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED 1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+ uint32_t type;
+ uint32_t baseaddr;
+ uint32_t baud;
+ uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE 0x0010
+struct lb_console {
+ uint32_t tag;
+ uint32_t size;
+ uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250 0
+#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI 5
+#define LB_TAG_CONSOLE_SERIAL8250MEM 6
+
+#define LB_TAG_FORWARD 0x0011
+struct lb_forward {
+ uint32_t tag;
+ uint32_t size;
+ uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER 0x0012
+struct lb_framebuffer {
+ uint32_t tag;
+ uint32_t size;
+
+ uint64_t physical_address;
+ uint32_t x_resolution;
+ uint32_t y_resolution;
+ uint32_t bytes_per_line;
+ uint8_t bits_per_pixel;
+ uint8_t red_mask_pos;
+ uint8_t red_mask_size;
+ uint8_t green_mask_pos;
+ uint8_t green_mask_size;
+ uint8_t blue_mask_pos;
+ uint8_t blue_mask_size;
+ uint8_t reserved_mask_pos;
+ uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO 0x0013
+
+struct lb_gpio {
+ uint32_t port;
+ uint32_t polarity;
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+ uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+ uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t count;
+ struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT 0x0015
+#define LB_TAG_VBNV 0x0019
+#define LB_TAB_VBOOT_HANDOFF 0x0020
+#define LB_TAB_DMA 0x0022
+#define LB_TAG_RAM_OOPS 0x0023
+#define LB_TAG_MTC 0x002b
+struct lb_range {
+ uint32_t tag;
+ uint32_t size;
+
+ uint64_t range_start;
+ uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS 0x0016
+#define LB_TAG_CBMEM_CONSOLE 0x0017
+#define LB_TAG_MRC_CACHE 0x0018
+#define LB_TAG_ACPI_GNVS 0x0024
+#define LB_TAG_WIFI_CALIBRATION 0x0027
+struct lb_cbmem_ref {
+ uint32_t tag;
+ uint32_t size;
+
+ uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR 0x0021
+struct lb_x86_rom_mtrr {
+ uint32_t tag;
+ uint32_t size;
+ /* The variable range MTRR index covering the ROM. */
+ uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID 0x0025
+struct lb_board_id {
+ uint32_t tag;
+ uint32_t size;
+ /* Board ID as retrieved from the board revision GPIOs. */
+ uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS 0x0026
+struct mac_address {
+ uint8_t mac_addr[6];
+ uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t count;
+ struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE 0x0028
+struct lb_ram_code {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH 0x0029
+struct lb_spi_flash {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t flash_size;
+ uint32_t sector_size;
+ uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+ uint32_t tag;
+ uint32_t size;
+ /* offsets are relative to start of boot media */
+ uint64_t fmap_offset;
+ uint64_t cbfs_offset;
+ uint64_t cbfs_size;
+ uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO 0x002a
+#define MAX_SERIALNO_LENGTH 32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+ uint32_t tag; /* CMOS definitions table type */
+ uint32_t size; /* size of the entire table */
+ uint32_t header_length; /* length of header */
+};
+
+/* cmos entry record
+ This record is variable length. The name field may be
+ shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+ anywhere in the byte, but can not span bytes unless it
+ starts at the beginning of the byte and the length is
+ fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+ uint32_t tag; /* entry type */
+ uint32_t size; /* length of this record */
+ uint32_t bit; /* starting bit from start of image */
+ uint32_t length; /* length of field in bits */
+ uint32_t config; /* e=enumeration, h=hex, r=reserved */
+ uint32_t config_id; /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+ uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+ variable length int aligned */
+};
+
+
+/* cmos enumerations record
+ This record is variable length. The text field may be
+ shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+ uint32_t tag; /* enumeration type */
+ uint32_t size; /* length of this record */
+ uint32_t config_id; /* a number identifying the config id */
+ uint32_t value; /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+ uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+ variable length int aligned */
+};
+
+/* cmos defaults record
+ This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+ uint32_t tag; /* default type */
+ uint32_t size; /* length of this record */
+ uint32_t name_length; /* length of the following name field */
+ uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+ uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct cmos_checksum {
+ uint32_t tag;
+ uint32_t size;
+ /* In practice everything is byte aligned, but things are measured
+ * in bits to be consistent.
+ */
+ uint32_t range_start; /* First bit that is checksummed (byte aligned) */
+ uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
+ uint32_t location; /* First bit of the checksum (byte aligned) */
+ uint32_t type; /* Checksum algorithm that is used */
+#define CHECKSUM_NONE 0
+#define CHECKSUM_PCBIOS 1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE "__FMAP__"
+#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
+#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
+#define FMAP_STRLEN 32 /* maximum length for strings, */
+ /* including null-terminator */
+
+enum fmap_flags {
+ FMAP_AREA_STATIC = 1 << 0,
+ FMAP_AREA_COMPRESSED = 1 << 1,
+ FMAP_AREA_RO = 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+ uint32_t offset; /* offset relative to base */
+ uint32_t size; /* size in bytes */
+ uint8_t name[FMAP_STRLEN]; /* descriptive name */
+ uint16_t flags; /* flags for this area */
+} __attribute__((packed));
+
+struct fmap {
+ uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
+ uint8_t ver_major; /* major version */
+ uint8_t ver_minor; /* minor version */
+ uint64_t base; /* address of the firmware binary */
+ uint32_t size; /* size of firmware binary in bytes */
+ uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
+ uint16_t nareas; /* number of areas described by
+ fmap_areas[] below */
+ struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif /* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a) ALIGN((x),(a))
+#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+ offsetof(struct structure, member) == offset, \
+ "`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr: the pointer to the member.
+ * @param type: the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG 0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT 1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT 2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR 3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING 4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE 5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO 6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG 7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW 8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER 9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+ uint8_t *buf;
+ size_t size;
+ uint8_t *last_alloc;
+ size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_) \
+ { \
+ .buf = (buf_), \
+ .size = (size_), \
+ .last_alloc = NULL, \
+ .free_offset = 0, \
+ }
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+ mp->last_alloc = NULL;
+ mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+ mp->buf = buf;
+ mp->size = sz;
+ mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device. Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+ size_t size);
+
+
+/****************************************
+ * Implementation of a region device *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+ size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+ void *(*mmap)(const struct region_device *, size_t, size_t);
+ int (*munmap)(const struct region_device *, void *);
+ ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+ size_t offset;
+ size_t size;
+};
+
+struct region_device {
+ const struct region_device *root;
+ const struct region_device_ops *ops;
+ struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_) \
+ { \
+ .root = NULL, \
+ .ops = (ops_), \
+ .region = { \
+ .offset = (offset_), \
+ .size = (size_), \
+ }, \
+ }
+
+static inline size_t region_offset(const struct region *r)
+{
+ return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+ return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+ return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+ return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+ return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+ char *base;
+ struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+ size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_) \
+ { \
+ .base = (void *)(base_), \
+ .rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)), \
+ }
+
+struct mmap_helper_region_device {
+ struct mem_pool pool;
+ struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+ { \
+ .rdev = REGION_DEV_INIT((ops_), (offset_), (size_)), \
+ }
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+ void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values. */
+struct rmodule_header {
+ uint16_t magic;
+ uint8_t version;
+ uint8_t type;
+ /* The payload represents the program's loadable code and data. */
+ uint32_t payload_begin_offset;
+ uint32_t payload_end_offset;
+ /* Begin and of relocation information about the program module. */
+ uint32_t relocations_begin_offset;
+ uint32_t relocations_end_offset;
+ /* The starting address of the linked program. This address is vital
+ * for determining relocation offsets as the relocation info and other
+ * symbols (bss, entry point) need this value as a basis to calculate
+ * the offsets.
+ */
+ uint32_t module_link_start_address;
+ /* The module_program_size is the size of memory used while running
+ * the program. The program is assumed to consume a contiguous amount
+ * of memory. */
+ uint32_t module_program_size;
+ /* This is program's execution entry point. */
+ uint32_t module_entry_point;
+ /* Optional parameter structure that can be used to pass data into
+ * the module. */
+ uint32_t parameters_begin;
+ uint32_t parameters_end;
+ /* BSS section information so the loader can clear the bss. */
+ uint32_t bss_begin;
+ uint32_t bss_end;
+ /* Add some room for growth. */
+ uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+ uint32_t entry_id;
+ uint64_t entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+ uint64_t base_time;
+ uint16_t max_entries;
+ uint16_t tick_freq_mhz;
+ uint32_t num_entries;
+ struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+ TS_START_ROMSTAGE = 1,
+ TS_BEFORE_INITRAM = 2,
+ TS_AFTER_INITRAM = 3,
+ TS_END_ROMSTAGE = 4,
+ TS_START_VBOOT = 5,
+ TS_END_VBOOT = 6,
+ TS_START_COPYRAM = 8,
+ TS_END_COPYRAM = 9,
+ TS_START_RAMSTAGE = 10,
+ TS_START_BOOTBLOCK = 11,
+ TS_END_BOOTBLOCK = 12,
+ TS_START_COPYROM = 13,
+ TS_END_COPYROM = 14,
+ TS_START_ULZMA = 15,
+ TS_END_ULZMA = 16,
+ TS_DEVICE_ENUMERATE = 30,
+ TS_DEVICE_CONFIGURE = 40,
+ TS_DEVICE_ENABLE = 50,
+ TS_DEVICE_INITIALIZE = 60,
+ TS_DEVICE_DONE = 70,
+ TS_CBMEM_POST = 75,
+ TS_WRITE_TABLES = 80,
+ TS_LOAD_PAYLOAD = 90,
+ TS_ACPI_WAKE_JUMP = 98,
+ TS_SELFBOOT_JUMP = 99,
+
+ /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+ TS_START_COPYVER = 501,
+ TS_END_COPYVER = 502,
+ TS_START_TPMINIT = 503,
+ TS_END_TPMINIT = 504,
+ TS_START_VERIFY_SLOT = 505,
+ TS_END_VERIFY_SLOT = 506,
+ TS_START_HASH_BODY = 507,
+ TS_DONE_LOADING = 508,
+ TS_DONE_HASHING = 509,
+ TS_END_HASH_BODY = 510,
+
+ /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+ TS_FSP_MEMORY_INIT_START = 950,
+ TS_FSP_MEMORY_INIT_END = 951,
+ TS_FSP_TEMP_RAM_EXIT_START = 952,
+ TS_FSP_TEMP_RAM_EXIT_END = 953,
+ TS_FSP_SILICON_INIT_START = 954,
+ TS_FSP_SILICON_INIT_END = 955,
+ TS_FSP_BEFORE_ENUMERATE = 956,
+ TS_FSP_AFTER_ENUMERATE = 957,
+ TS_FSP_BEFORE_FINALIZE = 958,
+ TS_FSP_AFTER_FINALIZE = 959,
+
+ /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+ void *p;
+
+ /* Make all allocations be at least 8 byte aligned. */
+ sz = ALIGN_UP(sz, 8);
+
+ /* Determine if any space available. */
+ if ((mp->size - mp->free_offset) < sz)
+ return NULL;
+
+ p = &mp->buf[mp->free_offset];
+
+ mp->free_offset += sz;
+ mp->last_alloc = p;
+
+ return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+ /* Determine if p was the most recent allocation. */
+ if (p == NULL || mp->last_alloc != p)
+ return;
+
+ mp->free_offset = mp->last_alloc - mp->buf;
+ /* No way to track allocation before this one. */
+ mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+ return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+ if (region_offset(c) < region_offset(p))
+ return 0;
+
+ if (region_sz(c) > region_sz(p))
+ return 0;
+
+ if (region_end(c) > region_end(p))
+ return 0;
+
+ return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+ inner->offset += region_offset(outer);
+ return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+ if (rdev->root == NULL)
+ return rdev;
+ return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+ const struct region_device *rdev;
+ struct region req = {
+ .offset = offset,
+ .size = size,
+ };
+
+ if (!normalize_and_ok(&rd->region, &req))
+ return NULL;
+
+ rdev = rdev_root(rd);
+
+ return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+ const struct region_device *rdev;
+
+ rdev = rdev_root(rd);
+
+ return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+ size_t size)
+{
+ const struct region_device *rdev;
+ struct region req = {
+ .offset = offset,
+ .size = size,
+ };
+
+ if (!normalize_and_ok(&rd->region, &req))
+ return -1;
+
+ rdev = rdev_root(rd);
+
+ return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+ size_t offset, size_t size)
+{
+ struct region req = {
+ .offset = offset,
+ .size = size,
+ };
+
+ if (!normalize_and_ok(&parent->region, &req))
+ return -1;
+
+ /* Keep track of root region device. Note the offsets are relative
+ * to the root device. */
+ child->root = rdev_root(parent);
+ child->ops = NULL;
+ child->region.offset = req.offset;
+ child->region.size = req.size;
+
+ return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+ size_t size)
+{
+ memset(mdev, 0, sizeof(*mdev));
+ mdev->base = base;
+ mdev->rdev.ops = &mem_rdev_ops;
+ mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+ size_t size)
+{
+ const struct mem_region_device *mdev;
+
+ mdev = container_of(rd, typeof(*mdev), rdev);
+
+ return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+ return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+ size_t offset, size_t size)
+{
+ const struct mem_region_device *mdev;
+
+ mdev = container_of(rd, typeof(*mdev), rdev);
+
+ memcpy(b, &mdev->base[offset], size);
+
+ return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+ .mmap = mdev_mmap,
+ .munmap = mdev_munmap,
+ .readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+ void *cache, size_t cache_size)
+{
+ mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+ size_t size)
+{
+ struct mmap_helper_region_device *mdev;
+ void *mapping;
+
+ mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+ mapping = mem_pool_alloc(&mdev->pool, size);
+
+ if (mapping == NULL)
+ return NULL;
+
+ if (rd->ops->readat(rd, mapping, offset, size) != size) {
+ mem_pool_free(&mdev->pool, mapping);
+ return NULL;
+ }
+
+ return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+ struct mmap_helper_region_device *mdev;
+
+ mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+ mem_pool_free(&mdev->pool, mapping);
+
+ return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 9695b3b..b3772a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
#include <fsp/soc_binding.h>
#include <fsp/gop.h>
#include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
/* find_fsp() should only be called from assembly code. */
FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
#ifndef ASSETS_H
#define ASSETS_H
-#include <region.h>
+#include <commonlib/region.h>
/* An asset represents data used to boot the system. It can be found within
* CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
#ifndef COREBOOT_TABLES_H
#define COREBOOT_TABLES_H
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image. Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing. For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed. This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- * a particular motherboard is constructed? (Assuming the kernel
- * has drivers for all of the hardware but it does not have
- * assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not. This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped. Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
- uint32_t lo;
- uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
- uint64_t result;
- result = value.hi;
- result = (result << 32) + value.lo;
- return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
- struct lb_uint64 result;
- result.lo = (value >> 0) & 0xffffffff;
- result.hi = (value >> 32) & 0xffffffff;
- return result;
-}
-
-struct lb_header
-{
- uint8_t signature[4]; /* LBIO */
- uint32_t header_bytes;
- uint32_t header_checksum;
- uint32_t table_bytes;
- uint32_t table_checksum;
- uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record. Encoding both type and size. The type is obviously
- * so you can tell what it is. The size allows you to skip that
- * boot environment record if you don't know what it is. This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
- uint32_t tag; /* tag ID */
- uint32_t size; /* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED 0x0000
-
-#define LB_TAG_MEMORY 0x0001
-
-struct lb_memory_range {
- struct lb_uint64 start;
- struct lb_uint64 size;
- uint32_t type;
-#define LB_MEM_RAM 1 /* Memory anyone can use */
-#define LB_MEM_RESERVED 2 /* Don't use this memory region */
-#define LB_MEM_ACPI 3 /* ACPI Tables */
-#define LB_MEM_NVS 4 /* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE 5 /* Unusable address space */
-#define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */
-#define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
- uint32_t tag;
- uint32_t size;
- struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB 0x0002
-struct lb_hwrpb {
- uint32_t tag;
- uint32_t size;
- uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD 0x0003
-struct lb_mainboard {
- uint32_t tag;
- uint32_t size;
- uint8_t vendor_idx;
- uint8_t part_number_idx;
- uint8_t strings[0];
-};
-
-#define LB_TAG_VERSION 0x0004
-#define LB_TAG_EXTRA_VERSION 0x0005
-#define LB_TAG_BUILD 0x0006
-#define LB_TAG_COMPILE_TIME 0x0007
-#define LB_TAG_COMPILE_BY 0x0008
-#define LB_TAG_COMPILE_HOST 0x0009
-#define LB_TAG_COMPILE_DOMAIN 0x000a
-#define LB_TAG_COMPILER 0x000b
-#define LB_TAG_LINKER 0x000c
-#define LB_TAG_ASSEMBLER 0x000d
-struct lb_string {
- uint32_t tag;
- uint32_t size;
- uint8_t string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP 0x0026
-struct lb_timestamp {
- uint32_t tag;
- uint32_t size;
- uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL 0x000f
-struct lb_serial {
- uint32_t tag;
- uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED 1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
- uint32_t type;
- uint32_t baseaddr;
- uint32_t baud;
- uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE 0x0010
-struct lb_console {
- uint32_t tag;
- uint32_t size;
- uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250 0
-#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI 5
-#define LB_TAG_CONSOLE_SERIAL8250MEM 6
-
-#define LB_TAG_FORWARD 0x0011
-struct lb_forward {
- uint32_t tag;
- uint32_t size;
- uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER 0x0012
-struct lb_framebuffer {
- uint32_t tag;
- uint32_t size;
-
- uint64_t physical_address;
- uint32_t x_resolution;
- uint32_t y_resolution;
- uint32_t bytes_per_line;
- uint8_t bits_per_pixel;
- uint8_t red_mask_pos;
- uint8_t red_mask_size;
- uint8_t green_mask_pos;
- uint8_t green_mask_size;
- uint8_t blue_mask_pos;
- uint8_t blue_mask_size;
- uint8_t reserved_mask_pos;
- uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO 0x0013
-
-struct lb_gpio {
- uint32_t port;
- uint32_t polarity;
-#define ACTIVE_LOW 0
-#define ACTIVE_HIGH 1
- uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
- uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
- uint32_t tag;
- uint32_t size;
-
- uint32_t count;
- struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT 0x0015
-#define LB_TAG_VBNV 0x0019
-#define LB_TAB_VBOOT_HANDOFF 0x0020
-#define LB_TAB_DMA 0x0022
-#define LB_TAG_RAM_OOPS 0x0023
-#define LB_TAG_MTC 0x002b
-struct lb_range {
- uint32_t tag;
- uint32_t size;
-
- uint64_t range_start;
- uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS 0x0016
-#define LB_TAG_CBMEM_CONSOLE 0x0017
-#define LB_TAG_MRC_CACHE 0x0018
-#define LB_TAG_ACPI_GNVS 0x0024
-#define LB_TAG_WIFI_CALIBRATION 0x0027
-struct lb_cbmem_ref {
- uint32_t tag;
- uint32_t size;
-
- uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR 0x0021
-struct lb_x86_rom_mtrr {
- uint32_t tag;
- uint32_t size;
- /* The variable range MTRR index covering the ROM. */
- uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID 0x0025
-struct lb_board_id {
- uint32_t tag;
- uint32_t size;
- /* Board ID as retrieved from the board revision GPIOs. */
- uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS 0x0026
-struct mac_address {
- uint8_t mac_addr[6];
- uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
- uint32_t tag;
- uint32_t size;
- uint32_t count;
- struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE 0x0028
-struct lb_ram_code {
- uint32_t tag;
- uint32_t size;
- uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH 0x0029
-struct lb_spi_flash {
- uint32_t tag;
- uint32_t size;
- uint32_t flash_size;
- uint32_t sector_size;
- uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
- uint32_t tag;
- uint32_t size;
- /* offsets are relative to start of boot media */
- uint64_t fmap_offset;
- uint64_t cbfs_offset;
- uint64_t cbfs_size;
- uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO 0x002a
-#define MAX_SERIALNO_LENGTH 32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
- uint32_t tag; /* CMOS definitions table type */
- uint32_t size; /* size of the entire table */
- uint32_t header_length; /* length of header */
-};
-
-/* cmos entry record
- This record is variable length. The name field may be
- shorter than CMOS_MAX_NAME_LENGTH. The entry may start
- anywhere in the byte, but can not span bytes unless it
- starts at the beginning of the byte and the length is
- fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
- uint32_t tag; /* entry type */
- uint32_t size; /* length of this record */
- uint32_t bit; /* starting bit from start of image */
- uint32_t length; /* length of field in bits */
- uint32_t config; /* e=enumeration, h=hex, r=reserved */
- uint32_t config_id; /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
- uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
- variable length int aligned */
-};
-
-
-/* cmos enumerations record
- This record is variable length. The text field may be
- shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
- uint32_t tag; /* enumeration type */
- uint32_t size; /* length of this record */
- uint32_t config_id; /* a number identifying the config id */
- uint32_t value; /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
- uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
- variable length int aligned */
-};
-
-/* cmos defaults record
- This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
- uint32_t tag; /* default type */
- uint32_t size; /* length of this record */
- uint32_t name_length; /* length of the following name field */
- uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
- uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct cmos_checksum {
- uint32_t tag;
- uint32_t size;
- /* In practice everything is byte aligned, but things are measured
- * in bits to be consistent.
- */
- uint32_t range_start; /* First bit that is checksummed (byte aligned) */
- uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
- uint32_t location; /* First bit of the checksum (byte aligned) */
- uint32_t type; /* Checksum algorithm that is used */
-#define CHECKSUM_NONE 0
-#define CHECKSUM_PCBIOS 1
-};
-
+#include <commonlib/coreboot_tables.h>
/* function prototypes for building the coreboot table */
unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
#ifndef _BOOT_DEVICE_H_
#define _BOOT_DEVICE_H_
-#include <region.h>
+#include <commonlib/region.h>
/* Return the region_device for the read-only boot device. */
const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
#ifndef _CBFS_H_
#define _CBFS_H_
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
#include <program_loading.h>
-#include <region.h>
/*
* CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- * - The GNU GPL, version 2, as published by the Free Software Foundation
- * - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
- algorithms that coreboot knows about for stages and
- payloads. Of course, other CBFS users can use whatever
- values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE 0
-#define CBFS_COMPRESS_LZMA 1
-
-/** These are standard component types for well known
- components (i.e - those that coreboot needs to consume.
- Users are welcome to use any other value for their
- components */
-
-#define CBFS_TYPE_STAGE 0x10
-#define CBFS_TYPE_PAYLOAD 0x20
-#define CBFS_TYPE_OPTIONROM 0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW 0x50
-#define CBFS_TYPE_VSA 0x51
-#define CBFS_TYPE_MBI 0x52
-#define CBFS_TYPE_MICROCODE 0x53
-#define CBFS_TYPE_FSP 0x60
-#define CBFS_TYPE_MRC 0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD 0xab
-#define CBFS_TYPE_MRC_CACHE 0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC 0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
- uint32_t magic;
- uint32_t version;
- uint32_t romsize;
- uint32_t bootblocksize;
- uint32_t align; /* fixed to 64 bytes */
- uint32_t offset;
- uint32_t architecture;
- uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86 0x00000001
-#define CBFS_ARCHITECTURE_ARM 0x00000010
-
-/** This is a component header - every entry in the CBFS
- will have this header.
-
- This is how the component is arranged in the ROM:
-
- -------------- <- 0
- component header
- -------------- <- sizeof(struct component)
- component name
- -------------- <- offset
- data
- ...
- -------------- <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
- char magic[8];
- uint32_t len;
- uint32_t type;
- uint32_t checksum;
- uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
- component types */
-
-/** This is the sub-header for stage components. Stages are
- loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
- uint32_t compression; /** Compression type */
- uint64_t entry; /** entry point */
- uint64_t load; /** Where to load in memory */
- uint32_t len; /** length of data to load */
- uint32_t memlen; /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components. Payloads
- are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
- uint32_t type;
- uint32_t compression;
- uint32_t offset;
- uint64_t load_addr;
- uint32_t len;
- uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
- struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE 0x45444F43
-#define PAYLOAD_SEGMENT_DATA 0x41544144
-#define PAYLOAD_SEGMENT_BSS 0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY 0x52544E45
-
-struct cbfs_optionrom {
- uint32_t compression;
- uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
#ifndef _CBMEM_H_
#define _CBMEM_H_
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
#include <rules.h>
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI 0x41435049
-#define CBMEM_ID_ACPI_GNVS 0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME 0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
-#define CBMEM_ID_CBTABLE 0x43425442
-#define CBMEM_ID_CONSOLE 0x434f4e53
-#define CBMEM_ID_COVERAGE 0x47434f56
-#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9
-#define CBMEM_ID_ELOG 0x454c4f47
-#define CBMEM_ID_FREESPACE 0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME 0x52505346
-#define CBMEM_ID_GDT 0x4c474454
-#define CBMEM_ID_HOB_POINTER 0x484f4221
-#define CBMEM_ID_IGD_OPREGION 0x4f444749
-#define CBMEM_ID_IMD_ROOT 0xff4017ff
-#define CBMEM_ID_IMD_SMALL 0x53a11439
-#define CBMEM_ID_MEMINFO 0x494D454D
-#define CBMEM_ID_MPTABLE 0x534d5054
-#define CBMEM_ID_MRCDATA 0x4d524344
-#define CBMEM_ID_MTC 0xcb31d31c
-#define CBMEM_ID_NONE 0x00000000
-#define CBMEM_ID_PIRQ 0x49525154
-#define CBMEM_ID_POWER_STATE 0x50535454
-#define CBMEM_ID_RAM_OOPS 0x05430095
-#define CBMEM_ID_RAMSTAGE 0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e
-#define CBMEM_ID_REFCODE 0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE 0x4efc0de5
-#define CBMEM_ID_RESUME 0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH 0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO 0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT 0xff4007ff
-#define CBMEM_ID_SMBIOS 0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
-#define CBMEM_ID_SPINTABLE 0x59175917
-#define CBMEM_ID_STAGEx_META 0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
-#define CBMEM_ID_TCPA_LOG 0x54435041
-#define CBMEM_ID_TIMESTAMP 0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF 0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE \
- { CBMEM_ID_ACPI, "ACPI " }, \
- { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
- { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \
- { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
- { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
- { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
- { CBMEM_ID_CBTABLE, "COREBOOT " }, \
- { CBMEM_ID_CONSOLE, "CONSOLE " }, \
- { CBMEM_ID_COVERAGE, "COVERAGE " }, \
- { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \
- { CBMEM_ID_ELOG, "ELOG " }, \
- { CBMEM_ID_FREESPACE, "FREE SPACE " }, \
- { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
- { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \
- { CBMEM_ID_GDT, "GDT " }, \
- { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \
- { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \
- { CBMEM_ID_MEMINFO, "MEM INFO " }, \
- { CBMEM_ID_MPTABLE, "SMP TABLE " }, \
- { CBMEM_ID_MRCDATA, "MRC DATA " }, \
- { CBMEM_ID_MTC, "MTC " }, \
- { CBMEM_ID_PIRQ, "IRQ TABLE " }, \
- { CBMEM_ID_POWER_STATE, "POWER STATE" }, \
- { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \
- { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \
- { CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \
- { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \
- { CBMEM_ID_REFCODE, "REFCODE " }, \
- { CBMEM_ID_RESUME, "ACPI RESUME" }, \
- { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \
- { CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \
- { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \
- { CBMEM_ID_ROOT, "CBMEM ROOT " }, \
- { CBMEM_ID_SMBIOS, "SMBIOS " }, \
- { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
- { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \
- { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \
- { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
- { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
- { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \
- { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <rules.h>
#include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef __ROMCC__
struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
#include <console/console.h>
#include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
/* While in romstage, console loglevel is built-time constant.
* With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki at nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG 0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT 1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT 2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR 3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING 4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE 5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO 6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG 7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW 8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER 9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
#ifndef _FMAP_H_
#define _FMAP_H_
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
/* Locate the fmap directory. Return 0 on success, < 0 on error. */
int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE "__FMAP__"
-#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
-#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
-#define FMAP_STRLEN 32 /* maximum length for strings, */
- /* including null-terminator */
-
-enum fmap_flags {
- FMAP_AREA_STATIC = 1 << 0,
- FMAP_AREA_COMPRESSED = 1 << 1,
- FMAP_AREA_RO = 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
- uint32_t offset; /* offset relative to base */
- uint32_t size; /* size in bytes */
- uint8_t name[FMAP_STRLEN]; /* descriptive name */
- uint16_t flags; /* flags for this area */
-} __attribute__((packed));
-
-struct fmap {
- uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
- uint8_t ver_major; /* major version */
- uint8_t ver_minor; /* minor version */
- uint64_t base; /* address of the firmware binary */
- uint32_t size; /* size of firmware binary in bytes */
- uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
- uint16_t nareas; /* number of areas described by
- fmap_areas[] below */
- struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif /* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
- uint8_t *buf;
- size_t size;
- uint8_t *last_alloc;
- size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_) \
- { \
- .buf = (buf_), \
- .size = (size_), \
- .last_alloc = NULL, \
- .free_offset = 0, \
- }
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
- mp->last_alloc = NULL;
- mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
- mp->buf = buf;
- mp->size = sz;
- mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device. Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
- size_t size);
-
-
-/****************************************
- * Implementation of a region device *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
- size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
- void *(*mmap)(const struct region_device *, size_t, size_t);
- int (*munmap)(const struct region_device *, void *);
- ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
- size_t offset;
- size_t size;
-};
-
-struct region_device {
- const struct region_device *root;
- const struct region_device_ops *ops;
- struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_) \
- { \
- .root = NULL, \
- .ops = (ops_), \
- .region = { \
- .offset = (offset_), \
- .size = (size_), \
- }, \
- }
-
-static inline size_t region_offset(const struct region *r)
-{
- return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
- return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
- return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
- return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
- return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
- char *base;
- struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
- size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_) \
- { \
- .base = (void *)(base_), \
- .rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)), \
- }
-
-struct mmap_helper_region_device {
- struct mem_pool pool;
- struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
- { \
- .rdev = REGION_DEV_INIT((ops_), (offset_), (size_)), \
- }
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
- void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values. */
-struct rmodule_header {
- uint16_t magic;
- uint8_t version;
- uint8_t type;
- /* The payload represents the program's loadable code and data. */
- uint32_t payload_begin_offset;
- uint32_t payload_end_offset;
- /* Begin and of relocation information about the program module. */
- uint32_t relocations_begin_offset;
- uint32_t relocations_end_offset;
- /* The starting address of the linked program. This address is vital
- * for determining relocation offsets as the relocation info and other
- * symbols (bss, entry point) need this value as a basis to calculate
- * the offsets.
- */
- uint32_t module_link_start_address;
- /* The module_program_size is the size of memory used while running
- * the program. The program is assumed to consume a contiguous amount
- * of memory. */
- uint32_t module_program_size;
- /* This is program's execution entry point. */
- uint32_t module_entry_point;
- /* Optional parameter structure that can be used to pass data into
- * the module. */
- uint32_t parameters_begin;
- uint32_t parameters_end;
- /* BSS section information so the loader can clear the bss. */
- uint32_t bss_begin;
- uint32_t bss_end;
- /* Add some room for growth. */
- uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <stddef.h>
#include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
enum {
RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
#ifndef STDDEF_H
#define STDDEF_H
+#include <commonlib/helpers.h>
+
typedef long ptrdiff_t;
#ifndef __SIZE_TYPE__
#define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
#define NULL ((void *)0)
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
- offsetof(struct structure, member) == offset, \
- "`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr: the pointer to the member.
- * @param type: the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({ \
- const typeof( ((type *)0)->member ) *__mptr = (ptr); \
- (type *)( (char *)__mptr - offsetof(type,member) );})
-
#ifdef __PRE_RAM__
#define ROMSTAGE_CONST const
#else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
#include <stddef.h>
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a) ALIGN((x),(a))
-#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
-
#define min(a,b) MIN((a),(b))
#define max(a,b) MAX((a),(b))
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
#ifndef __TIMESTAMP_H__
#define __TIMESTAMP_H__
-#include <stdint.h>
-
-struct timestamp_entry {
- uint32_t entry_id;
- uint64_t entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
- uint64_t base_time;
- uint16_t max_entries;
- uint16_t tick_freq_mhz;
- uint32_t num_entries;
- struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
- TS_START_ROMSTAGE = 1,
- TS_BEFORE_INITRAM = 2,
- TS_AFTER_INITRAM = 3,
- TS_END_ROMSTAGE = 4,
- TS_START_VBOOT = 5,
- TS_END_VBOOT = 6,
- TS_START_COPYRAM = 8,
- TS_END_COPYRAM = 9,
- TS_START_RAMSTAGE = 10,
- TS_START_BOOTBLOCK = 11,
- TS_END_BOOTBLOCK = 12,
- TS_START_COPYROM = 13,
- TS_END_COPYROM = 14,
- TS_START_ULZMA = 15,
- TS_END_ULZMA = 16,
- TS_DEVICE_ENUMERATE = 30,
- TS_DEVICE_CONFIGURE = 40,
- TS_DEVICE_ENABLE = 50,
- TS_DEVICE_INITIALIZE = 60,
- TS_DEVICE_DONE = 70,
- TS_CBMEM_POST = 75,
- TS_WRITE_TABLES = 80,
- TS_LOAD_PAYLOAD = 90,
- TS_ACPI_WAKE_JUMP = 98,
- TS_SELFBOOT_JUMP = 99,
-
- /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
- TS_START_COPYVER = 501,
- TS_END_COPYVER = 502,
- TS_START_TPMINIT = 503,
- TS_END_TPMINIT = 504,
- TS_START_VERIFY_SLOT = 505,
- TS_END_VERIFY_SLOT = 506,
- TS_START_HASH_BODY = 507,
- TS_DONE_LOADING = 508,
- TS_DONE_HASHING = 509,
- TS_END_HASH_BODY = 510,
-
- /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
- TS_FSP_MEMORY_INIT_START = 950,
- TS_FSP_MEMORY_INIT_END = 951,
- TS_FSP_TEMP_RAM_EXIT_START = 952,
- TS_FSP_TEMP_RAM_EXIT_END = 953,
- TS_FSP_SILICON_INIT_START = 954,
- TS_FSP_SILICON_INIT_END = 955,
- TS_FSP_BEFORE_ENUMERATE = 956,
- TS_FSP_AFTER_ENUMERATE = 957,
- TS_FSP_BEFORE_FINALIZE = 958,
- TS_FSP_AFTER_FINALIZE = 959,
-
- /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
/*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
bootblock-$(CONFIG_I2C_TPM) += delay.c
bootblock-y += memchr.c
bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
bootblock-y += boot_device.c
bootblock-y += fmap.c
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
verstage-y += libgcc.c
verstage-y += memcmp.c
verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
verstage-y += boot_device.c
verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
romstage-y += assets.c
romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
endif
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
-romstage-y += region.c
-ramstage-y += region.c
romstage-y += boot_device.c
ramstage-y += boot_device.c
-smm-y += region.c
smm-y += boot_device.c
smm-y += fmap.c
smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
#include <cbfs.h>
#include <console/console.h>
#include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
/* This function is marked as weak to allow a particular platform to
* override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
#include <boot_device.h>
#include <console/console.h>
#include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
#include <stddef.h>
#include <string.h>
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
- void *p;
-
- /* Make all allocations be at least 8 byte aligned. */
- sz = ALIGN_UP(sz, 8);
-
- /* Determine if any space available. */
- if ((mp->size - mp->free_offset) < sz)
- return NULL;
-
- p = &mp->buf[mp->free_offset];
-
- mp->free_offset += sz;
- mp->last_alloc = p;
-
- return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
- /* Determine if p was the most recent allocation. */
- if (p == NULL || mp->last_alloc != p)
- return;
-
- mp->free_offset = mp->last_alloc - mp->buf;
- /* No way to track allocation before this one. */
- mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
- return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
- if (region_offset(c) < region_offset(p))
- return 0;
-
- if (region_sz(c) > region_sz(p))
- return 0;
-
- if (region_end(c) > region_end(p))
- return 0;
-
- return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
- inner->offset += region_offset(outer);
- return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
- if (rdev->root == NULL)
- return rdev;
- return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
- const struct region_device *rdev;
- struct region req = {
- .offset = offset,
- .size = size,
- };
-
- if (!normalize_and_ok(&rd->region, &req))
- return NULL;
-
- rdev = rdev_root(rd);
-
- return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
- const struct region_device *rdev;
-
- rdev = rdev_root(rd);
-
- return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
- size_t size)
-{
- const struct region_device *rdev;
- struct region req = {
- .offset = offset,
- .size = size,
- };
-
- if (!normalize_and_ok(&rd->region, &req))
- return -1;
-
- rdev = rdev_root(rd);
-
- return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
- size_t offset, size_t size)
-{
- struct region req = {
- .offset = offset,
- .size = size,
- };
-
- if (!normalize_and_ok(&parent->region, &req))
- return -1;
-
- /* Keep track of root region device. Note the offsets are relative
- * to the root device. */
- child->root = rdev_root(parent);
- child->ops = NULL;
- child->region.offset = req.offset;
- child->region.size = req.size;
-
- return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
- size_t size)
-{
- memset(mdev, 0, sizeof(*mdev));
- mdev->base = base;
- mdev->rdev.ops = &mem_rdev_ops;
- mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
- size_t size)
-{
- const struct mem_region_device *mdev;
-
- mdev = container_of(rd, typeof(*mdev), rdev);
-
- return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
- return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
- size_t offset, size_t size)
-{
- const struct mem_region_device *mdev;
-
- mdev = container_of(rd, typeof(*mdev), rdev);
-
- memcpy(b, &mdev->base[offset], size);
-
- return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
- .mmap = mdev_mmap,
- .munmap = mdev_munmap,
- .readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
- void *cache, size_t cache_size)
-{
- mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
- size_t size)
-{
- struct mmap_helper_region_device *mdev;
- void *mapping;
-
- mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
- mapping = mem_pool_alloc(&mdev->pool, size);
-
- if (mapping == NULL)
- return NULL;
-
- if (rd->ops->readat(rd, mapping, offset, size) != size) {
- mem_pool_free(&mdev->pool, mapping);
- return NULL;
- }
-
- return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
- struct mmap_helper_region_device *mdev;
-
- mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
- mem_pool_free(&mdev->pool, mapping);
-
- return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
#include <spd.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
#include <boot_device.h>
#include <cbfs.h>
#include <cbmem.h>
+#include <commonlib/region.h>
#include <console/console.h>
#include <device/i2c.h>
#include <drivers/maxim/max77802/max77802.h>
#include <program_loading.h>
-#include <region.h>
#include <soc/clk.h>
#include <soc/cpu.h>
#include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
#include <stdint.h>
#include <string.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
#ifndef _BROADWELL_ME_H_
#define _BROADWELL_ME_H_
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#define ME_RETRY 100000 /* 1 second */
#define ME_DELAY 10 /* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
#include <cpu/amd/common/cbtypes.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifdef NULL
#undef NULL
#endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
#include "sb_cimx.h"
#include "sb700_cfg.h" /*sb700_cimx_config*/
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include "smbus.h"
/**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
#include "SbPlatform.h"
#include "sb_cimx.h"
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include "smbus.h"
/**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
#include <assert.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
#include <assert.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
#include <assert.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
#include "amdlib.h"
#include "cbfs.h"
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
// TODO Add a kconfig option to name the AGESA ROM file in CBFS
#define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
#include <assert.h>
#include <config.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
AGESA_INC += -I$(src)/arch/x86/include
AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
#define VBOOT_COMMON_H
#include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
/* The FW areas consist of multiple components. At the beginning of
* each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 65d5710..db93fe1 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -9,6 +9,7 @@ CFLAGS += -Wstrict-prototypes -Wwrite-strings
CPPFLAGS += -D_DEFAULT_SOURCE # memccpy() from string.h
CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h
CPPFLAGS += -Iflashmap
+CPPFLAGS += -I../../src/commonlib/include
LDFLAGS += -g3
CBFSTOOL_BINARY:=$(obj)/cbfstool
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 976f0c2..f14ad11 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -49,6 +49,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
TOOLCPPFLAGS += -I$(top)/util/cbfstool
TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
TOOLLDFLAGS ?=
ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
#include "elfparsing.h"
#include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
/*
* Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
CC ?= $(CROSS_COMPILE)gcc
CFLAGS ?= -O2
CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
OBJS = $(PROGRAM).o
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
#include <sys/mman.h>
#include <libgen.h>
#include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
#ifdef __OpenBSD__
#include <sys/param.h>
@@ -42,18 +45,12 @@
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
-#include "cbmem_id.h"
-#include "timestamp.h"
-
#define CBMEM_VERSION "1.1"
/* verbose output? */
More information about the coreboot-gerrit
mailing list