[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Create "RtcLock" Silicon UPD from coreboot

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit b090a268a2e993fc7fa719ab3b9b7283034c9d10
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Tue Sep 8 16:00:46 2015 +0530

    intel/skylake: Create "RtcLock" Silicon UPD from coreboot
    
    FSP should not lock CMOS unconditionally. coreboot sends Silicon
    UPD parameter "RtcLock" to FSP to take action on CMOS
    region locking/un-locking. This patch has CB generic code for
    creating the Silicon UPD paramater.
    
    BUG=chrome-os-partner:44484
    BRANCH=none
    TEST=Build and booted in kunimitsu, tested using below command-
    When DIsabled RtcLock from devicetree in coreboot, booted to kernel
    and run following commands -
    >> crossystem fw_result=success
    >> crossystem | grep fw_result
    It should reflect the value that is set. Here, success.
    If ENabled RtcLock from Coreboot devicetree, The same commands will
    fail to update the fw_result status from crossystem utility.
    CQ-DEPEND=CL:*229144
    
    Change-Id: I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c7b8293a2c55117d7ca2001ac9ec0de24d35b80b
    Original-Change-Id: If708e2c782644dcf7f03785d1bfa235ef5385d80
    Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297980
    Original-Commit-Ready: Subrata Banik <subrata.banik at intel.com>
    Original-Tested-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11655
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11655 for details.

-gerrit