[coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: add README

[WANG Siyuan (wangsiyuanbuaa@gmail.com)]

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11737

-gerrit

commit 64daad064db528b6cb4ca9759f81fe0b08307af5
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Tue Sep 29 11:12:03 2015 +0800

    AMD Bettong: add README
    
    AMD provide stable Bettong code in github.
    
    Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/mainboard/amd/bettong/README | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/mainboard/amd/bettong/README b/src/mainboard/amd/bettong/README
new file mode 100644
index 0000000..acbe0bb
--- /dev/null
+++ b/src/mainboard/amd/bettong/README
@@ -0,0 +1,23 @@
+coreboot is changing all the time and the patches are reabsed when push to
+community, so it is a little difficult to provide stable Bettong code.
+From now on, AMD provide souce code which is validated by QA team.
+The code is push to github https://github.com/BTDC/coreboot
+The version is identified by tag. All the changes will be push to coreboot
+community.
+
+=====
+TCMEF1F0:
+1. Fix external graphics issue.
+2. Add board ID support.
+3. Support DDR4.
+4. Support SD 2.0.
+5. Fix Windows 7 S4 issue.
+6. Add GPIO, I2C and UART support.
+7. Fix the interrupt routine.
+8. Restruct PCI interrupt table (C00/C01).
+9. Fix DSDT issue.
+10. Fix the PCIe lane map.
+11. Lower the TOM to give more MMIO space.
+12. Add USB device.
+13. Set the USB3 port as unremoveable.
+14. Update AGESA to CarrizoPI 1.1.0.1.