[coreboot-gerrit] Patch set updated for coreboot: northbridge/intel/gm45: Fix native VGA init

[Audrey Pearson (apearson@raptorengineeringinc.com)]

Audrey Pearson (apearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11738

-gerrit

commit 44a9388820a437f9239d4246d3c66bcd8e6939aa
Author: Audrey Pearson <apearson at raptorengineeringinc.com>
Date:   Tue Sep 29 12:36:52 2015 -0500

    northbridge/intel/gm45: Fix native VGA init
    
    Building an image for the Lenovo X200 with native graphics
    initialization selected fails due to the changes introduced
    by commit a3b898aa (edid: Clean-up the edid struct).
    
    Change-Id: Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25
    Signed-off-by: Audrey Pearson <apearson at raptorengineeringinc.com>
---
 src/northbridge/intel/gm45/gma.c | 32 +++++++++++++++++---------------
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index f29b9b1..42b340a 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -109,6 +109,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 	int i;
 	u8 edid_data[128];
 	struct edid edid;
+	struct edid_mode *mode;
 	u32 hactive, vactive, right_border, bottom_border;
 	int hpolarity, vpolarity;
 	u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
@@ -155,25 +156,26 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 	intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128);
 	decode_edid(edid_data,
 		    sizeof(edid_data), &edid);
+	mode = &edid.mode;
 
 	/* Disable screen memory to prevent garbage from appearing.  */
 	vga_sr_write(1, vga_sr_read(1) | 0x20);
 
 	hactive = edid.x_resolution;
 	vactive = edid.y_resolution;
-	right_border = edid.hborder;
-	bottom_border = edid.vborder;
-	hpolarity = (edid.phsync == '-');
-	vpolarity = (edid.pvsync == '-');
-	vsync = edid.vspw;
-	hsync = edid.hspw;
-	vblank = edid.vbl;
-	hblank = edid.hbl;
-	hfront_porch = edid.hso;
-	vfront_porch = edid.vso;
-
-	target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
-		: (2 * edid.pixel_clock);
+	right_border = mode->hborder;
+	bottom_border = mode->vborder;
+	hpolarity = (mode->phsync == '-');
+	vpolarity = (mode->pvsync == '-');
+	vsync = mode->vspw;
+	hsync = mode->hspw;
+	vblank = mode->vbl;
+	hblank = mode->hbl;
+	hfront_porch = mode->hso;
+	vfront_porch = mode->vso;
+
+	target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock
+		: (2 * mode->pixel_clock);
 #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_sr_write(1, 1);
 	vga_sr_write(0x2, 0xf);
@@ -240,8 +242,8 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 		return;
 	}
 
-	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
-	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
+	link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
+	data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
 		/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",