[coreboot-gerrit] New patch to review for coreboot: arch/arm64: Use correct SPSR.DAIF mask for BL31 and payload

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13596

-gerrit

commit 2ad28bbb7feef54e53ea45dc1ae44d03593ccd18
Author: Julius Werner <jwerner at chromium.org>
Date:   Mon Feb 1 19:47:10 2016 -0800

    arch/arm64: Use correct SPSR.DAIF mask for BL31 and payload
    
    The PSTATE mask bits for Debug exceptions, external Aborts, Interrupts
    and Fast interrupts are usually best left unset: under normal
    circumstances none of those exceptions should occur in firmware, and if
    they do it's better to get a crash close to the code that caused it
    (rather than much later when the kernel first unmasks them). For this
    reason arm64_cpu_init unmasks them right after boot. However, the EL2
    payload was still running with all mask bits set, which this patch
    fixes.
    
    BL31, on the other hand, explicitly wants to be entered with all masks
    set (see calling convention in docs/firmware-design.md), which we had
    previously not been doing. It doesn't seem to make a difference at the
    moment, but since it's explicitly specified we should probably comply.
    
    BRANCH=None
    BUG=None
    TEST=Booted Oak, confirmed with raw_read_daif() in payload that mask
    bits are now cleared.
    
    Change-Id: I04406da4c435ae7d44e2592c41f9807934bbc802
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6ba55bc23fbde962d91c87dc0f982437572a69a8
    Original-Change-Id: Ic5fbdd4e1cd7933c8b0c7c5fe72eac2022c9553c
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/325056
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/arm64/arm_tf.c | 1 +
 src/arch/arm64/boot.c   | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c
index 1cb35ba..9735e1b 100644
--- a/src/arch/arm64/arm_tf.c
+++ b/src/arch/arm64/arm_tf.c
@@ -84,6 +84,7 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 
 	dcache_clean_by_mva(&bl31_params, sizeof(bl31_params));
 	dcache_clean_by_mva(&bl33_ep_info, sizeof(bl33_ep_info));
+	raw_write_daif(SPSR_EXCEPTION_MASK);
 	mmu_disable();
 	bl31_entry(&bl31_params, bl31_plat_params);
 	die("BL31 returned!");
diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
index eea758c..fa83c3f 100644
--- a/src/arch/arm64/boot.c
+++ b/src/arch/arm64/boot.c
@@ -31,7 +31,7 @@ static void run_payload(struct prog *prog)
 
 	doit = prog_entry(prog);
 	arg = prog_entry_arg(prog);
-	u64 payload_spsr = SPSR_EXCEPTION_MASK | get_eret_el(EL2, SPSR_USE_L);
+	u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L);
 
 	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr);