[coreboot-gerrit] New patch to review for coreboot: cpu/intel/microcode: allow microcode to be loaded in romstage

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13611

-gerrit

commit f1b6217fd29315ef669d93350cccf88385ff2f45
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Feb 5 14:58:06 2016 -0600

    cpu/intel/microcode: allow microcode to be loaded in romstage
    
    The previous usage of the intel microcode support supported using
    the library under ROMCC and ramstage. Allow for microcode support
    to be used in normal C-based romstage as well by:
    
    1. Only using walkcbfs when ROMCC is defined.
    2. Only using spinlocks if !__PRE_RAM__
    
    The header file now unconditionally exposes the declarations
    of the supporting functions.
    
    Change-Id: I903578bcb4422b4c050903c53b60372b64b79af1
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/intel/microcode/Makefile.inc | 1 +
 src/cpu/intel/microcode/microcode.c  | 8 ++++----
 src/include/cpu/intel/microcode.h    | 4 ++--
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index 1feb504..7452973 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -3,3 +3,4 @@
 ## directly from CBFS. You have been WARNED!!!
 ################################################################################
 ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
+romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 35eff16..b068141 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -19,7 +19,10 @@
 #include <stdint.h>
 #include <stddef.h>
 #if !defined(__ROMCC__)
+#include <cbfs.h>
 #include <console/console.h>
+#else
+#include <arch/cbfs.h>
 #endif
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
@@ -27,11 +30,8 @@
 #include <rules.h>
 
 #if !defined(__PRE_RAM__)
-#include <cbfs.h>
 #include <smp/spinlock.h>
 DECLARE_SPIN_LOCK(microcode_lock)
-#else
-#include <arch/cbfs.h>
 #endif
 
 struct microcode {
@@ -121,7 +121,7 @@ const void *intel_microcode_find(void)
 	unsigned int x86_model, x86_family;
 	msr_t msr;
 
-#ifdef __PRE_RAM__
+#ifdef __ROMCC__
 	struct cbfs_file *microcode_file;
 
 	microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE);
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index 0f71b5d..0783ace 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -16,7 +16,8 @@
 #ifndef __CPU__INTEL__MICROCODE__
 #define __CPU__INTEL__MICROCODE__
 
-#ifndef __PRE_RAM__
+#include <stdint.h>
+
 void intel_update_microcode_from_cbfs(void);
 /* Find a microcode that matches the revision and platform family returning
  * NULL if none found. */
@@ -29,6 +30,5 @@ void intel_microcode_load_unlocked(const void *microcode_patch);
 /* SoC specific check to determine if microcode update is really
  * required, will skip microcode update if true. */
 int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id);
-#endif
 
 #endif