[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Add gpio macro for unused GPIO pins

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 4852dec1ab21e6c6e32eb85354ce4f4182537442
Author: david <david_wu at quantatw.com>
Date:   Tue Dec 29 15:02:04 2015 +0800

    intel/skylake: Add gpio macro for unused GPIO pins
    
    Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
    GPIO TX/RX will be disabled.
    
    BUG=none
    BRANCH=none
    TEST=Build and boot lars
    
    Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9
    Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
    Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/319964
    Original-Commit-Ready: David Wu <david_wu at quantatw.com>
    Original-Tested-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj at intel.com>
    Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
    Reviewed-on: https://review.coreboot.org/13628
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/13628 for details.

-gerrit