[coreboot-gerrit] Patch set updated for coreboot: link: Support native raminit
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Wed Feb 10 03:20:05 CET 2016
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13665
-gerrit
commit 9362d79c79460c39f56ea554093cfac9ef3a3110
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Wed Feb 10 03:07:42 2016 +0100
link: Support native raminit
Change-Id: I95173c06d334a340fa2157511a1d69f38877b264
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/google/link/Kconfig | 4 ----
src/mainboard/google/link/devicetree.cb | 2 ++
src/mainboard/google/link/romstage.c | 34 +++++++++++++++++++++++++++------
3 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index c9bfa2e..ac06a62 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_NATIVE_VGA_INIT
-config USE_NATIVE_RAMINIT
- bool
- default n
-
config CHROMEOS
select CHROMEOS_VBNV_CMOS
select LID_SWITCH
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 5ac8d6b..437b3cb 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
+ register "max_mem_clock_mhz" = "666"
+
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 11afd4f..a975674 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -114,7 +114,7 @@ void rcba_config(void)
RCBA32(FD) = reg32;
}
-static void copy_spd(struct pei_data *peid)
+static uint8 *locate_spd(void)
{
const int gpio_vector[] = {41, 42, 43, 10, -1};
char *spd_file;
@@ -135,10 +135,8 @@ static void copy_spd(struct pei_data *peid)
if (spd_file_len < sizeof(peid->spd_data[0]))
die("Missing SPD data.");
- memcpy(peid->spd_data[0],
- spd_file +
- spd_index * sizeof(peid->spd_data[0]),
- sizeof(peid->spd_data[0]));
+ return spd_file +
+ spd_index * sizeof(peid->spd_data[0]);
}
void mainboard_fill_pei_data(struct pei_data *pei_data)
@@ -189,7 +187,31 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
},
};
*pei_data = pei_data_template;
- copy_spd(pei_data);
+ memcpy(peid->spd_data[0],
+ locate_spd(),
+ sizeof(peid->spd_data[0]));
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* enabled power usb oc pin */
+ { 0, 0, -1 }, /* P0: Empty */
+ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
+ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */
+ { 1, 0, -1 }, /* P3: SDCARD (no OC) */
+ { 0, 0, -1 }, /* P4: Empty */
+ { 1, 0, -1 }, /* P5: WWAN (no OC) */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 1, 0, -1 }, /* P8: Camera (no OC) */
+ { 1, 0, -1 }, /* P9: Bluetooth (no OC) */
+ { 0, 0, -1 }, /* P10: Empty */
+ { 0, 0, -1 }, /* P11: Empty */
+ { 0, 0, -1 }, /* P12: Empty */
+ { 0, 0, -1 }, /* P13: Empty */
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
+ memcpy(&spd[0], locate_spd(), 128);
}
void mainboard_early_init(int s3resume)
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