[coreboot-gerrit] New patch to review for coreboot: Intel common: add microcode loading to romstage before fspmemoryinit
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Feb 11 22:19:04 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13688
-gerrit
commit 7370d5431cb3a587bb678c20c09e978209949da8
Author: robbie zhang <robbie.zhang at intel.com>
Date: Wed Feb 10 11:40:11 2016 -0800
Intel common: add microcode loading to romstage before fspmemoryinit
The intend is to seek upgraded microcode in RW section and load it
before Fsp memoryinit, to ensure any goodness in the microcode update,
especially related to memory configuration, can be applied earlier.
BUG=chrome-os-partner:50132
BRANCH=glados
TEST=Built and boot on kunimintus. Verified microcode gets reloaded.
Boot time impact is very minor.
CQ-DEPEND=CL:327170
Change-Id: I1a5df1d1efa25fb256743dca6a661c828263ec7c
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: d7f700c1876e53194748d1d1c66637b9419b7086
Original-Change-Id: I7083ec6305af9e14a57d7b0cb1bd800cd9e22f44
Original-Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327193
Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/drivers/intel/fsp1_1/romstage.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 7466575..d53712e 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -22,6 +22,7 @@
#include <boardid.h>
#include <console/console.h>
#include <cbmem.h>
+#include <cpu/intel/microcode.h>
#include <cpu/x86/mtrr.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
@@ -49,6 +50,9 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
timestamp_add_now(TS_START_ROMSTAGE);
+ /* Load microcode before ram init */
+ intel_update_microcode_from_cbfs();
+
memset(&pei_data, 0, sizeof(pei_data));
/* Display parameters */
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