[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: limit bootblock size to 32KiB

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13692

-gerrit

commit 1bad47114676c815920b7ae0863a52adeb5ecb56
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Feb 11 14:47:33 2016 -0600

    soc/intel/apollolake: limit bootblock size to 32KiB
    
    The CSE places the bootblock (IBBL in Intel parlance) below 4GiB
    at top of the address space. However, it's size is limited to
    32KiB. For now, just limit all of bootblock to 32KiB.
    
    Change-Id: I8f84138fb81027eae1712b7af3943942c35cf0ea
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/apollolake/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index dcfbad6..3212659 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_RAMSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_VERSTAGE_X86_32
+	select HAS_CUSTOM_BOOTBLOCK_SIZE
 	# CPU specific options
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select IOAPIC
@@ -75,4 +76,9 @@ config CONSOLE_UART_BASE_ADDRESS
 	hex "MMIO base address for UART"
 	default 0xde000000
 
+# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB.
+config CUSTOM_BOOTBLOCK_SIZE
+	hex
+	default 0x8000
+
 endif