[coreboot-gerrit] Patch set updated for coreboot: nb/intel/sandybridge/raminit: Add shift offset

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13682

-gerrit

commit 400bd09e11c9d227ee9dcd90cdad5fc15d3e1b5a
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Wed Feb 10 19:16:34 2016 +0100

    nb/intel/sandybridge/raminit: Add shift offset
    
    It looks like the falling timing was missing the shift offset.
    Not sure if this was intentional, I guess not.
    
    Tested on my hardware and produced no regressions.
    
    Test system:
     * Intel IvyBridge
     * Gigabyte GA-B75M-D3H
    
    Please test on real hardware !
    
    Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 4810618..97b75b6 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -1619,8 +1619,8 @@ static void program_timings(ramctr_timing * ctrl, int channel)
 			     (((ctrl->timings[channel][slotrank].lanes[lane].
 				timA + shift -
 				(post_timA_min_high << 6)) & 0x1c0) << 10)
-			     | (ctrl->timings[channel][slotrank].lanes[lane].
-				falling << 20));
+			     | ((ctrl->timings[channel][slotrank].lanes[lane].
+				falling + shift) << 20));
 
 			MCHBAR32(lane_registers[lane] + 0x20 + 0x100 * channel +
 				 4 * slotrank)