[coreboot-gerrit] Patch set updated for coreboot: x86: add coreboot table entry for TSC info
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Feb 18 22:48:43 CET 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13670
-gerrit
commit 091439b2afe388d4f56ef35987f524168b37c82e
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Feb 10 10:56:06 2016 -0600
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/arch/x86/cpu.c | 19 +++++++++++++++++++
src/commonlib/include/commonlib/coreboot_tables.h | 8 ++++++++
2 files changed, 27 insertions(+)
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 18c4e4a..cba105a 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
+#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <arch/io.h>
@@ -18,6 +19,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
+#include <cpu/x86/tsc.h>
#include <arch/cpu.h>
#include <device/path.h>
#include <device/device.h>
@@ -290,4 +292,21 @@ void cpu_initialize(unsigned int index)
void lb_arch_add_records(struct lb_header *header)
{
+ uint32_t freq_khz;
+ struct lb_tsc_info *tsc_info;
+
+ /* Don't advertise a TSC rate unless it's constant. */
+ if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ return;
+
+ freq_khz = tsc_freq_mhz() * 1000;
+
+ /* No use exposing a TSC frequency that is zero. */
+ if (freq_khz == 0)
+ return;
+
+ tsc_info = (void *)lb_new_record(header);
+ tsc_info->tag = LB_TAG_TSC_INFO;
+ tsc_info->size = sizeof(*tsc_info);
+ tsc_info->freq_khz = freq_khz;
}
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 43adb09..5c28791 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -335,6 +335,14 @@ struct lb_cbmem_entry {
uint32_t id;
};
+#define LB_TAG_TSC_INFO 0x0032
+struct lb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
More information about the coreboot-gerrit
mailing list