[coreboot-gerrit] New patch to review for coreboot: RISC-V: Make inline asm usage safer
Andrew Waterman (aswaterman@gmail.com)
gerrit at coreboot.org
Fri Feb 19 01:09:36 CET 2016
Andrew Waterman (aswaterman at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13735
-gerrit
commit a0e5a158140b4896c0feb825a6f8afe5021cf59f
Author: Andrew Waterman <waterman at cs.berkeley.edu>
Date: Thu Feb 18 16:06:21 2016 -0800
RISC-V: Make inline asm usage safer
Change-Id: Id547c98e876e9fd64fa4d12239a2608bfd2495d2
Signed-off-by: Andrew Waterman <aswaterman at gmail.com>
---
src/arch/riscv/trap_handler.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 16b66d8..53bcbf9 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -84,20 +84,18 @@ void handle_supervisor_call(trapframe *tf) {
void trap_handler(trapframe *tf) {
write_csr(mscratch, tf);
- int cause = 0;
- void* epc = 0;
- void* badAddr = 0;
+ uintptr_t cause;
+ void *epc;
+ void *badAddr;
// extract cause
- asm("csrr t0, mcause");
- asm("move %0, t0" : "=r"(cause));
+ asm("csrr %0, mcause" : "=r"(cause));
// extract faulting Instruction pc
epc = (void*) tf->epc;
// extract bad address
- asm("csrr t0, mbadaddr");
- asm("move %0, t0" : "=r"(badAddr));
+ asm("csrr %0, mbadaddr" : "=r"(badAddr));
switch(cause) {
case 0:
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