[coreboot-gerrit] New patch to review for coreboot: mainboard/google/chell: provide configuration for all pads
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Feb 26 23:48:35 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13831
-gerrit
commit 06e746b85b0715be660181bd0f8cadab3bcbe25a
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Feb 17 13:24:42 2016 -0600
mainboard/google/chell: provide configuration for all pads
Instead of relying on power-on-reset values provide configuration
for all pads. PAD_CFG_NC() was used for all pads which had no nets
routed on the board. PAD_CFG_GPO(0) was used for pads which had nets
routed on the board in order to terminate them.
BUG=chrome-os-partner:50301
BRANCH=glados
TEST=Built and booted chell. Suspended and resumed on EVT.
Change-Id: I7960442d5c06f58a1b671cdefac71ef0bc3b0cd5
Signed-off-by: Patrick Georgi <pgeorgi at google.com>
Original-Commit-Id: 6a167cd0a747402bfc3cc9b6fbaaceceda766ee9
Original-Change-Id: I519011b049235dc2a960939c0bed274252dbffa8
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327835
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
src/mainboard/google/chell/gpio.h | 162 +++++++++++++++++++-------------------
1 file changed, 81 insertions(+), 81 deletions(-)
diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h
index f9374d1..01b4e31 100644
--- a/src/mainboard/google/chell/gpio.h
+++ b/src/mainboard/google/chell/gpio.h
@@ -66,58 +66,58 @@ static const struct pad_config gpio_table[] = {
/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PIRQA# */ /* GPP_A7 */
+/* PIRQA# */ PAD_CFG_NC(GPP_A7),
/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
-/* CLKOUT_LPC1 */ /* GPP_A10 */
-/* PME# */ /* GPP_A11 */
-/* BM_BUSY# */ /* GPP_A12 */
+/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
+/* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP),
+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-/* SUS_STAT# */ /* GPP_A14 */
+/* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP),
/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
-/* SD_1P8_SEL */ /* GPP_A16 */
-/* SD_PWR_EN# */ /* GPP_A17 */
-/* ISH_GP0 */ /* GPP_A18 */
-/* ISH_GP1 */ /* GPP_A19 */
-/* ISH_GP2 */ /* GPP_A20 */
-/* ISH_GP3 */ /* GPP_A21 */
-/* ISH_GP4 */ /* GPP_A22 */
-/* ISH_GP5 */ /* GPP_A23 */
-/* CORE_VID0 */ /* GPP_B0 */
-/* CORE_VID1 */ /* GPP_B1 */
-/* VRALERT# */ /* GPP_B2 */
+/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
+/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17),
+/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
+/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
+/* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP),
+/* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP),
+/* VRALERT# */ PAD_CFG_NC(GPP_B2),
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */
-/* CPU_GP3 */ /* GPP_B4 */
+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */
-/* SRCCLKREQ3# */ /* GPP_B8 */
-/* SRCCLKREQ4# */ /* GPP_B9 */
-/* SRCCLKREQ5# */ /* GPP_B10 */
-/* EXT_PWR_GATE# */ /* GPP_B11 */
+/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
+/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
+/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
+/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* SPKR */ /* GPP_B14 */
-/* GSPI0_CS# */ /* GPP_B15 */
+/* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP),
+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */
-/* GSPI0_MISO */ /* GPP_B17 */
-/* GSPI0_MOSI */ /* GPP_B18 */
-/* GSPI1_CS# */ /* GPP_B19 */
-/* GSPI1_CLK */ /* GPP_B20 */
-/* GSPI1_MISO */ /* GPP_B21 */
-/* GSPI1_MOSI */ /* GPP_B22 */
+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP),
+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
+/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
+/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
+/* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP),
/* SM1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
-/* SMBALERT# */ /* GPP_C2 */
+/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */
/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */
/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */
/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */
-/* UART0_RXD */ /* GPP_C8 */
-/* UART0_TXD */ /* GPP_C9 */
-/* UART0_RTS# */ /* GPP_C10 */
+/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
+/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
+/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
@@ -131,39 +131,39 @@ static const struct pad_config gpio_table[] = {
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
-/* SPI1_CS# */ /* GPP_D0 */
-/* SPI1_CLK */ /* GPP_D1 */
-/* SPI1_MISO */ /* GPP_D2 */
-/* SPI1_MOSI */ /* GPP_D3 */
-/* FASHTRIG */ /* GPP_D4 */
+/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP),
+/* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP),
+/* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP),
+/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP),
+/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
-/* ISH_I2C1_SDA */ /* GPP_D7 */
-/* ISH_I2C1_SCL */ /* GPP_D8 */
-/* ISH_SPI_CS# */ /* GPP_D9 */
+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
+/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9),
/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */
-/* ISH_SPI_MISO */ /* GPP_D11 */
+/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11),
/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
-/* ISH_UART0_RXD */ /* GPP_D13 */
-/* ISH_UART0_TXD */ /* GPP_D14 */
-/* ISH_UART0_RTS# */ /* GPP_D15 */
-/* ISH_UART0_CTS# */ /* GPP_D16 */
-/* DMIC_CLK1 */ /* GPP_D17 */
-/* DMIC_DATA1 */ /* GPP_D18 */
+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
+/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
+/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-/* SPI1_IO2 */ /* GPP_D21 */
+/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP),
/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */
-/* SATAXPCIE1 */ /* GPP_E1 */
-/* SATAXPCIE2 */ /* GPP_E2 */
-/* CPU_GP0 */ /* GPP_E3 */
-/* SATA_DEVSLP0 */ /* GPP_E4 */
-/* SATA_DEVSLP1 */ /* GPP_E5 */
-/* SATA_DEVSLP2 */ /* GPP_E6 */
+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
+/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
+/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */
-/* SATALED# */ /* GPP_E8 */
+/* SATALED# */ PAD_CFG_NC(GPP_E8),
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */
/* USB2_OC1# */ /* GPP_E10 */
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */
@@ -173,12 +173,12 @@ static const struct pad_config gpio_table[] = {
/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */
/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */ /* GPP_E18 */
-/* DDPB_CTRLDATA */ /* GPP_E19 */
-/* DDPC_CTRLCLK */ /* GPP_E20 */
-/* DDPC_CTRLDATA */ /* GPP_E21 */
-/* DDPD_CTRLCLK */ /* GPP_E22 */
-/* DDPD_CTRLDATA */ /* GPP_E23 */
+/* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP),
+/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */
+/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
+/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */
+/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
+/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
/*
* The next 4 pads are for bit banging the amplifiers. They are connected
* together with i2s0 signals. For default behavior of i2s make these
@@ -188,14 +188,14 @@ static const struct pad_config gpio_table[] = {
/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
-/* I2C2_SDA */ /* GPP_F4 */
-/* I2C2_SCL */ /* GPP_F5 */
-/* I2C3_SDA */ /* GPP_F6 */
-/* I2C3_SCL */ /* GPP_F7 */
+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */
/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */
/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */
-/* I2C5_SCL */ /* GPP_F11 */
+/* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP),
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
@@ -207,27 +207,27 @@ static const struct pad_config gpio_table[] = {
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-/* RSVD */ /* GPP_F23 */
-/* SD_CMD */ /* GPP_G0 */
-/* SD_DATA0 */ /* GPP_G1 */
-/* SD_DATA1 */ /* GPP_G2 */
-/* SD_DATA2 */ /* GPP_G3 */
-/* SD_DATA3 */ /* GPP_G4 */
-/* SD_CD# */ /* GPP_G5 */
-/* SD_CLK */ /* GPP_G6 */
-/* SD_WP */ /* GPP_G7 */
+/* RSVD */ PAD_CFG_NC(GPP_F23),
+/* SD_CMD */ PAD_CFG_NC(GPP_G0),
+/* SD_DATA0 */ PAD_CFG_NC(GPP_G1),
+/* SD_DATA1 */ PAD_CFG_NC(GPP_G2),
+/* SD_DATA2 */ PAD_CFG_NC(GPP_G3),
+/* SD_DATA3 */ PAD_CFG_NC(GPP_G4),
+/* SD_CD# */ PAD_CFG_NC(GPP_G5),
+/* SD_CLK */ PAD_CFG_NC(GPP_G6),
+/* SD_WP */ PAD_CFG_NC(GPP_G7),
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
-/* SLP_A# */ /* GPD6 */
-/* RSVD */ /* GPD7 */
+/* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP),
+/* RSVD */ PAD_CFG_NC(GPD7),
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-/* SLP_WLAN# */ /* GPD9 */
-/* SLP_S5# */ /* GPD10 */
-/* LANPHYC */ /* GPD11 */
+/* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP),
+/* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP),
+/* LANPHYC */ PAD_CFG_NC(GPD11),
};
/* Early pad configuration in romstage. */
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