[coreboot-gerrit] New patch to review for coreboot: Skylake boards: Enabling HWP

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13843

-gerrit

commit 3eae1fdd1f1db2f4b7090f424fbb858cca699d00
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Mon Feb 8 17:19:10 2016 +0530

    Skylake boards: Enabling HWP
    
    This patch provides config options to enable/disable Intel SST.
    
    BUG=chrome-os-partner:47517
    BRANCH=None
    TEST=Booted kunimitsu/lars, verified HWP driver load successfully.
    
    CQ-DEPEND=CL:313107
    
    Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e
    Signed-off-by: Patrick Georgi <pgeorgi at google.com>
    Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d
    Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f
    Original-Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/326650
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Benson Leung <bleung at chromium.org>
---
 src/mainboard/google/chell/devicetree.cb    | 3 +++
 src/mainboard/google/glados/devicetree.cb   | 3 +++
 src/mainboard/google/lars/devicetree.cb     | 3 +++
 src/mainboard/intel/kunimitsu/devicetree.cb | 3 +++
 4 files changed, 12 insertions(+)

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index ac3a5c1..bb925ce 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -16,6 +16,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 894f0e1..89fcff8 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -16,6 +16,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index cf3649a..50b3e1e 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -15,6 +15,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index d2a70c8..62a0c26 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -15,6 +15,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable DPTF
 	register "dptf_enable" = "1"