SDRAM row page size wierdness
Richard Smith
rsmith at bitworks.com
Mon Apr 21 21:19:01 CEST 2003
Richard Smith wrote:
Ok... I got the page size detection worked out. I'm still confused but
at least it works.
Going back over the original 440BX code I noticed that it used the
number of _column_ address rather than the number of row adresses. At
first I thought this was a typo (spd loc 4 rather than 3). This was
further reenforced by the 440gx code and Eriks general code which use
the number of row adress bits.
Sounds logical... The number of row adress bits indicating row page size
but...
After testing several DIMMs using the row address bits failed in about
50% of the cases so I started looking back at the column address bits.
I don't understand why but if you use the number of column address bits
as a index for what page size to use it works great.
Basically just subtract 8 from the value to shift it down to zero.
8 column bits = 2k page
9 = 4k
10 = 8k
The 440bx dosen't do beyond 8k pages.
I tested as many different DIMMs as I could find here and they all work.
Any ideas on why this would be the case?
--
Richard A. Smith
rsmith at bitworks.com
More information about the coreboot
mailing list