From stepan at suse.de  Tue Jul  1 02:36:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Jul  1 02:36:00 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
Message-ID: <20030701064304.GB4896@suse.de>

* ron minnich <rminnich at lanl.gov> [030630 17:22]:
> sourceforge is really having trouble nowadays. Half my browsers think the 
> web pages are to be downloaded for some reason; cvs updates are seeing 
> 24-hour delays; and random outages are a daily occurence. 

Worst I saw was about a week of delay on the freebios2 tree.

> Any comments or objections to me at least looking into a move to 
> bitkeeper.com? It has lots of advantages, not the least that it supports 
> distributed repositories. 
> 
> Anyone have anything to say about this, pro or con?

There are quite some versioning systems that could be used instead of
CVS. I've been testing tla (Tom Lords Arch) for the openbios core i am
developing. It's relatively new, but promising (knows transactions,
renaming and deletion of files and directories etc)
Aegis otoh sets up on cvs (iirc) and gives additional checkin security
(4 eyes principle for checkins to the stable tree, automatic testsuites
and others)
subversion (svn) is probably the closest to cvs when it comes down to
usage (most cvs commands are available in svn, so developers don't have
to recalibrate on the new system).

Another thing is moving the source tree away from Sourceforge. In that
regard it'd be possible that we move the tree to the openbios cvs server
as well. It was very reliable up to now and the people administrating it 
are willing to help open source firmware projects. Moving to a
versioning system other than CVS should not be a problem.

  Stefan

-- 
Architecture Team
    SuSE Linux AG


From justin at street-vision.com  Wed Jul  2 14:24:00 2003
From: justin at street-vision.com (Justin Cormack)
Date: Wed Jul  2 14:24:00 2003
Subject: NC-670
Message-ID: <1057170820.7193.9.camel@lotte>


Has anyone looked at doing a port for the NC-670?

http://www.netcomipc.com.tw/02Embedded/htm/NC670.htm

it is an embedded VIA Eden platform with some advantages over the
consumer EPIA model, eg hardware watchdog, runs off 5V only, has CF
socket, 4 serial ports etc. I will have a look at it when I get some
more, and some more time.

lspci:

00:00.0 Host bridge: VIA Technologies, Inc. VT8605 [ProSavage PM133]
00:01.0 PCI bridge: VIA Technologies, Inc. VT8605 [PM133 AGP]
00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South]
(rev 40)
00:07.1 IDE interface: VIA Technologies, Inc. VT82C586B PIPC Bus Master
IDE (rev 06)
00:07.2 USB Controller: VIA Technologies, Inc. USB (rev 1a)
00:07.3 USB Controller: VIA Technologies, Inc. USB (rev 1a)
00:07.4 Bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev
40)
00:07.5 Multimedia audio controller: VIA Technologies, Inc. VT82C686
AC97 Audio
Controller (rev 50)
00:0f.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100]
(rev 08)
01:00.0 VGA compatible controller: S3 Inc. VT8603 [ProSavage PN133]
AGP4X VGA Controller (Twister) (rev 02)


lspci -vv
00:00.0 Host bridge: VIA Technologies, Inc. VT8605 [ProSavage PM133]
        Subsystem: VIA Technologies, Inc. VT8605 [ProSavage PM133]
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
        Latency: 0
        Region 0: Memory at e8000000 (32-bit, prefetchable) [size=64M]
        Capabilities: [a0] AGP version 2.0
                Status: RQ=31 SBA+ 64bit- FW- Rate=x1,x2,x4
                Command: RQ=0 SBA- AGP- 64bit- FW- Rate=<none>
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:01.0 PCI bridge: VIA Technologies, Inc. VT8605 [PM133 AGP] (prog-if
00 [Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
        Latency: 0
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
        Memory behind bridge: ec000000-ec0fffff
        Prefetchable memory behind bridge: e0000000-e7ffffff
        BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B-
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South]
(rev 40)
        Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping+ SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.1 IDE interface: VIA Technologies, Inc. VT82C586B PIPC Bus Master
IDE (rev 06) (prog-if 8a [Master SecP PriP])
        Subsystem: VIA Technologies, Inc. VT82C586B PIPC Bus Master IDE
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32
        Region 4: I/O ports at d000 [size=16]
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.2 USB Controller: VIA Technologies, Inc. USB (rev 1a) (prog-if 00
[UHCI])
        Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32, cache line size 08
        Interrupt: pin D routed to IRQ 9
        Region 4: I/O ports at d400 [size=32]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.3 USB Controller: VIA Technologies, Inc. USB (rev 1a) (prog-if 00
[UHCI])
        Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32, cache line size 08
        Interrupt: pin D routed to IRQ 9
        Region 4: I/O ports at d800 [size=32]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.4 Bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev
40)
        Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI]
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Interrupt: pin ? routed to IRQ 11
        Capabilities: [68] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.5 Multimedia audio controller: VIA Technologies, Inc. VT82C686
AC97 Audio
Controller (rev 50)
        Subsystem: VIA Technologies, Inc. VT82C686 AC97 Audio Controller
        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Interrupt: pin C routed to IRQ 11
        Region 0: I/O ports at dc00 [size=256]
        Region 1: I/O ports at e000 [size=4]
        Region 2: I/O ports at e400 [size=4]
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0f.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100]
(rev 08)
        Subsystem: Intel Corp. EtherExpress PRO/100+ Server Adapter
(PILA8470B)
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 (2000ns min, 14000ns max), cache line size 08
        Interrupt: pin A routed to IRQ 11
        Region 0: Memory at ec300000 (32-bit, non-prefetchable)
[size=4K]
        Region 1: I/O ports at e800 [size=64]
        Region 2: Memory at ec100000 (32-bit, non-prefetchable)
[size=1M]
        Expansion ROM at <unassigned> [disabled] [size=1M]
        Capabilities: [dc] Power Management version 2
                Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=2 PME-

01:00.0 VGA compatible controller: S3 Inc. VT8603 [ProSavage PN133]
AGP4X VGA Controller (Twister) (rev 02) (prog-if 00 [VGA])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 (1000ns min, 63750ns max), cache line size 08
        Interrupt: pin A routed to IRQ 12
        Region 0: Memory at ec000000 (32-bit, non-prefetchable)
[size=512K]
        Region 1: Memory at e0000000 (32-bit, prefetchable) [size=128M]
        Expansion ROM at <unassigned> [disabled] [size=64K]
        Capabilities: [dc] Power Management version 2
                Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [80] AGP version 2.0
                Status: RQ=31 SBA- 64bit- FW- Rate=x4
                Command: RQ=0 SBA- AGP- 64bit- FW- Rate=x4





From joshua at joshuawise.com  Wed Jul  2 14:45:01 2003
From: joshua at joshuawise.com (Joshua Wise)
Date: Wed Jul  2 14:45:01 2003
Subject: What information would I need?
Message-ID: <200307021453.37781.joshua@joshuawise.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Assuming I wanted to do a port to the ABIT KG7-RAID, what information would I 
need? I have experience writing bootloader-type things from working on an ARM 
bootloader.

~joshua

- -- 
Joshua Wise | www.joshuawise.com
GPG Key     | 0xEA80E0B3
Quote       | <lilo> I akilled *@* by mistake
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.1 (GNU/Linux)

iD8DBQE/AyoxPn9tWOqA4LMRAo/LAJ98iK1mtwHzLgofgqsaQxbK7tJK8QCfZrTB
Z8F1B4VStGJB1pZIbHjoI5A=
=Z0n6
-----END PGP SIGNATURE-----



From aip at cwlinux.com  Wed Jul  2 20:18:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Wed Jul  2 20:18:00 2003
Subject: NC-670
In-Reply-To: <1057170820.7193.9.camel@lotte>; from Justin Cormack on Wed, Jul 02, 2003 at 07:33:39PM +0100
References: <1057170820.7193.9.camel@lotte>
Message-ID: <20030703082657.A23924@mail.cwlinux.com>

Justin,

> Has anyone looked at doing a port for the NC-670?
> http://www.netcomipc.com.tw/02Embedded/htm/NC670.htm
> it is an embedded VIA Eden platform with some advantages over the
> consumer EPIA model, eg hardware watchdog, runs off 5V only, has CF
> socket, 4 serial ports etc. I will have a look at it when I get some
> more, and some more time.
> 00:00.0 Host bridge: VIA Technologies, Inc. VT8605 [ProSavage PM133]
> 00:01.0 PCI bridge: VIA Technologies, Inc. VT8605 [PM133 AGP]
> 00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South]
> (rev 40)
AFAIK, vt8605 is not supported yet, but vt82c686 is already in the tree.
I think vt8605 is similar to vt8601(EPIA) with different display unit.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From YhLu at tyan.com  Wed Jul  2 20:50:01 2003
From: YhLu at tyan.com (YhLu)
Date: Wed Jul  2 20:50:01 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
Message-ID: <3174569B9743D511922F00A0C943142302DD09EF@TYANWEB>

Eric,

Thanks for the Info, I can get two cpus running now. but it die in Kernel.

Ron,
I use 2.4.21 kernel and it died on 
CPU 0: Machine Check Exception: 0000000000000007
Bank 3: b40000000000083b at 000000fdfc000cfe
Kernel panic: Unable to continue

Any advise.

Regards

Yinghai Lu


LinuxBIOS-1.1.02.0Fallback Thu Jul 3 00:33:17 EDT 2003 starting...

LinuxBIOS-1.1.02.0Fallback Thu Jul 3 00:33:17 EDT 2003 starting...
apic_id: 00000000
Bootstrap cpu
setting up resource map....
done.
setting up coherent ht domain....
done.
PCI: 00:01.00
PCI: 00:01.01
PCI: 00:02.00
PCI: 00:02.01
PCI: 00:03.00
PCI: 00:04.00
PCI: 00:04.01
PCI: 00:04.02
PCI: 00:04.03
PCI: 00:04.05
PCI: 00:04.06
PCI: 00:18.00
PCI: 00:18.01
PCI: 00:18.02
PCI: 00:18.03
PCI: 00:19.00
PCI: 00:19.01
PCI: 00:19.02
PCI: 00:19.03
SMBus controller enabled
Ram1
setting up CPU0 northbridge registers
done.
setting up CPU1 northbridge registers
done.
Ram2
RAM: 0x00180000 KB
Ram3
dcl: 08018000
Initializing memory:  done
dcl: 08018000
Initializing memory:  done
Ram4
Ram5
Ram6


LinuxBIOS-1.1.02.0Fallback Thu Jul 3 00:33:17 EDT 2003 starting...


LinuxBIOS-1.1.02.0Fallback Thu Jul 3 00:33:17 EDT 2003 starting...
apic_id: 00000001
Application processor
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
LinuxBIOS-1.1.02.0Fallback Thu Jul 3 00:33:17 EDT 2003 booting...
Finding PCI configuration type.
PCI: Using configuration type 1
Enumerating buses...PCI: pci_scan_bus for bus 0
PCI: 00:01.0 [1022/7450]
PCI: 00:01.1 [1022/7451]
PCI: 00:02.0 [1022/7450]
PCI: 00:02.1 [1022/7451]
PCI: 00:03.0 [1022/7460]
PCI: 00:04.0 [1022/7468] ops
PCI: 00:04.0 [1022/7468]
PCI: 00:04.1 [1022/7469] ops
PCI: 00:04.1 [1022/7469]
PCI: 00:04.2 [1022/746a]
PCI: 00:04.3 [1022/746b] ops
PCI: 00:04.3 [1022/746b]
PCI: 00:04.5 [1022/746d]
PCI: 00:04.6 [1022/746e]
PCI: 00:18.0 [1022/1100]
PCI: 00:18.1 [1022/1101]
PCI: 00:18.2 [1022/1102]
PCI: 00:18.3 [1022/1103]
PCI: 00:19.0 [1022/1100]
PCI: 00:19.1 [1022/1101]
PCI: 00:19.2 [1022/1102]
PCI: 00:19.3 [1022/1103]
PCI: pci_scan_bus for bus 1
PCI: 01:09.0 [14e4/1648]
PCI: 01:09.1 [14e4/1648]
PCI: 01:0a.0 [1000/0030]
PCI: 01:0a.1 [1000/0030]
PCI: pci_scan_bus returning with max=01
PCI: pci_scan_bus for bus 2
PCI: pci_scan_bus returning with max=02
PCI: pci_scan_bus for bus 3
PCI: 03:00.0 [1022/7464] ops
PCI: 03:00.0 [1022/7464]
PCI: 03:00.1 [1022/7464] ops
PCI: 03:00.1 [1022/7464]
PCI: 03:00.2 [1022/7463]
PCI: 03:01.0 [1022/7462]
PCI: 03:05.0 [105a/3373]
PCI: 03:06.0 [1002/4752]
PCI: pci_scan_bus returning with max=03
PCI: pci_scan_bus returning with max=03
done
Allocating resources...
ASSIGN RESOURCES, bus 0
PCI: 00:01.0 1c <- [0x00001000 - 0x00001fff] bus 1 io
PCI: 00:01.0 24 <- [0xfe200000 - 0xfe1fffff] bus 1 prefmem
PCI: 00:01.0 20 <- [0xfe100000 - 0xfe1fffff] bus 1 mem
ASSIGN RESOURCES, bus 1
PCI: 01:09.0 10 <- [0xfe100000 - 0xfe10ffff] mem
PCI: 01:09.0 18 <- [0xfe110000 - 0xfe11ffff] mem
PCI: 01:09.1 10 <- [0xfe120000 - 0xfe12ffff] mem
PCI: 01:09.1 18 <- [0xfe130000 - 0xfe13ffff] mem
PCI: 01:0a.0 10 <- [0x00001000 - 0x000010ff] io
PCI: 01:0a.0 14 <- [0xfe140000 - 0xfe14ffff] mem
PCI: 01:0a.0 1c <- [0xfe150000 - 0xfe15ffff] mem
PCI: 01:0a.1 10 <- [0x00001400 - 0x000014ff] io
PCI: 01:0a.1 14 <- [0xfe160000 - 0xfe16ffff] mem
PCI: 01:0a.1 1c <- [0xfe170000 - 0xfe17ffff] mem
ASSIGNED RESOURCES, bus 1
PCI: 00:02.0 1c <- [0x00003000 - 0x00002fff] bus 2 io
PCI: 00:02.0 24 <- [0xfe200000 - 0xfe1fffff] bus 2 prefmem
PCI: 00:02.0 20 <- [0xfe200000 - 0xfe1fffff] bus 2 mem
PCI: 00:03.0 1c <- [0x00002000 - 0x00002fff] bus 3 io
PCI: 00:03.0 24 <- [0xfe200000 - 0xfe1fffff] bus 3 prefmem
PCI: 00:03.0 20 <- [0xfd000000 - 0xfe0fffff] bus 3 mem
ASSIGN RESOURCES, bus 3
PCI: 03:00.0 10 <- [0xfe020000 - 0xfe020fff] mem
PCI: 03:00.1 10 <- [0xfe021000 - 0xfe021fff] mem
PCI: 03:00.2 10 <- [0xfe025000 - 0xfe0250ff] mem
PCI: 03:00.2 14 <- [0xfe026000 - 0xfe02601f] mem
PCI: 03:01.0 10 <- [0xfe022000 - 0xfe022fff] mem
PCI: 03:05.0 10 <- [0x00002480 - 0x000024bf] io
PCI: 03:05.0 14 <- [0x000024c0 - 0x000024cf] io
PCI: 03:05.0 18 <- [0x00002400 - 0x0000247f] io
PCI: 03:05.0 1c <- [0xfe023000 - 0xfe023fff] mem
PCI: 03:05.0 20 <- [0xfe000000 - 0xfe01ffff] mem
PCI: 03:06.0 10 <- [0xfd000000 - 0xfdffffff] mem
PCI: 03:06.0 14 <- [0x00002000 - 0x000020ff] io
PCI: 03:06.0 18 <- [0xfe024000 - 0xfe024fff] mem
ASSIGNED RESOURCES, bus 3
PCI: 00:04.1 20 <- [0x000038e0 - 0x000038ef] io
PCI: 00:04.2 10 <- [0x000038c0 - 0x000038df] io
PCI: 00:04.5 10 <- [0x00003000 - 0x000030ff] io
PCI: 00:04.5 14 <- [0x00003880 - 0x000038bf] io
PCI: 00:04.6 10 <- [0x00003400 - 0x000034ff] io
PCI: 00:04.6 14 <- [0x00003800 - 0x0000387f] io
ASSIGNED RESOURCES, bus 0
Allocating VGA resource
done.
Enabling resourcess...DEV: 00:01.0 cmd <- 07
DEV: 00:01.1 cmd <- 00
DEV: 00:02.0 cmd <- 07
DEV: 00:02.1 cmd <- 00
DEV: 00:03.0 cmd <- 07
DEV: 00:04.0 cmd <- 0f
DEV: 00:04.1 cmd <- 01
DEV: 00:04.2 cmd <- 01
DEV: 00:04.3 cmd <- 00
DEV: 00:04.5 cmd <- 01
DEV: 00:04.6 cmd <- 01
DEV: 00:18.0 cmd <- 00
DEV: 00:18.1 cmd <- 00
DEV: 00:18.2 cmd <- 00
DEV: 00:18.3 cmd <- 00
DEV: 00:19.0 cmd <- 00
DEV: 00:19.1 cmd <- 00
DEV: 00:19.2 cmd <- 00
DEV: 00:19.3 cmd <- 00
DEV: 01:09.0 cmd <- 02
DEV: 01:09.1 cmd <- 02
DEV: 01:0a.0 cmd <- 03
DEV: 01:0a.1 cmd <- 03
DEV: 03:00.0 cmd <- 02
DEV: 03:00.1 cmd <- 02
DEV: 03:00.2 cmd <- 02
DEV: 03:01.0 cmd <- 02
DEV: 03:05.0 cmd <- 03
DEV: 03:06.0 cmd <- 83
done.
Initializing devices...
PCI: 00:04.0 init
lpc_init
PCI: 00:04.1 init
ide_init
IDE1 IDE0 PCI: 00:04.3 init
PCI: 03:00.0 init
USB: Setting up controller.. done.
PCI: 03:00.1 init
USB: Setting up controller.. done.
Devices initialized
totalram: 1536M
Initializing CPU #0
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) type: WB
Setting fixed MTRRs(72-88) type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 1024MB, type WB
Setting variable MTRR 1, base: 1024MB, range:  512MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
call intel_enable_fixed_mtrr()
call intel_enable_var_mtrr()
Leave setup_mtrrs
done.

Max cpuid index    : 1
Vendor ID          : AuthenticAMD
Processor Type     : 0x00
Processor Family   : 0x0f
Processor Model    : 0x05
Processor Mask     : 0x00
Processor Stepping : 0x08
Feature flags      : 0x078bfbff


MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0 done.
CPU #0 Initialized
clocks_per_usec: 1793
secondary_cpu_init
Waiting for 2 CPUS to stop
Initializing CPU #1
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) type: WB
Setting fixed MTRRs(72-88) type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 1024MB, type WB
Setting variable MTRR 1, base: 1024MB, range:  512MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
call intel_enable_fixed_mtrr()
call intel_enable_var_mtrr()
Leave setup_mtrrs
done.

Max cpuid index    : 1
Vendor ID          : AuthenticAMD
Processor Type     : 0x00
Processor Family   : 0x0f
Processor Model    : 0x05
Processor Mask     : 0x00
Processor Stepping : 0x08
Feature flags      : 0x078bfbff


MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 16777216 done.
CPU #1 Initialized
secondary_cpu_init  1/1
All AP CPUs stopped
Checking IRQ routing tables...
/root/xx/xx/freebios2/src/arch/i386/boot/pirq_routing.c:
29:check_pirq_routin
g_table() - irq_routing_table located at: 0x0000a140
done.
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...succeed
Wrote the mp table end at: 00000020 - 0000014c
Wrote linuxbios table at: 00000500 - 00000b08  checksum 707a

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

Found ELF candiate at offset 0
Loading Etherboot version: 5.1.8
Dropping non PT_LOAD segment
New segment addr 0x20000 size 0x34718 offset 0xb0 filesize 0x56d6
(cleaned up) New segment addr 0x20000 size 0x34718 offset 0xb0 filesize
0x56d6
Loading Segment: addr: 0x0000000000020000 memsz: 0x0000000000034718 filesz:
0x00
000000000056d6
Clearing Segment: addr: 0x00000000000256d6 memsz: 0x000000000002f042
Jumping to boot code at 0x20000
ROM segment 0x33cc length 0x9866 reloc 0x00020000
CPU 1857 Mhz
Etherboot 5.1.8 (GPL) Tagged ELF (Multiboot) for [TG3]
Relocating _text from: [000256e0,00054d50) to [5ffd0990,60000000)
Probing pci nic...
[TG3]Cannot find PowerManagement capability, aborting.
[TG3]Ethernet addr: 00:E0:81:F0:18:CD
Tigon3 [partno(BCM95704A7) rev 2002 PHY(5704)] (PCIX:100MHz:64-bit)
Link is up at 100 Mbps, half duplex.
Searching for server (DHCP)...
..Me: 192.168.1.198, Server: 192.168.1.1, Gateway 192.168.1.1
Loading 192.168.1.1:ram0_2.5_2.4.21_k8_lsi_mydisk4.elf ...(ELF)...
.............
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
.................................................done
Firmware type: LinuxBIOS
Linux version 2.4.21 (root at tst2723_rh9) (gcc version 3.2.2 20030222 (Red Hat
Lin
ux 3.2.2-5)) #13 SMP Tue Jul 1 21:09:41 EDT 2003
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 0000000000000b68 (reserved)
 BIOS-e820: 0000000000000b68 - 00000000000a0000 (usable)
 BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
 BIOS-e820: 0000000000100000 - 0000000060000000 (usable)
640MB HIGHMEM available.
896MB LOWMEM available.
hm, page 00000000 reserved twice.
found SMP MP-table at 00000010
hm, page 00000000 reserved twice.
hm, page 00001000 reserved twice.
hm, page 00000000 reserved twice.
hm, page 00001000 reserved twice.
On node 0 totalpages: 393216
zone(0): 4096 pages.
zone(1): 225280 pages.
zone(2): 163840 pages.
Intel MultiProcessor Specification v1.4
    Virtual Wire compatibility mode.
OEM ID: TYAN     Product ID: S2880        APIC at: 0xFEE00000
Processor #0 Unknown CPU [15:5] APIC version 16
Processor #1 Unknown CPU [15:5] APIC version 16
I/O APIC #2 Version 17 at 0xFEC00000.
Enabling APIC mode: Flat.       Using 1 I/O APICs
Processors: 2
Kernel command line: root=/dev/ram0 rw ram0_2.5_2.4.21_k8_lsi_mydisk4.elf
-retad
dr 0X5FFD0B34
Initializing CPU#0
Detected 1792.125 MHz processor.
Calibrating delay loop... 3565.15 BogoMIPS
Memory: 1547448k/1572864k available (1493k kernel code, 25028k reserved,
323k da
ta, 284k init, 655360k highmem)
Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
Inode cache hash table entries: 131072 (order: 8, 1048576 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer-cache hash table entries: 131072 (order: 7, 524288 bytes)
Page-cache hash table entries: 524288 (order: 9, 2097152 bytes)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
mtrr: v1.40 (20010327) Richard Gooch (rgooch at atnf.csiro.au)
mtrr: detected mtrr type: Intel
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
Intel machine check reporting enabled on CPU#0.
CPU0: AMD 02/05 stepping 08
per-CPU timeslice cutoff: 2925.71 usecs.
enabled ExtINT on CPU#0
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
Booting processor 1/1 eip 2000
Initializing CPU#1
masked ExtINT on CPU#1
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
Calibrating delay loop... 3578.26 BogoMIPS
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
Intel machine check reporting enabled on CPU#1.
CPU1: AMD 02/05 stepping 08
Total of 2 processors activated (7143.42 BogoMIPS).
ENABLING IO-APIC IRQs
Setting 2 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 2 ... ok.
..TIMER: vector=0x31 pin1=2 pin2=0
testing the IO APIC.......................

.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1792.0936 MHz.
..... host bus clock speed is 199.1214 MHz.
cpu: 0, clocks: 1991214, slice: 663738
CPU0<T0:1991200,T1:1327456,D:6,S:663738,C:1991214>
cpu: 1, clocks: 1991214, slice: 663738
CPU1<T0:1991200,T1:663712,D:12,S:663738,C:1991214>
checking TSC synchronization across CPUs: passed.
Waiting on wait_init_idle (map = 0x2)
All processors have done init_idle
CPU 0: Machine Check Exception: 0000000000000007
Bank 3: b40000000000083b at 000000fdfc000cfe
Kernel panic: Unable to continue


From ebiederman at lnxi.com  Wed Jul  2 22:59:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jul  2 22:59:00 2003
Subject: freebios2 anonymous checkout
In-Reply-To: <000a01c3410d$fa485310$6501a8c0@5000P4>
References: <000a01c3410d$fa485310$6501a8c0@5000P4>
Message-ID: <m3of0ce2c2.fsf@maxwell.lnxi.com>

"mitch wright" <mitch.wright at earthlink.net> writes:

> Hello Eric,
> 
> Why does cvs not let me check out the freebios2 tree with anonymous username and
> an empty password?

It looks like sourceforge is crumbling under it's current load.

> I'd really like to take a look at it.

I'd love to share.

Eric



From rminnich at lanl.gov  Wed Jul  2 23:55:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul  2 23:55:01 2003
Subject: freebios2 anonymous checkout
In-Reply-To: <m3of0ce2c2.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307022203590.23477-100000@maxroach.lanl.gov>

If this doesn't get better soon I'll probably take unilateral action and 
move it. We'll see.

ron



From hansolofalcon at worldnet.att.net  Thu Jul  3 00:08:00 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Thu Jul  3 00:08:00 2003
Subject: freebios2 anonymous checkout
In-Reply-To: <Pine.LNX.4.44.0307022203590.23477-100000@maxroach.lanl.gov>
Message-ID: <000001c3411a$079890a0$239efea9@who5>

Hello from Gregg C Levine
When did this happen, guys? When I used the steps on the site to
download the stuff in CVS, both, it worked for me. In fact, I was
surprised as to how quickly this happened. This was done, about a week
ago. Granted, Source Forge is having kittens over its current load,
it's my guess. I suggest we wait a couple more days, before you decide
to, " take unilateral action.". As to why this is happening, now, I
haven't a clew. I am tempted to contact the characters at Source Forge
and lodge a few complaints.

You, all, will notice that I used that term to describe the people at
Source Forge. So far, the only ones I've met, have been everything
we've expected. But I expect the administrators behind CVS aren't
those sorts of people.  
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of ron minnich
> Sent: Thursday, July 03, 2003 12:04 AM
> To: Eric W. Biederman
> Cc: mitch wright; LinuxBIOS
> Subject: Re: freebios2 anonymous checkout
> 
> If this doesn't get better soon I'll probably take unilateral action
and
> move it. We'll see.
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From nathanael at gnat.ca  Thu Jul  3 02:18:00 2003
From: nathanael at gnat.ca (Nathanael Noblet)
Date: Thu Jul  3 02:18:00 2003
Subject: CVS Server
Message-ID: <5EB0DE4C-AD1F-11D7-A0BD-0003931B4D6A@gnat.ca>

	I've been watching the threads about SF and the problems you are 
experiencing with it. I can say I've had a few of my own, though not 
lately. I haven't worked on my port of LinuxBIOS to my own SBC for 
awhile work and summer pulling me in all sorts of directions. In 
anycase, I have a server that I'd be willing to use to host your CVS. I 
already have a cvs server setup for my own work and could migrate the 
tree over if desired. I don't know how well this would work, but in the 
interm would work fairly well I would imagine. The server is a Dual 
PIII 1Ghz (2x1Ghz) 768MB RAM and 320 GB of space on a 4 Disk RAID 0 
array. Though the connection is only through ADSL (albeit one with good 
speed upload speed) I usually get 100K/s from my server most places 
I've been to.

	Anyway, I'd be more then happy to offer the server's resources free of 
charge (cvs & web if necessary) for however long it you need it for 
even permanently if needed. It rarely goes down (only for kernel 
updates)...

-- 
Nathanael Noblet
Gnat Solutions
4604 Monterey Ave NW
Calgary, AB
T3B 5K4

T/F 403.288.5360
C 403.809.5368

http://www.gnat.ca/



From rimy2000 at hotmail.com  Thu Jul  3 04:47:00 2003
From: rimy2000 at hotmail.com (elife elife)
Date: Thu Jul  3 04:47:00 2003
Subject: epia-m vgabios
Message-ID: <BAY2-F76p4CMxfqclwm00001904@hotmail.com>

Hi,
  I have boot linux succ with linuxbios/serial console in my epia-m. Now I 
would like add VGA support. I try testbios, but it report "int15 
encountered". What should I do? Or there are other methods to let linux's 
tty0 works?

running file epia-m.videobios.bin
No size specified. defaulting to 32k
No base specified. defaulting to 0xc0000
No initial code segment specified. defaulting to 0xc000
No initial instruction pointer specified. defaulting to 0x0003
eax=0x8 ecx=0x3 eflags=0x44

int15 encountered.
	EAX=00005f19  EBX=00000800  ECX=00000000  EDX=000003d4  
	ESP=0000ffcc  EBP=00000000  ESI=000058d8  EDI=00000044
	DS=0000  ES=0000  SS=0030  CS=c000  EIP=00004ef9
	NV UP DI NG NZ NA PE NC 

int15 encountered.
	EAX=00005f19  EBX=00000f04  ECX=00000000  EDX=000003d4  
	ESP=0000ffb4  EBP=00000000  ESI=000058d8  EDI=00000044
	DS=0000  ES=0000  SS=0030  CS=c000  EIP=000051df
	NV UP DI PL NZ NA PO NC 

int15 encountered.
	EAX=00005f19  EBX=0000f004  ECX=00000000  EDX=000003c4  
	ESP=0000ffcc  EBP=00000000  ESI=00000000  EDI=0000b1a9
	DS=0000  ES=0000  SS=0030  CS=c000  EIP=00004fcb
	NV UP DI PL NZ NA PO NC 

int15 encountered.
	EAX=00005f19  EBX=0000f004  ECX=00000000  EDX=000003d4  
	ESP=0000ffcc  EBP=00000000  ESI=00000000  EDI=0000b1a9
	DS=0000  ES=0000  SS=0030  CS=c000  EIP=00005020
	NV UP DI PL NZ NA PO NC 

int15 encountered.
	EAX=00005f0f  EBX=00000000  ECX=00000000  EDX=000003d5  
	ESP=0000fff2  EBP=00000000  ESI=00000000  EDI=00000044
	DS=0000  ES=0000  SS=0030  CS=c000  EIP=00005c98
	NV UP DI NG NZ NA PO NC 

int15 encountered.
	EAX=00005f19  EBX=00000000  ECX=00000000  EDX=000003d4  
	ESP=0000ffdc  EBP=00000000  ESI=00000000  EDI=00000044
	DS=0000  ES=0000  SS=0030  CS=c000  EIP=000051df
	NV UP DI PL NZ NA PO NC 

int15 encountered.
	EAX=00005f02  EBX=00000000  ECX=00000000  EDX=000003d4  
	ESP=0000fff2  EBP=00000000  ESI=00000000  EDI=00000044
	DS=0000  ES=0000  SS=0030  CS=c000  EIP=00005ce8
	NV UP DI PL ZR AC PE NC 
halt_sys: file ops.c, line 8583
halted

_________________________________________________________________
?????????????? MSN Messenger:  http://messenger.msn.com/cn  



From ts1 at cma.co.jp  Thu Jul  3 05:10:00 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Thu Jul  3 05:10:00 2003
Subject: epia-m vgabios
In-Reply-To: <BAY2-F76p4CMxfqclwm00001904@hotmail.com>
References: <BAY2-F76p4CMxfqclwm00001904@hotmail.com>
Message-ID: <20030703091829.GA6358@cma.co.jp>

On Thu, Jul 03, 2003 at 08:56:02AM +0000, elife elife wrote:
> Hi,
>  I have boot linux succ with linuxbios/serial console in my epia-m. Now I 
> would like add VGA support. I try testbios, but it report "int15 
> encountered". What should I do? Or there are other methods to let linux's 
> tty0 works?

To run VGABIOS inside LinuxBIOS, try config options like below, it is
successfully used to boot EPIA (non-M). I don't know about EPIA-M.

    option CONFIG_VGABIOS=1
    option CONFIG_REALMODE_IDT=1
    dir src/bioscall
    option CONFIG_PCIBIOS=1
    option VGABIOS_START=0xfffe0000
    addaction romimage dd if=../vgabios.bin of=romimage bs=65536 seek=2 conv=sync conv=notrunc

--
Takeshi


From rimy2000 at hotmail.com  Thu Jul  3 05:51:00 2003
From: rimy2000 at hotmail.com (elife elife)
Date: Thu Jul  3 05:51:00 2003
Subject: epia-m: NO VGA FOUND
Message-ID: <BAY2-F112fGdMNFmWAF00012199@hotmail.com>

Hi,

After I add in my epia-m config file,
option CONFIG_VGABIOS=1
option CONFIG_REALMODE_IDT=1
dir src/bioscall
option CONFIG_PCIBIOS=1
option VGABIOS_START=0xfffc0000
 
now lb report "NO VGA FOUND". Any hint?

Thanks a lot!




setting pci slot

4d0: 0x20

4d1: 0x1c

4d0: 0x20

4d1: 0x1c

INSTALL REAL-MODE IDT

DO THE VGA BIOS

NO VGA FOUND

Checking IRQ routing tables...

/freebios/src/arch/i386/lib/pirq_routing.c:    
29:check_pirq_routing_table() - irq_routing_table located at: 0x0000b740

done.

Copying IRQ routing tables to 0xf0000...done.

Verifing priq routing tables copy at 0xf0000...failed

Wrote linuxbios table at: 00000500 - 00000690  checksum 9f11

Jumping to linuxbiosmain()...

_________________________________________________________________
???? MSN Explorer:   http://explorer.msn.com/lccn/  



From ts1 at cma.co.jp  Thu Jul  3 06:04:00 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Thu Jul  3 06:04:00 2003
Subject: epia-m: NO VGA FOUNDg
In-Reply-To: <BAY2-F112fGdMNFmWAF00012199@hotmail.com>
References: <BAY2-F112fGdMNFmWAF00012199@hotmail.com>
Message-ID: <20030703101302.GB7506@cma.co.jp>

On Thu, Jul 03, 2003 at 09:55:51AM +0000, elife elife wrote:
> now lb report "NO VGA FOUND". Any hint?

It means LinuxBIOS has not enabled the internal VGA device.
Try option HAVE_FRAMEBUFFER=1.
If that fails, wait for a comment from Andrew.. :)

--
Takeshi


From aip at cwlinux.com  Thu Jul  3 06:33:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Thu Jul  3 06:33:01 2003
Subject: epia-m: NO VGA FOUNDg
In-Reply-To: <20030703101302.GB7506@cma.co.jp>; from SONE Takeshi on Thu, Jul 03, 2003 at 07:13:02PM +0900
References: <BAY2-F112fGdMNFmWAF00012199@hotmail.com> <20030703101302.GB7506@cma.co.jp>
Message-ID: <20030703184126.C28824@mail.cwlinux.com>

Hi,

> It means LinuxBIOS has not enabled the internal VGA device.
> Try option HAVE_FRAMEBUFFER=1.
> If that fails, wait for a comment from Andrew.. :)
I don't think the vga is enbled yet, but it is on my todo list.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Thu Jul  3 18:11:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul  3 18:11:00 2003
Subject: CVS Server
In-Reply-To: <5EB0DE4C-AD1F-11D7-A0BD-0003931B4D6A@gnat.ca>
Message-ID: <Pine.LNX.4.44.0307031618440.31670-100000@maxroach.lanl.gov>

I appreciate the offers people are making. 

If we move from sourceforge, I want it to be to an organization that is 
bigger than any single person/project and that I won't have to worry about 
for at least another 4-5 years. Bitkeeper fills the bill, as does LANL. 

Anyway let's give sourceforge another few days to get better and then 
we'll see. 

But it is being a very bad week for sourceforge, that's for sure.

ron



From rminnich at lanl.gov  Thu Jul  3 18:14:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul  3 18:14:00 2003
Subject: epia-m: NO VGA FOUND
In-Reply-To: <BAY2-F112fGdMNFmWAF00012199@hotmail.com>
Message-ID: <Pine.LNX.4.44.0307031622340.31670-100000@maxroach.lanl.gov>

On Thu, 3 Jul 2003, elife elife wrote:

> now lb report "NO VGA FOUND". Any hint?

It did not find a VGA BIOS. 

You need to put a VGA BIOS image in flash, somewhere.

ron



From rimy2000 at hotmail.com  Thu Jul  3 20:43:00 2003
From: rimy2000 at hotmail.com (elife elife)
Date: Thu Jul  3 20:43:00 2003
Subject: epim-M: NO VGA FOUND
Message-ID: <BAY2-F66UUx6EfkU9X300003c57@hotmail.com>

 I had put a VGA BIOS image in flash (offset 0 of 256K flash, and set 
option VGABIOS_START=0xfffc0000)but ld reported "NO VGA FOUND". In 
vgabios.c 

  dev = pci_find_class(PCI_CLASS_DISPLAY_VGA <<8, NULL);

  if (! dev) {
    printk_debug("NO VGA FOUND\n");
    return;
  }

Is it sth wrong related to pci?

_________________________________________________________________
???? MSN Explorer:   http://explorer.msn.com/lccn  



From ts1 at cma.co.jp  Fri Jul  4 02:16:01 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Fri Jul  4 02:16:01 2003
Subject: epim-M: NO VGA FOUND
In-Reply-To: <BAY2-F66UUx6EfkU9X300003c57@hotmail.com>
References: <BAY2-F66UUx6EfkU9X300003c57@hotmail.com>
Message-ID: <20030704062531.GA1090@cma.co.jp>

On Fri, Jul 04, 2003 at 12:52:17AM +0000, elife elife wrote:
> I had put a VGA BIOS image in flash (offset 0 of 256K flash, and set 
> option VGABIOS_START=0xfffc0000)but ld reported "NO VGA FOUND". In 
> vgabios.c 
> 
>  dev = pci_find_class(PCI_CLASS_DISPLAY_VGA <<8, NULL);
> 
>  if (! dev) {
>    printk_debug("NO VGA FOUND\n");
>    return;
>  }

I left that VGA device detection code, even if the VGA BIOS image is
loaded from flash, just to make sure.
I'm pretty sure the device must be enabled prior to start VGA BIOS,
otherwise VGA BIOS won't see the device either.

> Is it sth wrong related to pci?

If you booted Linux from PCBIOS, you see the VGA device in lspci.
But with current LinuxBIOS, you don't.
Some work is needed to enabled it.

--
Takeshi


From xpegenaute at telepolis.es  Fri Jul  4 10:09:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Fri Jul  4 10:09:00 2003
Subject: freebios2
Message-ID: <1057331453.1714.1.camel@p-133>

Hi,

i'd like to see the code for freebios2, is it possible ?

i want this because i'm doing a documentation about LinuxBios for my
thesis, i want to know how different are the both.

Thanks.
Xavi.



From rminnich at lanl.gov  Fri Jul  4 11:42:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul  4 11:42:01 2003
Subject: epim-M: NO VGA FOUND
In-Reply-To: <BAY2-F66UUx6EfkU9X300003c57@hotmail.com>
Message-ID: <Pine.LNX.4.44.0307040950350.6293-100000@maxroach.lanl.gov>

Boot normal linux and send me an lspci and an lspci -xxx

thanks

ron




From rminnich at lanl.gov  Fri Jul  4 11:49:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul  4 11:49:01 2003
Subject: freebios2
In-Reply-To: <1057331453.1714.1.camel@p-133>
Message-ID: <Pine.LNX.4.44.0307040957580.6293-100000@maxroach.lanl.gov>

On 4 Jul 2003, Xavier Pegenaute wrote:

> i want this because i'm doing a documentation about LinuxBios for my
> thesis, i want to know how different are the both.

co freebios2, not freebios, e.g.

cvs -d:pserver:anonymous at cvs.freebios.sourceforge.net:/cvsroot/freebios login 
cvs -z3 
-d:pserver:anonymous at cvs.freebios.sourceforge.net:/cvsroot/freebios co freebios2






From rminnich at lanl.gov  Fri Jul  4 11:50:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul  4 11:50:00 2003
Subject: LinuxBios for Asus TX-97
In-Reply-To: <3F05AF4E.4090800@informatik.uni-ulm.de>
Message-ID: <Pine.LNX.4.44.0307040959050.6293-100000@maxroach.lanl.gov>

On Fri, 4 Jul 2003, Jens M?ller wrote:

> Hello Ron,
> 
> on the status page on www.linuxbios.org is mentioned that linuxbios 
> works on the asus/tx97le? Does that include the TX-97? I would like to 
> find it out, but I don't like crashing my board. So maybe you can tell 
> me my chances?
> 
> Bye,
> Jens
> 

anybody know?

ron




From xpegenaute at telepolis.es  Fri Jul  4 14:03:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Fri Jul  4 14:03:01 2003
Subject: PCI
Message-ID: <1057345538.1718.10.camel@p-133>

Hi,

i'd like to know more about PIRQ and PCI en general, but the
documentation in http://www.pcisig.com/specifications is private and you
have to pay.

I have'n enough with the link
http://www.microsoft.com/whdc/hwdev/archive/BUSBIOS/pciirq.mspx

I have'nt the red PCI book.

Then any one know where i can reach more info ? i want to know also what
kind of information is showed in "lscpi". What is exactly interesting
for you abaout "lspci -x" ?

Thanks a lot.
Xavi.



From xpegenaute at telepolis.es  Sat Jul  5 08:04:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Sat Jul  5 08:04:01 2003
Subject: ADLO
Message-ID: <1057410423.574.42.camel@p-133>

Hi,

a question, may be i'm wrong, but .. Actually if we build an ADLO
system, how the binari with "loader+vga bios+pirq+bochs bios" is the
payload of LinuxBios,then we can't start a minisystem recorded in one
DoC, no?

If we want to do this is it enough with a Jump to the position of Kernel
image in a DoC ? instead of jump to the power up entry of Bochs ?

Xavi.
Thanks.



From stepan at suse.de  Sat Jul  5 09:25:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Sat Jul  5 09:25:01 2003
Subject: ADLO
In-Reply-To: <1057410423.574.42.camel@p-133>
References: <1057410423.574.42.camel@p-133>
Message-ID: <20030705133317.GA31258@suse.de>

* Xavier Pegenaute <xpegenaute at telepolis.es> [030705 15:07]:
> a question, may be i'm wrong, but .. Actually if we build an ADLO
> system, how the binari with "loader+vga bios+pirq+bochs bios" is the
> payload of LinuxBios,then we can't start a minisystem recorded in one
> DoC, no?
 
you should be able to boot from DoC via lilo/grub.

> If we want to do this is it enough with a Jump to the position of Kernel
> image in a DoC ? instead of jump to the power up entry of Bochs ?

something like that might also work. Or maybe returning to LinuxBIOS
from ADLO and chainloading another payload?

BTW, while looking at ADLO I was wondering why ADLO needs to include the
VGA bios in the payload. This makes sense for onboard graphics cards,
but safing the space on systems with AGP/PCI graphics adapters with
onboard roms would be nice. 
Another thing, I tried ADLO on a K8 system and I could get it to read 
the bootloader partly from disk, the output I got was:

Bochs BIOS, 1 cpu, $Revision: 1.2 $ $Date: 2003/05/22 12:52:38 $
[BOCHS BIOS VER:1.79]
[COMPILE DATE:Jul  1 2003 TIME:18:04:49]

DEVICE:0
ata0 master: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
ata0 master: IC35L080AVVA07-0 ATA-5 Hard-Disk (12997 MBytes)

int13_harddisk: AX=0201 BX=0000 CX=0001 DX=0080 ES=07C0
Booting from Hard Disk...
GRUBint13_harddisk: AX=4100 BX=55AA CX=0001 DX=0080 ES=0000
int13_harddisk: AX=4200 BX=75EF CX=6165 DX=0080 ES=0000
Loading stage2int13_harddisk: AX=4200 BX=75F0 CX=6165 DX=0080 ES=0800
.int13_harddisk: AX=4200 BX=766F CX=6165 DX=0080 ES=0820
.
int13_harddisk: AX=0000 BX=0001 CX=6165 DX=0080 ES=0000
[infinite hang]

It apparently hangs in stage2/asm.S in this code or shortly after it
(~line 140):
        /* transition to protected mode */
        DATA32  call EXT_C(real_to_prot)

Any idea what could be wrong?

Best regards,
  Stefan Reinauer
  
-- 
Architecture Team
    SuSE Linux AG


From niki.waibel at newlogic.com  Sat Jul  5 09:52:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Sat Jul  5 09:52:01 2003
Subject: DIP / PLCC
Message-ID: <200307051401.h65E17H3023764@enterprise2.newlogic.at>

hi,

it seems that more and more boards are using PLCC chips instead
of DIP chips.
(http://www.ioss.com.tw/web/English/RD1BIOSSavior/SelectionChart.html)

if DIP is used you can replace the onboard bios chip (normally
2mbit) by a 8mbyte (64mbit) (m-systems md-2800-d08 or md-2802-d08)
DIP chip. that way you have the possability to put the kernel and
a small rootfs directly into the bios chip.

why cannot you do this if your board uses a PLCC chip?
are there no PLCC chips with larger memory available?
what types of PLCC chips are used?
from which companies?

-- 
niki w. waibel - system administrator @ newlogic technologies ag


From niki.waibel at newlogic.com  Sat Jul  5 12:59:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Sat Jul  5 12:59:01 2003
Subject: DIP / PLCC
In-Reply-To: <200307051401.h65E17H3023764@enterprise2.newlogic.at>
Message-ID: <200307051707.h65H7tH3009125@enterprise2.newlogic.at>

hmmm - on http://www.epboard.com/ you can find a PLCC to DIP adapter.

i'd like to know if it is possible to use E32-0041 (PLCC-32 to DIP-32
IC Adapter) on a epia-m board with a MD2802-D08 doc (m-systems).
it seems that these chips have capacities of 2, 4, 8, 12, 24, 40, 72 MByte!!!

niki



On 05-Jul-2003 Niki Waibel wrote:
> hi,
> 
> it seems that more and more boards are using PLCC chips instead
> of DIP chips.
> (http://www.ioss.com.tw/web/English/RD1BIOSSavior/SelectionChart.html)
> 
> if DIP is used you can replace the onboard bios chip (normally
> 2mbit) by a 8mbyte (64mbit) (m-systems md-2800-d08 or md-2802-d08)
> DIP chip. that way you have the possability to put the kernel and
> a small rootfs directly into the bios chip.
> 
> why cannot you do this if your board uses a PLCC chip?
> are there no PLCC chips with larger memory available?
> what types of PLCC chips are used?
> from which companies?
> 
> -- 
> niki w. waibel - system administrator @ newlogic technologies ag


From bendany at mistdl.com  Sat Jul  5 21:45:01 2003
From: bendany at mistdl.com (bendany Qian)
Date: Sat Jul  5 21:45:01 2003
Subject: LinuxBios for Asus TX-97
References: <Pine.LNX.4.44.0307040959050.6293-100000@maxroach.lanl.gov>
Message-ID: <000b01c343df$8beda080$8e00a8c0@notebook>

Tx-97 & Tx-97le base on same chipset. maybe tx97 works. just try it. I
think.

----- Original Message ----- 
From: "ron minnich" <rminnich at lanl.gov>
To: "Jens M?ller" <jens.mueller at informatik.uni-ulm.de>
Cc: <linuxbios at clustermatic.org>
Sent: Friday, July 04, 2003 8:59 AM
Subject: Re: LinuxBios for Asus TX-97


> On Fri, 4 Jul 2003, Jens M?ller wrote:
>
> > Hello Ron,
> >
> > on the status page on www.linuxbios.org is mentioned that linuxbios
> > works on the asus/tx97le? Does that include the TX-97? I would like to
> > find it out, but I don't like crashing my board. So maybe you can tell
> > me my chances?
> >
> > Bye,
> > Jens
> >
>
> anybody know?
>
> ron
>
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>



From rminnich at lanl.gov  Sun Jul  6 18:07:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jul  6 18:07:01 2003
Subject: DIP / PLCC
In-Reply-To: <200307051707.h65H7tH3009125@enterprise2.newlogic.at>
Message-ID: <Pine.LNX.4.44.0307061616050.8610-100000@maxroach.lanl.gov>

On Sat, 5 Jul 2003, Niki Waibel wrote:

> hmmm - on http://www.epboard.com/ you can find a PLCC to DIP adapter.
> 
> i'd like to know if it is possible to use E32-0041 (PLCC-32 to DIP-32
> IC Adapter) on a epia-m board with a MD2802-D08 doc (m-systems).
> it seems that these chips have capacities of 2, 4, 8, 12, 24, 40, 72 MByte!!!
> 


you will have to write IPL code that can bring the chipset up in 256 
instructions or less. 

ron



From hcyun at etri.re.kr  Sun Jul  6 21:24:00 2003
From: hcyun at etri.re.kr (=?euc-kr?B?wLHI8cO2?=)
Date: Sun Jul  6 21:24:00 2003
Subject: ADLO
Message-ID: <9E664A0522ABD711827B00D0B7A8AC4AB6351D@cms3.etri.re.kr>


Did you check your memory configuration?. I mean that part IV of loader.s
should be configured correctly. 

-
HeeChul Yun,          
Embedded S/W Team at ETRI
phone: +82-42-860-1673


> Bochs BIOS, 1 cpu, $Revision: 1.2 $ $Date: 2003/05/22 12:52:38 $
> [BOCHS BIOS VER:1.79]
> [COMPILE DATE:Jul  1 2003 TIME:18:04:49]
> 
> DEVICE:0
> ata0 master: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
> ata0 master: IC35L080AVVA07-0 ATA-5 Hard-Disk (12997 MBytes)
> 
> int13_harddisk: AX=0201 BX=0000 CX=0001 DX=0080 ES=07C0
> Booting from Hard Disk...
> GRUBint13_harddisk: AX=4100 BX=55AA CX=0001 DX=0080 ES=0000
> int13_harddisk: AX=4200 BX=75EF CX=6165 DX=0080 ES=0000
> Loading stage2int13_harddisk: AX=4200 BX=75F0 CX=6165 DX=0080 ES=0800
> .int13_harddisk: AX=4200 BX=766F CX=6165 DX=0080 ES=0820
> .
> int13_harddisk: AX=0000 BX=0001 CX=6165 DX=0080 ES=0000
> [infinite hang]
> 
> It apparently hangs in stage2/asm.S in this code or shortly after it
> (~line 140):
>         /* transition to protected mode */
>         DATA32  call EXT_C(real_to_prot)
> 
> Any idea what could be wrong?
> 
> Best regards,
>   Stefan Reinauer
>   
> -- 
> Architecture Team
>     SuSE Linux AG
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
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From ollie at sis.com.tw  Sun Jul  6 21:27:00 2003
From: ollie at sis.com.tw (ollie lho)
Date: Sun Jul  6 21:27:00 2003
Subject: DIP / PLCC
In-Reply-To: <200307051707.h65H7tH3009125@enterprise2.newlogic.at>
References: <200307051707.h65H7tH3009125@enterprise2.newlogic.at>
Message-ID: <1057540926.9649.4.camel@ollie>

On Sun, 2003-07-06 at 01:07, Niki Waibel wrote:
> hmmm - on http://www.epboard.com/ you can find a PLCC to DIP adapter.
> 
> i'd like to know if it is possible to use E32-0041 (PLCC-32 to DIP-32
> IC Adapter) on a epia-m board with a MD2802-D08 doc (m-systems).
> it seems that these chips have capacities of 2, 4, 8, 12, 24, 40, 72 MByte!!!
> 

AKIAK, DoC doesn't come with PLCC package. This is the main reason we 
don't like a mb with PLCC socket.

I may be wrong but doesn't epia-m come with 2 sockets one for Flash the 
other for DoC ?
-- 
ollie lho <ollie at sis.com.tw>



From rimy2000 at hotmail.com  Sun Jul  6 21:32:00 2003
From: rimy2000 at hotmail.com (elife elife)
Date: Sun Jul  6 21:32:00 2003
Subject: epia-M: lspci
Message-ID: <BAY2-F1629Odutox7ny0000a2ff@hotmail.com>

lspci
00:00.0 Class 0600: 1106:3123
00:01.0 Class 0604: 1106:b091
00:0d.0 Class 0c00: 1106:3044 (rev 80)
00:10.0 Class 0c03: 1106:3038 (rev 80)
00:10.1 Class 0c03: 1106:3038 (rev 80)
00:10.2 Class 0c03: 1106:3038 (rev 80)
00:10.3 Class 0c03: 1106:3104 (rev 82)
00:11.0 Class 0601: 1106:3177
00:11.1 Class 0101: 1106:0571 (rev 06)
00:11.5 Class 0401: 1106:3059 (rev 50)
00:12.0 Class 0200: 1106:3065 (rev 74)
01:00.0 Class 0300: 1106:3122 (rev 03)

lspci -xxx
00:00.0 Class 0600: 1106:3123
00: 06 11 23 31 06 00 30 22 00 00 00 06 00 08 00 00
10: 08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 01 aa
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00
50: c8 de cf 88 e0 07 00 00 f1 00 10 10 10 10 00 00
60: 02 aa 2a 20 e6 32 01 2a c5 2d 43 58 00 44 00 00
70: 82 c8 00 01 01 08 50 00 01 00 00 00 00 00 00 00
80: 0f 61 00 00 80 00 00 00 02 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00
b0: 00 00 00 00 80 00 00 00 68 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 81 dd 42 00 00 00 01 00 40 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 03 13 00 00 00 00 00 00 00 00

00:01.0 Class 0604: 1106:b091
00: 06 11 91 b0 07 01 30 a2 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 00
20: 00 dc f0 dd 00 d8 f0 db 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00
40: 83 c5 00 44 24 72 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 02 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0d.0 Class 0c00: 1106:3044 (rev 80)
00: 06 11 44 30 07 00 10 02 80 10 00 0c 08 20 00 00
10: 00 00 00 de 01 d0 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 44 30
30: 00 00 00 00 50 00 00 00 00 00 00 00 0c 01 00 20
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 02 e4 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:10.0 Class 0c03: 1106:3038 (rev 80)
00: 06 11 38 30 07 00 10 02 80 00 03 0c 08 20 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 d4 00 00 00 00 00 00 00 00 00 00 06 11 38 30
30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 01 00 00
40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00

00:10.1 Class 0c03: 1106:3038 (rev 80)
00: 06 11 38 30 07 00 10 02 80 00 03 0c 08 20 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 d8 00 00 00 00 00 00 00 00 00 00 06 11 38 30
30: 00 00 00 00 80 00 00 00 00 00 00 00 0c 02 00 00
40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00

00:10.2 Class 0c03: 1106:3038 (rev 80)
00: 06 11 38 30 07 00 10 02 80 00 03 0c 08 20 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 dc 00 00 00 00 00 00 00 00 00 00 06 11 38 30
30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 03 00 00
40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00

00:10.3 Class 0c03: 1106:3104 (rev 82)
00: 06 11 04 31 17 00 10 02 82 20 03 0c 08 20 00 00
10: 00 10 00 de 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 04 31
30: 00 00 00 00 80 00 00 00 00 00 00 00 05 04 00 00
40: 00 02 03 00 00 00 00 00 80 10 00 09 00 00 00 00
50: 00 5a 00 80 00 00 00 00 04 0b 66 88 33 66 00 00
60: 20 20 01 00 00 00 00 00 01 00 00 00 00 00 08 c0
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00

00:11.0 Class 0601: 1106:3177
00: 06 11 77 31 87 00 10 02 00 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 01 aa
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00
40: 45 00 f0 00 00 00 00 00 0c 20 00 00 44 00 0a 08
50: 81 1d 09 00 00 b0 ac 50 03 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 00
70: 06 11 01 aa 00 00 00 00 00 00 00 00 20 00 00 00
80: 20 84 59 00 f2 70 00 00 01 04 00 00 00 18 00 00
90: 00 12 00 88 a0 c0 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 05 01 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 14 08 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 05 00 00 00 00 00 00 00 00 00

00:11.1 Class 0101: 1106:0571 (rev 06)
00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 e0 00 00 00 00 00 00 00 00 00 00 06 11 01 aa
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 01 00 00
40: 0b f2 09 05 18 1c c0 00 a8 a8 a8 20 ff 00 b6 b6
50: 07 07 07 e6 0c 03 00 00 a8 a8 a8 a8 00 00 00 00
60: 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00
70: 22 01 00 00 00 00 00 00 82 01 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 06 00 71 05 06 11 01 aa 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 07 00 00 00 00 00 00 00 00 00

00:11.5 Class 0401: 1106:3059 (rev 50)
00: 06 11 59 30 01 00 10 02 50 00 01 04 00 00 00 00
10: 01 e4 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 01 aa
30: 00 00 00 00 c0 00 00 00 00 00 00 00 0a 03 00 00
40: 01 ca 00 00 00 00 00 00 00 00 00 00 3f 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 06 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 02 06 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:12.0 Class 0200: 1106:3065 (rev 74)
00: 06 11 65 30 07 00 10 02 74 00 00 02 08 20 00 00
10: 01 ec 00 00 00 20 00 de 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 02 01
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 03 08
40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01:00.0 Class 0300: 1106:3122 (rev 03)
00: 06 11 22 31 07 00 10 02 03 00 00 03 00 20 00 00
10: 08 00 00 d8 00 00 00 dc 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 22 31
30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 02 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 01 70 22 06 00 00 00 00 00 00 00 00 00 00 00 00
70: 02 00 20 00 07 02 00 1f 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Thanks!

_________________________________________________________________
?????????????? MSN Messenger:  http://messenger.msn.com/cn  



From niki.waibel at newlogic.com  Mon Jul  7 05:38:00 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Jul  7 05:38:00 2003
Subject: DIP / PLCC
In-Reply-To: <1057540926.9649.4.camel@ollie>
Message-ID: <200307070947.h679llH3006113@enterprise2.newlogic.at>

On 07-Jul-2003 ollie lho wrote:
> On Sun, 2003-07-06 at 01:07, Niki Waibel wrote:
>> hmmm - on http://www.epboard.com/ you can find a PLCC to DIP adapter.
>> 
>> i'd like to know if it is possible to use E32-0041 (PLCC-32 to DIP-32
>> IC Adapter) on a epia-m board with a MD2802-D08 doc (m-systems).
>> it seems that these chips have capacities of 2, 4, 8, 12, 24, 40, 72 MByte!!!
>> 
> 
> AKIAK, DoC doesn't come with PLCC package. This is the main reason we 
> don't like a mb with PLCC socket.

but there is this PLCC -> DIP converter from epboard.
you can put the (dip) doc device onto that converter.
then you can put it into the PLCC socket.
see here:
http://www.epboard.com/eproducts/protoadapter2.htm#PLCCtoDIPAdapter
product number: E32-0041

> I may be wrong but doesn't epia-m come with 2 sockets one for Flash the 
> other for DoC ?

i ordered 2 boards -- will tell you soon :)
but i think there is only 1 PLCC socket.
(maybe the older boards had a DIP socket...)


From niki.waibel at newlogic.com  Mon Jul  7 05:40:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Jul  7 05:40:01 2003
Subject: DIP / PLCC
In-Reply-To: <Pine.LNX.4.44.0307061616050.8610-100000@maxroach.lanl.gov>
Message-ID: <200307070949.h679nbH3006150@enterprise2.newlogic.at>

>> hmmm - on http://www.epboard.com/ you can find a PLCC to DIP adapter.
>> 
>> i'd like to know if it is possible to use E32-0041 (PLCC-32 to DIP-32
>> IC Adapter) on a epia-m board with a MD2802-D08 doc (m-systems).
>> it seems that these chips have capacities of 2, 4, 8, 12, 24, 40, 72 MByte!!!
>> 
> 
> you will have to write IPL code that can bring the chipset up in 256 
> instructions or less. 

i am quite new to all this.
could you explain a bit more -- or give me some hints to written
documentation?

do you think it is possible to make that working?

do you think it will be easy?

niki


From stepan at suse.de  Mon Jul  7 06:13:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Jul  7 06:13:01 2003
Subject: DIP / PLCC
In-Reply-To: <1057540926.9649.4.camel@ollie>
References: <200307051707.h65H7tH3009125@enterprise2.newlogic.at> <1057540926.9649.4.camel@ollie>
Message-ID: <20030707102224.GA3735@suse.de>

* ollie lho <ollie at sis.com.tw> [030707 03:22]:
> 
> AKIAK, DoC doesn't come with PLCC package. This is the main reason we 
> don't like a mb with PLCC socket.
> 
> I may be wrong but doesn't epia-m come with 2 sockets one for Flash the 
> other for DoC ?

Mine (Epia-M 10000) only has 1 PLCC socket for 2/4MBit flash (no idea
whether more is possible)

  Stefan

-- 
Architecture Team
    SuSE Linux AG


From aip at cwlinux.com  Mon Jul  7 07:24:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jul  7 07:24:01 2003
Subject: DIP / PLCC
In-Reply-To: <20030707102224.GA3735@suse.de>; from Stefan Reinauer on Mon, Jul 07, 2003 at 12:22:24PM +0200
References: <200307051707.h65H7tH3009125@enterprise2.newlogic.at> <1057540926.9649.4.camel@ollie> <20030707102224.GA3735@suse.de>
Message-ID: <20030707193327.A12480@mail.cwlinux.com>

> Mine (Epia-M 10000) only has 1 PLCC socket for 2/4MBit flash (no idea
> whether more is possible)
I think only EPIA has that socket.  IIRC, Snapgear has got the driver
for doc mil+, but I havn't seen anything yet.  We have used a custom made
DIP-PLCC adapter to connect DOC on EPIA, and Linux is able to see the
DOC with mtd.  However, we haven't done anything further.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From niki.waibel at newlogic.com  Mon Jul  7 08:06:00 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Jul  7 08:06:00 2003
Subject: DIP / PLCC
In-Reply-To: <20030707193327.A12480@mail.cwlinux.com>
Message-ID: <200307071215.h67CFLH3020339@enterprise2.newlogic.at>

>> Mine (Epia-M 10000) only has 1 PLCC socket for 2/4MBit flash (no idea
>> whether more is possible)
> I think only EPIA has that socket.  IIRC, Snapgear has got the driver
> for doc mil+, but I havn't seen anything yet.  We have used a custom made
> DIP-PLCC adapter to connect DOC on EPIA, and Linux is able to see the
> DOC with mtd.  However, we haven't done anything further.

"custom made DIP-PLCC":
what did you customize?

there is also
 http://www.epboard.com/eproducts/ezadapter.htm#DIP to PLCC Adapter
 product number: E32-0030
 name: DIP-32 to  PLCC-32 eZ-Reconfigurable IC Adapter
which seems to be a pin reconfigurable adapter...

andrew, do you think that the DIP chips could work
with such an adapter?

niki


From aip at cwlinux.com  Mon Jul  7 08:11:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jul  7 08:11:01 2003
Subject: DIP / PLCC
In-Reply-To: <200307071215.h67CFLH3020339@enterprise2.newlogic.at>; from Niki Waibel on Mon, Jul 07, 2003 at 02:15:21PM +0200
References: <20030707193327.A12480@mail.cwlinux.com> <200307071215.h67CFLH3020339@enterprise2.newlogic.at>
Message-ID: <20030707202115.A13222@mail.cwlinux.com>

Hi Niki,

> "custom made DIP-PLCC":
> what did you customize?
> there is also
>  http://www.epboard.com/eproducts/ezadapter.htm#DIP to PLCC Adapter
>  product number: E32-0030
>  name: DIP-32 to  PLCC-32 eZ-Reconfigurable IC Adapter
> which seems to be a pin reconfigurable adapter...
> andrew, do you think that the DIP chips could work
> with such an adapter?
We have gotten a PCB design for this.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From niki.waibel at newlogic.com  Mon Jul  7 08:37:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Jul  7 08:37:01 2003
Subject: DIP / PLCC
In-Reply-To: <20030707202115.A13222@mail.cwlinux.com>
Message-ID: <200307071246.h67CkoH3023504@enterprise2.newlogic.at>

>> "custom made DIP-PLCC":
>> what did you customize?
>> there is also
>>  http://www.epboard.com/eproducts/ezadapter.htm#DIP to PLCC Adapter
>>  product number: E32-0030
>>  name: DIP-32 to  PLCC-32 eZ-Reconfigurable IC Adapter
>> which seems to be a pin reconfigurable adapter...
>> andrew, do you think that the DIP chips could work
>> with such an adapter?
> We have gotten a PCB design for this.
is it just pin switching, or is it more you have to do?

niki


From rminnich at lanl.gov  Mon Jul  7 10:48:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul  7 10:48:01 2003
Subject: DIP / PLCC
In-Reply-To: <200307070949.h679nbH3006150@enterprise2.newlogic.at>
Message-ID: <Pine.LNX.4.44.0307070857140.15319-100000@maxroach.lanl.gov>

On Mon, 7 Jul 2003, Niki Waibel wrote:

> i am quite new to all this.
> could you explain a bit more -- or give me some hints to written
> documentation?

take a look at the sis630 ipl.S code to get an idea. Then study the via 
vt8601 code for ram startup. 

> do you think it is possible to make that working?

not sure.


> do you think it will be easy?

it's easier for some than others. For me, it's always hard.

ron



From xpegenaute at telepolis.es  Mon Jul  7 12:36:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Mon Jul  7 12:36:01 2003
Subject: elfboot
Message-ID: <1057599558.521.58.camel@p-133>

Hi,

any one can help me with this ?

I was thinking that after crt0.S in ROMBASE (0x80000 for Matsonic) copy
the LinuxBios (the payload) into DRAM (RAMBASE 0x4000 for Matsonic)
follow the code to hardwaremain() initialitizing all hardware and arrive
in write_tables that prepare the memory to let information about the
hardware to the next O.S., and now we can choose between:

1) We want start an ELF binary (not payload) that is in DoC (p.e.) after
LinuxBios. Then we execute elfboot() that look inside the ROM for the
next code starting with a valid ELF header, build the segments, copy the
segments and give the control to the program.

No problem in this case, i think.


2) We want start a Linux Kernel that is recorded (neither payload) after
LinuxBios binary in DoC (p.e.), then we execute linuxbiosmain() and in
the end of this function we make a long jump to 0x90000.

Here, i don't see what function in linuxbiosmain() copy the code of
Kernel to DRAM.Any one know it ?


Thanks. 
Xavi.



From ebiederman at lnxi.com  Mon Jul  7 19:49:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul  7 19:49:00 2003
Subject: [PATCH] Fix to elfboot checksum problem
In-Reply-To: <20030630182331.GA12910@tsn.or.jp>
References: <20030630182331.GA12910@tsn.or.jp>
Message-ID: <m3wuet28ih.fsf@maxwell.lnxi.com>

SONE Takeshi <ts1 at tsn.or.jp> writes:

> Hi,
> I think I've at last found a bug in elfboot.c.
> Until this fix, I had always needed to disable verify code in
> elfboot.c to get it work.
> Now it boots ELF kernel with BOOT_IDE perfectly.
> 
> One of doubly-linked chain was not initialized.
> I think it did not cause problem when memory near address 0 comes
> up with zeroes.
> But my raminit.inc leaves gabages there so some bogus memory ranges
> have been included in checksum.

Thanks good catch.  

Another possibility is that the checksum is optional and not all
versions of mkelfImage add it, and etherboot does not.  So that
code path is not exercised quite as much as it should be.

Eric



From ebiederman at lnxi.com  Mon Jul  7 19:54:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul  7 19:54:01 2003
Subject: elfboot
In-Reply-To: <1057599558.521.58.camel@p-133>
References: <1057599558.521.58.camel@p-133>
Message-ID: <m3smph28bd.fsf@maxwell.lnxi.com>

Xavier Pegenaute <xpegenaute at telepolis.es> writes:

> Hi,
> 
> any one can help me with this ?
> 
> I was thinking that after crt0.S in ROMBASE (0x80000 for Matsonic) copy
> the LinuxBios (the payload) into DRAM (RAMBASE 0x4000 for Matsonic)
> follow the code to hardwaremain() initialitizing all hardware and arrive
> in write_tables that prepare the memory to let information about the
> hardware to the next O.S., and now we can choose between:
> 
> 1) We want start an ELF binary (not payload) that is in DoC (p.e.) after
> LinuxBios. Then we execute elfboot() that look inside the ROM for the
> next code starting with a valid ELF header, build the segments, copy the
> segments and give the control to the program.
> 
> No problem in this case, i think.

Sounds like standard use.

> 2) We want start a Linux Kernel that is recorded (neither payload) after
> LinuxBios binary in DoC (p.e.), then we execute linuxbiosmain() and in
> the end of this function we make a long jump to 0x90000.

Linuxbiosmain() is deprecated code and it always jumps to 0x100000 1MB.
Anything is not done.  And everyone is encouraged not to use linuxbiosmain
for new deployments.

> Here, i don't see what function in linuxbiosmain() copy the code of
> Kernel to DRAM.Any one know it ?

It is the gunzip part.  But please don't use that.

Eric



From ollie at sis.com.tw  Mon Jul  7 21:32:00 2003
From: ollie at sis.com.tw (ollie lho)
Date: Mon Jul  7 21:32:00 2003
Subject: DIP / PLCC
In-Reply-To: <20030707193327.A12480@mail.cwlinux.com>
References: <200307051707.h65H7tH3009125@enterprise2.newlogic.at>
	 <1057540926.9649.4.camel@ollie> <20030707102224.GA3735@suse.de>
	 <20030707193327.A12480@mail.cwlinux.com>
Message-ID: <1057627707.9649.200.camel@ollie>

On Mon, 2003-07-07 at 19:33, Andrew Ip wrote:
> > Mine (Epia-M 10000) only has 1 PLCC socket for 2/4MBit flash (no idea
> > whether more is possible)
> I think only EPIA has that socket.  IIRC, Snapgear has got the driver
> for doc mil+, but I havn't seen anything yet.  We have used a custom made
> DIP-PLCC adapter to connect DOC on EPIA, and Linux is able to see the
> DOC with mtd.  However, we haven't done anything further.
> 

Is Snapgear's code GPLed ?

-- 
ollie lho <ollie at sis.com.tw>



From xpegenaute at telepolis.es  Tue Jul  8 03:24:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Jul  8 03:24:01 2003
Subject: elfboot
In-Reply-To: <m3smph28bd.fsf@maxwell.lnxi.com>
References: <1057599558.521.58.camel@p-133>
	 <m3smph28bd.fsf@maxwell.lnxi.com>
Message-ID: <1057652813.515.23.camel@p-133>

Hi,


On Tue, 2003-07-08 at 02:03, Eric W. Biederman wrote:
> > 1) We want start an ELF binary (not payload) that is in DoC (p.e.) after
> > LinuxBios. Then we execute elfboot() that look inside the ROM for the
> > next code starting with a valid ELF header, build the segments, copy the
> > segments and give the control to the program.
> > 
> > No problem in this case, i think.
> 
> Sounds like standard use.
> 
> > 2) We want start a Linux Kernel that is recorded (neither payload) after
> > LinuxBios binary in DoC (p.e.), then we execute linuxbiosmain() and in
> > the end of this function we make a long jump to 0x90000.
> 
> Linuxbiosmain() is deprecated code and it always jumps to 0x100000 1MB.
> Anything is not done.  And everyone is encouraged not to use linuxbiosmain
> for new deployments.
> 
> > Here, i don't see what function in linuxbiosmain() copy the code of
> > Kernel to DRAM.Any one know it ?
> 
> It is the gunzip part.  But please don't use that.

The problem, is that, if i follow the instructions of
freebios/HOWTO/SiS630, the linux kernel binary generated doesn't has
elfheader.

Then if i want to use the standard use, i have apply some external
utility to generate an elf file (mkelfImage) and put in config file
"fileoption USE_ELF_BOOT=1". Is it right ?

Another think, i thought that the Linux Kernel alone has the code to
decompress himself (in the same way that we can put Kernel in a floppy
disk and it decompress alone. (dd if=kernel of=/dev/fd0))

Thanks.
Xavi.





From aip at cwlinux.com  Tue Jul  8 04:18:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jul  8 04:18:01 2003
Subject: DIP / PLCC
In-Reply-To: <1057627707.9649.200.camel@ollie>; from ollie lho on Tue, Jul 08, 2003 at 09:28:28AM +0800
References: <200307051707.h65H7tH3009125@enterprise2.newlogic.at> <1057540926.9649.4.camel@ollie> <20030707102224.GA3735@suse.de> <20030707193327.A12480@mail.cwlinux.com> <1057627707.9649.200.camel@ollie>
Message-ID: <20030708162823.C24252@mail.cwlinux.com>

> Is Snapgear's code GPLed ?
Should be.
Got this one from Linux Devices
http://www.linuxdevices.com/news/NS9097179629.html

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From ollie at sis.com.tw  Tue Jul  8 04:50:01 2003
From: ollie at sis.com.tw (ollie lho)
Date: Tue Jul  8 04:50:01 2003
Subject: DIP / PLCC
In-Reply-To: <20030708162823.C24252@mail.cwlinux.com>
References: <200307051707.h65H7tH3009125@enterprise2.newlogic.at>
	 <1057540926.9649.4.camel@ollie> <20030707102224.GA3735@suse.de>
	 <20030707193327.A12480@mail.cwlinux.com> <1057627707.9649.200.camel@ollie>
	 <20030708162823.C24252@mail.cwlinux.com>
Message-ID: <1057653999.9649.230.camel@ollie>

On Tue, 2003-07-08 at 16:28, Andrew Ip wrote:
> > Is Snapgear's code GPLed ?
> Should be.
> Got this one from Linux Devices
> http://www.linuxdevices.com/news/NS9097179629.html

Yea, I saw it on the MTD CVS. Wondering how M-system
changed their mind.
-- 
ollie lho <ollie at sis.com.tw>



From ebiederman at lnxi.com  Tue Jul  8 06:58:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jul  8 06:58:00 2003
Subject: elfboot
In-Reply-To: <1057652813.515.23.camel@p-133>
References: <1057599558.521.58.camel@p-133> <m3smph28bd.fsf@maxwell.lnxi.com>
	<1057652813.515.23.camel@p-133>
Message-ID: <m3he5xnumk.fsf@maxwell.lnxi.com>

Xavier Pegenaute <xpegenaute at telepolis.es> writes:

> Hi,
> 
> 
> On Tue, 2003-07-08 at 02:03, Eric W. Biederman wrote:
> > > 1) We want start an ELF binary (not payload) that is in DoC (p.e.) after
> > > LinuxBios. Then we execute elfboot() that look inside the ROM for the
> > > next code starting with a valid ELF header, build the segments, copy the
> > > segments and give the control to the program.
> > > 
> > > No problem in this case, i think.
> > 
> > Sounds like standard use.
> > 
> > > 2) We want start a Linux Kernel that is recorded (neither payload) after
> > > LinuxBios binary in DoC (p.e.), then we execute linuxbiosmain() and in
> > > the end of this function we make a long jump to 0x90000.
> > 
> > Linuxbiosmain() is deprecated code and it always jumps to 0x100000 1MB.
> > Anything is not done.  And everyone is encouraged not to use linuxbiosmain
> > for new deployments.
> > 
> > > Here, i don't see what function in linuxbiosmain() copy the code of
> > > Kernel to DRAM.Any one know it ?
> > 
> > It is the gunzip part.  But please don't use that.
> 
> The problem, is that, if i follow the instructions of
> freebios/HOWTO/SiS630, the linux kernel binary generated doesn't has
> elfheader.
>
> Then if i want to use the standard use, i have apply some external
> utility to generate an elf file (mkelfImage) and put in config file
> "fileoption USE_ELF_BOOT=1". Is it right ?

Essentially correct.  MkelfImage takes a standard x86 linux kernel and
wraps so it is a bootable ELF executable.

The latest mkelfImage can be found at:

ftp://ftp.lnxi.com/pub/mkelfImage/

> Another think, i thought that the Linux Kernel alone has the code to
> decompress himself (in the same way that we can put Kernel in a floppy
> disk and it decompress alone. (dd if=kernel of=/dev/fd0))

The strange choices in linuxbios main where it decompresses the kernel
instead of using the kernels own decompressor, are among the many
reasons it is deprecated.

Eric



From rminnich at lanl.gov  Tue Jul  8 10:01:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul  8 10:01:01 2003
Subject: elfboot
In-Reply-To: <m3he5xnumk.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307080810460.25149-100000@maxroach.lanl.gov>

On 8 Jul 2003, Eric W. Biederman wrote:

> 
> The strange choices in linuxbios main where it decompresses the kernel
> instead of using the kernels own decompressor, are among the many
> reasons it is deprecated.

no strange at all in 2000, when we figured to boot many other kernels that 
did not have their own decompressor.

ron



From aip at cwlinux.com  Tue Jul  8 11:03:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jul  8 11:03:00 2003
Subject: EPIA-M 10000 is also working with current epia-m code
Message-ID: <20030708231327.A29032@mail.cwlinux.com>

Hi,

	Just wanna confirm that EPIA-M 10000 is also working with current
epia-m code, although both of them use different northbridge(vt8623 and
vt8633).  Here are what is missing on epia-m
- enabling flash so that flash_rom can run
- VGA support

patches are welcome.  :)

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From salmon.chen at msa.hinet.net  Tue Jul  8 23:33:01 2003
From: salmon.chen at msa.hinet.net (=?big5?B?qvy6YQ==?=)
Date: Tue Jul  8 23:33:01 2003
Subject: make crt0.s problem
Message-ID: <003b01c345cc$28920910$160aa8c0@D29092.findquick.com>

Hi,
    I am junior for Linux BIOS , I have a problem to make crt0.s on supermicro p4dc6p platform.Below is my sequence to make crt0.s

1.)install red hat 9 on my p4dc6p platform

2.) export CVS_RSH=ssh 
     cvs -d:pserver:anonymous at cvs.freebios.sourceforge.net:/cvsroot/freebios login 
     cvs -z3 -d:pserver:anonymous at cvs.freebios.sourceforge.net:/cvsroot/freebios co freebios 

3.) mkdir p4dc6p
     cd p4dc6p

4.) copy example-normal.config form source code to p4dc6p

5.)python /root/src/freebois/util/config/NLBConfig.py example-normal.config /root/src/freebios

 After these process I got below files,but I can't find crt0.s .Does any guys help me to figure out it?

crt0_includes.h
LinuxBIOSDoc.config
makefile
makefile.settings
nsuperio.c



Thanks,
Tien
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From root at hamburg.de  Wed Jul  9 05:04:00 2003
From: root at hamburg.de (Felix Kloeckner)
Date: Wed Jul  9 05:04:00 2003
Subject: Linuxbios, bugfix in sis flash_rom
Message-ID: <20030709111107.A848@synapse.pentanet>

Hello,

after wondering why flash_rom wasn't working, i found that the compiler
did some optimization on the reading/writing from/to the flash. So i
made the variables for accessing the flash 'volatile', now it works!

could you apply the patch to the linuxbios cvs?


thanks

  Felix Kloeckner

ps

this patch is for jedec flash only, other parts probably have the
same problem
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From rogerxxmaillist at san.rr.com  Wed Jul  9 06:08:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Wed Jul  9 06:08:01 2003
Subject: intel 440bx unshadow for doc2001
Message-ID: <1057745829.20103.19.camel@localhost3.localdomain>

Figured out from scanning through the openbios/devbios code on howto
unshadow the intel 440bx to be able to successfully load the MTD doc2001
module and have it successfully detect the DOC.

The devbios/openbios project can be found here:
http://www.openbios.info/download/index.html
And the url is at the bottom of the page for
http://www.openbios.info/bin/devbios-0.3.2.tar.gz

Does anybody know if any of this is already in the MTD drivers?  This
code unshadows and gives access to many bios devices.

Went into the openbios/devbios/pcisets.c and commented out the two
statements within the "static void intel4x0_deactivate(void)" function
(this prevents the unshadowing after the bios.o module is loaded -- and
while i was at it, uncommented the a printk debug statement).  Loading
the bios.o module shows the isa bridge info:

Jul  9 02:40:27  BIOS: host bridge is 8086, 7190, 0
Jul  9 02:40:27  BIOS: isa bridge is 8086, 7110, 38
Jul  9 02:40:27  BIOS: isa bridge cfg is 0x64
Jul  9 02:40:27  BIOS: isa bridge cfg is 0x64
Jul  9 02:40:27  BIOS: isa bridge cfg is 0x64
(last line repeated many times)
Jul  9 02:40:27  BIOS: 0k flashchip (ID 0x5f1f) found at physical
address 0xfff01000 (va=0xd8854000+0x101000).
Jul  9 02:40:27  BIOS: Probing PCI device with 256k rom
Jul  9 02:40:27  BIOS: Probing PCI device with 64k rom



Once I unshadowed the intel 440bx, the following script loads doc with
ease:

#!/bin/bash
modprobe doc2001
modprobe docprobe doc_config_location=0xfff00000

cat /proc/mtd

modprobe nft


If i'm correct, the unshadow code just needs to be written into MTD for
everything to work easily? mm...guess i should post to MTD mailing list.
-- 

Roger
http://www.eskimo.com/~roger/index.html



From rminnich at lanl.gov  Wed Jul  9 07:58:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul  9 07:58:01 2003
Subject: Linuxbios, bugfix in sis flash_rom
In-Reply-To: <20030709111107.A848@synapse.pentanet>
Message-ID: <Pine.LNX.4.44.0307090607250.1936-100000@maxroach.lanl.gov>

thanks, I thought I had caught all the missing volatiles ... glad to see 
someone else catches this fun stuff :-)

ron




From aod at uninet.com.br  Wed Jul  9 08:44:00 2003
From: aod at uninet.com.br (aod at uninet.com.br)
Date: Wed Jul  9 08:44:00 2003
Subject: m810 and 256mb memory problems
Message-ID: <3efd1176.4c3a.0@uninet.com.br>

Hi All, Ron,


I have been using linuxbios with sis730 motherboards (K7SEM and M810LMR)
and I am having several systems "freezes"  using 256MB sdram sticks (but
none using 128MB memory sticks). Also I haven`t been able to use memory in
the second memory banck (DIMM2). Linuxbios just doesnt sees memory in
DIMM2.

thanks for any feedback




From aod at uninet.com.br  Wed Jul  9 08:44:12 2003
From: aod at uninet.com.br (aod at uninet.com.br)
Date: Wed Jul  9 08:44:12 2003
Subject: very large DOCs and DOCs with UID
Message-ID: <3efd11fa.4c41.0@uninet.com.br>

Has anyone tried to use 144MB DoCs with linux bios ? I am using 8MBs with
no problem, but could not format a 144MB doc properly in linux.

Als, has anyone use the new DoC millenium with the Unique Identification
Number? Can we read this number in linux?

thanks folks


From marco_hetzel at web.de  Wed Jul  9 08:44:15 2003
From: marco_hetzel at web.de (Marco Hetzel)
Date: Wed Jul  9 08:44:15 2003
Subject: Asus A7N8X
Message-ID: <200307091248.h69CmPQ09877@mailgate5.cinetic.de>

  Hi!

I've got a Asus A7N8X-Mainboard with NForce2 chipset. Is there any chance to run the liuxbios on my box? Do you hae any helping links? Thanks,

 Marco
______________________________________________________________________________
Mit der Multi-SMS von WEB.DE FreeMail koennen Sie 760 Zeichen versenden.
Informationen unter http://freemail.web.de/features/?mc=021184



From marco_hetzel at web.de  Wed Jul  9 09:14:00 2003
From: marco_hetzel at web.de (Marco Hetzel)
Date: Wed Jul  9 09:14:00 2003
Subject: Asus A7N8X
Message-ID: <200307091324.h69DOCQ14680@mailgate5.cinetic.de>

"Marco Hetzel" <marco_hetzel at web.de> schrieb am 09.07.03 14:48:23:
  Hi!

I've got a Asus A7N8X-Mainboard with NForce2 chipset. Is there any chance to run the liuxbios on my box? Do you hae any helping links? Thanks,

 Marco


____________________________________________________________________________
Nur bei WEB.DE Testsieger FreeMail testen und damit 1 qm Regenwald
schuetzen. Jetzt anmelden und mithelfen! http://user.web.de/Regenwald



From rminnich at lanl.gov  Wed Jul  9 10:39:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul  9 10:39:00 2003
Subject: Linuxbios, bugfix in sis flash_rom
In-Reply-To: <20030709111107.A848@synapse.pentanet>
Message-ID: <Pine.LNX.4.44.0307090849180.3047-100000@maxroach.lanl.gov>

fixed and committed, please test.

ron

p.s. we're getting close to freeze, I figure when we get the K7SEM fix in 
we're done on 1.0.1

ron



From james.mcmechan at navy.mil  Wed Jul  9 15:33:01 2003
From: james.mcmechan at navy.mil (McMechan, James W CIV)
Date: Wed Jul  9 15:33:01 2003
Subject: Sourceforge and CVS
Message-ID: <02E6075B2450E94CA159E22331C16204E96B92@NAWECHLKEX02VA.nadsuswe.nads.navy.mil>

It may that the CVS delays ~24 hours are a result of external pserver requests/ViewCVS being routed to the backup CVS system, it appears that SF is trying to organize for a hardware upgrade, and is providing direct connections to the main servers only when logged in via SSH, anonymous connections are being deferred to the backup server farm which has the ~24 hour delay.


http://sourceforge.net/docman/display_doc.php?docid=2352&group_id=1#cvs
see the message from 6-19-2003.
They also have a August target date for the new hardware.

Also while I still can't access CVS due to firewall issues I did download the automated daily snapshot tarball from http://cvs.sf.net/cvstarballs/freebios-cvsroot.tar.gz
It does not appear to have been updated since Wed July 2,2003 16:50 was that the last checkin or is something else broken at SF, but still it is much more recent than that 2001 tarball I had before.


From ebiederman at lnxi.com  Wed Jul  9 22:35:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jul  9 22:35:01 2003
Subject: elfboot
In-Reply-To: <Pine.LNX.4.44.0307080810460.25149-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307080810460.25149-100000@maxroach.lanl.gov>
Message-ID: <m3llv73xri.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On 8 Jul 2003, Eric W. Biederman wrote:
> 
> > 
> > The strange choices in linuxbios main where it decompresses the kernel
> > instead of using the kernels own decompressor, are among the many
> > reasons it is deprecated.
> 
> no strange at all in 2000, when we figured to boot many other kernels that 
> did not have their own decompressor.

I agree it makes sense from the context in which it was written.  I was just
to lazy to fill in the context for a deprecated feature.

Eric



From ijpriya at hotmail.com  Wed Jul  9 23:09:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Wed Jul  9 23:09:01 2003
Subject: config
Message-ID: <BAY2-F123mrvoGdKO8F00007bab@hotmail.com>

Hello,

        I have 2.4.18-14 Redhat linux kernel.To use linux bios for sc1200, 
which .config file from kernel_patches directory should I use? Can I use the 
same the same configuration as 2.4.18-14?

Thanks in advance for any help!

_________________________________________________________________
Race along with NK. The fastest Indian 
http://server1.msn.co.in/sp03/tataracing/index.asp Feel the thrill!



From lichaojun at zys.dq.cnpc.com.cn  Thu Jul 10 03:49:01 2003
From: lichaojun at zys.dq.cnpc.com.cn (lichaojun)
Date: Thu Jul 10 03:49:01 2003
Subject: ga-6bxc
Message-ID: <3F0D1E04.6010402@zys.dq.cnpc.com.cn>

 hi!
     i got a ga-6bxc and download freebios from cvs.when complie it ,it say:
linuxbios_c.o: In function 'mainboard_fixup':
linuxbios_c.o(.text+0x10b9): undefined reference to 'pci_zero_irq_setting'

 anybody can help me!

 i want to my ga-6bxc (with 2 Mb flash) boot from  ide disk,using etherboot
 could give me a config file!

   



From ijpriya at hotmail.com  Thu Jul 10 05:03:00 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Thu Jul 10 05:03:00 2003
Subject: Is Intel 810 chipset supported?
Message-ID: <BAY2-F103bKWZfEAkqB00001521@hotmail.com>

	I am having the Intel 810 chipset with onboard graphics controller. Can I 
use linux bios for this?

_________________________________________________________________
Race along with NK. The fastest Indian 
http://server1.msn.co.in/sp03/tataracing/index.asp Feel the thrill!



From ijpriya at hotmail.com  Thu Jul 10 05:22:00 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Thu Jul 10 05:22:00 2003
Subject: ide-spinup.patch
Message-ID: <BAY2-F172rAXBirbThA000092a2@hotmail.com>

Hello,

       I am using the kernel version 2.4.18-14. I guess the patch 
ide-spinup.patch is given for 2.4.7 . What patch shall I apply for 
2.4.18-14?

Thanks in advance for any help!

_________________________________________________________________
Dress up your desktop! Get the best wallpapers. 
http://server1.msn.co.in/msnchannels/Entertainment/wallpaperhome.asp Just 
click here!



From ferenc at engard.hu  Thu Jul 10 09:36:00 2003
From: ferenc at engard.hu (Ferenc Engard)
Date: Thu Jul 10 09:36:00 2003
Subject: Geode GX1 processor?
Message-ID: <Pine.LNX.4.40.0307101537370.24460-100000@korus.hu>

Hi all,

A bit offtopic: I am looking for a forum/mailing list/people who are work
with this processor, especially with its 2d video accel on linux. I have
problems, NSC didn't respond, and I stucked... :-(

Thanks:
Circum



From rminnich at lanl.gov  Thu Jul 10 09:39:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 10 09:39:00 2003
Subject: Geode GX1 processor?
In-Reply-To: <Pine.LNX.4.40.0307101537370.24460-100000@korus.hu>
Message-ID: <Pine.LNX.4.44.0307100749160.11863-100000@maxroach.lanl.gov>

On Thu, 10 Jul 2003, Ferenc Engard wrote:

> A bit offtopic: I am looking for a forum/mailing list/people who are work
> with this processor, especially with its 2d video accel on linux. I have
> problems, NSC didn't respond, and I stucked... :-(

you can split a list off for geode, but we're interested here, and I would
welcome a discussion on this list -- it's not a high traffic list.

ron



From bari at onelabs.com  Thu Jul 10 10:30:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Thu Jul 10 10:30:01 2003
Subject: Geode GX1 processor?
In-Reply-To: <Pine.LNX.4.44.0307100749160.11863-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307100749160.11863-100000@maxroach.lanl.gov>
Message-ID: <3F0D7B7B.90602@onelabs.com>

ron minnich wrote:

>On Thu, 10 Jul 2003, Ferenc Engard wrote:
>
>  
>
>>A bit offtopic: I am looking for a forum/mailing list/people who are work
>>with this processor, especially with its 2d video accel on linux. I have
>>problems, NSC didn't respond, and I stucked... :-(
>>    
>>
>
>you can split a list off for geode, but we're interested here, and I would
>welcome a discussion on this list -- it's not a high traffic list.
>
>  
>
NSC has been trying to sell their IA/Geode group for the past few months

http://www.national.com/news/item/0,1735,863,00.html

Support has generally been non-existent for the IA products if you're 
not in their loop. Go ahead and ask away. A few of us here may be able 
to help.

-Bari






From rminnich at lanl.gov  Thu Jul 10 10:34:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 10 10:34:01 2003
Subject: Geode GX1 processor?
In-Reply-To: <3F0D7B7B.90602@onelabs.com>
Message-ID: <Pine.LNX.4.44.0307100842481.11863-100000@maxroach.lanl.gov>

On Thu, 10 Jul 2003, Bari Ari wrote:

> NSC has been trying to sell their IA/Geode group for the past few months
> 
> http://www.national.com/news/item/0,1735,863,00.html

hmm.

> 
> Support has generally been non-existent for the IA products ...

gee, could there be a cause-and-effect here?

ron



From bari at onelabs.com  Thu Jul 10 10:48:00 2003
From: bari at onelabs.com (Bari Ari)
Date: Thu Jul 10 10:48:00 2003
Subject: Geode GX1 processor?
In-Reply-To: <Pine.LNX.4.44.0307100842481.11863-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307100842481.11863-100000@maxroach.lanl.gov>
Message-ID: <3F0D7FBE.6040506@onelabs.com>

ron minnich wrote:

>On Thu, 10 Jul 2003, Bari Ari wrote:
>
>  
>
>>NSC has been trying to sell their IA/Geode group for the past few months
>>
>>http://www.national.com/news/item/0,1735,863,00.html
>>    
>>
>
>hmm.
>
>  
>
>>Support has generally been non-existent for the IA products ...
>>    
>>
>
>gee, could there be a cause-and-effect here?
>  
>
Support has been pretty good if you've made it into their "inner 
circle". It's the typical situation for all the chipset vendors. Nearly 
zero support unless you're a volume OEM. All the IA/Geode data sheets 
are still only available on a confidential website that requires 
authorization. You can find some helpful info and source code for the 
Gedoes at: 

www.linux4.tv

-Bari





From bgr at gw.linespeed.net  Thu Jul 10 10:56:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Thu Jul 10 10:56:01 2003
Subject: Geode GX1 processor?
In-Reply-To: <3F0D7FBE.6040506@onelabs.com>
References: <Pine.LNX.4.44.0307100842481.11863-100000@maxroach.lanl.gov>
 <3F0D7FBE.6040506@onelabs.com>
Message-ID: <Pine.LNX.4.53.0307100959250.9045@gw.linespeed.net>

They left their geode roadmap quite a while ago.  From what I heard when
we started working with their products and created a reference design they
would have about the same speed and features as VIA has now on their
mini-itx boards.

You can get to some of the IA stuff at.

http://wwwd.national.com/National/developer.nsf/designs/System.htm

Since they changed their site I haven't had to log in for the software
anymore, and I haven't been able to find most of the resources I
previously used.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Thu, 10 Jul 2003, Bari Ari wrote:

> ron minnich wrote:
>
> >On Thu, 10 Jul 2003, Bari Ari wrote:
> >
> >
> >
> >>NSC has been trying to sell their IA/Geode group for the past few months
> >>
> >>http://www.national.com/news/item/0,1735,863,00.html
> >>
> >>
> >
> >hmm.
> >
> >
> >
> >>Support has generally been non-existent for the IA products ...
> >>
> >>
> >
> >gee, could there be a cause-and-effect here?
> >
> >
> Support has been pretty good if you've made it into their "inner
> circle". It's the typical situation for all the chipset vendors. Nearly
> zero support unless you're a volume OEM. All the IA/Geode data sheets
> are still only available on a confidential website that requires
> authorization. You can find some helpful info and source code for the
> Gedoes at:
>
> www.linux4.tv
>
> -Bari
>
>
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From sc at flagen.com  Thu Jul 10 17:17:00 2003
From: sc at flagen.com (David Hendricks)
Date: Thu Jul 10 17:17:00 2003
Subject: Any EPIA etherboot success stories?
Message-ID: <44564.128.165.250.195.1057875722.squirrel@mail.flagen.com>

I see a lot of people here have gotten LinuxBIOS working with the Via EPIA
using an IDE device, but has anyone managed to get it working using
etherboot to boot a kernel over a network? I'm a hopeless newbie and have
been struggling with this for some time. I have links to logs, my payload,
and my config below (Trying to keep the list archives tidy).

I had gotten etherboot working with the PCM-5823s earlier and compared the
minicom log with that of my Epia. The only real obvious discrepency I see
is the entry point. The Geode entered at 0x00094000 (606,208), while the
Epia is trying to enter at 0x00020000 (131,072).

I'm using CVS versions of Etherboot and LinuxBios. However, I haven't been
able to update in the past one or two weeks due to Sourceforge's problems
so I might have missed an important patch.

Links
EPIA minicom log (High verbosity):
http://www.flagen.com/~sc/linux/funstuff/epia-dave
My Rhine payload:
http://www.flagen.com/~sc/linux/funstuff/via-rhine-ebcvs.elf
My config file: http://www.flagen.com/~sc/linux/funstuff/epia.config
Geode (Elfboot part only):
http://www.flagen.com/~sc/linux/funstuff/geode-elfboot-dave

TIA
--David


From heinz.mailing.list at cycnus.de  Thu Jul 10 18:00:00 2003
From: heinz.mailing.list at cycnus.de (Heinz N. Gies)
Date: Thu Jul 10 18:00:00 2003
Subject: Where to buy the a Matsonic MS7308E
Message-ID: <200307110006.25214.heinz.mailing.list@cycnus.de>

hi i read your nice sis630 howto,
after i finished ther are stilll some questions at first a very essential 
problem:
where to get such a 'Matsonic MS7308E', i googled for it but only fins ome 
sides i japaneso or some language wich i can't differ as dumb european ;) and 
the side from ledtech where i don't find a suplier too :(
so if someone know where to get this fine mainbords to but a LinuxBIOS on, 
please tell em :D

secend question:
did i realy need this FIZ if i wrrite the FlashRom in the same machine i want 
to use it? (cause it is very expensiv ... and i am just a poor student)
third and fourth question:
did i need an additional flashrom or can i use the buildin bios as flashrom 
and (i read that with an 4mb flash it is possible to put the whole boot 
proces in it) is possible to get a larger rom (and what is a n approx. price 
for such a 'ting')

please excure my bad englsh

thx
Heinz N. Gies



From mwilkinson at ndirect.co.uk  Thu Jul 10 18:10:01 2003
From: mwilkinson at ndirect.co.uk (Mark Wilkinson)
Date: Thu Jul 10 18:10:01 2003
Subject: Any EPIA etherboot success stories?
In-Reply-To: <44564.128.165.250.195.1057875722.squirrel@mail.flagen.com>
References: <44564.128.165.250.195.1057875722.squirrel@mail.flagen.com>
Message-ID: <200307102320.55874.mwilkinson@ndirect.co.uk>

Hi David,
	If you mean has anyone managed to boot a Via EPIA using etherboot as the 
payload, and loading the kernel via (no pun) tftp, then yes.... but then I 
wrote it all down in the EPIA howto :-)


Regards
Mark.


On Thursday 10 Jul 2003 23:22, David Hendricks wrote:
> I see a lot of people here have gotten LinuxBIOS working with the Via EPIA
> using an IDE device, but has anyone managed to get it working using
> etherboot to boot a kernel over a network? I'm a hopeless newbie and have
> been struggling with this for some time. I have links to logs, my payload,
> and my config below (Trying to keep the list archives tidy).
>
> I had gotten etherboot working with the PCM-5823s earlier and compared the
> minicom log with that of my Epia. The only real obvious discrepency I see
> is the entry point. The Geode entered at 0x00094000 (606,208), while the
> Epia is trying to enter at 0x00020000 (131,072).
>
> I'm using CVS versions of Etherboot and LinuxBios. However, I haven't been
> able to update in the past one or two weeks due to Sourceforge's problems
> so I might have missed an important patch.
>
> Links
> EPIA minicom log (High verbosity):
> http://www.flagen.com/~sc/linux/funstuff/epia-dave
> My Rhine payload:
> http://www.flagen.com/~sc/linux/funstuff/via-rhine-ebcvs.elf
> My config file: http://www.flagen.com/~sc/linux/funstuff/epia.config
> Geode (Elfboot part only):
> http://www.flagen.com/~sc/linux/funstuff/geode-elfboot-dave
>
> TIA
> --David
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From mwilkinson at ndirect.co.uk  Thu Jul 10 18:28:00 2003
From: mwilkinson at ndirect.co.uk (Mark Wilkinson)
Date: Thu Jul 10 18:28:00 2003
Subject: Any EPIA etherboot success stories?
In-Reply-To: <200307102320.55874.mwilkinson@ndirect.co.uk>
References: <44564.128.165.250.195.1057875722.squirrel@mail.flagen.com> <200307102320.55874.mwilkinson@ndirect.co.uk>
Message-ID: <200307102338.53510.mwilkinson@ndirect.co.uk>

On Thursday 10 Jul 2003 23:20, Mark Wilkinson wrote:
> Hi David,
> 	If you mean has anyone managed to boot a Via EPIA using etherboot as the
> payload, and loading the kernel via (no pun) tftp, then yes.... but then I
> wrote it all down in the EPIA howto :-)
>

oops, hit the wrong key there...

what seems to be the problem that you're having ? your epia.config, the 
zkernel_start address looks odd. My configs have this option commented out or 
set to 0xfffc000

what version of etherboot are you using ?


Regards
Mark.

>
> Regards
> Mark.
>
> On Thursday 10 Jul 2003 23:22, David Hendricks wrote:
> > I see a lot of people here have gotten LinuxBIOS working with the Via
> > EPIA using an IDE device, but has anyone managed to get it working using
> > etherboot to boot a kernel over a network? I'm a hopeless newbie and have
> > been struggling with this for some time. I have links to logs, my
> > payload, and my config below (Trying to keep the list archives tidy).
> >
> > I had gotten etherboot working with the PCM-5823s earlier and compared
> > the minicom log with that of my Epia. The only real obvious discrepency I
> > see is the entry point. The Geode entered at 0x00094000 (606,208), while
> > the Epia is trying to enter at 0x00020000 (131,072).
> >
> > I'm using CVS versions of Etherboot and LinuxBios. However, I haven't
> > been able to update in the past one or two weeks due to Sourceforge's
> > problems so I might have missed an important patch.
> >
> > Links
> > EPIA minicom log (High verbosity):
> > http://www.flagen.com/~sc/linux/funstuff/epia-dave
> > My Rhine payload:
> > http://www.flagen.com/~sc/linux/funstuff/via-rhine-ebcvs.elf
> > My config file: http://www.flagen.com/~sc/linux/funstuff/epia.config
> > Geode (Elfboot part only):
> > http://www.flagen.com/~sc/linux/funstuff/geode-elfboot-dave
> >
> > TIA
> > --David
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From sc at flagen.com  Thu Jul 10 19:08:00 2003
From: sc at flagen.com (David Hendricks)
Date: Thu Jul 10 19:08:00 2003
Subject: Any EPIA etherboot success stories?
In-Reply-To: <200307102338.53510.mwilkinson@ndirect.co.uk>
References: <44564.128.165.250.195.1057875722.squirrel@mail.flagen.com> 
     <200307102320.55874.mwilkinson@ndirect.co.uk> 
     <200307102338.53510.mwilkinson@ndirect.co.uk>
Message-ID: <45011.128.165.250.195.1057882345.squirrel@mail.flagen.com>

EPIA howto? I must've overlooked it in my extensive Googling.

I tried fff80000 because when I run flash_rom, it finds my SST28SF040A at
that address. I did notice, however, that you and Sone used fffc0000 for
the zkernel_start address. fff80000 does not seem to work at all, so I
guess the Epia specifically looks for that address.

My fault for not keeping the epia.config file exactly the same as it was
used in the minicom log. That's what I get for being a packrat and keeping
so many of them sitting around. The config I'm currently using is exactly
the same, but using fffc0000.

As for my etherboot version, it was originally downloaded using CVS on
June 25. I'm using version etherboot-5.1.

> On Thursday 10 Jul 2003 23:20, Mark Wilkinson wrote:
>> Hi David,
>> 	If you mean has anyone managed to boot a Via EPIA using etherboot as
>> the
>> payload, and loading the kernel via (no pun) tftp, then yes.... but then
>> I
>> wrote it all down in the EPIA howto :-)
>>
>
> oops, hit the wrong key there...
>
> what seems to be the problem that you're having ? your epia.config, the
> zkernel_start address looks odd. My configs have this option commented out
> or
> set to 0xfffc000
>
> what version of etherboot are you using ?
>
>
> Regards
> Mark.
>
>>
>> Regards
>> Mark.
>>
>> On Thursday 10 Jul 2003 23:22, David Hendricks wrote:
>> > I see a lot of people here have gotten LinuxBIOS working with the Via
>> > EPIA using an IDE device, but has anyone managed to get it working
>> using
>> > etherboot to boot a kernel over a network? I'm a hopeless newbie and
>> have
>> > been struggling with this for some time. I have links to logs, my
>> > payload, and my config below (Trying to keep the list archives tidy).
>> >
>> > I had gotten etherboot working with the PCM-5823s earlier and compared
>> > the minicom log with that of my Epia. The only real obvious
>> discrepency I
>> > see is the entry point. The Geode entered at 0x00094000 (606,208),
>> while
>> > the Epia is trying to enter at 0x00020000 (131,072).
>> >
>> > I'm using CVS versions of Etherboot and LinuxBios. However, I haven't
>> > been able to update in the past one or two weeks due to Sourceforge's
>> > problems so I might have missed an important patch.
>> >
>> > Links
>> > EPIA minicom log (High verbosity):
>> > http://www.flagen.com/~sc/linux/funstuff/epia-dave
>> > My Rhine payload:
>> > http://www.flagen.com/~sc/linux/funstuff/via-rhine-ebcvs.elf
>> > My config file: http://www.flagen.com/~sc/linux/funstuff/epia.config
>> > Geode (Elfboot part only):
>> > http://www.flagen.com/~sc/linux/funstuff/geode-elfboot-dave
>> >
>> > TIA
>> > --David
>> > _______________________________________________
>> > Linuxbios mailing list
>> > Linuxbios at clustermatic.org
>> > http://www.clustermatic.org/mailman/listinfo/linuxbios
>>
>> _______________________________________________
>> Linuxbios mailing list
>> Linuxbios at clustermatic.org
>> http://www.clustermatic.org/mailman/listinfo/linuxbios
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>



From ts1 at cma.co.jp  Fri Jul 11 03:07:00 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Fri Jul 11 03:07:00 2003
Subject: Any EPIA etherboot success stories?
In-Reply-To: <45011.128.165.250.195.1057882345.squirrel@mail.flagen.com>
References: <44564.128.165.250.195.1057875722.squirrel@mail.flagen.com> <200307102320.55874.mwilkinson@ndirect.co.uk> <200307102338.53510.mwilkinson@ndirect.co.uk> <45011.128.165.250.195.1057882345.squirrel@mail.flagen.com>
Message-ID: <20030711071742.GA3779@cma.co.jp>

On Thu, Jul 10, 2003 at 05:12:25PM -0700, David Hendricks wrote:
> EPIA howto? I must've overlooked it in my extensive Googling.

Look at freebios/HOWTO directory of your freebios tree.
I thought you've been aware of it.

> I tried fff80000 because when I run flash_rom, it finds my SST28SF040A at
> that address. I did notice, however, that you and Sone used fffc0000 for
> the zkernel_start address. fff80000 does not seem to work at all, so I
> guess the Epia specifically looks for that address.

SST28SF040A is 512KByte (4Mbit). 
I'm using 256KB part and as far as I know EPIA comes with 256KB part
installed so it's standard for EPIA.
If you use the 512KB part, you must change other values in the config.

--
Takeshi


From mwilkinson at ndirect.co.uk  Fri Jul 11 03:14:00 2003
From: mwilkinson at ndirect.co.uk (Mark Wilkinson)
Date: Fri Jul 11 03:14:00 2003
Subject: Any EPIA etherboot success stories?
In-Reply-To: <45011.128.165.250.195.1057882345.squirrel@mail.flagen.com>
References: <44564.128.165.250.195.1057875722.squirrel@mail.flagen.com> <200307102338.53510.mwilkinson@ndirect.co.uk> <45011.128.165.250.195.1057882345.squirrel@mail.flagen.com>
Message-ID: <200307110824.31272.mwilkinson@ndirect.co.uk>

On Friday 11 Jul 2003 01:12, David Hendricks wrote:
> EPIA howto? I must've overlooked it in my extensive Googling.

It's in the HOWTO directory from CVS.

>
> I tried fff80000 because when I run flash_rom, it finds my SST28SF040A at
> that address. I did notice, however, that you and Sone used fffc0000 for
> the zkernel_start address. fff80000 does not seem to work at all, so I
> guess the Epia specifically looks for that address.

Oh, you've got a 28SF040.... the chip my EPIA came with is a 39SF020A, which 
is half the size (hence using 0xfffc0000)

What you might need to do, is set the zkernel_start to 0xfff80000, AND set the 
ROM_SIZE to 524288.

why ? well, memory address is 0 to 0xffffffff which is a total of 0x100000000 
bytes. the bios rom sits at the top of this and extends from 0xffffffff down.
if your rom chip is 256K this will extend down my 0x40000 bytes ( to start at 
0xfffc0000)
as you rom is 512K, this will extend down by 0x80000 bytes (and start at the 
correctly used and found 0xfff80000)

There may be some magic in the Makefiles that works out the correct 
ZKERNEL_START from the rom size, but you will need to set the ROM_SIZE option 
to the size of your rom chip !

You may also have to increase the PAYLOAD_SIZE option by 256K

As to the version of etherboot, i've not used 5.1 to boot from the network, 
only used it to boot from a CF disk

regards Mark.

>
> My fault for not keeping the epia.config file exactly the same as it was
> used in the minicom log. That's what I get for being a packrat and keeping
> so many of them sitting around. The config I'm currently using is exactly
> the same, but using fffc0000.
>
> As for my etherboot version, it was originally downloaded using CVS on
> June 25. I'm using version etherboot-5.1.
>
> > On Thursday 10 Jul 2003 23:20, Mark Wilkinson wrote:
> >> Hi David,
> >> 	If you mean has anyone managed to boot a Via EPIA using etherboot as
> >> the
> >> payload, and loading the kernel via (no pun) tftp, then yes.... but then
> >> I
> >> wrote it all down in the EPIA howto :-)
> >
> > oops, hit the wrong key there...
> >
> > what seems to be the problem that you're having ? your epia.config, the
> > zkernel_start address looks odd. My configs have this option commented
> > out or
> > set to 0xfffc000
> >
> > what version of etherboot are you using ?
> >
> >
> > Regards
> > Mark.
> >
> >> Regards
> >> Mark.
> >>
> >> On Thursday 10 Jul 2003 23:22, David Hendricks wrote:
> >> > I see a lot of people here have gotten LinuxBIOS working with the Via
> >> > EPIA using an IDE device, but has anyone managed to get it working
> >>
> >> using
> >>
> >> > etherboot to boot a kernel over a network? I'm a hopeless newbie and
> >>
> >> have
> >>
> >> > been struggling with this for some time. I have links to logs, my
> >> > payload, and my config below (Trying to keep the list archives tidy).
> >> >
> >> > I had gotten etherboot working with the PCM-5823s earlier and compared
> >> > the minicom log with that of my Epia. The only real obvious
> >>
> >> discrepency I
> >>
> >> > see is the entry point. The Geode entered at 0x00094000 (606,208),
> >>
> >> while
> >>
> >> > the Epia is trying to enter at 0x00020000 (131,072).
> >> >
> >> > I'm using CVS versions of Etherboot and LinuxBios. However, I haven't
> >> > been able to update in the past one or two weeks due to Sourceforge's
> >> > problems so I might have missed an important patch.
> >> >
> >> > Links
> >> > EPIA minicom log (High verbosity):
> >> > http://www.flagen.com/~sc/linux/funstuff/epia-dave
> >> > My Rhine payload:
> >> > http://www.flagen.com/~sc/linux/funstuff/via-rhine-ebcvs.elf
> >> > My config file: http://www.flagen.com/~sc/linux/funstuff/epia.config
> >> > Geode (Elfboot part only):
> >> > http://www.flagen.com/~sc/linux/funstuff/geode-elfboot-dave
> >> >
> >> > TIA
> >> > --David
> >> > _______________________________________________
> >> > Linuxbios mailing list
> >> > Linuxbios at clustermatic.org
> >> > http://www.clustermatic.org/mailman/listinfo/linuxbios
> >>
> >> _______________________________________________
> >> Linuxbios mailing list
> >> Linuxbios at clustermatic.org
> >> http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Fri Jul 11 10:44:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 11 10:44:01 2003
Subject: Any EPIA etherboot success stories?
In-Reply-To: <200307102338.53510.mwilkinson@ndirect.co.uk>
Message-ID: <Pine.LNX.4.44.0307110854350.22296-100000@maxroach.lanl.gov>

On Thu, 10 Jul 2003, Mark Wilkinson wrote:

> what seems to be the problem that you're having ? your epia.config, the 
> zkernel_start address looks odd. My configs have this option commented out or 
> set to 0xfffc000

it's a 512KB part. Is this not addressable on this board?

ron



From YhLu at tyan.com  Fri Jul 11 22:31:01 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jul 11 22:31:01 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
Message-ID: <3174569B9743D511922F00A0C943142302DD0F25@TYANWEB>

Eric,

I switch to RH preview AMD 64 to build the kernel now the MB can finish the
booting.

I also try to boot local HD in normal boot.  I use hda1 to store elf (
Kernel+RAM disk). But LinuxBIOS seems don't recogonize the elf format. And
failed. 

I have use tg3.zelf to substitute the elf in the HD. LinuxBIOS can load it
from HD and execute it.

Any idea to produce ELF for HD booting. Or LinuxBIOS now only support 23bit
elf?

Regards

Yinghai Lu



From ebiederman at lnxi.com  Fri Jul 11 22:58:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jul 11 22:58:00 2003
Subject: freebios2 and $Id:
Message-ID: <m3brw030h2.fsf@maxwell.lnxi.com>

Unless someone has something to say in defense of the $Id: construct I
am hereby banning it from the freebios2 tree.  It makes it a pain
to maintain a secondary CVS tree in sync as there are multiple
unnecessary hits.  

Didn't we already ban $Id: ? in freebios2.

In any case a huge lot of them had slipped in and I have removed all
of them from the tree.  And I intend to keep doing that when ever I
find more of them.

Eric



From ebiederman at lnxi.com  Fri Jul 11 23:01:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jul 11 23:01:01 2003
Subject: ANN: arima hdama boots...
Message-ID: <m37k6o30ay.fsf@maxwell.lnxi.com>

I have finally gotten all of the hard codes out of the memory
initialization code and I can get the Arima HDAMA dual Opteron
motherboard booting.  And I have checked in the code.  There is a lot
more to do including cleanup of the code that works but one major
piece is done.

Eric



From ebiederman at lnxi.com  Fri Jul 11 23:19:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jul 11 23:19:00 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
In-Reply-To: <3174569B9743D511922F00A0C943142302DD0F25@TYANWEB>
References: <3174569B9743D511922F00A0C943142302DD0F25@TYANWEB>
Message-ID: <m38yr4whfi.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I switch to RH preview AMD 64 to build the kernel now the MB can finish the
> booting.
> 
> I also try to boot local HD in normal boot.  I use hda1 to store elf (
> Kernel+RAM disk). But LinuxBIOS seems don't recogonize the elf format. And
> failed. 

Hmm. Odd.  OTOH I have serious suspicions about the general reliability of
ide_stream.c
 
> I have use tg3.zelf to substitute the elf in the HD. LinuxBIOS can load it
> from HD and execute it.

Cool.  I am still wresting with a strange 8131 issue that is slowing that
part down for me.  But I do have an eepro100 working when plugged in.
 
> Any idea to produce ELF for HD booting. Or LinuxBIOS now only support 23bit
> elf?

Well there is not 23bit elf :)

The etherboot code ide_disk.zelf or something like tg3--ide_disk.zelf should
work and supports both 32bit and 64bit binaries.

Currently the builtin ELF loader can either be compiled for 32bit of 64bit ELF
but it cannot handle both simultaneously and the choice is made depending
on the platform LinuxBIOS was compiled for.

Earlier you said you had gotten SMP working.  Would you like to share the
patch?

Eric



From tuguangxiu at yahoo.com  Sat Jul 12 00:54:00 2003
From: tuguangxiu at yahoo.com (tu guangxiu)
Date: Sat Jul 12 00:54:00 2003
Subject: how to set 100 FSB for sis630
Message-ID: <20030712050432.59127.qmail@web13303.mail.yahoo.com>

I need my winfast6300( using sis630 )to support 100M
FSB.
I know that there is sis630.reg, who has some glues to

set FSB from 66 to 100 in sis630.reg or other file?

thanks

__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
http://sbc.yahoo.com


From ijpriya at hotmail.com  Sat Jul 12 05:27:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Sat Jul 12 05:27:01 2003
Subject: files to be placed in target.
Message-ID: <BAY2-F816Ci6nx8dyDd0000085a@hotmail.com>

Hello,
     These are the files in my build directory when I built my linuxbios for 
geode sc1200. I don't use DOC.

boot.o                 isa-dma.o              linuxbios_payload.nrv2b  nrv2b
clog2.o                keyboard.o             linuxbios.rom            
nsuperio.c
compute_ip_checksum.o  ldoptions              linuxbios.strip          
params.o
cpuid.o                ldscript.ld            linuxbios_table.o        
payload.block
crt0_includes.h        linux.bin.gz           linuxpci.o               
printk.o
crt0.o                 linuxbios              mainboard.o              
rom_fill_inbuf.o
crt0.s                 linuxbios.a            Makefile                 
romimage
crt0.S                 linuxbios_c            Makefile.settings        
serial_subr.o
c_start.o              linuxbios_c.map        malloc.o                 
southbridge.o
c_start.s              linuxbios_c.o          mc146818rtc.o            
subr.o
delay.o                LinuxBIOSDoc.config    memcmp.o                 
version.o
do_inflate.o           linuxbiosmain.o        memcpy.o                 
vsprintf.o
hardwaremain.o         linuxbios.map          memset.o
i386_subr.o            linuxbios_payload      newpci.o
ide.o                  linuxbios_payload.bin  northbridge.o

             Out of these files, plz tell what for each of the following 
files stands for:
linux.bin.gz
linuxbios (executable file)
linuxbios.a (contains many .o files)
linuxbios_c (executable file)
linuxbios_payload (unknown type)
linuxbios_payload.bin
linuxbios.nrv2b
linuxbios.rom
linuxbios.strip
nrv2b(executable)
payload.block(Gzip file)
romimage (Gzip file)

        Out of these files which files are to be placed in the target?

	Thanks in advance for any help in advance.

_________________________________________________________________
Polyphonic ringtones. Latest movie trailors. 
http://server1.msn.co.in/sp03/gprs/index.asp On your mobile!



From ijpriya at hotmail.com  Sat Jul 12 05:30:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Sat Jul 12 05:30:01 2003
Subject: audio support?
Message-ID: <BAY2-F141RQwGF5ucvp00004576@hotmail.com>

Hello,

     It is said that audio support is not good in geode sc1200 using 
linuxbios. Then to get audio support what actions to be done?

Thanks in advance for any help!

_________________________________________________________________
Are you a geek? Do gizmos make you grin? 
http://www.msn.co.in/Computing/Gizmos/ Click here!



From root at hamburg.de  Sat Jul 12 06:58:00 2003
From: root at hamburg.de (Felix Kloeckner)
Date: Sat Jul 12 06:58:00 2003
Subject: Linuxbios, bugfix in sis flash_rom
In-Reply-To: <Pine.LNX.4.44.0307090849180.3047-100000@maxroach.lanl.gov>; from rminnich@lanl.gov on Wed, Jul 09, 2003 at 16:49:39 +0200
References: <20030709111107.A848@synapse.pentanet> <Pine.LNX.4.44.0307090849180.3047-100000@maxroach.lanl.gov>
Message-ID: <20030712130615.A6379@synapse.pentanet>

hello,

it't working, but i think other files lacks the same problem. if i find some
time i will correct them.

Felix

On 2003.07.09 16:49 ron minnich wrote:
> fixed and committed, please test.
> 
> ron
> 
> p.s. we're getting close to freeze, I figure when we get the K7SEM fix in 
> we're done on 1.0.1
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
> 


From bgr at gw.linespeed.net  Sat Jul 12 18:34:00 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Sat Jul 12 18:34:00 2003
Subject: audio support?
In-Reply-To: <BAY2-F141RQwGF5ucvp00004576@hotmail.com>
References: <BAY2-F141RQwGF5ucvp00004576@hotmail.com>
Message-ID: <Pine.LNX.4.53.0307121742190.10402@gw.linespeed.net>

Use the OSS or ALSA drivers from national's website.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Sat, 12 Jul 2003, Devi Priya wrote:

> Hello,
>
>      It is said that audio support is not good in geode sc1200 using
> linuxbios. Then to get audio support what actions to be done?
>
> Thanks in advance for any help!
>
> _________________________________________________________________
> Are you a geek? Do gizmos make you grin?
> http://www.msn.co.in/Computing/Gizmos/ Click here!
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From xpegenaute at telepolis.es  Sun Jul 13 08:16:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Sun Jul 13 08:16:01 2003
Subject: VGA
Message-ID: <1058102423.511.8.camel@p-133>

Hi,

i have some questions about VGA in LinuxBios. If we don't use ADLO,
there is'nt VGA Bios, then the unique possibility to see something in in
Linux with the VGA is that we have implemented a FrameBuffer driver for
the specific VGA board, and ofcourse that this driver has to talk
directly with the hardware. And what about the Xserver ? the X software
talk directly with the hardware ?

For example if i want to mount a little computer in my home to see DVDs
and Divx, is it possible with LinuxBios?

Thanks.
Xavi.



From gwatson at lanl.gov  Sun Jul 13 11:42:01 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Sun Jul 13 11:42:01 2003
Subject: ppc linuxbios support
In-Reply-To: <000801c348ae$ef920760$65fda8c0@kramlin>
References: <000801c348ae$ef920760$65fda8c0@kramlin>
Message-ID: <p06001a03bb37294bfdad@[10.0.1.2]>

Hi Ramkumar,

Ports to new boards, or suggestions on how to make the PPC code more 
modular and robust are always appreciated.

You might want to start by getting linuxbios booting a linux kernel 
on the 755. This shouldn't be too difficult, as the 755 appears to 
use the same northbridge as the 7410. I used the MontiVista linux as 
it was already ported to the Sandpoint, though I had to make a few 
patches to get it to boot with linuxbios. Let me know when you get to 
this point and I can send you the patches.

I've just ordered an EP405PC from EmbeddedPlanet which will be my 
next port. It uses the IBM PPC 405Gpr chip which is sufficiently 
different to the 7410 to be challenging.

Hopefully this week I'll have the PPC version working under the new 
configuration system (check out freebios2 instead of freebios). This 
is going to allow us to build a static device tree which can be 
passed to linux. Heiko Schick and I have been discussing the 
possibility of mapping this device tree to an Open Firmware device 
tree that can then be used to boot linux on an OF system (such as 
Power Mac's).

Stefan Reinauer has reminded me that we should work with the openbios 
community on this, though looking at the IEEE 1275 spec (all 250+ 
pages) I think they've got a big job ahead. :-)

Cheers,

Greg


>I would be interested in helping out in the testing/development of 
>the PPC BIOS. Also, have access to sandpoint 755. Let me know if I 
>can help.
>
>Thanks
>
>Ramkumar
-------------- next part --------------
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From agnew at cs.umd.edu  Sun Jul 13 12:49:01 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Sun Jul 13 12:49:01 2003
Subject: VGA
In-Reply-To: <1058102423.511.8.camel@p-133>
Message-ID: <20030713130815.E37380-100000@www.missl.cs.umd.edu>

You can get VGA through just LinuxBIOS too. Find Richard Smith's FAQ on
this mailing list archive and I think it covers how. And for watching
DVDs, you can either use Mplayer's frame buffer output method, Mplayer's
directfb output method, or Xfree86's fbdev. But you're right, if you get
the vga bios working through linuxbios or adlo/bochs, you wont have to
worry about framebuffers.

- Adam A.

On 13 Jul 2003, Xavier Pegenaute wrote:

> Hi,
>
> i have some questions about VGA in LinuxBios. If we don't use ADLO,
> there is'nt VGA Bios, then the unique possibility to see something in in
> Linux with the VGA is that we have implemented a FrameBuffer driver for
> the specific VGA board, and ofcourse that this driver has to talk
> directly with the hardware. And what about the Xserver ? the X software
> talk directly with the hardware ?
>
> For example if i want to mount a little computer in my home to see DVDs
> and Divx, is it possible with LinuxBios?
>
> Thanks.
> Xavi.
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>



From rminnich at lanl.gov  Sun Jul 13 13:17:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jul 13 13:17:00 2003
Subject: VGA
In-Reply-To: <20030713130815.E37380-100000@www.missl.cs.umd.edu>
Message-ID: <Pine.LNX.4.44.0307131126070.29905-100000@maxroach.lanl.gov>

David Hendriks, working here this summer, is going to be trying to get the 
Nvidia N35 going on a P4 system with the native LinuxBIOS VGA support. He 
is wrapping up the EPIA now, recreating the the work others have done for 
VGA on that system, and learning all the ins and outs of that platform.

Poor David, I just blew his cover :-)

ron



From YhLu at tyan.com  Mon Jul 14 19:10:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 14 19:10:01 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
Message-ID: <3174569B9743D511922F00A0C943142302DD0FD4@TYANWEB>

Eric,

I have tried to build the tg3--ide_disk.zelf and use it in fallback and
normal but all failed.

In fallback track:
It said: Searching for image...................................<abort>

In Normal track:
It said: Wrong index
I have use to cmos_util to change boot track and BOOT_FIRST=HDD and
BOOT_SECOND=Network.

When building tg3--ide_disk.zelf, I used BOOT_FIRST=IDE and BOOT_SECOND=NIC.

What kind of image in HDD that eltherboot wound want?

Regards

Yinghai Lu


Fallback:
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

Found ELF candiate at offset 0
Loading Etherboot version: 5.1.8
Dropping non PT_LOAD segment
New segment addr 0x20000 size 0x3586f offset 0xb0 filesize 0x5d65
(cleaned up) New segment addr 0x20000 size 0x3586f offset 0xb0 filesize
0x5d65
Loading Segment: addr: 0x0000000000020000 memsz: 0x000000000003586f filesz:
0x00
00000000005d65
Clearing Segment: addr: 0x0000000000025d65 memsz: 0x000000000002fb0a
Jumping to boot code at 0x20000
ROM segment 0x33cc length 0x9842 reloc 0x00020000
CPU 1859 Mhz
Etherboot 5.1.8 (GPL) Tagged ELF (Multiboot) for [TG3][IDE]
Relocating _text from: [00025d70,00056480) to [5ffcf8f0,60000000)
Probing pci disk...
[IDE]disk-1 80043264k cap: 2f00
Searching for image...
................................<abort>
Probing pci disk...
[IDE]Probing isa disk...
Probing pci nic...
[TG3]Cannot find PowerManagement capability, aborting.
[TG3]Ethernet addr: 00:E0:81:52:6C:56
Tigon3 [partno(BCM95704A7) rev 2003 PHY(5704)] (PCIX:100MHz:64-bit)
Link is up at 100 Mbps, half duplex.
Searching for server (DHCP)...
..Me: 192.168.1.200, Server: 192.168.1.1, Gateway 192.168.1.1
Loading 192.168.1.1:ram0_2.5_2.4.21_k8_lsi_mydisk4.elf ...(ELF)..


Normal:

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

Found ELF candiate at offset 0
Loading Etherboot version: 5.1.8
Dropping non PT_LOAD segment
New segment addr 0x20000 size 0x3586f offset 0xb0 filesize 0x5d65
(cleaned up) New segment addr 0x20000 size 0x3586f offset 0xb0 filesize
0x5d65
Loading Segment: addr: 0x0000000000020000 memsz: 0x000000000003586f filesz:
0x00
00000000005d65
Clearing Segment: addr: 0x0000000000025d65 memsz: 0x000000000002fb0a
Jumping to boot code at 0x20000
ROM segment 0x0000 length 0x0000 reloc 0x00020000
CPU 1870 Mhz
Etherboot 5.1.8 (GPL) Tagged ELF (Multiboot) for [TG3][IDE]
Relocating _text from: [00025d70,00056480) to [5ffcf8f0,60000000)
Probing pci disk...
[IDE]disk-1 80043264k cap: 2f00
Wrong index
Probing pci disk...
[IDE]Probing isa disk...
Probing pci nic...
[TG3]Cannot find PowerManagement capability, aborting.
[TG3]Ethernet addr: 00:E0:81:52:6C:56
Tigon3 [partno(BCM95704A7) rev 2003 PHY(5704)] (PCIX:100MHz:64-bit)
Link is up at 100 Mbps, half duplex.
Searching for server (DHCP)...
..Me: 192.168.1.200, Server: 192.168.1.1, Gateway 192.168.1.1
Loading 192.168.1.1:ram0_2.5_2.4.21_k8_lsi_mydisk4.elf ...(ELF)...
.............
...........................................................................


From ebiederman at lnxi.com  Mon Jul 14 21:09:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul 14 21:09:00 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
In-Reply-To: <3174569B9743D511922F00A0C943142302DD0FD4@TYANWEB>
References: <3174569B9743D511922F00A0C943142302DD0FD4@TYANWEB>
Message-ID: <m3el0sfuus.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have tried to build the tg3--ide_disk.zelf and use it in fallback and
> normal but all failed.
> 
> In fallback track:
> It said: Searching for image...................................<abort>
> 
> In Normal track:
> It said: Wrong index
> I have use to cmos_util to change boot track and BOOT_FIRST=HDD and
> BOOT_SECOND=Network.

Yes. It only pays attention to the variables in Normal mode.

> When building tg3--ide_disk.zelf, I used BOOT_FIRST=IDE and BOOT_SECOND=NIC.
> 
> What kind of image in HDD that eltherboot wound want?

An ELF image within 8K from the start of the DISK.  Imperfect but it works.

Eric



From ollie at sis.com.tw  Mon Jul 14 21:48:00 2003
From: ollie at sis.com.tw (ollie lho)
Date: Mon Jul 14 21:48:00 2003
Subject: VGA
In-Reply-To: <Pine.LNX.4.44.0307131126070.29905-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307131126070.29905-100000@maxroach.lanl.gov>
Message-ID: <1058233499.26058.135.camel@ollie>

On Mon, 2003-07-14 at 01:28, ron minnich wrote:
> David Hendriks, working here this summer, is going to be trying to get the 
> Nvidia N35 going on a P4 system with the native LinuxBIOS VGA support. He 
> is wrapping up the EPIA now, recreating the the work others have done for 
> VGA on that system, and learning all the ins and outs of that platform.
> 

Did you get any docs for Nvidia ? Or you have to do it the hard way ?

-- 
ollie lho <ollie at sis.com.tw>



From rminnich at lanl.gov  Mon Jul 14 22:57:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 14 22:57:00 2003
Subject: VGA
In-Reply-To: <1058233499.26058.135.camel@ollie>
Message-ID: <Pine.LNX.4.44.0307142108210.5074-100000@maxroach.lanl.gov>

On 15 Jul 2003, ollie lho wrote:

> Did you get any docs for Nvidia ? Or you have to do it the hard way ?

The Hard Way. But within the limits of The Hard Way, Nvidia is being very 
nice to us.

ron



From YhLu at tyan.com  Mon Jul 14 23:10:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 14 23:10:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302DD1039@TYANWEB>

Eric,

Thanks, I change 8k to 40k and it works. Because I put the elf in hda1.

In the Config of Ehterboot, I have set BOOT_FIRST=BOOT_DISK and
BOOT_SECOND=BOOT_NIC.
In the fallback track, It works great and if HD is not there is will boot
from Network.
About the normal boot, it seems there some problems. After change the
cmos.conf. boot_option=Normal
boot_first=HDD
boot_second=HDD
boot_third=Network

Then corresponding to BOOT_FIRST it says that "Wrong index" ???
When the HDD is present, it works as touch pci_ide (find one HD and print
"Wrong index")/ isa_ide/ pci_ide and load image from ide.
And When the HDD is not present , it works as touch pci_ide/isa_ide/pci_nic
and load image from ide.

Is it because boot_first should be set Network fixedly?
In the main.c of Etherboot, it only at state=3 and index=0 and type
mismatched can print such "Wrong index", 

It is a bug in Etherboot 5.1.8.?

Regards

Yinghai Lu


-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?7?14? 18:21
???: YhLu
??: ron minnich; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have tried to build the tg3--ide_disk.zelf and use it in fallback and
> normal but all failed.
> 
> In fallback track:
> It said: Searching for image...................................<abort>
> 
> In Normal track:
> It said: Wrong index
> I have use to cmos_util to change boot track and BOOT_FIRST=HDD and
> BOOT_SECOND=Network.

Yes. It only pays attention to the variables in Normal mode.

> When building tg3--ide_disk.zelf, I used BOOT_FIRST=IDE and
BOOT_SECOND=NIC.
> 
> What kind of image in HDD that eltherboot wound want?

An ELF image within 8K from the start of the DISK.  Imperfect but it works.

Eric


From ijpriya at hotmail.com  Tue Jul 15 02:02:00 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Tue Jul 15 02:02:00 2003
Subject: ide-spinup.patch
Message-ID: <BAY2-F117AW2m8grRfZ0000c69e@hotmail.com>

Hello,

       I am using the kernel version 2.4.18-14. I guess the patch 
ide-spinup.patch is given for 2.4.7 . Can I apply the same patch to the 
kernel 2.4.18-14? Else what patch shall I apply for 2.4.18-14? Plzzz help 
me.

Thanks in advance for any help!

_________________________________________________________________
It's new, it's here! It's full of fun! 
http://server1.msn.co.in/sp03/messengerpromo/index.asp MSN Messenger V6.0



From ebiederman at lnxi.com  Tue Jul 15 03:37:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jul 15 03:37:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <3174569B9743D511922F00A0C943142302DD1039@TYANWEB>
References: <3174569B9743D511922F00A0C943142302DD1039@TYANWEB>
Message-ID: <m3u19o2prg.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Thanks, I change 8k to 40k and it works. Because I put the elf in hda1.
> 
> In the Config of Ehterboot, I have set BOOT_FIRST=BOOT_DISK and
> BOOT_SECOND=BOOT_NIC.
> In the fallback track, It works great and if HD is not there is will boot
> from Network.
> About the normal boot, it seems there some problems. After change the
> cmos.conf. boot_option=Normal
> boot_first=HDD
> boot_second=HDD
> boot_third=Network
> 
> Then corresponding to BOOT_FIRST it says that "Wrong index" ???
> When the HDD is present, it works as touch pci_ide (find one HD and print
> "Wrong index")/ isa_ide/ pci_ide and load image from ide.
> And When the HDD is not present , it works as touch pci_ide/isa_ide/pci_nic
> and load image from ide.
> 
> Is it because boot_first should be set Network fixedly?
> In the main.c of Etherboot, it only at state=3 and index=0 and type
> mismatched can print such "Wrong index", 
> 
> It is a bug in Etherboot 5.1.8.?

The semantics are there is a boot_index variable.  boot_index
only applies to the type of device selected with boot_first.

if (boot_index != 0) then it will walk through the devices it
finds of the appropriate type 1,2,3,4... until its count matches
boot_index.  This allows you to specify exactly which device you want
to boot from.  

If it can't boot from the first device it tries the second and third
etc.  How is that patch coming?

Eric



From xpegenaute at telepolis.es  Tue Jul 15 05:49:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Jul 15 05:49:00 2003
Subject: VGA
In-Reply-To: <Pine.LNX.4.44.0307142108210.5074-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307142108210.5074-100000@maxroach.lanl.gov>
Message-ID: <1058266419.717.7.camel@p-133>

On Tue, 2003-07-15 at 05:08, ron minnich wrote:
> On 15 Jul 2003, ollie lho wrote:
> 
> > Did you get any docs for Nvidia ? Or you have to do it the hard way ?
> 
> The Hard Way. But within the limits of The Hard Way, Nvidia is being very 
> nice to us.

Hard Way ?, is something like sniff the dialog of the VGA with the
processor ?

Xavi.



From aip at cwlinux.com  Tue Jul 15 07:08:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jul 15 07:08:00 2003
Subject: DDR problem
Message-ID: <20030715191936.A27108@mail.cwlinux.com>

Hi,

	I'm testing 2 DDR from Samsung on EPIA-M, M368L1713DTL-CB0 and
M368L1624DTL-CB0.  Both of them are DDR266 128MB.  The main different is
M368L1713DTL-CB0 has 8x16MB IC's and M368L1624DTL-CB0 has 4x32MB IC's.
So far, LinuxBIOS can boot flawlessly with M368L1713DTL-CB0.  However,
it fails when running ram test.  Here is the log

dump northbridge:
00: 06 11 23 31 06 00 30 02 00 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00
50: c8 de cf 88 c0 04 00 00 6c 00 08 08 10 10 00 00
60: 0a 00 00 00 e6 32 01 20 c5 25 43 58 00 44 00 00
70: 82 48 00 01 01 08 50 00 01 00 00 00 00 00 02 02
80: 00 61 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 c0 20 00 01 02 00 1f 00 00 00 00 00 02 00 00
b0: 00 00 00 00 80 00 00 00 68 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 01 00 40 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 03 13 00 00 00 00 00 00 00 00
Done.
Testing SDRAM : 00000000-0009ffff
SDRAM fill:
0009ffff
SDRAM verify:
00000000:00001000
00000004:00001004
00000008:00001008
0000000c:0000100c
00000010:00001010
00000014:00001014
00000018:00001018
0000001c:0000101c
00000020:00001020
00000024:00001024
00000028:00001028
0000002c:0000102c
00000030:00001030
00000034:00001034
00000038:00001038
0000003c:0000103c
Too many errors.

BTW, normal bios doesn't have this problem.  And I have also compared 
settings between regular and LinuxBIOS bios, even double check with DDR 
init sequence.  I haven't found anything strange yet.  Have any seen this 
kind of strange behavior?

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From ijpriya at hotmail.com  Tue Jul 15 07:17:00 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Tue Jul 15 07:17:00 2003
Subject: LinuxBios-help!
Message-ID: <BAY2-F74eeFUtLch9wP000046ce@hotmail.com>

Hi,

     I am unable to understand many things here. I am using sc1200. External 
devices include 32 MB SDRAM, 4 MB Flash ROM, Ethernet, PCI audio/video 
decoder, FI1216-Tuner, LM4550-Audio codec, hard disk. I probably want to 
load linux from hard disk. If i want to use linuxbios for my project what 
are the things should be done?
I dont use Disk on chip.
Plz I have very limited knowledge reg this linuxbios. Help me to understand.

_________________________________________________________________
Astrology can be fun. Find out for yourself. 
http://www.msn.co.in/Astrology/Astromagic/ With just a click!



From aip at cwlinux.com  Tue Jul 15 07:34:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jul 15 07:34:01 2003
Subject: LinuxBios-help!
In-Reply-To: <BAY2-F74eeFUtLch9wP000046ce@hotmail.com>; from Devi Priya on Tue, Jul 15, 2003 at 11:28:54AM +0000
References: <BAY2-F74eeFUtLch9wP000046ce@hotmail.com>
Message-ID: <20030715194502.A27552@mail.cwlinux.com>

Hi Devi,

>      I am unable to understand many things here. I am using sc1200. External 
> devices include 32 MB SDRAM, 4 MB Flash ROM, Ethernet, PCI audio/video 
> decoder, FI1216-Tuner, LM4550-Audio codec, hard disk. I probably want to 
> load linux from hard disk. If i want to use linuxbios for my project what 
> are the things should be done?
> I dont use Disk on chip.
> Plz I have very limited knowledge reg this linuxbios. Help me to understand.
You probably want to use scx200 as a base.  Then, work on the serial, then
memory, then irq,...  Serial port is very helpfully for debugging.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Tue Jul 15 10:02:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 15 10:02:01 2003
Subject: VGA
In-Reply-To: <1058266419.717.7.camel@p-133>
Message-ID: <Pine.LNX.4.44.0307150813030.10013-100000@maxroach.lanl.gov>

On 15 Jul 2003, Xavier Pegenaute wrote:

> Hard Way ?, is something like sniff the dialog of the VGA with the
> processor ?

The Hard Way is calling the VGA bios and supporting it in linuxbios.

ron



From xpegenaute at telepolis.es  Tue Jul 15 13:10:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Jul 15 13:10:00 2003
Subject: VGA
In-Reply-To: <Pine.LNX.4.44.0307150813030.10013-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307150813030.10013-100000@maxroach.lanl.gov>
Message-ID: <1058292858.1628.2.camel@p-133>

On Tue, 2003-07-15 at 16:13, ron minnich wrote:
> On 15 Jul 2003, Xavier Pegenaute wrote:
> 
> > Hard Way ?, is something like sniff the dialog of the VGA with the
> > processor ?
> 
> The Hard Way is calling the VGA bios and supporting it in linuxbios.

I don't know where is the hard way, may be i dind'tn understend, but
copy the bios into a binary image copy in memory, and put the int10 to
the correct position, is this the hard way ?

Thanks.
Xavi.



From rminnich at lanl.gov  Tue Jul 15 13:32:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 15 13:32:00 2003
Subject: VGA
In-Reply-To: <1058292858.1628.2.camel@p-133>
Message-ID: <Pine.LNX.4.44.0307151142590.10435-100000@maxroach.lanl.gov>

On 15 Jul 2003, Xavier Pegenaute wrote:

> I don't know where is the hard way, may be i dind'tn understend, but
> copy the bios into a binary image copy in memory, and put the int10 to
> the correct position, is this the hard way ?

no, I'll try to explain later.

ron



From rminnich at lanl.gov  Tue Jul 15 13:36:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 15 13:36:00 2003
Subject: building HDAMA the old way and the new way: 
Message-ID: <Pine.LNX.4.44.0307151144080.10435-100000@maxroach.lanl.gov>

The jmp for fallback is wrong from what I can see. At 0xffff0 I have this:
   0:   e9 11 00 00 00          jmp    0x16

in other words, the segment is 0000, not f000. 

The 32-bit is ok:
   0:   e9 5b 00 ff ff          jmp    0xffff0060

This is happening with both old and new config tools.

the _start symbol is a T symbol at 0xffff0004 in linuxbios.map. 

The correct ldscript.ld files are being loaded. 

Any suggestions?

thanks

ron



From ferenc at engard.hu  Tue Jul 15 15:59:01 2003
From: ferenc at engard.hu (Ferenc Engard)
Date: Tue Jul 15 15:59:01 2003
Subject: Geode GX1 processor?
In-Reply-To: <Pine.LNX.4.44.0307100749160.11863-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.40.0307101623270.24460-100000@korus.hu>

Sorry for being late, my router / mail server has hardware problems. :-(

> > A bit offtopic: I am looking for a forum/mailing list/people who are work
> > with this processor, especially with its 2d video accel on linux. I have
> > problems, NSC didn't respond, and I stucked... :-(
>
> you can split a list off for geode, but we're interested here, and I would
> welcome a discussion on this list -- it's not a high traffic list.

I know, it's a refreshment after lkml, or, say, comp.lang.tcl. :-)

So, my problem is not related to linuxbios (maybe there will be one time,
if we decide to use this processor for our product).

I have an Advantech PCM-5820 board, with GX1 and CS5530, and I play with
it to test it's hardware bitblt feature. I have patched the 2.4.17 kernel
with NSC's geodefb driver, compiled a user-space GAL lib. I wrote a
program to move a part of the screen, the usleep a short interval (aka
scrolling a region). I know that this is not nice as the GX1 spec said
that I should not use the fb while the bitblt engine is working, and
because I have fb console, the console writes into it (it do not know
about the bitblt engine), but there was no problem, the center of the
screen scrolled like a dream, just when I typed something, there were 1-1
pixel errors.

The problem was when I decided to check the memory bandwidth, and issued a
dd if=/dev/mem of=/dev/null bs=1024 count=16384
command. Sometimes (about every 2nd time) it completely freezes the
machine. No oops, no kernel panic, just freeze to death. :-(  And I do not
understand what is going on, because if I do not scroll, there is no such
problem, and the bitblt operation just means to write some values into
some (processor-handled) IO registers.

What could be the problem? How to debug? What 'dd if=/dev/mem ...' exactly
do? Many questions, and I have not answers. What a philosophical work is
ours... :-)

Thanks:
Circum





From mmmooretx at earthlink.net  Tue Jul 15 17:05:00 2003
From: mmmooretx at earthlink.net (mmmooretx at earthlink.net)
Date: Tue Jul 15 17:05:00 2003
Subject: AMD64 & LinuxBIOS
Message-ID: <811345.1058303766007.JavaMail.nobody@bert.psp.pas.earthlink.net>

I am interested in assembling a CAD/CAM & Gaming machine for my home LAN.  The chip is due out mid Sept.  I have no details on the motherboard yet.  I run SuSE 8.2 Pro at home now.  Any inputs would be appreciated, rumors too...  If there was an Opteron motherboard with an AGP slot I'd go down that path...


From agnew at cs.umd.edu  Tue Jul 15 20:15:01 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Tue Jul 15 20:15:01 2003
Subject: AMD64 & LinuxBIOS
In-Reply-To: <811345.1058303766007.JavaMail.nobody@bert.psp.pas.earthlink.net>
Message-ID: <20030715202956.H49943-100000@www.missl.cs.umd.edu>


On Tue, 15 Jul 2003 mmmooretx at earthlink.net wrote:

> I am interested in assembling a CAD/CAM & Gaming machine for my home
> LAN.  The chip is due out mid Sept.  I have no details on the
> motherboard yet.  I run SuSE 8.2 Pro at home now.  Any inputs would be
> appreciated, rumors too...  If there was an Opteron motherboard with an
> AGP slot I'd go down that path...

I believe the ASUS SK8N is what you want. It's available at myinfinity.com
it seems. However, I couldn't find the board on ASUS's website.
- Adam A.



From xpegenaute at telepolis.es  Wed Jul 16 06:45:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Wed Jul 16 06:45:01 2003
Subject: document
Message-ID: <3F153BB3.20507@telepolis.es>

Hi,

i almost finnished the documentation that i collected about LinuxBios, 
you can see this in http://www-est-fib.upc.es/~e6058836/projecte.pdf, 
i'm open to critics, suggestions, etc ..., in this document only i put 
the information that for me was useful to understand LinuxBios.

I think that it can be better if i put some information about PCI (i 
have no time for this at the moment), for the rest, i think it's enough.

Thanks a lot.
Xavi.



From xpegenaute at telepolis.es  Wed Jul 16 07:10:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Wed Jul 16 07:10:00 2003
Subject: Document (with the correct link)
Message-ID: <3F15419C.9020500@telepolis.es>

http://www-est.fib.upc.es/~e6058836/projecte.pdf

Sorry.
Xavi.



From nick.jarmany at densitron.co.uk  Wed Jul 16 19:52:00 2003
From: nick.jarmany at densitron.co.uk (Nick Jarmany)
Date: Wed Jul 16 19:52:00 2003
Subject: Recommendations for ROM/Flash emulator
Message-ID: <0AC9329AE6A1194AB949C6EB075F561508A20D@bhsv3.densitron.co.uk>

Can anyone give some recommendations on ROM emulator hardware?
 
We want to get stuck into LinuxBIOS on a new board design using the
SiS661FX, but would like to ease the process of recovering from broken
code. A decent emulator with fast download speed and an auto-reset would
seem to be the way to go.
 
Does anyone have suitable hardware that they would thorougly recommend?
 
Nick
 
P.S. Ollie - are you doing any work on the newer SiS chipsets? Is your
work confined just to LinuxBIOS or do you have other interests in the
Linux field related to SiS hardware, e.g. graphics?

*************************************************

Registered Office:

Densitron Technologies P.L.C.

Unit 4
Airport Trading Estate
Biggin Hill
Westerham
Kent

TN16 3BW

Telephone (01959) 542000
Facsimile (01959) 542001

www.densitron.com


Disclaimer Statement
--------------------

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From ijpriya at hotmail.com  Wed Jul 16 23:41:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Wed Jul 16 23:41:01 2003
Subject: files to be placed in target?
Message-ID: <BAY2-F4723PDH8qHNwK00006140@hotmail.com>

Hello,


           I compiled the linuxbios for mainboard nano (sc1200). I want my 
bios program in my Flash ROM (4MB). My kernel image will be in hard disk.

These are my generated files.

linuxbios_payload.nrv2b
nrv2b
linuxbios.rom
linuxbios.strip
payload.block
linux.bin.gz
linuxbios
linuxbios.a
romimage
linuxbios_c
linuxbios_payload
linuxbios_payload.bin

             Out of these files which files are to be placed in my Flash ROM 
and hard disk in my target? I assume linuxbios.rom is placed in Flash Rom, 
linux.bin.gz placed in hard disk. Is it correct? But I have no clear cut 
idea with what other files satnds for? Plzz even if I question looks too 
preliminary help me.

_________________________________________________________________
Are you Unmarried? http://www.bharatmatrimony.com/cgi-bin/bmclicks1.cgi?4d 
Register in India's No 1 Matrimony



From xpegenaute at telepolis.es  Thu Jul 17 07:09:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Thu Jul 17 07:09:00 2003
Subject: Linuxbios
In-Reply-To: <200307161921.h6GJL7Q31415@mailgate5.cinetic.de>
References: <200307161921.h6GJL7Q31415@mailgate5.cinetic.de>
Message-ID: <1058444062.546.7.camel@p-133>

Hi,

On Wed, 2003-07-16 at 21:21, Marco Hetzel wrote:
>   Hi!
> I'm sorry, but I don't know what to do. I asked in Forums and in this mailing-list, but noone simply  answers my questions or gives me a link to a page that answers them. So I try to write you :)!
> I've got a Asus A7N8X - Mainboard with NForce2 Chipset. Is it anyhow possible to run LinuxBios on it? You don't have to answer long. But pleas send me any links, that you have to this issue.

First, you have to look what kind of northbridge/southbridge you have
(lspci), then look for the model of chipset inside the directories
(src/northbridge and src/northbridge) if there is the chipset
implemented probably you will can run LinuxBios, else you have to port
it.

You can see info in:
http://www.linuxbios.org/developer/portguides/sbc710/index.html

Xavi.



From stepan at suse.de  Thu Jul 17 09:51:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 17 09:51:00 2003
Subject: ADLO, Framebuffer et al.
Message-ID: <20030717140234.GB9132@suse.de>

Hi,

I noticed that for video initialization I need to keep a copy
of the video rom in the system rom for execution. This definitely
makes sense for onboard graphics, but for other devices it would
be nice to just use the option roms held on expansion cards.
(Like Video cards, SCSI controllers, network cards, etc)

Is this just a matter of mapping the roms into address space, or is
there some higher magic preventing this to happen?

Stefan.





From rminnich at lanl.gov  Thu Jul 17 09:58:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 17 09:58:00 2003
Subject: ADLO, Framebuffer et al.
In-Reply-To: <20030717140234.GB9132@suse.de>
Message-ID: <Pine.LNX.4.44.0307170805110.5815-100000@maxroach.lanl.gov>

On Thu, 17 Jul 2003, Stefan Reinauer wrote:

> I noticed that for video initialization I need to keep a copy
> of the video rom in the system rom for execution. This definitely
> makes sense for onboard graphics, but for other devices it would
> be nice to just use the option roms held on expansion cards.
> (Like Video cards, SCSI controllers, network cards, etc)

that works. In other words, for linuxbios vga support, the vga startup 
code will find an option room for a VGA device and use it. That code could 
be extended for arbitrary expansion roms. 

I'm not sure you want to always do that. Some of these expansion roms for 
disk cards want to interact with you on bootup, which is crazy for a 
cluster node (crazy in general, as far as I'm concerned).

I think the ADLO code works the way it does because it was set up on an 
SIS 630 which had built-in graphics.

> Is this just a matter of mapping the roms into address space, or is
> there some higher magic preventing this to happen?

The only real issue is expansion roms that break the rules. Some VGA 
roms (e.g. older Nvidia) con't quite follow the rules, and that is hard to 
fix.

But all the bits are there in linuxbios to support arbitrary expansion 
roms. Let me know if you hit trouble.

ron



From rminnich at lanl.gov  Thu Jul 17 09:58:05 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 17 09:58:05 2003
Subject: ADLO, Framebuffer et al.
In-Reply-To: <20030717140234.GB9132@suse.de>
Message-ID: <Pine.LNX.4.44.0307170810000.5815-100000@maxroach.lanl.gov>

Forgot to mention, david will probably be starting the P4/Nvidia work next 
week.

ron



From stepan at suse.de  Thu Jul 17 10:08:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 17 10:08:00 2003
Subject: ADLO, Framebuffer et al.
In-Reply-To: <Pine.LNX.4.44.0307170805110.5815-100000@maxroach.lanl.gov>
References: <20030717140234.GB9132@suse.de> <Pine.LNX.4.44.0307170805110.5815-100000@maxroach.lanl.gov>
Message-ID: <20030717142003.GB9219@suse.de>

* ron minnich <rminnich at lanl.gov> [030717 16:09]:
> On Thu, 17 Jul 2003, Stefan Reinauer wrote:
> 
> > I noticed that for video initialization I need to keep a copy
> > of the video rom in the system rom for execution. This definitely
> > makes sense for onboard graphics, but for other devices it would
> > be nice to just use the option roms held on expansion cards.
> > (Like Video cards, SCSI controllers, network cards, etc)
> 
> that works. In other words, for linuxbios vga support, the vga startup 
> code will find an option room for a VGA device and use it. That code could 
> be extended for arbitrary expansion roms. 
> 
> I'm not sure you want to always do that. Some of these expansion roms for 
> disk cards want to interact with you on bootup, which is crazy for a 
> cluster node (crazy in general, as far as I'm concerned).
 
It is, but it would allow to boot off any scsi controller you put into
such a box. Since quite some systems around have scsi only or in
addition to IDE, this would be very nice to have.

> I think the ADLO code works the way it does because it was set up on an 
> SIS 630 which had built-in graphics.

So with the LinuxBIOS builtin code this is different?

> The only real issue is expansion roms that break the rules. Some VGA 
> roms (e.g. older Nvidia) con't quite follow the rules, and that is hard to 
> fix.
 
Have an example? I assume you need a workaround for these specific cards
then? I know that pretty well from the Alpha days :-(

> But all the bits are there in linuxbios to support arbitrary expansion 
> roms. Let me know if you hit trouble.

I was playing around with ADLO on the K8, and I could get it to load
grub, but grub hung right after loading stage2 every time. Video did not
work at all. I'll give the builtin stuff a try.

Stefan




From rminnich at lanl.gov  Thu Jul 17 10:16:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 17 10:16:01 2003
Subject: ADLO, Framebuffer et al.
In-Reply-To: <20030717142003.GB9219@suse.de>
Message-ID: <Pine.LNX.4.44.0307170823490.6008-100000@maxroach.lanl.gov>

On Thu, 17 Jul 2003, Stefan Reinauer wrote:

> So with the LinuxBIOS builtin code this is different?

only in that you have to copy the code into the linuxbios image, since
there is no expansion flash part for it to live in. Most of the rest of
should be pretty much the same.

> Have an example? I assume you need a workaround for these specific cards
> then? I know that pretty well from the Alpha days :-(

yes, one nvidia card we had just assumed that it was the only thing in the
universe that mattered -- it did not call PCI BIOS or even walk the bus
itself, or even take the busdevfn parameter you pass to the VGA rom when
you call it. This broke a bit when there were two of them -- IIRC the bios
from one card initialized -- but it initialized the other card! Other
cards we've seen do similar strange things, such as assume they are mapped
at 0xc0000, etc.

I am pretty sure the builtin stuff is solid on EPIA, and we're going to to 
what is needed to make it more solid, so keep in touch.

ron



From adam at cfar.umd.edu  Thu Jul 17 12:52:01 2003
From: adam at cfar.umd.edu (Adam Sulmicki)
Date: Thu Jul 17 12:52:01 2003
Subject: ADLO, Framebuffer et al.
In-Reply-To: <20030717142003.GB9219@suse.de>
Message-ID: <20030717131609.W58693-100000@www.missl.cs.umd.edu>

On Thu, 17 Jul 2003, Stefan Reinauer wrote:

> > I'm not sure you want to always do that. Some of these expansion roms for
> > disk cards want to interact with you on bootup, which is crazy for a
> > cluster node (crazy in general, as far as I'm concerned).
>
> It is, but it would allow to boot off any scsi controller you put into
> such a box. Since quite some systems around have scsi only or in
> addition to IDE, this would be very nice to have.

me thinks you might be able to get away with using linux kernel+kexec
instead of the scsi bios. I guess depends on quality of drivers in kernel.



-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers




From linuxbios at xdr.com  Thu Jul 17 17:47:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Jul 17 17:47:01 2003
Subject: Test
Message-ID: <200307172159.h6HLxNe5003302@xdr.com>

Test post, moderator asleep and not ok'ing my post about epia-m stuff,
in limbo since I'm not a list member...Sorry if this comes across...

-Dave


From rminnich at lanl.gov  Thu Jul 17 17:51:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 17 17:51:01 2003
Subject: Test [PMX:#]
In-Reply-To: <200307172159.h6HLxNe5003302@xdr.com>
Message-ID: <Pine.LNX.4.44.0307171602460.13563-100000@maxroach.lanl.gov>

On Thu, 17 Jul 2003, Dave Ashley wrote:

> Test post, moderator asleep and not ok'ing my post about epia-m stuff,
> in limbo since I'm not a list member...Sorry if this comes across...

moderator not asleep, moderator busy.

ron



From linuxbios at xdr.com  Thu Jul 17 18:28:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Jul 17 18:28:00 2003
Subject: DDR problem
Message-ID: <200307172240.h6HMe1Y2003390@xdr.com>

I think this problem is configuration of Rx58 bits 7-5, you have 10/11
bit column address but it is behaving like 9 bit column address.

 From looking at the code for ddr init it looks like cpu address
shifted right by 3 bits is the address going into the chip. So
accessing 0x150 is really like accessing 0x02a on the ddr chips.
Accessing 0x1000 is chip address 0x200 which overflows 9 bits.

I can get this same behaviour with to DDR rams. However when I try to
configure ddram control matching award bios settings, it works better
but fails later during vga init I think. Passes ramtest also.

-Dave


>SDRAM verify:
>00000000:00001000
>00000004:00001004
>00000008:00001008
>0000000c:0000100c
>00000010:00001010
>00000014:00001014
>00000018:00001018
>0000001c:0000101c
>00000020:00001020
>00000024:00001024
>00000028:00001028
>0000002c:0000102c
>00000030:00001030
>00000034:00001034
>00000038:00001038
>0000003c:0000103c
>Too many errors.


From mwilkinson at ndirect.co.uk  Thu Jul 17 20:18:00 2003
From: mwilkinson at ndirect.co.uk (Mark Wilkinson)
Date: Thu Jul 17 20:18:00 2003
Subject: EPIA Howto Update
Message-ID: <200307180129.48380.mwilkinson@ndirect.co.uk>

Hello All,
	Just a quick note to say that I've updated my EPIA howto to include a little  
section for the brave on enabling the onboard VGA.

This is based on Sone Takeshi's work.

Thanks to Andrew Ip for committing the update to CVS.

Regards
Mark.


From andre.renaud at hp.com  Thu Jul 17 20:45:00 2003
From: andre.renaud at hp.com (Renaud, Andre)
Date: Thu Jul 17 20:45:00 2003
Subject: EPIA Howto Update
Message-ID: <2E94204C7720924D8646DFE898B0DBAF03535172@nzmexc01.asiapacific.cpqcorp.net>

How does the VGA Bios code impact using graphics once the system has booted linux? What I'm asking is, if you don't do the extra VGA bios steps, can you still attempt to use X or framebuffer code from linux, or is the VGA bios required to set things up appropriately?

Sorry if this is blatantly obvious to everyone, I'm really only just getting started on this stuff.

Thanks,
Andre 

-----Original Message-----
From: Mark Wilkinson [mailto:mwilkinson at ndirect.co.uk]
Sent: Friday, 18 July 2003 12:30 PM
To: linuxbios at clustermatic.org
Subject: EPIA Howto Update


Hello All,
	Just a quick note to say that I've updated my EPIA howto to include a little  
section for the brave on enabling the onboard VGA.

This is based on Sone Takeshi's work.

Thanks to Andrew Ip for committing the update to CVS.

Regards
Mark.
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From rminnich at lanl.gov  Thu Jul 17 20:49:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 17 20:49:01 2003
Subject: EPIA Howto Update
In-Reply-To: <2E94204C7720924D8646DFE898B0DBAF03535172@nzmexc01.asiapacific.cpqcorp.net>
Message-ID: <Pine.LNX.4.44.0307171900360.16810-100000@maxroach.lanl.gov>

On Fri, 18 Jul 2003, Renaud, Andre wrote:

> How does the VGA Bios code impact using graphics once the system has
> booted linux? What I'm asking is, if you don't do the extra VGA bios
> steps, can you still attempt to use X or framebuffer code from linux, or
> is the VGA bios required to set things up appropriately?

that is really chip-dependent. Some work, some don't. 

ron



From andre.renaud at hp.com  Thu Jul 17 20:55:01 2003
From: andre.renaud at hp.com (Renaud, Andre)
Date: Thu Jul 17 20:55:01 2003
Subject: EPIA Howto Update
Message-ID: <2E94204C7720924D8646DFE898B0DBAF03535173@nzmexc01.asiapacific.cpqcorp.net>

On Fri, 18 Jul 2003, ron minnich wrote:

>> How does the VGA Bios code impact using graphics once the system has
>> booted linux? What I'm asking is, if you don't do the extra VGA bios
>> steps, can you still attempt to use X or framebuffer code from linux, or
>> is the VGA bios required to set things up appropriately?
>
>that is really chip-dependent. Some work, some don't. 

Any ideas about the EPIA chip(s)?

Thanks,
Andre


From Qwani at hanafos.com  Thu Jul 17 22:28:01 2003
From: Qwani at hanafos.com (Kyuwan Jung)
Date: Thu Jul 17 22:28:01 2003
Subject: files to be placed in target?
References: <BAY2-F4723PDH8qHNwK00006140@hotmail.com>
Message-ID: <001501c34cd3$8d026260$0400a8c0@wsjkw>

If you have a few partitions and let hda1 be for kernel image
- BOOT_IDE = 1 in nano.config
- commandline root=/dev/hda2 blur blur in nano.config

try this
dd if=romimage of=/dev/hda1

----- Original Message ----- 
From: "Devi Priya" <ijpriya at hotmail.com>
To: <linuxbios at clustermatic.org>
Sent: Thursday, July 17, 2003 12:52 PM
Subject: files to be placed in target?


> Hello,
> 
> 
>            I compiled the linuxbios for mainboard nano (sc1200). I want my 
> bios program in my Flash ROM (4MB). My kernel image will be in hard disk.
> 
> These are my generated files.
> 
> linuxbios_payload.nrv2b
> nrv2b
> linuxbios.rom
> linuxbios.strip
> payload.block
> linux.bin.gz
> linuxbios
> linuxbios.a
> romimage
> linuxbios_c
> linuxbios_payload
> linuxbios_payload.bin
> 
>              Out of these files which files are to be placed in my Flash ROM 
> and hard disk in my target? I assume linuxbios.rom is placed in Flash Rom, 
> linux.bin.gz placed in hard disk. Is it correct? But I have no clear cut 
> idea with what other files satnds for? Plzz even if I question looks too 
> preliminary help me.
> 
> _________________________________________________________________
> Are you Unmarried? http://www.bharatmatrimony.com/cgi-bin/bmclicks1.cgi?4d 
> Register in India's No 1 Matrimony
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


From Qwani at hanafos.com  Thu Jul 17 22:31:01 2003
From: Qwani at hanafos.com (Kyuwan Jung)
Date: Thu Jul 17 22:31:01 2003
Subject: files to be placed in target?
References: <BAY2-F4723PDH8qHNwK00006140@hotmail.com>
Message-ID: <002f01c34cd6$04d9c9c0$0400a8c0@wsjkw>

Sorry for omitting answer for your question.
how stupid was I~

You should write 'linuxbios.rom' to your flash rom.
Check first ROM_IMAGE_SIZE and ROM_SIZE in your nano.config
fit to your flash rom.


----- Original Message ----- 
From: "Devi Priya" <ijpriya at hotmail.com>
To: <linuxbios at clustermatic.org>
Sent: Thursday, July 17, 2003 12:52 PM
Subject: files to be placed in target?


> Hello,
> 
> 
>            I compiled the linuxbios for mainboard nano (sc1200). I want my 
> bios program in my Flash ROM (4MB). My kernel image will be in hard disk.
> 
> These are my generated files.
> 
> linuxbios_payload.nrv2b
> nrv2b
> linuxbios.rom
> linuxbios.strip
> payload.block
> linux.bin.gz
> linuxbios
> linuxbios.a
> romimage
> linuxbios_c
> linuxbios_payload
> linuxbios_payload.bin
> 
>              Out of these files which files are to be placed in my Flash ROM 
> and hard disk in my target? I assume linuxbios.rom is placed in Flash Rom, 
> linux.bin.gz placed in hard disk. Is it correct? But I have no clear cut 
> idea with what other files satnds for? Plzz even if I question looks too 
> preliminary help me.
> 
> _________________________________________________________________
> Are you Unmarried? http://www.bharatmatrimony.com/cgi-bin/bmclicks1.cgi?4d 
> Register in India's No 1 Matrimony
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


From thomas.wehrspann at tu-clausthal.de  Fri Jul 18 00:10:01 2003
From: thomas.wehrspann at tu-clausthal.de (Thomas Wehrspann)
Date: Fri Jul 18 00:10:01 2003
Subject: DoC 2000
Message-ID: <200307111332.36151.thomas.wehrspann@tu-clausthal.de>

Hello,

I use successfully linuxbios with kernel and filesystem on a DoC Millenium
- a describe in the Documantation - but the DoC 2000 is availeable in much 
greater size.
Is it possible to replace the BIOS with a DoC 2000 istead of a Millenium?
Or is there non special booting area?

Thanks
Thomas


From dash at xdr.com  Fri Jul 18 00:11:24 2003
From: dash at xdr.com (David Ashley)
Date: Fri Jul 18 00:11:24 2003
Subject: ADLO + EPIA-M + No hard disk, just etherboot/tftp?
Message-ID: <200307141752.h6EHqJ4Y026762@xdr.com>

I'm working with the VIA EPIA-M motherboard.

I'm trying to bring up ADLO with linuxbios, and I've gotten this far using
tftp:
Linuxbios -> etherboot-5.0.10 -> ADLO

Previously I have had
Linuxbios -> etherboot-5.0.10 -> linux, all ok except no VGA

So I'm working on getting VGA up since although evidently people have done it
they're not sharing.

This is a diskless workstation so the idea is its root filesystem exists
only over the network, and linux will always be booted with etherboot/bootp.
However ADLO locks you into a hard drive boot.

SO:

Is it possible to merge the ADLO payload and my linux payload (made with
mkelfImage-2.5) so that everything will work? Maybe I'd modify ADLO to
just initialize itself then chain to the linux payload directly rather than
try booting a hard drive.

Any help appreciated. When/if successful I *will* share the procedure of
getting VGA working with epia-m. Please cc me on replies since I'm not
subscribed.

Thanks--
Dave


From dash at xdr.com  Fri Jul 18 00:11:38 2003
From: dash at xdr.com (David Ashley)
Date: Fri Jul 18 00:11:38 2003
Subject: linuxbios + epia-m + vga success, here are details
Message-ID: <200307142223.h6EMN0QY027494@xdr.com>

I included my epia-m contents when I pulled from the linuxbios cvs
snapshot, then made some changes.

My setup is we have a custom pci card in the slot of the epia-m that
has an rtl8139 as well as some other parts. This causes some special
problems. We want to boot of the pci card, not the internal via-rhine
chip. The problem was that the other circuitry on the pci card was
generating an interrupt, so when the board was soft reset there would be
a lockup as soon as the rtl8139 interrupt became active--there was no driver
present to ack the interrupt and make it go away.

SO to fix that problem I made the epia-m reboot (see earlysetup.inc) once
on startup. It uses CMOS ram byte 0x0e as a marker to tell whether we've
already rebooted. In order to access CMOS this early in linuxbios the
firewire device has to be moved out of the way, it defaults to answering
PCI IO address 0000-, so the CMOS access ports 0x70-0x71 can't be seen.
I don't know if my method here is strictly kosher but it seems to work
so far.

Incidentally there is a bug in the rtl8139.c driver of etherboot (and linux
for that matter). The use of the IntrStatus register (word 0x3e) is incorrect.
It is read only, any read clears all interrupts. The drivers behave as if
they have to write 1 bits back to this register to explicitly clear interrupt
request bits. This not the case. Careful reading of the rtl8139 data sheet
explains how the register works.

VGA system: There is a bit that has to be set in the device 0 function 0
pci registers to enable the VGA, as well as set its memory size. My setup is
to hardcode it to 32 megs of ram. ADLO + Bochs are not used at all since we
only want to boot into linux, no other legacy OS's. In another post on this
newsgroup were instructions on how to get the pcbios features working to
add a dummy bios as well as vga bios. In order to get the vga bios to write
to 0xc0000 the shadow ram has to be enabled there.

I extracted the VGA bios as described in the ADLO docs, doing the dd on
/proc/kcore.

I'm going
Linuxbios -> etherboot 5.0.10 -> tftp linux
The linux bootfile is produced with mkelfImage version 2.5, I'm using this
command:
	/ram/mkelfImage-2.5/objdir/sbin/mkelfImage  \
	  --command-line="root=/dev/ram console=ttyS0,115200 console=tty0" \
	  --kernel=/build/linux-via/arch/i386/boot/bzImage \
	  --ramdisk=/code/bootfiles/bootfiles/rd.gz \
	  --type=bzImage-i386 \
	  --output=bootfile_via_insecure

Now what do I have?

I have some simple bios boot message appearing on startup, VIA CLE266 appears
as well as some other text in the upper left. The system boots and launched
XFree86 without problems. No frame buffer device, I'm using VIA's own XFree86
drivers. Everything I've tested works, however a couple of applications using
SDL wig out the X server and cause it to seg fault, this should be easy to
track down. Also for some reasom the lm_sensors readings
cat /proc/sys/dev/sensors/vt1211-isa-ec00/temp*
are no longer valid, they seem frozen at some arbitrary values.

Linuxbios logs lots of biosint messages, some of which are unsupported:
biosint: # 0x15, eax 0x5f19 ebx 0x810 ecx 0x20 edx 0x3d4                        
biosint: ebp 0x11c30 esp 0xfca edi 0x44 esi 0xfffeb167                          
biosint: ip 0x4ef9 cs 0x44 flags 0x86                                           

biosint: Unsupport int #0x15                                                    
biosint: # 0x15, eax 0x5f0f ebx 0x10 ecx 0x20 edx 0x3d5                         
biosint: ebp 0x11c30 esp 0xff0 edi 0x44 esi 0xfffe0000                          
biosint: ip 0x5c98 cs 0x0 flags 0x2                                             

biosint: Unsupport int #0x15                                                    
biosint: # 0x15, eax 0x5f02 ebx 0x10 ecx 0x20 edx 0x3d4                         
biosint: ebp 0x11c30 esp 0xfde edi 0x44 esi 0xfffe0000                          
biosint: ip 0x4008 cs 0x0 flags 0x46                                            

biosint: Unsupport int #0x15                                                    
biosint: # 0x15, eax 0x5f18 ebx 0x10 ecx 0x20 edx 0x3d4                         
biosint: ebp 0x10000 esp 0xff0 edi 0x44 esi 0xfffe0000                          
biosint: ip 0x5d7f cs 0x0 flags 0x86                                            

In another email someone said these could be implemented, the VIA
BIOS PORTING GUIDE describes what they need to do. That might relate to
the crashing of XFree86.

Performance seems to be perhaps 10-15% slower than under the stock bios,
but that's not certain.

I've attached a uuencoded copy of my epia-m directory contents from
the freebios tree. I think that's all I've touched.

Hope this saves other people some time.
-Dave

begin 644 epia-m.tgz
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`
end


From dash at xdr.com  Fri Jul 18 00:11:50 2003
From: dash at xdr.com (David Ashley)
Date: Fri Jul 18 00:11:50 2003
Subject: WTF
Message-ID: <200307172151.h6HLptuT003138@xdr.com>

I posted to the mailing list some important messages but they haven't
appeared. What's the holdup? Is this moderation or censorship?

-Dave


From rminnich at lanl.gov  Fri Jul 18 00:16:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 00:16:01 2003
Subject: DoC 2000
In-Reply-To: <200307111332.36151.thomas.wehrspann@tu-clausthal.de>
Message-ID: <Pine.LNX.4.44.0307172227280.18206-100000@maxroach.lanl.gov>

On Fri, 11 Jul 2003, Thomas Wehrspann wrote:

> Is it possible to replace the BIOS with a DoC 2000 istead of a Millenium?

unfortunately, not. The Millenium has a special "IPL area" which the 2000 
does not. We use this area for booting.

ron



From rminnich at lanl.gov  Fri Jul 18 00:18:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 00:18:00 2003
Subject: linuxbios + epia-m + vga success, here are details [PMX:#]
In-Reply-To: <200307142223.h6EMN0QY027494@xdr.com>
Message-ID: <Pine.LNX.4.44.0307172229360.18206-100000@maxroach.lanl.gov>

Great stuff. I am hoping Andrew Ip can take a look and use some of it. 

What is INT 15 anyway?

ron



From rminnich at lanl.gov  Fri Jul 18 00:20:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 00:20:00 2003
Subject: WTF
In-Reply-To: <200307172151.h6HLptuT003138@xdr.com>
Message-ID: <Pine.LNX.4.44.0307172229570.18206-100000@maxroach.lanl.gov>

On Thu, 17 Jul 2003, David Ashley wrote:

> I posted to the mailing list some important messages but they haven't
> appeared. What's the holdup? Is this moderation or censorship?

It's just me being slow. The list gets tons of spam so I just hate to go 
to the site to sift through it all. Plus all those nigerians sending the 
spam never write me back when I tell them my bank account numbers. 

However, your note was the occasional diamond we get for all that spam. 

You have done really excellent work, and thanks. I'd like to resolve your
SEGV and 15% problems. I need to get an EPIA-M however.

ron



From ts1 at cma.co.jp  Fri Jul 18 00:44:00 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Fri Jul 18 00:44:00 2003
Subject: EPIA Howto Update
In-Reply-To: <200307180129.48380.mwilkinson@ndirect.co.uk>
References: <200307180129.48380.mwilkinson@ndirect.co.uk>
Message-ID: <20030718045627.GA869@cma.co.jp>

On Fri, Jul 18, 2003 at 01:29:48AM +0100, Mark Wilkinson wrote:
> 	Just a quick note to say that I've updated my EPIA howto to include a little  
> section for the brave on enabling the onboard VGA.
> 
> This is based on Sone Takeshi's work.
> 
> Thanks to Andrew Ip for committing the update to CVS.


Hi Mark,
Thank you for your work.

Perhaps everyone already forgets about it, but I was asked by Ron
for a HOWTO on EPIA+VGA.
I started it, but it isn't finished. (I was fiddling with BOOT_IDE etc
to include in my documentation...)
Now that your HOWTO covers VGA, everything is OK.

Some points...

- Line 37-40:
    NOTE: At present, the epia can be booted with a serial console. Power
	  management to turn off the power is not available, neither is the
	  video bios. Memeory is currenly hard coded to report 64M - you must
	  have at least this much memory.

You can use video console once VGA is enabled (option VIDEO_CONSOLE=1).
It isn't very useful however, since VGA initialization is almost at the
end of LinuxBIOS execution. 
Memory configuration is also fixed already.

- Line 364-367:
                0 - Disable Framebuffer
                1 - 1 Mbyte
                2 - 2 Mbytes
                8 - 8 Mbytes

This is incorrect. Valid values are 2, 4, and 8 (MB).
To disable framebuffer, remove the option HAVE_FRAMEBUFFER.

Also, now I use folowing lines in the config for the VGA BIOS image to be
patched in the romimage:
    option ZKERNEL_START=0xfffc0000
    option VGABIOS_START=0xfffe0000
    addaction romimage dd if=/path/to/vgabios.bin of=romimage bs=65536 \
	seek=2 conv=sync conv=notrunc
This way you don't have to handcraft the vga+eb payload.

--
Takeshi


From agnew at cs.umd.edu  Fri Jul 18 01:16:01 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Fri Jul 18 01:16:01 2003
Subject: linuxbios + epia-m + vga success, here are details [PMX:#]
In-Reply-To: <Pine.LNX.4.44.0307172229360.18206-100000@maxroach.lanl.gov>
Message-ID: <20030718013804.H57050-100000@www.missl.cs.umd.edu>

>
> What is INT 15 anyway?

A variety of system information (ram size, keyboard interface, etc).

See Ralf Brown's interrupt list:
http://oopweb.com/Assembly/Documents/InterList/Volume2.html

- Adam A.



From mwilkinson at ndirect.co.uk  Fri Jul 18 02:08:00 2003
From: mwilkinson at ndirect.co.uk (Mark Wilkinson)
Date: Fri Jul 18 02:08:00 2003
Subject: EPIA Howto Update
In-Reply-To: <20030718045627.GA869@cma.co.jp>
References: <200307180129.48380.mwilkinson@ndirect.co.uk> <20030718045627.GA869@cma.co.jp>
Message-ID: <200307180720.22059.mwilkinson@ndirect.co.uk>

Hi Sone,

	Thanks for the comments, looks like an update to the update will be on it's 
way shortly !

On Friday 18 Jul 2003 05:56, SONE Takeshi wrote:
> On Fri, Jul 18, 2003 at 01:29:48AM +0100, Mark Wilkinson wrote:
> > 	Just a quick note to say that I've updated my EPIA howto to include a
> > little section for the brave on enabling the onboard VGA.
> >
> > This is based on Sone Takeshi's work.
> >
> > Thanks to Andrew Ip for committing the update to CVS.
>
> Hi Mark,
> Thank you for your work.
>
> Perhaps everyone already forgets about it, but I was asked by Ron
> for a HOWTO on EPIA+VGA.
> I started it, but it isn't finished. (I was fiddling with BOOT_IDE etc
> to include in my documentation...)
> Now that your HOWTO covers VGA, everything is OK.
>
> Some points...
>
> - Line 37-40:
>     NOTE: At present, the epia can be booted with a serial console. Power
> 	  management to turn off the power is not available, neither is the
> 	  video bios. Memeory is currenly hard coded to report 64M - you must
> 	  have at least this much memory.
>
> You can use video console once VGA is enabled (option VIDEO_CONSOLE=1).
> It isn't very useful however, since VGA initialization is almost at the
> end of LinuxBIOS execution.
> Memory configuration is also fixed already.

Oops, forgot all about the memory configuration being fixed, and I haven't had 
a chance to play with the VIDEO_CONSOLE=1 option yet (old story about not 
being enough hours in the day... :-)

>
> - Line 364-367:
>                 0 - Disable Framebuffer
>                 1 - 1 Mbyte
>                 2 - 2 Mbytes
>                 8 - 8 Mbytes
>
> This is incorrect. Valid values are 2, 4, and 8 (MB).
> To disable framebuffer, remove the option HAVE_FRAMEBUFFER.

Will correct that, although what I can remember from the northbridge docs is 
that a setting of 0 also disables the framebuffer - perhaps this option is 
really a 'have framebuffer, but don't share with it memory option'

>
> Also, now I use folowing lines in the config for the VGA BIOS image to be
> patched in the romimage:
>     option ZKERNEL_START=0xfffc0000
>     option VGABIOS_START=0xfffe0000
>     addaction romimage dd if=/path/to/vgabios.bin of=romimage bs=65536 \
> 	seek=2 conv=sync conv=notrunc
> This way you don't have to handcraft the vga+eb payload.

so this copies the vgabios into the rom image after the payload (not the 
otherway around) doesn't copying 65536 bytes to 0xfffe000 overwrite the 
Linuxbios part of the rom image ? or is that done afterwards, in which case 
the LinuxBIOS would overwrite part of the vgabios image... althought, I think 
the VGA bios is only 48K in size isn't it !

I'll have to try this, just to get my head around what's happening !

Regards
Mark.


From ts1 at cma.co.jp  Fri Jul 18 02:25:01 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Fri Jul 18 02:25:01 2003
Subject: EPIA Howto Update
In-Reply-To: <200307180720.22059.mwilkinson@ndirect.co.uk>
References: <200307180129.48380.mwilkinson@ndirect.co.uk> <20030718045627.GA869@cma.co.jp> <200307180720.22059.mwilkinson@ndirect.co.uk>
Message-ID: <20030718063715.GA6632@cma.co.jp>

On Fri, Jul 18, 2003 at 07:20:22AM +0100, Mark Wilkinson wrote:
> Will correct that, although what I can remember from the northbridge docs is 
> that a setting of 0 also disables the framebuffer - perhaps this option is 
> really a 'have framebuffer, but don't share with it memory option'

vgainit.inc has #if's to examine the value to choose the value for 
the northbridge register, it cause #error if it's 0.

> >     option ZKERNEL_START=0xfffc0000
> >     option VGABIOS_START=0xfffe0000
> >     addaction romimage dd if=/path/to/vgabios.bin of=romimage bs=65536 \
> > 	seek=2 conv=sync conv=notrunc

> so this copies the vgabios into the rom image after the payload (not the 
> otherway around) doesn't copying 65536 bytes to 0xfffe000 overwrite the 
> Linuxbios part of the rom image ? or is that done afterwards, in which case 
> the LinuxBIOS would overwrite part of the vgabios image... althought, I think 
> the VGA bios is only 48K in size isn't it !

It copies vgabios.bin at 128-192KB of romimage.
LinuxBIOS lives at 192-256KB.
128KB space at the beginning is left for payload.

-- 
Takeshi


From ijpraveen1 at yahoo.com  Fri Jul 18 09:07:00 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Fri Jul 18 09:07:00 2003
Subject: Loading OS from Flash ROM.
Message-ID: <20030718131918.34777.qmail@web41712.mail.yahoo.com>

                        I am new to linux bios. My project is based on geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB). I saw the HOW-TO for Sis based on DiskOnChip. What I have to modify and what other information i have to add if I want to boot from Flash ROM into SDRAM. 
  
Please help.
Thanks.


---------------------------------
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
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From rminnich at lanl.gov  Fri Jul 18 09:53:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 09:53:00 2003
Subject: linuxbios + epia-m + vga success, here are details [PMX:#]
In-Reply-To: <20030718013804.H57050-100000@www.missl.cs.umd.edu>
Message-ID: <Pine.LNX.4.44.0307180804120.22772-100000@maxroach.lanl.gov>

On Fri, 18 Jul 2003, Adam Agnew wrote:

> >
> > What is INT 15 anyway?
> 
> A variety of system information (ram size, keyboard interface, etc).
> 
> See Ralf Brown's interrupt list:
> http://oopweb.com/Assembly/Documents/InterList/Volume2.html
> 
> - Adam A.
> 


OK, looks like I"ll be implementing this unless Andrew Ip already 
committed something (but I have not seen it).

ron



From rminnich at lanl.gov  Fri Jul 18 09:56:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 09:56:01 2003
Subject: EPIA Howto Update
In-Reply-To: <20030718063715.GA6632@cma.co.jp>
Message-ID: <Pine.LNX.4.44.0307180805450.22772-100000@maxroach.lanl.gov>

suggestion: next week the config tool should be basically done for
freebios2. You folks cold look at converting DRAM code to C and porting
the EPIA code to freebios2. It is about 100 times easier to code this
stuff up in C.

ron



From rminnich at lanl.gov  Fri Jul 18 10:03:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 10:03:00 2003
Subject: Loading OS from Flash ROM.
In-Reply-To: <20030718131918.34777.qmail@web41712.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0307180813270.22772-100000@maxroach.lanl.gov>

On Fri, 18 Jul 2003, John Praveen wrote:

>                         I am new to linux bios. My project is based on
> geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB). 

I have sad news. You can't get a 4 MB chip on that board, I bet. It is 
probably 4 Mbits, 512 KB. You'll have to put that overweight linux kernel 
on a diet to get it to fit in there. 

One option is 2.4.0 or so, that might fit.

Can DoC fit on your geode anywhere?

ron



From bgr at gw.linespeed.net  Fri Jul 18 10:09:00 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Fri Jul 18 10:09:00 2003
Subject: ADLO + EPIA-M + No hard disk, just etherboot/tftp?
In-Reply-To: <200307141752.h6EHqJ4Y026762@xdr.com>
References: <200307141752.h6EHqJ4Y026762@xdr.com>
Message-ID: <Pine.LNX.4.53.0307180913120.7455@gw.linespeed.net>

are you trying to use adlo specifically for VGA?  ifso then you could just
use linuxbios's vgabios support.


Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Mon, 14 Jul 2003, David Ashley wrote:

> I'm working with the VIA EPIA-M motherboard.
>
> I'm trying to bring up ADLO with linuxbios, and I've gotten this far using
> tftp:
> Linuxbios -> etherboot-5.0.10 -> ADLO
>
> Previously I have had
> Linuxbios -> etherboot-5.0.10 -> linux, all ok except no VGA
>
> So I'm working on getting VGA up since although evidently people have done it
> they're not sharing.
>
> This is a diskless workstation so the idea is its root filesystem exists
> only over the network, and linux will always be booted with etherboot/bootp.
> However ADLO locks you into a hard drive boot.
>
> SO:
>
> Is it possible to merge the ADLO payload and my linux payload (made with
> mkelfImage-2.5) so that everything will work? Maybe I'd modify ADLO to
> just initialize itself then chain to the linux payload directly rather than
> try booting a hard drive.
>
> Any help appreciated. When/if successful I *will* share the procedure of
> getting VGA working with epia-m. Please cc me on replies since I'm not
> subscribed.
>
> Thanks--
> Dave
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From aip at cwlinux.com  Fri Jul 18 10:31:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Fri Jul 18 10:31:01 2003
Subject: linuxbios + epia-m + vga success, here are details [PMX:#]
In-Reply-To: <Pine.LNX.4.44.0307180804120.22772-100000@maxroach.lanl.gov>; from ron minnich on Fri, Jul 18, 2003 at 08:04:46AM -0600
References: <20030718013804.H57050-100000@www.missl.cs.umd.edu> <Pine.LNX.4.44.0307180804120.22772-100000@maxroach.lanl.gov>
Message-ID: <20030718224311.A10303@mail.cwlinux.com>

Hi,

> OK, looks like I"ll be implementing this unless Andrew Ip already 
> committed something (but I have not seen it).
Not yet.  I still have to work on the DDR config for EPIA-M.  Help
are welcome.  :)

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From linuxbios at xdr.com  Fri Jul 18 10:45:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Jul 18 10:45:01 2003
Subject: linuxbios + epia-m + vga success, here are details
Message-ID: <200307181456.h6IEukH1005309@xdr.com>

Just an update on progress.

The X server crash was caused by our custom Xinput module
not intializing a feedback device handler, SDL makes use of this probably
related to joystick use. The call I needed to add is
InitPtrFeedbackClassDeviceStruct however this is unrelated to linuxbios and
was just a coincidence. I think I had gotten the problem before linuxbios
but it didn't cause a seg fault of the X server for some reason. Who knows?

The lm_sensors stuff wasn't working because the vt1211 superio device sensor
machinery wasn't initialized or turned on. The stock bios initializes it
but linuxbios doesn't. I added to epia-m's mainboard.c this table:
static unsigned char vt1211hwmonitorinits[]={
0x10,0x3, 0x11,0x10, 0x12,0xd, 0x13,0x7f,
0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a,
0x18,0x0, 0x19,0x0, 0x1a,0x0, 0x1b,0x0,
0x1d,0xff, 0x1e,0x0, 0x1f,0x73, 0x20,0x67,
0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2,
0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x0,
0x2a,0x0, 0x2b,0xff, 0x2c,0x0, 0x2d,0xff,
0x2e,0x0, 0x2f,0xff, 0x30,0x0, 0x31,0xff,
0x32,0x0, 0x33,0xff, 0x34,0x0, 0x39,0xff,
0x3a,0x0, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff,
0x3e,0x0, 0x3f,0xb0, 0x43,0xff, 0x44,0xff,
0x46,0xff, 0x47,0x50, 0x4a,0x3, 0x4b,0xc0,
0x4c,0x0, 0x4d,0x0, 0x4e,0xf, 0x5d,0x77,
0x5c,0x0, 0x5f,0x33, 0x40,0x1};

And inside mainboard_fixup() this function:
// initialize vt1211 hardware monitor registers, which are at 0xECXX
	for(i=0;i<sizeof(vt1211hwmonitorinits);i+=2)
		outb(vt1211hwmonitorinits[i+1],0xec00+vt1211hwmonitorinits[i]);

This seems to work.

I also am using CMOS registers 0x80+ to store a bootrom version string.
In our application we actually might prefer to remove the cmos battery.


There was mention of the performance being 15% slow, this is real and was
fixed by inplementing the bios callback for int 21 ax=0x5f18:

Inside src/arch/i386/lib/idt.c

	case MEMSIZE: 
		// who cares. 
		eax = 64 * 1024;
		ret = 0;
		break;
+#ifdef CONFIG_INT21HANDLER
+	case 0x15:
+		ret=handleint21( &edi, &esi, &ebp, &esp, 
+				&ebx, &edx, &ecx, &eax, &flags);
+		break;
+#endif
	default:
		printk_info(__FUNCTION__ ": Unsupport int #0x%x\n", 
					intnumber);
		break;
	}


Inside epia-m/mainboard.c again:
int handleint21( unsigned long *edi, unsigned long *esi, unsigned long *ebp,
			  unsigned long *esp, unsigned long *ebx, unsigned long *edx,
			  unsigned long *ecx, unsigned long *eax, unsigned long *flags)
{
int res=-1;
	switch(*eax&0xffff)
	{
	case 0x5f19:
		break;
	case 0x5f18:
		*eax=0x5f;
		*ebx=0x15; // MCLK = 133, 32M frame buffer
		res=0;
		break;
	}
	return res;
}
--- And then inside the Config file:
option CONFIG_INT21HANDLER=1


NOW: Everything appears fine except for these:
1) Serial port baud settings are not working correctly, something
   strange is happening. Probably some io device stepping on another.
2) DDR ram is hardcoded for some certain type of DDR module, instead of
   reading the SPD eeprom chip to determine the module configuration.
   I had at least 2 types of DDR modules, one of which doesn't work with
   the current setup. It has 8 chips labeled GET (128M total). The one that
   works has 16 chips labeled ICT (128M total also).

-Dave

>From linuxbios-admin at clustermatic.org  Thu Jul 17 21:24:43 2003
>From: David Ashley <dash at xdr.com>
>To: Linuxbios at clustermatic.org
>Subject: linuxbios + epia-m + vga success, here are details
>Now what do I have?
>
>I have some simple bios boot message appearing on startup, VIA CLE266 appears
>as well as some other text in the upper left. The system boots and launched
>XFree86 without problems. No frame buffer device, I'm using VIA's own XFree86
>drivers. Everything I've tested works, however a couple of applications using
>SDL wig out the X server and cause it to seg fault, this should be easy to
>track down. Also for some reasom the lm_sensors readings
>cat /proc/sys/dev/sensors/vt1211-isa-ec00/temp*
>are no longer valid, they seem frozen at some arbitrary values.
>


From linuxbios at xdr.com  Fri Jul 18 10:53:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Jul 18 10:53:01 2003
Subject: EPIA Howto Update
Message-ID: <200307181504.h6IF4nF3005338@xdr.com>

How would C code work without the DRAM present? C requires a stack. I'd like
to understand this if it is actually possible :^).

I was thinking the CALLSP macro could be enhanced to some depth more than
1 using mmx registers as a stack. However maybe depth of 1 is plenty.

-Dave


>suggestion: next week the config tool should be basically done for
>freebios2. You folks cold look at converting DRAM code to C and porting
>the EPIA code to freebios2. It is about 100 times easier to code this
>stuff up in C.
>
>ron
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From rminnich at lanl.gov  Fri Jul 18 10:54:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 10:54:00 2003
Subject: linuxbios + epia-m + vga success, here are details [PMX:#]
In-Reply-To: <200307181456.h6IEukH1005309@xdr.com>
Message-ID: <Pine.LNX.4.44.0307180904000.23073-100000@maxroach.lanl.gov>

On Fri, 18 Jul 2003, Dave Ashley wrote:

> Inside src/arch/i386/lib/idt.c
> 
> 	case MEMSIZE: 
> 		// who cares. 
> 		eax = 64 * 1024;
> 		ret = 0;
> 		break;
> +#ifdef CONFIG_INT21HANDLER
> +	case 0x15:
> +		ret=handleint21( &edi, &esi, &ebp, &esp, 
> +				&ebx, &edx, &ecx, &eax, &flags);
> +		break;
> +#endif
> 	default:
> 		printk_info(__FUNCTION__ ": Unsupport int #0x%x\n", 
> 					intnumber);
> 		break;
> 	}

oh! how embarrasing!

This is good stuff, and you're implementing it just right. 

IF you want to send a c-diff for the int21 stuff I'll apply it. 

What I'll probably change is just have the INT21HANDLER call memsize() 
which works on all platforms.

sorry.
ron



From rminnich at lanl.gov  Fri Jul 18 10:54:18 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 10:54:18 2003
Subject: EPIA Howto Update [PMX:#]
In-Reply-To: <200307181504.h6IF4nF3005338@xdr.com>
Message-ID: <Pine.LNX.4.44.0307180906001.23073-100000@maxroach.lanl.gov>

On Fri, 18 Jul 2003, Dave Ashley wrote:

> How would C code work without the DRAM present? C requires a stack. I'd like
> to understand this if it is actually possible :^).

freebios2/util/romcc. Needs no memory.

read all about it. Quite cool.

ron



From linuxbios at xdr.com  Fri Jul 18 11:31:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Jul 18 11:31:01 2003
Subject: linuxbios + epia-m + vga success, here are details [PMX:#]
Message-ID: <200307181543.h6IFhXT4005557@xdr.com>

Setting up a c-diff would be tricky on my end. The CVS checkout doesn't
actually work as described in the linuxbios web page. I had to download the
daily snapshot, then extract that into my own cvs server, then check that
out to get the code. However I then started checking stuff back in since it
was already setup...so what two trees can I diff now? Anyway all the
relavent code was included in the email.

You wouldn't want to change the MEMSIZE stuff, it is a different interrupt.
You'd be mixing different things that should stay separate. I think how I've
implemented it is the way to go.

-Dave

>oh! how embarrasing!
>
>This is good stuff, and you're implementing it just right.
>
>IF you want to send a c-diff for the int21 stuff I'll apply it.
>
>What I'll probably change is just have the INT21HANDLER call memsize()
>which works on all platforms.


From linuxbios at xdr.com  Fri Jul 18 12:18:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Jul 18 12:18:00 2003
Subject: EPIA-M DDR SPD detection
Message-ID: <200307181630.h6IGUhcJ005649@xdr.com>

It appears we've got 3 people interested in having this functional,
Ron, Andrew and myself.
Myself = I need it working asap just to round out our epia-m solution
Andrew = Seems to be working on it right now, priority unknown
Ron    = Seems to want it eventually but if it's in freebios2 that would be ok

As I understand it Ron doesn't have an epia-m to experiment with anyway.
I can't do anything with freebios2 at this stage since everything is
working so well with the freebios mechanics as it is. I don't mind doing
bit banging in X86 code to get stuff done. Someone else can clean that up
at a later date and convert it to C/romcc for maintainability.

Now realistically I knew nothing concrete about DRAM configuration or the
details on the SPD system itself until some time 2 days ago and the time
since. With the lm_sensors project I've managed to read out the serial
eeprom contents and view it with a perl script and it looks like the right
stuff. But I wouldn't know how to interpret that data and configure the
dram controller and the ddr ram itself appropriately without more studying.

What I can contribute quickly could be figuring out how to read the
SPD data from the VT8235 I2C or SMB bus or whatever early in the boot
process. I was going to look into this right now anyway. Then maybe one of
you other guys can run with this info to get the SPD dram configuration
working.

-Dave



From rminnich at lanl.gov  Fri Jul 18 12:27:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 12:27:00 2003
Subject: EPIA-M DDR SPD detection [PMX:#]
In-Reply-To: <200307181630.h6IGUhcJ005649@xdr.com>
Message-ID: <Pine.LNX.4.44.0307181039180.23073-100000@maxroach.lanl.gov>

are you sure that the I2C is not being read now on EPIA-M? I have not 
looked but it seems it ought to be.

ron



From linuxbios at xdr.com  Fri Jul 18 12:37:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Jul 18 12:37:00 2003
Subject: EPIA-M DDR SPD detection [PMX:#]
Message-ID: <200307181649.h6IGniTT005747@xdr.com>

I'm not sure of anything, except that epia-m currently hardcodes the dram
settings which isn't optimum. My approach was going to be
A) Figure out how bloatware lm_sensors is reading the eeprom
B) Understand the underlying mechanics
C) Look for similiar functionality/implementation in linuxbios/northbridge
D) Implement mechanism in epia-m to just hex dump the eeprom contents
E) Pass the ball to someone else!

-Dave

>are you sure that the I2C is not being read now on EPIA-M? I have not 
>looked but it seems it ought to be.
>
>ron
>


From ts1 at tsn.or.jp  Fri Jul 18 13:20:01 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Fri Jul 18 13:20:01 2003
Subject: EPIA Howto Update
In-Reply-To: <Pine.LNX.4.44.0307180805450.22772-100000@maxroach.lanl.gov>
References: <20030718063715.GA6632@cma.co.jp> <Pine.LNX.4.44.0307180805450.22772-100000@maxroach.lanl.gov>
Message-ID: <20030718173138.GC24213@tsn.or.jp>

On Fri, Jul 18, 2003 at 08:08:24AM -0600, ron minnich wrote:
> suggestion: next week the config tool should be basically done for
> freebios2. You folks cold look at converting DRAM code to C and porting
> the EPIA code to freebios2. It is about 100 times easier to code this
> stuff up in C.

My raminit code does not use SPD. It does "probe" instead. 
(I first saw this method in NetBSD BIOS)
In C, SPD stuff should easily be done, but I'm not very excited
to adapt it to EPIA since I'm quite happy with current probing code.

Probing is implemented with fewer assembly code (and some in C),
but has disadvantage that it can't detect timing parameters
(PC100/133, CL2/CL3) at runtime.
Still it should be done in C 10 times easier though.

--
Takeshi


From linuxbios at xdr.com  Fri Jul 18 14:30:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Jul 18 14:30:01 2003
Subject: EPIA-M SPD progress
Message-ID: <200307181842.h6IIgCZs006021@xdr.com>

I used the freebios/util/scanspd code as a starting point and found out
the DDR ram is at slot 0x50 and can be accessed through standard SMBus reads
at io ports 0x500+. A dump of my working eeprom is this:

128 8 7 12 10 1 64 0 4 117 117 0 128 8 0 1
14 4 12 1 2 32 0 160 117 0 0 80 60 80 45 32
144 144 80 80 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156
Then 0's.

These are read using
int i;
unsigned char val;
smbus_wait_until_ready();
	for(i=0;i<64;++i)
	{
		smbus_read_byte(0x50,i,&val);
		printf("%d%c",val, (i&15)==15 ? '\n' : ' ');
	}

The southbridge vt8235 code sets 1106:3177 RxD1 + RxD2 in its misc_setup.inc.
So standard smbus reads should be available at dram init time.

Probe vs SPD discussion: I think the question is which produces a better
result, regardless of complexity. Probing seems to have disadvantages in
that it can't know how to set timing amounts, signal levels, or clock delays.
It would only allow you to figure out the right column bit size I expect.
What disadvantages does SPD have other than it is more complex? Wouldn't it
let you then be able to correctly use any DDR module you want?

-Dave



From linuxbios at xdr.com  Fri Jul 18 14:35:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Jul 18 14:35:01 2003
Subject: Assembly code errors
Message-ID: <200307181847.h6IIl9pO006041@xdr.com>

When I write some assembly code and I've got the syntax wrong, the build
fails but the line numbers reported in error messages don't relate to the
source I'm working on. I'm wondering could the build process for the assembly
code be changed so the python script creates a global
  toplevel.asm
file that has within it #includes for all the source files? So rather than
cat'ing all the files, you let the compiler include them, so its error
messages will be informative.

There's nothing especially bad about ASM code development, but things
like accurate error reporting can make it easier (or harder when absent).

-Dave


From rminnich at lanl.gov  Fri Jul 18 15:01:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 15:01:01 2003
Subject: EPIA-M SPD progress [PMX:#]
In-Reply-To: <200307181842.h6IIgCZs006021@xdr.com>
Message-ID: <Pine.LNX.4.44.0307181312020.27466-100000@maxroach.lanl.gov>

On Fri, 18 Jul 2003, Dave Ashley wrote:

> What disadvantages does SPD have other than it is more complex? Wouldn't it
> let you then be able to correctly use any DDR module you want?

some SPD roms have incorrect information. You have to take care with SPD. 

Overall, SPD is better. However, if you are on a short fuse and need to 
deliver soon, I would go with probing for now and restrict the type of ram 
you use. 

Longer term, we want to do SPD.

ron



From stepan at suse.de  Fri Jul 18 15:11:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Fri Jul 18 15:11:01 2003
Subject: EPIA-M SPD progress [PMX:#]
In-Reply-To: <Pine.LNX.4.44.0307181312020.27466-100000@maxroach.lanl.gov>; from rminnich@lanl.gov on Fri, Jul 18, 2003 at 01:12:53PM -0600
References: <200307181842.h6IIgCZs006021@xdr.com> <Pine.LNX.4.44.0307181312020.27466-100000@maxroach.lanl.gov>
Message-ID: <20030718212314.A19664@suse.de>

* ron minnich <rminnich at lanl.gov> [030718 21:12]:
> On Fri, 18 Jul 2003, Dave Ashley wrote:
> 
> > What disadvantages does SPD have other than it is more complex? Wouldn't it
> > let you then be able to correctly use any DDR module you want?
> 
> some SPD roms have incorrect information. You have to take care with SPD. 

Does this happen if you buy cheap ram, or ram of a certain type?
How can this kind of problem be avoided? I heard and read this a couple
of times now, but (I think) it never happened to me 'til now

Stefan

-- 
Architecture Team
    SuSE Linux AG


From rminnich at lanl.gov  Fri Jul 18 15:28:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 15:28:00 2003
Subject: EPIA-M SPD progress [PMX:#]
In-Reply-To: <20030718212314.A19664@suse.de>
Message-ID: <Pine.LNX.4.44.0307181339130.27466-100000@maxroach.lanl.gov>

On Fri, 18 Jul 2003, Stefan Reinauer wrote:

> > some SPD roms have incorrect information. You have to take care with SPD. 
> 
> Does this happen if you buy cheap ram, or ram of a certain type?

You need to find quality vendors and stick with them. Even then, you can 
get in trouble. 

> How can this kind of problem be avoided? I heard and read this a couple
> of times now, but (I think) it never happened to me 'til now

It can't as long as vendors mix up SEEPROM and DRAM parts incorrectly.

ron



From ebiederman at lnxi.com  Fri Jul 18 15:47:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jul 18 15:47:01 2003
Subject: EPIA-M SPD progress
In-Reply-To: <200307181842.h6IIgCZs006021@xdr.com>
References: <200307181842.h6IIgCZs006021@xdr.com>
Message-ID: <m3brvrhafu.fsf@maxwell.lnxi.com>

Dave Ashley <linuxbios at xdr.com> writes:

> I used the freebios/util/scanspd code as a starting point and found out
> the DDR ram is at slot 0x50 and can be accessed through standard SMBus reads
> at io ports 0x500+. A dump of my working eeprom is this:
> 
> 128 8 7 12 10 1 64 0 4 117 117 0 128 8 0 1
> 14 4 12 1 2 32 0 160 117 0 0 80 60 80 45 32
> 144 144 80 80 0 0 0 0 0 0 0 0 0 0 0 0
> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156
> Then 0's.
> 
> These are read using
> int i;
> unsigned char val;
> smbus_wait_until_ready();
> 	for(i=0;i<64;++i)
> 	{
> 		smbus_read_byte(0x50,i,&val);
> 		printf("%d%c",val, (i&15)==15 ? '\n' : ' ');
> 	}
> 
> The southbridge vt8235 code sets 1106:3177 RxD1 + RxD2 in its misc_setup.inc.
> So standard smbus reads should be available at dram init time.
> 
> Probe vs SPD discussion: I think the question is which produces a better
> result, regardless of complexity. Probing seems to have disadvantages in
> that it can't know how to set timing amounts, signal levels, or clock delays.
> It would only allow you to figure out the right column bit size I expect.
> What disadvantages does SPD have other than it is more complex? Wouldn't it
> let you then be able to correctly use any DDR module you want?

SPD is required for DDR SDRAM because there are no universally safe timings,
that will work with all DIMMS.  Universally safe timings existed with SDRAM.

As for SPD information being buggy.  Yes vendors can put the wrong labels on
their products.  If someone cares you can usually write the SPD just as easily
as you can read from it, so you can fix the bad SPD data.

Since SPD usage is mandatory for DDR SDRAM it is usually supported.

Eric



From ebiederman at lnxi.com  Fri Jul 18 16:01:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jul 18 16:01:01 2003
Subject: Assembly code errors
In-Reply-To: <200307181847.h6IIl9pO006041@xdr.com>
References: <200307181847.h6IIl9pO006041@xdr.com>
Message-ID: <m365lzfv85.fsf@maxwell.lnxi.com>

Dave Ashley <linuxbios at xdr.com> writes:

> When I write some assembly code and I've got the syntax wrong, the build
> fails but the line numbers reported in error messages don't relate to the
> source I'm working on. I'm wondering could the build process for the assembly
> code be changed so the python script creates a global
>   toplevel.asm
> file that has within it #includes for all the source files? So rather than
> cat'ing all the files, you let the compiler include them, so its error
> messages will be informative.

So far it is CPP doing the including.   You can look at the crt0.s file
and track down the error from there.  Imperfect but it works.

The long term solution is to use romcc.  That already reports the correct
line numbers.
 
> There's nothing especially bad about ASM code development, but things
> like accurate error reporting can make it easier (or harder when absent).

I agree it is nice not to need an intermediate step.  Unless it is an absolutely
trivial change we probably won't do anything for the freebios1 tree.  As we don't want
to break anything.

Eric



From rminnich at lanl.gov  Fri Jul 18 16:04:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 16:04:01 2003
Subject: Assembly code errors
In-Reply-To: <m365lzfv85.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307181415490.27466-100000@maxroach.lanl.gov>

On 18 Jul 2003, Eric W. Biederman wrote:

> > There's nothing especially bad about ASM code development, but things
> > like accurate error reporting can make it easier (or harder when absent).
> 
> I agree it is nice not to need an intermediate step.  Unless it is an absolutely
> trivial change we probably won't do anything for the freebios1 tree.  As we don't want
> to break anything.

yes, I'm sorry about this, but we're trying hard to freeze the 1 tree. 
This is a big change and I think it is too late for it.

ron



From linuxbios at xdr.com  Fri Jul 18 17:03:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Jul 18 17:03:01 2003
Subject: EPIA-M SPD progress [PMX:#]
Message-ID: <200307182115.h6ILFQCw006535@xdr.com>

src/sdram/smbus_pcibus.inc has some smbus code, I was able to compile it
into the epia-m tree and do some test SMBUS_READ_BYTE calls that actually
read out values from the ddr eeprom. I had to #if out the section that
actually does the dram configuration to get it to compile.

I'm in a bad way for experimenting with this, I have to physically remove
the BIOS and plug in a new one if something goes bad, and do the reverse
to recover. I've fried 2 motherboards with my pliers rubbing out traces
under the flashrom socket (good luck fixing that!).

If the dram settings are wrong it might make the product flaky. We're
trying to field some units for in situ testing real soon, and the system
has to be solid. We can probably hardcode the dram configuration for our
known good ddr module that we're using mostly. However I'd like the system
to function the right way. I'll keep messing with it for now.

-Dave


>some SPD roms have incorrect information. You have to take care with SPD. 
>
>Overall, SPD is better. However, if you are on a short fuse and need to 
>deliver soon, I would go with probing for now and restrict the type of ram 
>you use. 
>
>Longer term, we want to do SPD.
>
>ron
>


From rminnich at lanl.gov  Fri Jul 18 17:16:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 18 17:16:00 2003
Subject: EPIA-M SPD progress [PMX:#] [PMX:#]
In-Reply-To: <200307182115.h6ILFQCw006535@xdr.com>
Message-ID: <Pine.LNX.4.44.0307181527130.27466-100000@maxroach.lanl.gov>

On Fri, 18 Jul 2003, Dave Ashley wrote:

> the BIOS and plug in a new one if something goes bad, and do the reverse
> to recover. I've fried 2 motherboards with my pliers rubbing out traces
> under the flashrom socket (good luck fixing that!).

you need to go to radioshack and get the flash part extractors. They are 
perfect for this. 

Also, failing that, put dental floss under the chip when you install and 
and then you can lift it out (thanks to Steve James for this one).

ron



From gwatson at lanl.gov  Fri Jul 18 17:29:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Fri Jul 18 17:29:00 2003
Subject: Assembly code errors [PMX:#]
In-Reply-To: <200307181847.h6IIl9pO006041@xdr.com>
References: <200307181847.h6IIl9pO006041@xdr.com>
Message-ID: <p06001a00bb3e16b8c76e@[10.0.1.2]>

This is what the new configuration scheme in freebios2 does.

Greg

At 2:25 PM -0700 18/7/03, Dave Ashley wrote:
>When I write some assembly code and I've got the syntax wrong, the build
>fails but the line numbers reported in error messages don't relate to the
>source I'm working on. I'm wondering could the build process for the assembly
>code be changed so the python script creates a global
>   toplevel.asm
>file that has within it #includes for all the source files? So rather than
>cat'ing all the files, you let the compiler include them, so its error
>messages will be informative.
>
>There's nothing especially bad about ASM code development, but things
>like accurate error reporting can make it easier (or harder when absent).
>
>-Dave
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From bari at onelabs.com  Fri Jul 18 17:53:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Fri Jul 18 17:53:01 2003
Subject: EPIA-M SPD progress [PMX:#]
In-Reply-To: <20030718212314.A19664@suse.de>
References: <200307181842.h6IIgCZs006021@xdr.com> <Pine.LNX.4.44.0307181312020.27466-100000@maxroach.lanl.gov> <20030718212314.A19664@suse.de>
Message-ID: <3F186FB5.6070402@onelabs.com>

Stefan Reinauer wrote:

>* ron minnich <rminnich at lanl.gov> [030718 21:12]:
>  
>
>>On Fri, 18 Jul 2003, Dave Ashley wrote:
>>
>>    
>>
>>>What disadvantages does SPD have other than it is more complex? Wouldn't it
>>>let you then be able to correctly use any DDR module you want?
>>>      
>>>
>>some SPD roms have incorrect information. You have to take care with SPD. 
>>    
>>
>
>Does this happen if you buy cheap ram, or ram of a certain type?
>How can this kind of problem be avoided? I heard and read this a couple
>of times now, but (I think) it never happened to me 'til now
>
SPD only works if the RAM vendor properly programs the serial EEPROM. 
RAM is a commodity item and vendors churn out millions of modules a 
year. An assembly line can build thousands of modules per day. If there 
is a hickup on the procurement side (parts not showing up or late  for 
assembly) an assembler may be forced to use a different part number that 
is in stock that is still compatible with the module pcb layout but does 
not have the same timing specs. Other times the SPD info is just 
programmed wrong and the only QC is based on the end user complaining 
about a problem. Another way that SPD breaks is by flaky software or SPD 
bus corruption that writes data to the SPD device on the RAM module. 
Don't be surprised by how much broken PC hardware gets sent off to 
market with fixes via BIOS and other still broken means.

-Bari




From linuxbios at techfreakz.net  Fri Jul 18 18:05:00 2003
From: linuxbios at techfreakz.net (Alex Scarbro)
Date: Fri Jul 18 18:05:00 2003
Subject: EPIA-M SPD progress [PMX:#]
In-Reply-To: <3F186FB5.6070402@onelabs.com>
Message-ID: <2003718231649.884120@techfreakz>

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From jerj at coplanar.net  Fri Jul 18 18:24:01 2003
From: jerj at coplanar.net (Jeremy Jackson)
Date: Fri Jul 18 18:24:01 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306201005080.9687-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306201005080.9687-100000@maxroach.lanl.gov>
Message-ID: <3F187662.30806@coplanar.net>

ron minnich wrote:
> I need something that comes in at ca. $25 ...

Perhaps a high end 450W power supply (cost divided by 4) with a custom 
"Y" cable from a cable maker.  In quantity the cables might be cheap 
enough.  Someone will have to calculate a power budget for each voltage. 
  It would be best to also measure an actual system's current draw on 
each rail, under  full load to verify.  You would probably require 
several hundred (4 board) systems to justify the initial design costs.

Jeremy



From jerj at coplanar.net  Fri Jul 18 18:51:01 2003
From: jerj at coplanar.net (Jeremy Jackson)
Date: Fri Jul 18 18:51:01 2003
Subject: IDE chipsets and hdd hotswap
Message-ID: <3F187CA2.6050702@coplanar.net>

Hi,

I have an application for IDE hdd hotswap, and I'm trying to determine 
the best chipset.  I think one thing to consider is the ability or 
Linux/LinuxBIOS to completely initialize the chipset from power on reset 
to use UltraDMA (133 if possible).  If it can do that, logically it can 
re-do it when a different drive is swapped in.

So I'm asking on the LinuxBIOS list since IDE chip initialization has 
surely been dealt with.  Can anyone give me the name of chipsets which 
they have gotten going with UltraDMA and LinuxBIOS?

The second issue is the ability to tri-state off the bus, but I can find 
that info elsewhere (ie kernel source)  The hdparm utility/kernel driver 
has the beginnings of this support.

I know that the Promise PCI card controllers have a bios which probably 
contains hidden magic, perhaps another off-board card can be found.

Regards,

Jeremy



From rsmith at bitworks.com  Fri Jul 18 19:40:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Fri Jul 18 19:40:00 2003
Subject: IDE chipsets and hdd hotswap
In-Reply-To: <3F187CA2.6050702@coplanar.net>
References: <3F187CA2.6050702@coplanar.net>
Message-ID: <3F188821.1030501@bitworks.com>

Jeremy Jackson wrote:

> 
> The second issue is the ability to tri-state off the bus, but I can find 
> that info elsewhere (ie kernel source)  The hdparm utility/kernel driver 
> has the beginnings of this support.

I know its an old chipset but the 440bx has a bit that you set to 
disable the ide[01] device and tristate all its lines.  I suspect that 
most of the other chipsets have the same type setup.  That functionality 
and a gp input pin with a really weak pullup attached to a ground pin on 
the IDE cable should give you hotplug functionality.


-- 
Richard A. Smith
rsmith at bitworks.com




From YhLu at tyan.com  Fri Jul 18 20:44:01 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jul 18 20:44:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302DD1423@TYANWEB>

Eric,

My boss has said that I can release the source code to you.

Please find out the patch I made. Make the diff to today's tree.

I didn't test RON new script and still use the old scripts tools.

I strip out the LSI scsi support, because I don't know if there is any
license problem, and I have referred to their documents and may need put
their FW in the ROM.

It's greater you add ops->enable function that make it easy to handle
special device. To some device if it is not gotten magic code, it will not
get the resource allocate to it. Before that I have to do it in init
function and re-allocate the resource to it again. Please refer to my old
amd8131_ioapic.c in southbridge/amd8111. Also you init the io_base, upper16
reg, otherwise the device in PCIX will not got io port allocated to them,
and will not work. 

I have tested Stefan's the code about coherent_ht.c, and add some hardcode
to it.
coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one.
coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones.

raminit.c and raminit.1.c are till the hardcode one, and I have tried to use
the configurable one, but auto.c can not be compiled, it is too big and used
up REG?
The old one has been renamed to raminit.o.c. 

To start other cpus, in auto.c  We must enable apic and make sure all
apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu
function.

Again, thank you all to answer my questions to help Tyan s2880 work with
LinuxBIOS.

Regards

Yinghai Lu



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From ijpraveen1 at yahoo.com  Fri Jul 18 23:19:00 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Fri Jul 18 23:19:00 2003
Subject: Loading OS from Flash
Message-ID: <20030719033059.48504.qmail@web41704.mail.yahoo.com>

Hi
 
          Thanks. My Geode one is SC1200.

ron minnich <rminnich at lanl.gov> wrote:

On Fri, 18 Jul 2003, John Praveen wrote:

> I am new to linux bios. My project is based on
> geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB). 

I have sad news. You can't get a 4 MB chip on that board, I bet. 

           I can't get to this. This means that 4 MB Flash ROM cannot be used with SC1200? Or is it not supported in LinuxBIOS. Plz help me to understand these.

It is 
probably 4 Mbits, 512 KB. You'll have to put that overweight linux kernel 
on a diet to get it to fit in there. 

One option is 2.4.0 or so, that might fit.

Can DoC fit on your geode anywhere?


No I don't use DiskOnChip.


ron




---------------------------------
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
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From aip at cwlinux.com  Sat Jul 19 00:04:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Sat Jul 19 00:04:01 2003
Subject: EPIA-M DDR SPD detection [PMX:#]
In-Reply-To: <Pine.LNX.4.44.0307181039180.23073-100000@maxroach.lanl.gov>; from ron minnich on Fri, Jul 18, 2003 at 10:39:35AM -0600
References: <200307181630.h6IGUhcJ005649@xdr.com> <Pine.LNX.4.44.0307181039180.23073-100000@maxroach.lanl.gov>
Message-ID: <20030719121549.A17693@mail.cwlinux.com>

Hi Ron,

> are you sure that the I2C is not being read now on EPIA-M? I have not 
> looked but it seems it ought to be.
DDR init is now hardcoded such that it might work for some DDR but not
all.  In long term, SPD will be implemented.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From aip at cwlinux.com  Sat Jul 19 00:05:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Sat Jul 19 00:05:00 2003
Subject: EPIA-M SPD progress [PMX:#]
In-Reply-To: <200307182115.h6ILFQCw006535@xdr.com>; from Dave Ashley on Fri, Jul 18, 2003 at 02:15:26PM -0700
References: <200307182115.h6ILFQCw006535@xdr.com>
Message-ID: <20030719121648.B17693@mail.cwlinux.com>

Hi Dave,

> src/sdram/smbus_pcibus.inc has some smbus code, I was able to compile it
> into the epia-m tree and do some test SMBUS_READ_BYTE calls that actually
> read out values from the ddr eeprom. I had to #if out the section that
> actually does the dram configuration to get it to compile.
> I'm in a bad way for experimenting with this, I have to physically remove
> the BIOS and plug in a new one if something goes bad, and do the reverse
> to recover. I've fried 2 motherboards with my pliers rubbing out traces
> under the flashrom socket (good luck fixing that!).
BIOS Savior will save you.  :)

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From ebiederman at lnxi.com  Sat Jul 19 00:22:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sat Jul 19 00:22:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <3174569B9743D511922F00A0C943142302DD1423@TYANWEB>
References: <3174569B9743D511922F00A0C943142302DD1423@TYANWEB>
Message-ID: <m3oezr6sm4.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> My boss has said that I can release the source code to you.
> 
> Please find out the patch I made. Make the diff to today's tree.
> 
> I didn't test RON new script and still use the old scripts tools.
> 
> I strip out the LSI scsi support, because I don't know if there is any
> license problem, and I have referred to their documents and may need put
> their FW in the ROM.
> 
> It's greater you add ops->enable function that make it easy to handle
> special device. To some device if it is not gotten magic code, it will not
> get the resource allocate to it. Before that I have to do it in init
> function and re-allocate the resource to it again. Please refer to my old
> amd8131_ioapic.c in southbridge/amd8111. Also you init the io_base, upper16
> reg, otherwise the device in PCIX will not got io port allocated to them,
> and will not work. 
> 
> I have tested Stefan's the code about coherent_ht.c, and add some hardcode
> to it.
> coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one.
> coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones.
> 
> raminit.c and raminit.1.c are till the hardcode one, and I have tried to use
> the configurable one, but auto.c can not be compiled, it is too big and used
> up REG?
> The old one has been renamed to raminit.o.c. 
> 
> To start other cpus, in auto.c  We must enable apic and make sure all
> apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu
> function.
> 
> Again, thank you all to answer my questions to help Tyan s2880 work with
> LinuxBIOS.

Welcome. 

You have the most interesting time.  Your stuff always seems to come in 
just as I am about to walk away for the day.

I have just gotten SMP working in my tree and that is checked in.

I did the fun thing and am using the apic timer as my timer.  It has
the nice property of working without calibration because it is based
on the FSB clock, which on the Opteron is fixed at 200Mhz.  And as a
very cool thing I have that code compiling both ways.

More later, Good Night.

Eric



From bari at onelabs.com  Sat Jul 19 11:16:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Sat Jul 19 11:16:01 2003
Subject: IDE chipsets and hdd hotswap
In-Reply-To: <3F187CA2.6050702@coplanar.net>
References: <3F187CA2.6050702@coplanar.net>
Message-ID: <3F196463.8060005@onelabs.com>

Jeremy Jackson wrote:

> So I'm asking on the LinuxBIOS list since IDE chip initialization has 
> surely been dealt with.  Can anyone give me the name of chipsets which 
> they have gotten going with UltraDMA and LinuxBIOS?
>
> The second issue is the ability to tri-state off the bus, but I can 
> find that info elsewhere (ie kernel source)  The hdparm utility/kernel 
> driver has the beginnings of this support.
>
> I know that the Promise PCI card controllers have a bios which 
> probably contains hidden magic, perhaps another off-board card can be 
> found.

Are you looking for chipsets with integrated IDE controllers that 
support UDMA or just PCI based IDE controller IC's that support UDMA and 
can tri-state the IDE lines?

-Bari




From jerj at coplanar.net  Sat Jul 19 13:45:01 2003
From: jerj at coplanar.net (Jeremy Jackson)
Date: Sat Jul 19 13:45:01 2003
Subject: IDE chipsets and hdd hotswap
In-Reply-To: <3F196463.8060005@onelabs.com>
References: <3F187CA2.6050702@coplanar.net> <3F196463.8060005@onelabs.com>
Message-ID: <3F198678.50602@coplanar.net>

Maybe I should clarify.  I'm not designing a board.  I just want to 
identify and IDE controller, integrated or not, that has complete Linux 
support for PIO/UDMA tuning (and tri-state but many support this) so 
that after hot-swap (which will power cycle the drive, change the model, 
etc.), the drive and controller can be configured without rebooting to 
get the BIOS involved.

My logic for asking on the LinuxBIOS list is that since LinuxBIOS does 
the basics from power on, and Linux finishes things, *everything* that 
is needed must be there if UDMA works with Linux/LinuxBIOS, and all that 
I have to do is move some code around so the hdparm -U/-R and -b stuff 
is a bit easier to work with.

So, I guess my question should be: Does anyone have and IDE drive 
working  with UDMA under LinuxBIOS/Linux?  If so, please tell me what 
chipset(s).

Thanks,

Jeremy

Bari Ari wrote:
> Jeremy Jackson wrote:
> 
>> So I'm asking on the LinuxBIOS list since IDE chip initialization has 
>> surely been dealt with.  Can anyone give me the name of chipsets which 
>> they have gotten going with UltraDMA and LinuxBIOS?
>>
>> The second issue is the ability to tri-state off the bus, but I can 
>> find that info elsewhere (ie kernel source)  The hdparm utility/kernel 
>> driver has the beginnings of this support.
>>
>> I know that the Promise PCI card controllers have a bios which 
>> probably contains hidden magic, perhaps another off-board card can be 
>> found.
> 
> 
> Are you looking for chipsets with integrated IDE controllers that 
> support UDMA or just PCI based IDE controller IC's that support UDMA and 
> can tri-state the IDE lines?
> 
> -Bari
> 




From ts1 at tsn.or.jp  Sat Jul 19 13:51:59 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Sat Jul 19 13:51:59 2003
Subject: EPIA-M SPD progress
In-Reply-To: <200307181842.h6IIgCZs006021@xdr.com>
References: <200307181842.h6IIgCZs006021@xdr.com>
Message-ID: <20030719175810.GB2055@tsn.or.jp>

On Fri, Jul 18, 2003 at 11:42:12AM -0700, Dave Ashley wrote:
> Probe vs SPD discussion: I think the question is which produces a better
> result, regardless of complexity. Probing seems to have disadvantages in
> that it can't know how to set timing amounts, signal levels, or clock delays.

I know SPD is the right thing to do, and the complexity is the cost
we have to pay for that.

Current code for EPIA is just simple and stupid but works for
(almost) everyone.

Eric said romcc bloats the resulting code since it has to
inline all the function calls. I understand how hard doing
non-inline functions without RAM is but code bloat sounds
not very sexy to me.

I will look into it when I am ready and feel good enough
to learn how to read that yet another kind of hex dumps...


> It would only allow you to figure out the right column bit size I expect.

And the amount of RAM too of course. :)

> What disadvantages does SPD have other than it is more complex? Wouldn't it
> let you then be able to correctly use any DDR module you want?

I don't know about DDR, but for EPIA, which uses non-DDR SDRAM,
so far I haven't heard of a case where the current code fails.

On wrong SPD: I figured out why most BIOSes have the setup option
to force DRAM parameters other than "By SPD".
Do we need that feature too? :)

--
Takeshi


From ebiederman at lnxi.com  Sun Jul 20 04:45:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sun Jul 20 04:45:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <3174569B9743D511922F00A0C943142302DD1423@TYANWEB>
References: <3174569B9743D511922F00A0C943142302DD1423@TYANWEB>
Message-ID: <m3brvpvaj0.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> My boss has said that I can release the source code to you.
> 
> Please find out the patch I made. Make the diff to today's tree.
> 
> I didn't test RON new script and still use the old scripts tools.
> 
> I strip out the LSI scsi support, because I don't know if there is any
> license problem, and I have referred to their documents and may need put
> their FW in the ROM.

Ah, an interesting problem.
 
> It's greater you add ops->enable function that make it easy to handle
> special device. To some device if it is not gotten magic code, it will not
> get the resource allocate to it. Before that I have to do it in init
> function and re-allocate the resource to it again. 

Welcome.

> Please refer to my old amd8131_ioapic.c in southbridge/amd8111. 

> Also you init the io_base, upper16 reg, otherwise the device in PCIX
> will not got io port allocated to them,  and will not work. 

Sorry I don't quite parse that sentence.

> I have tested Stefan's the code about coherent_ht.c, and add some hardcode
> to it.
> coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one.
> coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones.

Interesting looking at this code are you working with C0 stepping Opterons?
I have the stock B3 and am having fun getting the memory resets in all of the proper
places.
 
> raminit.c and raminit.1.c are till the hardcode one, and I have tried to use
> the configurable one, but auto.c can not be compiled, it is too big and used
> up REG?

Looking.  It is your romcc options.  By default romcc will not use mmx
or sse registers unless you tell it that you have them.  I have been
doing this with -mcpu=k8.  The register pressure is much less when you
have 24 registers to work with instead of just 8.

> The old one has been renamed to raminit.o.c. 
> 
> To start other cpus, in auto.c  We must enable apic and make sure all
> apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu
> function.

Yep, an interesting way of doing it.  
 
> Again, thank you all to answer my questions to help Tyan s2880 work with
> LinuxBIOS.

Ron, Stefan.  Could one of you help with merging Yinghai's code?  I
might have time, but I don't think I will manage it before I leave
for OLS on Tuesday.

Eric



From rminnich at lanl.gov  Sun Jul 20 12:41:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jul 20 12:41:00 2003
Subject: EPIA-M SPD progress
In-Reply-To: <20030719175810.GB2055@tsn.or.jp>
Message-ID: <Pine.LNX.4.44.0307201052190.27010-100000@maxroach.lanl.gov>

On Sun, 20 Jul 2003, SONE Takeshi wrote:

> On wrong SPD: I figured out why most BIOSes have the setup option
> to force DRAM parameters other than "By SPD".
> Do we need that feature too? :)

We actually have had serious conversations on this. The conclusion was 
"don't buy busted memory". 

If there are no universal save DDR settings it will probably be impossible
for the BIOS to run long enough to put up a "force DRAM parameters" page 
anyway.

ron



From rminnich at lanl.gov  Sun Jul 20 12:47:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jul 20 12:47:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <m3brvpvaj0.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307201058240.27010-100000@maxroach.lanl.gov>

What I will do is first, get my tree in sync with Greg's new config tool 
code and Eric's new updates for SMP; Then look at YhLu's code and try to 
get it integrated.

Next week is K8 week for me. It is very exciting to see this coming up on 
my bench after reading about all the work you folks have been doing.

ron



From ijpraveen1 at yahoo.com  Mon Jul 21 01:14:00 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Mon Jul 21 01:14:00 2003
Subject: Loading OS from Flash ROM!
Message-ID: <20030721052631.37896.qmail@web41701.mail.yahoo.com>


On Fri, 18 Jul 2003, John Praveen wrote:

> I am new to linux bios. My project is based on
> geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB). 

>I have sad news. You can't get a 4 MB chip on that board, I bet. 

           I can't get to this. This means that 4 MB Flash ROM cannot be used with SC1200? Or is it not supported in LinuxBIOS. Plz help me to understand these.

>It is 
>probably 4 Mbits, 512 KB. You'll have to put that overweight linux kernel 
>on a diet to get it to fit in there. 

>One option is 2.4.0 or so, that might fit.

>Can DoC fit on your geode anywhere?


No I don't use DiskOnChip.

Thanks.




---------------------------------
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
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From bari at onelabs.com  Mon Jul 21 02:26:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Mon Jul 21 02:26:01 2003
Subject: Loading OS from Flash ROM!
In-Reply-To: <20030721052631.37896.qmail@web41701.mail.yahoo.com>
References: <20030721052631.37896.qmail@web41701.mail.yahoo.com>
Message-ID: <3F1B8B21.7000708@onelabs.com>

John Praveen wrote:

> On Fri, 18 Jul 2003, John Praveen wrote:
>
> > I am new to linux bios. My project is based on
> > geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB).
>
> >I have sad news. You can't get a 4 MB chip on that board, I bet.
>
>            I can't get to this. This means that 4 MB Flash ROM cannot 
> be used with SC1200? Or is it not supported in LinuxBIOS. Plz help me 
> to understand these.
>
The SC1200 can address up to 16MB of memory on the ISA bus (which is 
where the Flash Rom would be located for the BIOS if strapped for ISA 
BIOS ROM seek after reset) or it can use the LPC bus (if strapped for 
LPC BIOS ROM seek after reset). This is what the SC1200 is capable of if 
you're designing your own board. It's just unlikely that if you're using 
an off the shelf board that it will support >2MB of flash ROM on ISA. If 
it uses an LPC ROM then it's probably soldered down and a 2MB device. 
LinuxBIOS can support a 4MB device or up to a 4GB flash ROM (if they 
actually existed).

> >It is
> >probably 4 Mbits, 512 KB. You'll have to put that overweight linux 
> kernel
> >on a diet to get it to fit in there.
>
> >One option is 2.4.0 or so, that might fit.
>
> >Can DoC fit on your geode anywhere?
>
> No I don't use DiskOnChip.
>
> Thanks.
>
> ------------------------------------------------------------------------
> Do you Yahoo!?
> SBC Yahoo! DSL 
> <http://pa.yahoo.com/*http://rd.yahoo.com/evt=1207/*http://promo.yahoo.com/sbc/> 
> - Now only $29.95 per month! 





From tamer.higazi at web.de  Mon Jul 21 10:15:00 2003
From: tamer.higazi at web.de (Tamer Higazi)
Date: Mon Jul 21 10:15:00 2003
Subject: about linux bios on newer boards...
Message-ID: <3F1BF844.5060808@web.de>

Hi!
I'd like to buy a new Computer and i am using Linux continuesly. I have 
asked myself if a Linuxbios could run on a newer board.

Either i am asking myself, if a linuxbios could halt (run down) my linux 
machine if i push the power switch on my computer as it is allready 
possible on WinXP.

For any help and answer thank you

Tamer




From linuxbios at xdr.com  Mon Jul 21 10:22:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Mon Jul 21 10:22:01 2003
Subject: EPIA-M, linuxbios + power button
Message-ID: <200307211435.h6LEZBSE012837@xdr.com>

Under award bios the power button did an instant off. Under linuxbios I
have to hold the power button down for 4 seconds to get the power to go
off. I vaguely remember reading about controlling the power button, but I can't
find it in the docs. Does anyone know how to fix this?


From rminnich at lanl.gov  Mon Jul 21 10:41:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 10:41:00 2003
Subject: Loading OS from Flash ROM!
In-Reply-To: <20030721052631.37896.qmail@web41701.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0307210853240.2915-100000@maxroach.lanl.gov>

On Sun, 20 Jul 2003, John Praveen wrote:

>            I can't get to this. This means that 4 MB Flash ROM cannot be
> used with SC1200? Or is it not supported in LinuxBIOS. Plz help me to
> understand these.

it means that you said "4 MB" which is a common mistake. If you send me 
the part # of flash I will bet it is actually 4Mbits (i.e. 4 Mb)

you can't put linux kernel in 4Mbits any more.

ron



From ts1 at tsn.or.jp  Mon Jul 21 10:45:00 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Mon Jul 21 10:45:00 2003
Subject: EPIA-M, linuxbios + power button
In-Reply-To: <200307211435.h6LEZBSE012837@xdr.com>
References: <200307211435.h6LEZBSE012837@xdr.com>
Message-ID: <20030721145751.GA28607@tsn.or.jp>

On Mon, Jul 21, 2003 at 07:35:11AM -0700, Dave Ashley wrote:
> Under award bios the power button did an instant off. Under linuxbios I
> have to hold the power button down for 4 seconds to get the power to go
> off. I vaguely remember reading about controlling the power button, but I can't
> find it in the docs. Does anyone know how to fix this?

On EPIA, I neither found the bit to switch the functionality of
power button.
I thought that "Instant Off" feature is implemented by SMM BIOS.

So I wrote a small daemon program to poll the status of power button,
and invokes "/sbin/init 0" when hit.
Polling in the user space will not miss a short-time button press
(in my application it is simulated by PIC micro)
because the status bit will be stay ON once it is pressed.

Probably the same will apply to EPIA-M.

--
Takeshi


From rminnich at lanl.gov  Mon Jul 21 10:55:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 10:55:01 2003
Subject: EPIA-M, linuxbios + power button [PMX:#]
In-Reply-To: <200307211435.h6LEZBSE012837@xdr.com>
Message-ID: <Pine.LNX.4.44.0307210905560.2915-100000@maxroach.lanl.gov>

On Mon, 21 Jul 2003, Dave Ashley wrote:

> Under award bios the power button did an instant off. Under linuxbios I
> have to hold the power button down for 4 seconds to get the power to go
> off. I vaguely remember reading about controlling the power button, but I can't
> find it in the docs. Does anyone know how to fix this?

what mobo? Is this the 440bx one again? 

you can make the power switch event cause an interrupt, I guess, and catch 
it. 

Linux power handling could use help, if anybody wants to take that on.

ron



From bari at onelabs.com  Mon Jul 21 12:17:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Mon Jul 21 12:17:01 2003
Subject: Loading OS from Flash ROM!
In-Reply-To: <3F1B8B21.7000708@onelabs.com>
References: <20030721052631.37896.qmail@web41701.mail.yahoo.com> <3F1B8B21.7000708@onelabs.com>
Message-ID: <3F1C15AC.7030006@onelabs.com>

Bari Ari wrote:

> John Praveen wrote:
>
>> On Fri, 18 Jul 2003, John Praveen wrote:
>>
>> > I am new to linux bios. My project is based on
>> > geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB).
>>
>> >I have sad news. You can't get a 4 MB chip on that board, I bet.
>>
>>            I can't get to this. This means that 4 MB Flash ROM cannot 
>> be used with SC1200? Or is it not supported in LinuxBIOS. Plz help me 
>> to understand these.
>>
> The SC1200 can address up to 16MB of memory on the ISA bus (which is 
> where the Flash Rom would be located for the BIOS if strapped for ISA 
> BIOS ROM seek after reset) or it can use the LPC bus (if strapped for 
> LPC BIOS ROM seek after reset). This is what the SC1200 is capable of 
> if you're designing your own board. It's just unlikely that if you're 
> using an off the shelf board that it will support >2MB of flash ROM on 
> ISA. If it uses an LPC ROM then it's probably soldered down and a 2MB 
> device. LinuxBIOS can support a 4MB device or up to a 4GB flash ROM 
> (if they actually existed). 

Sorry about the typos. (MB megabyte vs Mb megabit) That last sentence 
should be:

It's just unlikely that if you're using an off the shelf board that it 
will support >2Mb of flash ROM on ISA. If it uses an LPC ROM then it's 
probably soldered down and a 2Mb device. LinuxBIOS can support a 4MB 
device or up to a 4GB flash ROM (if they actually existed).

-Bari




From ts1 at tsn.or.jp  Mon Jul 21 12:49:00 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Mon Jul 21 12:49:00 2003
Subject: EPIA-M, linuxbios + power button
In-Reply-To: <20030721145751.GA28607@tsn.or.jp>
References: <200307211435.h6LEZBSE012837@xdr.com> <20030721145751.GA28607@tsn.or.jp>
Message-ID: <20030721170118.GB28607@tsn.or.jp>

On Mon, Jul 21, 2003 at 11:57:51PM +0900, SONE Takeshi wrote:
> So I wrote a small daemon program to poll the status of power button,
> and invokes "/sbin/init 0" when hit.

Of course this starts normal shutdown sequence rather than 
Instant Off.
You will again have to deal with PM I/O space to power off.

Handling SCI interrupt in kernel space would be better solution
but userspace program is almost trivial.

--
Takeshi


From YhLu at tyan.com  Mon Jul 21 13:21:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 21 13:21:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302DD1478@TYANWEB>

Eric,

Thanks info about ROMCC option about -mcpu=k8. I will try and make the RAM
can be configurable.

My CPU is C0, In Opteron We may need to manipulate the MSR to enable the
apic.

Regards

Yinghai Lu


YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> My boss has said that I can release the source code to you.
> 
> Please find out the patch I made. Make the diff to today's tree.
> 
> I didn't test RON new script and still use the old scripts tools.
> 
> I strip out the LSI scsi support, because I don't know if there is any
> license problem, and I have referred to their documents and may need put
> their FW in the ROM.

Ah, an interesting problem.
 
> It's greater you add ops->enable function that make it easy to handle
> special device. To some device if it is not gotten magic code, it will not
> get the resource allocate to it. Before that I have to do it in init
> function and re-allocate the resource to it again. 

Welcome.

> Please refer to my old amd8131_ioapic.c in southbridge/amd8111. 

> Also you init the io_base, upper16 reg, otherwise the device in PCIX
> will not got io port allocated to them,  and will not work. 

Sorry I don't quite parse that sentence.

> I have tested Stefan's the code about coherent_ht.c, and add some hardcode
> to it.
> coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode
one.
> coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones.

Interesting looking at this code are you working with C0 stepping Opterons?
I have the stock B3 and am having fun getting the memory resets in all of
the proper
places.
 
> raminit.c and raminit.1.c are till the hardcode one, and I have tried to
use
> the configurable one, but auto.c can not be compiled, it is too big and
used
> up REG?

Looking.  It is your romcc options.  By default romcc will not use mmx
or sse registers unless you tell it that you have them.  I have been
doing this with -mcpu=k8.  The register pressure is much less when you
have 24 registers to work with instead of just 8.

> The old one has been renamed to raminit.o.c. 
> 
> To start other cpus, in auto.c  We must enable apic and make sure all
> apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu
> function.

Yep, an interesting way of doing it.  
 
> Again, thank you all to answer my questions to help Tyan s2880 work with
> LinuxBIOS.

Ron, Stefan.  Could one of you help with merging Yinghai's code?  I
might have time, but I don't think I will manage it before I leave
for OLS on Tuesday.

Eric


From linuxbios at xdr.com  Mon Jul 21 14:36:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Mon Jul 21 14:36:01 2003
Subject: EPIA-M DDR ram init progress
Message-ID: <200307211849.h6LInQ8Q013431@xdr.com>

As a recap I was trying to get 2 specific DDR modules working with the
epia-m. One has ICT chips and the other has GET chips. The ICT module works
with the hardcoded dram configuration, but the GET module doesn't.
ICT = 1 bank 128M colbits = 10
GET = 2 banks 64M colbits = 9

I had tried hardcoding the dram settings to the ones award bios uses for the
GET module, but it wasn't working. I figured out what the problem was.
I need to do the ddr setup for each bank on the ddr module, not just the
first one. The hardcoded settings correspond to a ddr with just a single bank.

SPD contents is very easy to access. The epia-m code is including
src/northbridge/via/vt8623/raminit.inc
to initialize ram. I found problems with this, the jedec ddr init spec
sequence calls for reads of the ddr memory, this source actually does some
writes.

I'm wondering what the preferred way of implementing spd for epia-m would
be. Should instead of including src/northbridge/via/vt8623/raminit.inc I put
that code in with the epia-m code, mix it with the smbus SPD read code,
and leave the result in the epia-m tree? Or should I modify the
src/northbridge/via/vt8623/raminit.inc file directly? I don't see how that
can work since the SMBUS/SPD is accessed with the vt8235 registers, but the
DDR dram control registers are part of the northbridge.

I can rebuild linuxbios to have it work hardcoded for either memory module
type and it works fine, and I can probably live with this state until
someone else gets SPD working if it might happen within a month or two.
Otherwise I'll probably have to tackle it myself.

VIA's Bios porting guide for the nortbridge on the epia-m seems very
explicit on how to configure the ddr memory based on the SPD settings.
Implementing it should just be a matter of grinding through their flow charts.
It's simplified because it only has to deal with DDR memory.

-Dave


From rminnich at lanl.gov  Mon Jul 21 15:42:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 15:42:01 2003
Subject: silly ld question
Message-ID: <Pine.LNX.4.44.0307211353280.2915-100000@maxroach.lanl.gov>

anybody know why ld would give you something like this:

bash-2.05b$ readelf -l linuxbios

Elf file type is EXEC (Executable file)
Entry point 0xffff0004
There are 3 program headers, starting at offset 52

Program Headers:
  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
  LOAD           0x001000 0xffff0000 0xffff0000 0x117d0 0x117d0 RWE 0x1000
  LOAD           0x012fd8 0xffffffd8 0xffffffd8 0x00028 0x00028 RWE 0x1000
  LOAD           0x013ff0 0xfffffff0 0xfffffff0 0x00000 0x00000 RW  0x1000

 Section to Segment mapping:
  Segment Sections...
   00     .rom .payload .reset .id 
   01     .reset .id 
   02     
bash-2.05b$ emacs ldoptions 


note that section 00 and section 01 have got the .reset and .id sections. 
This is misdirecting objcopy to do the wrong thing. 

What could cause ld to put duplicate section names in two different 
segments? 

What's odder: the ldcscripts that produce this file, and the right file:

Program Headers:
  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
  LOAD           0x001000 0xffff0000 0xffff0000 0x10000 0x10000 RWE 0x1000
  LOAD           0x011ff0 0xfffffff0 0xfffffff0 0x00000 0x00000 RW  0x1000

 Section to Segment mapping:
  Segment Sections...
   00     .rom .payload .reset .id 
   01     

are IDENTICAL. So I guess it's something in how things are compiled? I am 
stumped at present.

ron



From rminnich at lanl.gov  Mon Jul 21 16:17:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 16:17:01 2003
Subject: silly ld question
In-Reply-To: <Pine.LNX.4.44.0307211353280.2915-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.44.0307211429520.2915-100000@maxroach.lanl.gov>

On Mon, 21 Jul 2003, ron minnich wrote:

> 
> anybody know why ld would give you something like this:
> 
> bash-2.05b$ readelf -l linuxbios
> 
> Elf file type is EXEC (Executable file)
> Entry point 0xffff0004
> There are 3 program headers, starting at offset 52
> 
> Program Headers:
>   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
>   LOAD           0x001000 0xffff0000 0xffff0000 0x117d0 0x117d0 RWE 0x1000
>   LOAD           0x012fd8 0xffffffd8 0xffffffd8 0x00028 0x00028 RWE 0x1000
>   LOAD           0x013ff0 0xfffffff0 0xfffffff0 0x00000 0x00000 RW  0x1000
> 
>  Section to Segment mapping:
>   Segment Sections...
>    00     .rom .payload .reset .id 
>    01     .reset .id 
>    02     

It was staring me in the face ....

the size of segment zero is too large. 

simple!

ron



From YhLu at tyan.com  Mon Jul 21 17:19:00 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 21 17:19:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302DD14DC@TYANWEB>

Eric,

I can build the linuxbios. But it is too large and it is around 60k, and
tg3.zelf is about 22k, and tg3--ide_disk.zelf is about 24k, then the sum is
above 65k.So I can not build the images.

The Ram conf costs 20k ???

Any advise.

Regards

Yinghai Lu

-----????-----
???: YhLu 
????: 2003?7?21? 10:31
???: 'ebiederman at lnxi.com'
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

Eric,

Thanks info about ROMCC option about -mcpu=k8. I will try and make the RAM
can be configurable.

My CPU is C0, In Opteron We may need to manipulate the MSR to enable the
apic.

Regards

Yinghai Lu


YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> My boss has said that I can release the source code to you.
> 
> Please find out the patch I made. Make the diff to today's tree.
> 
> I didn't test RON new script and still use the old scripts tools.
> 
> I strip out the LSI scsi support, because I don't know if there is any
> license problem, and I have referred to their documents and may need put
> their FW in the ROM.

Ah, an interesting problem.
 
> It's greater you add ops->enable function that make it easy to handle
> special device. To some device if it is not gotten magic code, it will not
> get the resource allocate to it. Before that I have to do it in init
> function and re-allocate the resource to it again. 

Welcome.

> Please refer to my old amd8131_ioapic.c in southbridge/amd8111. 

> Also you init the io_base, upper16 reg, otherwise the device in PCIX
> will not got io port allocated to them,  and will not work. 

Sorry I don't quite parse that sentence.

> I have tested Stefan's the code about coherent_ht.c, and add some hardcode
> to it.
> coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode
one.
> coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones.

Interesting looking at this code are you working with C0 stepping Opterons?
I have the stock B3 and am having fun getting the memory resets in all of
the proper
places.
 
> raminit.c and raminit.1.c are till the hardcode one, and I have tried to
use
> the configurable one, but auto.c can not be compiled, it is too big and
used
> up REG?

Looking.  It is your romcc options.  By default romcc will not use mmx
or sse registers unless you tell it that you have them.  I have been
doing this with -mcpu=k8.  The register pressure is much less when you
have 24 registers to work with instead of just 8.

> The old one has been renamed to raminit.o.c. 
> 
> To start other cpus, in auto.c  We must enable apic and make sure all
> apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu
> function.

Yep, an interesting way of doing it.  
 
> Again, thank you all to answer my questions to help Tyan s2880 work with
> LinuxBIOS.

Ron, Stefan.  Could one of you help with merging Yinghai's code?  I
might have time, but I don't think I will manage it before I leave
for OLS on Tuesday.

Eric


From rminnich at lanl.gov  Mon Jul 21 17:32:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 17:32:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <3174569B9743D511922F00A0C943142302DD14DC@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307211539180.2915-100000@maxroach.lanl.gov>

On Mon, 21 Jul 2003, YhLu wrote:

> I can build the linuxbios. But it is too large and it is around 60k, and
> tg3.zelf is about 22k, and tg3--ide_disk.zelf is about 24k, then the sum is
> above 65k.So I can not build the images.

I now routinely set my linuxbios size for 64K with payload size of 32k. 

romcc is WONDERFUL but it does grow things a bit.

ron



From YhLu at tyan.com  Mon Jul 21 17:35:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 21 17:35:01 2003
Subject: =?gb2312?B?tPC4tDogSzggKyAyLjQuMjEgKyBUeWFuIFMyODgw?=
Message-ID: <3174569B9743D511922F00A0C943142302DD14DF@TYANWEB>

Ron,

So fallback image will be 96K?

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?7?21? 14:45
???: YhLu
??: ebiederman at lnxi.com; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

On Mon, 21 Jul 2003, YhLu wrote:

> I can build the linuxbios. But it is too large and it is around 60k, and
> tg3.zelf is about 22k, and tg3--ide_disk.zelf is about 24k, then the sum
is
> above 65k.So I can not build the images.

I now routinely set my linuxbios size for 64K with payload size of 32k. 

romcc is WONDERFUL but it does grow things a bit.

ron


From rminnich at lanl.gov  Mon Jul 21 17:36:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 17:36:00 2003
Subject: =?gb2312?B?tPC4tDogSzggKyAyLjQuMjEgKyBUeWFuIFMyODgw?=
In-Reply-To: <3174569B9743D511922F00A0C943142302DD14DF@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307211548520.2915-100000@maxroach.lanl.gov>

On Mon, 21 Jul 2003, YhLu wrote:

> So fallback image will be 96K?

that's how I'm doing it. With a 1 Mbyte flash I don't worry much.

ron



From YhLu at tyan.com  Mon Jul 21 17:48:00 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 21 17:48:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302DD14E2@TYANWEB>

Ron,

Before fallback is 64k, I make normal image into (512-64)k, and fallback
image into 64k, and then cat them into one 512k. 
Actually the normal is quite loose with a lot of zeros, and the payload is
about 20k. 
So I need to change to Config in the mainboard dir to make sure normal image
has 512-96k. or that's to say change several 65536 to 96*1024??

It that right?

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?7?21? 14:49
???: YhLu
??: ebiederman at lnxi.com; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: ??: K8 + 2.4.21 + Tyan S2880

On Mon, 21 Jul 2003, YhLu wrote:

> So fallback image will be 96K?

that's how I'm doing it. With a 1 Mbyte flash I don't worry much.

ron


From ebiederman at lnxi.com  Mon Jul 21 17:49:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul 21 17:49:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <Pine.LNX.4.44.0307211539180.2915-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307211539180.2915-100000@maxroach.lanl.gov>
Message-ID: <m37k6bedwi.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On Mon, 21 Jul 2003, YhLu wrote:
> 
> > I can build the linuxbios. But it is too large and it is around 60k, and
> > tg3.zelf is about 22k, and tg3--ide_disk.zelf is about 24k, then the sum is
> > above 65k.So I can not build the images.
> 
> I now routinely set my linuxbios size for 64K with payload size of 32k. 
> 
> romcc is WONDERFUL but it does grow things a bit.

Next time I get to it I intend to start honoring the inline keyword.
The problem is that it inlines everything and creates code bloat.

So far it is working well enough and there are other priorities that I
have not come back to it.  It is my goal that before the 2.0 release
I can fit everything back into 64K for fallback again.  It is not
critical now but it is a warning sign of troubles ahead.

Eric



From rminnich at lanl.gov  Mon Jul 21 17:51:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 17:51:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <m37k6bedwi.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307211603190.2915-100000@maxroach.lanl.gov>

On 21 Jul 2003, Eric W. Biederman wrote:

> Next time I get to it I intend to start honoring the inline keyword.
> The problem is that it inlines everything and creates code bloat.

hmm, I'll be wanting to see how you solve the call stack problem :-)

> So far it is working well enough and there are other priorities that I
> have not come back to it.  It is my goal that before the 2.0 release
> I can fit everything back into 64K for fallback again.  It is not
> critical now but it is a warning sign of troubles ahead.

Personally, for now, I think it's fine.

ron



From ebiederman at lnxi.com  Mon Jul 21 18:06:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul 21 18:06:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <Pine.LNX.4.44.0307211603190.2915-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307211603190.2915-100000@maxroach.lanl.gov>
Message-ID: <m3u19fa5do.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On 21 Jul 2003, Eric W. Biederman wrote:
> 
> > Next time I get to it I intend to start honoring the inline keyword.
> > The problem is that it inlines everything and creates code bloat.
> 
> hmm, I'll be wanting to see how you solve the call stack problem :-)

Well routines that are only called once will still get inlined.

And with 24 registers I have a lot more freedom, than with just 8.

Historically Fortran did not have a call stack and it made procedure
and function calls just fine.  The same techniques with registers instead
of hard coded memory locations should work fine.

> > So far it is working well enough and there are other priorities that I
> > have not come back to it.  It is my goal that before the 2.0 release
> > I can fit everything back into 64K for fallback again.  It is not
> > critical now but it is a warning sign of troubles ahead.
> 
> Personally, for now, I think it's fine.

You haven't had your debug code fail to compile because linuxbios goes
over the 64K limit yet either.

Eric



From rminnich at lanl.gov  Mon Jul 21 18:18:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 18:18:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <m3u19fa5do.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307211631000.2915-100000@maxroach.lanl.gov>

On 21 Jul 2003, Eric W. Biederman wrote:

> You haven't had your debug code fail to compile because linuxbios goes
> over the 64K limit yet either.

I just did :-)

ron



From gwatson at lanl.gov  Mon Jul 21 18:41:01 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Mon Jul 21 18:41:01 2003
Subject: Please do not fork.
In-Reply-To: <m34r1fedir.fsf@maxwell.lnxi.com>
References: <Pine.LNX.4.44.0307211547440.2915-100000@maxroach.lanl.gov>
 <m34r1fedir.fsf@maxwell.lnxi.com>
Message-ID: <p06001a02bb421972b449@[128.165.250.184]>

At 4:11 PM -0600 21/7/03, Eric W. Biederman wrote:
>ron minnich <rminnich at lanl.gov> writes:
>
>>  On Mon, 21 Jul 2003, Stefan Reinauer wrote:
>>
>>  we're not going to fork.
>>
>>  That was more of a warning about what could happen. We have lots of
>>  committers out there and more are going to join. We may not always agree
>>  on how things are done, and we must not get into the habit of ripping each
>>  other's code out -- that way lies madness.
>
>There are some major design decisions coming before we freeze the 2.0 core,
>and this is just a warning that we need to be looking at these things
>closely, and that there are some strong opinions out there.  I never
>had any intention of forking.
>
>The target is to have a hardware independent hardwaremain.c
>
>We have called a cease fire for a until I get back with Ron and Greg promising
>to look at what I have done with the device stuff.
>
>If a enumerate_static_devices can be written that converts from the chip tree
>to the device tree and we get everyone working with and familiar with
>both pieces of the code we should be able to have some more rational
>discussion about what needs to happen.
>
>Conversations beyond this need to start hitting the list.
>
>Eric

The issue for me is that I need to have static initialization working 
before I can continue, so my intention is build something that will 
hopefully be acceptable to everyone. I can probably merge the chip 
and device structures that gives me a way forward without replicating 
what Eric is doing. However a single call to 
enumerate_static_devices, particularly at the current location, is 
NOT acceptable to me.

Here's my suggestion to move forward:

1. I need to be able to enable/configure static devices at specific 
points in hardwaremain, particularly on entry,  after console_init 
and prior to pci enumeration. I suggest a routine called 
device_configure()  that is passed the root of the device tree and a 
pass flag:

void device_configure(struct device *, enum dev_pass)

enum dev_pass {
	DEV_PASS_PRE_CONSOLE,
	DEV_PASS_PRE_PCI,
	DEV_PASS_ENUMERATE,
	DEV_PASS_CONFIGURE,
	DEV_PASS_ENABLE,
	DEV_PASS_INITIALIZE
};

Calls to device_configure() with the appropriate flag will be 
inserted in the appropriate locations in hardwaremain. More 
flags/calls call be added if necessary. Calls to dev_enumerate(), 
dev_configure(), etc. to probe and configure dynamic bus devices will 
be replaced with calls to device_configure() with the appropriate 
flag. Dynamic devices will be added to the device tree as appropriate.

2. New fields added to struct device, including a 'static' flag that 
is set for static devices, and something analogous to the chip 
structure for static device info.

3. Continue use of the chip.h files in configuration directories 
(although the name could be changed to device.h) and the 'register' 
configuration directive.

4. Removal of all device specific calls from hardwaremain, such as 
'init_timer()' into static initialization files using (4) above.

5. The configuration process will build a static device tree that 
will be called device_{target}.c in the target build directory and 
linked with the linuxbios image.

My intention is to start coding this tomorrow, so if anyone has any 
major objections/suggestions, please let me know asap.

Regards,

Greg




From ebiederman at lnxi.com  Mon Jul 21 19:28:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul 21 19:28:00 2003
Subject: Please do not fork.
In-Reply-To: <p06001a02bb421972b449@[128.165.250.184]>
References: <Pine.LNX.4.44.0307211547440.2915-100000@maxroach.lanl.gov>
	<m34r1fedir.fsf@maxwell.lnxi.com>
	<p06001a02bb421972b449@[128.165.250.184]>
Message-ID: <m3k7ab78h6.fsf@maxwell.lnxi.com>

Greg Watson <gwatson at lanl.gov> writes:

> 
> The issue for me is that I need to have static initialization working before I
> can continue, so my intention is build something that will hopefully be
> acceptable to everyone. I can probably merge the chip and device structures that
> 
> gives me a way forward without replicating what Eric is doing. However a single
> call to enumerate_static_devices, particularly at the current location, is NOT
> acceptable to me.

That is fine.  What I have right now in hardwaremain is just a first pass not 
a final solution to this problem.
 
> Here's my suggestion to move forward:
> 
> 1. I need to be able to enable/configure static devices at specific points in
> hardwaremain, particularly on entry,  after console_init and prior to pci
> enumeration. I suggest a routine called device_configure()  that is passed the
> root of the device tree and a pass flag:
> 
> void device_configure(struct device *, enum dev_pass)
> 
> enum dev_pass {
> 	DEV_PASS_PRE_CONSOLE,
> 	DEV_PASS_PRE_PCI,
> 	DEV_PASS_ENUMERATE,
> 	DEV_PASS_CONFIGURE,
> 	DEV_PASS_ENABLE,
> 	DEV_PASS_INITIALIZE
> };
> 
> Calls to device_configure() with the appropriate flag will be inserted in the
> appropriate locations in hardwaremain. More flags/calls call be added if
> necessary. Calls to dev_enumerate(), dev_configure(), etc. to probe and
> configure dynamic bus devices will be replaced with calls to device_configure()
> with the appropriate flag. Dynamic devices will be added to the device tree as
> appropriate.

I have nits to pick with a single device_configure().  After we have something
working I will start picking them.

> 2. New fields added to struct device, including a 'static' flag that is set for
> static devices, and something analogous to the chip structure for static device
> info.

Reasonable.
 
> 3. Continue use of the chip.h files in configuration directories (although the
> name could be changed to device.h) and the 'register' configuration directive.

I don't have a problem with that.
 
> 4. Removal of all device specific calls from hardwaremain, such as
> 'init_timer()' into static initialization files using (4) above.

OK.  I think.

In general timer services are a generic part of LinuxBIOS and just like
the console we may need an init routine.  We have avoided it many times
in the past by having a static variable and having the timer code magically
do something the very first time it is called.

When I built code that could be compiled with romcc I discovered that idiom
would not always work.
 
> 5. The configuration process will build a static device tree that will be called
> 
> device_{target}.c in the target build directory and linked with the linuxbios
> image.
> 
> My intention is to start coding this tomorrow, so if anyone has any major
> objections/suggestions, please let me know asap.

Long term I would like to see if we can get the cpus into this structure as
well.  But expressing the dependencies is an interesting process.

I plan on reviewing what you have when I get back from OLS.

Eric



From YhLu at tyan.com  Mon Jul 21 20:07:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 21 20:07:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302DD1517@TYANWEB>

Eric,

In the auto.c, if I enable : sdram_initialize(&cpu1), the linuxbios need
another 20k. What happened? Only add one line and the same function has been
called ???

Regards

Yinghai Lu

-----????-----
???: YhLu 
????: 2003?7?21? 14:58
???: 'ron minnich'
??: ebiederman at lnxi.com; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

Ron,

Before fallback is 64k, I make normal image into (512-64)k, and fallback
image into 64k, and then cat them into one 512k. 
Actually the normal is quite loose with a lot of zeros, and the payload is
about 20k. 
So I need to change to Config in the mainboard dir to make sure normal image
has 512-96k. or that's to say change several 65536 to 96*1024??

It that right?

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?7?21? 14:49
???: YhLu
??: ebiederman at lnxi.com; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: ??: K8 + 2.4.21 + Tyan S2880

On Mon, 21 Jul 2003, YhLu wrote:

> So fallback image will be 96K?

that's how I'm doing it. With a 1 Mbyte flash I don't worry much.

ron


From ebiederman at lnxi.com  Mon Jul 21 21:19:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul 21 21:19:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <3174569B9743D511922F00A0C943142302DD1517@TYANWEB>
References: <3174569B9743D511922F00A0C943142302DD1517@TYANWEB>
Message-ID: <m365lv4a75.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> In the auto.c, if I enable : sdram_initialize(&cpu1), the linuxbios need
> another 20k. What happened? Only add one line and the same function has been
> called ???

All functions are inline and the set of functions called is large.
At least I believe that is the issue.

And good luck catching up....

While I am away you get a chance.  My latest code has changed sdram_initialize
one more time to take a cpu count parameter.

And perversely this should help because if a function is called in a loop
it will only be inlined once instead of multiple times.

Eric



From ebiederman at lnxi.com  Mon Jul 21 21:19:33 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul 21 21:19:33 2003
Subject: See you later...
Message-ID: <m31xwj4a5m.fsf@maxwell.lnxi.com>

I will be at the Ottowa Linux Symposium or travelling to and from there
for the rest of the week.

Eric



From rminnich at lanl.gov  Mon Jul 21 23:24:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 21 23:24:01 2003
Subject: New device layout, including static and dynamic initializers
In-Reply-To: <m3k7ab78h6.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307212133390.13414-100000@maxroach.lanl.gov>

On 21 Jul 2003, Eric W. Biederman wrote:

> I have nits to pick with a single device_configure().  After we have
> something working I will start picking them.

do you mean a single call or a single function? The plan is multiple calls 
to that function. 

> In general timer services are a generic part of LinuxBIOS and just like
> the console we may need an init routine.  We have avoided it many times
> in the past by having a static variable and having the timer code magically
> do something the very first time it is called.

Right. But if the timer is a device in the static tree, and it has a 
device_configure function, that will get called at some point with a PASS 
parameter which will tell it to turn on. 

Greg, you need to fill in the blanks a bit more about the PASS_ stuff.

Possibly show your hardwaremain()

> Long term I would like to see if we can get the cpus into this structure as
> well.  But expressing the dependencies is an interesting process.

The CPUs are in the static structure almost, as a class of CPU. I assume 
you want a static struct for each one. Very doable. But it makes more 
sense to make the instances of CPUs dynamic, and continue with the class 
as a static initializer.

ron



From ollie at sis.com.tw  Mon Jul 21 23:42:00 2003
From: ollie at sis.com.tw (ollie lho)
Date: Mon Jul 21 23:42:00 2003
Subject: New device layout, including static and dynamic initializers
In-Reply-To: <Pine.LNX.4.44.0307212133390.13414-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307212133390.13414-100000@maxroach.lanl.gov>
Message-ID: <1058845167.3345.103.camel@ollie>

On Tue, 2003-07-22 at 11:37, ron minnich wrote:
> On 21 Jul 2003, Eric W. Biederman wrote:
> 
> > I have nits to pick with a single device_configure().  After we have
> > something working I will start picking them.
> 
> do you mean a single call or a single function? The plan is multiple calls 
> to that function. 
> 

Why do you want to call a SINGLE function in different places with 
different enum value ? Is there any disadvantage to make each call
into it own function ?

-- 
ollie lho <ollie at sis.com.tw>



From aip at cwlinux.com  Mon Jul 21 23:51:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jul 21 23:51:01 2003
Subject: EPIA-M DDR ram init progress
In-Reply-To: <200307211849.h6LInQ8Q013431@xdr.com>; from Dave Ashley on Mon, Jul 21, 2003 at 11:49:26AM -0700
References: <200307211849.h6LInQ8Q013431@xdr.com>
Message-ID: <20030722120421.A20941@mail.cwlinux.com>

Hi Dave,

> As a recap I was trying to get 2 specific DDR modules working with the
> epia-m. One has ICT chips and the other has GET chips. The ICT module works
> with the hardcoded dram configuration, but the GET module doesn't.
> ICT = 1 bank 128M colbits = 10
> GET = 2 banks 64M colbits = 9
Same here, but if I set 0x58 to 0xc0, both works.

> I had tried hardcoding the dram settings to the ones award bios uses for the
> GET module, but it wasn't working. I figured out what the problem was.
> I need to do the ddr setup for each bank on the ddr module, not just the
> first one. The hardcoded settings correspond to a ddr with just a single bank.
That's right because EPIA-M has only 1 ddr bank.  If some custom has more
that 1 bank, I can check it.

> SPD contents is very easy to access. The epia-m code is including
> src/northbridge/via/vt8623/raminit.inc
> to initialize ram. I found problems with this, the jedec ddr init spec
> sequence calls for reads of the ddr memory, this source actually does some
> writes.
Thanks for the catch.  It has been fixed.  The funny thing is writes work,
too!!!

> I'm wondering what the preferred way of implementing spd for epia-m would
> be. Should instead of including src/northbridge/via/vt8623/raminit.inc I put
> that code in with the epia-m code, mix it with the smbus SPD read code,
> and leave the result in the epia-m tree? Or should I modify the
> src/northbridge/via/vt8623/raminit.inc file directly? I don't see how that
> can work since the SMBUS/SPD is accessed with the vt8235 registers, but the
> DDR dram control registers are part of the northbridge.
SMBUS/SPD should be in southbridge like other platforms.  Then, mainboard's
Config can include those code such that raminit.inc can call later.  E7500
is a very nice reference.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Tue Jul 22 00:16:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 00:16:01 2003
Subject: New device layout, including static and dynamic initializers
In-Reply-To: <1058845167.3345.103.camel@ollie>
Message-ID: <Pine.LNX.4.44.0307212205340.13800-100000@maxroach.lanl.gov>

On 22 Jul 2003, ollie lho wrote:

> Why do you want to call a SINGLE function in different places with 
> different enum value ? Is there any disadvantage to make each call
> into it own function ?


OK, to elaborate.

In superio code from 1.0, we had this:
struct superio_control {
  void (*pre_pci_init)(struct superio *s);
  void (*init)(struct superio *s);
  void (*finishup)(struct superio *s);
  unsigned int defaultport;     /* the defaultport. Can be overridden
                                 * by commands in config
                                 */
  // This is the print name for debugging
  char *name;
};

The names pre_pci_init, init, and finishup were an implicit definition of 
those functions. They could be filled in, or NULL, as in:

struct superio_control superio_winbond_w83977ef_control = {
        pre_pci_init:   (void *) 0,
        init:           setup_devices, 
        finishup:       (void *) 0,
        defaultport:    PNPADDR,
        name:           "WinBond w83977tf"
};


These three functions roughly correspond to "passes" in hardwaremain, and 
are intended to be called as hardwaremain proceeds through platform 
configuration. 

In other words, you had some degree of control of when a device's control 
functions were called. This has been very important -- some of these 
devices need code before PCI enumeration, for example. 

The problem is, are the three functions defined sufficient? how many 
should there be? What if hardwaremain changes and we add new "passes", do 
we have to add some new set of functions? If we add new passes, how do we 
go about fixing all the parts that we have written code for? 

Also, we wanted to generalize beyond just superios to all devices. 

Finally, the PPC has very different rules than standard PCs, and we're 
trying to come up with a non-Pentium-centric way of doing things. 

Now, internally, the code that walked the superio tree was ALWAYS called 
with a 'pass', as in:

void
handle_superio(int pass, struct superio *all_superio[], int nsuperio)
{
.
.
.
               // need to have both pre_pci_init and devfn defined.
                if (s->super->pre_pci_init && (pass == 0)) {
                        printk_debug("  Call pre_pci_init\n");
                        s->super->pre_pci_init(s);
                } else if (s->super->init && (pass == 1)) {
                        printk_debug("  Call init\n");
                        s->super->init(s);
                } else if (s->super->finishup && (pass == 2)) {
                        printk_debug("  Call finishup\n");
                        s->super->finishup(s);
                }

.
.
.
}

This code has been this way for two or more years. 

So all we're really doing is creating ONE interface function to the chips, 
not three:

/* there is one of these for each TYPE of chip */
struct chip_control {
  void (*enable)(struct chip *, enum chip_pass);
  char *path;     /* the default path. Can be overridden
                   * by commands in config
                   */
  // This is the print name for debugging
  char *name;
};

and that code will now be called with a pass. We expect that in this 
enable function we'll see things like this:

static void enable(struct chip *, enum chip_pass) {
	struct superio *s = chip->chip_info;
	switch (chip_pass) {
	default:
		break;
	case        DEV_PASS_PRE_CONSOLE: 
		/* make sure serial is enabled; this chip is weird */
		if (s->com1.enable)
			serial_enable(&s->com1);
		break;
        DEV_PASS_PRE_PCI: 
		/* if the ide_enable static initializer is set, 
		 * set the IDE controller so it is visible on PCI */
		if (s->ide_enable)
			ide_on();
		break;
	}

}

In other words, most passes don't matter, but if some passes do, then the 
code can manage it. We'll thus have a standard "template" for all 
resources on the motherboard, and a standard way to enable resources 
during different passes (phases, maybe we should call it?) of 
hardwaremain(). 

hardwaremain changes a bit too. 

For instance, this:
        post_code(0x80);
        /* displayinit MUST PRECEDE ALL PRINTK! */
        console_init();

becomes this:
	device_configure(chip_root, DEV_PASS_PRE_CONSOLE);
        post_code(0x80);
        /* displayinit MUST PRECEDE ALL PRINTK! */
        console_init();

and so on. device_configure is called at different phases in hardwaremain, 
as the platform becomes more configured. device_configure is capable for 
walking the device tree, and calling functions as needed. 

That's the basic idea, anyway. It is motivated by the goal of replacing 
this type of code:

        /* PCI Interface */
        .byte   0x80,   0x72    #
        .byte   0x81,   0x07    #
        .byte   0x82,   0xFF    #

with C code that people can deal with. There was a lot of confusion on how 
to enable/disable built-in-ethernet on the SiS 950, for example, and we're 
trying to reduce confusion.

Comments welcome.


ron







From rminnich at lanl.gov  Tue Jul 22 00:18:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 00:18:00 2003
Subject: EPIA-M DDR ram init progress
In-Reply-To: <20030722120421.A20941@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.44.0307212230000.13800-100000@maxroach.lanl.gov>

On Tue, 22 Jul 2003, Andrew Ip wrote:

> > SPD contents is very easy to access. The epia-m code is including
> > src/northbridge/via/vt8623/raminit.inc
> > to initialize ram. I found problems with this, the jedec ddr init spec
> > sequence calls for reads of the ddr memory, this source actually does some
> > writes.
> Thanks for the catch.  It has been fixed.  The funny thing is writes work,
> too!!!

interesting. The Intel 430TX part specified reads, but would hang unless 
you did writes. 

ron



From ebiederman at lnxi.com  Tue Jul 22 01:35:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jul 22 01:35:01 2003
Subject: New device layout, including static and dynamic initializers
In-Reply-To: <Pine.LNX.4.44.0307212205340.13800-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307212205340.13800-100000@maxroach.lanl.gov>
Message-ID: <m3ptk3f6v1.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On 22 Jul 2003, ollie lho wrote:
> 
> > Why do you want to call a SINGLE function in different places with 
> > different enum value ? Is there any disadvantage to make each call
> > into it own function ?

I hereby reserve judgment until I see Greg's implementation.

I think I am going to complain but I think there is a lot we
can work with as well.

> The problem is, are the three functions defined sufficient? how many 
> should there be? What if hardwaremain changes and we add new "passes", do 
> we have to add some new set of functions? If we add new passes, how do we 
> go about fixing all the parts that we have written code for? 

It is trivial to simply add another function to a table of
function pointers if you have something appropriate.

Experience tells me specific functions will do a better job
than a pass argument.  But it in the big picture it doesn't much
matter.  It is which hooks you have that matter.  

Adding entry points is not a problem.  I added the enable function
to the device side of things and everything that didn't care
just worked.

As far as I am concerned the real debate begins when I get
back and can sink my teeth into Greg's code.

For the rest who haven't looked so closely.  
Greg and Ron are taking the existing superio model and generalizing it.

I have taken the existing pci device model and generalized it.

And now we have the design review/fight/slug out as we meet in
the middle.

I suspect the union of the two sets of functions from struct
device_operations and from the superio side is two high.   But the way
forward is to get that union and have everyone understand the pieces
backwards and forwards.

Eric



From ollie at sis.com.tw  Tue Jul 22 02:00:01 2003
From: ollie at sis.com.tw (ollie lho)
Date: Tue Jul 22 02:00:01 2003
Subject: New device layout, including static and dynamic initializers
In-Reply-To: <m3ptk3f6v1.fsf@maxwell.lnxi.com>
References: <Pine.LNX.4.44.0307212205340.13800-100000@maxroach.lanl.gov>
	 <m3ptk3f6v1.fsf@maxwell.lnxi.com>
Message-ID: <1058853472.3345.111.camel@ollie>

On Tue, 2003-07-22 at 13:49, Eric W. Biederman wrote:
> 
> For the rest who haven't looked so closely.  
> Greg and Ron are taking the existing superio model and generalizing it.
> 
> I have taken the existing pci device model and generalized it.
> 
> And now we have the design review/fight/slug out as we meet in
> the middle.
> 
> I suspect the union of the two sets of functions from struct
> device_operations and from the superio side is two high.   But the way
> forward is to get that union and have everyone understand the pieces
> backwards and forwards.
> 

I still don't see the point of the dispute. In the PCI model, you
make the operations (functions) a separated entity and in the superio
model, the operations are embedded in the data structure. Is there
any fundamental or design conflict between these two ?

-- 
ollie lho <ollie at sis.com.tw>



From ebiederman at lnxi.com  Tue Jul 22 02:48:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jul 22 02:48:00 2003
Subject: New device layout, including static and dynamic initializers
In-Reply-To: <1058853472.3345.111.camel@ollie>
References: <Pine.LNX.4.44.0307212205340.13800-100000@maxroach.lanl.gov>
	<m3ptk3f6v1.fsf@maxwell.lnxi.com> <1058853472.3345.111.camel@ollie>
Message-ID: <m3n0f7qc0l.fsf@maxwell.lnxi.com>

ollie lho <ollie at sis.com.tw> writes:

> On Tue, 2003-07-22 at 13:49, Eric W. Biederman wrote:
> > 
> > For the rest who haven't looked so closely.  
> > Greg and Ron are taking the existing superio model and generalizing it.
> > 
> > I have taken the existing pci device model and generalized it.
> > 
> > And now we have the design review/fight/slug out as we meet in
> > the middle.
> > 
> > I suspect the union of the two sets of functions from struct
> > device_operations and from the superio side is two high.   But the way
> > forward is to get that union and have everyone understand the pieces
> > backwards and forwards.
> > 
> 
> I still don't see the point of the dispute. In the PCI model, you
> make the operations (functions) a separated entity and in the superio
> model, the operations are embedded in the data structure. Is there
> any fundamental or design conflict between these two ?

Fundamentally no.  And things should work out ok.  

The was a point earlier today where things were not meeting in the
middle as they should.  So the comprehension or the communication that
needed to be there, at least appeared absent.

It was especially aggravated by the fact, that I am gone the rest
of the week, and the situation could have continued to the point
where it would be nasty to put the pieces back together.

My impression of the flow of development is that I asked for
some static devices structures for the pci devices, since Ron
and Greg are reworking the configuration files.  And what
I got was the a generalized version of the superio complete with
methods.

The ideas have been discussed in the past on this list and I thought
I had communicated clearly.  Given that my vision and Ron and Greg's
have not yet meshed.  It is clear that the communicate was not
as clear as I thought.  The only way I see to make this clear is for
people to start using the code.  And putting the two halves together.

Then I can give constructive criticism, on the small details.

For me this is sort of like when I was pushing the ELF file format
for the payload.  Until it happened and I had the code in place
people just didn't see it.

>From working with it, Stefan, Yhlu, and I seem to have a pretty good
grasp of how to make the dynamic side of it work, at least for
the easy things.  Ron and Greg seem to have a good feel for the
dynamic side.  But we haven't merged the two so there is no good
global feel for things yet. 

So until the static and the dynamic pieces are fit together 
feel that it is ineffective and inappropriate to talk about little
details of the design.  I will talk about what needs to happen to glue
the two pieces together (An appropriate enumerate_static_devices
method). 

So what you see is much more pent of design discussion and frustration 
than actual conflict.

The goals of the design are lofty.
- A universal hardwaremain.c that can be used on multiple
  architectures.
- A device architecture that handles both static and dynamic devices.
- Clear requirements from the methods so things fit together cleanly
  and intuitively instead of a weird mish mash that just happens
  to work.

We have a pretty good position on the basic architecture, a device
tree.  But refining it from there in a practical matter is a problem.

Adding to the fun is the fact that there are customers that have to
use the code and don't care how brilliant the design is.  They want
something that works today.  So there has been a lot of work put in on
the Opteron side lately just to make things work.  Which painfully
lengthens the amount of time disconnects in the design exist.

Eric



From R.Marek at sh.cvut.cz  Tue Jul 22 03:26:01 2003
From: R.Marek at sh.cvut.cz (Rudolf Marek)
Date: Tue Jul 22 03:26:01 2003
Subject: SPD reading with asus A7S333 - SiS745
In-Reply-To: <20030721184800.24883.76842.Mailman@nwn.definitive.org>
Message-ID: <Pine.LNX.3.96.1030722092751.19369A-100000@desitka.sh.cvut.cz>

Hello,

Someone earlier got similar problem. Asus is muxing the
devices on the SMBUS. I'm developing drivers for lm_sensors project.
(W83785 driver) I got my smbus working (same as SiS645) There are some 
 devices on the bus - ATXP2, W83785 and some Asus ASIC.
But no SPD EEPROM, nor PLL. I'm curious about the content of my SPD.

Someone here pointed out that it can be enabled by some of GPO bits.

I got 2 problems. 

1) I dont have a datasheet for SiS745 (I ot only for SiS630)
2) I dont know which GPO to enable.

Please would someone be so king and give me some advice?

I got disassembled BIOS for reference, but I even dont know in wich PCI
dev should I look for GPO.

You will need this information anyway if you plan tu support this
motherboard :) (it will be very nice)

Regards

	Rudolf Marek



 






From rminnich at lanl.gov  Tue Jul 22 10:03:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 10:03:01 2003
Subject: New device layout, including static and dynamic initializers
In-Reply-To: <1058853472.3345.111.camel@ollie>
Message-ID: <Pine.LNX.4.44.0307220814360.18687-100000@maxroach.lanl.gov>

On 22 Jul 2003, ollie lho wrote:

> I still don't see the point of the dispute. 

I don't think there is a dispute, just uncertainty about how to hook them 
up. 

Also, we can in fact have lots of different entry points in the struct, 
but there is disagreement about having one function with a pass parameter 
or 15 functions. It's really a matter of taste. 

ron




From rminnich at lanl.gov  Tue Jul 22 10:07:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 10:07:00 2003
Subject: SPD reading with asus A7S333 - SiS745
In-Reply-To: <Pine.LNX.3.96.1030722092751.19369A-100000@desitka.sh.cvut.cz>
Message-ID: <Pine.LNX.4.44.0307220819150.18687-100000@maxroach.lanl.gov>

to figure out which GPIO to do, you have to program each GPIO in turn and 
then read SPD, and see when it changes. Painful but it doesn't take too 
long.

ron



From rminnich at lanl.gov  Tue Jul 22 10:07:08 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 10:07:08 2003
Subject: configurable onboard components
In-Reply-To: <20030722082440.GA1929@suse.de>
Message-ID: <Pine.LNX.4.44.0307220819570.18687-100000@maxroach.lanl.gov>

On Tue, 22 Jul 2003, Stefan Reinauer wrote:

> * you disabled onboard ethernet and ac97 in amd8111_lpc.c
>   can we make this somehow configurable? Is there a way to probe
>   whether these are actually wired through to some outputs?

hmm, could I have a better example of why we need that static device tree 
:-)

ron



From YhLu at tyan.com  Tue Jul 22 13:31:00 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Jul 22 13:31:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302DD1559@TYANWEB>

Eric,

It can be compiled with you new code. But it meet problems in Etherboot
stage.
In S2880 has two broadcom NIC port in 8131 bus B, and one amd 8111 built-in
nic, and even if I hide it in amd8111 init and Etherboot can find it and try
to enable it and can not find the PM cap so aborting, in the old linuxbios
code (before yesterday) ( with mem hard code), it will go to tickle on
Broadcom nic, but in the new code (yesterday check in) ( mem configurable),
it will go to MB restarting.???

How about arima broadcom nic position? 

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?7?21? 18:33
???: YhLu
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> In the auto.c, if I enable : sdram_initialize(&cpu1), the linuxbios need
> another 20k. What happened? Only add one line and the same function has
been
> called ???

All functions are inline and the set of functions called is large.
At least I believe that is the issue.

And good luck catching up....

While I am away you get a chance.  My latest code has changed
sdram_initialize
one more time to take a cpu count parameter.

And perversely this should help because if a function is called in a loop
it will only be inlined once instead of multiple times.

Eric


From root at hamburg.de  Tue Jul 22 13:47:00 2003
From: root at hamburg.de (Felix Kloeckner)
Date: Tue Jul 22 13:47:00 2003
Subject: fallbackimage, question
Message-ID: <20030722195634.A13123@synapse.pentanet>

hello,
i successfully ported the fallbackimage-principle for the
elitegroup p6stp-fl (sis630)but the problem is that it only
works with 64KB fallback-image (i took the calculations
from "supermicro/p4dpeg2/Config")

because i need more space for the payload i need a bigger
fallbackimage, but if i change the size of "FALLBACK_IMAGE_SIZE"
only the fallbackimage will boot, not the normalimage (each
time the normalimage should be jumped to the watchdogtimer
expires and resets the board, after that the fallbackimage
will boot again)


does anybody see what i made wrong? (below is a part of my config

- felix




size related stuff from my config
----------------------------------------------

option USE_FALLBACK_IMAGE=0
expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE

option ROM_SIZE=0x80000

#works only with exactly 0x10000, need more!   <---------
option FALLBACK_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=43520

expr ROM_SECTION_SIZE=(USE_FALLBACK_IMAGE * FALLBACK_IMAGE_SIZE) + (USE_NORMAL_IMAGE * (ROM_SIZE - FALLBACK_IMAGE_SIZE) )
expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE * (ROM_SIZE - FALLBACK_IMAGE_SIZE)) + (USE_NORMAL_IMAGE * 0)
expr ZKERNEL_START=(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
expr PAYLOAD_SIZE=ROM_SECTION_SIZE - ROM_IMAGE_SIZE
expr _ROMBASE=ZKERNEL_START + PAYLOAD_SIZE

#cache the upper 16M of the 4G address space
#or else the decompression would be so slow that
#the watchdogtimer resets the board even before
#decompression is done
option XIP_ROM_SIZE= 0x01000000
option XIP_ROM_BASE= 0xfe000000


From rminnich at lanl.gov  Tue Jul 22 20:35:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 20:35:01 2003
Subject: freebios2 mod to reset code. 
Message-ID: <Pine.LNX.4.44.0307221703070.21850-100000@maxroach.lanl.gov>

Now that we are using romcc, and all functions are inline, it is getting
increasingly painful to deal with linuxbios images smaller than 64k. This
problem happens as we need a 16-bit jump to the start of the linuxbios
code, which limits us to jumping to 0xffff0000. But if linuxbios is bigger 
than that, we need to be able to jmp to 0xfffe0000, which is not possible 
with the current setup. 

We can grow this if we do the following: 

make reset a rel jump to 0xfffffff0 - (sizeof entry16). Then put entry 16
right before 0xfffffff0. Entry16 code turns on 32-bit mode and then jumps
to the real start of the linuxbios image -- which can now be anywhere in
the flash image. I could use this now, as could others.

here is sample code which I am trying. It now assembles and inspection of 
the object reveals that it is certainly close to correct.

Here's where I wish I had a really good emulator for linux -- checking 
this out would be a whole lot easier.

The test reset16 code:

.section .reset
	.code16

.globl rgdtptr16
.globl reset_start
.type reset_start, @function

reset_start: 
	cli

	xorl	%eax, %eax
	movl	%eax, %cr3    /* Invalidate TLB*/
	invd
	movw	%cs, %ax
	shlw	$4, %ax
	movw	$gdtptr16_offset, %bx
	subw	%ax, %bx
	data32  lgdt %cs:(%bx)

	movl	%cr0, %eax
	andl	$0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
	orl	$0x60000001, %eax /* CD, NW, PE = 1 */
	movl	%eax, %cr0

	/* Now that we are in protected mode jump to a 32 bit code 
segment. */
	data32	ljmp	$ROM_CODE_SEG, $__protected_start

/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
 * at 0x18; these are Linux-compatible. 
 */

.align	4
.globl rgdtptr16
rgdtptr16:
	.word	gdt_end - gdt -1 /* compute the table limit */
	.long	gdt		 /* we know the offset */

.globl	reset_vector
.align 4
reset_vector:
	jmp reset_start

The net effect is this: 16-bit reset jmps to a very small startup code 
right before 0xfffffff0 that enables full 32-bit mode. We can then jmp 
anywhere we want -- to 0xfffe0000 for example -- which we can't do now. 
This will alleviate the problem of linuxbios images growing to > 64K which 
is a consequence of romcc right now. This will allow us to live with 
really big linuxbios images until romcc makes tighter code.

Comments?  Errors in the code? 

thanks

ron




From rminnich at lanl.gov  Tue Jul 22 21:14:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 21:14:00 2003
Subject: alternate startup idea. 
Message-ID: <Pine.LNX.4.44.0307221924180.21850-100000@maxroach.lanl.gov>

Well, my alternate startup idea works fine on the K8. Except ... looks 
like flash rom addressing is not enabled by default for anything but the 
0xffff0000 segment, which means while my idea works, it's useless: if I 
jump to the 0xfffe0000 segment, I'll be reading air, not the flash part. 

Darn it. I kind of wish that we could get the chipmakers to default to 
full addressing in the high part of the address space, i.e. when it 
decodes for the flash, it decodes from 0xfff00000 up, not 0xffff0000 up. 
Someday ...

Well, at least I have an interesting (I guess) proof-of-concept. Not sure 
where to take it, but I think I'll go ahead and put it aside. Sigh.

ron



From ijpraveen1 at yahoo.com  Tue Jul 22 22:03:01 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Tue Jul 22 22:03:01 2003
Subject: Loading OS from Flash ROM!
In-Reply-To: <Pine.LNX.4.44.0307210853240.2915-100000@maxroach.lanl.gov>
Message-ID: <20030723021613.23988.qmail@web41710.mail.yahoo.com>


Sorry mine is TE28F320C3TC70 (Intel) 32Mbit Flash memory. If I have to boot from Flash memory what part of linux bios should I concentrate? What changes has to be done?
 
Thanks.

 
ron minnich <rminnich at lanl.gov> wrote:
On Sun, 20 Jul 2003, John Praveen wrote:

> I can't get to this. This means that 4 MB Flash ROM cannot be
> used with SC1200? Or is it not supported in LinuxBIOS. Plz help me to
> understand these.

it means that you said "4 MB" which is a common mistake. If you send me 
the part # of flash I will bet it is actually 4Mbits (i.e. 4 Mb)

you can't put linux kernel in 4Mbits any more.

ron


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From rminnich at lanl.gov  Tue Jul 22 22:38:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 22:38:00 2003
Subject: Loading OS from Flash ROM!
In-Reply-To: <20030723021613.23988.qmail@web41710.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0307222051090.375-100000@maxroach.lanl.gov>

On Tue, 22 Jul 2003, John Praveen wrote:

> 
> Sorry mine is TE28F320C3TC70 (Intel) 32Mbit Flash memory. If I have to
> boot from Flash memory what part of linux bios should I concentrate?
> What changes has to be done?

NEAT!

removeable or soldered on?

ron



From rminnich at lanl.gov  Tue Jul 22 23:08:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 23:08:00 2003
Subject: K8 news
Message-ID: <Pine.LNX.4.44.0307222111560.956-100000@maxroach.lanl.gov>

For those just joining. 

Eric Biederman has a solid C compiler for x86 for no-memory situations.  
The amount of assembly code in LinuxBIOS shrinks day-by-day.  Stefan
Reinauer at Suse and Eric have been working on different parts of the K8
problem and have linuxbios up on K8 1, 2, and 4 CPU systems. YHLu of Tyan
has linuxbios up on the new K8 motherboard. Linuxbios also works now on
the Arima HDAMA.

Greg Watson and I have been upgrading the config tool. It is a substantial 
improvement. I am now easily able to track the tree and build with the new 
config tool only. The new tool is faster and produces more comprehensible 
makefiles. Perl expressions in makefiles are a thing of the past. The new 
tool is also much better for non-PC systems, e.g. PPC. 

I am also booting Linux directly out of FLASH using the 49LF080 1 Mbyte
parts.

I will be starting work on the NewISYS board soon.

AMD has provided support in many ways, including opening up the documents.
AMD should be credited for their longstanding support of LinuxBIOS on the
K8, going back to long before the K8 was officially released.

I think vendors such as AMD, LNXI, Suse, Tyan, Arima, and Newisys (I hope
I left no one else out) are to be commended for their support of LinuxBIOS
on this new CPU. This work represents a substantial financial commitment
on the part of these companies.

Thanks to you all.

ron



From rminnich at lanl.gov  Tue Jul 22 23:08:27 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 23:08:27 2003
Subject: SC1200-BLDT (fwd)
Message-ID: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov>

anybody?

ron

---------- Forwarded message ----------
Date: Wed, 23 Jul 2003 03:12:33 +0000
From: Devi Priya <ijpriya at hotmail.com>
To: rminnich at lanl.gov
Subject: SC1200-BLDT


Hello

        I have compiled the linuxbios for sc1200. I also have Dorado xpress 
loader. Can you plz tell how could I boot my linux OS from Flash into RAM 
using the BLDT from National? I assume the BLDT is for WindowsCE OS.

        I assume like this. I can have the (lilo) bootloader as the option 
ROM. So my BIOS program shall scan for the option ROMs. Is it correct?

_________________________________________________________________
It's all happening @ F1. Feel the thrill! 
http://server1.msn.co.in/sp03/formula2003/index.asp Race along right here!



From hansolofalcon at worldnet.att.net  Tue Jul 22 23:21:01 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Tue Jul 22 23:21:01 2003
Subject: SC1200-BLDT (fwd)
In-Reply-To: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov>
Message-ID: <000801c350cb$67bb09c0$0100a8c0@who5>

Hello from Gregg C Levine
Here's a suggestion. When people post questions like that, just ask
them, to restate the questions, in a different format. It always
works. Especially when I talk like that.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of ron minnich
> Sent: Tuesday, July 22, 2003 11:21 PM
> To: linuxbios at clustermatic.org
> Subject: SC1200-BLDT (fwd)
> 
> 
> anybody?
> 
> ron
> 
> ---------- Forwarded message ----------
> Date: Wed, 23 Jul 2003 03:12:33 +0000
> From: Devi Priya <ijpriya at hotmail.com>
> To: rminnich at lanl.gov
> Subject: SC1200-BLDT
> 
> 
> Hello
> 
>         I have compiled the linuxbios for sc1200. I also have Dorado
xpress
> loader. Can you plz tell how could I boot my linux OS from Flash
into RAM
> using the BLDT from National? I assume the BLDT is for WindowsCE OS.
> 
>         I assume like this. I can have the (lilo) bootloader as the
option
> ROM. So my BIOS program shall scan for the option ROMs. Is it
correct?
> 
> _________________________________________________________________
> It's all happening @ F1. Feel the thrill!
> http://server1.msn.co.in/sp03/formula2003/index.asp Race along right
here!
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From hansolofalcon at worldnet.att.net  Tue Jul 22 23:21:08 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Tue Jul 22 23:21:08 2003
Subject: SC1200-BLDT (fwd)
In-Reply-To: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov>
Message-ID: <000901c350cb$6f284880$0100a8c0@who5>

Hello from Gregg C Levine
Here's a suggestion. When people post questions like that, just ask
them, to restate the questions, in a different format. It always
works. Especially when I talk like that.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of ron minnich
> Sent: Tuesday, July 22, 2003 11:21 PM
> To: linuxbios at clustermatic.org
> Subject: SC1200-BLDT (fwd)
> 
> 
> anybody?
> 
> ron
> 
> ---------- Forwarded message ----------
> Date: Wed, 23 Jul 2003 03:12:33 +0000
> From: Devi Priya <ijpriya at hotmail.com>
> To: rminnich at lanl.gov
> Subject: SC1200-BLDT
> 
> 
> Hello
> 
>         I have compiled the linuxbios for sc1200. I also have Dorado
xpress
> loader. Can you plz tell how could I boot my linux OS from Flash
into RAM
> using the BLDT from National? I assume the BLDT is for WindowsCE OS.
> 
>         I assume like this. I can have the (lilo) bootloader as the
option
> ROM. So my BIOS program shall scan for the option ROMs. Is it
correct?
> 
> _________________________________________________________________
> It's all happening @ F1. Feel the thrill!
> http://server1.msn.co.in/sp03/formula2003/index.asp Race along right
here!
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From hansolofalcon at worldnet.att.net  Tue Jul 22 23:25:00 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Tue Jul 22 23:25:00 2003
Subject: About my last post
Message-ID: <000a01c350cb$f62c7e00$0100a8c0@who5>

Hello again from Gregg C Levine
I dislike sending these. Along with the problems associated with this
cloddish mailer. Sorry guys for sending that blasted thing out, twice.
Ron, when you get the four of them, just discard one pair, or the
other.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )






From rminnich at lanl.gov  Tue Jul 22 23:55:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 22 23:55:01 2003
Subject: static and dynamic devices (again)
Message-ID: <Pine.LNX.4.44.0307222121460.956-100000@maxroach.lanl.gov>

Greg has spent the day exploring options for how to merge the static and
dynamic device trees in LinuxBIOS, per Eric's comments. He wrote a
substantial amount of code, which at this point we may not commit. The
goal of the code was to see if it makes sense to merge the static and
dynamic trees. I am not convinced such a merger makes sense.

Discussion follows.

The problem is this: on a given motherboard, there are a static set of 
devices, such as northbridges, southbridges, so on: these are soldered to 
the board. Then there are dynamic devices, plugged into PCI slots. 

On a motherboard, we know that the static devices are there, and we even
know a lot about them, such as what certain registers do.  We need on
the motherboard to initialize components of the static devices. In other
words, we have knowledge about:
o the type of the device; 
o instances ofthe device; 
o special operations we need to do to the device to modify internal 
  state (e.g. turn off the IDE controller, turn on Ethernet, etc.)
o special control information that is highly device-specific

These operations are operations that we have to do because the OS assumes
they will be finished when the OS starts, or we need to do them to
initialize things, such as DRAM.

Dynamic devices are known only in a generic fashion. In LinuxBIOS, the sum
total of our knowledge of dynamic devices is the Base Address Register
set, the Command register, and possibly (in future) the IRQ. LinuxBIOS has
no knowledge of device-specific I/O registers. For dynamic devices,
LinuxBIOS does a few generic operations and lets the OS do the rest. 

So for dynamic devics we know about:
o instances of the device
o Generic control information that is not device-specific

So, to sum up: for static devices, LinuxBIOS needs knowledge that goes
beyond what the OS knows, and will perform device-specific operations
based on internal knowledge LinuxBIOS has about the device. LinuxBIOS will
maintain information about the type of the device and all instances of the
device. In many cases, LinuxBIOS will do operations on the device that the
OS is not capable of doing.

For dynamic devices, LinuxBIOS only does the most general configuration, 
and has no knowledge of device internals. The OS manages device-specific 
operations. 

The dichotomy is pretty clear. 

It is kind of like a house. There are walls and floors and outlets and
phone jacks. These are fixed (static). Then there are chairs and lights
and phones. These are dynamic. You know all about the phone jacks, but you
don't know about what phones are plugged in, and the phones change all the
time, especially if you have children in the house. The static devices
(walls) are a fundamentally different thing than the dynamic devices
(chairs).

We are calling static devices 'chips'. Chips are structured as follows:
there is a chip_control structure for a TYPE of a chip, with generic
information about the chip and a pointer to a control function that is
specific to that chip. Then, for each instance of the chip, there is a
chip structure that contains a pointer to the chip_control structure and
information specific to the INSTANCE of the chip.

Think of chip_info as the class definition, and chip as instantiations of
the chip. 

Chips are statically declared and initialized, and form a tree with a root
at the mainboard, with sibling pointers for chips at the same level --
e.g., two devices hung off the same southbridge are siblings. These
structures are filled out at compile time.

Dynamic devices are called struct device. There is (currently) a device
struct allocated dynamically for each function on a device. 

[digression:  The PCI heritage of devices is very clear once you start
looking at them. This is reasonable, as even on HyperTransport everything
looks like a PCI device.  But it may bite us at some point.]

Devices also form a tree, with children, parents, siblings, etc. One
assumption we've noticed in the device code is that of a 'root bus'.  
Properly, this should not really exist: there can be multiple northbridges
in a system, each with a PCI bus. But the device code so far inherits from 
freebios 1.0 the PC assumption that there is one root bus, and that it is 
configured from a common point of control -- on PCs, the 0xcf8/0xcfc 
mechanism. 

Our early assumption was that we could take the static tree, build a
dynamic tree, and then populate the tree with dynamic devices. Eric would
like to see this happen. Greg and I are no longer convinced this makes
sense. Hence the source of this discussion. 

At minimum, if you build a dynamic tree from the static tree, you'll have
to mark the devices as static. You'll have to handle them differently
because the resources work differently. Some resources such as Base
Address Registers won't exist on devices in the static tree. You'll have
to note that some devices are capable of having device-specific code, and
others are not. You'll end up with structure that really contains two
structures inside: structure members for static devices only, and
structure members for dynamic devices only. It won't be a happy marriage.  
Finally, all your code will have to handle two cases: static and dynamic
devices. Once we looked at this, we saw that we ended up with a dynamic
tree with static devices grafted in, with no apparent savings on
complexity and no real code reuse.

Here is what we think makes sense. The dichotomy between static and 
dynamic devices should remain. The static devices will not be converted 
into some form of dynamic device. There will need to be a linkage from the 
static devices to dynamic devices. This linkage will be at the northbridge 
-- as it is in hardware. 

Northbridges, i.e. devices which have an attached PCI bus (or more than
one), will have a device structure pointer in the device-specific data
structure (i.e. in the chip structure). At some point, as part of the code
that walks the statically allocated northbridge, pci enumeration for that
northbridge takes place.  This has a major advantage for non-PC platforms
(such as PPC) that don't use the standard PC 0xfcf8/0xcfc mechanism for
configuring the PCI bus -- it makes sense to talk to the northbridge
device directly to configure the bus(ses) on that northbridge. It is also
a big win for systems with more than one northbridge -- these will be more
and more common. And for switched, not bus-based, systems the advantage is
apparent.

We thus have a static tree (representing the static resources) with links
at certain places to the dynamic tree (representing dynamic resources).  
LinuxBIOS can do device-specific operations on devices in the static tree,
and can attach dynamic devices to nodes in the static tree. On the
whiteboard in Greg's office, this setup makes lots of sense. We'll see how
it is in practice.

We plan to prototype this in the coming few days and try it out. 

Comments and questions are welcome. We need to open this discussion up. I 
would really like to hear from you folks. As Eric pointed out, we're 
trying to define the 2.0 core functionality, and we want to make it a good 
structure but also one that is easy for people to do new ports. It is 
essential to hear from those of you who are doing ports -- there are lots 
of you on this list.

thanks

ron



From rminnich at lanl.gov  Wed Jul 23 00:01:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 00:01:01 2003
Subject: second alternate startup idea
Message-ID: <Pine.LNX.4.44.0307222213070.956-100000@maxroach.lanl.gov>

Seems to me we could enable the full flash rom decoding, then put the 
c_payload at 0xfffx0000, then have really big linuxbios images. I'll take 
a look at this too, later.

ron



From Qwani at hanafos.com  Wed Jul 23 00:10:00 2003
From: Qwani at hanafos.com (Kyuwan Jung)
Date: Wed Jul 23 00:10:00 2003
Subject: SC1200-BLDT (fwd)
References: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov>
Message-ID: <004b01c350d2$2d3e2eb0$0400a8c0@wsjkw>

xpressLoader has different GDT table with linux kernel.
If you fix this, lilo rom(?) may work.
If you have BootOS source from N.S., porting only linuxbiosmain.c to boot rom
works fine with vsa rom. That was my case.

kyuwan


----- Original Message ----- 
From: "ron minnich" <rminnich at lanl.gov>
To: <linuxbios at clustermatic.org>
Sent: Wednesday, July 23, 2003 12:21 PM
Subject: SC1200-BLDT (fwd)


> 
> anybody?
> 
> ron
> 
> ---------- Forwarded message ----------
> Date: Wed, 23 Jul 2003 03:12:33 +0000
> From: Devi Priya <ijpriya at hotmail.com>
> To: rminnich at lanl.gov
> Subject: SC1200-BLDT
> 
> 
> Hello
> 
>         I have compiled the linuxbios for sc1200. I also have Dorado xpress 
> loader. Can you plz tell how could I boot my linux OS from Flash into RAM 
> using the BLDT from National? I assume the BLDT is for WindowsCE OS.
> 
>         I assume like this. I can have the (lilo) bootloader as the option 
> ROM. So my BIOS program shall scan for the option ROMs. Is it correct?
> 
> _________________________________________________________________
> It's all happening @ F1. Feel the thrill! 
> http://server1.msn.co.in/sp03/formula2003/index.asp Race along right here!
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


From ijpraveen1 at yahoo.com  Wed Jul 23 00:30:01 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Wed Jul 23 00:30:01 2003
Subject: Loading OS from Flash ROM!
In-Reply-To: <Pine.LNX.4.44.0307222051090.375-100000@maxroach.lanl.gov>
Message-ID: <20030723044332.47281.qmail@web41710.mail.yahoo.com>

 
                     It is a soldered one.

 
 
 

ron minnich <rminnich at lanl.gov> wrote:
On Tue, 22 Jul 2003, John Praveen wrote:

> 
> Sorry mine is TE28F320C3TC70 (Intel) 32Mbit Flash memory. If I have to
> boot from Flash memory what part of linux bios should I concentrate?
> What changes has to be done?

NEAT!

removeable or soldered on?

ron


---------------------------------
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From gwatson at lanl.gov  Wed Jul 23 00:36:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Wed Jul 23 00:36:00 2003
Subject: static and dynamic devices (again)
In-Reply-To: <Pine.LNX.4.44.0307222121460.956-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307222121460.956-100000@maxroach.lanl.gov>
Message-ID: <p06001a01bb43bd10ddeb@[10.0.1.2]>

Thanks Ron, post this tome at 10pm so I have to stay up late...

As Ron points out, I spent some time today seeing if it was possible 
to unify the static and dynamic device code. It certainly is 
possible, but it turns out that we're trying to do things in two 
fundamentally different ways. The result is that we just push the 
separation between the two types of devices down another level. I'm 
not sure is something that we want to do, because it just makes 
things more difficult to understand.

My feeling is that keeping them separate is probably the way to go. 
Modifying the current device code so that  dynamic trees can hang off 
a static device (such as a northbridge) will solve some problems that 
are on the horizon. This will also allow code development to move 
forward without major changes, but not preclude unifying the two 
schemes in the future if it becomes necessary.

I'm also interested in any comments on this approach.

Greg

At 10:08 PM -0600 22/7/03, ron minnich wrote:
>Greg has spent the day exploring options for how to merge the static and
>dynamic device trees in LinuxBIOS, per Eric's comments. He wrote a
>substantial amount of code, which at this point we may not commit. The
>goal of the code was to see if it makes sense to merge the static and
>dynamic trees. I am not convinced such a merger makes sense.
>
>Discussion follows.
>
>The problem is this: on a given motherboard, there are a static set of
>devices, such as northbridges, southbridges, so on: these are soldered to
>the board. Then there are dynamic devices, plugged into PCI slots.
>
>On a motherboard, we know that the static devices are there, and we even
>know a lot about them, such as what certain registers do.  We need on
>the motherboard to initialize components of the static devices. In other
>words, we have knowledge about:
>o the type of the device;
>o instances ofthe device;
>o special operations we need to do to the device to modify internal
>   state (e.g. turn off the IDE controller, turn on Ethernet, etc.)
>o special control information that is highly device-specific
>
>These operations are operations that we have to do because the OS assumes
>they will be finished when the OS starts, or we need to do them to
>initialize things, such as DRAM.
>
>Dynamic devices are known only in a generic fashion. In LinuxBIOS, the sum
>total of our knowledge of dynamic devices is the Base Address Register
>set, the Command register, and possibly (in future) the IRQ. LinuxBIOS has
>no knowledge of device-specific I/O registers. For dynamic devices,
>LinuxBIOS does a few generic operations and lets the OS do the rest.
>
>So for dynamic devics we know about:
>o instances of the device
>o Generic control information that is not device-specific
>
>So, to sum up: for static devices, LinuxBIOS needs knowledge that goes
>beyond what the OS knows, and will perform device-specific operations
>based on internal knowledge LinuxBIOS has about the device. LinuxBIOS will
>maintain information about the type of the device and all instances of the
>device. In many cases, LinuxBIOS will do operations on the device that the
>OS is not capable of doing.
>
>For dynamic devices, LinuxBIOS only does the most general configuration,
>and has no knowledge of device internals. The OS manages device-specific
>operations.
>
>The dichotomy is pretty clear.
>
>It is kind of like a house. There are walls and floors and outlets and
>phone jacks. These are fixed (static). Then there are chairs and lights
>and phones. These are dynamic. You know all about the phone jacks, but you
>don't know about what phones are plugged in, and the phones change all the
>time, especially if you have children in the house. The static devices
>(walls) are a fundamentally different thing than the dynamic devices
>(chairs).
>
>We are calling static devices 'chips'. Chips are structured as follows:
>there is a chip_control structure for a TYPE of a chip, with generic
>information about the chip and a pointer to a control function that is
>specific to that chip. Then, for each instance of the chip, there is a
>chip structure that contains a pointer to the chip_control structure and
>information specific to the INSTANCE of the chip.
>
>Think of chip_info as the class definition, and chip as instantiations of
>the chip.
>
>Chips are statically declared and initialized, and form a tree with a root
>at the mainboard, with sibling pointers for chips at the same level --
>e.g., two devices hung off the same southbridge are siblings. These
>structures are filled out at compile time.
>
>Dynamic devices are called struct device. There is (currently) a device
>struct allocated dynamically for each function on a device.
>
>[digression:  The PCI heritage of devices is very clear once you start
>looking at them. This is reasonable, as even on HyperTransport everything
>looks like a PCI device.  But it may bite us at some point.]
>
>Devices also form a tree, with children, parents, siblings, etc. One
>assumption we've noticed in the device code is that of a 'root bus'. 
>Properly, this should not really exist: there can be multiple northbridges
>in a system, each with a PCI bus. But the device code so far inherits from
>freebios 1.0 the PC assumption that there is one root bus, and that it is
>configured from a common point of control -- on PCs, the 0xcf8/0xcfc
>mechanism.
>
>Our early assumption was that we could take the static tree, build a
>dynamic tree, and then populate the tree with dynamic devices. Eric would
>like to see this happen. Greg and I are no longer convinced this makes
>sense. Hence the source of this discussion.
>
>At minimum, if you build a dynamic tree from the static tree, you'll have
>to mark the devices as static. You'll have to handle them differently
>because the resources work differently. Some resources such as Base
>Address Registers won't exist on devices in the static tree. You'll have
>to note that some devices are capable of having device-specific code, and
>others are not. You'll end up with structure that really contains two
>structures inside: structure members for static devices only, and
>structure members for dynamic devices only. It won't be a happy marriage. 
>Finally, all your code will have to handle two cases: static and dynamic
>devices. Once we looked at this, we saw that we ended up with a dynamic
>tree with static devices grafted in, with no apparent savings on
>complexity and no real code reuse.
>
>Here is what we think makes sense. The dichotomy between static and
>dynamic devices should remain. The static devices will not be converted
>into some form of dynamic device. There will need to be a linkage from the
>static devices to dynamic devices. This linkage will be at the northbridge
>-- as it is in hardware.
>
>Northbridges, i.e. devices which have an attached PCI bus (or more than
>one), will have a device structure pointer in the device-specific data
>structure (i.e. in the chip structure). At some point, as part of the code
>that walks the statically allocated northbridge, pci enumeration for that
>northbridge takes place.  This has a major advantage for non-PC platforms
>(such as PPC) that don't use the standard PC 0xfcf8/0xcfc mechanism for
>configuring the PCI bus -- it makes sense to talk to the northbridge
>device directly to configure the bus(ses) on that northbridge. It is also
>a big win for systems with more than one northbridge -- these will be more
>and more common. And for switched, not bus-based, systems the advantage is
>apparent.
>
>We thus have a static tree (representing the static resources) with links
>at certain places to the dynamic tree (representing dynamic resources). 
>LinuxBIOS can do device-specific operations on devices in the static tree,
>and can attach dynamic devices to nodes in the static tree. On the
>whiteboard in Greg's office, this setup makes lots of sense. We'll see how
>it is in practice.
>
>We plan to prototype this in the coming few days and try it out.
>
>Comments and questions are welcome. We need to open this discussion up. I
>would really like to hear from you folks. As Eric pointed out, we're
>trying to define the 2.0 core functionality, and we want to make it a good
>structure but also one that is easy for people to do new ports. It is
>essential to hear from those of you who are doing ports -- there are lots
>of you on this list.
>
>thanks
>
>ron
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Wed Jul 23 01:07:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 01:07:00 2003
Subject: Loading OS from Flash ROM!
In-Reply-To: <20030723044332.47281.qmail@web41710.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0307222319051.1352-100000@maxroach.lanl.gov>

On Tue, 22 Jul 2003, John Praveen wrote:

>  
>                      It is a soldered one.

So is the question how you program it? Is there a recovery jumper for when
you burn a bad BIOS? Can you send me the URL for the board?

ron



From rminnich at lanl.gov  Wed Jul 23 01:21:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 01:21:00 2003
Subject: K8 Progress
In-Reply-To: <20030721232525.A17328@suse.de>
Message-ID: <Pine.LNX.4.44.0307222328310.1352-100000@maxroach.lanl.gov>

it's getting easier and easier to resync the new config tool to the
ongoing changes. Took a few minutes earlier today and I was back on the
air.

I have noticed that the testing of the first 16M of memory in auto.c is 
very slow, so I've turned it off on my version. My guess is for you guys 
it runs very fast. There must still be a difference somewhere. Can someone 
confirm that the K8 memory test in auto.c is fast? 

A note on the SST 49LF0[48]0 flash parts, since we've all had trouble with
them.  Here's what I have found. The first time I flash there is always
trouble. However, if I 'eraseall /dev/mtd0' a few times, then do the 'dd
trick':

dd if=image of=/dev/mtd0 bs=65536 seek=$i skip=$i

i.e. program individual blocks, it almost always works. 


From hansolofalcon at worldnet.att.net  Wed Jul 23 01:27:01 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Wed Jul 23 01:27:01 2003
Subject: static and dynamic devices (again)
In-Reply-To: <p06001a01bb43bd10ddeb@[10.0.1.2]>
Message-ID: <000201c350dc$f5888d20$0100a8c0@who5>

Hello again from Gregg C Levine
Greg, I am almost always up late. 
I looked over Ron's dissertation, and it looks to be a doozy. I'm not
being crude, or insulting, just that it looks to be the one method for
implementing Linux BIOS that should work, with almost any board we
choose. Regretfully I have not selected a port, or a board design,
because I have not been able to select one board that will work.

Ideally, I, should be able to be working with one, by sometime this
coming September. However, I am openminded enough to understand that
things change. Both of you have good ideas. 
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of Greg Watson
> Sent: Wednesday, July 23, 2003 12:48 AM
> To: ron minnich
> Cc: linuxbios at clustermatic.org
> Subject: Re: static and dynamic devices (again)
> 
> Thanks Ron, post this tome at 10pm so I have to stay up late...
> 
> As Ron points out, I spent some time today seeing if it was possible
> to unify the static and dynamic device code. It certainly is
> possible, but it turns out that we're trying to do things in two
> fundamentally different ways. The result is that we just push the
> separation between the two types of devices down another level. I'm
> not sure is something that we want to do, because it just makes
> things more difficult to understand.
> 
> My feeling is that keeping them separate is probably the way to go.
> Modifying the current device code so that  dynamic trees can hang
off
> a static device (such as a northbridge) will solve some problems
that
> are on the horizon. This will also allow code development to move
> forward without major changes, but not preclude unifying the two
> schemes in the future if it becomes necessary.
> 
> I'm also interested in any comments on this approach.
> 
> Greg
> 
> At 10:08 PM -0600 22/7/03, ron minnich wrote:
> >Greg has spent the day exploring options for how to merge the
static and
> >dynamic device trees in LinuxBIOS, per Eric's comments. He wrote a
> >substantial amount of code, which at this point we may not commit.
The
> >goal of the code was to see if it makes sense to merge the static
and
> >dynamic trees. I am not convinced such a merger makes sense.
> >
> >Discussion follows.
> >
> >The problem is this: on a given motherboard, there are a static set
of
> >devices, such as northbridges, southbridges, so on: these are
soldered to
> >the board. Then there are dynamic devices, plugged into PCI slots.
> >
> >On a motherboard, we know that the static devices are there, and we
even
> >know a lot about them, such as what certain registers do.  We need
on
> >the motherboard to initialize components of the static devices. In
other
> >words, we have knowledge about:
> >o the type of the device;
> >o instances ofthe device;
> >o special operations we need to do to the device to modify internal
> >   state (e.g. turn off the IDE controller, turn on Ethernet, etc.)
> >o special control information that is highly device-specific
> >
> >These operations are operations that we have to do because the OS
assumes
> >they will be finished when the OS starts, or we need to do them to
> >initialize things, such as DRAM.
> >
> >Dynamic devices are known only in a generic fashion. In LinuxBIOS,
the sum
> >total of our knowledge of dynamic devices is the Base Address
Register
> >set, the Command register, and possibly (in future) the IRQ.
LinuxBIOS has
> >no knowledge of device-specific I/O registers. For dynamic devices,
> >LinuxBIOS does a few generic operations and lets the OS do the
rest.
> >
> >So for dynamic devics we know about:
> >o instances of the device
> >o Generic control information that is not device-specific
> >
> >So, to sum up: for static devices, LinuxBIOS needs knowledge that
goes
> >beyond what the OS knows, and will perform device-specific
operations
> >based on internal knowledge LinuxBIOS has about the device.
LinuxBIOS will
> >maintain information about the type of the device and all instances
of the
> >device. In many cases, LinuxBIOS will do operations on the device
that the
> >OS is not capable of doing.
> >
> >For dynamic devices, LinuxBIOS only does the most general
configuration,
> >and has no knowledge of device internals. The OS manages
device-specific
> >operations.
> >
> >The dichotomy is pretty clear.
> >
> >It is kind of like a house. There are walls and floors and outlets
and
> >phone jacks. These are fixed (static). Then there are chairs and
lights
> >and phones. These are dynamic. You know all about the phone jacks,
but you
> >don't know about what phones are plugged in, and the phones change
all the
> >time, especially if you have children in the house. The static
devices
> >(walls) are a fundamentally different thing than the dynamic
devices
> >(chairs).
> >
> >We are calling static devices 'chips'. Chips are structured as
follows:
> >there is a chip_control structure for a TYPE of a chip, with
generic
> >information about the chip and a pointer to a control function that
is
> >specific to that chip. Then, for each instance of the chip, there
is a
> >chip structure that contains a pointer to the chip_control
structure and
> >information specific to the INSTANCE of the chip.
> >
> >Think of chip_info as the class definition, and chip as
instantiations of
> >the chip.
> >
> >Chips are statically declared and initialized, and form a tree with
a root
> >at the mainboard, with sibling pointers for chips at the same level
--
> >e.g., two devices hung off the same southbridge are siblings. These
> >structures are filled out at compile time.
> >
> >Dynamic devices are called struct device. There is (currently) a
device
> >struct allocated dynamically for each function on a device.
> >
> >[digression:  The PCI heritage of devices is very clear once you
start
> >looking at them. This is reasonable, as even on HyperTransport
everything
> >looks like a PCI device.  But it may bite us at some point.]
> >
> >Devices also form a tree, with children, parents, siblings, etc.
One
> >assumption we've noticed in the device code is that of a 'root
bus'.
> >Properly, this should not really exist: there can be multiple
northbridges
> >in a system, each with a PCI bus. But the device code so far
inherits from
> >freebios 1.0 the PC assumption that there is one root bus, and that
it is
> >configured from a common point of control -- on PCs, the
0xcf8/0xcfc
> >mechanism.
> >
> >Our early assumption was that we could take the static tree, build
a
> >dynamic tree, and then populate the tree with dynamic devices. Eric
would
> >like to see this happen. Greg and I are no longer convinced this
makes
> >sense. Hence the source of this discussion.
> >
> >At minimum, if you build a dynamic tree from the static tree,
you'll have
> >to mark the devices as static. You'll have to handle them
differently
> >because the resources work differently. Some resources such as Base
> >Address Registers won't exist on devices in the static tree. You'll
have
> >to note that some devices are capable of having device-specific
code, and
> >others are not. You'll end up with structure that really contains
two
> >structures inside: structure members for static devices only, and
> >structure members for dynamic devices only. It won't be a happy
marriage.
> >Finally, all your code will have to handle two cases: static and
dynamic
> >devices. Once we looked at this, we saw that we ended up with a
dynamic
> >tree with static devices grafted in, with no apparent savings on
> >complexity and no real code reuse.
> >
> >Here is what we think makes sense. The dichotomy between static and
> >dynamic devices should remain. The static devices will not be
converted
> >into some form of dynamic device. There will need to be a linkage
from the
> >static devices to dynamic devices. This linkage will be at the
northbridge
> >-- as it is in hardware.
> >
> >Northbridges, i.e. devices which have an attached PCI bus (or more
than
> >one), will have a device structure pointer in the device-specific
data
> >structure (i.e. in the chip structure). At some point, as part of
the code
> >that walks the statically allocated northbridge, pci enumeration
for that
> >northbridge takes place.  This has a major advantage for non-PC
platforms
> >(such as PPC) that don't use the standard PC 0xfcf8/0xcfc mechanism
for
> >configuring the PCI bus -- it makes sense to talk to the
northbridge
> >device directly to configure the bus(ses) on that northbridge. It
is also
> >a big win for systems with more than one northbridge -- these will
be more
> >and more common. And for switched, not bus-based, systems the
advantage is
> >apparent.
> >
> >We thus have a static tree (representing the static resources) with
links
> >at certain places to the dynamic tree (representing dynamic
resources).
> >LinuxBIOS can do device-specific operations on devices in the
static tree,
> >and can attach dynamic devices to nodes in the static tree. On the
> >whiteboard in Greg's office, this setup makes lots of sense. We'll
see how
> >it is in practice.
> >
> >We plan to prototype this in the coming few days and try it out.
> >
> >Comments and questions are welcome. We need to open this discussion
up. I
> >would really like to hear from you folks. As Eric pointed out,
we're
> >trying to define the 2.0 core functionality, and we want to make it
a good
> >structure but also one that is easy for people to do new ports. It
is
> >essential to hear from those of you who are doing ports -- there
are lots
> >of you on this list.
> >
> >thanks
> >
> >ron
> >
> >_______________________________________________
> >Linuxbios mailing list
> >Linuxbios at clustermatic.org
> >http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From ollie at sis.com.tw  Wed Jul 23 02:57:00 2003
From: ollie at sis.com.tw (ollie lho)
Date: Wed Jul 23 02:57:00 2003
Subject: static and dynamic devices (again)
In-Reply-To: <Pine.LNX.4.44.0307222121460.956-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307222121460.956-100000@maxroach.lanl.gov>
Message-ID: <1058943262.3345.147.camel@ollie>

On Wed, 2003-07-23 at 12:08, ron minnich wrote:
> 
> We thus have a static tree (representing the static resources) with links
> at certain places to the dynamic tree (representing dynamic resources).  
> LinuxBIOS can do device-specific operations on devices in the static tree,
> and can attach dynamic devices to nodes in the static tree. On the
> whiteboard in Greg's office, this setup makes lots of sense. We'll see how
> it is in practice.
> 

Does this mean you have a device tree with STATIC nodes and DYNAMIC
nodes ? Does your code have to distinguish between static nodes from
dynamic ones when traveling the tree ? Is my imaginary of the scenario
as the following correct ?

	1. Device tree with static node is build at compile time.
	   (with some nodes marked "dynamic extensible").
	2. Travel the tree to init static node, for dynamic extensible
	   nodes, grow the tree.
	2.1 Init the dynamic nodes.
	3. Travel the tree again to do post-pci (whatever you call it)
	   init for static nodes.

-- 
ollie lho <ollie at sis.com.tw>



From stepan at suse.de  Wed Jul 23 04:09:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Jul 23 04:09:01 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <Pine.LNX.4.44.0307221703070.21850-100000@maxroach.lanl.gov>; from rminnich@lanl.gov on Tue, Jul 22, 2003 at 06:48:27PM -0600
References: <Pine.LNX.4.44.0307221703070.21850-100000@maxroach.lanl.gov>
Message-ID: <20030723102155.A29527@suse.de>

* ron minnich <rminnich at lanl.gov> [030723 02:48]:
> make reset a rel jump to 0xfffffff0 - (sizeof entry16). Then put entry 16
> right before 0xfffffff0. Entry16 code turns on 32-bit mode and then jumps
> to the real start of the linuxbios image -- which can now be anywhere in
> the flash image. I could use this now, as could others.
 
Sounds pretty good!

> Here's where I wish I had a really good emulator for linux -- checking 
> this out would be a whole lot easier.

Have you tried this in bochs? It showed up to be pretty ok for bios
testing (as long as you don't test hw init of course)

Stefan
  
-- 
Architecture Team
    SuSE Linux AG


From stepan at suse.de  Wed Jul 23 04:11:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Jul 23 04:11:01 2003
Subject: alternate startup idea.
In-Reply-To: <Pine.LNX.4.44.0307221924180.21850-100000@maxroach.lanl.gov>; from rminnich@lanl.gov on Tue, Jul 22, 2003 at 07:26:52PM -0600
References: <Pine.LNX.4.44.0307221924180.21850-100000@maxroach.lanl.gov>
Message-ID: <20030723102432.B29527@suse.de>

* ron minnich <rminnich at lanl.gov> [030723 03:26]:
> Well, my alternate startup idea works fine on the K8. Except ... looks 
> like flash rom addressing is not enabled by default for anything but the 
> 0xffff0000 segment, which means while my idea works, it's useless: if I 
> jump to the 0xfffe0000 segment, I'll be reading air, not the flash part. 
> 
> Darn it. I kind of wish that we could get the chipmakers to default to 
> full addressing in the high part of the address space, i.e. when it 
> decodes for the flash, it decodes from 0xfff00000 up, not 0xffff0000 up. 
> Someday ...
 
Hm. On the K8 this might be a special problem as you have to do the non
coherent HT enumeration before you can actually access the southbridge 
registers. On any non-HT system it should be easy to map the missing
address space using the southbridge though.

  Stefan

-- 
Architecture Team
    SuSE Linux AG


From marco_hetzel at web.de  Wed Jul 23 04:20:00 2003
From: marco_hetzel at web.de (Marco Hetzel)
Date: Wed Jul 23 04:20:00 2003
Subject: NVidia NForce2
Message-ID: <200307231031.47232.marco_hetzel@web.de>

  Hi!
The help-fromular on your page isn't working, so I once again try to write 
here.
Are there any Driver for the NForce2 - Chipset? 
THX,

  Marco


From salmon.chen at msa.hinet.net  Wed Jul 23 06:10:01 2003
From: salmon.chen at msa.hinet.net (Tien)
Date: Wed Jul 23 06:10:01 2003
Subject: supermicro p4dc6p complier problem
Message-ID: <002e01c35104$617b3790$160aa8c0@D29092.findquick.com>

Hi guys,
           Does anyone can complier supermicro P4DC6P with latest version
source code?
Pls let me know how to do it if anyone know it.

Best regards,
Tien



From fre at wenglor.de  Wed Jul 23 08:40:01 2003
From: fre at wenglor.de (Franz Reinhardt)
Date: Wed Jul 23 08:40:01 2003
Subject: OT: job offer
Message-ID: <200307231446.02368.fre@wenglor.de>

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im Bereich der optischen Sensorik. 

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Weitere Informationen zu diesem Stellenangebot erhalten sie
per Email: fre at wenglor.de
oder telefonisch:  +49 (0)7542-5399-421

-- 
----wenglor(R)----sensors for your success----------



From rminnich at lanl.gov  Wed Jul 23 10:45:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 10:45:01 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <20030723102155.A29527@suse.de>
Message-ID: <Pine.LNX.4.44.0307230840010.5540-100000@maxroach.lanl.gov>

On Wed, 23 Jul 2003, Stefan Reinauer wrote:

> * ron minnich <rminnich at lanl.gov> [030723 02:48]:
> > make reset a rel jump to 0xfffffff0 - (sizeof entry16). Then put entry 16
> > right before 0xfffffff0. Entry16 code turns on 32-bit mode and then jumps
> > to the real start of the linuxbios image -- which can now be anywhere in
> > the flash image. I could use this now, as could others.
>  
> Sounds pretty good!

it sounded good to me too :-)

sadly, it appears that 0xffe0000 is not enabled at hardware startup. 

Stefan, what makes sense to do for this problem?

One option is to grow this idea a bit: have the 32-bit mode enable right 
below 0xfffffff0, but include in that a flash enable. Then it would work. 

By far the simplest thing to do is make it possible to move c_payload 
around, say to 0xfffe0000

ron



From rminnich at lanl.gov  Wed Jul 23 10:46:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 10:46:00 2003
Subject: alternate startup idea.
In-Reply-To: <20030723102432.B29527@suse.de>
Message-ID: <Pine.LNX.4.44.0307230858540.5540-100000@maxroach.lanl.gov>

On Wed, 23 Jul 2003, Stefan Reinauer wrote:

> Hm. On the K8 this might be a special problem as you have to do the non
> coherent HT enumeration before you can actually access the southbridge 
> registers. On any non-HT system it should be easy to map the missing
> address space using the southbridge though.

HT is cool, sometimes a little too cool :)

ron



From rminnich at lanl.gov  Wed Jul 23 10:47:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 10:47:00 2003
Subject: supermicro p4dc6p complier problem
In-Reply-To: <002e01c35104$617b3790$160aa8c0@D29092.findquick.com>
Message-ID: <Pine.LNX.4.44.0307230900250.5540-100000@maxroach.lanl.gov>

On Wed, 23 Jul 2003, Tien wrote:

>            Does anyone can complier supermicro P4DC6P with latest version
> source code?

I think that works.

ron



From stepan at suse.de  Wed Jul 23 10:53:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Jul 23 10:53:00 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <Pine.LNX.4.44.0307230840010.5540-100000@maxroach.lanl.gov>
References: <20030723102155.A29527@suse.de> <Pine.LNX.4.44.0307230840010.5540-100000@maxroach.lanl.gov>
Message-ID: <20030723150529.GA5714@suse.de>

* ron minnich <rminnich at lanl.gov> [030723 16:58]:
> > > make reset a rel jump to 0xfffffff0 - (sizeof entry16). Then put entry 16
> > > right before 0xfffffff0. Entry16 code turns on 32-bit mode and then jumps
> > > to the real start of the linuxbios image -- which can now be anywhere in
> > > the flash image. I could use this now, as could others.
 
> sadly, it appears that 0xffe0000 is not enabled at hardware startup. 

> One option is to grow this idea a bit: have the 32-bit mode enable right 
> below 0xfffffff0, but include in that a flash enable. Then it would work. 
 
If a flash enable can always happen that early, this is definitely a
good idea, as we want to know our code as soon as possible.

On the K8 this might mean that this early code has to contain all of:

* check if BSP
* coherent ht init
* non coherent ht enumeration
* enable flash

before actually jumping anywhere down. Don't know if that would all fit.

> By far the simplest thing to do is make it possible to move c_payload 
> around, say to 0xfffe0000

if this means that we can easily make linuxbios fallback and normal
share the same payload, it would be my fav.

Stefan





From rminnich at lanl.gov  Wed Jul 23 11:02:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 11:02:00 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <20030723150529.GA5714@suse.de>
Message-ID: <Pine.LNX.4.44.0307230912550.5540-100000@maxroach.lanl.gov>

On Wed, 23 Jul 2003, Stefan Reinauer wrote:

> > By far the simplest thing to do is make it possible to move c_payload 
> > around, say to 0xfffe0000
> 
> if this means that we can easily make linuxbios fallback and normal
> share the same payload, it would be my fav.

not sure about that. Currently the layout is something like this:

0xffff0000: 	linuxbios startup
  ffff9a30: 	c_payload
  fffffff0:     reset16

If linuxbios startup enables flash in lower addresses, we ought to be able 
to do this:
0xfffe0000:     c_payload
0xffff0000:	linuxbios startup
0xfffffff0: 	reset16

Life would be easier ... we could have lots of debug ...

ron



From stepan at suse.de  Wed Jul 23 11:15:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Jul 23 11:15:00 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <Pine.LNX.4.44.0307230912550.5540-100000@maxroach.lanl.gov>
References: <20030723150529.GA5714@suse.de> <Pine.LNX.4.44.0307230912550.5540-100000@maxroach.lanl.gov>
Message-ID: <20030723152752.GA6148@suse.de>

* ron minnich <rminnich at lanl.gov> [030723 17:15]:
> On Wed, 23 Jul 2003, Stefan Reinauer wrote:
> > if this means that we can easily make linuxbios fallback and normal
> > share the same payload, it would be my fav.
 
> not sure about that. Currently the layout is something like this:
 
ah,.. my fault.. i mixed up c_payload with the elf payload.

> 0xffff0000: 	linuxbios startup
>   ffff9a30: 	c_payload
>   fffffff0:     reset16
> 
> If linuxbios startup enables flash in lower addresses, we ought to be able 
> to do this:
> 0xfffe0000:     c_payload
> 0xffff0000:	linuxbios startup
> 0xfffffff0: 	reset16
 
since linuxbios startup does ht enumeration anyways before jumping into
c_payload, this should not be a problem

Stefan



From steve at nexpath.com  Wed Jul 23 11:47:00 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Wed Jul 23 11:47:00 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <Pine.LNX.4.44.0307221703070.21850-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307221703070.21850-100000@maxroach.lanl.gov>
Message-ID: <3F1EADEC.40807@nexpath.com>

ron minnich wrote:

> make reset a rel jump to 0xfffffff0 - (sizeof entry16). Then put entry 16
> right before 0xfffffff0. Entry16 code turns on 32-bit mode and then jumps
> to the real start of the linuxbios image -- which can now be anywhere in
> the flash image. I could use this now, as could others.
> 

I suggested this last year, with the comment that this is a more 
traditional way that embedded systems start up.  Your objections at the 
time were that it would cause trouble with some motherboards, but I 
don't remember the specifics.  I was wanting to do this since it is 
clear that we will be getting 2 Mbyte LPC soon and be able to boot 
Linux easily out of flash (as I think you have already done).

One caveat I discovered, I could never get Linux to boot with a gdt 
located higher than 1M.  So even if you put a linux compatible gdt high, 
it has to be moved to ram < 1M or linux hangs on boot.  Never figured 
out why (true for 2.4 anyway).

Also, on the dynamic/static trees, one thing to consider in the mix is 
the serial ATA.  I think it is an external chip now but will be subsumed 
into the bridge chips at some point.  Not sure how a chip function 
moving around like this affects the software design.

-Steve



From rminnich at lanl.gov  Wed Jul 23 11:55:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 11:55:01 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <3F1EADEC.40807@nexpath.com>
Message-ID: <Pine.LNX.4.44.0307231007200.5540-100000@maxroach.lanl.gov>

On Wed, 23 Jul 2003, Steve Gehlbach wrote:

> I suggested this last year, with the comment that this is a more 
> traditional way that embedded systems start up.  Your objections at the 
> time were that it would cause trouble with some motherboards, but I 
> don't remember the specifics.  I was wanting to do this since it is 
> clear that we will be getting 2 Mbyte LPC soon and be able to boot 
> Linux easily out of flash (as I think you have already done).

you have an inconvenient memory: you were right and I was wrong :-)


> One caveat I discovered, I could never get Linux to boot with a gdt 
> located higher than 1M.  So even if you put a linux compatible gdt high, 
> it has to be moved to ram < 1M or linux hangs on boot.  Never figured 
> out why (true for 2.4 anyway).

we're not seeing this. We have GDTs in very high memory and it all works. 
Interesting.

> Also, on the dynamic/static trees, one thing to consider in the mix is 
> the serial ATA.  I think it is an external chip now but will be subsumed 
> into the bridge chips at some point.  Not sure how a chip function 
> moving around like this affects the software design.

I think it might work. On the Acer, the IDE controller has always been in 
that static initialization. In fact, the superio architecture was 
motivated by the acer chip.

ron



From stepan at suse.de  Wed Jul 23 12:08:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Jul 23 12:08:01 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <Pine.LNX.4.44.0307231007200.5540-100000@maxroach.lanl.gov>
References: <3F1EADEC.40807@nexpath.com> <Pine.LNX.4.44.0307231007200.5540-100000@maxroach.lanl.gov>
Message-ID: <20030723161938.GA7570@suse.de>

* ron minnich <rminnich at lanl.gov> [030723 18:08]:
> On Wed, 23 Jul 2003, Steve Gehlbach wrote:

> > One caveat I discovered, I could never get Linux to boot with a gdt 
> > located higher than 1M.  So even if you put a linux compatible gdt high, 
> > it has to be moved to ram < 1M or linux hangs on boot.  Never figured 
> > out why (true for 2.4 anyway).
> 
> we're not seeing this. We have GDTs in very high memory and it all works. 
> Interesting.
 
Could this cause the hang with ADLO/rombios when booting grub on K8? 
Grub seems to hang right when it switches to pmode the first time.


Stefan



From gwatson at lanl.gov  Wed Jul 23 12:17:01 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Wed Jul 23 12:17:01 2003
Subject: static and dynamic devices (again)
In-Reply-To: <1058943262.3345.147.camel@ollie>
References: <Pine.LNX.4.44.0307222121460.956-100000@maxroach.lanl.gov>
 <1058943262.3345.147.camel@ollie>
Message-ID: <p06001a08bb4466b91d6f@[10.0.1.2]>

At 2:54 PM +0800 23/7/03, ollie lho wrote:
>On Wed, 2003-07-23 at 12:08, ron minnich wrote:
>>
>>  We thus have a static tree (representing the static resources) with links
>>  at certain places to the dynamic tree (representing dynamic resources). 
>>  LinuxBIOS can do device-specific operations on devices in the static tree,
>>  and can attach dynamic devices to nodes in the static tree. On the
>>  whiteboard in Greg's office, this setup makes lots of sense. We'll see how
>>  it is in practice.
>>
>
>Does this mean you have a device tree with STATIC nodes and DYNAMIC
>nodes ? Does your code have to distinguish between static nodes from
>dynamic ones when traveling the tree ? Is my imaginary of the scenario
>as the following correct ?
>
>	1. Device tree with static node is build at compile time.
>	   (with some nodes marked "dynamic extensible").
>	2. Travel the tree to init static node, for dynamic extensible
>	   nodes, grow the tree.
>	2.1 Init the dynamic nodes.
>	3. Travel the tree again to do post-pci (whatever you call it)
>	   init for static nodes.
>

Originally I was going to try using a single node type for both 
dynamic and static devices, but it turns out that there is very 
little in common and it seems to make more sense to keep them 
separate. Your scenario is correct, though I'm thinking that the 
static tree will be the primary data structure and the dynamic tree 
will be attached to a node the same way as other device-specific 
data. So the static tree will not grow, just be populated with data.

Greg


From YhLu at tyan.com  Wed Jul 23 13:30:01 2003
From: YhLu at tyan.com (YhLu)
Date: Wed Jul 23 13:30:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302FC9984@TYANWEB>

Eric or Ron or Stepfan,

To make the NIC under mem auto-conf code, I have spent one day on it. Here
are my findings:
1. Use the most updated code, in the Etherboot stage it will reboot after
firt NIC try aborting.
2. I have try to subsutite mem-conf with hard code version, and found
another problem, I can not start AP after conherent_ht or memory
initization. Only can start and stop in enable_routing function.
3. I have to move back to old code ( Before Eric moved some definition from
romcc_io.h to arch/io.h and cpu/p6/msr.h). At this situation, if I use
mem-conf, it still can not find broadcom nic in etherboot stage. But after I
substitute mem init with hard code one, It can find the nic.

I will study the difference today.

But anyway what make I can not start AP after conherent_ht or memory init,
so strange ???

Regards

Yinghai Lu

-----????-----
???: YhLu 
????: 2003?7?22? 10:41
???: 'ebiederman at lnxi.com'
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

Eric,

It can be compiled with you new code. But it meet problems in Etherboot
stage.
In S2880 has two broadcom NIC port in 8131 bus B, and one amd 8111 built-in
nic, and even if I hide it in amd8111 init and Etherboot can find it and try
to enable it and can not find the PM cap so aborting, in the old linuxbios
code (before yesterday) ( with mem hard code), it will go to tickle on
Broadcom nic, but in the new code (yesterday check in) ( mem configurable),
it will go to MB restarting.???

How about arima broadcom nic position? 

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?7?21? 18:33
???: YhLu
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> In the auto.c, if I enable : sdram_initialize(&cpu1), the linuxbios need
> another 20k. What happened? Only add one line and the same function has
been
> called ???

All functions are inline and the set of functions called is large.
At least I believe that is the issue.

And good luck catching up....

While I am away you get a chance.  My latest code has changed
sdram_initialize
one more time to take a cpu count parameter.

And perversely this should help because if a function is called in a loop
it will only be inlined once instead of multiple times.

Eric


From steve at nexpath.com  Wed Jul 23 13:39:00 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Wed Jul 23 13:39:00 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <Pine.LNX.4.44.0307231007200.5540-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307231007200.5540-100000@maxroach.lanl.gov>
Message-ID: <3F1EC3F2.4090304@nexpath.com>

ron minnich wrote:

>>One caveat I discovered, I could never get Linux to boot with a gdt 
>>located higher than 1M.  So even if you put a linux compatible gdt high, 
>>it has to be moved to ram < 1M or linux hangs on boot.  Never figured 
>>out why (true for 2.4 anyway).
> 
> 
> we're not seeing this. We have GDTs in very high memory and it all works. 
> Interesting.
> 

Hmm... are you sure?  I tested this many times, and it was also reported 
on the Xbox project as well.  Since Eric put in c_start.S, it has been 
located in RAM < 1M (moved with the C code), but I don't know how v2 is 
doing it, haven't looked at it.  The latest kernel I tested was 2.4.18 I 
believe.  I have never gotten the kernel to boot with the gdt in flash, 
where the addresses were just under 4G.  And it doesn't seem to have 
anything to do with the RO nature of flash.


-Steve



From steve at nexpath.com  Wed Jul 23 13:40:05 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Wed Jul 23 13:40:05 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <20030723161938.GA7570@suse.de>
References: <3F1EADEC.40807@nexpath.com> <Pine.LNX.4.44.0307231007200.5540-100000@maxroach.lanl.gov> <20030723161938.GA7570@suse.de>
Message-ID: <3F1EC4BA.8080709@nexpath.com>

Stefan Reinauer wrote:


>>>One caveat I discovered, I could never get Linux to boot with a gdt 
>>>located higher than 1M.  So even if you put a linux compatible gdt high, 
>>>it has to be moved to ram < 1M or linux hangs on boot.  Never figured 
>>>out why (true for 2.4 anyway).

> Could this cause the hang with ADLO/rombios when booting grub on K8? 
> Grub seems to hang right when it switches to pmode the first time.

For me, it happened every time, so I don't know what "first time" means. 
  I guess I could have been doing something really stupid (I regret to 
admit this is possible), but I do recall making a number of before and 
after tests with a number of different memory addresses.

-Steve



From bari at onelabs.com  Wed Jul 23 13:50:00 2003
From: bari at onelabs.com (Bari Ari)
Date: Wed Jul 23 13:50:00 2003
Subject: OT: job offer
In-Reply-To: <200307231446.02368.fre@wenglor.de>
References: <200307231446.02368.fre@wenglor.de>
Message-ID: <3F1ECEA6.3010806@onelabs.com>

Franz Reinhardt wrote:

>wenglor sensoric gmbh sucht:
>
>PC-HW/SW-Entwickler (Ingenieur/Techniker mit Berufserfahrung) zur 
>Schaltungsentwicklung und Treiberprogrammierung.
>
>  
>
Does he/she need to speak German? ;-)

-Bari




From han2004 at hotmail.com  Wed Jul 23 13:50:18 2003
From: han2004 at hotmail.com (gimyung han)
Date: Wed Jul 23 13:50:18 2003
Subject: Can you help me?     I'm working on VIA-EPIA 
Message-ID: <BAY2-F153e5dCmjMAok0000f436@hotmail.com>

hi everyone !!

I'm trying to burn romimage on the VIA-EPIA (VIA C3-800 Mhz, VT8231)

I just succeeded in making romimage, and I cd into 
/freebios/util/flash_and_burn, and type make to compile.

Finally, I got  excutive file "flash_rom".

To test "flash_rom", I typed flash_rom without any parameter.
and I saw following message

Calibrating timer since microsleep sucks ... takes a second
Setting up microsecond timing loop
153M loops per second
OK, calibrated, now do the deed
Enabling flash write on VT8231...tried to set 0x44 to 0x54 on VT8231 failed 
(WARNING ONLY)
Trying Am29F040B, 512 KB
probe_29f040b: id1 0x25, id2 0xa6
Trying At29C040A, 512 KB
probe_jedec: id1 0xbf, id2 0xb6
Trying Mx29f002, 256 KB
probe_29f002: id1 191, id2 182
Trying SST29EE020A, 256 KB
probe_jedec: id1 0xbf, id2 0xb6
Trying SST28SF040A, 512 KB
probe_28sf040: id1 0x25, id2 0xa6
Trying SST39SF020A, 256 KB
probe_39sf020: id1 0xbf, id2 0xb6
SST39SF020A found at physical address: 0xfffc0000
Part is SST39SF020A
OK, only ENABLING flash write, but NOT FLASHING


and then, I type "./flash_rom /root/epia/romimage".                   

 "/root/epia/romimage" is a full path of romimage I had made.

I saw messges like below

Calibrating timer since microsleep sucks ... takes a second
Setting up microsecond timing loop
152M loops per second
OK, calibrated, now do the deed
Enabling flash write on VT8231...OK
Trying Am29F040B, 512 KB
probe_29f040b: id1 0x25, id2 0xa6
Trying At29C040A, 512 KB
probe_jedec: id1 0xbf, id2 0xb6
Trying Mx29f002, 256 KB
probe_29f002: id1 191, id2 182
Trying SST29EE020A, 256 KB
probe_jedec: id1 0xbf, id2 0xb6
Trying SST28SF040A, 512 KB
probe_28sf040: id1 0x25, id2 0xa6
Trying SST39SF020A, 256 KB
probe_39sf020: id1 0xbf, id2 0xb6
SST39SF020A found at physical address: 0xfffc0000
Part is SST39SF020A

I thought, romimage was burnt on my rom.........
I reboot the system, buf nothing was changed............

What's wrong with my procedure.....................

I did change original rom..............................

is it impossible to burn image on the original rom ?

If so, What should I do?

Please, give me your wise advice.....

_________________________________________________________________
???? ?? ??? ???? ???... MSN ??? ???   
http://vod.msn.co.kr  



From bari at onelabs.com  Wed Jul 23 13:54:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Wed Jul 23 13:54:01 2003
Subject: SC1200-BLDT (fwd)
In-Reply-To: <004b01c350d2$2d3e2eb0$0400a8c0@wsjkw>
References: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov> <004b01c350d2$2d3e2eb0$0400a8c0@wsjkw>
Message-ID: <3F1ECF76.6090909@onelabs.com>

Kyuwan Jung wrote:

>xpressLoader has different GDT table with linux kernel.
>If you fix this, lilo rom(?) may work.
>If you have BootOS source from N.S., porting only linuxbiosmain.c to boot rom
>works fine with vsa rom. That was my case.
>  
>
What did you get working with the VSA rom? Audio? Power managment?

-Bari




From schmadde at syscall.de  Wed Jul 23 14:20:00 2003
From: schmadde at syscall.de (Martin Schmachtel)
Date: Wed Jul 23 14:20:00 2003
Subject: DoC again
Message-ID: <20030723183246.GA21054@syscall.de>

These may sound like stupid questions to you, but please bear with me, I'm
new to this stuff and have not found anything definitive on google about 
it.

M-Systems apparently no longer produces the Disk-on-chip millenium with the 
part number MD-2800-D08. The successor MD-2802-D08 is supposed to be 
compatible , but I'd like to be a little more certain about it. Has anybody 
used the new chips with linuxbios successfully? 

Can any bios chip (in DIP-32 package) be replaced by a DoC? Or are there
any requirements not all boards fullfil, like not all needed address lines
are connected? More specifically, I'd like to try to get linuxbios working
on my Asus P2B, which I hope will not be too difficult since some support
for 440BX seems already present.

ciaole
schmadde



From rminnich at lanl.gov  Wed Jul 23 14:37:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 14:37:00 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <3F1EC3F2.4090304@nexpath.com>
Message-ID: <Pine.LNX.4.44.0307231249510.8161-100000@maxroach.lanl.gov>

On Wed, 23 Jul 2003, Steve Gehlbach wrote:

> Hmm... are you sure?  I tested this many times, and it was also reported 
> on the Xbox project as well.  Since Eric put in c_start.S, it has been 
> located in RAM < 1M (moved with the C code), but I don't know how v2 is 
> doing it, haven't looked at it.  The latest kernel I tested was 2.4.18 I 
> believe.  I have never gotten the kernel to boot with the gdt in flash, 
> where the addresses were just under 4G.  And it doesn't seem to have 
> anything to do with the RO nature of flash.

I'll try to find the code for you.

ron



From rminnich at lanl.gov  Wed Jul 23 14:38:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 14:38:01 2003
Subject: Can you help me?     I'm working on VIA-EPIA 
In-Reply-To: <BAY2-F153e5dCmjMAok0000f436@hotmail.com>
Message-ID: <Pine.LNX.4.44.0307231250350.8161-100000@maxroach.lanl.gov>

On Wed, 23 Jul 2003, gimyung han wrote:

> and then, I type "./flash_rom /root/epia/romimage".                   

it's annoying, but you have to say:
./flash_rom -w /root/epia/romimage.

That should do it.

ron



From stepan at suse.de  Wed Jul 23 15:15:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Jul 23 15:15:01 2003
Subject: freebios2 mod to reset code.
In-Reply-To: <3F1EC4BA.8080709@nexpath.com>; from steve@nexpath.com on Wed, Jul 23, 2003 at 10:24:10AM -0700
References: <3F1EADEC.40807@nexpath.com> <Pine.LNX.4.44.0307231007200.5540-100000@maxroach.lanl.gov> <20030723161938.GA7570@suse.de> <3F1EC4BA.8080709@nexpath.com>
Message-ID: <20030723212831.A458@suse.de>

* Steve Gehlbach <steve at nexpath.com> [030723 19:24]:
> >>>One caveat I discovered, I could never get Linux to boot with a gdt 
> >>>located higher than 1M.  So even if you put a linux compatible gdt high, 
> >>>it has to be moved to ram < 1M or linux hangs on boot.  Never figured 
> >>>out why (true for 2.4 anyway).
> 
> > Could this cause the hang with ADLO/rombios when booting grub on K8? 
> > Grub seems to hang right when it switches to pmode the first time.
> 
> For me, it happened every time, so I don't know what "first time" means. 
>   I guess I could have been doing something really stupid (I regret to 
> admit this is possible), but I do recall making a number of before and 
> after tests with a number of different memory addresses.

Ah, i should have been more exact. I traced the code and grub runs fine,
loads it's second stage boot loader, and then early in second stage, it
switches to protected mode. I think it switches back and forth a couple
of times (prot_to_real/real_to_prot), but I never get over the very
first switching that occurs at all. But it does hang every time.

Stefan

-- 
Architecture Team
    SuSE Linux AG


From oleg at usm.uni-muenchen.de  Wed Jul 23 16:06:01 2003
From: oleg at usm.uni-muenchen.de (Oleg Gusev)
Date: Wed Jul 23 16:06:01 2003
Subject: TigerMPX and s2466.
Message-ID: <200307232216.36501.oleg@usm.uni-muenchen.de>

 Is there any difference between these two mainboards, other
 than s2466-4M having 4Mbit flash ROM? I would like to test
 linuxbios, but it is not obvious which one to take.

 Oleg.



From han2004 at hotmail.com  Wed Jul 23 16:09:01 2003
From: han2004 at hotmail.com (gimyung han)
Date: Wed Jul 23 16:09:01 2003
Subject: about a serial port.....
Message-ID: <BAY2-F1476Pij5OMBLs00013353@hotmail.com>

I finally succeeded in burning linuxbois on rom, however, how can i see if 
i succeed or not?

On the HOWTO I should connect linuxbios computer with serial port.....

where should I connect it?

can anybody explain about it?


thanks for any helps

_________________________________________________________________
?? ?? ?? ??? ??? ?? ? ????. MSN ??/??   
http://www.msn.co.kr/stock/  



From oleg at usm.uni-muenchen.de  Wed Jul 23 16:27:00 2003
From: oleg at usm.uni-muenchen.de (Oleg Gusev)
Date: Wed Jul 23 16:27:00 2003
Subject: irq routing on TigerMPX.
Message-ID: <200307232237.23179.oleg@usm.uni-muenchen.de>

 It seems that linuxbios (and linux) uses the irq routing tables 
 dumped from the bios mptable.
 Are there any good reasons to reroute 9 pci/agp interrupts (2 64-bit slots
 on the first pci bus + 1  agp + 4 32-bit slots + builtin ethernet on the  
second pci bus) to 4 apic pins 16,17,18,19 when at least the pins 5,9,10,11
are not used at all ? Now i have 3 devices sharing
 pin 19, and 2 devices on 16,17 and 18. 
 Is this the intended use of io-apic ?

 Oleg.



From bgr at gw.linespeed.net  Wed Jul 23 16:38:00 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Wed Jul 23 16:38:00 2003
Subject: Can you help me?     I'm working on VIA-EPIA 
In-Reply-To: <BAY2-F153e5dCmjMAok0000f436@hotmail.com>
References: <BAY2-F153e5dCmjMAok0000f436@hotmail.com>
Message-ID: <Pine.LNX.4.53.0307231547330.8338@gw.linespeed.net>

try using the -w switch with the path to your rom

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Wed, 23 Jul 2003, gimyung han wrote:

> hi everyone !!
>
> I'm trying to burn romimage on the VIA-EPIA (VIA C3-800 Mhz, VT8231)
>
> I just succeeded in making romimage, and I cd into
> /freebios/util/flash_and_burn, and type make to compile.
>
> Finally, I got  excutive file "flash_rom".
>
> To test "flash_rom", I typed flash_rom without any parameter.
> and I saw following message
>
> Calibrating timer since microsleep sucks ... takes a second
> Setting up microsecond timing loop
> 153M loops per second
> OK, calibrated, now do the deed
> Enabling flash write on VT8231...tried to set 0x44 to 0x54 on VT8231 failed
> (WARNING ONLY)
> Trying Am29F040B, 512 KB
> probe_29f040b: id1 0x25, id2 0xa6
> Trying At29C040A, 512 KB
> probe_jedec: id1 0xbf, id2 0xb6
> Trying Mx29f002, 256 KB
> probe_29f002: id1 191, id2 182
> Trying SST29EE020A, 256 KB
> probe_jedec: id1 0xbf, id2 0xb6
> Trying SST28SF040A, 512 KB
> probe_28sf040: id1 0x25, id2 0xa6
> Trying SST39SF020A, 256 KB
> probe_39sf020: id1 0xbf, id2 0xb6
> SST39SF020A found at physical address: 0xfffc0000
> Part is SST39SF020A
> OK, only ENABLING flash write, but NOT FLASHING
>
>
> and then, I type "./flash_rom /root/epia/romimage".
>
>  "/root/epia/romimage" is a full path of romimage I had made.
>
> I saw messges like below
>
> Calibrating timer since microsleep sucks ... takes a second
> Setting up microsecond timing loop
> 152M loops per second
> OK, calibrated, now do the deed
> Enabling flash write on VT8231...OK
> Trying Am29F040B, 512 KB
> probe_29f040b: id1 0x25, id2 0xa6
> Trying At29C040A, 512 KB
> probe_jedec: id1 0xbf, id2 0xb6
> Trying Mx29f002, 256 KB
> probe_29f002: id1 191, id2 182
> Trying SST29EE020A, 256 KB
> probe_jedec: id1 0xbf, id2 0xb6
> Trying SST28SF040A, 512 KB
> probe_28sf040: id1 0x25, id2 0xa6
> Trying SST39SF020A, 256 KB
> probe_39sf020: id1 0xbf, id2 0xb6
> SST39SF020A found at physical address: 0xfffc0000
> Part is SST39SF020A
>
> I thought, romimage was burnt on my rom.........
> I reboot the system, buf nothing was changed............
>
> What's wrong with my procedure.....................
>
> I did change original rom..............................
>
> is it impossible to burn image on the original rom ?
>
> If so, What should I do?
>
> Please, give me your wise advice.....
>
> _________________________________________________________________
> ???? ?? ??? ???? ???... MSN ??? ???
> http://vod.msn.co.kr
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From agnew at cs.umd.edu  Wed Jul 23 18:00:01 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Wed Jul 23 18:00:01 2003
Subject: OT: job offer
In-Reply-To: <3F1ECEA6.3010806@onelabs.com>
Message-ID: <20030723182255.D90127-100000@www.missl.cs.umd.edu>

> Does he/she need to speak German? ;-)


Here's a translated version (done by my good friend Mike Van Opstal) :

> wenglor sensoric gmbh sucht:
Wenglor Sendoric GmbH is looking for:

> PC-HW/SW-Entwickler (Ingenieur/Techniker mit Berufserfahrung) zur
> Schaltungsentwicklung und Treiberprogrammierung.
PC-hardware/software developer (engineer/technical degree with career
experience) for circuit-development and driver-programming

> Anforderung: Fundierte Kenntnisse in der PC-Architektur
requirements: fundamental expertness in pc architecture

> Aufgabengebiet:
> Entwicklung von PC-basierten Hauptplatinen
> Schaltungen in der PC-Peripherie (z.B. PCI-Bus)
Field of application:
development on pc-based operating platforms
circuits in pc-peripherals (i.e., pci-bus)

> Mit ?ber 300 Mitarbeitern sind wir in Deutschland die Nr. 2
> im Bereich der optischen Sensorik.
with over 300 employees we're the number 2 company in optical sensors in
germany

> Informationen zur Firma und unserer Produktpalette
> entnehmen sie bitte unserer Homepage http://www.wenglor.de
for information on our company and product line take a look at their
webpage

> Weitere Informationen zu diesem Stellenangebot erhalten sie
> per Email: fre at wenglor.de
> oder telefonisch:  +49 (0)7542-5399-421
for more information on this job offer contact via email: -
or telephone: -

> ----wenglor(R)----sensors for your success----------



From rminnich at lanl.gov  Wed Jul 23 18:49:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 23 18:49:00 2003
Subject: new config tool, static and dynamic trees
Message-ID: <Pine.LNX.4.44.0307231656320.10370-100000@maxroach.lanl.gov>

Greg has implemented the static tree/dynamic tree code mentioned 
yesterday, and today it passed its first test with flying colors. 

Greg needed some ide setup done on the southbridge to make his IDE 
interface work. 

To effect the change, he had to have certain code execute at a certain 
pass in the platform startup. Turned out the code could execute once PCI 
was configured. 

His code in the mainboard Config.lb did not change:

southbridge winbond/w83c553 end

That's it. 

But the C code for the southbridge had the CONF_PASS_POST_PCI code added 
for configuration: 

void southbridge_init(struct chip *chip, enum chip_pass pass)
{

        struct southbridge_winbond_w83c553_config *conf = (struct 
		southbridge_winbond_w83c553_config *)chip->chip_info;

        switch (pass) {
        case CONF_PASS_POST_PCI:
                w83c553_init();
                break;

        default:
                /* nothing yet */
                break;
        }
}

The tail end of the code looks like this:

struct chip_control southbridge_winbond_w83c553_control = {
        enable: southbridge_init,
        name:   "Winbond W83C553"
};

This last bit is the chip_control structure, the "class definition" code 
for this part. 

So, in short, it was trivial to set up, and showed, at least to us, that
this is a good direction.

ron



From thomas at wehrspann.de  Wed Jul 23 18:58:01 2003
From: thomas at wehrspann.de (Thomas Wehrspann)
Date: Wed Jul 23 18:58:01 2003
Subject: DoC again
In-Reply-To: <20030723183246.GA21054@syscall.de>
References: <20030723183246.GA21054@syscall.de>
Message-ID: <200307240108.58919.thomas@wehrspann.de>

> M-Systems apparently no longer produces the Disk-on-chip millenium with the
> part number MD-2800-D08. The successor MD-2802-D08 is supposed to be
> compatible , but I'd like to be a little more certain about it. Has anybody
> used the new chips with linuxbios successfully?
>
I have no problems with it. I tried both, the old and the new one with the 
Elitegroup K7SEM, successfully.

greetings
Thomas


From Qwani at hanafos.com  Wed Jul 23 21:01:01 2003
From: Qwani at hanafos.com (Kyuwan Jung)
Date: Wed Jul 23 21:01:01 2003
Subject: SC1200-BLDT (fwd)
References: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov> <004b01c350d2$2d3e2eb0$0400a8c0@wsjkw> <3F1ECF76.6090909@onelabs.com>
Message-ID: <001101c3517e$ab278950$0400a8c0@wsjkw>

N.S provides ALSA and Framebuffer drivers for linux which use vsa rom.
As far as I know, there isn't power management driver from N.S yet.

> >xpressLoader has different GDT table with linux kernel.
> >If you fix this, lilo rom(?) may work.
> >If you have BootOS source from N.S., porting only linuxbiosmain.c to boot rom
> >works fine with vsa rom. That was my case.
> >  
> >
> What did you get working with the VSA rom? Audio? Power managment?
> 
> -Bari
 


From rogerxxmaillist at speakeasy.net  Wed Jul 23 21:09:00 2003
From: rogerxxmaillist at speakeasy.net (Roger)
Date: Wed Jul 23 21:09:00 2003
Subject: DoC again
In-Reply-To: <20030723183246.GA21054@syscall.de>
References: <20030723183246.GA21054@syscall.de>
Message-ID: <1059009443.22392.28.camel@localhost3.localdomain>

On Wed, 2003-07-23 at 11:32, Martin Schmachtel wrote:
> These may sound like stupid questions to you, but please bear with me, I'm
> new to this stuff and have not found anything definitive on google about 
> it.

>From what I've seen, only the elite have dabbled into DOC's ;-)
You can find other info about MTD Developement and the DOC modules
within the MTD Mailling list.  Matter of fact, the developer for MTD has
the DOC's on his desktop.  DOC's should work and the only problems I
have seen tend to be chipset related.

> 
> M-Systems apparently no longer produces the Disk-on-chip millenium with the 
> part number MD-2800-D08. The successor MD-2802-D08 is supposed to be 
> compatible , but I'd like to be a little more certain about it. Has anybody 
> used the new chips with linuxbios successfully? 
> 
> Can any bios chip (in DIP-32 package) be replaced by a DoC? Or are there
> any requirements not all boards fullfil, like not all needed address lines
> are connected? More specifically, I'd like to try to get linuxbios working
> on my Asus P2B, which I hope will not be too difficult since some support
> for 440BX seems already present.

On my Tyan Tiger 1832DL (440BX) & Procomp B860/863 (440BX) motherboards,
I need to "unshadow" the bios chip to be able to have mtd (doc2001.o)
modules to see this chip.  

Basically, I aquired the openbios/devbios code and commented some lines
of code to prevent unshadowing after unloading the bios.o module -- if
you want this info, i can resend it.  It has already been posted once on
linuxbios & mtd maillinglists

I'm not sure if other 440bx boards have this problem (such as your
motherboard).  I've heard some 440bx motherboards not having this
"shadow" problem.

I have two of the MD2802-D08 chips and they work great on both
motherboards.  If you're iffy about the DOC's, you could always order a
couple of plan flash 32 pin dips.  I believe most of the later 440bx SMP
motherboards utilize a 256K flash.

If you want to use the extra Amtel flash dips for flashing them with
your manufacturer's compiled bios, you will need to use a chip size
equivalent to manufacturer's flash.bin file size (either 128K or 256K). 
(To check your flash size by doing a "ls -al" on your manufacturers
flash.bin file.  It will either be 128K or 256K.)

DOC Millennium 8MB Module
EMJ America Inc
http://www.emj.com/
Part No. 1MML8MB
(Tested on both of my 440BX motherboards.  Have not been able to boot
linuxbios -- due to doc ipl for 440bx in linuxbios?)

32 Pin w/ handle ARIES Zif socket (~$14 ea)
www.mouser.com
Stock No. 535-32-6554-11
Bin No. 94-68G1

DIP-32 256KX8 120NS Atmel Flash Memory (~$4 ea)
Stock No. 556-AT29C02012PC
Bin No. F0-59J8
(I have verified this chip on the Procomp B860/B863 motherboard but not
my Tyan.. it should work though)

Mouser, EMJ, Digikey all have online catalogs (in pdf format) and can be
easily searched via www.google.com.
-- 

Roger
http://www.eskimo.com/~roger/index.html



From rogerxxmaillist at speakeasy.net  Wed Jul 23 21:32:00 2003
From: rogerxxmaillist at speakeasy.net (Roger)
Date: Wed Jul 23 21:32:00 2003
Subject: about a serial port.....
In-Reply-To: <BAY2-F1476Pij5OMBLs00013353@hotmail.com>
References: <BAY2-F1476Pij5OMBLs00013353@hotmail.com>
Message-ID: <1059010861.22392.53.camel@localhost3.localdomain>

First, you need a 9 pin serial crossover cable to hook-up the two
computers.  Typically you'll find a 9 pin serial cable at Radio Shack
and with an optional crossover adapter that plugs into one end of the
cable.

I prefer kermit (instead of minicom -- kermit acts more like a common
shell)

Set /dev/ttyS? to your specific port number.
baud_rate can be set to whatever value you want. (This value is limited
by serial cable length.)

* On the box being used to monitor the target box *
~/.kermrc
set modem type none
set line /dev/ttyS0
set speed 115200
set flow rts/cts
set carrier-watch off

Ensure that baud_base is set to match the remote target box's baud_base
(can be any other supported baud_rate ie 9600):
roger at remote # setserial -a /dev/ttyS0

baud_base <> match the remote target box's baud_rate?
roger at remote # setserial ttyS0 baud_base 115200


* On the target box *

To test that it does work with your working kernel do something like the
following:

/etc/lilo.conf
image = /boot/blah
	label = blah
	root = /dev/hda1
	append = "console=ttyS1,115200"
This will spit-out the dmesg on boot to the remote box.  This is what
you basically want to occur with Linuxbios.  This config option is found
within the config file when building the actual linuxbios image file for
burning to a mtd device (ie flash, DOC, etc)

Or, add to /etc/inittab:
S1:12345:respawn:/sbin/agetty ttyS1 -L 115200 vt102
Restart inetd and this inittab addition will only display the later part
of the boot process and will give you a login shell via kermit/minicom.


Ok. After making sure that your port numbers and baudrates are correct,
fire up kermit on the remote box.  Reboot or restart initd depending on
which test method you decide to choose.


On Wed, 2003-07-23 at 13:22, gimyung han wrote:
> I finally succeeded in burning linuxbois on rom, however, how can i see if 
> i succeed or not?
> 
> On the HOWTO I should connect linuxbios computer with serial port.....
> 
> where should I connect it?
> 
> can anybody explain about it?
> 
> 
> thanks for any helps
> 
> _________________________________________________________________
> ?? ?? ?? ??? ??? ?? ? ????. MSN ??/??   
> http://www.msn.co.kr/stock/  
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
-- 

Roger
http://www.eskimo.com/~roger/index.html



From ollie at sis.com.tw  Wed Jul 23 22:12:00 2003
From: ollie at sis.com.tw (ollie lho)
Date: Wed Jul 23 22:12:00 2003
Subject: irq routing on TigerMPX.
In-Reply-To: <200307232237.23179.oleg@usm.uni-muenchen.de>
References: <200307232237.23179.oleg@usm.uni-muenchen.de>
Message-ID: <1059012451.3345.152.camel@ollie>

On Thu, 2003-07-24 at 04:37, Oleg Gusev wrote:
>  It seems that linuxbios (and linux) uses the irq routing tables 
>  dumped from the bios mptable.
>  Are there any good reasons to reroute 9 pci/agp interrupts (2 64-bit slots
>  on the first pci bus + 1  agp + 4 32-bit slots + builtin ethernet on the  
> second pci bus) to 4 apic pins 16,17,18,19 when at least the pins 5,9,10,11
> are not used at all ? Now i have 3 devices sharing
>  pin 19, and 2 devices on 16,17 and 18. 
>  Is this the intended use of io-apic ?
> 

Well, PCI spec only defines 4 IRQ Lines (A,B,C,D) and these lines are 
supposed to be shareable. These 4 lines are connected to 4 IRQ pins on
the apic. As a result, even apic has 24 irq pins, we allocate 4 pins
for PCI devices.
-- 
ollie lho <ollie at sis.com.tw>



From ijpraveen1 at yahoo.com  Wed Jul 23 22:40:01 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Wed Jul 23 22:40:01 2003
Subject: Loading OS from Flash ROM!
In-Reply-To: <Pine.LNX.4.44.0307222319051.1352-100000@maxroach.lanl.gov>
Message-ID: <20030724025340.36349.qmail@web41702.mail.yahoo.com>

Hi,
 
      Sorry if my question sounds stupid. How would
LinuxBIOS know that it has to boot from Flash memory.
Is something has to be mentioned in the nano.config
file?

     
     --- ron minnich <rminnich at lanl.gov> wrote:
> On Tue, 22 Jul 2003, John Praveen wrote:
> 
> >  
> >                      It is a soldered one.
> 
> So is the question how you program it? Is there a
> recovery jumper for when
> you burn a bad BIOS? Can you send me the URL for the
> board?
> 
> ron
> 

__________________________________
Do you Yahoo!?
Yahoo! SiteBuilder - Free, easy-to-use web site design software
http://sitebuilder.yahoo.com


From salmon.chen at msa.hinet.net  Wed Jul 23 23:28:00 2003
From: salmon.chen at msa.hinet.net (Tien)
Date: Wed Jul 23 23:28:00 2003
Subject: supermicro p4dc6p complier problem
References: <Pine.LNX.4.44.0307230900250.5540-100000@maxroach.lanl.gov>
Message-ID: <004e01c35195$7b09c280$160aa8c0@D29092.findquick.com>

Hi Ron,
             Nice to meet you and get your respond . I am a junior on
LinuxBIOS and want to start on p4dc6p.I can't complier it and get a message
that "No rule to make target
'/root/freebios/src/arch/i386/smp/secondary.inc'.I can't find secondary.inc
in latest version source code.Could you help me to complier it or tell me
which file I need to modify ? Thanks.


Best regards,
Tien


----- Original Message -----
From: "ron minnich" <rminnich at lanl.gov>
To: "Tien" <salmon.chen at msa.hinet.net>
Cc: <linuxbios at clustermatic.org>
Sent: Wednesday, July 23, 2003 8:00 AM
Subject: Re: supermicro p4dc6p complier problem


On Wed, 23 Jul 2003, Tien wrote:

>            Does anyone can complier supermicro P4DC6P with latest version
> source code?

I think that works.

ron





From rogerxxmaillist at speakeasy.net  Thu Jul 24 00:24:01 2003
From: rogerxxmaillist at speakeasy.net (Roger)
Date: Thu Jul 24 00:24:01 2003
Subject: about a serial port.....
In-Reply-To: <1059010861.22392.53.camel@localhost3.localdomain>
References: <BAY2-F1476Pij5OMBLs00013353@hotmail.com>
	 <1059010861.22392.53.camel@localhost3.localdomain>
Message-ID: <1059021025.4628.16.camel@localhost3.localdomain>

On Wed, 2003-07-23 at 18:41, Roger wrote:

> Or, add to /etc/inittab:
> S1:12345:respawn:/sbin/agetty ttyS1 -L 115200 vt102
> Restart inetd and this inittab addition will only display the later part
> of the boot process and will give you a login shell via kermit/minicom.

Inclusion here. To have the /etc/inittab file to be re-read:
# telinit q

(i also recall doing a "# killall agetty" for some reason)

The entire specifics of this can also be found in the "Remote Serial
Console HowTo"

> Ok. After making sure that your port numbers and baudrates are
correct, 
> fire up kermit on the remote box.  Reboot or restart initd depending on
> which test method you decide to choose.

After doing:
# kermit

type "connect" (most times, you'll also need to type "RETURN" to get
the shell to display the login prompt).  Type "ctrl \ c" & the "exit".


well, anyways, half of my post here is OT but should help-out.  I'm
also noticing I'll probably confuse any readers. oh well.

-- 

Roger
http://www.eskimo.com/~roger/index.html



From ts1 at cma.co.jp  Thu Jul 24 01:15:01 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Thu Jul 24 01:15:01 2003
Subject: Can you help me?     I'm working on VIA-EPIA
In-Reply-To: <Pine.LNX.4.44.0307231250350.8161-100000@maxroach.lanl.gov>
References: <BAY2-F153e5dCmjMAok0000f436@hotmail.com> <Pine.LNX.4.44.0307231250350.8161-100000@maxroach.lanl.gov>
Message-ID: <20030724052839.GA1232@cma.co.jp>

On Wed, Jul 23, 2003 at 12:51:00PM -0600, ron minnich wrote:
> On Wed, 23 Jul 2003, gimyung han wrote:
> 
> > and then, I type "./flash_rom /root/epia/romimage".                   
> 
> it's annoying, but you have to say:
> ./flash_rom -w /root/epia/romimage.

I thought this was a bug made by me and sent a patch to Ron some weeks ago,
but it seems it is not committed.

--
Takeshi


From stepan at suse.de  Thu Jul 24 05:18:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 24 05:18:01 2003
Subject: SC1200-BLDT (fwd)
In-Reply-To: <001101c3517e$ab278950$0400a8c0@wsjkw>
References: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov> <004b01c350d2$2d3e2eb0$0400a8c0@wsjkw> <3F1ECF76.6090909@onelabs.com> <001101c3517e$ab278950$0400a8c0@wsjkw>
Message-ID: <20030724093052.GA1623@suse.de>

* Kyuwan Jung <Qwani at hanafos.com> [030724 02:58]:
> N.S provides ALSA and Framebuffer drivers for linux which use vsa rom.
> As far as I know, there isn't power management driver from N.S yet.

I've seen some native powermanagement patch for linux on geode
somewhere, but it don't seem to do much.
Does the framebuffer stuff also work with 2.5? Is it still that huuuge
bunch of code coming in it's own kernel tree instead of a patch?

Stefan




From ijpraveen1 at yahoo.com  Thu Jul 24 07:50:01 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Thu Jul 24 07:50:01 2003
Subject: Flash memory?
Message-ID: <20030724120335.71999.qmail@web41709.mail.yahoo.com>

Hi 

          I read the document
www.linux-magazine.com/issue/28/LinuxBIOS.pdf. It
states that DiskOnChip is required for the linuxBIOS.
The How-to doc in linuxbios tree too is based on
building it for DiskOnChip. Thats what i was confused
whether my Flash device would be supported or not? 

__________________________________
Do you Yahoo!?
Yahoo! SiteBuilder - Free, easy-to-use web site design software
http://sitebuilder.yahoo.com


From Qwani at hanafos.com  Thu Jul 24 08:02:00 2003
From: Qwani at hanafos.com (Kyuwan Jung)
Date: Thu Jul 24 08:02:00 2003
Subject: SC1200-BLDT (fwd)
References: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov> <004b01c350d2$2d3e2eb0$0400a8c0@wsjkw> <3F1ECF76.6090909@onelabs.com> <001101c3517e$ab278950$0400a8c0@wsjkw> <20030724093052.GA1623@suse.de>
Message-ID: <00c201c351db$e18fef20$0400a8c0@wsjkw>

thanks for notice, Stefan.
NS framebuffer was for early version of 2.4, however I've used it with 2.4.19
after manual patch on config.in and makefile.
And it is true so far that they have their own source tree. Although 2.5 seems to 
have much support for Geode, i'm not sure of Geode framebuffer yet.
I plan to upgrade kernel to 2.5 and I will let you know if it works ;-)

kyuwan

> * Kyuwan Jung <Qwani at hanafos.com> [030724 02:58]:
> > N.S provides ALSA and Framebuffer drivers for linux which use vsa rom.
> > As far as I know, there isn't power management driver from N.S yet.
> 
> I've seen some native powermanagement patch for linux on geode
> somewhere, but it don't seem to do much.
> Does the framebuffer stuff also work with 2.5? Is it still that huuuge
> bunch of code coming in it's own kernel tree instead of a patch?
> 
> Stefan


From stepan at suse.de  Thu Jul 24 08:14:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 24 08:14:00 2003
Subject: SC1200-BLDT (fwd)
In-Reply-To: <00c201c351db$e18fef20$0400a8c0@wsjkw>
References: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov> <004b01c350d2$2d3e2eb0$0400a8c0@wsjkw> <3F1ECF76.6090909@onelabs.com> <001101c3517e$ab278950$0400a8c0@wsjkw> <20030724093052.GA1623@suse.de> <00c201c351db$e18fef20$0400a8c0@wsjkw>
Message-ID: <20030724121937.GA2212@suse.de>

* Kyuwan Jung <Qwani at hanafos.com> [030724 14:05]:
> thanks for notice, Stefan.
> NS framebuffer was for early version of 2.4, however I've used it with 2.4.19
> after manual patch on config.in and makefile.
> And it is true so far that they have their own source tree. Although 2.5 seems to 
> have much support for Geode, i'm not sure of Geode framebuffer yet.
> I plan to upgrade kernel to 2.5 and I will let you know if it works ;-)

Do you have a patch for 2.4.19?
This might save a lot of people a lot of work..

Stefan




From stepan at suse.de  Thu Jul 24 09:42:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 24 09:42:00 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <Pine.LNX.4.44.0307231656320.10370-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307231656320.10370-100000@maxroach.lanl.gov>
Message-ID: <20030724135415.GA2746@suse.de>

* ron minnich <rminnich at lanl.gov> [030724 01:02]:
> Greg has implemented the static tree/dynamic tree code mentioned 
> yesterday, and today it passed its first test with flying colors. 

I am still fighting this, since it broke NLBConfig in a way that is
probably not worth fixing (it's missing the static_root completely,
and we might not want to keep that in a generated file as well as in
the config file):
[..]
linuxbios_c.o(.text+0x203e): In function `hardwaremain':
: undefined reference to `static_root'
[...]

The new config method fails, but I can't seem to find the wrong line in
the config file.

~/LinuxBIOS/freebios2/targets> ./buildtarget arima/hdama/
Configuring TARGET hdama
Will place Makefile, crt0.S, etc. in arima/hdama/hdama
Configuring ROMIMAGE fallback
Configuring DIR /config/Config.lb
Configuring DIR /lib/Config.lb
Configuring DIR /console/Config.lb
Configuring DIR /stream/Config.lb
Configuring DIR /devices/Config.lb
Configuring DIR /pc80/Config.lb
Configuring DIR /boot/Config.lb
Configuring PART mainboard, path arima/hdama
Configuring PART arch, path i386
Adding init file: config/crt0.base
Configuring DIR lib/Config.lb
Configuring DIR boot/Config.lb
Configuring DIR smp/Config.lb
End PART arch
WARNING: Option CONFIG_SMP using default value 0
Configuring PART northbridge, path amd/amdk8
End PART northbridge
Configuring PART southbridge, path amd/amd8111
End PART southbridge
Configuring PART southbridge, path amd/amd8131
End PART southbridge
Configuring PART superio, path NSC/pc87360
Trying to find one of '=' on line 153:
>  end
>  ^
List of nearby tokens: 
  (@3368)  SOUTHBRIDGE  =  'southbridge'
  (@3380)  PATH  =  'amd/amd8111'
  (@3392)  END  =  'end'
  (@3396)  SOUTHBRIDGE  =  'southbridge'
  (@3408)  PATH  =  'amd/amd8131'
  (@3420)  END  =  'end'
  (@3466)  SUPERIO  =  'superio'
  (@3474)  PATH  =  'NSC/pc87360'
  (@3487)  REGISTER  =  'register'
  (@3496)  STR  =  '".com1={1}, .lpt=1"'
===> ERROR: Could not parse file
arima/hdama/Config.lb:0
mainboard/arima/hdama/Config.lb:0




Any idea?

Thanks,
   Stefan



From bgr at gw.linespeed.net  Thu Jul 24 09:49:00 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Thu Jul 24 09:49:00 2003
Subject: SC1200-BLDT (fwd)
In-Reply-To: <20030724121937.GA2212@suse.de>
References: <Pine.LNX.4.44.0307222121090.956-100000@maxroach.lanl.gov>
 <004b01c350d2$2d3e2eb0$0400a8c0@wsjkw> <3F1ECF76.6090909@onelabs.com>
 <001101c3517e$ab278950$0400a8c0@wsjkw> <20030724093052.GA1623@suse.de>
 <00c201c351db$e18fef20$0400a8c0@wsjkw> <20030724121937.GA2212@suse.de>
Message-ID: <Pine.LNX.4.53.0307240842550.5087@gw.linespeed.net>

The nsc-kfb 2.7.7 patch/installer works on 2.4.19 and 2.4.20.  Same with
both the OSS and Alsa audio drivers.  Same with the udma patch with minor
modifications, though it does not work at 66mhz.  their v4l driver hardly
works, though I have only been trying to use it with the framebuffer as
the output device.  I eagerly await not using their hardware anymore.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Thu, 24 Jul 2003, Stefan Reinauer wrote:

> * Kyuwan Jung <Qwani at hanafos.com> [030724 14:05]:
> > thanks for notice, Stefan.
> > NS framebuffer was for early version of 2.4, however I've used it with 2.4.19
> > after manual patch on config.in and makefile.
> > And it is true so far that they have their own source tree. Although 2.5 seems to
> > have much support for Geode, i'm not sure of Geode framebuffer yet.
> > I plan to upgrade kernel to 2.5 and I will let you know if it works ;-)
>
> Do you have a patch for 2.4.19?
> This might save a lot of people a lot of work..
>
> Stefan
>
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From gwatson at lanl.gov  Thu Jul 24 10:03:01 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Thu Jul 24 10:03:01 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <20030724135415.GA2746@suse.de>
References: <Pine.LNX.4.44.0307231656320.10370-100000@maxroach.lanl.gov>
 <20030724135415.GA2746@suse.de>
Message-ID: <p06001a00bb45994dee6e@[10.0.1.2]>

Stefan,

Sorry about that. I'll #define this better so that it's not required 
with the old configuration system.

The 'register' directive has changed slightly, but hasn't been 
updated in the tree. I've checked in the new version now.

Greg

At 3:54 PM +0200 24/7/03, Stefan Reinauer wrote:
>* ron minnich <rminnich at lanl.gov> [030724 01:02]:
>>  Greg has implemented the static tree/dynamic tree code mentioned
>>  yesterday, and today it passed its first test with flying colors.
>
>I am still fighting this, since it broke NLBConfig in a way that is
>probably not worth fixing (it's missing the static_root completely,
>and we might not want to keep that in a generated file as well as in
>the config file):
>[..]
>linuxbios_c.o(.text+0x203e): In function `hardwaremain':
>: undefined reference to `static_root'
>[...]
>
>The new config method fails, but I can't seem to find the wrong line in
>the config file.
>
>~/LinuxBIOS/freebios2/targets> ./buildtarget arima/hdama/
>Configuring TARGET hdama
>Will place Makefile, crt0.S, etc. in arima/hdama/hdama
>Configuring ROMIMAGE fallback
>Configuring DIR /config/Config.lb
>Configuring DIR /lib/Config.lb
>Configuring DIR /console/Config.lb
>Configuring DIR /stream/Config.lb
>Configuring DIR /devices/Config.lb
>Configuring DIR /pc80/Config.lb
>Configuring DIR /boot/Config.lb
>Configuring PART mainboard, path arima/hdama
>Configuring PART arch, path i386
>Adding init file: config/crt0.base
>Configuring DIR lib/Config.lb
>Configuring DIR boot/Config.lb
>Configuring DIR smp/Config.lb
>End PART arch
>WARNING: Option CONFIG_SMP using default value 0
>Configuring PART northbridge, path amd/amdk8
>End PART northbridge
>Configuring PART southbridge, path amd/amd8111
>End PART southbridge
>Configuring PART southbridge, path amd/amd8131
>End PART southbridge
>Configuring PART superio, path NSC/pc87360
>Trying to find one of '=' on line 153:
>>   end
>>   ^
>List of nearby tokens:
>   (@3368)  SOUTHBRIDGE  =  'southbridge'
>   (@3380)  PATH  =  'amd/amd8111'
>   (@3392)  END  =  'end'
>   (@3396)  SOUTHBRIDGE  =  'southbridge'
>   (@3408)  PATH  =  'amd/amd8131'
>   (@3420)  END  =  'end'
>   (@3466)  SUPERIO  =  'superio'
>   (@3474)  PATH  =  'NSC/pc87360'
>   (@3487)  REGISTER  =  'register'
>   (@3496)  STR  =  '".com1={1}, .lpt=1"'
>===> ERROR: Could not parse file
>arima/hdama/Config.lb:0
>mainboard/arima/hdama/Config.lb:0
>
>
>
>
>Any idea?
>
>Thanks,
>    Stefan
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Thu Jul 24 10:25:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 10:25:01 2003
Subject: Can you help me?     I'm working on VIA-EPIA
In-Reply-To: <20030724052839.GA1232@cma.co.jp>
Message-ID: <Pine.LNX.4.44.0307240838380.17116-100000@maxroach.lanl.gov>

On Thu, 24 Jul 2003, SONE Takeshi wrote:

> On Wed, Jul 23, 2003 at 12:51:00PM -0600, ron minnich wrote:
> > On Wed, 23 Jul 2003, gimyung han wrote:
> > 
> > > and then, I type "./flash_rom /root/epia/romimage".                   
> > 
> > it's annoying, but you have to say:
> > ./flash_rom -w /root/epia/romimage.
> 
> I thought this was a bug made by me and sent a patch to Ron some weeks ago,
> but it seems it is not committed.

resend patch?

ron



From rminnich at lanl.gov  Thu Jul 24 10:31:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 10:31:01 2003
Subject: Flash memory?
In-Reply-To: <20030724120335.71999.qmail@web41709.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0307240842520.17116-100000@maxroach.lanl.gov>

On Thu, 24 Jul 2003, John Praveen wrote:

>           I read the document
> www.linux-magazine.com/issue/28/LinuxBIOS.pdf. It
> states that DiskOnChip is required for the linuxBIOS.

oh, that's an error. It is not required. There has to be something we said 
that implies that, as people keep asking that question. 

ron



From rminnich at lanl.gov  Thu Jul 24 10:37:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 10:37:00 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <20030724135415.GA2746@suse.de>
Message-ID: <Pine.LNX.4.44.0307240844200.17116-100000@maxroach.lanl.gov>

On Thu, 24 Jul 2003, Stefan Reinauer wrote:

> I am still fighting this, since it broke NLBConfig in a way that is
> probably not worth fixing (it's missing the static_root completely,
> and we might not want to keep that in a generated file as well as in
> the config file):

our mistake. We need to get greg to #ifdef that for now until we all cut 
over.

> The new config method fails, but I can't seem to find the wrong line in
> the config file.
> 
> ~/LinuxBIOS/freebios2/targets> ./buildtarget arima/hdama/
> Configuring TARGET hdama
> Will place Makefile, crt0.S, etc. in arima/hdama/hdama
> Configuring ROMIMAGE fallback
> Configuring DIR /config/Config.lb
> Configuring DIR /lib/Config.lb
> Configuring DIR /console/Config.lb
> Configuring DIR /stream/Config.lb
> Configuring DIR /devices/Config.lb
> Configuring DIR /pc80/Config.lb
> Configuring DIR /boot/Config.lb
> Configuring PART mainboard, path arima/hdama
> Configuring PART arch, path i386
> Adding init file: config/crt0.base
> Configuring DIR lib/Config.lb
> Configuring DIR boot/Config.lb
> Configuring DIR smp/Config.lb
> End PART arch
> WARNING: Option CONFIG_SMP using default value 0
> Configuring PART northbridge, path amd/amdk8
> End PART northbridge
> Configuring PART southbridge, path amd/amd8111
> End PART southbridge
> Configuring PART southbridge, path amd/amd8131
> End PART southbridge
> Configuring PART superio, path NSC/pc87360
> Trying to find one of '=' on line 153:
> >  end
> >  ^

cvs update, I fixed this yesterday.

sorry, this was a tweak to some of the initialization code.

I've got one more tweak to make today, but you should be able to build a 
working image. The problem I'm having now is that the 16 MB DRAM fill is 
so slow, any idea what would do this?


thanks

ron



From stepan at suse.de  Thu Jul 24 10:43:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 24 10:43:01 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <Pine.LNX.4.44.0307240844200.17116-100000@maxroach.lanl.gov>
References: <20030724135415.GA2746@suse.de> <Pine.LNX.4.44.0307240844200.17116-100000@maxroach.lanl.gov>
Message-ID: <20030724145037.GA4952@suse.de>

* ron minnich <rminnich at lanl.gov> [030724 16:46]:
> cvs update, I fixed this yesterday.
> 
> sorry, this was a tweak to some of the initialization code.
 
ah.. it works now.. thanks.

> I've got one more tweak to make today, but you should be able to build a 
> working image. The problem I'm having now is that the 16 MB DRAM fill is 
> so slow, any idea what would do this?

hm 2nd level cache disabled?
 


   Stefan




From rminnich at lanl.gov  Thu Jul 24 10:48:53 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 10:48:53 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <20030724145037.GA4952@suse.de>
Message-ID: <Pine.LNX.4.44.0307240852510.17116-100000@maxroach.lanl.gov>

On Thu, 24 Jul 2003, Stefan Reinauer wrote:

> 
> hm 2nd level cache disabled?

yeah, but why? I thought I had copied the old config setup pretty well. Do 
you see anything?

Next bit is get SMP in there.

ron




From rminnich at lanl.gov  Thu Jul 24 10:55:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 10:55:01 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <20030724145037.GA4952@suse.de>
Message-ID: <Pine.LNX.4.44.0307240904320.17116-100000@maxroach.lanl.gov>

Stefan, in a few minutes I'll be committing a simple change that greatly 
reduces the size of targets/arima/hdama/Config.lb. 

I have tested this and it works fine, save for the slow memory test (which 
may be L2 cache, but may be who knows ... TOM again?)

ron



From rminnich at lanl.gov  Thu Jul 24 11:01:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 11:01:00 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <Pine.LNX.4.44.0307240852510.17116-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.44.0307240912330.17116-100000@maxroach.lanl.gov>

so, stefan, it is working for you? HMM. Just stopped working for me :)

ron



From stepan at suse.de  Thu Jul 24 11:15:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 24 11:15:01 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <Pine.LNX.4.44.0307240912330.17116-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307240852510.17116-100000@maxroach.lanl.gov> <Pine.LNX.4.44.0307240912330.17116-100000@maxroach.lanl.gov>
Message-ID: <20030724152832.GA6544@suse.de>

* ron minnich <rminnich at lanl.gov> [030724 17:12]:
> 
> so, stefan, it is working for you? HMM. Just stopped working for me :)

No, it seems there is some flaw in memory setup of the second CPU. This
is stil built with the old config. All the memory gets detected, but
LinuxBIOS just restarts right after the timeout at:
Boot from (N)etwork (D)isk (F)loppy or from (L)ocal? 

Stefan




From rminnich at lanl.gov  Thu Jul 24 11:21:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 11:21:00 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <20030724152832.GA6544@suse.de>
Message-ID: <Pine.LNX.4.44.0307240932540.17116-100000@maxroach.lanl.gov>

On Thu, 24 Jul 2003, Stefan Reinauer wrote:

> No, it seems there is some flaw in memory setup of the second CPU. This
> is stil built with the old config. All the memory gets detected, but
> LinuxBIOS just restarts right after the timeout at:
> Boot from (N)etwork (D)isk (F)loppy or from (L)ocal? 

you lost me. This is happening with the old or new config?

Does it all work correctly with the old config?

ron



From stepan at suse.de  Thu Jul 24 11:27:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 24 11:27:01 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <Pine.LNX.4.44.0307240904320.17116-100000@maxroach.lanl.gov>
References: <20030724145037.GA4952@suse.de> <Pine.LNX.4.44.0307240904320.17116-100000@maxroach.lanl.gov>
Message-ID: <20030724151642.GB5490@suse.de>

* ron minnich <rminnich at lanl.gov> [030724 17:05]:
> 
> Stefan, in a few minutes I'll be committing a simple change that greatly 
> reduces the size of targets/arima/hdama/Config.lb. 
> 
> I have tested this and it works fine, save for the slow memory test (which 
> may be L2 cache, but may be who knows ... TOM again?)

Hm. Do you have the second cpu's memory controller activated? This seems
to take forever here as well, since it tests at 2G but the machine has 1

Stefan



From stepan at suse.de  Thu Jul 24 11:44:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 24 11:44:00 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <Pine.LNX.4.44.0307240932540.17116-100000@maxroach.lanl.gov>
References: <20030724152832.GA6544@suse.de> <Pine.LNX.4.44.0307240932540.17116-100000@maxroach.lanl.gov>
Message-ID: <20030724155724.GA6560@suse.de>

* ron minnich <rminnich at lanl.gov> [030724 17:33]:
> you lost me. This is happening with the old or new config?
 
with the current latest CVS I get the following error: 

Configuring TARGET hdama
Will place Makefile, crt0.S, etc. in arima/hdama/hdama
===> ERROR: Attempt to set nonexistent option MAXIMUM_CONSOLE_LOGLEVEL
arima/hdama/Config.lb:0

I tried building an image with the prior version, but I assumed this
would build ok if I adopt the targets/arima/hdama/Config.lb file to
use my payload. I will try switching to new config method completely
when it builds with above config file again.

> Does it all work correctly with the old config?

as long as you don't initialize ram on the second cpu with the arima
hdama, yes. 

Stefan




From rminnich at lanl.gov  Thu Jul 24 11:58:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 11:58:01 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <20030724155724.GA6560@suse.de>
Message-ID: <Pine.LNX.4.44.0307241011190.17116-100000@maxroach.lanl.gov>

On Thu, 24 Jul 2003, Stefan Reinauer wrote:

> Configuring TARGET hdama
> Will place Makefile, crt0.S, etc. in arima/hdama/hdama
> ===> ERROR: Attempt to set nonexistent option MAXIMUM_CONSOLE_LOGLEVEL
> arima/hdama/Config.lb:0

put this at the top of Config.lb

uses MAXIMUM_CONSOLE_LOGLEVEL

This is a new restriction.

ron



From gwatson at lanl.gov  Thu Jul 24 12:38:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Thu Jul 24 12:38:00 2003
Subject: AMD package/part numbers
Message-ID: <p06001a06bb45bea21675@[10.0.1.2]>

Any idea how to translate an AMD package number to an AMD part number?

I have a flash part that is marked D323GB90V1 but I can't find 
anything on the AMD site that helps translate this to a part number, 
short of reading every data sheet.

Thanks,

Greg


From ts1 at tsn.or.jp  Thu Jul 24 13:12:00 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Thu Jul 24 13:12:00 2003
Subject: Can you help me?     I'm working on VIA-EPIA
In-Reply-To: <Pine.LNX.4.44.0307240838380.17116-100000@maxroach.lanl.gov>
References: <20030724052839.GA1232@cma.co.jp> <Pine.LNX.4.44.0307240838380.17116-100000@maxroach.lanl.gov>
Message-ID: <20030724172510.GA21107@tsn.or.jp>

On Thu, Jul 24, 2003 at 08:38:44AM -0600, ron minnich wrote:
> > I thought this was a bug made by me and sent a patch to Ron some weeks ago,
> > but it seems it is not committed.
> 
> resend patch?


Attached is CVS diff against my current tree.
Beside 2 bug fixes (both by me), this includes some enhancements.
If you can't accept these, I will make a patch consists of only bug
fixes.

* Fixed to do write operation when no option but a filename is supplied
* Fixed wrong error report when enabling flash on vt8231
* Changed to report progress every 4KB instead of byte by byte on some chips
(significantly speeds up flashing those chips)
* Added -c option: only specified Flash ROM is probed; this saves
BIOS Savior users from accidentially overwrite the "known good" BIOS
if he/she forgot to toggle the switch.


Index: flash_rom.c
===================================================================
RCS file: /cvsroot/freebios/freebios/util/flash_and_burn/flash_rom.c,v
retrieving revision 1.21
diff -u -r1.21 flash_rom.c
--- flash_rom.c	22 Jul 2003 10:12:08 -0000	1.21
+++ flash_rom.c	24 Jul 2003 17:02:07 -0000
@@ -33,6 +33,7 @@
 #include <unistd.h>
 #include <stdio.h>
 #include <pci/pci.h>
+#include <string.h>
 
 #include "flash.h"
 #include "jedec.h"
@@ -69,6 +70,8 @@
     {NULL,}
 };
 
+char *chip_to_probe = NULL;
+
 int enable_flash_sis630 (struct pci_dev *dev, char *name)
 {
     char b;
@@ -127,7 +130,6 @@
 enable_flash_e7500(struct pci_dev *dev, char *name) {
   /* register 4e.b gets or'ed with one */
   unsigned char old, new;
-  int ok;
   /* if it fails, it fails. There are so many variations of broken mobos
    * that it is hard to argue that we should quit at this point. 
    */
@@ -139,11 +141,11 @@
   if (new == old)
       return 0;
 
-  ok = pci_write_byte(dev, 0x4e, new);
+  pci_write_byte(dev, 0x4e, new);
 
-  if (ok != new) {
+  if (pci_read_byte(dev, 0x4e) != new) {
     printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 
-	   old, new, name);
+	   0x4e, new, name);
     return -1;
   }
   return 0;
@@ -189,21 +191,15 @@
 
 int
 enable_flash_vt8231(struct pci_dev *dev, char *name) {
-  unsigned char old, new;
-  int ok;
+  unsigned char val;
   
-  old = pci_read_byte(dev, 0x40);
-
-  new = old | 0x10;
+  val = pci_read_byte(dev, 0x40);
+  val |= 0x10;
+  pci_write_byte(dev, 0x40, val);
 
-  if (new == old)
-      return 0;
-
-  ok = pci_write_byte(dev, 0x40, new);
-
-  if (ok != 0) {
+  if (pci_read_byte(dev, 0x40) != val) {
     printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 
-	   old, new, name);
+	   0x40, val, name);
     return -1;
   }
   return 0;
@@ -278,6 +274,10 @@
     }
 
     while (flash->name != NULL) {
+	if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) {
+	    flash++;
+	    continue;
+	}
 	printf("Trying %s, %d KB\n", flash->name, flash->total_size);
 	size = flash->total_size * 1024;
 	bios = mmap (0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
@@ -425,10 +425,11 @@
 
 void usage(const char *name)
 {
-    printf("usage: %s [-rwv] [file]\n", name);
+    printf("usage: %s [-rwv] [-c chipname][file]\n", name);
     printf("-r: read flash and save into file\n"
         "-w: write file into flash (default when file is specified)\n"
         "-v: verify flash against file\n"
+        "-c: probe only for specified flash chip\n"
         " If no file is specified, then all that happens\n"
         " is that flash info is dumped\n");
     exit(1);
@@ -444,7 +445,10 @@
     int opt;
     int read_it = 0, write_it = 0, verify_it = 0;
     char *filename = NULL;
-    while ((opt = getopt(argc, argv, "rwv")) != EOF) {
+
+    setbuf(stdout, NULL);
+
+    while ((opt = getopt(argc, argv, "rwvc:")) != EOF) {
         switch (opt) {
         case 'r':
             read_it = 1;
@@ -455,6 +459,9 @@
         case 'v':
             verify_it = 1;
             break;
+        case 'c':
+            chip_to_probe = strdup(optarg);
+            break;
         default:
             usage(argv[0]);
             break;
@@ -509,7 +516,7 @@
         fclose(image);
     }
 
-    if (write_it)
+    if (write_it || (!read_it && !verify_it))
         flash->write (flash, buf);
     if (verify_it)
         verify_flash (flash, buf, /* verbose = */ 0);
Index: mx29f002.c
===================================================================
RCS file: /cvsroot/freebios/freebios/util/flash_and_burn/mx29f002.c,v
retrieving revision 1.4
diff -u -r1.4 mx29f002.c
--- mx29f002.c	11 Feb 2003 16:09:12 -0000	1.4
+++ mx29f002.c	24 Jul 2003 17:02:07 -0000
@@ -97,7 +97,8 @@
    printf ("Programming Page: ");
     for (i = 0; i < total_size; i++) {
 	/* write to the sector */
-	printf ("address: 0x%08lx", i);
+	if ((i & 0xfff) == 0)
+	    printf ("address: 0x%08lx", i);
 	*(bios + 0x5555) = 0xAA;
 	*(bios + 0x2AAA) = 0x55;
 	*(bios + 0x5555) = 0xA0;
@@ -106,7 +107,8 @@
 	/* wait for Toggle bit ready */
 	toggle_ready_jedec(dst);
 
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
+	if ((i & 0xfff) == 0)
+	    printf ("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
     }
 #endif
     printf("\n");
Index: w49f002u.c
===================================================================
RCS file: /cvsroot/freebios/freebios/util/flash_and_burn/w49f002u.c,v
retrieving revision 1.2
diff -u -r1.2 w49f002u.c
--- w49f002u.c	28 Feb 2003 17:21:38 -0000	1.2
+++ w49f002u.c	24 Jul 2003 17:02:07 -0000
@@ -97,7 +97,8 @@
    printf ("Programming Page: ");
     for (i = 0; i < total_size; i++) {
 	/* write to the sector */
-	printf ("address: 0x%08lx", i);
+	if ((i & 0xfff) == 0)
+	    printf ("address: 0x%08lx", i);
 	*(bios + 0x5555) = 0xAA;
 	*(bios + 0x2AAA) = 0x55;
 	*(bios + 0x5555) = 0xA0;
@@ -106,7 +107,8 @@
 	/* wait for Toggle bit ready */
 	toggle_ready_jedec(dst);
 
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
+	if ((i & 0xfff) == 0)
+	    printf ("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
     }
 #endif
     printf("\n");


From kdemirev at yahoo.com  Thu Jul 24 14:11:01 2003
From: kdemirev at yahoo.com (kdemirev at yahoo.com)
Date: Thu Jul 24 14:11:01 2003
Subject: CVS three broken ???
Message-ID: <20030724182424.38275.qmail@web13903.mail.yahoo.com>

Can not cvs the three !!

cvs -z3
-d:pserver:anonymous at cvs.freebios.sourceforge.net:/cvsroot/freebios
co freebios

stops forever after next message:

U freebios/util/webconfig/var/pyservlog

Please check cvs three!

Kosta


__________________________________
Do you Yahoo!?
Yahoo! SiteBuilder - Free, easy-to-use web site design software
http://sitebuilder.yahoo.com


From rminnich at lanl.gov  Thu Jul 24 15:05:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 15:05:00 2003
Subject: CVS three broken ???
In-Reply-To: <20030724182424.38275.qmail@web13903.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0307241318040.17116-100000@maxroach.lanl.gov>

the tree is fine, sourceforge is probably overloaded again.

ron



From rminnich at lanl.gov  Thu Jul 24 15:12:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 15:12:00 2003
Subject: new config tool, static and dynamic trees
In-Reply-To: <20030724151642.GB5490@suse.de>
Message-ID: <Pine.LNX.4.44.0307241324500.17116-100000@maxroach.lanl.gov>

I'm now stopping with post code 0xee.

I do get past the memory test. There is a post code at 0x80 for a while. 

darn it. Worked until the last cvs update.

ron



From YhLu at tyan.com  Thu Jul 24 15:16:00 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jul 24 15:16:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302FC9AEB@TYANWEB>

Ron,

I find the problem. Can you merge the diff the tree?

1. in raminit.c, when computing csbase, should recount from 0 for every
memory controllers. Otherwise the memory on second northbridge will not be
init properly and can not be used.

2. add start/stop notify function. ( in coherent_ht.c and auto.c)  Otherwise
when using image that was compiled in non debug mode for auto.c, the second
cpu can not be started.

Thanks.

Yinghai Lu

-----????-----
???: YhLu 
????: 2003?7?23? 10:41
???: 'ebiederman at lnxi.com'; 'ron minnich'; 'Stefan Reinauer'
??: 'linuxbios at clustermatic.org'
??: Re: K8 + 2.4.21 + Tyan S2880

Eric or Ron or Stepfan,

To make the NIC under mem auto-conf code, I have spent one day on it. Here
are my findings:
1. Use the most updated code, in the Etherboot stage it will reboot after
firt NIC try aborting.
2. I have try to subsutite mem-conf with hard code version, and found
another problem, I can not start AP after conherent_ht or memory
initization. Only can start and stop in enable_routing function.
3. I have to move back to old code ( Before Eric moved some definition from
romcc_io.h to arch/io.h and cpu/p6/msr.h). At this situation, if I use
mem-conf, it still can not find broadcom nic in etherboot stage. But after I
substitute mem init with hard code one, It can find the nic.

I will study the difference today.

But anyway what make I can not start AP after conherent_ht or memory init,
so strange ???

Regards

Yinghai Lu

-----????-----
???: YhLu 
????: 2003?7?22? 10:41
???: 'ebiederman at lnxi.com'
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

Eric,

It can be compiled with you new code. But it meet problems in Etherboot
stage.
In S2880 has two broadcom NIC port in 8131 bus B, and one amd 8111 built-in
nic, and even if I hide it in amd8111 init and Etherboot can find it and try
to enable it and can not find the PM cap so aborting, in the old linuxbios
code (before yesterday) ( with mem hard code), it will go to tickle on
Broadcom nic, but in the new code (yesterday check in) ( mem configurable),
it will go to MB restarting.???

How about arima broadcom nic position? 

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?7?21? 18:33
???: YhLu
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> In the auto.c, if I enable : sdram_initialize(&cpu1), the linuxbios need
> another 20k. What happened? Only add one line and the same function has
been
> called ???

All functions are inline and the set of functions called is large.
At least I believe that is the issue.

And good luck catching up....

While I am away you get a chance.  My latest code has changed
sdram_initialize
one more time to take a cpu count parameter.

And perversely this should help because if a function is called in a loop
it will only be inlined once instead of multiple times.

Eric

-------------- next part --------------
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From rminnich at lanl.gov  Thu Jul 24 15:24:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 15:24:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9AEB@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307241337130.17116-100000@maxroach.lanl.gov>

Thank you for the patch. 

What I would like to do is get my linuxbios back to working condition, 
then merge these in. Otherwise, if Stefan can test and verify them, maybe 
he can merge them in before me. 

Thanks

ron



From stepan at suse.de  Thu Jul 24 15:41:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 24 15:41:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <Pine.LNX.4.44.0307241337130.17116-100000@maxroach.lanl.gov>; from rminnich@lanl.gov on Thu, Jul 24, 2003 at 01:37:53PM -0600
References: <3174569B9743D511922F00A0C943142302FC9AEB@TYANWEB> <Pine.LNX.4.44.0307241337130.17116-100000@maxroach.lanl.gov>
Message-ID: <20030724215015.C7701@suse.de>

* ron minnich <rminnich at lanl.gov> [030724 21:37]:
> Thank you for the patch. 
> 
> What I would like to do is get my linuxbios back to working condition, 
> then merge these in. Otherwise, if Stefan can test and verify them, maybe 
> he can merge them in before me. 

I'm sitting at home and don't have access to any SMP K8 from here, so
I'm going to test (and commit) this tommorrow at work..

  Greetings,
     Stefan
-- 
Architecture Team
    SuSE Linux AG


From rminnich at lanl.gov  Thu Jul 24 18:21:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 18:21:01 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <20030724215015.C7701@suse.de>
Message-ID: <Pine.LNX.4.44.0307241634030.17116-100000@maxroach.lanl.gov>

OK, I'm back, the checked out tree works fine now. 

YhLu, I will try to commit your changes tomrrow.

ron



From rminnich at lanl.gov  Thu Jul 24 18:53:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 18:53:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9AEB@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307241701330.17116-100000@maxroach.lanl.gov>

YhLu: I can fix your problem without adding the mainboard init function to 
hardware main, and also without code like this to the include file:

====
#ifdef FINAL_MAINBOARD_FIXUP
void final_mainboard_fixup(void);
#else
#  define final_mainboard_fixup() do {} while(0)
#endif /* FINAL_MAINBOARD_FIXUP */

====

All I need to do is add an enable function for the mainboard into the 
static device tree, and create a structure for your mainboard in the 
mainboard/tyan/2880 directory. This is pretty easy, and will let us test 
out the new static device support. 

But, if I make this change you are going to have to use the new config
tool for your mainboard. There is no going back to the old config tool
once I make the change.

The new config tool is working pretty well, now, however: Greg and Stefan 
and I are using it, and Greg and I use it exclusively. There are still 
some glitches here and there but overall it is quite solid.

Is this acceptable to you? Stefan, Greg, and I can help you with any
problems you encounter with the new config tool.

thanks

ron




From YhLu at tyan.com  Thu Jul 24 18:58:00 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jul 24 18:58:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
Message-ID: <3174569B9743D511922F00A0C943142302FC9B3D@TYANWEB>

Good, I will use your new config tool for s2880.

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?7?24? 16:07
???: YhLu
??: ebiederman at lnxi.com; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + Tyan S2880

YhLu: I can fix your problem without adding the mainboard init function to 
hardware main, and also without code like this to the include file:

====
#ifdef FINAL_MAINBOARD_FIXUP
void final_mainboard_fixup(void);
#else
#  define final_mainboard_fixup() do {} while(0)
#endif /* FINAL_MAINBOARD_FIXUP */

====

All I need to do is add an enable function for the mainboard into the 
static device tree, and create a structure for your mainboard in the 
mainboard/tyan/2880 directory. This is pretty easy, and will let us test 
out the new static device support. 

But, if I make this change you are going to have to use the new config
tool for your mainboard. There is no going back to the old config tool
once I make the change.

The new config tool is working pretty well, now, however: Greg and Stefan 
and I are using it, and Greg and I use it exclusively. There are still 
some glitches here and there but overall it is quite solid.

Is this acceptable to you? Stefan, Greg, and I can help you with any
problems you encounter with the new config tool.

thanks

ron



From rminnich at lanl.gov  Thu Jul 24 19:01:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 19:01:00 2003
Subject: K8 + 2.4.21 + Tyan S2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9B3D@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307241714290.17116-100000@maxroach.lanl.gov>

OK, I will start on this tonight.

ron



From rminnich at lanl.gov  Thu Jul 24 22:43:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 22:43:00 2003
Subject: 2 quick changes to arima/hdama
Message-ID: <Pine.LNX.4.44.0307242055350.28514-100000@maxroach.lanl.gov>

I've temporarily bumped up debugging output inside that file (the romimage 
gets too big otherwise) and shrunk the size of the tested memory region 
until I can get it to run faster.

ron



From rminnich at lanl.gov  Thu Jul 24 22:54:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 24 22:54:00 2003
Subject: NOTE: recent commit from YhLu
Message-ID: <Pine.LNX.4.44.0307242106110.28616-100000@maxroach.lanl.gov>

I have just committed the changes from YhLu which he sent this morning. 
The following files are changed:

CVS:    src/include/device/pci_ids.h src/mainboard/tyan/s2880/Config
CVS:    src/mainboard/tyan/s2880/auto.c
CVS:    src/mainboard/tyan/s2880/failover.c
CVS:    src/mainboard/tyan/s2880/tyan-fallback.config
CVS:    src/mainboard/tyan/s2880/tyan-normal.config
CVS:    src/northbridge/amd/amdk8/coherent_ht.c
CVS:    src/northbridge/amd/amdk8/raminit.c
CVS:    src/southbridge/amd/amd8111/Config
CVS:    src/southbridge/amd/amd8111/Config.lb
CVS:    src/southbridge/amd/amd8131/amd8131_bridge.c


Note that most of this is s2880-specific, with only a few mods to the amd 
chip files. 

The next step is to add options for the new config tool to enable 
mainboard-specific functions to be called. 

Please make sure your K8 ports still work. I can send the results of a 
c-diff on request.

ron



From han2004 at hotmail.com  Thu Jul 24 23:50:01 2003
From: han2004 at hotmail.com (gimyung han)
Date: Thu Jul 24 23:50:01 2003
Subject: Can you check my result, is it right?
Message-ID: <BAY2-F16n2HiVQ4hf0200003114@hotmail.com>

it is  part of the result of booting linux bios on my epia board

but i'm not sure I'm doing right...........
it's almost end of it...........


Wrote linuxbios table at: 00000500 - 0000068c  checksum a514
                                                                            
    

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2
                                                                            
    
    37:init_bytes() - zkernel_start:0xfff00000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x94000 size 0x7328 offset 0x60 filesize 0x37e0
(cleaned up) New segment addr 0x94000 size 0x7328 offset 0x60 filesize 
0x37e0
Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007328 filesz: 
0x00Clearing Segment: addr: 0x00000000000977e0 memsz: 0x0000000000003b48
Jumping to boot code at 0x94000
ROM segment 0xffff length 0xfffe reloc 0x9400
Etherboot 5.0.8 (GPL) Tagged ELF for [VIA 86C100]
Boot from (N)etwork or from (L)ocal? clocks_per_tick = 504391
N
Probing...[VIA 86C100]Found VIA 6102 ROM address 0x0000
rhine.c v1.0.0 2000-01-07
IO address 1800 Ethernet Address: 00:40:63:CB:C8:11
Analyzing Media type,this will take several seconds........OK
Linespeed=100Mbs Halfduplex
The PCI BIOS has not enabled this device!
Updating PCI command 0003->0007. pci_bus 00 pci_device_fn 90
Searching for server (DHCP)...
..................

_________________________________________________________________
?? ??? ?? ?? ??. ??? ??? MSN ???? ?????.   
http://www.msn.co.kr/news/  



From rminnich at lanl.gov  Fri Jul 25 00:00:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 00:00:01 2003
Subject: Can you check my result, is it right?
In-Reply-To: <BAY2-F16n2HiVQ4hf0200003114@hotmail.com>
Message-ID: <Pine.LNX.4.44.0307242212420.30568-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, gimyung han wrote:

> Updating PCI command 0003->0007. pci_bus 00 pci_device_fn 90
> Searching for server (DHCP)...
> ..................
> 

we saw this too. It looks like etherboot trouble. 

did you snoop the network to see if packets are getting out?

ron



From aip at cwlinux.com  Fri Jul 25 00:11:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Fri Jul 25 00:11:00 2003
Subject: Can you check my result, is it right?
In-Reply-To: <BAY2-F16n2HiVQ4hf0200003114@hotmail.com>; from gimyung han on Fri, Jul 25, 2003 at 04:03:50AM +0000
References: <BAY2-F16n2HiVQ4hf0200003114@hotmail.com>
Message-ID: <20030725122425.A30331@mail.cwlinux.com>

Hi,

	It is working, but you need to setup dhcpd and tftp server.

-Andrew

On Fri, Jul 25, 2003 at 04:03:50AM +0000, gimyung han wrote:
> 
> it is  part of the result of booting linux bios on my epia board
> 
> but i'm not sure I'm doing right...........
> it's almost end of it...........
> 
> 
> Wrote linuxbios table at: 00000500 - 0000068c  checksum a514
>                                                                             
>     
> 
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.2
>                                                                             
>     
>     37:init_bytes() - zkernel_start:0xfff00000  zkernel_mask:0x0000ffff
> Found ELF candiate at offset 0
> New segment addr 0x94000 size 0x7328 offset 0x60 filesize 0x37e0
> (cleaned up) New segment addr 0x94000 size 0x7328 offset 0x60 filesize 
> 0x37e0
> Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007328 filesz: 
> 0x00Clearing Segment: addr: 0x00000000000977e0 memsz: 0x0000000000003b48
> Jumping to boot code at 0x94000
> ROM segment 0xffff length 0xfffe reloc 0x9400
> Etherboot 5.0.8 (GPL) Tagged ELF for [VIA 86C100]
> Boot from (N)etwork or from (L)ocal? clocks_per_tick = 504391
> N
> Probing...[VIA 86C100]Found VIA 6102 ROM address 0x0000
> rhine.c v1.0.0 2000-01-07
> IO address 1800 Ethernet Address: 00:40:63:CB:C8:11
> Analyzing Media type,this will take several seconds........OK
> Linespeed=100Mbs Halfduplex
> The PCI BIOS has not enabled this device!
> Updating PCI command 0003->0007. pci_bus 00 pci_device_fn 90
> Searching for server (DHCP)...
> ..................
> 
> _________________________________________________________________
> ???? ?????? ???? ???? ????. ?????? ?????? MSN ???????? ??????????.   
> http://www.msn.co.kr/news/  
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Fri Jul 25 00:17:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 00:17:00 2003
Subject: Fixes for Tyan s2880
Message-ID: <Pine.LNX.4.44.0307242215070.30568-100000@maxroach.lanl.gov>

Yh Lu needed to add a mainboard-specific initialization code for the Tyan
s2880 board, and needed it called at a special place in hardwaremain(). In
V1, we would use defines and other such trickery to get this capability.
We're trying to avoid that in V2.

This problem turns out to be a perfect use for the static device
initialization support.

First, we apply patches that are tyan-only or are bug fixes to these files:

src/include/device/pci_ids.h
src/mainboard/tyan/s2880/auto.c
src/mainboard/tyan/s2880/Config
src/mainboard/tyan/s2880/debug.c
src/mainboard/tyan/s2880/failover.c
src/mainboard/tyan/s2880/static_devices.c
src/mainboard/tyan/s2880/tyan-fallback.config
src/mainboard/tyan/s2880/tyan-normal.config
src/mainboard/tyan/s2880/VERSION
src/mainboard/tyan/VERSION
src/northbridge/amd/amdk8/coherent_ht.c
src/northbridge/amd/amdk8/raminit.c
src/southbridge/amd/amd8111/Config
src/southbridge/amd/amd8111/Config.lb
src/southbridge/amd/amd8131/amd8131_bridge.c
targets/tyan/s2880/Config.lb

Now, we need to ensure that YhLu's "special code" is called for his mainboard. 

As it happens, the mainboard is also a "chip" in the new scheme. The
config tool builds a tree based on this structure, from 
src/include/device/chip.h: 

struct chip {
  struct chip_control *control; /* for this device */
  char *path; /* can be 0, in which case the default is taken */
  char *configuration; /* can be 0. */
  int irq;
  struct chip *next, *children;
  /* there is one of these for each INSTANCE of a chip */
  void *chip_info; /* the dreaded "void *" */
};

The tree for the s2880 looks like this:

=====
#include <device/chip.h>
struct chip static_root, static_dev1, static_dev2, static_dev3, static_dev4, sta
tic_dev5, static_dev6, static_dev7, static_dev8, static_dev9, static_dev10;
#include "/home/rminnich/src/bios/freebios2/src/mainboard/tyan/s2880/chip.h"

struct chip static_root = {
/* mainboard /home/rminnich/src/bios/freebios2/src/mainboard/tyan/s2880 */
  .children = &static_dev9,
};
struct chip static_dev9 = {
/* cpu /home/rminnich/src/bios/freebios2/src/cpu/k8 */
  .next = &static_dev8,
};

.
.
.

======

(the rest is removed for clearness)

Note that there are even "chips" for CPUs: it is possible to handle
CPU fixup in this system. 

Each entry in the above structures defines a static device. 

Please recall that static devices consist of a generic structure and then 
special-purpose (device specific) structures. 

The generic structure is this:
/* there is one of these for each TYPE of chip */
struct chip_control {
  void (*enable)(struct chip *, enum chip_pass);
  char *path;     /* the default path. Can be overridden
                   * by commands in config
                   */
  // This is the print name for debugging
  char *name;
};

Device-specific classes are defined by the attributes of the device, and
hence vary for each device. In the V1 days, we tried to have one 
generic structure, but that did not even work for the limited case
of superio's, so for V2 we are making the structure unique to 
each device. 

We have to define one device structure for the Tyan s2880. 
The structure has to be defined in an include file that is in the 
directory that contains the code for the device. So, for the 
tyan s2880 mainboard, we need to have a definition file in 
src/mainboard/tyan/s2880. We'll call it src/mainboard/tyan/s2880/chip.h. 

In this case, it is rather simple:

struct mainboard_tyan_s2880_config {
        int fixup_scsi;
};

This is the only thing we're controlling at present. Note that the name of 
the struct is a 'flattened' version of the device name.

We need to tell the config tool where to find the file containing the 
structure, and how to initialize the struct in the file.
Add these lines to src/tyan/s2880/Config.lb. They will define the name of the 
file to use, and the code to initialize the static device. 

config chip.h 
register "fixup_scsi" = "1"

We need to create the structure that defines the generic structure for the 
mainboard, so linuxbios can hook into it. So add these lines to the end
of src/mainboard/tyan/s2880/mainboard.c:

struct chip_control mainboard_tyan_s2880_control = {
                enable: enable,
                name:   "Tyan s2880 mainboard "
};

Then add the enable function (BEFORE the struct chip_control declaration).
Note that it is declared 'static', and has only one entry in the 
switch. 

static void
enable(struct chip *chip, enum chip_pass pass)
{

        struct mainboard_tyan_s2880_config *conf =
                (struct mainboard_tyan_s2880_config *)chip->chip_info;

        switch (pass) {
                default: break;
                case CONF_PASS_PRE_BOOT:
                         if (conf->fixup_scsi)
                                onboard_scsi_fixup();
                        printk_debug("mainboard fixup pass %d done\r\n",
                                        pass);
                        break;
        }

}

That's pretty much it. total changes are 170 lines.
The static device tree (which is generated by the config tool, you 
don't have to write this code) now looks like this:

==========
#include <device/chip.h>
struct chip static_root, static_dev1, static_dev2, static_dev3, static_dev4, sta
tic_dev5, static_dev6, static_dev7, static_dev8, static_dev9, static_dev10;
#include "/home/rminnich/src/bios/freebios2/src/mainboard/tyan/s2880/chip.h"
extern struct chip_control mainboard_tyan_s2880_control;
struct mainboard_tyan_s2880_config mainboard_tyan_s2880_config_0        = {
  .fixup_scsi = 1,
};

struct chip static_root = {
/* mainboard /home/rminnich/src/bios/freebios2/src/mainboard/tyan/s2880 */
  .children = &static_dev9,
  .control= &mainboard_tyan_s2880_control,
  .chip_info = (void *) &mainboard_tyan_s2880_config_0,
};
struct chip static_dev9 = {
/* cpu /home/rminnich/src/bios/freebios2/src/cpu/k8 */
  .next = &static_dev8,
};
=====

Note that the mainboard now has several new entries, and there
is a new struct for controlling the mainboard, along with an 
initializer. The enable function for the mainboard will be called at several 
places in hardwaremain with a different pass #, and since there is 
only one case defined, only one action is taken. 


So to add this capability for this mainbard, we had to:
- define a file containing the device-specific structure which 
  we called chip.h, and placed in src/mainboard/tyan/s2880
- add two lines to src/mainboard/tyan/s2880/Config.lb, which 
  define the file we need (chip.h) and the initialization of 
  the structure. 
- add the "base class" structure to src/mainboard/tyan/s2880/mainboard.c,
  along with the enable function. 

I've built this mainboard and hexdump of the romimage looks pretty good.
Yh Lu, can you please verify this? The config.lb is in
targets/tyan/s2880/Config.lb.  I can send the context diffs if that will
help.

Note that this technique will work for anything that the config tool 
considers a 'device': mainboard, cpu, north and south bridge, superio, 
etc.

Thanks

ron



From rminnich at lanl.gov  Fri Jul 25 00:19:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 00:19:00 2003
Subject: Can you check my result, is it right?
In-Reply-To: <20030725122425.A30331@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.44.0307242230570.30568-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, Andrew Ip wrote:

> 	It is working, but you need to setup dhcpd and tftp server.

I think he should snoop the network to make sure dhcp packets are getting 
off the board.

ron



From rminnich at lanl.gov  Fri Jul 25 00:25:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 00:25:01 2003
Subject: Can you help me?     I'm working on VIA-EPIA
In-Reply-To: <20030724172510.GA21107@tsn.or.jp>
Message-ID: <Pine.LNX.4.44.0307242237590.30809-100000@maxroach.lanl.gov>

I committed these patches, please test.

thanks

ron



From han2004 at hotmail.com  Fri Jul 25 02:27:00 2003
From: han2004 at hotmail.com (gimyung han)
Date: Fri Jul 25 02:27:00 2003
Subject: Do I need to make Makefile.conf for myself?
Message-ID: <BAY2-F157WtIIZS2TRq00001caf@hotmail.com>

Thanks to your help, I could succeed in setup dhcp server and tftp

And then, I tried to get over to next step, making elfboot image.

At first time, I just typed whole command written in the HOWTO, but I 
failed with "Error: no Makefile.conf "

so I changed the original file, "Makefile.conf.in" to "Makefile.conf", then 
I typed whole command again.

After all, I failed and saw following message:
"bash: ./mkelfImage: @PERL@: bad Interpreter: No such file or directory 
exist"

Did I need to make my own Makefile.conf instead of changing 
Makefile.conf.in?
If so, How can I make my own?

thanks for your help

_________________________________________________________________
MSN Messenger? ?? ????? ?? ??? ??? ????.   
http://messenger.msn.co.kr  



From mwilkinson at ndirect.co.uk  Fri Jul 25 02:37:00 2003
From: mwilkinson at ndirect.co.uk (Mark Wilkinson)
Date: Fri Jul 25 02:37:00 2003
Subject: Do I need to make Makefile.conf for myself?
In-Reply-To: <BAY2-F157WtIIZS2TRq00001caf@hotmail.com>
References: <BAY2-F157WtIIZS2TRq00001caf@hotmail.com>
Message-ID: <200307250750.25090.mwilkinson@ndirect.co.uk>

If you haven't build the mkelfImage yet,
the first step it to run the configure program provided so that it can work 
out how to compile the mkelfImage program.

in the directory you untar'd mkelfImage type the following
	./configure

it should then give a long output checking for various things
once it's finished,

	make

	make install

which should install the mkelfImage programs to /usr/local/bin


Regards
Mark.

On Friday 25 Jul 2003 07:40, gimyung han wrote:
> Thanks to your help, I could succeed in setup dhcp server and tftp
>
> And then, I tried to get over to next step, making elfboot image.
>
> At first time, I just typed whole command written in the HOWTO, but I
> failed with "Error: no Makefile.conf "
>
> so I changed the original file, "Makefile.conf.in" to "Makefile.conf", then
> I typed whole command again.
>
> After all, I failed and saw following message:
> "bash: ./mkelfImage: @PERL@: bad Interpreter: No such file or directory
> exist"
>
> Did I need to make my own Makefile.conf instead of changing
> Makefile.conf.in?
> If so, How can I make my own?
>
> thanks for your help
>
> _________________________________________________________________
> MSN Messenger? ?? ????? ?? ??? ??? ????.
> http://messenger.msn.co.kr
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From ts1 at cma.co.jp  Fri Jul 25 02:38:00 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Fri Jul 25 02:38:00 2003
Subject: Do I need to make Makefile.conf for myself?
In-Reply-To: <BAY2-F157WtIIZS2TRq00001caf@hotmail.com>
References: <BAY2-F157WtIIZS2TRq00001caf@hotmail.com>
Message-ID: <20030725065129.GA6958@cma.co.jp>

On Fri, Jul 25, 2003 at 06:40:47AM +0000, gimyung han wrote:
> And then, I tried to get over to next step, making elfboot image.
> 
> At first time, I just typed whole command written in the HOWTO, but I 
> failed with "Error: no Makefile.conf "
> 
> so I changed the original file, "Makefile.conf.in" to "Makefile.conf", then 
> I typed whole command again.
> 
> After all, I failed and saw following message:
> "bash: ./mkelfImage: @PERL@: bad Interpreter: No such file or directory 
> exist"

Use the latest mkelfImage at:
ftp://ftp.lnxi.com/pub/mkelfImage/mkelfImage-2.5.tar.gz
It's not written in perl anymore.

--
Takeshi


From aip at cwlinux.com  Fri Jul 25 03:03:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Fri Jul 25 03:03:01 2003
Subject: Do I need to make Makefile.conf for myself?
In-Reply-To: <BAY2-F157WtIIZS2TRq00001caf@hotmail.com>; from gimyung han on Fri, Jul 25, 2003 at 06:40:47AM +0000
References: <BAY2-F157WtIIZS2TRq00001caf@hotmail.com>
Message-ID: <20030725151635.C31593@mail.cwlinux.com>

Hi gimyung,

> Thanks to your help, I could succeed in setup dhcp server and tftp
> And then, I tried to get over to next step, making elfboot image.
> At first time, I just typed whole command written in the HOWTO, but I 
> failed with "Error: no Makefile.conf "
> so I changed the original file, "Makefile.conf.in" to "Makefile.conf", then 
> I typed whole command again.
> After all, I failed and saw following message:
> "bash: ./mkelfImage: @PERL@: bad Interpreter: No such file or directory 
> exist"
> Did I need to make my own Makefile.conf instead of changing 
> Makefile.conf.in?
> If so, How can I make my own?
For testing, you can use mine which is located at
ftp://ftp.cwlinux.com/pub/downloads/linuxbios-sdk/kernel/elfkernel
Since it is compiled with 386 setting, it probably will boot from most
system.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From ijpriya at hotmail.com  Fri Jul 25 08:09:00 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Fri Jul 25 08:09:00 2003
Subject: ldscript.ld contents?
Message-ID: <BAY2-F166tO7WUHbSss000039be@hotmail.com>

Hello,

         I compiled the linuxbios for sc1200. The ldscript.ld contents looks 
like this:

INCLUDE ldoptions
INCLUDE 
/root/PT06/Reference/LinuxBios/Freebios/freebios/src/arch/i386/config/ldscript.base
INCLUDE 
/root/PT06/Reference/LinuxBios/Freebios/freebios/src/cpu/i386/entry16.lds
INCLUDE 
/root/PT06/Reference/LinuxBios/Freebios/freebios/src/cpu/i386/entry32.lds
INCLUDE 
/root/PT06/Reference/LinuxBios/Freebios/freebios/src/cpu/i386/reset16.lds


     It looks completely different from the ldscript.ld found in romimages 
directory. I hope this ldcript.ld is automatically generated when running 
the python program. Is the entries correct? Or what i should do to correct 
it?

Thanks in advance for any help.

With Regards,
Priya.

_________________________________________________________________
Nagesh Kukunoor's back! With 3 Deewarein. 
http://server1.msn.co.in/sp03/3deewarein/index.asp Win tickets here.



From stepan at suse.de  Fri Jul 25 09:45:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Fri Jul 25 09:45:01 2003
Subject: coherent hypertransport hardcodes.
In-Reply-To: <3174569B9743D511922F00A0C943142302DD1423@TYANWEB>
References: <3174569B9743D511922F00A0C943142302DD1423@TYANWEB>
Message-ID: <20030725135847.GA9591@suse.de>

* YhLu <YhLu at tyan.com> [030719 02:59]:

> I have tested Stefan's the code about coherent_ht.c, and add some hardcode
> to it.
> coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one.
> coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones.
 
I am not happy with these hardcodes at all, they will make all
motherboards fail that have a different link setup than the tyan S2880
(It should be ok for hdama, but will definitely make the AMD quartet
fail)

Link speed and width setup should be done "dynamically" based on the link
capabilities of the devices connected to each other.

I wrote two functions to do this for every pair of hypertransport
devices, they should probably be enhanced to take a configurable
(per nvram or config option) maximum in addition to relying on what the
devices say.

This needs support from the motherboard specific Config.lb files,
because we need to know for every cpu which bridge/cpu is connected to 
which link on the hypertransport bus.

Tom from LNXI has also written some code that fills the speed registers
it seems. But this is executed in C-Payload when doing PCI. As we need
to assert LDTSTOP_L I am not sure whether it can be kept there. Tom?  

I checked in cpu and southbridge dependent parts of LDTSTOP_L assertion,
they should be operational as soon as we know the link configuration
from the config file .

The static tree generated at the moment seems not right to me:
for the one cpu that is actually configured, several nodes are
generated:

struct chip static_dev9 = {
/* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/k8 */
  .next = &static_dev8,
};
struct chip static_dev8 = {
/* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/k7 */
  .next = &static_dev7,
};
struct chip static_dev7 = {
/* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/p6 */
  .next = &static_dev6,
};
struct chip static_dev6 = {
/* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/p5 */
  .next = &static_dev5,
};

I assume this is to allow callbacks for each cpu type the k8
"implements" at the right place. but it looks really nasty. And
it seems that there are no callbacks anyways here. Or am I wrong?

Is this really needed? It looks like this should be one entry for every
cpu that can be plugged into the system, plus for every bridge on the
system.

In the config file this shows up as:

 option i686=1
 option i586=1
 option INTEL_PPRO_MTRR=1
 option k7=1
 option k8=1


Ron, is it already possible to add information on links between the
cht and ncht devices?

The chain i want to describe looks pretty much like:

       K8-CPU[2] ------- K8-CPU[3]
          |                 |
          |                 |
       K8-CPU[0] ------- K8-CPU[1]
          |                 |
          |                 |
       8111-SB[0]        8131-SB[0]

with possibly multiple bridges of the same type.


Stefan

-------------- next part --------------
#define SPEED_100  15
#define SPEED_200  0
#define SPEED_400  2
#define SPEED_600  4
#define SPEED_800  5
#define SPEED_1000 6
#define SUPPORTS(x) & (1<<x)

uint8_t get_maximum_cht_speed(uint16_t mask)
{
	if(mask SUPPORTS(SPEED_1000))
		return SPEED_1000;
	if(mask SUPPORTS(SPEED_800))
		return SPEED_800;
	if(mask SUPPORTS(SPEED_600))
		return SPEED_600;
	if(mask SUPPORTS(SPEED_400))
		return SPEED_400;
	if(mask SUPPORTS(SPEED_200))
		return SPEED_200;
	if(mask SUPPORTS(SPEED_100))
		return SPEED_100;
}

#if 1
void print_speed(uint8_t speed)
{
	const static char *speeds[]={ "200", "n/a", "400", "n/a", "600", "800", 
				     "1000", "n/a", "n/a", "n/a", "n/a", "n/a",
				     "n/a", "n/a", "n/a", "100" };
	print_debug("Link speed: ");
	print_debug(speeds[speed]);
	print_debug("MHz\r\n");

}
#endif

/*
 * dev_a, dev_b   :   device that share a link
 * link_a, link_b :   link output on device a/b (0,1,2)
 */

void setup_cht_linkspeed(device_t dev_a, device_t dev_b, 
				uint8_t link_a, uint8_t link_b)
{
	uint8_t reg_a, reg_b, speed_max;
	uint16_t speed_mask
	uint32_t tmp;

	reg_a = (0x20*link_a)+0x88;
	reg_b = (0x20*link_b)+0x88;

	/* 
	 * get link speed mask of both devices and AND them
	 * to get the speeds supported by both devices.
	 */

	speed_mask = (pci_read_config32(dev_a, reg_a) >> 16) & \
	               (pci_read_config32(dev_b, reg_b) >> 16);
	
	speed_max=get_maximum_cht_speed(speed_mask);
	
#if 1
	print_speed(speed_max);
#endif

	/* write link width on device a */
	tmp =  pci_read_config32(dev_a, reg_a);
	tmp &= ~(15<<8);
	tmp |= (speed_max<<8);
	pci_write_config32(dev_a, reg_a, tmp);
	
	/* write link width on device b */
	tmp =  pci_read_config32(dev_b, reg_b);
	tmp &= ~(15<<8);
	tmp |= (speed_max<<8);
	pci_write_config32(dev_b, reg_b, tmp);

}	
	


-------------- next part --------------

/*
 * dev_a, dev_b   :   device that share a link
 * link_a, link_b :   link output on device a/b (0,1,2)
 */

#if 1
int print_width(uint8_t width)
{
	switch (max_width) {
	case 0:
		print_debug("8bit");
		break;
	case 1:
		print_debug("16bit");	
		break;
	case 3:
		print_debug("32bit");
		break;
	case 4:
		print_debug("2bit");
		break;
	case 5:
		print_debug("4bit");
		break;
	case 7:
		print_debug("physically not connected");
		break;
	default:
		print_debug("unknown");
	}
}
#endif

void setup_cht_linkwidth(device_t dev_a, device_t dev_b, 
				uint8_t link_a, uint8_t link_b)
{
	uint8_t in_width, out_width, reg_a, reg_b;
	uint32_t tmp;

	reg_a = (0x20*link_a)+0x84;
	reg_b = (0x20*link_b)+0x84;

	/* get maximum link width in/out */
	in_width = ((pci_read_config32(dev_a, reg_a) >> 16) & 0x07) & \
	               ((pci_read_config32(dev_b, reg_b) >> 20) & 0x07);

	/* get maximum link width out/in */
	out_width = ((pci_read_config32(dev_a, reg_a) >> 20) & 0x07) & \
	               ((pci_read_config32(dev_b, reg_b) >> 16) & 0x07);

#if 1
	print_debug("link width ( a->b / b->a ) : ");
	print_width(in_width);
	print_debug("/");
	print_width(out_width);
	print_debug("\r\n");
#endif

	/* write link width on device a */
	tmp =  pci_read_config32(dev_a, reg_a);
	tmp &= ~( (7<<24) | (7<<28) );
	tmp |= ( (in_width<<24)|(out_width<<28) );
	pci_write_config32(dev_a, reg_a, tmp);
	
	/* write link width on device b */
	tmp =  pci_read_config32(dev_b, reg_b);
	tmp &= ~( (7<<24) | (7<<28) );
	tmp |= ( (out_width<<24)|(in_width<<28) );
	pci_write_config32(dev_b, reg_b, tmp);

}	
	



From rminnich at lanl.gov  Fri Jul 25 11:07:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 11:07:00 2003
Subject: Do I need to make Makefile.conf for myself?
In-Reply-To: <BAY2-F157WtIIZS2TRq00001caf@hotmail.com>
Message-ID: <Pine.LNX.4.44.0307250920450.893-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, gimyung han wrote:

> so I changed the original file, "Makefile.conf.in" to "Makefile.conf", then 
> I typed whole command again.

no. 

I believe you have to run automake.

ron



From rminnich at lanl.gov  Fri Jul 25 11:12:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 11:12:00 2003
Subject: ldscript.ld contents?
In-Reply-To: <BAY2-F166tO7WUHbSss000039be@hotmail.com>
Message-ID: <Pine.LNX.4.44.0307250925530.893-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, Devi Priya wrote:

>      It looks completely different from the ldscript.ld found in romimages 
> directory. I hope this ldcript.ld is automatically generated when running 
> the python program. Is the entries correct? Or what i should do to correct 
> it?

it looks good to me.

Why not just try it?

ron



From rminnich at lanl.gov  Fri Jul 25 11:25:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 11:25:00 2003
Subject: coherent hypertransport hardcodes.
In-Reply-To: <20030725135847.GA9591@suse.de>
Message-ID: <Pine.LNX.4.44.0307250933050.893-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, Stefan Reinauer wrote:

> The static tree generated at the moment seems not right to me:
> for the one cpu that is actually configured, several nodes are
> generated:
> 
> struct chip static_dev9 = {
> /* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/k8 */
>   .next = &static_dev8,
> };
> struct chip static_dev8 = {
> /* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/k7 */
>   .next = &static_dev7,
> };
> struct chip static_dev7 = {
> /* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/p6 */
>   .next = &static_dev6,
> };
> struct chip static_dev6 = {
> /* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/p5 */
>   .next = &static_dev5,
> };

I agree with you. This is arguably wrong, there should only be one cpu
entry in the tree; it's on the "to fix" list. The code is pretty dumb
right now, just emitting a tree for all devices. I'm just trying to figure
out how "to fix" it, but have an idea. Most preferable would be to say
just:

cpu k8 end

and have it automagically bring in whatever else is needed. I think that 
is the right thing. 

> I assume this is to allow callbacks for each cpu type the k8
> "implements" at the right place. but it looks really nasty. And
> it seems that there are no callbacks anyways here. Or am I wrong?

There will be no callbacks unless they are defined. None are defined. 

> Is this really needed? It looks like this should be one entry for every
> cpu that can be plugged into the system, plus for every bridge on the
> system.

yes, this is what should be there. 

> Ron, is it already possible to add information on links between the
> cht and ncht devices?
> 
> The chain i want to describe looks pretty much like:
> 
>        K8-CPU[2] ------- K8-CPU[3]
>           |                 |
>           |                 |
>        K8-CPU[0] ------- K8-CPU[1]
>           |                 |
>           |                 |
>        8111-SB[0]        8131-SB[0]
> 
> with possibly multiple bridges of the same type.

something like:

cpu k8 
	register "cpuid" = "1"
	regiser  "southlink" = "amd8111-1"
	register "rightlink" = "k8-cpu3"
end

or some such? Would something like this do it?

this is something we need to finish up. But yes, it's in the plan. We're 
still trying to figure out what people most want.

I hope it can last until week after next, I am gone most of next week, but 
maybe we can convince Greg to put it in.

I think there is work left to be done in this part of configuration.

ron



From rminnich at lanl.gov  Fri Jul 25 11:25:09 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 11:25:09 2003
Subject: coherent hypertransport hardcodes.
In-Reply-To: <20030725135847.GA9591@suse.de>
Message-ID: <Pine.LNX.4.44.0307250938370.893-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, Stefan Reinauer wrote:

> I am not happy with these hardcodes at all, they will make all
> motherboards fail that have a different link setup than the tyan S2880
> (It should be ok for hdama, but will definitely make the AMD quartet
> fail)

just checking, did this cause trouble for you Stefan? If so, we may want 
to back these out. 

ron



From stepan at suse.de  Fri Jul 25 12:10:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Fri Jul 25 12:10:00 2003
Subject: coherent hypertransport hardcodes.
In-Reply-To: <Pine.LNX.4.44.0307250933050.893-100000@maxroach.lanl.gov>
References: <20030725135847.GA9591@suse.de> <Pine.LNX.4.44.0307250933050.893-100000@maxroach.lanl.gov>
Message-ID: <20030725162415.GA27430@suse.de>

* ron minnich <rminnich at lanl.gov> [030725 17:38]:
> I agree with you. This is arguably wrong, there should only be one cpu
> entry in the tree; it's on the "to fix" list. The code is pretty dumb
> right now, just emitting a tree for all devices. I'm just trying to figure
> out how "to fix" it, but have an idea. Most preferable would be to say
> just:
> 
> cpu k8 end
 
> and have it automagically bring in whatever else is needed. I think that 
> is the right thing. 
 
Ack.

> > The chain i want to describe looks pretty much like:
> > 
> >        K8-CPU[2] ------- K8-CPU[3]
> >           |                 |
> >           |                 |
> >        K8-CPU[0] ------- K8-CPU[1]
> >           |                 |
> >           |                 |
> >        8111-SB[0]        8131-SB[0]
> 
> cpu k8 
> 	register "cpuid" = "1"
> 	regiser  "southlink" = "amd8111-1"
> 	register "rightlink" = "k8-cpu3"
> end

> or some such? Would something like this do it?

Yes, then cpu and bridge configuration could be done really readable
like in this example of above scenario:

cpu cpu-k8-0
        register "cpuid"      = "0"
        register "arch"       = "k8" # if a special cpu type needs 
                                     # to add callbacks.

        register "acrosslink" = "cpu-k8-1"
        register "uplink"     = "cpu-k8-2"
        register "downlink"   = "bridge-8111-0"
end

cpu cpu-k8-1
        register "cpuid"      = "1"
        register "arch"       = "k8"

        register "acrosslink" = "cpu-k8-0"
        register "uplink"     = "cpu-k8-3"
        register "downlink"   = "bridge-8131-0"
end

cpu cpu-k8-2
        register "cpuid"      = "2"
        register "arch"       = "k8"

        register "acrosslink" = "cpu-k8-3"
        register "downlink"   = "cpu-k8-0"
end

cpu cpu-k8-3
        register "cpuid"      = "3"
        register "arch"       = "k8"

        register "acrosslink" = "cpu-k8-2"
        register "downlink"   = "cpu-k8-1"
end

bridge bridge-8111-0
        register "class"      = "southbridge"
        register "bridgeid"   = "0" # first 8111 sb on the bus

        register "vendor"     = "amd"
        register "deviceid"   = "amd8111"

        register "uplink"     = "cpu-k8-0"

        # special configuration like switching off
        # builtin nics could happen here.

end        

bridge bridge-8131-0 #
        register "class"      = "pcibridge" # currently 8131 code sits
                                            # in src/southbridge. It
                                            # could be either moved or
                                            # mapped.
        register "bridgeid"   = "0"         # first 8131 pci-x bridge
                                            # on the bus

        register "vendor"     = "amd"
        register "deviceid"   = "amd8131"

        register "uplink"     = "cpu-k8-1"
end        

> this is something we need to finish up. But yes, it's in the plan. We're 
> still trying to figure out what people most want.

> I hope it can last until week after next, I am gone most of next week, but 
> maybe we can convince Greg to put it in.

this would make the configuration scenario of AMD64 systems a lot more
flexible. Most of the hardcodes like link speed selection for the tyan
board could be made configurable in the motherboard configuration file
without really knowing anything but the board specification.

  Stefan


-- 
Architecture Team
    SuSE Linux AG


From stepan at suse.de  Fri Jul 25 12:23:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Fri Jul 25 12:23:01 2003
Subject: coherent hypertransport hardcodes.
In-Reply-To: <Pine.LNX.4.44.0307250938370.893-100000@maxroach.lanl.gov>
References: <20030725135847.GA9591@suse.de> <Pine.LNX.4.44.0307250938370.893-100000@maxroach.lanl.gov>
Message-ID: <20030725163656.GB27430@suse.de>

* ron minnich <rminnich at lanl.gov> [030725 17:38]:
> On Fri, 25 Jul 2003, Stefan Reinauer wrote:
> 
> > I am not happy with these hardcodes at all, they will make all
> > motherboards fail that have a different link setup than the tyan S2880
> > (It should be ok for hdama, but will definitely make the AMD quartet
> > fail)
> 
> just checking, did this cause trouble for you Stefan? If so, we may want 
> to back these out. 

I have not enabled LDTSTOP_L assertion in the tree yet, thus the writes
to the link speed registers are done but wait to become current. I'm
thinking about moving the code to tyans mb specific code and have the
same thing for the other mainboards until it can be done dynamically.

  Stefan

-- 
Architecture Team
    SuSE Linux AG


From rminnich at lanl.gov  Fri Jul 25 13:00:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 13:00:01 2003
Subject: coherent hypertransport hardcodes.
In-Reply-To: <20030725163656.GB27430@suse.de>
Message-ID: <Pine.LNX.4.44.0307251113260.893-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, Stefan Reinauer wrote:

> I have not enabled LDTSTOP_L assertion in the tree yet, thus the writes
> to the link speed registers are done but wait to become current. I'm
> thinking about moving the code to tyans mb specific code and have the
> same thing for the other mainboards until it can be done dynamically.

OK. we're looking at your ideas on the config tool and will try to have 
something for you next week.

ron



From Uberto.Barbini at ceda.polimi.it  Fri Jul 25 13:04:01 2003
From: Uberto.Barbini at ceda.polimi.it (Barbini Uberto)
Date: Fri Jul 25 13:04:01 2003
Subject: Linuxbios and Via M10000, where to start?
Message-ID: <1A4E530F40B6D3119E880050041D6DE00412FE82@wntceda3.ceda.polimi.it>

Hi, I'm sorry for the quite trivial question, but I cannot be able to found
it by myself.

I have a via M10000 motherboard and I'm using it with gentoo with kernel
2.6.0.test1 and xfree86 latest snap, and acpid for clean poweroff by power
button.
All works fine, and I'm quite an happy user.
I'm wondering if I happiness can grow still more using linuxbios to cut off
booting time. ;)
But is there any risk I cannot be able to run the above software? (first
question)

I'm not sure what I'm supposed to do, after downloading freebios, but I'm
unsure of its function too. In the donwload page of linuxbios.org there is a
link to "other software", I have to download that too?

I'll be grateful for any hints and I apologize if this is not the right
place to ask for it.

Bye

Uberto Barbini


From meinrad.sauter at gmx.de  Fri Jul 25 13:04:06 2003
From: meinrad.sauter at gmx.de (Meinrad Sauter)
Date: Fri Jul 25 13:04:06 2003
Subject: Questions on BX Chipset
Message-ID: <200307232138.38851.meinrad.sauter@gmx.de>

Hi,

after a short period of pain, I finally made LinuxBIOS running on my machine 
(Siemens Fujitsu Multitainer / i440BX Chipset). I use this device as a 
digital video recorder running (of course) Linux and Klaus Schmidingers 
famous VDR. 
Unfortunately there are some features I couldn't get to work until now, 
probably you can give me some hints:
- Soft Power-Off: I used the APM-BIOS in my Original Setup for this. I 
understand that LinuxBIOS doesn't implement such BIOS functions. I also found 
a kernel patch that implements this feature for SIS-Chipsets. Is there a 
possibility to get that thin running on a BX board?
- HD-Spindown: Same as above, simply doesnt work with my current LinuxBIOS 
setup
- VGA: The Multitainer has an onboard MPACT2 Graphics adapter. It would be 
nice to have, but not really required. From the docs, I think I could make it 
work using ADLO or with the builtin VGA support. What do you think?
- Wake on RTC: Not even the original BIOS supported this. Anyway I don't think 
its a hardware limitation. Do you think it is possible to implement this for 
LinuxBIOS?

Thanks for your answers and keep up the good work!

Meinrad
-- 
Meinrad Sauter
email: meinrad.sauter at gmx.de



From John.Hearns at micromuse.com  Fri Jul 25 13:04:11 2003
From: John.Hearns at micromuse.com (John Hearns)
Date: Fri Jul 25 13:04:11 2003
Subject: Mini-ITX
Message-ID: <021801c351f5$9d93eaa0$8461cdc2@DREAD>

I've been off the linuxbios list for some time. I see there are a few
threads on mini-ITX.

Can I ask for some pointers to ROM images for EPIA-800
and M10000 Nehemiah boards (I've just got one on order)

I see the ones on cwlinux.com - which specific boards are these for?
Thanks!



From tomz at lnxi.com  Fri Jul 25 13:04:17 2003
From: tomz at lnxi.com (tomz)
Date: Fri Jul 25 13:04:17 2003
Subject: coherent hypertransport hardcodes.
References: <3174569B9743D511922F00A0C943142302DD1423@TYANWEB> <20030725135847.GA9591@suse.de>
Message-ID: <3F2157FB.184A8ACF@lnxi.com>

Stefan Reinauer wrote:

> * YhLu <YhLu at tyan.com> [030719 02:59]:
>
> > I have tested Stefan's the code about coherent_ht.c, and add some hardcode
> > to it.
> > coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one.
> > coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones.
>
> I am not happy with these hardcodes at all, they will make all
> motherboards fail that have a different link setup than the tyan S2880
> (It should be ok for hdama, but will definitely make the AMD quartet
> fail)
>
> Link speed and width setup should be done "dynamically" based on the link
> capabilities of the devices connected to each other.
>
> I wrote two functions to do this for every pair of hypertransport
> devices, they should probably be enhanced to take a configurable
> (per nvram or config option) maximum in addition to relying on what the
> devices say.
>
> This needs support from the motherboard specific Config.lb files,
> because we need to know for every cpu which bridge/cpu is connected to
> which link on the hypertransport bus.
>
> Tom from LNXI has also written some code that fills the speed registers
> it seems. But this is executed in C-Payload when doing PCI. As we need
> to assert LDTSTOP_L I am not sure whether it can be kept there. Tom?

Yes, I have code working that dynamically sets the link speeds and widths.
The only board I have tested it on is the hdama, and it seems to work.
The code now is messy, as we originally had it in the early setup, but needed
more registers in the rom c compiler than were available, so we moved
it to the PCI setup.  It presently works by calculating the values and
comparing them to the ones presently set.  If they are different, they are
set to the correct values, and a reset is done.  I am using a reset because
I have not yet been able to get the LDTSTOP_L to work.  The system
reboots and the next time the routine is run, the values in the registers
are correct, so the reset is not done, and the system continues to boot.

I am presently rewriting the routines without optimizing registers, so it is
more understandable.  I will make the code available when it is done.

I looked at the link_speed.c and link_width.c routines.  The reg_a and reg_b
settings will not work for the following reasons:  The upstream link may be
a host or a slave.  For example on the hdama the uplink is a host for the
8131,  and a slave for the 8111.  The speed registers are in a different
location for the slave and host.  The links are not in fixed locations, and are
not all 0x20 in length.  The only fixed location is the start of the link chain
at location 0x34.  For example on the  hdama 8131, 0x34 points to 0xa0,
which points to 0xb8, which points to 0xc0, which is identified by the
capability and flags registers as the needed link entry.

I will let you know of further development.  Tom Zimmerman

>
>
> I checked in cpu and southbridge dependent parts of LDTSTOP_L assertion,
> they should be operational as soon as we know the link configuration
> from the config file .
>
> The static tree generated at the moment seems not right to me:
> for the one cpu that is actually configured, several nodes are
> generated:
>
> struct chip static_dev9 = {
> /* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/k8 */
>   .next = &static_dev8,
> };
> struct chip static_dev8 = {
> /* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/k7 */
>   .next = &static_dev7,
> };
> struct chip static_dev7 = {
> /* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/p6 */
>   .next = &static_dev6,
> };
> struct chip static_dev6 = {
> /* cpu /home/stepan/LinuxBIOS/freebios2/src/cpu/p5 */
>   .next = &static_dev5,
> };
>
> I assume this is to allow callbacks for each cpu type the k8
> "implements" at the right place. but it looks really nasty. And
> it seems that there are no callbacks anyways here. Or am I wrong?
>
> Is this really needed? It looks like this should be one entry for every
> cpu that can be plugged into the system, plus for every bridge on the
> system.
>
> In the config file this shows up as:
>
>  option i686=1
>  option i586=1
>  option INTEL_PPRO_MTRR=1
>  option k7=1
>  option k8=1
>
> Ron, is it already possible to add information on links between the
> cht and ncht devices?
>
> The chain i want to describe looks pretty much like:
>
>        K8-CPU[2] ------- K8-CPU[3]
>           |                 |
>           |                 |
>        K8-CPU[0] ------- K8-CPU[1]
>           |                 |
>           |                 |
>        8111-SB[0]        8131-SB[0]
>
> with possibly multiple bridges of the same type.
>
> Stefan
>
>   ------------------------------------------------------------------------
>
>    link_speed.cName: link_speed.c
>                Type: Plain Text (text/plain)
>
>    link_width.cName: link_width.c
>                Type: Plain Text (text/plain)



From rminnich at lanl.gov  Fri Jul 25 13:07:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 13:07:01 2003
Subject: Questions on BX Chipset
In-Reply-To: <200307232138.38851.meinrad.sauter@gmx.de>
Message-ID: <Pine.LNX.4.44.0307251120420.893-100000@maxroach.lanl.gov>

On Wed, 23 Jul 2003, Meinrad Sauter wrote:

> - VGA: The Multitainer has an onboard MPACT2 Graphics adapter. It would be 
> nice to have, but not really required. From the docs, I think I could make it 
> work using ADLO or with the builtin VGA support. What do you think?

it would be cool if you would test the builtin VGA support and let us know 
how it goes.

ron



From rminnich at lanl.gov  Fri Jul 25 13:15:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 13:15:00 2003
Subject: coherent hypertransport hardcodes.
In-Reply-To: <3F2157FB.184A8ACF@lnxi.com>
Message-ID: <Pine.LNX.4.44.0307251128460.893-100000@maxroach.lanl.gov>

Stefan, I just fixed that 'False' bug.

ron



From YhLu at tyan.com  Fri Jul 25 14:48:00 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jul 25 14:48:00 2003
Subject: Fixes for Tyan s2880
Message-ID: <3174569B9743D511922F00A0C943142302FC9BF6@TYANWEB>

Ron,

It seems that you roll back to the tree, because of Stefan's complain.

I want to give detail description on the coherent_ht.c and raminit.c
1. coherent_ht.c  add two function: notify_bsp_ap_is_stopped. And
wait_ap_stop.
2. raminit.c change csbase counting methods.

Any way you at least can put files on s2880 for me.

Also please send the Config.lb to me and I would to test the new config
tool.

Thanks.

Regards

Yinghai Lu
-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?7?24? 21:31
???: linuxbios at clustermatic.org
??: Fixes for Tyan s2880

Yh Lu needed to add a mainboard-specific initialization code for the Tyan
s2880 board, and needed it called at a special place in hardwaremain(). In
V1, we would use defines and other such trickery to get this capability.
We're trying to avoid that in V2.

This problem turns out to be a perfect use for the static device
initialization support.

First, we apply patches that are tyan-only or are bug fixes to these files:

src/include/device/pci_ids.h
src/mainboard/tyan/s2880/auto.c
src/mainboard/tyan/s2880/Config
src/mainboard/tyan/s2880/debug.c
src/mainboard/tyan/s2880/failover.c
src/mainboard/tyan/s2880/static_devices.c
src/mainboard/tyan/s2880/tyan-fallback.config
src/mainboard/tyan/s2880/tyan-normal.config
src/mainboard/tyan/s2880/VERSION
src/mainboard/tyan/VERSION
src/northbridge/amd/amdk8/coherent_ht.c
src/northbridge/amd/amdk8/raminit.c
src/southbridge/amd/amd8111/Config
src/southbridge/amd/amd8111/Config.lb
src/southbridge/amd/amd8131/amd8131_bridge.c
targets/tyan/s2880/Config.lb

Now, we need to ensure that YhLu's "special code" is called for his
mainboard. 

As it happens, the mainboard is also a "chip" in the new scheme. The
config tool builds a tree based on this structure, from 
src/include/device/chip.h: 

struct chip {
  struct chip_control *control; /* for this device */
  char *path; /* can be 0, in which case the default is taken */
  char *configuration; /* can be 0. */
  int irq;
  struct chip *next, *children;
  /* there is one of these for each INSTANCE of a chip */
  void *chip_info; /* the dreaded "void *" */
};

The tree for the s2880 looks like this:

=====
#include <device/chip.h>
struct chip static_root, static_dev1, static_dev2, static_dev3, static_dev4,
sta
tic_dev5, static_dev6, static_dev7, static_dev8, static_dev9, static_dev10;
#include "/home/rminnich/src/bios/freebios2/src/mainboard/tyan/s2880/chip.h"

struct chip static_root = {
/* mainboard /home/rminnich/src/bios/freebios2/src/mainboard/tyan/s2880 */
  .children = &static_dev9,
};
struct chip static_dev9 = {
/* cpu /home/rminnich/src/bios/freebios2/src/cpu/k8 */
  .next = &static_dev8,
};

.
.
.

======

(the rest is removed for clearness)

Note that there are even "chips" for CPUs: it is possible to handle
CPU fixup in this system. 

Each entry in the above structures defines a static device. 

Please recall that static devices consist of a generic structure and then 
special-purpose (device specific) structures. 

The generic structure is this:
/* there is one of these for each TYPE of chip */
struct chip_control {
  void (*enable)(struct chip *, enum chip_pass);
  char *path;     /* the default path. Can be overridden
                   * by commands in config
                   */
  // This is the print name for debugging
  char *name;
};

Device-specific classes are defined by the attributes of the device, and
hence vary for each device. In the V1 days, we tried to have one 
generic structure, but that did not even work for the limited case
of superio's, so for V2 we are making the structure unique to 
each device. 

We have to define one device structure for the Tyan s2880. 
The structure has to be defined in an include file that is in the 
directory that contains the code for the device. So, for the 
tyan s2880 mainboard, we need to have a definition file in 
src/mainboard/tyan/s2880. We'll call it src/mainboard/tyan/s2880/chip.h. 

In this case, it is rather simple:

struct mainboard_tyan_s2880_config {
        int fixup_scsi;
};

This is the only thing we're controlling at present. Note that the name of 
the struct is a 'flattened' version of the device name.

We need to tell the config tool where to find the file containing the 
structure, and how to initialize the struct in the file.
Add these lines to src/tyan/s2880/Config.lb. They will define the name of
the 
file to use, and the code to initialize the static device. 

config chip.h 
register "fixup_scsi" = "1"

We need to create the structure that defines the generic structure for the 
mainboard, so linuxbios can hook into it. So add these lines to the end
of src/mainboard/tyan/s2880/mainboard.c:

struct chip_control mainboard_tyan_s2880_control = {
                enable: enable,
                name:   "Tyan s2880 mainboard "
};

Then add the enable function (BEFORE the struct chip_control declaration).
Note that it is declared 'static', and has only one entry in the 
switch. 

static void
enable(struct chip *chip, enum chip_pass pass)
{

        struct mainboard_tyan_s2880_config *conf =
                (struct mainboard_tyan_s2880_config *)chip->chip_info;

        switch (pass) {
                default: break;
                case CONF_PASS_PRE_BOOT:
                         if (conf->fixup_scsi)
                                onboard_scsi_fixup();
                        printk_debug("mainboard fixup pass %d done\r\n",
                                        pass);
                        break;
        }

}

That's pretty much it. total changes are 170 lines.
The static device tree (which is generated by the config tool, you 
don't have to write this code) now looks like this:

==========
#include <device/chip.h>
struct chip static_root, static_dev1, static_dev2, static_dev3, static_dev4,
sta
tic_dev5, static_dev6, static_dev7, static_dev8, static_dev9, static_dev10;
#include "/home/rminnich/src/bios/freebios2/src/mainboard/tyan/s2880/chip.h"
extern struct chip_control mainboard_tyan_s2880_control;
struct mainboard_tyan_s2880_config mainboard_tyan_s2880_config_0        = {
  .fixup_scsi = 1,
};

struct chip static_root = {
/* mainboard /home/rminnich/src/bios/freebios2/src/mainboard/tyan/s2880 */
  .children = &static_dev9,
  .control= &mainboard_tyan_s2880_control,
  .chip_info = (void *) &mainboard_tyan_s2880_config_0,
};
struct chip static_dev9 = {
/* cpu /home/rminnich/src/bios/freebios2/src/cpu/k8 */
  .next = &static_dev8,
};
=====

Note that the mainboard now has several new entries, and there
is a new struct for controlling the mainboard, along with an 
initializer. The enable function for the mainboard will be called at several

places in hardwaremain with a different pass #, and since there is 
only one case defined, only one action is taken. 


So to add this capability for this mainbard, we had to:
- define a file containing the device-specific structure which 
  we called chip.h, and placed in src/mainboard/tyan/s2880
- add two lines to src/mainboard/tyan/s2880/Config.lb, which 
  define the file we need (chip.h) and the initialization of 
  the structure. 
- add the "base class" structure to src/mainboard/tyan/s2880/mainboard.c,
  along with the enable function. 

I've built this mainboard and hexdump of the romimage looks pretty good.
Yh Lu, can you please verify this? The config.lb is in
targets/tyan/s2880/Config.lb.  I can send the context diffs if that will
help.

Note that this technique will work for anything that the config tool 
considers a 'device': mainboard, cpu, north and south bridge, superio, 
etc.

Thanks

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From rminnich at lanl.gov  Fri Jul 25 14:51:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 14:51:00 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9BF6@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307251304020.893-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, YhLu wrote:

> It seems that you roll back to the tree, because of Stefan's complain.

no, I did not roll anything back. Did something roll back?

Or are you seeing the 24-hour sourceforge.net delay?

ron



From YhLu at tyan.com  Fri Jul 25 14:58:01 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jul 25 14:58:01 2003
Subject: Fixes for Tyan s2880
Message-ID: <3174569B9743D511922F00A0C943142302FC9BF7@TYANWEB>

Maybe you are right, becase I can not see any update on s2880 dir. And can
not get config.lb and chip.c that you prepare for me.

Can you send those files to me?

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?7?25? 12:05
???: YhLu
??: linuxbios at clustermatic.org
??: Re: Fixes for Tyan s2880

On Fri, 25 Jul 2003, YhLu wrote:

> It seems that you roll back to the tree, because of Stefan's complain.

no, I did not roll anything back. Did something roll back?

Or are you seeing the 24-hour sourceforge.net delay?

ron


From rsmith at bitworks.com  Fri Jul 25 16:18:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Fri Jul 25 16:18:01 2003
Subject: Questions on BX Chipset
In-Reply-To: <Pine.LNX.4.44.0307251120420.893-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307251120420.893-100000@maxroach.lanl.gov>
Message-ID: <3F219378.9090104@bitworks.com>

ron minnich wrote:

> On Wed, 23 Jul 2003, Meinrad Sauter wrote:

>>- VGA: The Multitainer has an onboard MPACT2 Graphics adapter. It would be 
>>nice to have, but not really required. From the docs, I think I could make it 
>>work using ADLO or with the builtin VGA support. What do you think?
> 
> it would be cool if you would test the builtin VGA support and let us know 
> how it goes.
> 

2nd that.  Last time I tried the builtin VGA stuff I was unable to get 
it to compile but the problem didn't seem to happen for Ron.  So please 
try the builtin support.  Lots of stuff has changed since then and I 
haven't re-tested.

You should be able to make it work with ADLO no problem.  Find my ADLO 
440bx loader patch in the archives and locate the bios image in the 
right spot.


-- 
Richard A. Smith
rsmith at bitworks.com




From rsmith at bitworks.com  Fri Jul 25 17:04:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Fri Jul 25 17:04:00 2003
Subject: Questions on BX Chipset
In-Reply-To: <200307232138.38851.meinrad.sauter@gmx.de>
References: <200307232138.38851.meinrad.sauter@gmx.de>
Message-ID: <3F219E3C.7080001@bitworks.com>

Meinrad Sauter wrote:

I'm just now reading the original post.... Missed it earlier.

> - Soft Power-Off: I used the APM-BIOS in my Original Setup for this. I 
> understand that LinuxBIOS doesn't implement such BIOS functions. I also found 
> a kernel patch that implements this feature for SIS-Chipsets. Is there a 
> possibility to get that thin running on a BX board?

ADLO might help you here but I don't remember if it supports APM or not. 
  I'm also not sure if the Bochs bios code is still going to be  present 
in ram after you boot linux.

> - HD-Spindown: Same as above, simply doesnt work with my current LinuxBIOS 
> setup

I though hdparm could do this.

> - VGA: The Multitainer has an onboard MPACT2 Graphics adapter. It would be 
> nice to have, but not really required. From the docs, I think I could make it 
> work using ADLO or with the builtin VGA support. What do you think?

See my other post.

> - Wake on RTC: Not even the original BIOS supported this. Anyway I don't think 
> its a hardware limitation. Do you think it is possible to implement this for 
> LinuxBIOS?

There is an internal RTC in the 440bx which supports an alarm function 
via irq8.  These pins are also muxed with some GPIO.  So it's not a 
limit of the 440bx but it might be a limit of your motherboard depending 
on what they did with those pins. If they are using that pin as a GPI 
then I don't think you can enable the internal IRQ8.  Or if they have an 
external IRQ8 you will have problems as well.  Unless of course its an 
external RTC.  But I don't know why you would do that when an internal 
one exists already.

Either way there isn't any software support for it in Linuxbios.  Doing 
a suspend requires lots of register saving and then restoring in the 
right order.  I'm not even sure if all the documentation on what 
registers to set/read is available via the Intel's site docs.  Some 
reverse engineering with a 440bx based laptop system might have to occur.

-- 
Richard A. Smith
rsmith at bitworks.com




From rminnich at lanl.gov  Fri Jul 25 17:25:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jul 25 17:25:00 2003
Subject: Questions on BX Chipset
In-Reply-To: <3F219E3C.7080001@bitworks.com>
Message-ID: <Pine.LNX.4.44.0307251537510.893-100000@maxroach.lanl.gov>

On Fri, 25 Jul 2003, Richard Smith wrote:

> Meinrad Sauter wrote:
> 
> I'm just now reading the original post.... Missed it earlier.
> 
> > - Soft Power-Off: I used the APM-BIOS in my Original Setup for this. I 
> > understand that LinuxBIOS doesn't implement such BIOS functions. I also found 
> > a kernel patch that implements this feature for SIS-Chipsets. Is there a 
> > possibility to get that thin running on a BX board?
> 
> ADLO might help you here but I don't remember if it supports APM or not. 
>   I'm also not sure if the Bochs bios code is still going to be  present 
> in ram after you boot linux.

I would recommend extending the power patches I made to linux long ago. 
These patches allower soft power off and reset.

> 
> > - HD-Spindown: Same as above, simply doesnt work with my current LinuxBIOS 
> > setup
> 
> I though hdparm could do this.

I thought so too ...

ron



From Phreak_Show at gmx.de  Sat Jul 26 05:05:01 2003
From: Phreak_Show at gmx.de (Stefan)
Date: Sat Jul 26 05:05:01 2003
Subject: GA-7DXR
Message-ID: <3F2246DC.309@gmx.de>

Some weeks ago, I wanted to know if my Gigabyte GA-7DXR is compatible 
with the LinuxBIOS, and ron asked my something about the serial, etc, 
written on the surface of the bios rom!
Now, here's it:

HYUNDAI      KOR
HY20F002TC-
90                   0119A

There was also a kind of sticker on it, on which was written:

PhoenixBIOS
D686 BIOS
006919492

I hope you can help me now, thx & greetings



From han2004 at hotmail.com  Sat Jul 26 11:00:01 2003
From: han2004 at hotmail.com (gimyung han)
Date: Sat Jul 26 11:00:01 2003
Subject: how can I tell dhcp server to load vmlinuz.epia
Message-ID: <BAY2-F17SA1XvpFVjCR00006529@hotmail.com>

I thought I succeed in configuring dhcp server. 

But I can't check if dhcp server is working right.

are there any messages to be poped up when my epia found dhcp server?

Another question.............  After I succeed in configuring dhcp server, 
how can I tell server to load vmlinux.epia.

I just made vmliuz.epia using mkelfImage tool.


I'll gladly thank for any help.........

I'm just beginner............

_________________________________________________________________
MSN Messenger? ?? ????? ?? ??? ??? ????.   
http://messenger.msn.co.kr  



From ts1 at tsn.or.jp  Sat Jul 26 13:26:01 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Sat Jul 26 13:26:01 2003
Subject: Can you help me?     I'm working on VIA-EPIA
In-Reply-To: <Pine.LNX.4.44.0307242237590.30809-100000@maxroach.lanl.gov>
References: <20030724172510.GA21107@tsn.or.jp> <Pine.LNX.4.44.0307242237590.30809-100000@maxroach.lanl.gov>
Message-ID: <20030726173932.GA18803@tsn.or.jp>

On Thu, Jul 24, 2003 at 10:38:08PM -0600, ron minnich wrote:
> I committed these patches, please test.

It compiles and works fine for me.

Btw, Ron, could you commit my other fix to elfboot.c in the freebios tree?
It's a trivial bug fix, the freebios2 tree seems already 
has that fix applied by Eric.


Index: elfboot.c
===================================================================
RCS file: /cvsroot/freebios/freebios/src/lib/elfboot.c,v
retrieving revision 1.15
diff -u -r1.15 elfboot.c
--- elfboot.c	10 Oct 2002 22:23:43 -0000	1.15
+++ elfboot.c	26 Jul 2003 17:37:56 -0000
@@ -368,6 +368,7 @@
 	int i;
 	memset(head, 0, sizeof(*head));
 	head->next = head->prev = head;
+	head->phdr_next = head->phdr_prev = head;
 	for(i = 0; i < headers; i++) {
 		struct segment *new;
 		/* Ignore data that I don't need to handle */


From yhlu at tyan.com  Sat Jul 26 18:28:00 2003
From: yhlu at tyan.com (Yinghai Lu)
Date: Sat Jul 26 18:28:00 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <Pine.LNX.4.44.0307251304020.893-100000@maxroach.lanl.gov>
Message-ID: <000001c353c6$c6dc9240$9ab6ca3f@yhlunb>

Ron,

The image that is built via the new config tool can work as the old
config tools last night.
CHIP_CONFIGURE is workable too. It will be very useful to device config
or disable some device.

I can send you the diff next Monday if you want.

I add LINUXBIOS_EXTRA_VERSION to the Option.lb in the config. Use that
We can diff from normal boot to fallback boot in the output.

Change some #ifdef to #if CONFIG_SMP==1....

Also please verify
1. Several CONFIG_MAX_CPUS using in the source code, You may need to
select one from CONFIG_MAX_CPUS and
MAX_CPUS.....CONFIG_MAX_PHYSICAL_CPUS.....
Since all SMP have been changed to CONFIG_SMP, and Will you use
CONFIG_MAX_CPUS etc instead of MAX_CPUS etc...
2. Config.lb in arch/i386/smp, missed secondary.S.need to remove the #.
3. _RAMBASE default is 0x100000 in the new Config , and it is not
working with SMP. In hardwaremain(), can not start the second CPU. Need
to change to 0x4000 as the old config tool did.
4. You need to remove make.base.lb, since the function has been replaced
by the above Config.lb.  the rule control make linuxbios.rom.

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?7?25? 14:44
???: YhLu
??: Re: Fixes for Tyan s2880

On Fri, 25 Jul 2003, YhLu wrote:

> 1. I have tried to add lines
> In targets/tyan/s2880/Config.lb
> 
> Uses CONFIG_LSI_SCSI_FW_FIXUP
> Option CONFIG_LSI_SCSI_FW_FIXUP=1

you shouldn't need to do that at all. What code depends on it? 

As I set up the code, this should just be working right now. We need to 
talk about what you need to do, I may have gotten part of it wrong.

> 
> 2. Another problem:
> In Makefile newconfig tool it creates, it says
> "linuxbios.rom: linuxbios.strip buildrom
> 	./buildrom $< $@ $(PAYLOAD) $(ROM_IMAGE_SIZE) $(ROM_SIZE)"
> 
> can you change ROM_SIZE to ROM_SECTION_SIZE?

committed.

> You also changes the standing for linuxbios.rom. old tool it doesn't
include
> pay load and only romimage include payload, if so you should discard
> romimage define.

fixed and committed. 

Thanks very much for working with the new tool.

ron



From agnew at cs.umd.edu  Sat Jul 26 18:33:00 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Sat Jul 26 18:33:00 2003
Subject: Intel Firmware Hubs
In-Reply-To: <000001c353c6$c6dc9240$9ab6ca3f@yhlunb>
Message-ID: <20030726185906.I10188-100000@www.missl.cs.umd.edu>

What's the deal with Intel's firmware hubs? The status file for
Clearwaters seems to indicate that only an Intel firmware hub will do.. Is
that the case, or should I still be able to use a standard plcc flash
part? This is an unforseen snag for someone without a flash programmer..

- Adam Agnew



From rminnich at lanl.gov  Sat Jul 26 23:50:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Jul 26 23:50:01 2003
Subject: GA-7DXR
In-Reply-To: <3F2246DC.309@gmx.de>
Message-ID: <Pine.LNX.4.44.0307262202580.18274-100000@maxroach.lanl.gov>

On Sat, 26 Jul 2003, Stefan wrote:

> Some weeks ago, I wanted to know if my Gigabyte GA-7DXR is compatible 
> with the LinuxBIOS, and ron asked my something about the serial, etc, 
> written on the surface of the bios rom!


> Now, here's it:
> 
> HYUNDAI      KOR
> HY20F002TC-
> 90                   0119A

a 256KByte part. Can you send that lspci again? 

Also is this a little square part or a long 32-pin part?

ron



From rminnich at lanl.gov  Sat Jul 26 23:54:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Jul 26 23:54:00 2003
Subject: Intel Firmware Hubs
In-Reply-To: <20030726185906.I10188-100000@www.missl.cs.umd.edu>
Message-ID: <Pine.LNX.4.44.0307262207160.18274-100000@maxroach.lanl.gov>

On Sat, 26 Jul 2003, Adam Agnew wrote:

> 
> What's the deal with Intel's firmware hubs? The status file for
> Clearwaters seems to indicate that only an Intel firmware hub will do.. Is
> that the case, or should I still be able to use a standard plcc flash
> part? This is an unforseen snag for someone without a flash programmer..

you have to use the 82801ab or ac parts. They are easy to get, I got mine 
from avnet.

BE SURE to ask for N82801AB or N82801AC. Their search tools need the 
exact name.

ron



From jpipkins at austin.rr.com  Sun Jul 27 05:53:00 2003
From: jpipkins at austin.rr.com (Jeff Pipkins)
Date: Sun Jul 27 05:53:00 2003
Subject: coherent hypertransport hardcodes.
References: <20030725135847.GA9591@suse.de> <Pine.LNX.4.44.0307250933050.893-100000@maxroach.lanl.gov> <20030725162415.GA27430@suse.de>
Message-ID: <3F23A429.7090207@austin.rr.com>

Just a reminder (in case this isn't complicated enough yet), on 
configurations with nc chains like k8=>8131->8111 or k8=>8131->8131, the 
link downstream from the 8131 has to be 8 bits wide, even if it has 16 
bits coming into it.

--Jeff




From thomas at wehrspann.de  Sun Jul 27 08:30:01 2003
From: thomas at wehrspann.de (Thomas Wehrspann)
Date: Sun Jul 27 08:30:01 2003
Subject: CVS three broken ???
In-Reply-To: <20030724182424.38275.qmail@web13903.mail.yahoo.com>
References: <20030724182424.38275.qmail@web13903.mail.yahoo.com>
Message-ID: <200307271441.43547.thomas@wehrspann.de>

Am Donnerstag, 24. Juli 2003 20:24 schrieb kdemirev at yahoo.com:
> Can not cvs the three !!
>
> cvs -z3
> -d:pserver:anonymous at cvs.freebios.sourceforge.net:/cvsroot/freebios
> co freebios
>
> stops forever after next message:
>
> U freebios/util/webconfig/var/pyservlog
>
It's the last file, not really important.
Just CTRL-C then works for me.

Thomas


From han2004 at hotmail.com  Sun Jul 27 10:10:01 2003
From: han2004 at hotmail.com (gimyung han)
Date: Sun Jul 27 10:10:01 2003
Subject: Unknown bootloader class !! error.......... what is this?
Message-ID: <BAY2-F57kWSxlXpskAd00007a86@hotmail.com>

I finally succeed to load linux kernel image via etherboot............

but I encountered following error

Loading 192.168.0.1: 
/tftpboot/vmlinuz.epia...(ELF)..............................erhine disable

Unknown bootloader class !
type= 00000000
data= 0009882e
Firmware type: LinuxBIOS


it's all I got................

I made kernel image on the host computer( p4-2.65GHz, 512ddr)

Of course, its configuration is fit for my host computer.

Thanks for any help......................


From ts1 at tsn.or.jp  Sun Jul 27 12:14:00 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Sun Jul 27 12:14:00 2003
Subject: Unknown bootloader class !! error.......... what is this?
In-Reply-To: <BAY2-F57kWSxlXpskAd00007a86@hotmail.com>
References: <BAY2-F57kWSxlXpskAd00007a86@hotmail.com>
Message-ID: <20030727162752.GA25981@tsn.or.jp>

On Sun, Jul 27, 2003 at 02:24:10PM +0000, gimyung han wrote:
> Unknown bootloader class !
> type= 00000000
> data= 0009882e

This is from setup code of your ELF kernel, and it's not an error,
just a warning.

> Firmware type: LinuxBIOS
> it's all I got................

If you configure your kernel to have console on serial port
and give the command line like "console=ttyS0,115200"
to the kernel (at mkelfImage), you should see the messages from
kernel in addition to the above lines.

> I made kernel image on the host computer( p4-2.65GHz, 512ddr)
> 
> Of course, its configuration is fit for my host computer.

EPIA doesn't boot with kernel optimized for P4,
because C3 processor doesn't have CMOV instructions.
You should use a kernel compiled for C3.


--
Takeshi


From thomas at wehrspann.de  Sun Jul 27 13:58:01 2003
From: thomas at wehrspann.de (Thomas Wehrspann)
Date: Sun Jul 27 13:58:01 2003
Subject: K7SEM support broken in freebios?
Message-ID: <200307272010.09229.thomas@wehrspann.de>

Hello, 

is seems that the support for the ecs k7sem got broken.
When i use the current CVS copiling is no problem, but when i boot
linuxbios stops before the mtrr stuff with "Enabling cache...".

I followed the procedure in the howto and used the serial console (no debug).

The CVS version from 2003-04-01 works, the one from 2003-05-01 works not.


Thomas


From pyro at linuxlabs.com  Sun Jul 27 15:03:01 2003
From: pyro at linuxlabs.com (steven james)
Date: Sun Jul 27 15:03:01 2003
Subject: Intel Firmware Hubs
In-Reply-To: <20030726185906.I10188-100000@www.missl.cs.umd.edu>
Message-ID: <Pine.LNX.4.21.0307271514250.12132-100000@ucontrol.mobiledns.com>

Greetings,

It needs to be a firmware hub as far as I can tell. Those do come in 4 and
8MBIT PLCC versions. From a software standpoint, they behave the same as
any other flash part, it's just something in the electrical specs. SST
makes a compatible part (I can check the part number when I get in
tomorrow.

G'day,
sjames



On Sat, 26 Jul 2003, Adam Agnew wrote:

> 
> What's the deal with Intel's firmware hubs? The status file for
> Clearwaters seems to indicate that only an Intel firmware hub will do.. Is
> that the case, or should I still be able to use a standard plcc flash
> part? This is an unforseen snag for someone without a flash programmer..
> 
> - Adam Agnew
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 

-- 
-------------------------steven james, director of research, linux labs
... ........ ..... ....                    230 peachtree st nw ste 2701
the original linux labs                             atlanta.ga.us 30303
      -since 1995                              http://www.linuxlabs.com
                                   office 404.577.7747 fax 404.577.7743
-----------------------------------------------------------------------




From agnew at cs.umd.edu  Sun Jul 27 19:02:00 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Sun Jul 27 19:02:00 2003
Subject: Intel Firmware Hubs
In-Reply-To: <Pine.LNX.4.21.0307271514250.12132-100000@ucontrol.mobiledns.com>
Message-ID: <20030727192604.T12231-100000@www.missl.cs.umd.edu>

> any other flash part, it's just something in the electrical specs. SST

I think you're right there. The datasheet for the 82802s shows that
they're all 3.3v while a myriad of datasheets i found for other plcc flash
parts were 5v. Good to know. It seems AMD offers a line of low voltage
flash parts as SST must too. Thanks Steven.

- Adam Agnew




From stepan at suse.de  Sun Jul 27 19:32:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Sun Jul 27 19:32:01 2003
Subject: Intel Firmware Hubs
In-Reply-To: <20030727192604.T12231-100000@www.missl.cs.umd.edu>; from agnew@cs.umd.edu on Sun, Jul 27, 2003 at 07:31:41PM -0400
References: <Pine.LNX.4.21.0307271514250.12132-100000@ucontrol.mobiledns.com> <20030727192604.T12231-100000@www.missl.cs.umd.edu>
Message-ID: <20030728014619.A31779@suse.de>

* Adam Agnew <agnew at cs.umd.edu> [030728 01:31]:
> 
> > any other flash part, it's just something in the electrical specs. SST
> 
> I think you're right there. The datasheet for the 82802s shows that
> they're all 3.3v while a myriad of datasheets i found for other plcc flash
> parts were 5v. Good to know. It seems AMD offers a line of low voltage
> flash parts as SST must too. Thanks Steven.

the 49* types should all be 3.3v as well. but i am not sure the pinout
is the same..

Stefan
  
-- 
Architecture Team
    SuSE Linux AG


From ollie at sis.com.tw  Sun Jul 27 21:31:00 2003
From: ollie at sis.com.tw (ollie lho)
Date: Sun Jul 27 21:31:00 2003
Subject: how can I tell dhcp server to load vmlinuz.epia
In-Reply-To: <BAY2-F17SA1XvpFVjCR00006529@hotmail.com>
References: <BAY2-F17SA1XvpFVjCR00006529@hotmail.com>
Message-ID: <1059355756.3345.216.camel@ollie>

On Sat, 2003-07-26 at 23:14, gimyung han wrote:
> I thought I succeed in configuring dhcp server. 
> 
> But I can't check if dhcp server is working right.
> 
> are there any messages to be poped up when my epia found dhcp server?
> 

The message will show the network configurations like netmask, ip 
address etc.

> Another question.............  After I succeed in configuring dhcp server, 
> how can I tell server to load vmlinux.epia.
> 

You have not configure dhcp server completely. In the config file,
you should specify the download file by the "filename" command

	filename "/tftpboot/vmlinux.epia"

DHCP server will send the pathname to Etherboot, etherboot will
aks your tftp server to fetch the file.

> I just made vmliuz.epia using mkelfImage tool.
> 

Move the file to the directory you specify in the filename
command in the DHCP config file.

-- 
ollie lho <ollie at sis.com.tw>



From rminnich at lanl.gov  Mon Jul 28 00:06:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 28 00:06:01 2003
Subject: Unknown bootloader class !! error.......... what is this?
In-Reply-To: <BAY2-F57kWSxlXpskAd00007a86@hotmail.com>
Message-ID: <Pine.LNX.4.44.0307272220160.8104-100000@maxroach.lanl.gov>

did you load a kernel or an elfimage built from a kernel?

You are making good progress.

ron



From rminnich at lanl.gov  Mon Jul 28 00:13:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 28 00:13:00 2003
Subject: Unknown bootloader class !! error.......... what is this?
In-Reply-To: <20030727162752.GA25981@tsn.or.jp>
Message-ID: <Pine.LNX.4.44.0307272220570.8104-100000@maxroach.lanl.gov>

On Mon, 28 Jul 2003, SONE Takeshi wrote:

> On Sun, Jul 27, 2003 at 02:24:10PM +0000, gimyung han wrote:
> > Unknown bootloader class !
> > type= 00000000
> > data= 0009882e
> 
> This is from setup code of your ELF kernel, and it's not an error,
> just a warning.
> 
> > Firmware type: LinuxBIOS
> > it's all I got................
> 
> If you configure your kernel to have console on serial port
> and give the command line like "console=ttyS0,115200"
> to the kernel (at mkelfImage), you should see the messages from
> kernel in addition to the above lines.

Oh, right, you should do this for your very first kernel:
- make it an i386, and turn off all features (mtrr, etc).
- turn off vga consoles
- enable console on serial port

ron




From rminnich at lanl.gov  Mon Jul 28 00:18:43 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 28 00:18:43 2003
Subject: K7SEM support broken in freebios?
In-Reply-To: <200307272010.09229.thomas@wehrspann.de>
Message-ID: <Pine.LNX.4.44.0307272222540.8104-100000@maxroach.lanl.gov>

On Sun, 27 Jul 2003, Thomas Wehrspann wrote:

> When i use the current CVS copiling is no problem, but when i boot
> linuxbios stops before the mtrr stuff with "Enabling cache...".

yes, this is the reason we have not frozen the tree. I am hoping somebody 
can fix the K7sem :-(

ron



From rminnich at lanl.gov  Mon Jul 28 00:24:27 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 28 00:24:27 2003
Subject: Intel Firmware Hubs
In-Reply-To: <20030727192604.T12231-100000@www.missl.cs.umd.edu>
Message-ID: <Pine.LNX.4.44.0307272223550.8104-100000@maxroach.lanl.gov>

On Sun, 27 Jul 2003, Adam Agnew wrote:

> I think you're right there. The datasheet for the 82802s shows that
> they're all 3.3v while a myriad of datasheets i found for other plcc flash
> parts were 5v. Good to know. It seems AMD offers a line of low voltage
> flash parts as SST must too. Thanks Steven.

no, the 82802ac uses address-address multiplexing to get up to 27 bits of 
address. They are a synchronous part whereas many flashes we have used to 
date are not. So the bus, clocking, and timing are nothing like the parts 
we've used on other platforms.

You can only program an 82802ac on a board with support for firmware hub.

ron



From rminnich at lanl.gov  Mon Jul 28 00:31:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 28 00:31:01 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <000001c353c6$c6dc9240$9ab6ca3f@yhlunb>
Message-ID: <Pine.LNX.4.44.0307272230170.8104-100000@maxroach.lanl.gov>

On Sat, 26 Jul 2003, Yinghai Lu wrote:

> I can send you the diff next Monday if you want.

please do.

> 
> I add LINUXBIOS_EXTRA_VERSION to the Option.lb in the config. Use that
> We can diff from normal boot to fallback boot in the output.

very cool.

> 
> Change some #ifdef to #if CONFIG_SMP==1....

thanks, we're still working on them. 


> Also please verify
> 1. Several CONFIG_MAX_CPUS using in the source code, You may need to
> select one from CONFIG_MAX_CPUS and
> MAX_CPUS.....CONFIG_MAX_PHYSICAL_CPUS.....
> Since all SMP have been changed to CONFIG_SMP, and Will you use
> CONFIG_MAX_CPUS etc instead of MAX_CPUS etc...

Eric and Stefan, please pick a name and let us know what it should be. Are 
CONFIG_MAX_CPUS and CONFIG_MAX_PHYSICAL_CPUS the same or different (I'm 
guessing different due to hyperthreading)?

> 2. Config.lb in arch/i386/smp, missed secondary.S.need to remove the #.

I fixed this too, please make sure you have it as I have comitted it.

> 3. _RAMBASE default is 0x100000 in the new Config , and it is not
> working with SMP. In hardwaremain(), can not start the second CPU. Need
> to change to 0x4000 as the old config tool did.

Done and committed. Eric, Stefan, please make sure this is not a problem 
for you, but it looks harmless to me.

> 4. You need to remove make.base.lb, since the function has been replaced
> by the above Config.lb.  the rule control make linuxbios.rom.

Done and committed.

I thank you for using the new tool. We intend to make further changes this 
week as requested by Stefan. I am on vacation so this will not happen as 
quickly as I would wish, but it should happen. I think we are getting 
closer to the goals we set for the new tool. I know Greg is very happy 
with it for his use on PPC. 

thanks

ron



From stepan at suse.de  Mon Jul 28 03:39:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Jul 28 03:39:00 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <Pine.LNX.4.44.0307272230170.8104-100000@maxroach.lanl.gov>; from rminnich@lanl.gov on Sun, Jul 27, 2003 at 10:38:19PM -0600
References: <000001c353c6$c6dc9240$9ab6ca3f@yhlunb> <Pine.LNX.4.44.0307272230170.8104-100000@maxroach.lanl.gov>
Message-ID: <20030728095053.B1642@suse.de>

* ron minnich <rminnich at lanl.gov> [030728 06:38]:
> Eric and Stefan, please pick a name and let us know what it should be. Are 
> CONFIG_MAX_CPUS and CONFIG_MAX_PHYSICAL_CPUS the same or different (I'm 
> guessing different due to hyperthreading)?
 
I agree. Naming CONFIG_MAX_CPUS CONFIG_MAX_LOGICAL_CPUS would imply that
there is a number of max. physical cpus as well.

  Stefan

-- 
Architecture Team
    SuSE Linux AG


From aip at cwlinux.com  Mon Jul 28 03:46:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jul 28 03:46:01 2003
Subject: K7SEM support broken in freebios?
In-Reply-To: <Pine.LNX.4.44.0307272222540.8104-100000@maxroach.lanl.gov>; from ron minnich on Sun, Jul 27, 2003 at 10:23:21PM -0600
References: <200307272010.09229.thomas@wehrspann.de> <Pine.LNX.4.44.0307272222540.8104-100000@maxroach.lanl.gov>
Message-ID: <20030728155404.B5562@mail.cwlinux.com>

Hi,

> yes, this is the reason we have not frozen the tree. I am hoping somebody 
> can fix the K7sem :-(
Could it be the ecc problem?

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From stepan at suse.de  Mon Jul 28 09:11:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Jul 28 09:11:01 2003
Subject: Epia-M
Message-ID: <20030728132541.GA8253@suse.de>

* Thomas Wehrspann <thomas at wehrspann.de> [030727 20:10]:
> is seems that the support for the ecs k7sem got broken.
> When i use the current CVS copiling is no problem, but when i boot
> linuxbios stops before the mtrr stuff with "Enabling cache...".
 
I have a similar problem with the EPIA-M (latest CVS):

Initializing PCI devices...
PCI devices initialized
totalram: 127M
Initializing CPU #0
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
[hang]

Is this due to the 128MB stick I am using? It seems to get recognized
though.


   Stefan







From stepan at suse.de  Mon Jul 28 10:28:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Jul 28 10:28:00 2003
Subject: Epia-M
In-Reply-To: <20030728132541.GA8253@suse.de>
References: <20030728132541.GA8253@suse.de>
Message-ID: <20030728144014.GA1856@suse.de>

* Stefan Reinauer <stepan at suse.de> [030728 15:25]:
> Initializing PCI devices...
> PCI devices initialized
> totalram: 127M
> Initializing CPU #0
> Enabling cache...
> Setting fixed MTRRs(0-88) type: UC
> [hang]
> 
> Is this due to the 128MB stick I am using? It seems to get recognized
> though.

Hm.. reading the archive, this seems to be a problem of only
initializing the first bank of the ram module.. 

Stefan




From rminnich at lanl.gov  Mon Jul 28 10:43:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 28 10:43:01 2003
Subject: K7SEM support broken in freebios?
In-Reply-To: <20030728155404.B5562@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.44.0307280857180.12872-100000@maxroach.lanl.gov>

On Mon, 28 Jul 2003, Andrew Ip wrote:

> > yes, this is the reason we have not frozen the tree. I am hoping somebody 
> > can fix the K7sem :-(
> Could it be the ecc problem?

I think so. Is there a reasonable fix?

ron



From aip at cwlinux.com  Mon Jul 28 12:27:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jul 28 12:27:00 2003
Subject: Epia-M
In-Reply-To: <20030728132541.GA8253@suse.de>; from Stefan Reinauer on Mon, Jul 28, 2003 at 03:25:41PM +0200
References: <20030728132541.GA8253@suse.de>
Message-ID: <20030729004113.B10880@mail.cwlinux.com>

Hi Stefan,

> Is this due to the 128MB stick I am using? It seems to get recognized
> though.
Most likely.  Have you tried different ddr?  A more reliable DDR setup
is on my to-do-list.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From aip at cwlinux.com  Mon Jul 28 12:36:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jul 28 12:36:00 2003
Subject: K7SEM support broken in freebios?
In-Reply-To: <Pine.LNX.4.44.0307280857180.12872-100000@maxroach.lanl.gov>; from ron minnich on Mon, Jul 28, 2003 at 08:57:26AM -0600
References: <20030728155404.B5562@mail.cwlinux.com> <Pine.LNX.4.44.0307280857180.12872-100000@maxroach.lanl.gov>
Message-ID: <20030729004953.C11225@mail.cwlinux.com>

Hi,

> I think so. Is there a reasonable fix?
It should be in the archive.  IIRC, I just skip the ecc setup.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From aip at cwlinux.com  Mon Jul 28 12:58:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jul 28 12:58:00 2003
Subject: Linuxbios and Via M10000, where to start?
In-Reply-To: <1A4E530F40B6D3119E880050041D6DE00412FE82@wntceda3.ceda.polimi.it>; from Barbini Uberto on Wed, Jul 23, 2003 at 09:34:43AM +0200
References: <1A4E530F40B6D3119E880050041D6DE00412FE82@wntceda3.ceda.polimi.it>
Message-ID: <20030729011203.A11518@mail.cwlinux.com>

Hi Barbini,

> I have a via M10000 motherboard and I'm using it with gentoo with kernel
> 2.6.0.test1 and xfree86 latest snap, and acpid for clean poweroff by power
> button.
> All works fine, and I'm quite an happy user.
> I'm wondering if I happiness can grow still more using linuxbios to cut off
> booting time. ;)
> But is there any risk I cannot be able to run the above software? (first
> question)
For EPIA-M10000, I have only tested with no vga and no power managment.
I think Dave has got the X working at some point.
> I'm not sure what I'm supposed to do, after downloading freebios, but I'm
> unsure of its function too. In the donwload page of linuxbios.org there is a
> link to "other software", I have to download that too?
You can follow the HOWTO for EPIA to get started.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From aip at cwlinux.com  Mon Jul 28 13:00:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jul 28 13:00:00 2003
Subject: Mini-ITX
In-Reply-To: <021801c351f5$9d93eaa0$8461cdc2@DREAD>; from John Hearns on Thu, Jul 24, 2003 at 04:09:39PM +0100
References: <021801c351f5$9d93eaa0$8461cdc2@DREAD>
Message-ID: <20030729011428.B11518@mail.cwlinux.com>

Hi John,

> Can I ask for some pointers to ROM images for EPIA-800
> and M10000 Nehemiah boards (I've just got one on order)
> I see the ones on cwlinux.com - which specific boards are these for?
It is for EPIA-800 with no vga.  Because of the license issue, I can't
distribute the +vga version.  I think it should be possible to write
a little script to extract vgabios from the system and then combine it
with linuxbios. 

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From stepan at suse.de  Mon Jul 28 13:37:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Jul 28 13:37:00 2003
Subject: Epia-M
In-Reply-To: <20030729004113.B10880@mail.cwlinux.com>; from aip@cwlinux.com on Tue, Jul 29, 2003 at 12:41:13AM +0800
References: <20030728132541.GA8253@suse.de> <20030729004113.B10880@mail.cwlinux.com>
Message-ID: <20030728195109.A5379@suse.de>

* Andrew Ip <aip at cwlinux.com> [030728 18:41]:
> Hi Stefan,
> 
> > Is this due to the 128MB stick I am using? It seems to get recognized
> > though.
> Most likely.  Have you tried different ddr?  A more reliable DDR setup
> is on my to-do-list.

I tried a different stick from another vendor, but the same thing. What
DDR Ram is known to be good? I saw you initialize for 512MB. I only used
256MB, of which 127 were shown. One was single sided, one double sided.

  Stefan


From YhLu at tyan.com  Mon Jul 28 15:30:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 28 15:30:01 2003
Subject: Fixes for Tyan s2880
Message-ID: <3174569B9743D511922F00A0C943142302FC9D40@TYANWEB>

Ron.

Changes in raminit.c add fill_last function.
So remove following error while kernel booting:

" Scanning NUMA topology in Northbridge 24
Node 0 MemBase 0000000000000000 Limit 000000007fffffff
Node 1 MemBase 0000000080000000 Limit 00000000f0000000
Node map not sorted 80000000,0
No NUMA configuration found
Faking a node at 0000000000000000-00000000f0000000
Bootmem setup node 0 0000000000000000-00000000f0000000
"

To:
" Scanning NUMA topology in Northbridge 24
Node 0 MemBase 0000000000000000 Limit 000000007fffffff
Node 1 MemBase 0000000080000000 Limit 00000000f0000000
Using node hash shift of 24
Bootmem setup node 0 0000000000000000-000000007fffffff
Bootmem setup node 1 0000000080000000-00000000f0000000
"

Is the raminit.c taken care by ERIC? Is he planning to add 4G support in
that?

Regards

Yinghai Lu


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From gwatson at lanl.gov  Mon Jul 28 17:46:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Mon Jul 28 17:46:00 2003
Subject: static initialization
Message-ID: <p06001a08bb4b40f568e7@[10.0.1.2]>

Stefan,

I've added the ability to name parts. This means that you can do the following:

cpu k8 "cpu0"
	register "south" = "&sb0"
	register "east" = "&cpu1"
end

cpu k8 "cpu1"
	register "south" = ...
	register "east" = ...
end

southbridge <device>/<vendor> "sb0"
end

In the k8 directory you will need to add 'config chip.h' to 
Config.lb, then create a chip.h that contains something like:

#ifndef _CPU_K8
#define _CPU_K8

extern struct chip_control cpu_k8_control;

struct cpu_k8_config {
	struct chip *south;
	struct chip *east;
	<any other stuff>
};
#endif /* _CPU_K8 */

Then add an object that contains the code that deals with 
'cpu_k8_control' (see superio/NSC/pc97307/superio.c for an example).

Hopefully this will allow you to deal with the hyperchannel setup stuff.

Things that still need to be done/other changes:

1. The above scheme assumes that all cpu's actually exist, which may 
not be the case. Only the first cpu can be relied on to exist.  So we 
need to think about the best way to indicate that subsequent cpu's 
are optional. One way might be to add the keyword 'optional' to the 
definition. e.g.

cpu k8 "cpu1"
	optional
	register "south" = ...
	register "east" = ...
end

We could add an extra pass to the chip_configure() routine called 
CHIP_PASS_PROBE that is called for all devices that are marked 
optional. It would then be up to the individual device to check for 
its existence. This could set a flag that means the enable() entry 
point is called on subsequent passes for the device.

One problem with this approach is that you've already set the 'south' 
field to point at cpu1. If cpu1 doesn't exist then the probe code 
would need to set this field to 0.

Let me know what you think.

2. Ron is testing replacing:

cpu p5 end
cpu p6 end
cpu k7 end
cpu k8 end

with just 'cpu k8 end', then using the 'dir' command in the k8 
Config.lb file to include support for k7, p6, p5. This will hopefully 
prevent spurious devices from being included in the static tree.

3. You now must declare:

extern struct chip_control part_vendor_device_control;

in the part specific chip.h file.

Cheers,

Greg



From ebiederman at lnxi.com  Mon Jul 28 21:16:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jul 28 21:16:01 2003
Subject: coherent hypertransport hardcodes.
In-Reply-To: <3F23A429.7090207@austin.rr.com>
References: <20030725135847.GA9591@suse.de>
	<Pine.LNX.4.44.0307250933050.893-100000@maxroach.lanl.gov>
	<20030725162415.GA27430@suse.de> <3F23A429.7090207@austin.rr.com>
Message-ID: <m3fzkqw20p.fsf@maxwell.lnxi.com>

Jeff Pipkins <jpipkins at austin.rr.com> writes:

> Just a reminder (in case this isn't complicated enough yet), on configurations
> with nc chains like k8=>8131->8111 or k8=>8131->8131, the link downstream from
> the 8131 has to be 8 bits wide, even if it has 16 bits coming into it.

If you aren't hard coding that one is trivial to get right because the 8131
reports the downstream link is only 8 bits.

Although that is a pretty good case for not chaining two 8131s...

Eric



From YhLu at tyan.com  Mon Jul 28 21:27:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jul 28 21:27:01 2003
Subject: Above 4G RAM
Message-ID: <3174569B9743D511922F00A0C943142302FC9D96@TYANWEB>

Eric,

I have tried following memconfig on Tyan S2880. It seems ok.
4*1G DDR in CPU0 Memory slots.
2*256M DDR in CPU1 Memory slots.

The MB can boot into the end. (Till end). 

If I use all 1G DDR, It can download the image but can not execute it and
reboot again.

Any advise?

Regards

Yinghai Lu



From rminnich at lanl.gov  Mon Jul 28 23:58:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jul 28 23:58:00 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9D40@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307282211570.18907-100000@maxroach.lanl.gov>

Yh Lu, this will take me a little time to integrate your patches, I hope 
to be done tomorrow. Some of the things you have patched I have also 
fixed, but due to the 24-hour delay at sourceforge.net, we are out of 
sync. 

Thanks for your patches, I hpoe to commit by tomorrow.

ron



From leon.woestenberg at gmx.net  Tue Jul 29 05:55:01 2003
From: leon.woestenberg at gmx.net (Leon Woestenberg)
Date: Tue Jul 29 05:55:01 2003
Subject: EPIA-ME6000
Message-ID: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl>

Hello,

I have been fiddling with etherboot 5.0.10 and freebios(v1) from CVS today
on a EPIA-ME6000 platform.

This is the unit with a low speed clock (500MHz?) Eden C3 processor
which copes with passive cooling. I think it is EPIA-M9000 alike otherwise.

Using a hardware flash programmer, I first copied the VIA BIOS from the
STT39SF040A (256Kbytes) into a STMicro 29F040B (512Kbytes) device.

That only worked after I copied the BIOS into the upper half of the larger
device (from 0x40000 to 0x7FFFF). So I recon the highest address line
is not connected on the board and so the FlashROM sees high-impedance
on its most significant address line (and addresses the upper half always)>

I followed the HOWTO/EPIA document to the letter (without the VGA
BIOS at first) booting linuxbios w/ via-rhine.elf payload.

When booting, I merely got garbled output on the serial port.

I have double checked that the config file reads 115200 and that my
terminal reads 115200 8N1. (The 115200 is assembly hardcoded in
the vt82c686 superio code -- does it cope with my different processor
speed? I do not have the datasheet (yet?).

After that, I have tried all speeds on the terminal without result.

Is the EPIA-ME6000 (aka M6000) already reported to work here,
or are you guys'n'gals refering to the M9000 and M10000 alone?

How can I help?

Regards,

Leon.


From paulw at mmail.ath.cx  Tue Jul 29 06:49:00 2003
From: paulw at mmail.ath.cx (paul)
Date: Tue Jul 29 06:49:00 2003
Subject: size of linuxbios
Message-ID: <3F273656.4090802@mmail.ath.cx>

Hi

How big is linuxbios? will 256K byte of flash do? I only have a flash 
burner that will burn 512k byte.
I need to know before I download the source.

Thanks



From stepan at suse.de  Tue Jul 29 06:57:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Jul 29 06:57:01 2003
Subject: size of linuxbios
In-Reply-To: <3F273656.4090802@mmail.ath.cx>
References: <3F273656.4090802@mmail.ath.cx>
Message-ID: <20030729111151.GA1522@suse.de>

* paul <paulw at mmail.ath.cx> [030730 05:07]:
> How big is linuxbios? will 256K byte of flash do? I only have a flash 
> burner that will burn 512k byte.

LinuxBIOS easily fits into 256k, even with etherboot as payload. But if
you intend to burn a Linux Kernel into flash as well, you need at least
1MByte (kernel 2.4+)


Stefan


From ts1 at tsn.or.jp  Tue Jul 29 07:31:01 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Tue Jul 29 07:31:01 2003
Subject: EPIA-ME6000
In-Reply-To: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl>
References: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl>
Message-ID: <20030729114537.GA12529@tsn.or.jp>

On Tue, Jul 29, 2003 at 12:09:11PM +0200, Leon Woestenberg wrote:
> That only worked after I copied the BIOS into the upper half of the larger
> device (from 0x40000 to 0x7FFFF). So I recon the highest address line
> is not connected on the board and so the FlashROM sees high-impedance
> on its most significant address line (and addresses the upper half always)>

I think that it does not mean MSB is not connected.
Since BIOS is expected to live at highest address below 4GB,
you would have to write the 256KB image at highest portion of ROM anyway
if all address lines are connected.

If you had to write it in the lower half, you could say the highest
address line is grounded.

> I followed the HOWTO/EPIA document to the letter (without the VGA
> BIOS at first) booting linuxbios w/ via-rhine.elf payload.

HOWTO/EPIA is written for original EPIA boards like EPIA-5000 or EPIA-800,
not for EPIA-M(E).
Did you use config file for EPIA-M?

--
Takeshi


From bgr at gw.linespeed.net  Tue Jul 29 09:54:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Tue Jul 29 09:54:01 2003
Subject: EPIA-ME6000
In-Reply-To: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl>
References: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl>
Message-ID: <Pine.LNX.4.53.0307290900280.15334@gw.linespeed.net>

That board has a VIA vt82c686b south on it?  I built linuxbios for a
similar VIA board (endat) with an 8601 north and vt82c686b south.  That
won't work with the epia or epia-m configs.  but you can go from the
via/vt5426 config.  You are perhaps getting garbage serial output because
you're setting up serial for the wrong superio.

Have you figured out how to enable flash memory write?  I have two 686
datasheets which seem to contradict one another on how it's done.  one
appears like the 8231 south, and another alike the sis630.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Tue, 29 Jul 2003, Leon Woestenberg wrote:

> Hello,
>
> I have been fiddling with etherboot 5.0.10 and freebios(v1) from CVS today
> on a EPIA-ME6000 platform.
>
> This is the unit with a low speed clock (500MHz?) Eden C3 processor
> which copes with passive cooling. I think it is EPIA-M9000 alike otherwise.
>
> Using a hardware flash programmer, I first copied the VIA BIOS from the
> STT39SF040A (256Kbytes) into a STMicro 29F040B (512Kbytes) device.
>
> That only worked after I copied the BIOS into the upper half of the larger
> device (from 0x40000 to 0x7FFFF). So I recon the highest address line
> is not connected on the board and so the FlashROM sees high-impedance
> on its most significant address line (and addresses the upper half always)>
>
> I followed the HOWTO/EPIA document to the letter (without the VGA
> BIOS at first) booting linuxbios w/ via-rhine.elf payload.
>
> When booting, I merely got garbled output on the serial port.
>
> I have double checked that the config file reads 115200 and that my
> terminal reads 115200 8N1. (The 115200 is assembly hardcoded in
> the vt82c686 superio code -- does it cope with my different processor
> speed? I do not have the datasheet (yet?).
>
> After that, I have tried all speeds on the terminal without result.
>
> Is the EPIA-ME6000 (aka M6000) already reported to work here,
> or are you guys'n'gals refering to the M9000 and M10000 alone?
>
> How can I help?
>
> Regards,
>
> Leon.
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From rminnich at lanl.gov  Tue Jul 29 10:48:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 29 10:48:01 2003
Subject: size of linuxbios
In-Reply-To: <3F273656.4090802@mmail.ath.cx>
Message-ID: <Pine.LNX.4.44.0307290902260.23508-100000@maxroach.lanl.gov>

On Tue, 29 Jul 2003, paul wrote:

> How big is linuxbios? will 256K byte of flash do? I only have a flash
> burner that will burn 512k byte. I need to know before I download the
> source.

yes, 256KB is plenty for linuxbios + etherboot.

ron



From aip at cwlinux.com  Tue Jul 29 11:34:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jul 29 11:34:01 2003
Subject: EPIA-ME6000
In-Reply-To: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl>; from Leon Woestenberg on Tue, Jul 29, 2003 at 12:09:11PM +0200
References: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl>
Message-ID: <20030729234846.A26008@mail.cwlinux.com>

Hi Leon,

> I have been fiddling with etherboot 5.0.10 and freebios(v1) from CVS today
> on a EPIA-ME6000 platform.
> This is the unit with a low speed clock (500MHz?) Eden C3 processor
> which copes with passive cooling. I think it is EPIA-M9000 alike otherwise.
> Using a hardware flash programmer, I first copied the VIA BIOS from the
> STT39SF040A (256Kbytes) into a STMicro 29F040B (512Kbytes) device.
> That only worked after I copied the BIOS into the upper half of the larger
> device (from 0x40000 to 0x7FFFF). So I recon the highest address line
> is not connected on the board and so the FlashROM sees high-impedance
> on its most significant address line (and addresses the upper half always)>
> I followed the HOWTO/EPIA document to the letter (without the VGA
> BIOS at first) booting linuxbios w/ via-rhine.elf payload.
> When booting, I merely got garbled output on the serial port.
> I have double checked that the config file reads 115200 and that my
> terminal reads 115200 8N1. (The 115200 is assembly hardcoded in
> the vt82c686 superio code -- does it cope with my different processor
> speed? I do not have the datasheet (yet?).
> After that, I have tried all speeds on the terminal without result.
> Is the EPIA-ME6000 (aka M6000) already reported to work here,
> or are you guys'n'gals refering to the M9000 and M10000 alone?
> How can I help?
Have you tried 57600?  EPIA-M6000 seems to have problem to use 115200
under LinuxBIOS unless it is boot from normal bios and then reset the
system.  That's why you are getting garbage.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From bari at onelabs.com  Tue Jul 29 12:17:00 2003
From: bari at onelabs.com (Bari Ari)
Date: Tue Jul 29 12:17:00 2003
Subject: EPIA-ME6000
In-Reply-To: <20030729234846.A26008@mail.cwlinux.com>
References: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl> <20030729234846.A26008@mail.cwlinux.com>
Message-ID: <3F26A159.5010902@onelabs.com>

Andrew Ip wrote:

>
>Have you tried 57600?  EPIA-M6000 seems to have problem to use 115200
>under LinuxBIOS unless it is boot from normal bios and then reset the
>system.  That's why you are getting garbage.
>
>  
>
Any idea why? Broken hardware? Undocumented setups for the serial port?

-Bari




From aip at cwlinux.com  Tue Jul 29 12:59:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jul 29 12:59:00 2003
Subject: EPIA-ME6000
In-Reply-To: <3F26A159.5010902@onelabs.com>; from Bari Ari on Tue, Jul 29, 2003 at 11:31:21AM -0500
References: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl> <20030729234846.A26008@mail.cwlinux.com> <3F26A159.5010902@onelabs.com>
Message-ID: <20030730011359.A27075@mail.cwlinux.com>

Hi,

> Any idea why? Broken hardware? Undocumented setups for the serial port?
Most likely undocumented setup, 'coz my code works on another custom
board with the same chipset.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From leon.woestenberg at gmx.net  Tue Jul 29 19:51:01 2003
From: leon.woestenberg at gmx.net (Leon Woestenberg)
Date: Tue Jul 29 19:51:01 2003
Subject: EPIA-ME6000
References: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl> <20030729234846.A26008@mail.cwlinux.com>
Message-ID: <007e01c3562e$3c1661d0$17f09b83@campus.tue.nl>

Hello Andrew,

> > I have been fiddling with etherboot 5.0.10 and freebios(v1) from CVS
today
> > on a EPIA-ME6000 platform.
> > ...
> > When booting, I merely got garbled output on the serial port.
> > I have double checked that the config file reads 115200 and that my
> > terminal reads 115200 8N1. (The 115200 is assembly hardcoded in
> > the vt82c686 superio code -- does it cope with my different processor
>
> Have you tried 57600?  EPIA-M6000 seems to have problem to use 115200
> under LinuxBIOS unless it is boot from normal bios and then reset the
> system.  That's why you are getting garbage.
>
> -Andrew
>
Just to make sure; where would I need to set the 57600 bitrate? The file I
have been
looking at is the assembler code file in the vt82c686 directory, which just
sets a
register with some values I cannot compare with a datasheet (as I haven't
found one yet).
Or am I looking at the wrong file here: ?

http://cvs.sourceforge.net/cgi-bin/viewcvs.cgi/freebios/freebios/src/superio/via/vt82c686/setup_serial.inc?rev=1.2&content-type=text/vnd.viewcvs-markup

Also, I blew up my board (probably ESD problem) during replacing the cooling
compounds. :-/
I am waiting for a new one... This _does_ give me an extra (and original)
FlashROM part. :-)

BTW, does anyone know a source for the STT39F020A Flashes? They're hard to
come by here.

Regards,

Leon.



From bgr at gw.linespeed.net  Tue Jul 29 22:08:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Tue Jul 29 22:08:01 2003
Subject: EPIA-ME6000
In-Reply-To: <008401c3562f$d6612c10$17f09b83@campus.tue.nl>
References: <00ba01c355b9$758ecf30$17f09b83@campus.tue.nl>
 <Pine.LNX.4.53.0307290900280.15334@gw.linespeed.net>
 <008401c3562f$d6612c10$17f09b83@campus.tue.nl>
Message-ID: <Pine.LNX.4.53.0307292115060.4405@gw.linespeed.net>

That looks like an EPIA M-10000 compatable board to me.  btw, about flash
parts, you might more easily find the sst29f040 parts.  also macronix makes
compatable parts.  You're lucky it's not a vt82c686b south as linuxbios
does not work very well with that chipset.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Wed, 30 Jul 2003, Leon Woestenberg wrote:

> Hello,
>
> > That board has a VIA vt82c686b south on it?  I built linuxbios for a
> > similar VIA board (endat) with an 8601 north and vt82c686b south.  That
> >
> Whoops, the heatsinked chip doesn't have the vt82c686 designator, instead
> it reads CLE266. You might be right in me setting up the wrong chip there.
>
> Let me just list the chips I can find on the board, just to make sure that
> this
> EPIA-EM6000 is like the M9000 board, before we head of in a wrong
> direction.
>
> VT1211
> VT1622
> VT6103
> VT6307S
> VT8235
> CLE266 (under the heatsink, next to the processor)
>
> Regards,
>
> Leon.
>


From ijpraveen1 at yahoo.com  Tue Jul 29 22:37:00 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Tue Jul 29 22:37:00 2003
Subject: What bootloader is used?
Message-ID: <20030730025139.57457.qmail@web41704.mail.yahoo.com>

                I suppose that linuxbiosmain.c is the program that loads the kernel. Is any bootloader used when booting linux from Flash memory into SDRAM?


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From rminnich at lanl.gov  Tue Jul 29 22:57:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jul 29 22:57:00 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9D40@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307292107090.28725-100000@maxroach.lanl.gov>

OK, I have applied Yh Lu's patches for the most part. In almost all cases 
they are tyan 2880-specific. There are three things I can see that might 
affect others:

#ifdef some-variable 
no longer works in many places, it has to be
#if some-variable == 1

to work.


-  for the new config too, there is no longer a default for _RAMBASE, 
	due to PPC and K8 differences

raminit.c sees the following changes:
Index: src/northbridge/amd/amdk8/raminit.c
===================================================================
RCS file: /cvsroot/freebios/freebios2/src/northbridge/amd/amdk8/raminit.c,v
retrieving revision 1.12
diff -r1.12 raminit.c
921a922,927
> //BY LYH  add IOMMU 64M APERTURE
> 	PCI_ADDR(0, 0x18, 3, 0x94), 0xffff8000, 0x00000f70,
> 	PCI_ADDR(0, 0x18, 3, 0x90), 0xffffff80, 0x00000002,
>         PCI_ADDR(0, 0x18, 3, 0x98), 0x0000000f, 0x00068300,
> 
> //BY LYH END
1119c1125,1141
< 
---
> static void fill_last(unsigned long node_id,unsigned long base)
> {
> //BY LYH //Fill next base reg with right value
>         unsigned i;
>         unsigned base_reg;
>         base &=0xffff0000;
> 	device_t device;
>         for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
> += PCI_DEV(0, 1, 0)) {
>         	for(i=node_id+1;i<=7;i++) {
>                 	base_reg=0x40+(i<<3);
>                  	pci_write_config32(device,base_reg,base);
> 		}
>         }
> //BY LYH END
> }
>  
1128a1151
> 
1145a1169
> 	
1254,1256c1278,1280
< 		print_debug("csbase=");
< 		print_debug_hex32(csbase);
< 		print_debug("\r\n");
---
> //		print_debug("csbase=");
> //		print_debug_hex32(csbase);
> //		print_debug("\r\n");
1285a1310,1312
> //BY LYH
>         fill_last(ctrl->node_id, tom_k<<2);
> //BY LYH END
1288,1291c1315,1319
< 	if(ctrl->node_id==1) {
< 		pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
< 	
< 	}	
---
>         dump_pci_device(PCI_DEV(0, 0x18, 1));
>  
> //	if(ctrl->node_id==1) {
> //		pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
> //	}	


and the amd8111 sees this:

Index: src/southbridge/amd/amd8111/amd8111_ldtstop.c
===================================================================
RCS file: /cvsroot/freebios/freebios2/src/southbridge/amd/amd8111/amd8111_ldtstop.c,v
retrieving revision 1.4
diff -r1.4 amd8111_ldtstop.c
22c22
< 	pci_write_config16(dev, 0x48, pci_read_config16(dev,0x48) & ~CPUPIN);
---
> 	pci_write_config32(dev, 0x48, pci_read_config32(dev,0x48) & ~CPUPIN);
 

If this is trouble, let me know.

You are going to have to set _RAMBASE in your mainboard Config.lb now.

ron



From ebiederman at lnxi.com  Wed Jul 30 01:39:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jul 30 01:39:01 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <Pine.LNX.4.44.0307292107090.28725-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307292107090.28725-100000@maxroach.lanl.gov>
Message-ID: <m3ispkpngz.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> OK, I have applied Yh Lu's patches for the most part. In almost all cases 
> they are tyan 2880-specific. There are three things I can see that might 
> affect others:
> 
> #ifdef some-variable 
> no longer works in many places, it has to be
> #if some-variable == 1
> 
> to work.
> 
> 
> -  for the new config too, there is no longer a default for _RAMBASE, 
> 	due to PPC and K8 differences

Hmm.  We can't have a per architecture default _RAMBASE?

As long as there is an error if you don't set it I guess that
is ok.

> raminit.c sees the following changes:
> Index: src/northbridge/amd/amdk8/raminit.c

Ron on these kind of things please use diff -u or cvs diff -u
it is much, much, much more readable.

> ===================================================================
> RCS file: /cvsroot/freebios/freebios2/src/northbridge/amd/amdk8/raminit.c,v
> retrieving revision 1.12
> diff -r1.12 raminit.c
> 921a922,927
> > //BY LYH  add IOMMU 64M APERTURE
> > 	PCI_ADDR(0, 0x18, 3, 0x94), 0xffff8000, 0x00000f70,
> > 	PCI_ADDR(0, 0x18, 3, 0x90), 0xffffff80, 0x00000002,
> >         PCI_ADDR(0, 0x18, 3, 0x98), 0x0000000f, 0x00068300,
> > 
> > //BY LYH END
> 1119c1125,1141
> < 
> ---

With YhLu's observation that Function 2 dram base addresses are per
memory controller local addresses there are a number of pieces in here
that just need to be fixed. 

Hopefully I can get at it tomorrow.  The current code base does not
have the second memory controller working for me.

> > static void fill_last(unsigned long node_id,unsigned long base)
> > {
> > //BY LYH //Fill next base reg with right value
> >         unsigned i;
> >         unsigned base_reg;
> >         base &=0xffff0000;
> > 	device_t device;
> > for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
> 
> > += PCI_DEV(0, 1, 0)) {
> >         	for(i=node_id+1;i<=7;i++) {
> >                 	base_reg=0x40+(i<<3);
> >                  	pci_write_config32(device,base_reg,base);
> > 		}
> >         }
> > //BY LYH END
> > }
> >  
> 1128a1151
> > 
> 1145a1169
> > 	
> 1254,1256c1278,1280
> < 		print_debug("csbase=");
> < 		print_debug_hex32(csbase);
> < 		print_debug("\r\n");
> ---
> > //		print_debug("csbase=");
> > //		print_debug_hex32(csbase);
> > //		print_debug("\r\n");
> 1285a1310,1312
> > //BY LYH
> >         fill_last(ctrl->node_id, tom_k<<2);
> > //BY LYH END
> 1288,1291c1315,1319
> < 	if(ctrl->node_id==1) {
> < 		pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
> < 	
> < 	}	
> ---
> >         dump_pci_device(PCI_DEV(0, 0x18, 1));
> >  
> > //	if(ctrl->node_id==1) {
> > //		pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
> > //	}	

> 
> 
> and the amd8111 sees this:
> 
> Index: src/southbridge/amd/amd8111/amd8111_ldtstop.c
> ===================================================================
> RCS file:
> /cvsroot/freebios/freebios2/src/southbridge/amd/amd8111/amd8111_ldtstop.c,v
> 
> retrieving revision 1.4
> diff -r1.4 amd8111_ldtstop.c
> 22c22
> < 	pci_write_config16(dev, 0x48, pci_read_config16(dev,0x48) & ~CPUPIN);
> ---
> > 	pci_write_config32(dev, 0x48, pci_read_config32(dev,0x48) & ~CPUPIN);
>  

That looks to be a noop so it should not cause trouble.

> If this is trouble, let me know.
> 
> You are going to have to set _RAMBASE in your mainboard Config.lb
> now.

Unfortunate but it should be a large problem.

Ron while we are thinking about it where should we place tables on the
ARM?  It has a ROM chip as the first thing in memory.

Eric



From yl.huang at yahoo.com.tw  Wed Jul 30 05:07:00 2003
From: yl.huang at yahoo.com.tw (ylhuang-kimo)
Date: Wed Jul 30 05:07:00 2003
Subject: step 4 in L440GX(HOWTO) 
Message-ID: <3F278F07.9060201@yahoo.com.tw>

After I do make, I got lot of files and I do make phlash but
there is a message on the screen: No rule to make target
`vmlinux.bin.gz.block', needed by `phlash'. How can I solve
this problem?



From stepan at suse.de  Wed Jul 30 05:10:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Jul 30 05:10:01 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <m3ispkpngz.fsf@maxwell.lnxi.com>
References: <Pine.LNX.4.44.0307292107090.28725-100000@maxroach.lanl.gov> <m3ispkpngz.fsf@maxwell.lnxi.com>
Message-ID: <20030730092420.GE1675@suse.de>

* Eric W. Biederman <ebiederman at lnxi.com> [030730 07:55]:
> > Index: src/southbridge/amd/amd8111/amd8111_ldtstop.c
> > ===================================================================
> > RCS file:
> > /cvsroot/freebios/freebios2/src/southbridge/amd/amd8111/amd8111_ldtstop.c,v
> > 
> > retrieving revision 1.4
> > diff -r1.4 amd8111_ldtstop.c
> > 22c22
> > < 	pci_write_config16(dev, 0x48, pci_read_config16(dev,0x48) & ~CPUPIN);
> > ---
> > > 	pci_write_config32(dev, 0x48, pci_read_config32(dev,0x48) & ~CPUPIN);
 
The Bios and kernel developers guide specifies 16bit for that register.
But since it's all Little Endian it really does not matter.

OTOH, if Tom gets his warm reboot code in place after setting link
speed, we can probably get rid of ldtstop assertion completely.

How does doing a warm boot there affect boot time?



Stefan


From ebiederman at lnxi.com  Wed Jul 30 12:20:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jul 30 12:20:01 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <20030730092420.GE1675@suse.de>
References: <Pine.LNX.4.44.0307292107090.28725-100000@maxroach.lanl.gov>
	<m3ispkpngz.fsf@maxwell.lnxi.com> <20030730092420.GE1675@suse.de>
Message-ID: <m3oezchsy0.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * Eric W. Biederman <ebiederman at lnxi.com> [030730 07:55]:
> > > Index: src/southbridge/amd/amd8111/amd8111_ldtstop.c
> > > ===================================================================
> > > RCS file:
> > > /cvsroot/freebios/freebios2/src/southbridge/amd/amd8111/amd8111_ldtstop.c,v
> > > 
> > > retrieving revision 1.4
> > > diff -r1.4 amd8111_ldtstop.c
> > > 22c22
> > > < 	pci_write_config16(dev, 0x48, pci_read_config16(dev,0x48) & ~CPUPIN);
> > > ---
> > > > 	pci_write_config32(dev, 0x48, pci_read_config32(dev,0x48) & ~CPUPIN);
>  
> The Bios and kernel developers guide specifies 16bit for that register.
> But since it's all Little Endian it really does not matter.
> 
> OTOH, if Tom gets his warm reboot code in place after setting link
> speed, we can probably get rid of ldtstop assertion completely.

The code is there.  There is a challenge because of errata #48 that
says the 8131 cannot operate at 800Mhz reliably, but it reports that it can.

> How does doing a warm boot there affect boot time?

It pretty much doubles the time before the booloader.  And there is
the large delay that you see on current Opteron systems.

My plan for today is to see about integrating all of these divergent
pieces so I have everything working in one tree.

Eric



From YhLu at tyan.com  Wed Jul 30 13:16:01 2003
From: YhLu at tyan.com (YhLu)
Date: Wed Jul 30 13:16:01 2003
Subject: Fixes for Tyan s2880
Message-ID: <3174569B9743D511922F00A0C943142302FC9E8B@TYANWEB>

Eric,

I have made two changes in raminit.c
1. csbase counting
2. fill_last to make sure kernel to scan NUMA successfully.

For s2880 it can work with 4*1G+2*256M RAM, and doesn't work with
4*1G+2*512M or 4*1G+2*1G.

I would try to substitute raminit.c with hardcode one to test for 6G, if it
can help.

Please advise.

Regards

Yinghai Lu


From rminnich at lanl.gov  Wed Jul 30 14:42:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 30 14:42:00 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <m3ispkpngz.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307301254060.3784-100000@maxroach.lanl.gov>

On 29 Jul 2003, Eric W. Biederman wrote:

> Hmm.  We can't have a per architecture default _RAMBASE?

not sure if it makes sense per architecture. Consider those Alpha boards 
where rambase depended on chip type, board type, engineer's last name, and 
phase of the moon. I'm sure we'll see more of that. 


> Ron while we are thinking about it where should we place tables on the
> ARM?  It has a ROM chip as the first thing in memory.

cool! you're looking at ARM? 

possibly at put tables at the other end of memory? Is there an ARM 
standard for this?

ron



From stepan at suse.de  Wed Jul 30 15:11:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Jul 30 15:11:01 2003
Subject: Solo once again
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9E8B@TYANWEB>; from YhLu@tyan.com on Wed, Jul 30, 2003 at 10:35:29AM -0700
References: <3174569B9743D511922F00A0C943142302FC9E8B@TYANWEB>
Message-ID: <20030730212616.A23647@suse.de>

Hi,

does the Solo need any special init for the onboard winbond chip? I
got the solo target to compile again today, but all I get is
reeeaaallyyy slooooow output of the setting up default resources and
node1 before it just hangs.

  Stefan

-- 
Architecture Team
    SuSE Linux AG


From ebiederman at lnxi.com  Wed Jul 30 15:38:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jul 30 15:38:01 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <Pine.LNX.4.44.0307301254060.3784-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307301254060.3784-100000@maxroach.lanl.gov>
Message-ID: <m3el07g57r.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On 29 Jul 2003, Eric W. Biederman wrote:
> 
> > Hmm.  We can't have a per architecture default _RAMBASE?
> 
> not sure if it makes sense per architecture. Consider those Alpha boards 
> where rambase depended on chip type, board type, engineer's last name, and 
> phase of the moon. I'm sure we'll see more of that. 

Hmm.  Perhaps.  The SGI Itanium nodes start their memory at 196GB.

For commodity stuff standardization is the rule of the game, so
how much of this we will have to deal with LinuxBIOS wise is an interesting
question.  Mostly on the embedded stuff I would suspect.

> > Ron while we are thinking about it where should we place tables on the
> > ARM?  It has a ROM chip as the first thing in memory.
> 
> cool! you're looking at ARM? 

No, I have just been talking to a lot of people doing embedded stuff.
And I like to look at problems long before I actually have to cope with
them.  

> possibly at put tables at the other end of memory? Is there an ARM 
> standard for this?

ARM kernels currently have a fair amount of board specific knowledge
in them.  An ARM BIOS is so far to easy to share code with LinuxBIOS,
but we may be able to share a table structure with.

Eric



From rminnich at lanl.gov  Wed Jul 30 17:25:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 30 17:25:00 2003
Subject: Solo once again
In-Reply-To: <20030730212616.A23647@suse.de>
Message-ID: <Pine.LNX.4.44.0307301539410.4649-100000@maxroach.lanl.gov>

On Wed, 30 Jul 2003, Stefan Reinauer wrote:

> does the Solo need any special init for the onboard winbond chip? I
> got the solo target to compile again today, but all I get is
> reeeaaallyyy slooooow output of the setting up default resources and
> node1 before it just hangs.

if so, this is a good time to get the newconfig stuff up for solo.

Stefan, I plan to try the new config commands to get your desired topology 
working. I'll let you know.

ron



From rminnich at lanl.gov  Wed Jul 30 18:30:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 30 18:30:00 2003
Subject: static config for CPUs with K8 example
Message-ID: <Pine.LNX.4.44.0307301640370.4649-100000@maxroach.lanl.gov>

OK, I am hoping this is the kind of thing that will work for the K8. 

First, in cpu/k8, define a file, chip.h:

struct cpu_k8_config {
        struct chip *north, *south, *east, *west;
};

Thenin cpu/k8/Config.lb, add this line:
config chip.h

Note this file could be called anything, but chip.h is a habit for me.


In the mainboard config (mainboard/arima/hdama/Config.lb), you set things 
up as follows:

southbridge amd/amd8111 "amd8111"
end
southbridge amd/amd8131 "amd8131"
end

# pull in all includes, etc. for  the k8. 
# should we have a 'noise keyword' for this, e.g. 'cputype k8'?

dir /cpu/k8

# define the CPUs, their names, and their connections.
cpu k8 "cpu0"
  register "north" = "amd8111"
  register "east"  = "cpu1"
end

cpu k8 "cpu1"
  register "north" = "amd8131"
  register "west"  = "cpu0"
end

This will result in initialized structures, per-cpu, that "do the right 
thing". 


I've hit a bug I have to ask Greg about, but this is a rough idea. 
Comments?

ron



From YhLu at tyan.com  Wed Jul 30 18:55:01 2003
From: YhLu at tyan.com (YhLu)
Date: Wed Jul 30 18:55:01 2003
Subject: static config for CPUs with K8 example
Message-ID: <3174569B9743D511922F00A0C943142302FC9EFE@TYANWEB>

Ron,

If the 8111 is connected to 8131. Should add the config for 8131 and say its
north is "amd8111".

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?7?30? 15:45
???: linuxbios at clustermatic.org
??: static config for CPUs with K8 example


OK, I am hoping this is the kind of thing that will work for the K8. 

First, in cpu/k8, define a file, chip.h:

struct cpu_k8_config {
        struct chip *north, *south, *east, *west;
};

Thenin cpu/k8/Config.lb, add this line:
config chip.h

Note this file could be called anything, but chip.h is a habit for me.


In the mainboard config (mainboard/arima/hdama/Config.lb), you set things 
up as follows:

southbridge amd/amd8111 "amd8111"
end
southbridge amd/amd8131 "amd8131"
end

# pull in all includes, etc. for  the k8. 
# should we have a 'noise keyword' for this, e.g. 'cputype k8'?

dir /cpu/k8

# define the CPUs, their names, and their connections.
cpu k8 "cpu0"
  register "north" = "amd8111"
  register "east"  = "cpu1"
end

cpu k8 "cpu1"
  register "north" = "amd8131"
  register "west"  = "cpu0"
end

This will result in initialized structures, per-cpu, that "do the right 
thing". 


I've hit a bug I have to ask Greg about, but this is a rough idea. 
Comments?

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From rminnich at lanl.gov  Wed Jul 30 21:04:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 30 21:04:00 2003
Subject: static config for CPUs with K8 example
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9EFE@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307301918110.6831-100000@maxroach.lanl.gov>

On Wed, 30 Jul 2003, YhLu wrote:

> If the 8111 is connected to 8131. Should add the config for 8131 and say its
> north is "amd8111".

ah, ok, I need that more complex diagram that stefan sent me. All the 
diagrams he has sent so far show no link from 8131 to 8111 ...

Stefan? can you send 2 and 4 cpu pictures again?

ron



From rminnich at lanl.gov  Wed Jul 30 21:05:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 30 21:05:00 2003
Subject: static config for CPUs with K8 example
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9EFE@TYANWEB>
Message-ID: <Pine.LNX.4.44.0307301919150.6831-100000@maxroach.lanl.gov>

are the names 'north, south, east, west' acceptable to everyone? It 
follows current nomenclature.

ron



From ebiederman at lnxi.com  Wed Jul 30 21:56:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jul 30 21:56:00 2003
Subject: Solo once again
In-Reply-To: <20030730212616.A23647@suse.de>
References: <3174569B9743D511922F00A0C943142302FC9E8B@TYANWEB>
	<20030730212616.A23647@suse.de>
Message-ID: <m34r13cukm.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> Hi,
> 
> does the Solo need any special init for the onboard winbond chip?
Last I checked the Solo has an undocumented PNC chip.  But
it didn't need anything special to initialize the serial port.

>  I
> got the solo target to compile again today, but all I get is
> reeeaaallyyy slooooow output of the setting up default resources and
> node1 before it just hangs.

Hmm.  Is this perhaps running at 9600 baud.

I believe the speed problem is that the XIP defines have not been
picked up in the new configuration stuff.  Anyway that is where I
would look first for speed problems.

There are enough hard codes in the code at the moment that are smp specifc
that we may have a bug there, that can explain the crash.

Eric



From hansolofalcon at worldnet.att.net  Wed Jul 30 22:20:01 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Wed Jul 30 22:20:01 2003
Subject: static config for CPUs with K8 example
In-Reply-To: <Pine.LNX.4.44.0307301919150.6831-100000@maxroach.lanl.gov>
Message-ID: <000b01c3570c$64f66800$0100a8c0@who5>

Hello from Gregg C Levine
Okay. It works for me.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of ron minnich
> Sent: Wednesday, July 30, 2003 9:20 PM
> To: YhLu
> Cc: linuxbios at clustermatic.org
> Subject: Re: static config for CPUs with K8 example
> 
> are the names 'north, south, east, west' acceptable to everyone? It
> follows current nomenclature.
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From hansolofalcon at worldnet.att.net  Wed Jul 30 22:22:00 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Wed Jul 30 22:22:00 2003
Subject: Solo once again
In-Reply-To: <m34r13cukm.fsf@maxwell.lnxi.com>
Message-ID: <000c01c3570c$900cfc20$0100a8c0@who5>

Hello from Gregg C Levine
Now you've got my curiosity on active. Whose motherboard, is this? Is
it a Tyan job? Where can I get one?
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of Eric W. Biederman
> Sent: Wednesday, July 30, 2003 10:13 PM
> To: Stefan Reinauer
> Cc: YhLu; ebiederman at lnxi.com; ron minnich;
linuxbios at clustermatic.org
> Subject: Re: Solo once again
> 
> Stefan Reinauer <stepan at suse.de> writes:
> 
> > Hi,
> >
> > does the Solo need any special init for the onboard winbond chip?
> Last I checked the Solo has an undocumented PNC chip.  But
> it didn't need anything special to initialize the serial port.
> 
> >  I
> > got the solo target to compile again today, but all I get is
> > reeeaaallyyy slooooow output of the setting up default resources
and
> > node1 before it just hangs.
> 
> Hmm.  Is this perhaps running at 9600 baud.
> 
> I believe the speed problem is that the XIP defines have not been
> picked up in the new configuration stuff.  Anyway that is where I
> would look first for speed problems.
> 
> There are enough hard codes in the code at the moment that are smp
specifc
> that we may have a bug there, that can explain the crash.
> 
> Eric
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Wed Jul 30 22:57:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 30 22:57:00 2003
Subject: Solo once again
In-Reply-To: <m34r13cukm.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307302111390.7562-100000@maxroach.lanl.gov>

On 30 Jul 2003, Eric W. Biederman wrote:

> I believe the speed problem is that the XIP defines have not been
> picked up in the new configuration stuff.  Anyway that is where I
> would look first for speed problems.

oh ho. What XIP defines are needed? I'll put them in but can't test until 
monday.

ron



From rminnich at lanl.gov  Wed Jul 30 22:58:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jul 30 22:58:01 2003
Subject: Solo once again
In-Reply-To: <000c01c3570c$900cfc20$0100a8c0@who5>
Message-ID: <Pine.LNX.4.44.0307302112310.7562-100000@maxroach.lanl.gov>

On Wed, 30 Jul 2003, Gregg C Levine wrote:

> Now you've got my curiosity on active. Whose motherboard, is this? Is
> it a Tyan job? Where can I get one?

two current motherboards working that you can buy are the Arima HDAMA and 
the Tyan s2880

ron



From stepan at suse.de  Thu Jul 31 05:07:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 31 05:07:01 2003
Subject: Solo once again
In-Reply-To: <m34r13cukm.fsf@maxwell.lnxi.com>
References: <3174569B9743D511922F00A0C943142302FC9E8B@TYANWEB> <20030730212616.A23647@suse.de> <m34r13cukm.fsf@maxwell.lnxi.com>
Message-ID: <20030731092211.GC1673@suse.de>

* Eric W. Biederman <ebiederman at lnxi.com> [030731 04:13]:
> Stefan Reinauer <stepan at suse.de> writes:
> >  I
> > got the solo target to compile again today, but all I get is
> > reeeaaallyyy slooooow output of the setting up default resources and
> > node1 before it just hangs.
> 
> Hmm.  Is this perhaps running at 9600 baud.
 
Nope, don't think so. I have my terminal program running at 115200bps
and i get text through, always some bytes at once, then it lags, then
some more bytes and so on...

> I believe the speed problem is that the XIP defines have not been
> picked up in the new configuration stuff.  Anyway that is where I
> would look first for speed problems.
 
This happened with the old config method. 

> There are enough hard codes in the code at the moment that are smp specifc
> that we may have a bug there, that can explain the crash.

I basically took the hdama code and stripped it down to fit, but i
might very well have missed something.

Stefan


From stepan at suse.de  Thu Jul 31 05:17:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jul 31 05:17:01 2003
Subject: static config for CPUs with K8 example
In-Reply-To: <Pine.LNX.4.44.0307301640370.4649-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0307301640370.4649-100000@maxroach.lanl.gov>
Message-ID: <20030731093148.GD1673@suse.de>

* ron minnich <rminnich at lanl.gov> [030731 00:44]:
> 
> OK, I am hoping this is the kind of thing that will work for the K8. 
> 
> First, in cpu/k8, define a file, chip.h:
> 
> struct cpu_k8_config {
>         struct chip *north, *south, *east, *west;
> };

I don't think we need both of east and west really. The Bios Developers
Guide calls these links "UP", "DOWN" and "ACROSS", for LDT0-2. 
It might still be interesting to have a topological view on the
hardware, but at least for hypertransport setup, east and west is equal.

> In the mainboard config (mainboard/arima/hdama/Config.lb), you set things 
> up as follows:
> 
> southbridge amd/amd8111 "amd8111"
    register "north"     = "cpu0" 
    register "ht_width"  = "8"      # 8bit, even if device reports more
    register "ht_speed"  = "200"    # don't drive faster than 200MHz,
                                    # in case device reports false
                                    # maximum speed
> end
> southbridge amd/amd8131 "amd8131"
    register "north" = "cpu1" (for example)
    register "ht_width"  = "8"
    register "ht_speed"  = "200"
> end
 
> # pull in all includes, etc. for  the k8. 
> # should we have a 'noise keyword' for this, e.g. 'cputype k8'?
 
noise keyword?

> dir /cpu/k8  
  ^^^^^^^^^^^ 

can this not implicitly be generated from the below description? 
 
> # define the CPUs, their names, and their connections.
> cpu k8 "cpu0"
>   register "north" = "amd8111"
              ^^^^^ south (iirc)
>   register "east"  = "cpu1"
> end
> 
> cpu k8 "cpu1"
>   register "north" = "amd8131"
              ^^^^^ south
>   register "west"  = "cpu0"
> end
 

Stefan




From han2004 at hotmail.com  Thu Jul 31 11:03:01 2003
From: han2004 at hotmail.com (gimyung han)
Date: Thu Jul 31 11:03:01 2003
Subject: is there any way to boot linux without etherboot?
Message-ID: <BAY2-F88KFJ2I13pL3200004f08@hotmail.com>

I followed you HOWTO and succeed in Linux using LinuxBIOS with VGA

Is there other way to boot Linux using LinuxBIOS without etherbooting?

I saw message asking whether I will choose netbooting or local on the 
logging message?

is option to choose the way to boot system? like local boot?

If so, how to do that?

do I need to load whole Linux kernel on the bios rom? lik using a DoC ?

is anyone who boot Linux in other way on the EPIA mainboard?

Thank for any help...........

_________________________________________________________________
??? ???? ??? ???. AIG? ?????? ?????.   
http://www.msn.co.kr/webinclude/exredir.asp?STARTID=CLIP_5644&adgroup=KRMGEN&URL=http://msn.aigis.co.kr/weekly_msn/main.asp 
 



From rminnich at lanl.gov  Thu Jul 31 11:29:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 31 11:29:01 2003
Subject: static config for CPUs with K8 example
In-Reply-To: <20030731093148.GD1673@suse.de>
Message-ID: <Pine.LNX.4.44.0307310938500.12812-100000@maxroach.lanl.gov>

On Thu, 31 Jul 2003, Stefan Reinauer wrote:

> > First, in cpu/k8, define a file, chip.h:
> > 
> > struct cpu_k8_config {
> >         struct chip *north, *south, *east, *west;
> > };
> 
> I don't think we need both of east and west really. The Bios Developers
> Guide calls these links "UP", "DOWN" and "ACROSS", for LDT0-2. 
> It might still be interesting to have a topological view on the
> hardware, but at least for hypertransport setup, east and west is equal.

OK. I also occured to me last night that we need this:

struct ht_link {
	struct chip *chip;
	unsigned int ht_width, ht_speed;
}; 

then:

southbridge amd/amd8111 "amd8111"
	register "north" = "{.chip = &cpu0, .ht_width = 8, .ht_speed=200"
end

and so on.  Make sense? Or not? I don't have the data book so don't know 
if the 8111 has more than one link.

For the CPUs we then have 

struct cpu_k8_config {
	struct ht_link up, down, across;
};



> > dir /cpu/k8  
>   ^^^^^^^^^^^ 
> 
> can this not implicitly be generated from the below description? 

yes, and it should be, I had the same thought.

> > # define the CPUs, their names, and their connections.
cpu k8 "cpu0"

	register "down" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
	.
	.
end

better?

ron

p.s. the chip-specific structure for the PCI bridge will, of course, have
a pointer to the top of the PCI tree, and that becomes our link from the
static to the dynamic devices.



From agnew at cs.umd.edu  Thu Jul 31 13:07:00 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Thu Jul 31 13:07:00 2003
Subject: is there any way to boot linux without etherboot?
In-Reply-To: <BAY2-F88KFJ2I13pL3200004f08@hotmail.com>
Message-ID: <20030731133532.T30567-100000@www.missl.cs.umd.edu>

There are several ways. Please go through the LinuxBIOS archive looking
for posts by Richard Smith with a subject containing "FAQ". He wrote a faq
which covers many of them. If you can get a kernel image on your flash,
you're limited only by your imagination (and what devices the linux kernel
can make use of :) ).

On Thu, 31 Jul 2003, gimyung han wrote:

> I followed you HOWTO and succeed in Linux using LinuxBIOS with VGA
>
> Is there other way to boot Linux using LinuxBIOS without etherbooting?
>
> I saw message asking whether I will choose netbooting or local on the
> logging message?
>
> is option to choose the way to boot system? like local boot?
>
> If so, how to do that?
>
> do I need to load whole Linux kernel on the bios rom? lik using a DoC ?
>
> is anyone who boot Linux in other way on the EPIA mainboard?
>
> Thank for any help...........
>
> _________________________________________________________________
> ?????? ???????? ?????? ??????. AIG?? ???????????? ??????????.
> http://www.msn.co.kr/webinclude/exredir.asp?STARTID=CLIP_5644&adgroup=KRMGEN&URL=http://msn.aigis.co.kr/weekly_msn/main.asp
>
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>



From steve at nexpath.com  Thu Jul 31 13:24:01 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Thu Jul 31 13:24:01 2003
Subject: is there any way to boot linux without etherboot?
In-Reply-To: <20030731133532.T30567-100000@www.missl.cs.umd.edu>
References: <20030731133532.T30567-100000@www.missl.cs.umd.edu>
Message-ID: <3F29561A.3000606@nexpath.com>

>>Is there other way to boot Linux using LinuxBIOS without etherbooting?
>>

Also, two configs I submitted do not use etherboot:
     pcchips787.config
     stpc.config
in the util/config directory.  You can use them for some ideas.

-Steve



From ebiederman at lnxi.com  Thu Jul 31 23:04:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Jul 31 23:04:01 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FC9E8B@TYANWEB>
References: <3174569B9743D511922F00A0C943142302FC9E8B@TYANWEB>
Message-ID: <m3d6fqxdzb.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have made two changes in raminit.c
> 1. csbase counting
> 2. fill_last to make sure kernel to scan NUMA successfully.
> 
> For s2880 it can work with 4*1G+2*256M RAM, and doesn't work with
> 4*1G+2*512M or 4*1G+2*1G.
> 
> I would try to substitute raminit.c with hardcode one to test for 6G, if it
> can help.
> 
> Please advise.

There has been enough code churn that my head is still spinning in
trying to get in sync with the main tree. 

I have updated raminit.c so that it now handles the case of each
memory controller starting from 0 cleanly, and I have updated
cpufixup.c so that we are handling > 4GB of memory properly.  TOP_MEM2
was not getting set to the proper value.

fill_last was pretty much a duplicate of route_dram_access except
different assumptions were made, so I have removed fill_last again.

If you have memory that doesn't get setup properly now holler.

So we should be pretty close.  Before I can go much farther I need a
test for pre rev c0 cpus.  Because a lot of the remaining memory code
needs to be conditional on it.

I am in the last stages of stabilizing an internal version to
be used in large scale testing to search for hardware
incompatibilities.

I also have a the links width and speed being automatically setup
properly.  But the way I discover the links is still kind of
nasty, so I am not quite ready to push the code back yet.

I should be switching over to the new configuration system on Monday
and once that is sorted out quite I can start putting hard codes
where they belong in the board specific configuration.

Eric



From rminnich at lanl.gov  Thu Jul 31 23:08:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jul 31 23:08:00 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <m3d6fqxdzb.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0307312121590.17891-100000@maxroach.lanl.gov>

On 31 Jul 2003, Eric W. Biederman wrote:

> 
> I should be switching over to the new configuration system on Monday
> and once that is sorted out quite I can start putting hard codes
> where they belong in the board specific configuration.
> 

good timing, I'm back then. 

Greg has further ideas and we need to keep talking as we converge. I will 
try hard to get the cpu stuff in before monday.

Note that V2 is now supporting PPC and K8. I am going to use the AMD SC520 
for the third architecture test, then it's on to Elan for the fourth.



ron



From YhLu at tyan.com  Thu Jul 31 23:11:01 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jul 31 23:11:01 2003
Subject: Fixes for Tyan s2880
Message-ID: <3174569B9743D511922F00A0C943142302FCA037@TYANWEB>

Eric,

Great. Then there should be no big issue on opteron any more.

Can you send to the new raminit.c to me now?

Regards

Yinghai Lu




From YhLu at tyan.com  Thu Jul 31 23:15:01 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jul 31 23:15:01 2003
Subject: Fixes for Tyan s2880
Message-ID: <3174569B9743D511922F00A0C943142302FCA038@TYANWEB>

Eric,

I have checked your old k8/cpufixup.c, and it already has TOM2 etc setup.
and SYSCFG_TOM2_EN...etc...

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?7?31? 20:18
???: YhLu
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: Fixes for Tyan s2880

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have made two changes in raminit.c
> 1. csbase counting
> 2. fill_last to make sure kernel to scan NUMA successfully.
> 
> For s2880 it can work with 4*1G+2*256M RAM, and doesn't work with
> 4*1G+2*512M or 4*1G+2*1G.
> 
> I would try to substitute raminit.c with hardcode one to test for 6G, if
it
> can help.
> 
> Please advise.

There has been enough code churn that my head is still spinning in
trying to get in sync with the main tree. 

I have updated raminit.c so that it now handles the case of each
memory controller starting from 0 cleanly, and I have updated
cpufixup.c so that we are handling > 4GB of memory properly.  TOP_MEM2
was not getting set to the proper value.

fill_last was pretty much a duplicate of route_dram_access except
different assumptions were made, so I have removed fill_last again.

If you have memory that doesn't get setup properly now holler.

So we should be pretty close.  Before I can go much farther I need a
test for pre rev c0 cpus.  Because a lot of the remaining memory code
needs to be conditional on it.

I am in the last stages of stabilizing an internal version to
be used in large scale testing to search for hardware
incompatibilities.

I also have a the links width and speed being automatically setup
properly.  But the way I discover the links is still kind of
nasty, so I am not quite ready to push the code back yet.

I should be switching over to the new configuration system on Monday
and once that is sorted out quite I can start putting hard codes
where they belong in the board specific configuration.

Eric


From ebiederman at lnxi.com  Thu Jul 31 23:22:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Jul 31 23:22:01 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FCA038@TYANWEB>
References: <3174569B9743D511922F00A0C943142302FCA038@TYANWEB>
Message-ID: <m3wudyqc5b.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have checked your old k8/cpufixup.c, and it already has TOM2 etc setup.
> and SYSCFG_TOM2_EN...etc...

I shift by 12 instead of 10 for the low half of TOP_MEM2...

Which tends to leave TOP_MEM2 at 4GB...

Eric



From YhLu at tyan.com  Thu Jul 31 23:24:01 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jul 31 23:24:01 2003
Subject: =?GB2312?B?tPC4tDogRml4ZXMgZm9yIFR5YW4gczI4ODA=?=
Message-ID: <3174569B9743D511922F00A0C943142302FCA03A@TYANWEB>

Eric,

I see.

I move some code from raminit.c setup_top_ram to it and have a try.

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?7?31? 20:40
???: YhLu
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: Fixes for Tyan s2880

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have checked your old k8/cpufixup.c, and it already has TOM2 etc setup.
> and SYSCFG_TOM2_EN...etc...

I shift by 12 instead of 10 for the low half of TOP_MEM2...

Which tends to leave TOP_MEM2 at 4GB...

Eric


From ebiederman at lnxi.com  Thu Jul 31 23:25:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Jul 31 23:25:00 2003
Subject: Fixes for Tyan s2880
In-Reply-To: <3174569B9743D511922F00A0C943142302FCA037@TYANWEB>
References: <3174569B9743D511922F00A0C943142302FCA037@TYANWEB>
Message-ID: <m3smomqbzs.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Great. Then there should be no big issue on opteron any more.
> 
> Can you send to the new raminit.c to me now?

Here is my most recent snapshot, which is slightly newer
than what I have in the public CVS tree.

I think I need to scrub all of memory on the B3 stepping before
I start using it.  I have not tested anything that is C0 specific yet.

Eric

#include <cpu/k8/mtrr.h>
#include "raminit.h"

/* Function 2 */
#define DRAM_CSBASE	   0x40
#define DRAM_CSMASK	   0x60
#define DRAM_BANK_ADDR_MAP 0x80
#define DRAM_TIMING_LOW	   0x88
#define	 DTL_TCL_SHIFT	   0
#define	 DTL_TCL_MASK	   0x7
#define	  DTL_CL_2	   1
#define	  DTL_CL_3	   2
#define	  DTL_CL_2_5	   5
#define	 DTL_TRC_SHIFT	   4
#define	 DTL_TRC_MASK	   0xf
#define	  DTL_TRC_BASE	   7
#define	  DTL_TRC_MIN	   7
#define	  DTL_TRC_MAX	   22
#define	 DTL_TRFC_SHIFT	   8
#define	 DTL_TRFC_MASK	   0xf
#define	  DTL_TRFC_BASE	   9
#define	  DTL_TRFC_MIN	   9
#define	  DTL_TRFC_MAX	   24
#define	 DTL_TRCD_SHIFT	   12
#define	 DTL_TRCD_MASK	   0x7
#define	  DTL_TRCD_BASE	   0
#define	  DTL_TRCD_MIN	   2
#define	  DTL_TRCD_MAX	   6
#define	 DTL_TRRD_SHIFT	   16
#define	 DTL_TRRD_MASK	   0x7
#define	  DTL_TRRD_BASE	   0
#define	  DTL_TRRD_MIN	   2
#define	  DTL_TRRD_MAX	   4
#define	 DTL_TRAS_SHIFT	   20
#define	 DTL_TRAS_MASK	   0xf
#define	  DTL_TRAS_BASE	   0
#define	  DTL_TRAS_MIN	   5
#define	  DTL_TRAS_MAX	   15
#define	 DTL_TRP_SHIFT	   24
#define	 DTL_TRP_MASK	   0x7
#define	  DTL_TRP_BASE	   0
#define	  DTL_TRP_MIN	   2
#define	  DTL_TRP_MAX	   6
#define	 DTL_TWR_SHIFT	   28
#define	 DTL_TWR_MASK	   0x1
#define	  DTL_TWR_BASE	   2
#define	  DTL_TWR_MIN	   2
#define	  DTL_TWR_MAX	   3
#define DRAM_TIMING_HIGH   0x8c
#define	 DTH_TWTR_SHIFT	   0
#define	 DTH_TWTR_MASK	   0x1
#define	  DTH_TWTR_BASE	   1
#define	  DTH_TWTR_MIN	   1
#define	  DTH_TWTR_MAX	   2
#define	 DTH_TRWT_SHIFT	   4
#define	 DTH_TRWT_MASK	   0x7
#define	  DTH_TRWT_BASE	   1
#define	  DTH_TRWT_MIN	   1
#define	  DTH_TRWT_MAX	   6
#define	 DTH_TREF_SHIFT	   8
#define	 DTH_TREF_MASK	   0x1f
#define	  DTH_TREF_100MHZ_4K 0x00
#define	  DTH_TREF_133MHZ_4K 0x01
#define	  DTH_TREF_166MHZ_4K 0x02
#define	  DTH_TREF_200MHZ_4K 0x03
#define	  DTH_TREF_100MHZ_8K 0x08
#define	  DTH_TREF_133MHZ_8K 0x09
#define	  DTH_TREF_166MHZ_8K 0x0A
#define	  DTH_TREF_200MHZ_8K 0x0B
#define	 DTH_TWCL_SHIFT	    20
#define	 DTH_TWCL_MASK	    0x7
#define	  DTH_TWCL_BASE	    1
#define	  DTH_TWCL_MIN	    1
#define	  DTH_TWCL_MAX	    2
#define DRAM_CONFIG_LOW	   0x90
#define	 DCL_DLL_Disable   (1<<0)
#define	 DCL_D_DRV	   (1<<1)
#define	 DCL_QFC_EN	   (1<<2)
#define	 DCL_DisDqsHys	   (1<<3)
#define	 DCL_DramInit	   (1<<8)
#define	 DCL_DramEnable	   (1<<10)
#define	 DCL_MemClrStatus  (1<<11)
#define	 DCL_ESR	   (1<<12)
#define	 DCL_SRS	   (1<<13)
#define	 DCL_128BitEn	   (1<<16)
#define	 DCL_DimmEccEn	   (1<<17)
#define	 DCL_UnBufDimm	   (1<<18)
#define	 DCL_32ByteEn	   (1<<19)
#define	 DCL_x4DIMM_SHIFT  20
#define DRAM_CONFIG_HIGH   0x94
#define	 DCH_ASYNC_LAT_SHIFT  0
#define	 DCH_ASYNC_LAT_MASK   0xf
#define	  DCH_ASYNC_LAT_BASE  0
#define	  DCH_ASYNC_LAT_MIN   0
#define	  DCH_ASYNC_LAT_MAX   15
#define	 DCH_RDPREAMBLE_SHIFT 8
#define	 DCH_RDPREAMBLE_MASK  0xf
#define	  DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
#define	  DCH_RDPREAMBLE_MIN  ((2<<1)+0) /* 2.0 ns */
#define	  DCH_RDPREAMBLE_MAX  ((9<<1)+1) /* 9.5 ns */
#define	 DCH_IDLE_LIMIT_SHIFT 16
#define	 DCH_IDLE_LIMIT_MASK  0x7
#define	  DCH_IDLE_LIMIT_0    0
#define	  DCH_IDLE_LIMIT_4    1
#define	  DCH_IDLE_LIMIT_8    2
#define	  DCH_IDLE_LIMIT_16   3
#define	  DCH_IDLE_LIMIT_32   4
#define	  DCH_IDLE_LIMIT_64   5
#define	  DCH_IDLE_LIMIT_128  6
#define	  DCH_IDLE_LIMIT_256  7
#define	 DCH_DYN_IDLE_CTR_EN (1 << 19)
#define	 DCH_MEMCLK_SHIFT     20
#define	 DCH_MEMCLK_MASK      0x7
#define	  DCH_MEMCLK_100MHZ   0
#define	  DCH_MEMCLK_133MHZ   2
#define	  DCH_MEMCLK_166MHZ   5
#define	  DCH_MEMCLK_200MHZ   7
#define	 DCH_MEMCLK_VALID     (1 << 25)
#define	 DCH_MEMCLK_EN0	      (1 << 26) 
#define	 DCH_MEMCLK_EN1	      (1 << 27) 
#define	 DCH_MEMCLK_EN2	      (1 << 28) 
#define	 DCH_MEMCLK_EN3	      (1 << 29) 

/* Function 3 */
#define MCA_NB_CONFIG      0x44
#define   MNC_ECC_EN       (1 << 22)
#define   MNC_CHIPKILL_EN  (1 << 23)
#define SCRUB_CONTROL	   0x58
#define	  SCRUB_NONE	    0
#define	  SCRUB_40ns	    1
#define	  SCRUB_80ns	    2
#define	  SCRUB_160ns	    3
#define	  SCRUB_320ns	    4
#define	  SCRUB_640ns	    5
#define	  SCRUB_1_28us	    6
#define	  SCRUB_2_56us	    7
#define	  SCRUB_5_12us	    8
#define	  SCRUB_10_2us	    9
#define	  SCRUB_20_5us	   10
#define	  SCRUB_41_0us	   11
#define	  SCRUB_81_9us	   12
#define	  SCRUB_163_8us	   13
#define	  SCRUB_327_7us	   14
#define	  SCRUB_655_4us	   15
#define	  SCRUB_1_31ms	   16
#define	  SCRUB_2_62ms	   17
#define	  SCRUB_5_24ms	   18 
#define	  SCRUB_10_49ms	   19
#define	  SCRUB_20_97ms	   20
#define	  SCRUB_42ms	   21
#define	  SCRUB_84ms	   22
#define	 SC_DRAM_SCRUB_RATE_SHFIT  0
#define	 SC_DRAM_SCRUB_RATE_MASK   0x1f
#define	 SC_L2_SCRUB_RATE_SHIFT	   8
#define	 SC_L2_SCRUB_RATE_MASK	   0x1f
#define	 SC_L1D_SCRUB_RATE_SHIFT   16
#define	 SC_L1D_SCRUB_RATE_MASK	   0x1f
#define SCRUB_ADDR_LOW	   0x5C
#define SCRUB_ADDR_HIGH	   0x60
#define NORTHBRIDGE_CAP	   0xE8
#define	 NBCAP_128Bit	      0x0001
#define	 NBCAP_MP	      0x0002
#define	 NBCAP_BIG_MP	      0x0004
#define	 NBCAP_ECC	      0x0004
#define	 NBCAP_CHIPKILL_ECC   0x0010
#define	 NBCAP_MEMCLK_SHIFT   5
#define	 NBCAP_MEMCLK_MASK    3
#define	 NBCAP_MEMCLK_100MHZ  3
#define	 NBCAP_MEMCLK_133MHZ  2
#define	 NBCAP_MEMCLK_166MHZ  1
#define	 NBCAP_MEMCLK_200MHZ  0
#define	 NBCAP_MEMCTRL	      0x0100


static void setup_resource_map(const unsigned int *register_values, int max)
{
	int i;
	print_debug("setting up resource map....\r\n");
	for(i = 0; i < max; i += 3) {
		device_t dev;
		unsigned where;
		unsigned long reg;
#if 0
		print_debug_hex32(register_values[i]);
		print_debug(" <-");
		print_debug_hex32(register_values[i+2]);
		print_debug("\r\n");
#endif
		dev = register_values[i] & ~0xff;
		where = register_values[i] & 0xff;
		reg = pci_read_config32(dev, where);
		reg &= register_values[i+1];
		reg |= register_values[i+2];
		pci_write_config32(dev, where, reg);
#if 0
		reg = pci_read_config32(register_values[i]);
		reg &= register_values[i+1];
		reg |= register_values[i+2] & ~register_values[i+1];
		pci_write_config32(register_values[i], reg);
#endif
	}
	print_debug("done.\r\n");
}

static void setup_default_resource_map(void)
{
	static const unsigned int register_values[] = {
	/* Careful set limit registers before base registers which contain the enables */
	/* DRAM Limit i Registers
	 * F1:0x44 i = 0
	 * F1:0x4C i = 1
	 * F1:0x54 i = 2
	 * F1:0x5C i = 3
	 * F1:0x64 i = 4
	 * F1:0x6C i = 5
	 * F1:0x74 i = 6
	 * F1:0x7C i = 7
	 * [ 2: 0] Destination Node ID
	 *	   000 = Node 0
	 *	   001 = Node 1
	 *	   010 = Node 2
	 *	   011 = Node 3
	 *	   100 = Node 4
	 *	   101 = Node 5
	 *	   110 = Node 6
	 *	   111 = Node 7
	 * [ 7: 3] Reserved
	 * [10: 8] Interleave select
	 *	   specifies the values of A[14:12] to use with interleave enable.
	 * [15:11] Reserved
	 * [31:16] DRAM Limit Address i Bits 39-24
	 *	   This field defines the upper address bits of a 40 bit  address
	 *	   that define the end of the DRAM region.
	 */
	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
	/* DRAM Base i Registers
	 * F1:0x40 i = 0
	 * F1:0x48 i = 1
	 * F1:0x50 i = 2
	 * F1:0x58 i = 3
	 * F1:0x60 i = 4
	 * F1:0x68 i = 5
	 * F1:0x70 i = 6
	 * F1:0x78 i = 7
	 * [ 0: 0] Read Enable
	 *	   0 = Reads Disabled
	 *	   1 = Reads Enabled
	 * [ 1: 1] Write Enable
	 *	   0 = Writes Disabled
	 *	   1 = Writes Enabled
	 * [ 7: 2] Reserved
	 * [10: 8] Interleave Enable
	 *	   000 = No interleave
	 *	   001 = Interleave on A[12] (2 nodes)
	 *	   010 = reserved
	 *	   011 = Interleave on A[12] and A[14] (4 nodes)
	 *	   100 = reserved
	 *	   101 = reserved
	 *	   110 = reserved
	 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
	 * [15:11] Reserved
	 * [13:16] DRAM Base Address i Bits 39-24
	 *	   This field defines the upper address bits of a 40-bit address
	 *	   that define the start of the DRAM region.
	 */
	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,

	/* Memory-Mapped I/O Limit i Registers
	 * F1:0x84 i = 0
	 * F1:0x8C i = 1
	 * F1:0x94 i = 2
	 * F1:0x9C i = 3
	 * F1:0xA4 i = 4
	 * F1:0xAC i = 5
	 * F1:0xB4 i = 6
	 * F1:0xBC i = 7
	 * [ 2: 0] Destination Node ID
	 *	   000 = Node 0
	 *	   001 = Node 1
	 *	   010 = Node 2
	 *	   011 = Node 3
	 *	   100 = Node 4
	 *	   101 = Node 5
	 *	   110 = Node 6
	 *	   111 = Node 7
	 * [ 3: 3] Reserved
	 * [ 5: 4] Destination Link ID
	 *	   00 = Link 0
	 *	   01 = Link 1
	 *	   10 = Link 2
	 *	   11 = Reserved
	 * [ 6: 6] Reserved
	 * [ 7: 7] Non-Posted
	 *	   0 = CPU writes may be posted
	 *	   1 = CPU writes must be non-posted
	 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
	 *	   This field defines the upp adddress bits of a 40-bit address that
	 *	   defines the end of a memory-mapped I/O region n
	 */
	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,

	/* Memory-Mapped I/O Base i Registers
	 * F1:0x80 i = 0
	 * F1:0x88 i = 1
	 * F1:0x90 i = 2
	 * F1:0x98 i = 3
	 * F1:0xA0 i = 4
	 * F1:0xA8 i = 5
	 * F1:0xB0 i = 6
	 * F1:0xB8 i = 7
	 * [ 0: 0] Read Enable
	 *	   0 = Reads disabled
	 *	   1 = Reads Enabled
	 * [ 1: 1] Write Enable
	 *	   0 = Writes disabled
	 *	   1 = Writes Enabled
	 * [ 2: 2] Cpu Disable
	 *	   0 = Cpu can use this I/O range
	 *	   1 = Cpu requests do not use this I/O range
	 * [ 3: 3] Lock
	 *	   0 = base/limit registers i are read/write
	 *	   1 = base/limit registers i are read-only
	 * [ 7: 4] Reserved
	 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
	 *	   This field defines the upper address bits of a 40bit address 
	 *	   that defines the start of memory-mapped I/O region i
	 */
	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,

	/* PCI I/O Limit i Registers
	 * F1:0xC4 i = 0
	 * F1:0xCC i = 1
	 * F1:0xD4 i = 2
	 * F1:0xDC i = 3
	 * [ 2: 0] Destination Node ID
	 *	   000 = Node 0
	 *	   001 = Node 1
	 *	   010 = Node 2
	 *	   011 = Node 3
	 *	   100 = Node 4
	 *	   101 = Node 5
	 *	   110 = Node 6
	 *	   111 = Node 7
	 * [ 3: 3] Reserved
	 * [ 5: 4] Destination Link ID
	 *	   00 = Link 0
	 *	   01 = Link 1
	 *	   10 = Link 2
	 *	   11 = reserved
	 * [11: 6] Reserved
	 * [24:12] PCI I/O Limit Address i
	 *	   This field defines the end of PCI I/O region n
	 * [31:25] Reserved
	 */
	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,

	/* PCI I/O Base i Registers
	 * F1:0xC0 i = 0
	 * F1:0xC8 i = 1
	 * F1:0xD0 i = 2
	 * F1:0xD8 i = 3
	 * [ 0: 0] Read Enable
	 *	   0 = Reads Disabled
	 *	   1 = Reads Enabled
	 * [ 1: 1] Write Enable
	 *	   0 = Writes Disabled
	 *	   1 = Writes Enabled
	 * [ 3: 2] Reserved
	 * [ 4: 4] VGA Enable
	 *	   0 = VGA matches Disabled
	 *	   1 = matches all address < 64K and where A[9:0] is in the 
	 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
	 * [ 5: 5] ISA Enable
	 *	   0 = ISA matches Disabled
	 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
	 *	       from matching agains this base/limit pair
	 * [11: 6] Reserved
	 * [24:12] PCI I/O Base i
	 *	   This field defines the start of PCI I/O region n 
	 * [31:25] Reserved
	 */
	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,

	/* Config Base and Limit i Registers
	 * F1:0xE0 i = 0
	 * F1:0xE4 i = 1
	 * F1:0xE8 i = 2
	 * F1:0xEC i = 3
	 * [ 0: 0] Read Enable
	 *	   0 = Reads Disabled
	 *	   1 = Reads Enabled
	 * [ 1: 1] Write Enable
	 *	   0 = Writes Disabled
	 *	   1 = Writes Enabled
	 * [ 2: 2] Device Number Compare Enable
	 *	   0 = The ranges are based on bus number
	 *	   1 = The ranges are ranges of devices on bus 0
	 * [ 3: 3] Reserved
	 * [ 6: 4] Destination Node
	 *	   000 = Node 0
	 *	   001 = Node 1
	 *	   010 = Node 2
	 *	   011 = Node 3
	 *	   100 = Node 4
	 *	   101 = Node 5
	 *	   110 = Node 6
	 *	   111 = Node 7
	 * [ 7: 7] Reserved
	 * [ 9: 8] Destination Link
	 *	   00 = Link 0
	 *	   01 = Link 1
	 *	   10 = Link 2
	 *	   11 - Reserved
	 * [15:10] Reserved
	 * [23:16] Bus Number Base i
	 *	   This field defines the lowest bus number in configuration region i
	 * [31:24] Bus Number Limit i
	 *	   This field defines the highest bus number in configuration regin i
	 */
	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
	};
	int max;
	max = sizeof(register_values)/sizeof(register_values[0]);
	setup_resource_map(register_values, max);
}

static void sdram_set_registers(const struct mem_controller *ctrl)
{
	static const unsigned int register_values[] = {

	/* Careful set limit registers before base registers which contain the enables */
	/* DRAM Limit i Registers
	 * F1:0x44 i = 0
	 * F1:0x4C i = 1
	 * F1:0x54 i = 2
	 * F1:0x5C i = 3
	 * F1:0x64 i = 4
	 * F1:0x6C i = 5
	 * F1:0x74 i = 6
	 * F1:0x7C i = 7
	 * [ 2: 0] Destination Node ID
	 *	   000 = Node 0
	 *	   001 = Node 1
	 *	   010 = Node 2
	 *	   011 = Node 3
	 *	   100 = Node 4
	 *	   101 = Node 5
	 *	   110 = Node 6
	 *	   111 = Node 7
	 * [ 7: 3] Reserved
	 * [10: 8] Interleave select
	 *	   specifies the values of A[14:12] to use with interleave enable.
	 * [15:11] Reserved
	 * [31:16] DRAM Limit Address i Bits 39-24
	 *	   This field defines the upper address bits of a 40 bit  address
	 *	   that define the end of the DRAM region.
	 */
	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
	/* DRAM Base i Registers
	 * F1:0x40 i = 0
	 * F1:0x48 i = 1
	 * F1:0x50 i = 2
	 * F1:0x58 i = 3
	 * F1:0x60 i = 4
	 * F1:0x68 i = 5
	 * F1:0x70 i = 6
	 * F1:0x78 i = 7
	 * [ 0: 0] Read Enable
	 *	   0 = Reads Disabled
	 *	   1 = Reads Enabled
	 * [ 1: 1] Write Enable
	 *	   0 = Writes Disabled
	 *	   1 = Writes Enabled
	 * [ 7: 2] Reserved
	 * [10: 8] Interleave Enable
	 *	   000 = No interleave
	 *	   001 = Interleave on A[12] (2 nodes)
	 *	   010 = reserved
	 *	   011 = Interleave on A[12] and A[14] (4 nodes)
	 *	   100 = reserved
	 *	   101 = reserved
	 *	   110 = reserved
	 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
	 * [15:11] Reserved
	 * [13:16] DRAM Base Address i Bits 39-24
	 *	   This field defines the upper address bits of a 40-bit address
	 *	   that define the start of the DRAM region.
	 */
	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,

	/* DRAM CS Base Address i Registers
	 * F2:0x40 i = 0
	 * F2:0x44 i = 1
	 * F2:0x48 i = 2
	 * F2:0x4C i = 3
	 * F2:0x50 i = 4
	 * F2:0x54 i = 5
	 * F2:0x58 i = 6
	 * F2:0x5C i = 7
	 * [ 0: 0] Chip-Select Bank Enable
	 *	   0 = Bank Disabled
	 *	   1 = Bank Enabled
	 * [ 8: 1] Reserved
	 * [15: 9] Base Address (19-13)
	 *	   An optimization used when all DIMM are the same size...
	 * [20:16] Reserved
	 * [31:21] Base Address (35-25)
	 *	   This field defines the top 11 addresses bit of a 40-bit
	 *	   address that define the memory address space.  These
	 *	   bits decode 32-MByte blocks of memory.
	 */
	PCI_ADDR(0, 0x18, 2, 0x40), 0x001f01fe, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x50), 0x001f01fe, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x54), 0x001f01fe, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x58), 0x001f01fe, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x5C), 0x001f01fe, 0x00000000,
	/* DRAM CS Mask Address i Registers
	 * F2:0x60 i = 0
	 * F2:0x64 i = 1
	 * F2:0x68 i = 2
	 * F2:0x6C i = 3
	 * F2:0x70 i = 4
	 * F2:0x74 i = 5
	 * F2:0x78 i = 6
	 * F2:0x7C i = 7
	 * Select bits to exclude from comparison with the DRAM Base address register.
	 * [ 8: 0] Reserved
	 * [15: 9] Address Mask (19-13)
	 *	   Address to be excluded from the optimized case
	 * [20:16] Reserved
	 * [29:21] Address Mask (33-25)
	 *	   The bits with an address mask of 1 are excluded from address comparison
	 * [31:30] Reserved
	 * 
	 */
	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x70), 0xC01f01ff, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x74), 0xC01f01ff, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x78), 0xC01f01ff, 0x00000000,
	PCI_ADDR(0, 0x18, 2, 0x7C), 0xC01f01ff, 0x00000000,
	/* DRAM Bank Address Mapping Register
	 * F2:0x80
	 * Specify the memory module size
	 * [ 2: 0] CS1/0 
	 * [ 6: 4] CS3/2
	 * [10: 8] CS5/4
	 * [14:12] CS7/6
	 *	   000 = 32Mbyte  (Rows = 12 & Col =  8)
	 *	   001 = 64Mbyte  (Rows = 12 & Col =  9)
	 *	   010 = 128Mbyte (Rows = 13 & Col =  9)|(Rows = 12 & Col = 10)
	 *	   011 = 256Mbyte (Rows = 13 & Col = 10)|(Rows = 12 & Col = 11)
	 *	   100 = 512Mbyte (Rows = 13 & Col = 11)|(Rows = 14 & Col = 10)
	 *	   101 = 1Gbyte	  (Rows = 14 & Col = 11)|(Rows = 13 & Col = 12)
	 *	   110 = 2Gbyte	  (Rows = 14 & Col = 12)
	 *	   111 = reserved 
	 * [ 3: 3] Reserved
	 * [ 7: 7] Reserved
	 * [11:11] Reserved
	 * [31:15]
	 */
	PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000000,
	/* DRAM Timing Low Register
	 * F2:0x88
	 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
	 *	   000 = reserved
	 *	   001 = CL 2
	 *	   010 = CL 3
	 *	   011 = reserved
	 *	   100 = reserved
	 *	   101 = CL 2.5
	 *	   110 = reserved
	 *	   111 = reserved
	 * [ 3: 3] Reserved
	 * [ 7: 4] Trc (Row Cycle Time, Ras#-active to Ras#-active/bank auto refresh)
	 *	   0000 =  7 bus clocks
	 *	   0001 =  8 bus clocks
	 *	   ...
	 *	   1110 = 21 bus clocks
	 *	   1111 = 22 bus clocks
	 * [11: 8] Trfc (Row refresh Cycle time, Auto-refresh-active to RAS#-active or RAS#auto-refresh)
	 *	   0000 = 9 bus clocks
	 *	   0010 = 10 bus clocks
	 *	   ....
	 *	   1110 = 23 bus clocks
	 *	   1111 = 24 bus clocks
	 * [14:12] Trcd (Ras#-active to Case#-read/write Delay)
	 *	   000 = reserved
	 *	   001 = reserved
	 *	   010 = 2 bus clocks
	 *	   011 = 3 bus clocks
	 *	   100 = 4 bus clocks
	 *	   101 = 5 bus clocks
	 *	   110 = 6 bus clocks
	 *	   111 = reserved
	 * [15:15] Reserved
	 * [18:16] Trrd (Ras# to Ras# Delay)
	 *	   000 = reserved
	 *	   001 = reserved
	 *	   010 = 2 bus clocks
	 *	   011 = 3 bus clocks
	 *	   100 = 4 bus clocks
	 *	   101 = reserved
	 *	   110 = reserved
	 *	   111 = reserved
	 * [19:19] Reserved
	 * [23:20] Tras (Minmum Ras# Active Time)
	 *	   0000 to 0100 = reserved
	 *	   0101 = 5 bus clocks
	 *	   ...
	 *	   1111 = 15 bus clocks
	 * [26:24] Trp (Row Precharge Time)
	 *	   000 = reserved
	 *	   001 = reserved
	 *	   010 = 2 bus clocks
	 *	   011 = 3 bus clocks
	 *	   100 = 4 bus clocks
	 *	   101 = 5 bus clocks
	 *	   110 = 6 bus clocks
	 *	   111 = reserved
	 * [27:27] Reserved
	 * [28:28] Twr (Write Recovery Time)
	 *	   0 = 2 bus clocks
	 *	   1 = 3 bus clocks
	 * [31:29] Reserved
	 */
	PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x02522001 /* 0x03623125 */ ,
	/* DRAM Timing High Register
	 * F2:0x8C
	 * [ 0: 0] Twtr (Write to Read Delay)
	 *	   0 = 1 bus Clocks
	 *	   1 = 2 bus Clocks
	 * [ 3: 1] Reserved
	 * [ 6: 4] Trwt (Read to Write Delay)
	 *	   000 = 1 bus clocks
	 *	   001 = 2 bus clocks
	 *	   010 = 3 bus clocks
	 *	   011 = 4 bus clocks
	 *	   100 = 5 bus clocks
	 *	   101 = 6 bus clocks
	 *	   110 = reserved
	 *	   111 = reserved
	 * [ 7: 7] Reserved
	 * [12: 8] Tref (Refresh Rate)
	 *	   00000 = 100Mhz 4K rows
	 *	   00001 = 133Mhz 4K rows
	 *	   00010 = 166Mhz 4K rows
	 *	   00011 = 200Mhz 4K rows
	 *	   01000 = 100Mhz 8K/16K rows
	 *	   01001 = 133Mhz 8K/16K rows
	 *	   01010 = 166Mhz 8K/16K rows
	 *	   01011 = 200Mhz 8K/16K rows
	 * [19:13] Reserved
	 * [22:20] Twcl (Write CAS Latency)
	 *	   000 = 1 Mem clock after CAS# (Unbuffered Dimms)
	 *	   001 = 2 Mem clocks after CAS# (Registered Dimms)
	 * [31:23] Reserved
	 */
	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0),
	/* DRAM Config Low Register
	 * F2:0x90
	 * [ 0: 0] DLL Disable
	 *	   0 = Enabled
	 *	   1 = Disabled
	 * [ 1: 1] D_DRV
	 *	   0 = Normal Drive
	 *	   1 = Weak Drive
	 * [ 2: 2] QFC_EN
	 *	   0 = Disabled
	 *	   1 = Enabled
	 * [ 3: 3] Disable DQS Hystersis  (FIXME handle this one carefully)
	 *	   0 = Enable DQS input filter 
	 *	   1 = Disable DQS input filtering 
	 * [ 7: 4] Reserved
	 * [ 8: 8] DRAM_Init
	 *	   0 = Initialization done or not yet started.
	 *	   1 = Initiate DRAM intialization sequence
	 * [ 9: 9] SO-Dimm Enable
	 *	   0 = Do nothing
	 *	   1 = SO-Dimms present
	 * [10:10] DramEnable
	 *	   0 = DRAM not enabled
	 *	   1 = DRAM initialized and enabled
	 * [11:11] Memory Clear Status
	 *	   0 = Memory Clear function has not completed
	 *	   1 = Memory Clear function has completed
	 * [12:12] Exit Self-Refresh
	 *	   0 = Exit from self-refresh done or not yet started
	 *	   1 = DRAM exiting from self refresh
	 * [13:13] Self-Refresh Status
	 *	   0 = Normal Operation
	 *	   1 = Self-refresh mode active
	 * [15:14] Read/Write Queue Bypass Count
	 *	   00 = 2
	 *	   01 = 4
	 *	   10 = 8
	 *	   11 = 16
	 * [16:16] 128-bit/64-Bit
	 *	   0 = 64bit Interface to DRAM
	 *	   1 = 128bit Interface to DRAM
	 * [17:17] DIMM ECC Enable
	 *	   0 = Some DIMMs do not have ECC
	 *	   1 = ALL DIMMS have ECC bits
	 * [18:18] UnBuffered DIMMs
	 *	   0 = Buffered DIMMS
	 *	   1 = Unbuffered DIMMS
	 * [19:19] Enable 32-Byte Granularity
	 *	   0 = Optimize for 64byte bursts
	 *	   1 = Optimize for 32byte bursts
	 * [20:20] DIMM 0 is x4
	 * [21:21] DIMM 1 is x4
	 * [22:22] DIMM 2 is x4
	 * [23:23] DIMM 3 is x4
	 *	   0 = DIMM is not x4
	 *	   1 = x4 DIMM present
	 * [24:24] Disable DRAM Receivers
	 *	   0 = Receivers enabled
	 *	   1 = Receivers disabled
	 * [27:25] Bypass Max
	 *	   000 = Arbiters chois is always respected
	 *	   001 = Oldest entry in DCQ can be bypassed 1 time
	 *	   010 = Oldest entry in DCQ can be bypassed 2 times
	 *	   011 = Oldest entry in DCQ can be bypassed 3 times
	 *	   100 = Oldest entry in DCQ can be bypassed 4 times
	 *	   101 = Oldest entry in DCQ can be bypassed 5 times
	 *	   110 = Oldest entry in DCQ can be bypassed 6 times
	 *	   111 = Oldest entry in DCQ can be bypassed 7 times
	 * [31:28] Reserved
	 */
	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
	(4 << 25)|(0 << 24)| 
	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| 
	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| 
	(2 << 14)|(0 << 13)|(0 << 12)| 
	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| 
	(0 << 3) |(0 << 1) |(0 << 0),
	/* DRAM Config High Register
	 * F2:0x94
	 * [ 0: 3] Maximum Asynchronous Latency
	 *	   0000 = 0 ns
	 *	   ...
	 *	   1111 = 15 ns
	 * [ 7: 4] Reserved
	 * [11: 8] Read Preamble
	 *	   0000 = 2.0 ns
	 *	   0001 = 2.5 ns
	 *	   0010 = 3.0 ns
	 *	   0011 = 3.5 ns
	 *	   0100 = 4.0 ns
	 *	   0101 = 4.5 ns
	 *	   0110 = 5.0 ns
	 *	   0111 = 5.5 ns
	 *	   1000 = 6.0 ns
	 *	   1001 = 6.5 ns
	 *	   1010 = 7.0 ns
	 *	   1011 = 7.5 ns
	 *	   1100 = 8.0 ns
	 *	   1101 = 8.5 ns
	 *	   1110 = 9.0 ns
	 *	   1111 = 9.5 ns
	 * [15:12] Reserved
	 * [18:16] Idle Cycle Limit
	 *	   000 = 0 cycles
	 *	   001 = 4 cycles
	 *	   010 = 8 cycles
	 *	   011 = 16 cycles
	 *	   100 = 32 cycles
	 *	   101 = 64 cycles
	 *	   110 = 128 cycles
	 *	   111 = 256 cycles
	 * [19:19] Dynamic Idle Cycle Center Enable
	 *	   0 = Use Idle Cycle Limit
	 *	   1 = Generate a dynamic Idle cycle limit
	 * [22:20] DRAM MEMCLK Frequency
	 *	   000 = 100Mhz
	 *	   001 = reserved
	 *	   010 = 133Mhz
	 *	   011 = reserved
	 *	   100 = reserved
	 *	   101 = 166Mhz
	 *	   110 = reserved
	 *	   111 = reserved
	 * [24:23] Reserved
	 * [25:25] Memory Clock Ratio Valid (FIXME carefully enable memclk)
	 *	   0 = Disable MemClks
	 *	   1 = Enable MemClks
	 * [26:26] Memory Clock 0 Enable
	 *	   0 = Disabled
	 *	   1 = Enabled
	 * [27:27] Memory Clock 1 Enable
	 *	   0 = Disabled
	 *	   1 = Enabled
	 * [28:28] Memory Clock 2 Enable
	 *	   0 = Disabled
	 *	   1 = Enabled
	 * [29:29] Memory Clock 3 Enable
	 *	   0 = Disabled
	 *	   1 = Enabled
	 * [31:30] Reserved
	 */
	PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0,
	(0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)|
	(0 << 20)|(0 << 19)|(DCH_IDLE_LIMIT_16 << 16)|(0 << 8)|(0 << 0),
	/* DRAM Delay Line Register
	 * F2:0x98
	 * Adjust the skew of the input DQS strobe relative to DATA
	 * [15: 0] Reserved
	 * [23:16] Delay Line Adjust
	 *	   Adjusts the DLL derived PDL delay by one or more delay stages
	 *	   in either the faster or slower direction.
	 * [24:24} Adjust Slower
	 *	   0 = Do Nothing
	 *	   1 = Adj is used to increase the PDL delay
	 * [25:25] Adjust Faster
	 *	   0 = Do Nothing
	 *	   1 = Adj is used to decrease the PDL delay
	 * [31:26] Reserved
	 */
	PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
	/* DRAM Scrub Control Register
	 * F3:0x58
	 * [ 4: 0] DRAM Scrube Rate
	 * [ 7: 5] reserved
	 * [12: 8] L2 Scrub Rate
	 * [15:13] reserved
	 * [20:16] Dcache Scrub
	 * [31:21] reserved
	 *	   Scrub Rates
	 *	   00000 = Do not scrub
	 *	   00001 =  40.00 ns
	 *	   00010 =  80.00 ns
	 *	   00011 = 160.00 ns
	 *	   00100 = 320.00 ns
	 *	   00101 = 640.00 ns
	 *	   00110 =   1.28 us
	 *	   00111 =   2.56 us
	 *	   01000 =   5.12 us
	 *	   01001 =  10.20 us
	 *	   01011 =  41.00 us
	 *	   01100 =  81.90 us
	 *	   01101 = 163.80 us
	 *	   01110 = 327.70 us
	 *	   01111 = 655.40 us
	 *	   10000 =   1.31 ms
	 *	   10001 =   2.62 ms
	 *	   10010 =   5.24 ms
	 *	   10011 =  10.49 ms
	 *	   10100 =  20.97 ms
	 *	   10101 =  42.00 ms
	 *	   10110 =  84.00 ms
	 *	   All Others = Reserved
	 */
	PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
	/* DRAM Scrub Address Low Register
	 * F3:0x5C
	 * [ 0: 0] DRAM Scrubber Redirect Enable
	 *	   0 = Do nothing
	 *	   1 = Scrubber Corrects errors found in normal operation
	 * [ 5: 1] Reserved
	 * [31: 6] DRAM Scrub Address 31-6
	 */
	PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
	/* DRAM Scrub Address High Register
	 * F3:0x60
	 * [ 7: 0] DRAM Scrubb Address 39-32
	 * [31: 8] Reserved
	 */
	PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
#if 0
//BY LYH  add IOMMU 64M APERTURE
	PCI_ADDR(0, 0x18, 3, 0x94), 0xffff8000, 0x00000f70,
	PCI_ADDR(0, 0x18, 3, 0x90), 0xffffff80, 0x00000002,
	PCI_ADDR(0, 0x18, 3, 0x98), 0x0000000f, 0x00068300,

//BY LYH END
#endif
	};
	int i;
	int max;
	print_debug("setting up CPU");
	print_debug_hex8(ctrl->node_id);
	print_debug(" northbridge registers\r\n");
	max = sizeof(register_values)/sizeof(register_values[0]);
	for(i = 0; i < max; i += 3) {
		device_t dev;
		unsigned where;
		unsigned long reg;
#if 0
		print_debug_hex32(register_values[i]);
		print_debug(" <-");
		print_debug_hex32(register_values[i+2]);
		print_debug("\r\n");
#endif
		dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
		where = register_values[i] & 0xff;
		reg = pci_read_config32(dev, where);
		reg &= register_values[i+1];
		reg |= register_values[i+2];
		pci_write_config32(dev, where, reg);
#if 0

		reg = pci_read_config32(register_values[i]);
		reg &= register_values[i+1];
		reg |= register_values[i+2];
		pci_write_config32(register_values[i], reg);
#endif
	}
	print_debug("done.\r\n");
}


static int is_dual_channel(const struct mem_controller *ctrl)
{
	uint32_t dcl;
	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
	return dcl & DCL_128BitEn;
}

static int is_opteron(const struct mem_controller *ctrl)
{
	/* Test to see if I am an Opteron.  
	 * FIXME Testing dual channel capability is correct for now
	 * but a beter test is probably required.
	 */
#warning "FIXME implement a better test for opterons"
	uint32_t nbcap;
	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
	return !!(nbcap & NBCAP_128Bit);
}

static int is_registered(const struct mem_controller *ctrl)
{
	/* Test to see if we are dealing with registered SDRAM.
	 * If we are not registered we are unbuffered.
	 * This function must be called after spd_handle_unbuffered_dimms.
	 */
	uint32_t dcl;
	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
	return !(dcl & DCL_UnBufDimm);
}

struct dimm_size {
	unsigned long side1;
	unsigned long side2;
};

static struct dimm_size spd_get_dimm_size(unsigned device)
{
	/* Calculate the log base 2 size of a DIMM in bits */
	struct dimm_size sz;
	int value, low;
	sz.side1 = 0;
	sz.side2 = 0;

	/* Note it might be easier to use byte 31 here, it has the DIMM size as
	 * a multiple of 4MB.  The way we do it now we can size both
	 * sides of an assymetric dimm.
	 */
	value = spd_read_byte(device, 3);	/* rows */
	if (value < 0) goto out;
	sz.side1 += value & 0xf;

	value = spd_read_byte(device, 4);	/* columns */
	if (value < 0) goto out;
	sz.side1 += value & 0xf;

	value = spd_read_byte(device, 17);	/* banks */
	if (value < 0) goto out;
	sz.side1 += log2(value & 0xff);

	/* Get the module data width and convert it to a power of two */
	value = spd_read_byte(device, 7);	/* (high byte) */
	if (value < 0) goto out;
	value &= 0xff;
	value <<= 8;
	
	low = spd_read_byte(device, 6);	/* (low byte) */
	if (low < 0) goto out;
	value = value | (low & 0xff);
	sz.side1 += log2(value);

	/* side 2 */
	value = spd_read_byte(device, 5);	/* number of physical banks */
	if (value <= 1) goto out;

	/* Start with the symmetrical case */
	sz.side2 = sz.side1;

	value = spd_read_byte(device, 3);	/* rows */
	if (value < 0) goto out;
	if ((value & 0xf0) == 0) goto out;	/* If symmetrical we are done */
	sz.side2 -= (value & 0x0f);		/* Subtract out rows on side 1 */
	sz.side2 += ((value >> 4) & 0x0f);	/* Add in rows on side 2 */

	value = spd_read_byte(device, 4);	/* columns */
	if (value < 0) goto out;
	sz.side2 -= (value & 0x0f);		/* Subtract out columns on side 1 */
	sz.side2 += ((value >> 4) & 0x0f);	/* Add in columsn on side 2 */

 out:
	return sz;
}

static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index)
{
	uint32_t base0, base1, map;
	uint32_t dch;

#if 0
	print_debug("set_dimm_size: (");
	print_debug_hex32(sz.side1);
	print_debug_char(',');
	print_debug_hex32(sz.side2);
	print_debug_char(',');
	print_debug_hex32(index);
	print_debug(")\r\n");
#endif
	if (sz.side1 != sz.side2) {
		sz.side2 = 0;
	}
	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
	map &= ~(0xf << (index + 4));

	/* For each base register.
	 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
	 * The initialize dimm size is in bits.
	 * Set the base enable bit0.
	 */
	
	base0 = base1 = 0;

	/* Make certain side1 of the dimm is at least 32MB */
	if (sz.side1 >= (25 +3)) {
		map |= (sz.side1 - (25 + 3)) << (index *4);
		base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1;
	}
	/* Make certain side2 of the dimm is at least 32MB */
	if (sz.side2 >= (25 + 3)) {
		base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1;
	}

	/* Double the size if we are using dual channel memory */
	if (is_dual_channel(ctrl)) {
		base0 = (base0 << 1) | (base0 & 1);
		base1 = (base1 << 1) | (base1 & 1);
	}

	/* Clear the reserved bits */
	base0 &= ~0x001ffffe;
	base1 &= ~0x001ffffe;

	/* Set the appropriate DIMM base address register */
	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
	pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
	
	/* Enable the memory clocks for this DIMM */
	if (base0) {
		dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
		dch |= DCH_MEMCLK_EN0 << index;
		pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
	}
}

static void spd_set_ram_size(const struct mem_controller *ctrl)
{
	int i;
	
	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
		struct dimm_size sz;
		sz = spd_get_dimm_size(ctrl->channel0[i]);
		set_dimm_size(ctrl, sz, i);
	}
}

static void route_dram_accesses(const struct mem_controller *ctrl,
	unsigned long base_k, unsigned long limit_k)
{
	/* Route the addresses to the controller node */
	unsigned node_id;
	unsigned limit;
	unsigned base;
	unsigned index;
	unsigned limit_reg, base_reg;
	device_t device;

	node_id = ctrl->node_id;
	index = (node_id << 3);
	limit = (limit_k << 2);
	limit &= 0xffff0000;
	limit -= 0x00010000;
	limit |= ( 0 << 8) | (node_id << 0);
	base = (base_k << 2);
	base &= 0xffff0000;
	base |= (0 << 8) | (1<<1) | (1<<0);

	limit_reg = 0x44 + index;
	base_reg = 0x40 + index;
	for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
		pci_write_config32(device, limit_reg, limit);
		pci_write_config32(device, base_reg, base);
	}
}

static void set_top_mem(unsigned tom_k)
{
	/* Error if I don't have memory */
	if (!tom_k) {
		die("No memory");
	}

#if 1
	/* Report the amount of memory. */
	print_debug("RAM: 0x");
	print_debug_hex32(tom_k);
	print_debug(" KB\r\n");
#endif

	/* Now set top of memory */
	msr_t msr;
	msr.lo = (tom_k & 0x003fffff) << 10;
	msr.hi = (tom_k & 0xffc00000) >> 22;
	wrmsr(TOP_MEM2, msr);

	/* Leave a 64M hole between TOP_MEM and TOP_MEM2
	 * so I can see my rom chip and other I/O devices.
	 */
	if (tom_k >= 0x003f0000) {
		tom_k = 0x3f0000;
	}
	msr.lo = (tom_k & 0x003fffff) << 10;
	msr.hi = (tom_k & 0xffc00000) >> 22;
	wrmsr(TOP_MEM, msr);
}

static void order_dimms(const struct mem_controller *ctrl)
{
	unsigned long tom, tom_k, base_k;
	unsigned node_id;

	/* Compute the memory base address address */
	base_k = 0;
	/* Remember which registers we have used in the high 8 bits of tom */
	tom = base_k >> 15;
	for(;;) {
		/* Find the largest remaining canidate */
		unsigned index, canidate;
		uint32_t csbase, csmask;
		unsigned size;
		csbase = 0;
		canidate = 0;
		for(index = 0; index < 8; index++) {
			uint32_t value;
			value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));

			/* Is it enabled? */
			if (!(value & 1)) {
				continue;
			}
			
			/* Is it greater? */
			if (value <= csbase) {
				continue;
			}
			
			/* Has it already been selected */
			if (tom & (1 << (index + 24))) {
				continue;
			}
			/* I have a new canidate */
			csbase = value;
			canidate = index;
		}
		/* See if I have found a new canidate */
		if (csbase == 0) {
			break;
		}

		/* Remember the dimm size */
		size = csbase >> 21;

		/* Remember I have used this register */
		tom |= (1 << (canidate + 24));

		/* Recompute the cs base register value */
		csbase = (tom << 21) | 1;

		/* Increment the top of memory */
		tom += size;

		/* Compute the memory mask */
		csmask = ((size -1) << 21);
		csmask |= 0xfe00;		/* For now don't optimize */
#warning "Don't forget to optimize the DIMM size"

		/* Write the new base register */
		pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
		/* Write the new mask register */
		pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
		
	}
	tom_k = (tom & ~0xff000000) << 15;

	/* Compute the memory base address */
	base_k = 0;
	for(node_id = 0; node_id < ctrl->node_id; node_id++) {
		uint32_t limit, base;
		unsigned index;
		index = node_id << 3;
		base = pci_read_config32(ctrl->f1, 0x40 + index);
		/* Only look at the limit if the base is enabled */
		if ((base & 3) == 3) {
			limit = pci_read_config32(ctrl->f1, 0x44 + index);
			base_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
		}
	}
	tom_k += base_k;
#if 0
	print_debug("tom: ");
	print_debug_hex32(tom);
	print_debug(" base_k: ");
	print_debug_hex32(base_k);
	print_debug(" tom_k: ");
	print_debug_hex32(tom_k);
	print_debug("\r\n");
#endif
	route_dram_accesses(ctrl, base_k, tom_k);
	set_top_mem(tom_k);
}

static void disable_dimm(const struct mem_controller *ctrl, unsigned index)
{
	print_debug("disabling dimm"); 
	print_debug_hex8(index); 
	print_debug("\r\n");
	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
}


static void spd_handle_unbuffered_dimms(const struct mem_controller *ctrl)
{
	int i;
	int registered;
	int unbuffered;
	uint32_t dcl;
	unbuffered = 0;
	registered = 0;
	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
		int value;
		value = spd_read_byte(ctrl->channel0[i], 21);
		if (value < 0) {
			disable_dimm(ctrl, i);
			continue;
		}
		/* Registered dimm ? */
		if (value & (1 << 1)) {
			registered = 1;
		} 
		/* Otherwise it must be an unbuffered dimm */
		else {
			unbuffered = 1;
		}
	}
	if (unbuffered && registered) {
		die("Mixed buffered and registered dimms not supported");
	}
	if (unbuffered && is_opteron(ctrl)) {
		die("Unbuffered Dimms not supported on Opteron");
	}

	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
	dcl &= ~DCL_UnBufDimm;
	if (unbuffered) {
		dcl |= DCL_UnBufDimm;
	}
	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
#if 0
	if (is_registered(ctrl)) {
		print_debug("Registered\r\n");
	} else {
		print_debug("Unbuffered\r\n");
	}
#endif
}

static void spd_enable_2channels(const struct mem_controller *ctrl)
{
	int i;
	uint32_t nbcap;
	/* SPD addresses to verify are identical */
#warning "FINISHME review and see if these are the bytes I need"
	/* FINISHME review and see if these are the bytes I need */
	static const unsigned addresses[] = {
		2,	/* Type should be DDR SDRAM */
		3,	/* *Row addresses */
		4,	/* *Column addresses */
		5,	/* *Physical Banks */
		6,	/* *Module Data Width low */
		7,	/* *Module Data Width high */
		9,	/* *Cycle time at highest CAS Latency CL=X */
		11,	/* *SDRAM Type */
		13,	/* *SDRAM Width */
		17,	/* *Logical Banks */
		18,	/* *Supported CAS Latencies */
		21,	/* *SDRAM Module Attributes */
		23,	/* *Cycle time at CAS Latnecy (CLX - 0.5) */
		26,	/* *Cycle time at CAS Latnecy (CLX - 1.0) */
		27,	/* *tRP Row precharge time */
		28,	/* *Minimum Row Active to Row Active Delay (tRRD) */
		29,	/* *tRCD RAS to CAS */
		30,	/* *tRAS Activate to Precharge */
		41,	/* *Minimum Active to Active/Auto Refresh Time(Trc) */
		42,	/* *Minimum Auto Refresh Command Time(Trfc) */
	};
	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
	if (!(nbcap & NBCAP_128Bit)) {
		return;
	}
	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
		unsigned device0, device1;
		int value0, value1;
		int j;
		device0 = ctrl->channel0[i];
		device1 = ctrl->channel1[i];
		if (!device1)
			return;
		for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
			unsigned addr;
			addr = addresses[j];
			value0 = spd_read_byte(device0, addr);
			if (value0 < 0) {
				break;
			}
			value1 = spd_read_byte(device1, addr);
			if (value1 < 0) {
				return;
			}
			if (value0 != value1) {
				return;
			}
		}
	}
	print_debug("Enabling dual channel memory\r\n");
	uint32_t dcl;
	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
	dcl &= ~DCL_32ByteEn;
	dcl |= DCL_128BitEn;
	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
}

struct mem_param {
	uint8_t cycle_time;
	uint8_t divisor; /* In 1/2 ns increments */
	uint8_t tRC;
	uint8_t tRFC;
	uint32_t dch_memclk;
	uint16_t dch_tref4k, dch_tref8k;
	uint8_t	 dtl_twr;
	char name[9];
};

static const struct mem_param *get_mem_param(unsigned min_cycle_time)
{
	static const struct mem_param speed[] = {
		{
			.name	    = "100Mhz\r\n",
			.cycle_time = 0xa0,
			.divisor    = (10 <<1),
			.tRC	    = 0x46,
			.tRFC	    = 0x50,
			.dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT,
			.dch_tref4k = DTH_TREF_100MHZ_4K,
			.dch_tref8k = DTH_TREF_100MHZ_8K,
			.dtl_twr    = 2,
		},
		{
			.name	    = "133Mhz\r\n",
			.cycle_time = 0x75,
			.divisor    = (7<<1)+1,
			.tRC	    = 0x41,
			.tRFC	    = 0x4B,
			.dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,
			.dch_tref4k = DTH_TREF_133MHZ_4K,
			.dch_tref8k = DTH_TREF_133MHZ_8K,
			.dtl_twr    = 2,
		},
		{
			.name	    = "166Mhz\r\n",
			.cycle_time = 0x60,
			.divisor    = (6<<1),
			.tRC	    = 0x3C,
			.tRFC	    = 0x48,
			.dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,
			.dch_tref4k = DTH_TREF_166MHZ_4K,
			.dch_tref8k = DTH_TREF_166MHZ_8K,
			.dtl_twr    = 3,
		},
		{
			.name	    = "200Mhz\r\n",
			.cycle_time = 0x50,
			.divisor    = (5<<1),
			.tRC	    = 0x37,
			.tRFC	    = 0x46,
			.dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,
			.dch_tref4k = DTH_TREF_200MHZ_4K,
			.dch_tref8k = DTH_TREF_200MHZ_8K,
			.dtl_twr    = 3,
		},
		{
			.cycle_time = 0x00,
		},
	};
	const struct mem_param *param;
	for(param = &speed[0]; param->cycle_time ; param++) {
		if (min_cycle_time > (param+1)->cycle_time) {
			break;
		}
	}
	if (!param->cycle_time) {
		die("min_cycle_time to low");
	}
#if 1
	print_debug(param->name);
#endif
	return param;
}

static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl)
{
	/* Compute the minimum cycle time for these dimms */
	const struct mem_param *param;
	unsigned min_cycle_time, min_latency;
	int i;
	uint32_t value;

	static const int latency_indicies[] = { 26, 23, 9 };
	static const unsigned char min_cycle_times[] = {
		[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
		[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
		[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
		[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
	};


	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
	min_latency = 2;

#if 0
	print_debug("min_cycle_time: "); 
	print_debug_hex8(min_cycle_time); 
	print_debug(" min_latency: ");
	print_debug_hex8(min_latency);
	print_debug("\r\n");
#endif

	/* Compute the least latency with the fastest clock supported
	 * by both the memory controller and the dimms.
	 */
	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
		int new_cycle_time, new_latency;
		int index;
		int latencies;
		int latency;

		/* First find the supported CAS latencies
		 * Byte 18 for DDR SDRAM is interpreted:
		 * bit 0 == CAS Latency = 1.0
		 * bit 1 == CAS Latency = 1.5
		 * bit 2 == CAS Latency = 2.0
		 * bit 3 == CAS Latency = 2.5
		 * bit 4 == CAS Latency = 3.0
		 * bit 5 == CAS Latency = 3.5
		 * bit 6 == TBD
		 * bit 7 == TBD
		 */
		new_cycle_time = 0xa0;
		new_latency = 5;

		latencies = spd_read_byte(ctrl->channel0[i], 18);
		if (latencies <= 0) continue;

		/* Compute the lowest cas latency supported */
		latency = log2(latencies) -2;

		/* Loop through and find a fast clock with a low latency */
		for(index = 0; index < 3; index++, latency++) {
			int value;
			if ((latency < 2) || (latency > 4) ||
				(!(latencies & (1 << latency)))) {
				continue;
			}
			value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
			if (value < 0) {
				continue;
			}

			/* Only increase the latency if we decreas the clock */
			if ((value >= min_cycle_time) && (value < new_cycle_time)) {
				new_cycle_time = value;
				new_latency = latency;
			}
		}
		if (new_latency > 4){
			continue;
		}
		/* Does min_latency need to be increased? */
		if (new_cycle_time > min_cycle_time) {
			min_cycle_time = new_cycle_time;
		}
		/* Does min_cycle_time need to be increased? */
		if (new_latency > min_latency) {
			min_latency = new_latency;
		}
#if 0
		print_debug("i: ");
		print_debug_hex8(i);
		print_debug(" min_cycle_time: "); 
		print_debug_hex8(min_cycle_time); 
		print_debug(" min_latency: ");
		print_debug_hex8(min_latency);
		print_debug("\r\n");
#endif
	}
	/* Make a second pass through the dimms and disable
	 * any that cannot support the selected memclk and cas latency.
	 */
	
	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
		int latencies;
		int latency;
		int index;
		int value;
		int dimm;
		latencies = spd_read_byte(ctrl->channel0[i], 18);
		if (latencies <= 0) {
			goto dimm_err;
		}

		/* Compute the lowest cas latency supported */
		latency = log2(latencies) -2;

		/* Walk through searching for the selected latency */
		for(index = 0; index < 3; index++, latency++) {
			if (!(latencies & (1 << latency))) {
				continue;
			}
			if (latency == min_latency)
				break;
		}
		/* If I can't find the latency or my index is bad error */
		if ((latency != min_latency) || (index >= 3)) {
			goto dimm_err;
		}
		
		/* Read the min_cycle_time for this latency */
		value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
		
		/* All is good if the selected clock speed 
		 * is what I need or slower.
		 */
		if (value <= min_cycle_time) {
			continue;
		}
		/* Otherwise I have an error, disable the dimm */
	dimm_err:
		disable_dimm(ctrl, i);
	}
#if 0
	print_debug("min_cycle_time: "); 
	print_debug_hex8(min_cycle_time); 
	print_debug(" min_latency: ");
	print_debug_hex8(min_latency);
	print_debug("\r\n");
#endif
	/* Now that I know the minimum cycle time lookup the memory parameters */
	param = get_mem_param(min_cycle_time);

	/* Update DRAM Config High with our selected memory speed */
	value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
	value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
	value |= param->dch_memclk;
	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);

	static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
	/* Update DRAM Timing Low with our selected cas latency */
	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
	value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
	
	return param;
}


static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	unsigned clocks, old_clocks;
	uint32_t dtl;
	int value;
	value = spd_read_byte(ctrl->channel0[i], 41);
	if (value < 0) return -1;
	if ((value == 0) || (value == 0xff)) {
		value = param->tRC;
	}
	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
	if (clocks < DTL_TRC_MIN) {
		clocks = DTL_TRC_MIN;
	}
	if (clocks > DTL_TRC_MAX) {
		return -1;
	}

	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
	if (old_clocks > clocks) {
		clocks = old_clocks;
	}
	dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
	dtl |=	((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
	return 0;
}

static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	unsigned clocks, old_clocks;
	uint32_t dtl;
	int value;
	value = spd_read_byte(ctrl->channel0[i], 42);
	if (value < 0) return -1;
	if ((value == 0) || (value == 0xff)) {
		value = param->tRFC;
	}
	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
	if (clocks < DTL_TRFC_MIN) {
		clocks = DTL_TRFC_MIN;
	}
	if (clocks > DTL_TRFC_MAX) {
		return -1;
	}
	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
	if (old_clocks > clocks) {
		clocks = old_clocks;
	}
	dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
	dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
	return 0;
}


static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	unsigned clocks, old_clocks;
	uint32_t dtl;
	int value;
	value = spd_read_byte(ctrl->channel0[i], 29);
	if (value < 0) return -1;
#if 0
	clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
#else
	clocks = (value + ((param->divisor & 0xff) << 1) -1)/((param->divisor & 0xff) << 1);
#endif
	if (clocks < DTL_TRCD_MIN) {
		clocks = DTL_TRCD_MIN;
	}
	if (clocks > DTL_TRCD_MAX) {
		return -1;
	}
	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
	if (old_clocks > clocks) {
		clocks = old_clocks;
	}
	dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
	dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
	return 0;
}

static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	unsigned clocks, old_clocks;
	uint32_t dtl;
	int value;
	value = spd_read_byte(ctrl->channel0[i], 28);
	if (value < 0) return -1;
	clocks = (value + ((param->divisor & 0xff) << 1) -1)/((param->divisor & 0xff) << 1);
	if (clocks < DTL_TRRD_MIN) {
		clocks = DTL_TRRD_MIN;
	}
	if (clocks > DTL_TRRD_MAX) {
		return -1;
	}
	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
	if (old_clocks > clocks) {
		clocks = old_clocks;
	}
	dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
	dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
	return 0;
}

static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	unsigned clocks, old_clocks;
	uint32_t dtl;
	int value;
	value = spd_read_byte(ctrl->channel0[i], 30);
	if (value < 0) return -1;
	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
	if (clocks < DTL_TRAS_MIN) {
		clocks = DTL_TRAS_MIN;
	}
	if (clocks > DTL_TRAS_MAX) {
		return -1;
	}
	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
	if (old_clocks > clocks) {
		clocks = old_clocks;
	}
	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
	dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
	return 0;
}

static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	unsigned clocks, old_clocks;
	uint32_t dtl;
	int value;
	value = spd_read_byte(ctrl->channel0[i], 27);
	if (value < 0) return -1;
#if 0
	clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1);
#else
	clocks = (value + ((param->divisor & 0xff) << 1) - 1)/((param->divisor & 0xff) << 1);
#endif
#if 0
	print_debug("Trp: ");
	print_debug_hex8(clocks);
	print_debug(" spd value: ");
	print_debug_hex8(value);
	print_debug(" divisor: ");
	print_debug_hex8(param->divisor);
	print_debug("\r\n");
#endif
	if (clocks < DTL_TRP_MIN) {
		clocks = DTL_TRP_MIN;
	}
	if (clocks > DTL_TRP_MAX) {
		return -1;
	}
	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
	if (old_clocks > clocks) {
		clocks = old_clocks;
	}
	dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
	dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
	return 0;
}

static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
{
	uint32_t dtl;
	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
	dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
}


static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
{
	uint32_t dth;
	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
	dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
}

static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	uint32_t dth;
	int value;
	unsigned tref, old_tref;
	value = spd_read_byte(ctrl->channel0[i], 3);
	if (value < 0) return -1;
	value &= 0xf;

	tref = param->dch_tref8k;
	if (value == 12) {
		tref = param->dch_tref4k;
	}

	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
	old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
	if ((value == 12) && (old_tref == param->dch_tref4k)) {
		tref = param->dch_tref4k;
	} else {
		tref = param->dch_tref8k;
	}
	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
	dth |= (tref << DTH_TREF_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
	return 0;
}


static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	uint32_t dcl;
	int value;
	int dimm;
	value = spd_read_byte(ctrl->channel0[i], 13);
	if (value < 0) {
		return -1;
	}
	dimm = i;
	dimm += DCL_x4DIMM_SHIFT;
	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
	dcl &= ~(1 << dimm);
	if (value == 4) {
		dcl |= (1 << dimm);
	}
	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
	return 0;
}

static int update_dimm_ecc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
{
	uint32_t dcl;
	int value;
	value = spd_read_byte(ctrl->channel0[i], 11);
	if (value < 0) {
		return -1;
	}
	if (value != 2) {
		dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
		dcl &= ~DCL_DimmEccEn;
		pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
	}
	return 0;
}

static int count_dimms(const struct mem_controller *ctrl)
{
	int dimms;
	unsigned index;
	dimms = 0;
	for(index = 0; index < 8; index += 2) {
		uint32_t csbase;
		csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + index << 2));
		if (csbase & 1) {
			dimms += 1;
		}
	}
	return dimms;
}

static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param)
{
	uint32_t dth;
	unsigned clocks;
	clocks = 1; /* AMD says hard code this */
	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
	dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
	dth |= ((clocks - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
}

static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
{
	uint32_t dth, dtl;
	unsigned divisor;
	unsigned latency;
	unsigned clocks;

	clocks = 0;
	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
	latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
	divisor = param->divisor;

	if (is_opteron(ctrl)) {
		if (latency == DTL_CL_2) {
			if (divisor == ((6 << 0) + 0)) {
				/* 166Mhz */
				clocks = 3;
			}
			else if (divisor > ((6 << 0)+0)) {
				/* 100Mhz && 133Mhz */
				clocks = 2;
			}
		}
		else if (latency == DTL_CL_2_5) {
			clocks = 3;
		}
		else if (latency == DTL_CL_3) {
			if (divisor == ((6 << 0)+0)) {
				/* 166Mhz */
				clocks = 4;
			}
			else if (divisor > ((6 << 0)+0)) {
				/* 100Mhz && 133Mhz */
				clocks = 3;
			}
		}
	}
	else /* Athlon64 */ {
		if (is_registered(ctrl)) {
			if (latency == DTL_CL_2) {
				clocks = 2;
			}
			else if (latency == DTL_CL_2_5) {
				clocks = 3;
			}
			else if (latency == DTL_CL_3) {
				clocks = 3;
			}
		}
		else /* Unbuffered */{
			if (latency == DTL_CL_2) {
				clocks = 3;
			}
			else if (latency == DTL_CL_2_5) {
				clocks = 4;
			}
			else if (latency == DTL_CL_3) {
				clocks = 4;
			}
		}
	}
	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
		die("Unknown Trwt");
	}
	
	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
	dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
	dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
	return;
}

static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param)
{
	/* Memory Clocks after CAS# */
	uint32_t dth;
	unsigned clocks;
	if (is_registered(ctrl)) {
		clocks = 2;
	} else {
		clocks = 1;
	}
	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
	dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
	dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
}


static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param)
{
	uint32_t dch;
	unsigned divisor;
	unsigned rdpreamble;
	divisor = param->divisor;
	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
	rdpreamble = 0;
	if (is_registered(ctrl)) {
		if (divisor == ((10 << 1)+0)) {
			/* 100Mhz, 9ns */
			rdpreamble = ((9 << 1)+ 0);
		}
		else if (divisor == ((7 << 1)+1)) {
			/* 133Mhz, 8ns */
			rdpreamble = ((8 << 1)+0);
		}
		else if (divisor == ((6 << 1)+0)) {
			/* 166Mhz, 7.5ns */
			rdpreamble = ((7 << 1)+1);
		}
	}
	else {
		int slots;
		int i;
		slots = 0;
		for(i = 0; i < 4; i++) {
			if (ctrl->channel0[i]) {
				slots += 1;
			}
		}
		if (divisor == ((10 << 1)+0)) {
			/* 100Mhz */
			if (slots <= 2) {
				/* 9ns */
				rdpreamble = ((9 << 1)+0);
			} else {
				/* 14ns */
				rdpreamble = ((14 << 1)+0);
			}
		}
		else if (divisor == ((7 << 1)+1)) {
			/* 133Mhz */
			if (slots <= 2) {
				/* 7ns */
				rdpreamble = ((7 << 1)+0);
			} else {
				/* 11 ns */
				rdpreamble = ((11 << 1)+0);
			}
		}
		else if (divisor == ((6 << 1)+0)) {
			/* 166Mhz */
			if (slots <= 2) {
				/* 6ns */
				rdpreamble = ((7 << 1)+0);
			} else {
				/* 9ns */
				rdpreamble = ((9 << 1)+0);
			}
		}
		else if (divisor == ((5 << 1)+0)) {
			/* 200Mhz */
			if (slots <= 2) {
				/* 5ns */
				rdpreamble = ((5 << 1)+0);
			} else {
				/* 7ns */
				rdpreamble = ((7 << 1)+0);
			}
		}
	}
	if ((rdpreamble < DCH_RDPREAMBLE_MIN) || (rdpreamble > DCH_RDPREAMBLE_MAX)) {
		die("Unknown rdpreamble");
	}
	dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}

static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
{
	uint32_t dch;
	int i;
	unsigned async_lat;
	int dimms;

	dimms = count_dimms(ctrl);

	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
	dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
	async_lat = 0;
	if (is_registered(ctrl)) {
		if (dimms == 4) {
			/* 9ns */
			async_lat = 9;
		} 
		else {
			/* 8ns */
			async_lat = 8;
		}
	}
	else {
		if (dimms > 3) {
			die("Too many unbuffered dimms");
		}
		else if (dimms == 3) {
			/* 7ns */
			async_lat = 7;
		}
		else {
			/* 6ns */
			async_lat = 6;
		}
	}
	dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}

static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
{
	uint32_t dch;
	/* AMD says to Hardcode this */
	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
	dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
	dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
	dch |= DCH_DYN_IDLE_CTR_EN;
	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}

static void spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param)
{
	int dimms;
	int i;
	init_Tref(ctrl, param);
	for(i = 0; (i < 4) && ctrl->channel0[i]; i++) {
		int rc;
		/* DRAM Timing Low Register */
		if (update_dimm_Trc (ctrl, param, i) < 0) goto dimm_err;
		if (update_dimm_Trfc(ctrl, param, i) < 0) goto dimm_err;
		if (update_dimm_Trcd(ctrl, param, i) < 0) goto dimm_err;
		if (update_dimm_Trrd(ctrl, param, i) < 0) goto dimm_err;
		if (update_dimm_Tras(ctrl, param, i) < 0) goto dimm_err;
		if (update_dimm_Trp (ctrl, param, i) < 0) goto dimm_err;

		/* DRAM Timing High Register */
		if (update_dimm_Tref(ctrl, param, i) < 0) goto dimm_err;

		/* DRAM Config Low */
		if (update_dimm_x4 (ctrl, param, i) < 0) goto dimm_err;
		if (update_dimm_ecc(ctrl, param, i) < 0) goto dimm_err;
		continue;
	dimm_err:
		disable_dimm(ctrl, i);
		
	}
	/* DRAM Timing Low Register */
	set_Twr(ctrl, param);

	/* DRAM Timing High Register */
	set_Twtr(ctrl, param);
	set_Trwt(ctrl, param);
	set_Twcl(ctrl, param);

	/* DRAM Config High */
	set_read_preamble(ctrl, param);
	set_max_async_latency(ctrl, param);
	set_idle_cycle_limit(ctrl, param);
}

static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
{
	const struct mem_param *param;
	spd_enable_2channels(ctrl);
	spd_set_ram_size(ctrl);
	spd_handle_unbuffered_dimms(ctrl);
	param = spd_set_memclk(ctrl);
	spd_set_dram_timing(ctrl, param);
	order_dimms(ctrl);
}

#define TIMEOUT_LOOPS 300000
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
	int i;

	/* Before enabling memory start the memory clocks */
	for(i = 0; i < controllers; i++) {
		uint32_t dch;
		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
		dch |= DCH_MEMCLK_VALID;
		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
	}

	/* And if necessary toggle the the reset on the dimms by hand */
	memreset(controllers, ctrl);

	for(i = 0; i < controllers; i++) {
		uint32_t dcl;
		/* Toggle DisDqsHys to get it working */
		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
#if 0
		print_debug("dcl: ");
		print_debug_hex32(dcl);
		print_debug("\r\n");
#endif
		if (dcl & DCL_DimmEccEn) {
			uint32_t mnc;
			print_debug("ECC enabled\r\n");
			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
			mnc |= MNC_ECC_EN;
			if (dcl & DCL_128BitEn) {
				mnc |= MNC_CHIPKILL_EN;
			}
			pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
		}
		dcl |= DCL_DisDqsHys;
		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
		dcl &= ~DCL_DisDqsHys;
		dcl &= ~DCL_DLL_Disable;
		dcl &= ~DCL_D_DRV;
		dcl &= ~DCL_QFC_EN;
		dcl |= DCL_DramInit;
		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);

	}
	for(i = 0; i < controllers; i++) {
		uint32_t dcl;
		print_debug("Initializing memory: ");
		int loops = 0;
		do {
			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
			loops += 1;
			if ((loops & 1023) == 0) {
				print_debug(".");
			}
		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
		if (loops >= TIMEOUT_LOOPS) {
			print_debug(" failed\r\n");
		} else {
			print_debug(" done\r\n");
		}
		if (dcl & DCL_DimmEccEn) {
			print_debug("Clearing memory: ");
			if (is_cpu_pre_c0()) {
				/* Kick the memory scrubber into high gear and scrub everything */
				uint32_t base, last_scrub_k, scrub_k;
				/* First make certain the scrubber is disabled */
				pci_write_config32(ctrl[i].f3, SCRUB_CONTROL,
					(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
				/* Set the scrub base address */
				base = pci_read_config32(ctrl[i].f1, 0x40 + (ctrl[i].node_id << 3));
				base &= 0xffff0000;
				pci_write_config32(ctrl[i].f3, SCRUB_ADDR_LOW,  base << 8);
				pci_write_config32(ctrl[i].f3, SCRUB_ADDR_HIGH, base >> 24);
				/* Enable DRAM scrubbing at full speed */
				pci_write_config32(ctrl[i].f3, SCRUB_CONTROL,
					(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_40ns << 0));
				scrub_k = 0;
				/* Wait until the DRAM Scrubber gets past 0k */
				while(scrub_k == 0) {
					scrub_k = pci_read_config32(ctrl[i].f3, SCRUB_ADDR_LOW) >> 10;
					scrub_k |= pci_read_config32(ctrl[i].f3, SCRUB_ADDR_HIGH) << 22;
				}
				/* Wait until the DRAM Scrubber loops */
				do {
					last_scrub_k = scrub_k;
					scrub_k = pci_read_config32(ctrl[i].f3, SCRUB_ADDR_LOW) >> 10;
					scrub_k |= pci_read_config32(ctrl[i].f3, SCRUB_ADDR_HIGH) << 22;
				} while(last_scrub_k <= scrub_k);
				/* Now stop the scrubber */
				pci_write_config32(ctrl[i].f3, SCRUB_CONTROL,
					(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
			}
			else {
				/* Wait until the automatic ram scrubber is finished */
				dcl &= ~DCL_MemClrStatus;
				pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
				do {
					dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
				} while((dcl & DCL_MemClrStatus) == 0);
			}
			print_debug("done\r\n");
			uint32_t base;
			/* Disable scrubbing so it is safe to set the scrub address */
			pci_write_config32(ctrl[i].f3, SCRUB_CONTROL,
				(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));

			/* Find the Srub base address for this cpu */
			base = pci_read_config32(ctrl[i].f1, 0x40 + (ctrl[i].node_id << 3));
			base &= 0xffff0000;

			/* Set the scrub base address registers */
			pci_write_config32(ctrl[i].f3, SCRUB_ADDR_LOW, base << 8);
			pci_write_config32(ctrl[i].f3, SCRUB_ADDR_HIGH, base >> 24);

			/* Enable scrubbing at the lowest possible rate */
			pci_write_config32(ctrl[i].f3, SCRUB_CONTROL, 
				(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
		}
	}
}



From YhLu at tyan.com  Thu Jul 31 23:50:01 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jul 31 23:50:01 2003
Subject: Fixes for Tyan s2880
Message-ID: <3174569B9743D511922F00A0C943142302FCA03E@TYANWEB>

Eric,

Several Macro in console/console.h should be changed.

For example: 
#define print_debug_hex8(HEX) printk_debug("0x08x", ((HEX))
#define print_debug_hex16(HEX) printk_debug("0x016x", ((HEX))
#define print_debug_hex32(HEX) printk_debug("0x032x", ((HEX))

to:
#define print_debug_hex8(HEX) printk_debug("0x02x", ((HEX))
#define print_debug_hex16(HEX) printk_debug("0x04x", ((HEX))
#define print_debug_hex32(HEX) printk_debug("0x08x", ((HEX))

regards

Yinghai Lu


-----????-----
???: YhLu 
????: 2003?7?31? 20:44
???: ebiederman at lnxi.com
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: ??: Fixes for Tyan s2880

Eric,

I see.

I move some code from raminit.c setup_top_ram to it and have a try.

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?7?31? 20:40
???: YhLu
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: Fixes for Tyan s2880

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have checked your old k8/cpufixup.c, and it already has TOM2 etc setup.
> and SYSCFG_TOM2_EN...etc...

I shift by 12 instead of 10 for the low half of TOP_MEM2...

Which tends to leave TOP_MEM2 at 4GB...

Eric
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From YhLu at tyan.com  Thu Jul 31 23:55:00 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jul 31 23:55:00 2003
Subject: Fixes for Tyan s2880
Message-ID: <3174569B9743D511922F00A0C943142302FCA03F@TYANWEB>

Eric,

It works. For 6G.  Tommorrow I will try 12G.

Thanks.

Yinghai Lu

-----????-----
???: YhLu 
????: 2003?7?31? 20:44
???: ebiederman at lnxi.com
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: ??: Fixes for Tyan s2880

Eric,

I see.

I move some code from raminit.c setup_top_ram to it and have a try.

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?7?31? 20:40
???: YhLu
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: Re: Fixes for Tyan s2880

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have checked your old k8/cpufixup.c, and it already has TOM2 etc setup.
> and SYSCFG_TOM2_EN...etc...

I shift by 12 instead of 10 for the low half of TOP_MEM2...

Which tends to leave TOP_MEM2 at 4GB...

Eric
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios