coherent hypertransport hardcodes.

[Stefan Reinauer]

* ron minnich <rminnich at lanl.gov> [030725 17:38]:
> I agree with you. This is arguably wrong, there should only be one cpu
> entry in the tree; it's on the "to fix" list. The code is pretty dumb
> right now, just emitting a tree for all devices. I'm just trying to figure
> out how "to fix" it, but have an idea. Most preferable would be to say
> just:
> 
> cpu k8 end
 
> and have it automagically bring in whatever else is needed. I think that 
> is the right thing. 
 
Ack.

> > The chain i want to describe looks pretty much like:
> > 
> >        K8-CPU[2] ------- K8-CPU[3]
> >           |                 |
> >           |                 |
> >        K8-CPU[0] ------- K8-CPU[1]
> >           |                 |
> >           |                 |
> >        8111-SB[0]        8131-SB[0]
> 
> cpu k8 
> 	register "cpuid" = "1"
> 	regiser  "southlink" = "amd8111-1"
> 	register "rightlink" = "k8-cpu3"
> end

> or some such? Would something like this do it?

Yes, then cpu and bridge configuration could be done really readable
like in this example of above scenario:

cpu cpu-k8-0
        register "cpuid"      = "0"
        register "arch"       = "k8" # if a special cpu type needs 
                                     # to add callbacks.

        register "acrosslink" = "cpu-k8-1"
        register "uplink"     = "cpu-k8-2"
        register "downlink"   = "bridge-8111-0"
end

cpu cpu-k8-1
        register "cpuid"      = "1"
        register "arch"       = "k8"

        register "acrosslink" = "cpu-k8-0"
        register "uplink"     = "cpu-k8-3"
        register "downlink"   = "bridge-8131-0"
end

cpu cpu-k8-2
        register "cpuid"      = "2"
        register "arch"       = "k8"

        register "acrosslink" = "cpu-k8-3"
        register "downlink"   = "cpu-k8-0"
end

cpu cpu-k8-3
        register "cpuid"      = "3"
        register "arch"       = "k8"

        register "acrosslink" = "cpu-k8-2"
        register "downlink"   = "cpu-k8-1"
end

bridge bridge-8111-0
        register "class"      = "southbridge"
        register "bridgeid"   = "0" # first 8111 sb on the bus

        register "vendor"     = "amd"
        register "deviceid"   = "amd8111"

        register "uplink"     = "cpu-k8-0"

        # special configuration like switching off
        # builtin nics could happen here.

end        

bridge bridge-8131-0 #
        register "class"      = "pcibridge" # currently 8131 code sits
                                            # in src/southbridge. It
                                            # could be either moved or
                                            # mapped.
        register "bridgeid"   = "0"         # first 8131 pci-x bridge
                                            # on the bus

        register "vendor"     = "amd"
        register "deviceid"   = "amd8131"

        register "uplink"     = "cpu-k8-1"
end        

> this is something we need to finish up. But yes, it's in the plan. We're 
> still trying to figure out what people most want.

> I hope it can last until week after next, I am gone most of next week, but 
> maybe we can convince Greg to put it in.

this would make the configuration scenario of AMD64 systems a lot more
flexible. Most of the hardcodes like link speed selection for the tyan
board could be made configurable in the motherboard configuration file
without really knowing anything but the board specification.

  Stefan


-- 
Architecture Team
    SuSE Linux AG