From naren_naren at hotmail.com  Tue Jun  3 08:55:01 2003
From: naren_naren at hotmail.com (Narendra PAtel)
Date: Tue Jun  3 08:55:01 2003
Subject: Does LinuxBios Supports National's SC1200 ?
Message-ID: <Law14-F34Lmqj5Nez1x0000fdc8@hotmail.com>

Hello group,

Can anybody please tell if the LinuxBios supports the National's SC1200 
Chipset?

And what if I have load WinCE using LinuxBios?

Thanks in Advance!

best regards,

Narendra Patel

_________________________________________________________________
Attention NRIs! Send money to India. 
http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp Do it in a 
jiffy!



From xpegenaute at telepolis.es  Tue Jun  3 12:37:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Jun  3 12:37:01 2003
Subject: Alternatives implementations f LinuxBios
Message-ID: <3EDCDC26.4030201@telepolis.es>

Hello,

i'd like to know where i can find information about alternative 
implementations of LinuxBios. At the moment i have:

- LinuxBios with Standard Flash
- LinuxBios with DoC
- LinuxBios with CF (i don't have info, yet)
- Some other ?

Regards.
Xavi.



From rminnich at lanl.gov  Tue Jun  3 17:55:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun  3 17:55:00 2003
Subject: Different BOF (LINUXBIOS BOF) (fwd)
Message-ID: <Pine.LNX.4.44.0306031557030.3894-100000@maxroach.lanl.gov>

linuxbios BOF at Usenix.

thanks

ron


---------- Forwarded message ----------
Date: Tue, 3 Jun 2003 14:42:11 -0700
From: Jennifer Desimone <jdesimone at usenix.org>
To: ron minnich <rminnich at lanl.gov>
Subject: Re: Different BOF (LINUXBIOS BOF)

>Hello Ron,
>
>Here is your USENIX '03 BoF confirmation:
>
>Wednesday, June 11
>Salon K
>9:00pm-10:00pm
>LinuxBIOS BoF
Ron Minnich, Los Alamos National Lab

>We can only provide you with an overhead projector and screen. If
>you'd like to arrange for additional audio-visual equipment at your
>BoF, please contact Al Hymer,  Marriott Rivercenter Event
>Technology Manager, via email at <al.hymer at marriott.com>.



Thanks,
Jennifer Desimone
Conference Assistant
USENIX Association
2560 Ninth Street
Suite 215
Berkeley, CA 94710
510.528.8649 x30
Fax 510.548.5738
jdesimone at usenix.org






>On Fri, 30 May 2003, ron minnich wrote:
>
>>  On Fri, 30 May 2003, Jennifer Desimone wrote:
>>
>>  > 1) What day would you like to schedule your BoF?
>
>
>wednesday
>
>1 hour
>
>>  > 3) What time would you like to begin your BoF?
>>
>
>9pm
>
>>  > 4) What is the title of your BoF?
>
>LinuxBIOS BOF
>
>>  > 5) What is the name & affiliation of the BoF presenter?
>>
>>  Ron Minnich
>>  Los Alamos National Lab
>>
>>  > 6) How many people do you think may attend?
>
>
>That's a tough one. It could be anywhere form 5 to 30
>
>thanks
>
>ron


-- 



From rogerxxmaillist at san.rr.com  Tue Jun  3 19:22:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Tue Jun  3 19:22:01 2003
Subject: Different BOF (LINUXBIOS BOF) (fwd)
In-Reply-To: <Pine.LNX.4.44.0306031557030.3894-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306031557030.3894-100000@maxroach.lanl.gov>
Message-ID: <1054682007.11986.29.camel@localhost3.localdomain>

uh? and I wasn't invited??  ..eh. i'd have to fly my chopper up there to
make it on time.

On Tue, 2003-06-03 at 14:57, ron minnich wrote:
> linuxbios BOF at Usenix.
> 
> thanks
> 
> ron
> 
> 
> ---------- Forwarded message ----------
> Date: Tue, 3 Jun 2003 14:42:11 -0700
> From: Jennifer Desimone <jdesimone at usenix.org>
> To: ron minnich <rminnich at lanl.gov>
> Subject: Re: Different BOF (LINUXBIOS BOF)
> 
> >Hello Ron,
> >
> >Here is your USENIX '03 BoF confirmation:
> >
> >Wednesday, June 11
> >Salon K
> >9:00pm-10:00pm
> >LinuxBIOS BoF
> Ron Minnich, Los Alamos National Lab
> 
> >We can only provide you with an overhead projector and screen. If
> >you'd like to arrange for additional audio-visual equipment at your
> >BoF, please contact Al Hymer,  Marriott Rivercenter Event
> >Technology Manager, via email at <al.hymer at marriott.com>.
> 
> 
> 
> Thanks,
> Jennifer Desimone
> Conference Assistant
> USENIX Association
> 2560 Ninth Street
> Suite 215
> Berkeley, CA 94710
> 510.528.8649 x30
> Fax 510.548.5738
> jdesimone at usenix.org
> 
> 
> 
> 
> 
> 
> >On Fri, 30 May 2003, ron minnich wrote:
> >
> >>  On Fri, 30 May 2003, Jennifer Desimone wrote:
> >>
> >>  > 1) What day would you like to schedule your BoF?
> >
> >
> >wednesday
> >
> >1 hour
> >
> >>  > 3) What time would you like to begin your BoF?
> >>
> >
> >9pm
> >
> >>  > 4) What is the title of your BoF?
> >
> >LinuxBIOS BOF
> >
> >>  > 5) What is the name & affiliation of the BoF presenter?
> >>
> >>  Ron Minnich
> >>  Los Alamos National Lab
> >>
> >>  > 6) How many people do you think may attend?
> >
> >
> >That's a tough one. It could be anywhere form 5 to 30
> >
> >thanks
> >
> >ron
-- 

Roger
http://www.eskimo.com/~roger/index.html



From NEWBELL7 at magicn.com  Tue Jun  3 22:54:00 2003
From: NEWBELL7 at magicn.com (NEWBELL7 at magicn.com)
Date: Tue Jun  3 22:54:00 2003
Subject: PS/2 irq problem...[EPIA]
Message-ID: <f5f5b01c32a44$fc8456e0$81cda8c0@magicn.net>

Hello!! 

Have  you seen any ps/2 problem on EPIA ?
If you have PS/2 mouse & keyboard at same time on EPIA, mouse moving
makes problem for ps/2 working. After that , keyboard also didn't work.

If you use gpm for mouse, both of mouse & keyboard didn't work. And If
you unload gpm, keyboard buffer data while using gpm  print on screen
suddenly.

Do you know this problem? 

If you have any idea, let me know. please.

Thank you.

regards,
newbie

-------------- next part --------------
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From ts1 at cma.co.jp  Wed Jun  4 01:20:01 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Wed Jun  4 01:20:01 2003
Subject: PS/2 irq problem...[EPIA]
In-Reply-To: <f5f5b01c32a44$fc8456e0$81cda8c0@magicn.net>
References: <f5f5b01c32a44$fc8456e0$81cda8c0@magicn.net>
Message-ID: <20030604052253.GA3593@cma.co.jp>

On Wed, Jun 04, 2003 at 11:57:07AM +0900, NEWBELL7 at magicn.com wrote:
> Have  you seen any ps/2 problem on EPIA ?
> If you have PS/2 mouse & keyboard at same time on EPIA, mouse moving
> makes problem for ps/2 working. After that , keyboard also didn't work.
> 
> If you use gpm for mouse, both of mouse & keyboard didn't work. And If
> you unload gpm, keyboard buffer data while using gpm  print on screen
> suddenly.

I have not seriously used PS/2 mouse on EPIA.
I'll look at it if I have time.

-- 
Takeshi


From naren_naren at hotmail.com  Wed Jun  4 06:41:01 2003
From: naren_naren at hotmail.com (Narendra PAtel)
Date: Wed Jun  4 06:41:01 2003
Subject: Request for Status update of LinuxBios for SC1200 chipset
Message-ID: <Law14-F95YI9IJsaJbq00035db8@hotmail.com>

Dear Christer,

After going  through the mar2002 freebios mailing list I read about your 
achievement of SC1200 board working with linuxbios!!! As you mentioned in 
that mail that you had not tested graphics and Audio.

Could you please update us with the present status of Linuxbios development 
for NSC's SCx2xx chipset?

Does that final working code or patch being uploaded or can the final 
working code be available to us for our application which is very similar to 
Dorado II platform(SC1200 based)?

Did you achieved booting WinCe using Linuxbios?
Linuxbios homepage has posted one news that Linuxbios can boot windows 
2000!!!! but the code is not yet posted.

Thanks and regards,
Narendra Patel.

_________________________________________________________________
Technical writer?. Earn more now! 
http://server1.msn.co.in/msnleads/tis/index.asp Find out how.



From s.sorrenti at regia.tv  Wed Jun  4 11:09:00 2003
From: s.sorrenti at regia.tv (Serafino Sorrenti)
Date: Wed Jun  4 11:09:00 2003
Subject: boot problem with compact flash
Message-ID: <200306041711.24440.s.sorrenti@regia.tv>

Command? Max cpuid index    : 1
Command? Vendor ID          : AuthenticAMD
Command? Processor Type     : 0x00
Command? Processor Family   : 0x06
>>>>> 
>>>>> Too many errors encountered; the rest of the message is ignored:
> Processor Model    : 0x08
> Processor Mask     : 0x00
> Processor Stepping : 0x00
> Feature flags      : 0x0183f9ff
> 
> 
> MTRR check
> Fixed MTRRs   : Enabled
> Variable MTRRs: Enabled
> 
> Disabling local apic...done.
> CPU #0 Initialized
> Allocating PCI resources...
> ASSIGN RESOURCES, bus 0
> PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] mem
> PCI: 00:00.1 10 <- [0x00002c90 - 0x00002c93] io
> PCI: 00:00.1 14 <- [0x00002ca0 - 0x00002ca3] io
> PCI: 00:00.1 18 <- [0x00002cb0 - 0x00002cb3] io
> PCI: 00:00.1 1c <- [0x00002cc0 - 0x00002cc3] io
> PCI: 00:00.1 20 <- [0x00002c80 - 0x00002c8f] io
> PCI: 00:01.1 10 <- [0x00002000 - 0x000020ff] io
> PCI: 00:01.1 14 <- [0xfc100000 - 0xfc100fff] mem
> PCI: 00:01.2 10 <- [0xfc101000 - 0xfc101fff] mem
> PCI: 00:01.3 10 <- [0xfc102000 - 0xfc102fff] mem
> PCI: 00:01.4 10 <- [0x00002400 - 0x000024ff] io
> PCI: 00:01.4 14 <- [0xfc103000 - 0xfc103fff] mem
> PCI: 00:01.6 10 <- [0x00002800 - 0x000028ff] io
> PCI: 00:01.6 14 <- [0x00002c00 - 0x00002c7f] io
> PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 ??????io
> PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 ??????prefmem
> PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 ??????mem
> ASSIGN RESOURCES, bus 1
> PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem
> PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem
> PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io
> Allocating VGA resource
> done.
> Enabling PCI resourcess...PCI: 00:00.0 cmd <- 07
> PCI: 00:00.1 cmd <- 01
> PCI: 00:01.0 cmd <- 0c
> PCI: 00:01.1 cmd <- 03
> PCI: 00:01.2 cmd <- 02
> PCI: 00:01.3 cmd <- 02
> PCI: 00:01.4 cmd <- 03
> PCI: 00:01.6 cmd <- 01
> PCI: 00:02.0 cmd <- 27PCI: 01:00.0 cmd <- 03
> done.
> Initializing PCI devices...
> PCI devices initialized
> Enabled in SIS 503 regs 0x40 and 0x45
> handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318
> handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318
> handle_superio: Pass 1, Superio SiS 950
> handle_superio  port 0x2e, defaultport 0x2e
> handle_superio  Using port 0x2e
> handle_superio Pass 1, done #0
> handle_superio done
> PCCHIPS M810LMR (and similar)...Entering the initregs process
> Southbridge fixup done for SIS 503
> handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318
> handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318
> handle_superio: Pass 2, Superio SiS 950
> handle_superio  port 0x2e, defaultport 0x2e
> handle_superio  Using port 0x2e
>   Call finishup
> handle_superio Pass 2, done #0
> handle_superio done
> Copying IRQ routing tables to 0xf0000...done.
> Wrote linuxbios table at: 00000500 - 0000066c  checksum bc14
> 
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.2
> 
>     37:init_bytes() - zkernel_start:0xfffc0000  zkernel_mask:0x0000ffff
> Found ELF candiate at offset 0
> New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789
> (cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 
0x8789
> Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: 
> 0x0000000000008789
> Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417
> Jumping to boot code
> ROM segment 0x0000 length 0x0000 reloc 0x0000
> Etherboot 5.0.6 (GPL) ELF for [SIS900]
> Boot from (N)etwork or from (L)ocal? clocks_per_tick = 941374
> N
> I am now initializing the ide system
> init_drive sectors_per_track = [32], num_heads = [16],num_cylinders=[984], 
> num_sectors = [503808]
> LBA mode supported
> 
> Boot: (hd0,0)/kernel
> rawread (post_loop) ide_read_sector failed
> File not found
> Probing...[SIS900]Found SIS900 ROM address 0x0000
> The PCI BIOS has not enabled this device!
> Updating PCI command 0003->0007. pci_bus 00 pci_device_fn 09
> Found SIS 85C503/5513 PCI to ISA bridge ROM address 0x0000
> 
> sis900_probe: MAC addr 00:0A:E6:4B:4A:AF at ioaddr 0X2000
> sis900_probe: Vendor:0X1039 Device:0X0900
> sis900_probe: No MII transceivers found!
> No adapter found
> <sleep>
> <abort>
> Boot from (N)etwork or from (L)ocal? N
> I am now initializing the ide system
> init_drive sectors_per_track = [32], num_heads = [16],num_cylinders=[984], 
> num_sectors = [503808]
> LBA mode supported
> 
> Boot: (hd0,0)/kernel
> File not found
> Probing...[SIS900]Found SIS900 ROM address 0x0000
> Found SIS 85C503/5513 PCI to ISA bridge ROM address 0x0000
> 
> sis900_probe: MAC addr 00:0A:E6:4B:4A:AF at ioaddr 0X2000
> sis900_probe: Vendor:0X1039 Device:0X0900
> sis900_probe: No MII transceivers found!
> No adapter found
> <sleep>
> <abort>
> Boot from (N)etwork or from (L)ocal? N
> I am now initializing the ide system
> init_drive sectors_per_track = [32], num_heads = [16],num_cylinders=[984], 
> num_sectors = [503808]
> LBA mode supported
> 
> Boot: (hd0,0)/kernel
> File not found
> Probing...[SIS900]Found SIS900 ROM address 0x0000
> Found SIS 85C503/5513 PCI to ISA bridge ROM address 0x0000
> 
> sis900_probe: MAC addr 00:0A:E6:4B:4A:A?
> 
> 
> 
> 
> 
> this is the error on boot in my serial console, but in the Compact flash the 
> file /kernel is here and don't have any problem.
> 
> Tnx Serafino



From xpegenaute at telepolis.es  Thu Jun  5 06:39:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Thu Jun  5 06:39:00 2003
Subject: GDT in entry16/32.inc
Message-ID: <3EDF2B05.9090707@telepolis.es>

Hello,

for curiosity is there any specific reason for put values in the first 
entry of GDT in the file src/cpu/i386/entry[16|32].inc ?.

The content of the first entry is:

.globl EXT(gdtptr)
gdt:
EXT(gdtptr):
    .word    gdt_end - gdt -1 /* compute the table limit */
    .long    gdt         /* we know the offset */
    .word    0

... etc ...

Xavi.
Regards.



From gwatson at lanl.gov  Thu Jun  5 13:10:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Thu Jun  5 13:10:00 2003
Subject: PPC
Message-ID: <p0521060cbb0529db0e8d@[10.0.1.2]>

Just thought you might like to know that I booted a linux kernel 
using linuxbios on a PPC yesterday. There are still a few issues to 
sort out, but it's looking very promising.

For those that are attending USENIX next week, I'll have the machine 
at the BOF so you can see it really works!

Cheers,

Greg


From yapeehuey at hotmail.com  Fri Jun  6 03:24:01 2003
From: yapeehuey at hotmail.com (Yap Ee Huey)
Date: Fri Jun  6 03:24:01 2003
Subject: tusl2-c with kernel
Message-ID: <BAY2-F40Cy7rjcxtniF00018135@hotmail.com>

Hi all,

After failing to load with both Etherboot and ADLO, I tried to reduce the 
size of
kernel to 192k bytes ( which can only boot and execute simple command )  to
fit into my 256k rom. But after "Jumping to boot code", it reboots. Does 
that mean
my ram initialization is buggy ? Thanks. Below is my log :

regards,
eehuey


Wrote linuxbios table at: 00000500 - 0000065c  checksum 2d0c
Jumping to linuxbiosmain()...


Welcome to start32, the open sourced starter.
This space will eventually hold more diagnostic information.
January 2000, James Hendricks, Dale Webster, and Ron Minnich.
Version 0.1

    37:init_bytes() - zkernel_start:0xfffc0000  zkernel_mask:0x0000ffff

Gunzip setup
gunzip_setup
output data is 0x00100000
Gunzipping boot code
flush 0x00100000 count 0x00008000
flush 0x00108000 count 0x00008000
flush 0x00110000 count 0x00008000
flush 0x00118000 count 0x00008000
flush 0x00120000 count 0x00008000
flush 0x00128000 count 0x00008000
flush 0x00130000 count 0x00008000
flush 0x00138000 count 0x00008000
flush 0x00140000 count 0x00008000
flush 0x00148000 count 0x00008000
flush 0x00150000 count 0x00008000
flush 0x00158000 count 0x00008000
flush 0x00160000 count 0x00000b30
<990>
command line - [root=/dev/hda5]
Jumping to boot code

LinuxBIOS-1.0.0 Fri Jun 6 20:09:28 EDT 2003 starting...
Ram1
Ram2
Ram3
Ram Enable 1
Ram Enable 2
Ram Enable 3
Ram Enable 4
Ram Enable 5
Ram4
Ram5
Ram6

Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.

_________________________________________________________________
Download the latest MSN Messenger http://messenger.msn.com.my



From aip at cwlinux.com  Fri Jun  6 03:46:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Fri Jun  6 03:46:01 2003
Subject: PPC
In-Reply-To: <p0521060cbb0529db0e8d@[10.0.1.2]>; from Greg Watson on Thu, Jun 05, 2003 at 11:12:43AM -0600
References: <p0521060cbb0529db0e8d@[10.0.1.2]>
Message-ID: <20030606154922.A2960@mail.cwlinux.com>

Hi Greg,

> Just thought you might like to know that I booted a linux kernel 
> using linuxbios on a PPC yesterday. There are still a few issues to 
> sort out, but it's looking very promising.
Sounds great.  I have a TX3927(MIPS) with me and would like to see
if it is possible to port LinuxBIOS on it.  Are all the PPC code in 
the cvs?

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Fri Jun  6 09:37:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun  6 09:37:01 2003
Subject: tusl2-c with kernel
In-Reply-To: <BAY2-F40Cy7rjcxtniF00018135@hotmail.com>
Message-ID: <Pine.LNX.4.44.0306060740060.32140-100000@maxroach.lanl.gov>

Have you just tried memtest first?

I am wondering if you do in fact have a dram problem.

ron



From rminnich at lanl.gov  Fri Jun  6 10:37:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun  6 10:37:00 2003
Subject: new config language
Message-ID: <Pine.LNX.4.44.0306060837350.32140-100000@maxroach.lanl.gov>

comments welcome. This doc is in the RFC section.

ron
		New config language for LinuxBIOS

\begin{abstract}
We describe the new configuration language for LinuxBIOS.
\end{abstract}

\section{Scope}
This document defines the new configuration language for LinuxBIOS.

\section{Goals}
The goals of the new language are these: 
\begin{itemize}
\item Simplified Makefiles so people can see what is set
\item Move from the regular-expression-based language to something
a bit more comprehensible and flexible
\item make the specification easier for people to use and understand
\item allow unique register-set-specifiers for each chip
\end{itemize}

\section{Language}
Here is the new language. It is very similar to the old one, differing
in only a few respects. It borrows heavily from Greg Watson's suggestions. 

I am presenting it in a pseudo-BNF in the hopes it will be easier. Things 
in '' are keywords; things in ``'' are strings in the actual text. 
\begin{verbatim}
#exprs are composed of factor or factor + factor etc.
expr ::= factor ( ``+'' factor | ``-'' factor | )*
#factors are term or term * term or term / term or ...
factor ::=  term ( ``*'' term | ``/'' term | ... )*
# 
unary-op ::= ``!'' ID
# term is a number, hexnumber, ID, unary-op, or a full-blown expression
term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)''

# Option command. Can be an expression or quote-string.
# Options are used in the config tool itself (in expressions and 'if')
# and are also passed to the C compiler when building linuxbios.
# It is an error to have two option commands in a file. 
# It is an error to have an option command after the ID has been used
#   in an expression (i.e. 'set after used' is an error)
option ::= 'option' ID '=' (``value'' | term)

# Default command. The ID is set to this value if no option command
# is scanned. 
# Multiple defaults for an ID will produce warning, but not errors. 
# It is OK to scan a default command after use of an ID.
# Options always over-ride defaults.
default ::= 'default' ID '=' (``value'' | term)

# the mainboard, southbridge, northbridge commands
# cause sourcing of Config.lb files as in the old config tool
# as parts are sourced, a device tree is built. The structure 
# of the tree is determined by the structure of the components
# as they are specified. To attach a superio to a southbridge, for
# example, one would do this:
# southbridge acer/5432 
#   superio NSC/123 
#   end 
# end
# the tool generates static initializers for this hierarchy.

# add C code to the current component (motherboard, etc. )
# to initialise the component-INDEPENDENT structure members
init ::= 'init' ``CODE''

# add C code to the current component (motherboard, etc. )
# to initialise the component-DEPENDENT structure members
register ::= 'register' ``CODE''


# mainboard command
# statements in this block will set variables controlling the mainboard,
# and will also place components (northbridge etc.) in the device tree
# under this mainboard
mainboard ::= 'mainboard' PATH (statements)* 'end'

# standard linuxbios commands
southbridge ::= 'southbridge' PATH (statemnts)* 'end'			
northbridge ::= 'northbridge' PATH (statemnts)* 'end'			
superio ::= 'superio PATH (statemnts)* 'end'			
cpu ::= 'cpu' PATH (statemnts)* 'end'			
arch ::= 'arch' PATH (statemnts)* 'end'			

# files for building linuxbios
# include a file in crt0.S 
mainboardinit ::= 'mainboardinit' PATH 

# object file 
object ::= 'object' PATH
# driver objects are just built into the image in a different way
driver ::= 'driver' PATH

# Use the Config.lb file in the PATH
dir ::= 'dir' PATH

# add a file to the set of ldscript files
ldscript ::= 'ldscript' PATH

# dependencies or actions for the makerule command
dep ::= 'dep' ``dependency-string''
act ::= 'act' ``actions''
depsacts ::= (dep | act)*
# set up a makerule
#
makerule ::= 'makerule' PATH depsacts

#defines for use in makefiles only
# note usable in the config tool, not passed to cc
makedefine ::= 'makedefine' ``RAWTEXT''

# add an action to an existing make rule
addaction ::= 'addaction' PATH ``ACTION''

# statements
statement ::= 
		  option
		| default
        	| cpu
        	| arch
		| northbridge
		| southbridge
		| superio
		| object
		| driver
		| mainboardinit
		| makerule
		| makedefine
		| addaction
		| init
		| register
		| iif
		| dir
		| ldscript

statements ::= (statement)*

# target directory specification
target ::= 'target' PATH

# and the whole thing
board ::= target (option)* mainboard

\end{verbatim}

A sample file:

\begin{verbatim}
target x

# over-ride the default rom size in the mainboard file
option ROM_SIZE=0x100000
mainboard amd/solo
end

\end{verbatim}

Sample mainboard file
\begin{verbatim}
#
###
### Set all of the defaults for an x86 architecture
###
arch i386 end
cpu k8 end
#
option DEBUG=1
default USE_FALLBACK_IMAGE=1
option A=(1+2)
option B=0xa
#
###
### Build our 16 bit and 32 bit linuxBIOS entry code
###
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript cpu/i386/entry16.lds
ldscript cpu/i386/entry32.lds
#
###
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE 
  mainboardinit cpu/i386/reset16.inc 
  ldscript cpu/i386/reset16.lds 
end

if USE_NORMAL_IMAGE
  mainboardinit cpu/i386/reset32.inc 
  ldscript cpu/i386/reset32.lds 
end
.
.
.
if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
#
###
### Romcc output
###
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
#mainboardinit ./failover.inc
makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
mainboardinit ./auto.inc
#
###
### Setup RAM
###
mainboardinit ram/ramtest.inc
mainboardinit southbridge/amd/amd8111/smbus.inc
mainboardinit sdram/generic_dump_spd.inc
#
###
### Include the secondary Configuration files 
###
northbridge amd/amdk8
end
southbridge amd/amd8111
end
#mainboardinit arch/i386/smp/secondary.inc
superio NSC/pc87360
	register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
end
dir /pc80
##dir /src/superio/winbond/w83627hf
cpu p5 end
cpu p6 end
cpu k7 end
cpu k8 end
#
###
### Build the objects we have code for in this directory.
###
##object mainboard.o
driver mainboard.o
object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
### Location of the DIMM EEPROMS on the SMBUS
### This is fixed into a narrow range by the DIMM package standard.
###
option SMBUS_MEM_DEVICE_START=(0xa << 3)
option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
option SMBUS_MEM_DEVICE_INC=1
#
### The linuxBIOS bootloader.
###
option PAYLOAD_SIZE            = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
#

\end{verbatim}

I've found the output of the new tool to be easier to
handle. Makefile.settings looks like this, for example:
\begin{verbatim}
TOP:=/home/rminnich/src/yapps2/freebios2
TARGET_DIR:=x
export MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
export ARCH:=i386
export _RAMBASE:=0x4000
export ROM_IMAGE_SIZE:=65535
export PAYLOAD_SIZE:=131073
export MAX_CPUS:=1
export HEAP_SIZE:=8192
export STACK_SIZE:=8192
export MEMORY_HOLE:=0
export LINUXBIOS_VERSION:=1.1.0
export CC:=$(CROSS_COMPILE)gcc

\end{verbatim}

In other words, instead of expressions, we see the values. It's easier to 
deal with. 








From gwatson at lanl.gov  Sat Jun  7 11:38:01 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Sat Jun  7 11:38:01 2003
Subject: PPC
In-Reply-To: <20030606154922.A2960@mail.cwlinux.com>
References: <p0521060cbb0529db0e8d@[10.0.1.2]>
 <20030606154922.A2960@mail.cwlinux.com>
Message-ID: <p05210606bb07b7e3d328@[10.0.1.2]>

Andrew,

Current version is checked in. I'll be making some changes to the 
startup code over the next few days though.

Cheers,

Greg

At 3:49 PM +0800 6/6/03, Andrew Ip wrote:
>Hi Greg,
>
>>  Just thought you might like to know that I booted a linux kernel
>>  using linuxbios on a PPC yesterday. There are still a few issues to
>>  sort out, but it's looking very promising.
>Sounds great.  I have a TX3927(MIPS) with me and would like to see
>if it is possible to port LinuxBIOS on it.  Are all the PPC code in
>the cvs?
>
>-Andrew
>
>--
>Andrew Ip
>Email:  aip at cwlinux.com
>Tel:    (852) 2542 2046
>Fax:    (852) 2542 2036
>Mobile: (852) 9201 9866
>
>Cwlinux Limited
>Unit 202B 2/F Lai Cheong Factory Building,
>479-479A Castle Peak Road,
>Lai Chi Kok, Kowloon,
>Hong Kong.
>
>Tel: (852)2542 2046
>Fax: (852)2542 2036
>
>For public pgp key, please obtain it from http://www.keyserver.net/en.



From rogerxxmaillist at san.rr.com  Sat Jun  7 19:43:00 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Sat Jun  7 19:43:00 2003
Subject: docprobe can't find DOC
Message-ID: <1055028750.16753.30.camel@localhost3.localdomain>

Ok. I've been bit-banging all day and cannot get docprobe to find the
DOC chips.

This board is a tyan tiger 1832DL 440BX (2x750P3).  I'm wonder if there
are any known issues with DOC's on the 440bx boards?  Or any known
issues with any of the lately issued DOC Millinium chips?


It looks as if docprobe is a) not recognizing the DOC or b) isn't
probing the correct address.  (i've fiddled with the high (etc) settings
for the driver in the kernel config too.)


I've gotten as far as this:

Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID 89 found at
0xc8000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID 31 found at
0xca000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xcc000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xce000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID 0C found at
0xd0000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID 66 found at
0xd2000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xd4000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xd6000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xd8000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xda000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xdc000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xde000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID 00 found at
0xe0000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID C2 found at
0xe2000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID 75 found at
0xe4000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID 6C found at
0xe6000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xe8000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xea000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xec000
Jun  7 16:17:16  Possible DiskOnChip with unknown ChipID FF found at
0xee000
Jun  7 16:17:16  No recognised DiskOnChip devices found

-- 

Roger
http://www.eskimo.com/~roger/index.html



From rminnich at lanl.gov  Sun Jun  8 00:08:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun  8 00:08:01 2003
Subject: docprobe can't find DOC
In-Reply-To: <1055028750.16753.30.camel@localhost3.localdomain>
Message-ID: <Pine.LNX.4.44.0306072211200.15667-100000@maxroach.lanl.gov>

On 7 Jun 2003, roger wrote:

> This board is a tyan tiger 1832DL 440BX (2x750P3).  I'm wonder if there
> are any known issues with DOC's on the 440bx boards?  Or any known
> issues with any of the lately issued DOC Millinium chips?

I hate to say it, but it may be the old "hidden write enable" problem, 
i.e. there is a special GPIO line used to control write enable in addition 
to the normal mechanism.

ron



From yapeehuey at hotmail.com  Sun Jun  8 04:31:01 2003
From: yapeehuey at hotmail.com (Yap Ee Huey)
Date: Sun Jun  8 04:31:01 2003
Subject: tusl2-c with kernel
Message-ID: <BAY2-F107jkIYA5kcDj00002075@hotmail.com>

Hi ,

Thansk for the reply. I have been following the list , I noticed that there 
are
two different things RAMTEST and MEMTEST in linuxbios. My linuxbios (on 
815ep)
passed the RAMTEST few weeks ago. Is there any HOWTO on MEMTEST ?

Thanks.

Regards,
eehuey


>From: ron minnich <rminnich at lanl.gov>
>To: Yap Ee Huey <yapeehuey at hotmail.com>
>CC: linuxbios at clustermatic.org
>Subject: Re: tusl2-c with kernel
>Date: Fri, 6 Jun 2003 07:40:24 -0600 (MDT)
>
>Have you just tried memtest first?
>
>I am wondering if you do in fact have a dram problem.
>
>ron
>

_________________________________________________________________
Download the latest MSN Messenger http://messenger.msn.com.my



From rogerxxmaillist at san.rr.com  Sun Jun  8 07:17:00 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Sun Jun  8 07:17:00 2003
Subject: docprobe can't find DOC
In-Reply-To: <Pine.LNX.4.44.0306072211200.15667-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306072211200.15667-100000@maxroach.lanl.gov>
Message-ID: <1055070384.16753.43.camel@localhost3.localdomain>

On Sat, 2003-06-07 at 21:11, ron minnich wrote:
> On 7 Jun 2003, roger wrote:
> 
> > This board is a tyan tiger 1832DL 440BX (2x750P3).  I'm wonder if there
> > are any known issues with DOC's on the 440bx boards?  Or any known
> > issues with any of the lately issued DOC Millinium chips?
> 
> I hate to say it, but it may be the old "hidden write enable" problem, 
> i.e. there is a special GPIO line used to control write enable in addition 
> to the normal mechanism.
> 
> ron

(geez. i hate that. when clicking "reply" in the email client, it sets
the return address to ron at blah.domain instead of using the linuxbios
mailling address! oh well.)

I've done quite a bit of research and see you make mention of this once
during a discussion (with no follow-ups).

Is this problem chip specific (issue with the DOC)?

A simple solution would be to aquire a Eeprom programmer (ie h/w to
connect via serial cable to program/flash/read eeproms?)

If this problem is relative to my tyan tiger 1832dl (440BX) motherboard,
I could probably utilize a 440GX(?) board that I also have as a
solution.

-- 

Roger
http://www.eskimo.com/~roger/index.html



From rogerxxmaillist at san.rr.com  Sun Jun  8 10:53:00 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Sun Jun  8 10:53:00 2003
Subject: Additions to list of injuries
Message-ID: <1055083315.15908.54.camel@localhost3.localdomain>

1)  2-3 index & thumb fingures sustained several stabbings and blood
lossage.

1)  1st degree burn.  Thumb mysteriously has the letters "WA"
imprinted.  Could this be evidence that i'm the one that burned a now
labeled "A**RD" bios chip?

wow. and the darn thing still boots. i wonder if these bios chips could
last a trip through the sun and still boot?

Amazing as to how many bendings these pins can handle and still not
break!

-- 

Roger
http://www.eskimo.com/~roger/index.html



From rogerxxmaillist at san.rr.com  Sun Jun  8 16:30:00 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Sun Jun  8 16:30:00 2003
Subject: timer.h - No such file or directory
Message-ID: <1055103590.10423.18.camel@localhost3.localdomain>

Using the smartcore-p5 tree:

gcc ... -o ide.o /home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c
/home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c:27:19: timer.h: No
such file or directory

I'm seeing a freebios/src/etherboot/timer.h &
freebios/src/arch/ppc/include/timer.h but nothing for the i386/


-- 

Roger
http://www.eskimo.com/~roger/index.html



From gwatson at lanl.gov  Sun Jun  8 17:01:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Sun Jun  8 17:01:00 2003
Subject: timer.h - No such file or directory
In-Reply-To: <1055103590.10423.18.camel@localhost3.localdomain>
References: <1055103590.10423.18.camel@localhost3.localdomain>
Message-ID: <p05210616bb0954b184cf@[10.0.1.2]>

Sorry, my fault. This a new version of ide.c (and .h) which I've 
backported from Etherboot 5.1.8.

You can just remove the #include. I'll check in the new version now.

Greg

At 1:19 PM -0700 8/6/03, roger wrote:
>Using the smartcore-p5 tree:
>
>gcc ... -o ide.o /home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c
>/home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c:27:19: timer.h: No
>such file or directory
>
>I'm seeing a freebios/src/etherboot/timer.h &
>freebios/src/arch/ppc/include/timer.h but nothing for the i386/
>
>
>--
>
>Roger
>http://www.eskimo.com/~roger/index.html
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From gwatson at lanl.gov  Sun Jun  8 17:30:01 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Sun Jun  8 17:30:01 2003
Subject: timer.h - No such file or directory
In-Reply-To: <p05210616bb0954b184cf@[10.0.1.2]>
References: <1055103590.10423.18.camel@localhost3.localdomain>
 <p05210616bb0954b184cf@[10.0.1.2]>
Message-ID: <p05210617bb095c063ca5@[10.0.1.2]>

Actually there was some other stuff that was PPC dependent. Hopefully 
the version I've just checked in isn't.

Greg

At 3:03 PM -0600 8/6/03, Greg Watson wrote:
>Sorry, my fault. This a new version of ide.c (and .h) which I've 
>backported from Etherboot 5.1.8.
>
>You can just remove the #include. I'll check in the new version now.
>
>Greg
>
>At 1:19 PM -0700 8/6/03, roger wrote:
>>Using the smartcore-p5 tree:
>>
>>gcc ... -o ide.o /home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c
>>/home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c:27:19: timer.h: No
>>such file or directory
>>
>>I'm seeing a freebios/src/etherboot/timer.h &
>>freebios/src/arch/ppc/include/timer.h but nothing for the i386/
>>
>>
>>--
>>
>>Roger
>>http://www.eskimo.com/~roger/index.html
>>
>>_______________________________________________
>>Linuxbios mailing list
>>Linuxbios at clustermatic.org
>>http://www.clustermatic.org/mailman/listinfo/linuxbios
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From rogerxxmaillist at san.rr.com  Sun Jun  8 20:17:00 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Sun Jun  8 20:17:00 2003
Subject: docprobe can't find DOC
In-Reply-To: <1055028750.16753.30.camel@localhost3.localdomain>
References: <1055028750.16753.30.camel@localhost3.localdomain>
Message-ID: <1055117189.10423.36.camel@localhost3.localdomain>

Ok. by a fluke accident, i've gotten the DOC recognized.

I'm on a 2x750P3 SMP Tyan Tiger 1832dl and induced a "kernel oops" on
cpu1 by trying to insmod ./bios.o
(http://www.openbios.info/download/index.html
devbios-0.3.2.tar.gz)

the docprobe.o is compiled with "Physical Address = 0" and no other
options for docprobe.o.  ... using doc2001.o

i've attached dmesg output below of the oops condition  when trying to
insmod bios.o and then after the kernel-oops occurred, modprobed
mtdcore, mtdchar,dos2001,dosprobe doc_config_location=0xfff00000. 
(unknown if the doc_config_location is needed...have yet to try without
as i've only duplicated 3 times.)


-- 

Roger
http://www.eskimo.com/~roger/index.html




Jun  8 14:05:36  No recognised DiskOnChip devices found
Jun  8 14:06:22  Using configured DiskOnChip probe address 0xfff00000
Jun  8 14:06:22  Possible DiskOnChip with unknown ChipID FF found at
0xfff00000
Jun  8 14:06:22  No recognised DiskOnChip devices found
Jun  8 14:07:18  BIOS driver v0.3.2 (writing disabled) for
2.4.20-gaming-r3
Jun  8 14:07:18  BIOS: host bridge is 8086, 7190, 0
Jun  8 14:07:18  BIOS: isa bridge is 8086, 7110, 38
Jun  8 14:07:18  BIOS: Probing PCI device with 64k rom
Jun  8 14:07:18  BIOS: Probing PCI device with 1024k rom
Jun  8 14:07:18  BIOS: Probing PCI device with 64k rom
Jun  8 14:07:18  BIOS: No flash devices found.
Jun  8 14:07:41  BIOS driver v0.3.2 (writing disabled) for
2.4.20-gaming-r3
Jun  8 14:07:41  BIOS: host bridge is 8086, 7190, 0
Jun  8 14:07:41  BIOS: isa bridge is 8086, 7110, 38
Jun  8 14:07:41  Unable to handle kernel NULL pointer dereference at
virtual address 00000000
Jun  8 14:07:41  printing eip:
Jun  8 14:07:41  fdc7245a
Jun  8 14:07:41  *pde = 00000000
Jun  8 14:07:41  Oops: 0000
Jun  8 14:07:41  bios agpgart nvidia parport_pc lp parport mousedev
sr_mod sd_mod sg emu10k1 sound soundcore ac97_codec scanner usb-storage
hid input usb-ohci uhci supermount eepro100 mii raid1 raid0 md ide-scsi
scsi_mod  
Jun  8 14:07:41  CPU:    1
Jun  8 14:07:41  EIP:    0010:[<fdc7245a>]    Tainted: P 
Jun  8 14:07:41  EFLAGS: 00010046
Jun  8 14:07:41  eax: 00000000   ebx: f70da000   ecx: 8000384c   edx:
00000000
Jun  8 14:07:41  esi: 00000000   edi: 00000292   ebp: 00000000   esp:
f70dbe80
Jun  8 14:07:41  ds: 0018   es: 0018   ss: 0018
Jun  8 14:07:41  Process insmod (pid: 2010, stackpage=f70db000)
Jun  8 14:07:41  Stack: fdc71ae1 00000000 00000000 fde84000 00201000
f74db280 00000000 f74db280 
Jun  8 14:07:41  000001f0 f74db2ec 00200000 ffe00000 ffffffff 00000000
c0118bc1 00200000 
Jun  8 14:07:41  00000001 00000000 c011f3e0 ffffffea 00000000 00000000
00000000 fdc71df8 
Jun  8 14:07:41  Call Trace: [<fdc71ae1>]  [<c0118bc1>]  [<c011f3e0>] 
[<fdc71df8>]  [<fdc719c0>]  [<fdc74140>]  [<fdc700b3>]  [<fdc74000>] 
[<fdc735ca>]  [<c0120634>]  [<fdc70060>]  [<fdc70060>]  [<c010787f>] 
Jun  8 14:07:41  Code: 0f b6 04 10 0f b6 c0 c3 8d b4 26 00 00 00 00 8d
bc 27 00 00 
Jun  8 14:07:47  <6>Using configured DiskOnChip probe address 0xfff00000
Jun  8 14:07:47  DiskOnChip Millennium found at address 0xFFF00000
Jun  8 14:07:47  Flash chip found: Manufacturer ID: 98, Chip ID: E6
(Toshiba TC58V64AFT/DC)
Jun  8 14:07:47  1 flash chips found. Total DiskOnChip size: 8 MiB
Jun  8 14:08:33  Using configured DiskOnChip probe address 0xfff00000
Jun  8 14:08:33  DiskOnChip Millennium found at address 0xFFF00000
Jun  8 14:08:33  Flash chip found: Manufacturer ID: 98, Chip ID: E6
(Toshiba TC58V64AFT/DC)
Jun  8 14:08:33  1 flash chips found. Total DiskOnChip size: 8 MiB
Jun  8 14:08:43  NFTL driver: nftlcore.c $Revision: 1.85 $, nftlmount.c
$Revision: 1.25 $
Jun  8 14:08:44  nftla: p1
Jun  8 14:08:44  devfs_register(disc): NULL ops, got fde8a810 from major
table
Jun  8 14:08:44  devfs_register(part1): NULL ops, got fde8a810 from
major table



From rogerxxmaillist at san.rr.com  Sun Jun  8 20:20:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Sun Jun  8 20:20:01 2003
Subject: timer.h - No such file or directory
In-Reply-To: <1055103590.10423.18.camel@localhost3.localdomain>
References: <1055103590.10423.18.camel@localhost3.localdomain>
Message-ID: <1055117361.10423.39.camel@localhost3.localdomain>

Also, smartcore-p3 tree also has this error.

I get another error later on in the compilation in both smartcore-p?
trees.  I'll follow up shortly with a new post with that error.


On Sun, 2003-06-08 at 13:19, roger wrote:
> Using the smartcore-p5 tree:
> 
> gcc ... -o ide.o /home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c
> /home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c:27:19: timer.h: No
> such file or directory
> 
> I'm seeing a freebios/src/etherboot/timer.h &
> freebios/src/arch/ppc/include/timer.h but nothing for the i386/
-- 

Roger
http://www.eskimo.com/~roger/index.html



From rminnich at lanl.gov  Sun Jun  8 20:44:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun  8 20:44:01 2003
Subject: timer.h - No such file or directory
In-Reply-To: <1055103590.10423.18.camel@localhost3.localdomain>
Message-ID: <Pine.LNX.4.44.0306081847280.4238-100000@maxroach.lanl.gov>

On 8 Jun 2003, roger wrote:

> /home/roger/src/linuxbios/freebios/src/pc80/ide/ide.c:27:19: timer.h: No
> such file or directory
> 
> I'm seeing a freebios/src/etherboot/timer.h &
> freebios/src/arch/ppc/include/timer.h but nothing for the i386/

ah, greg, more portability fun :-)

ron



From yapeehuey at hotmail.com  Sun Jun  8 23:13:01 2003
From: yapeehuey at hotmail.com (Yap Ee Huey)
Date: Sun Jun  8 23:13:01 2003
Subject: tusl2-c with kernel
Message-ID: <BAY2-F1567s9e74tbcC0000a14a@hotmail.com>

Hi,

I used RAMTEST=1 and memtest (from memtest86.com) as payload :
USE_ELF_BOOT=1
payload memtest
(default memtest is elf , correct ?)


RAMTEST output  :

Testing SDRAM : 00000000-0009ffff

SDRAM fill:

00000000
00010000
00020000
00030000
00040000
00050000
00060000
00070000
00080000
00090000
0009ffff

SDRAM verify:

00000000
00010000
00020000
00030000
00040000
00050000
00060000
00070000
00080000
00090000
0009ffff

Done.

MEMTEST loading :

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2
    37:init_bytes() - zkernel_start:0xfff00000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
header_offset is 0
Try to load at offset 0x0
New segment addr 0x10000 size 0x112b8 offset 0x1000 filesize 0x112b8
(cleaned up) New segment addr 0x10000 size 0x112b8 offset 0x1000 filesize 
0x112b8
Loading Segment: addr: 0x000000000ff6e5a8 memsz: 0x00000000000112b8 filesz: 
0x00000000000112b8
Jumping to boot code at 0x10000
entry    = 0x00010000
lb_start = 0x00004000
lb_size  = 0x0004ed2c
adjust   = 0x0ffad2d4
buffer   = 0x0ff625a8
     elf_boot_notes = 0x0000cb40
adjusted_boot_notes = 0x0ffb9e14

LinuxBIOS-1.0.0 Mon Jun 9 16:13:25 EDT 2003 starting...
(REBOOTED)


Looks like my elf boot always failed.
Any debug direction  ?
Thanks.

regards,
eehuey


>From: ron minnich <rminnich at lanl.gov>
>To: Yap Ee Huey <yapeehuey at hotmail.com>
>CC: linuxbios at clustermatic.org
>Subject: Re: tusl2-c with kernel
>Date: Fri, 6 Jun 2003 07:40:24 -0600 (MDT)
>
>Have you just tried memtest first?
>
>I am wondering if you do in fact have a dram problem.
>
>ron
>

_________________________________________________________________
Using a handphone prepaid card? Reload your credit online! 
http://www.msn.com.my/reloadredir/default.asp



From rminnich at lanl.gov  Sun Jun  8 23:22:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun  8 23:22:01 2003
Subject: tusl2-c with kernel
In-Reply-To: <BAY2-F1567s9e74tbcC0000a14a@hotmail.com>
Message-ID: <Pine.LNX.4.44.0306082125140.5209-100000@maxroach.lanl.gov>

make very sure that the memtest86 is running with no BIOS support enabled.

I think that is your problem. 

Also make sure it uses serial console ONLY, no vga.

ron




From rminnich at lanl.gov  Sun Jun  8 23:38:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun  8 23:38:00 2003
Subject: new config language.
In-Reply-To: <m3smqncmw2.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306082126050.5209-100000@maxroach.lanl.gov>

I'm opening up this discussion, which was formerly just between the folks 
actively doing freebios2. We're getting closer to having things working 
and I am happy to hear any comments. 

linuxbios.a now builds for the K8 with the new config tool. Not all of 
linuxbios, just linuxbios.a, but that's quite a way to working.

Things are stricter now. We've been able to operate before with code like 
this:

#if SOME_VARIABLE_THAT_WAS_UNDEFINED == 0
	stuff
#endif

because in the GNU C preprocessor, 
#if (a == 0)
and
#ifndef a

are equivalent if a is undefined. 

I think that is a very poor way to operate: it can fool people, and in a 
BIOS you want more checking. 

Now that you can use an 'if' operator in the config language, setting up 
some things is a lot easier:

For example, this:
expr ROM_SECTION_SIZE  =(USE_FALLBACK_IMAGE*65536)+(USE_NORMAL_IMAGE*(ROM_SIZE 
- 65536))

expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE
*0)


now becomes this:
default FALLBACK_SIZE=65536
if USE_FALLBACK_IMAGE 
  option ROM_SECTION_SIZE  = FALLBACK_SIZE
  option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
end
if USE_NORMAL_IMAGE
  option ROM_SECTION_SIZE  = (ROM_SIZE - FALLBACK_SIZE)
  option ROM_SECTION_OFFSET= 0
end

Much better. However, if you have not defined USE_FALLBACK_IMAGE or 
USE_NORMAL_IMAGE, then you're going to get an error, which in the past was 
not the case. 

So we'll have to learn to be a bit more careful about defining things 
before they are used, and not using things that were never defined. This 
is all proving to be easy, but people will need to take more care with the 
Config files (which, in deference to Windows and MacOS, are now named 
Config.lb). 

ron




From rogerxxmaillist at san.rr.com  Sun Jun  8 23:51:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Sun Jun  8 23:51:01 2003
Subject: After make, where is file "docipl"?
Message-ID: <1055130057.10424.84.camel@localhost3.localdomain>

ok. completed the make/compile for the smartcore-p5/ but yet there's no
file called "docipl".

I would assume by the prefix that this is meant for the DOC.. for which
i do have.

I'm following the Sis documentation as a guideline.  


>From what I'm seeing in the util/mtd/burn_mtd script, I only need to
create the images (with dd) and then dd the images to the DiskOnChip (on
this 440BX board).

-- 

Roger
http://www.eskimo.com/~roger/index.html



From rsmith at bitworks.com  Mon Jun  9 15:35:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Mon Jun  9 15:35:00 2003
Subject: ADLO/Bochs and PCI config write
In-Reply-To: <Pine.LNX.4.44.0306082126050.5209-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306082126050.5209-100000@maxroach.lanl.gov>
Message-ID: <3EE4E209.9060508@bitworks.com>

Anyone have any idea why writing to PCI config space while in the middle 
of the Bochs BIOS with ADLO is running would cause lockups?

Our board has 2 video chips on the PCI bus and for Xwindows to be able 
to use the head I have to init it from the bios.  X (even 4.3) has 
issues with our setup because there is only one copy of the video bios 
for both chips and I haven't been able to make X go look for the bios in 
the right location.  Plus I need the head to come up early for field 
service reasons.

The way we did this under our old COTS bios kit was

enable IO on head 1
call vga bios
disable io on head 1
enable io on head 2
call vga bios
disable io on head 2
enable IO on head 1

Then all is well with X.

I found the vido init part of ADLO/Bochs and ported the 
PCI_[WRITE:READ]_CONFIG_DWORD macro from linuxbios but when I call it 
the system hangs.  Currently I'm down to just re-writing the IO bit in 
the config register of the already active head and it still hangs.

Perhaps I don't have my device IDs correct?  Can someone verify that if 
I want to read and write to the PCI command register and lspci lists my 
2 video heads as 0:12.0 and 0:14.0 that the corresponding values I 
should load into eax before calling the macros are:

12.0	0x9010
14.0	0xa010

Other than that is there prehaps some freaky 16bit real mode issue thats 
busting me?

-- 
Richard A. Smith
rsmith at bitworks.com




From rsmith at bitworks.com  Mon Jun  9 16:26:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Mon Jun  9 16:26:01 2003
Subject: ADLO/Bochs and PCI config write
In-Reply-To: <3EE4E209.9060508@bitworks.com>
References: <Pine.LNX.4.44.0306082126050.5209-100000@maxroach.lanl.gov> <3EE4E209.9060508@bitworks.com>
Message-ID: <3EE4EDE3.5030109@bitworks.com>

Richard Smith wrote:

> Anyone have any idea why writing to PCI config space while in the middle 
> of the Bochs BIOS with ADLO is running would cause lockups?
> 

Ok.. Some new info.  Turns out it dosen't have anything to do with PCI 
config space at all.  Its position dependant.

I can duplicate my problem with a macro of all mov instructions.

Depending on how many instructions over 6  I add into the Bochs bios 
file (in the vga init section) it will either hang or tell me that an 
NMI has been called when it calls _print_bios_banner.

Any ideas?  It seems unlikely that the bochs stuff would be that fragile 
so I must be missing something.

-- 
Richard A. Smith
rsmith at bitworks.com




From bgr at gw.linespeed.net  Mon Jun  9 19:12:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Mon Jun  9 19:12:01 2003
Subject: linuxbios and bochs
Message-ID: <Pine.LNX.4.53.0306091808430.25337@gw.linespeed.net>

I'm booting linuxbios with a adlo/bochs payload on a VIA EPIA 800. I have
also disabled vga in bochs so thatit does not hang when vgabios is not
present.  Bochs will load about 10% of the time when rebooting the system.
The rest of the time it will hang.

I am quite certain that it is somewhere in bochs where the problem exists
since I can load etherboot from linuxbios without issue.  The times bochs
does load from linux generally hangs shortly after lilo loads the kernel.

What I am wondering is if anyone else has had this problem and come up
with a workaround, or knows the reason, or atleast where I should look
more closely.

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

POST: 0xf8
    37:init_bytes() - zkernel_start:0xfffc0000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x7c00 size 0x20400 offset 0x100 filesize 0x20400
(cleaned up) New segment addr 0x7c00 size 0x20400 offset 0x100 filesize
0x20400
Loading Segment: addr: 0x00000000077649d8 memsz: 0x0000000000020400
filesz: 0x00000
Jumping to boot code at 0x7c00
POST: 0xfe


Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191



From adam at cfar.umd.edu  Mon Jun  9 19:15:00 2003
From: adam at cfar.umd.edu (Adam Sulmicki)
Date: Mon Jun  9 19:15:00 2003
Subject: ADLO/Bochs and PCI config write
In-Reply-To: <3EE4EDE3.5030109@bitworks.com>
Message-ID: <20030609192106.V53482-100000@www.missl.cs.umd.edu>

On Mon, 9 Jun 2003, Richard Smith wrote:

> Any ideas?  It seems unlikely that the bochs stuff would be that fragile
> so I must be missing something.

It is :/

turn off some deubgging stuff. it helps keep code smaller.

I suspect it is b/c of those legacy bios entry points embedded into the
bios code. they have fixed address. Perhaps it is some problem with BCC.

-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers



From adam at cfar.umd.edu  Mon Jun  9 19:18:01 2003
From: adam at cfar.umd.edu (Adam Sulmicki)
Date: Mon Jun  9 19:18:01 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306091808430.25337@gw.linespeed.net>
Message-ID: <20030609192324.H53482-100000@www.missl.cs.umd.edu>

On Mon, 9 Jun 2003, Brian G. Rhodes wrote:

> I am quite certain that it is somewhere in bochs where the problem exists
> since I can load etherboot from linuxbios without issue.  The times bochs
> does load from linux generally hangs shortly after lilo loads the kernel.

I had this problem. This is why I explictly list which motherboards it
works with.

The only way I was able to fix i was to try differnet motherboard.

my personal theory is that it is problem with ram timing and that just
bios badly supported that motherboard. but it is just a guess. so your
guess is as good as mine.

-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers




From rminnich at lanl.gov  Mon Jun  9 19:39:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun  9 19:39:00 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306091808430.25337@gw.linespeed.net>
Message-ID: <Pine.LNX.4.44.0306091742300.13090-100000@maxroach.lanl.gov>

tell me more. 

Are you always booting from power-on or just reset? Hard or soft reset?

ron



From bgr at gw.linespeed.net  Mon Jun  9 20:35:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Mon Jun  9 20:35:01 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.44.0306091742300.13090-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306091742300.13090-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.53.0306091922070.26009@gw.linespeed.net>

Ron,

I'm always doing a hard reset.  When using linuxbios I am unable to do a
soft reset with this board.  The last POST code I get when it does happen
to work is 0x77 (from bochs) which is at the end of the keyboard init
code.  One thing I have not tried is using etherboot to load adlo/bochs
from the had disk, but I really do not think that the step before bochs is
the issue.


Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Mon, 9 Jun 2003, ron minnich wrote:

> tell me more.
>
> Are you always booting from power-on or just reset? Hard or soft reset?
>
> ron
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From rminnich at lanl.gov  Mon Jun  9 22:28:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun  9 22:28:00 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306091922070.26009@gw.linespeed.net>
Message-ID: <Pine.LNX.4.44.0306092031480.14278-100000@maxroach.lanl.gov>

next question, why are you using BOCHS? If it is only for VGA support then 
you might want to try the alternative.

ron



From hcyun at etri.re.kr  Mon Jun  9 22:34:01 2003
From: hcyun at etri.re.kr (hcyun at etri.re.kr)
Date: Mon Jun  9 22:34:01 2003
Subject: ADLO/Bochs and PCI config write
Message-ID: <8470181DABD5D511B3E700D0B7A8AC4A9CD76E@cms3>

> On Mon, 9 Jun 2003, Richard Smith wrote:
> 
> > Any ideas?  It seems unlikely that the bochs stuff would be 
> that fragile so I must be missing something.
> 
> It is :/
> 
> turn off some deubgging stuff. it helps keep code smaller.

Can you explain why turning off debugging macros can help?. 
I have problems when I enabled debug macros. It fail to run bochs bios. 
But If I turn off all debug macros, it boot normally. 


> 
> I suspect it is b/c of those legacy bios entry points 
> embedded into the
> bios code. they have fixed address. Perhaps it is some 
> problem with BCC.
> 
> -- 
> Adam Sulmicki
> http://www.eax.com 	The Supreme Headquarters of the 32 bit registers
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
-------------- next part --------------
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From adam at cfar.umd.edu  Mon Jun  9 22:49:01 2003
From: adam at cfar.umd.edu (Adam Sulmicki)
Date: Mon Jun  9 22:49:01 2003
Subject: ADLO/Bochs and PCI config write
In-Reply-To: <8470181DABD5D511B3E700D0B7A8AC4A9CD76E@cms3>
Message-ID: <20030609225112.X57509-100000@www.missl.cs.umd.edu>

> > > Any ideas?  It seems unlikely that the bochs stuff would be
> > that fragile so I must be missing something.
> >
> > It is :/
> >
> > turn off some deubgging stuff. it helps keep code smaller.

> Can you explain why turning off debugging macros can help?.
> I have problems when I enabled debug macros. It fail to run bochs bios.
> But If I turn off all debug macros, it boot normally.

I think there are two reasons for this.

One is that there are number of legacy entry points into bios. They are
pretty much "uniformly" scattered across the 64kb address space. Making
the available space non-contignous. (doing 'grep .org rombios.c' will show
you all those).

The second is that adding debugging information I think adds lots of more
static code to be compiled in. Both the text messages as well as the code
to the print them.

Thus i think the combined extra code with fact that the space is
noncontignous causes it to breaksomewhere. But that's just a guess It
might as well turn out to be something else. I did not investiage it too
closely.

-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers



From ts1 at tsn.or.jp  Mon Jun  9 22:56:01 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Mon Jun  9 22:56:01 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306091808430.25337@gw.linespeed.net>
References: <Pine.LNX.4.53.0306091808430.25337@gw.linespeed.net>
Message-ID: <20030610030023.GB29250@tsn.or.jp>

Hi Brian,
Your mail server refuses mail from Japan! So, to answer your question
in the personal mail, the debug level and gcc version problems happened
only when I was modifying the code, and there is no such problem with
curernt code, at least for me.

On Mon, Jun 09, 2003 at 06:15:56PM -0500, Brian G. Rhodes wrote:
> I'm booting linuxbios with a adlo/bochs payload on a VIA EPIA 800. I have
> also disabled vga in bochs so thatit does not hang when vgabios is not
> present.  Bochs will load about 10% of the time when rebooting the system.
> The rest of the time it will hang.

I think Andrew Ip has similar problem with his EPIA.

I think Bochs BIOS and VGA BIOS are running with cache on.
Try changing mem.basek value from 768 to 1024 in northbridge.c,
it will report 0xC0000-0xFFFFF area as no ram, so it will not cached.

Also, VGA BIOS from EPIA BIOS version 0109 is reported to NOT work.
If you have problem with VGA BIOS, try latest image.

--
Takeshi


From aip at cwlinux.com  Mon Jun  9 23:22:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jun  9 23:22:01 2003
Subject: linuxbios and bochs
In-Reply-To: <20030610030023.GB29250@tsn.or.jp>; from SONE Takeshi on Tue, Jun 10, 2003 at 12:00:23PM +0900
References: <Pine.LNX.4.53.0306091808430.25337@gw.linespeed.net> <20030610030023.GB29250@tsn.or.jp>
Message-ID: <20030610112529.A16631@mail.cwlinux.com>

> I think Andrew Ip has similar problem with his EPIA.
> I think Bochs BIOS and VGA BIOS are running with cache on.
> Try changing mem.basek value from 768 to 1024 in northbridge.c,
> it will report 0xC0000-0xFFFFF area as no ram, so it will not cached.
I have got it fix when enabling VIDEO_CONSOLE, IIRC.  As Ron said,
you probably don't need ADLO when you don't need video console.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rsmith at bitworks.com  Mon Jun  9 23:32:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Mon Jun  9 23:32:01 2003
Subject: [FIXED] ADLO/Bochs and PCI config 
In-Reply-To: <20030609225112.X57509-100000@www.missl.cs.umd.edu>
References: <20030609225112.X57509-100000@www.missl.cs.umd.edu>
Message-ID: <3EE551C7.7060402@bitworks.com>

Adam Sulmicki wrote:
>>>>Any ideas?  It seems unlikely that the bochs stuff would be
>>>
>>>that fragile so I must be missing something.
>>>
>>>It is :/
>>>

Yes you are correct.  It _is_ much more fragile than I thought.  The 
boot POST area is limited in size.  Looking through the code you will 
find many references to intxx_relocated because it was too big to fit in 
the boot POST area.

I solved my problem by relocating the expansion ROM BIOS routine and my 
PCI config code into another area of the bios and then calling them as 
subroutines.

I also had a problem with the way I was doing my PCI config reads and 
writes.  The term 'Register' in a PCI config space read/write actually 
means 'which block of 4 bytes'  So to access the command register (bytes 
4 and 5) I had to use 0x09004 rather than 0x09010 in eax.

I now have both heads up and going... X works fine now except that the 
mouse dosen't work so it seems I have some more IRQ work to sort out.

-- 
Richard A. Smith
rsmith at bitworks.com




From bgr at gw.linespeed.net  Tue Jun 10 00:28:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Tue Jun 10 00:28:01 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.44.0306092031480.14278-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306092031480.14278-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.53.0306092331020.26009@gw.linespeed.net>

I am using BOCHS because I need to be able to load an initrd, and it
looked like the most straight forward way of doing so.  Is there another
way to accomplish that?

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Mon, 9 Jun 2003, ron minnich wrote:

> next question, why are you using BOCHS? If it is only for VGA support then
> you might want to try the alternative.
>
> ron
>


From YhLu at tyan.com  Tue Jun 10 00:53:00 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Jun 10 00:53:00 2003
Subject: =?GB2312?B?tPC4tDogbmV3IGNvbmZpZyBsYW5ndWFnZS4=?=
Message-ID: <3174569B9743D511922F00A0C943142302C43617@TYANWEB>

Ron,

How about the status of freebios2 support on K8?

Today I use to the code and try on Tyan s2880 found two problem
1. I use RH as host compiler system. payload make statement in make.base
with perl doesn't work, it produce strange size images near One mega byte.
2. I change that back to dd, and make one 512K romimage, But the code only
can execute to "jumping to LinuxBIOS". And then retry several times. I use
debug card and see the post code is 01--> 08--> 11 ->01...>11 -> 12. end.

Do you know the progress of Suse LinuxBIOS support on opteron?

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?6?8? 20:41
???: linuxbios at clustermatic.org
??: new config language.


I'm opening up this discussion, which was formerly just between the folks 
actively doing freebios2. We're getting closer to having things working 
and I am happy to hear any comments. 

linuxbios.a now builds for the K8 with the new config tool. Not all of 
linuxbios, just linuxbios.a, but that's quite a way to working.

Things are stricter now. We've been able to operate before with code like 
this:

#if SOME_VARIABLE_THAT_WAS_UNDEFINED == 0
	stuff
#endif

because in the GNU C preprocessor, 
#if (a == 0)
and
#ifndef a

are equivalent if a is undefined. 

I think that is a very poor way to operate: it can fool people, and in a 
BIOS you want more checking. 

Now that you can use an 'if' operator in the config language, setting up 
some things is a lot easier:

For example, this:
expr ROM_SECTION_SIZE
=(USE_FALLBACK_IMAGE*65536)+(USE_NORMAL_IMAGE*(ROM_SIZE 
- 65536))

expr
ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE
*0)


now becomes this:
default FALLBACK_SIZE=65536
if USE_FALLBACK_IMAGE 
  option ROM_SECTION_SIZE  = FALLBACK_SIZE
  option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
end
if USE_NORMAL_IMAGE
  option ROM_SECTION_SIZE  = (ROM_SIZE - FALLBACK_SIZE)
  option ROM_SECTION_OFFSET= 0
end

Much better. However, if you have not defined USE_FALLBACK_IMAGE or 
USE_NORMAL_IMAGE, then you're going to get an error, which in the past was 
not the case. 

So we'll have to learn to be a bit more careful about defining things 
before they are used, and not using things that were never defined. This 
is all proving to be easy, but people will need to take more care with the 
Config files (which, in deference to Windows and MacOS, are now named 
Config.lb). 

ron


_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From rminnich at lanl.gov  Tue Jun 10 00:57:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 10 00:57:01 2003
Subject: =?GB2312?B?tPC4tDogbmV3IGNvbmZpZyBsYW5ndWFnZS4=?=
In-Reply-To: <3174569B9743D511922F00A0C943142302C43617@TYANWEB>
Message-ID: <Pine.LNX.4.44.0306092258580.15036-100000@maxroach.lanl.gov>

On Mon, 9 Jun 2003, YhLu wrote:

> How about the status of freebios2 support on K8?

we're working on it. 

There are 3 big efforts going on. First, Eric is working on romcc for K8 
so that it works well. Suse is trying to get it to boot. I am working on a 
new config language which I hope is rich enough to capture the needs of 
freebios2.

Where are we? We are all collectively close. But we're not done.

ron



From YhLu at tyan.com  Tue Jun 10 01:05:01 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Jun 10 01:05:01 2003
Subject: =?GB2312?B?tPC4tDogtPC4tDogbmV3IGNvbmZpZyBsYW5ndWFnZS4=?=
Message-ID: <3174569B9743D511922F00A0C943142302C43618@TYANWEB>

Ron,

Is there any MB can boot to execute into LinuxBIOS after copying it to RAM?

The _RAMBASE WE use for E7501 is 0x8000, and the FreeBIOS2 default for K8 is
0x4000. How should I set the value to make the LinuxBIOS can boot into
hardwaremain.c.
It seems MB only execute the auto.c and crt0.base and can not jump to the
right address.

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?6?9? 22:01
???: YhLu
??: linuxbios at clustermatic.org
??: Re: ??: new config language.

On Mon, 9 Jun 2003, YhLu wrote:

> How about the status of freebios2 support on K8?

we're working on it. 

There are 3 big efforts going on. First, Eric is working on romcc for K8 
so that it works well. Suse is trying to get it to boot. I am working on a 
new config language which I hope is rich enough to capture the needs of 
freebios2.

Where are we? We are all collectively close. But we're not done.

ron


From rminnich at lanl.gov  Tue Jun 10 01:13:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 10 01:13:00 2003
Subject: =?GB2312?B?tPC4tDogtPC4tDogbmV3IGNvbmZpZyBsYW5ndWFnZS4=?=
In-Reply-To: <3174569B9743D511922F00A0C943142302C43618@TYANWEB>
Message-ID: <Pine.LNX.4.44.0306092311370.15036-100000@maxroach.lanl.gov>

On Mon, 9 Jun 2003, YhLu wrote:

> Is there any MB can boot to execute into LinuxBIOS after copying it to
> RAM?

yes, many.

> 
> The _RAMBASE WE use for E7501 is 0x8000, and the FreeBIOS2 default for K8 is
> 0x4000. How should I set the value to make the LinuxBIOS can boot into
> hardwaremain.c.
> It seems MB only execute the auto.c and crt0.base and can not jump to the
> right address.

I'm not sure what's wrong here. You may have to start checking the object 
code to see if it is correct.

For what it is worth the new config tool is almost working ... just trying 
to get the sizing of the romimage correct.

Hopefully I can start paying attention to linuxbios itself soon, now that 
I can bulid it.

ron



From ebiederman at lnxi.com  Tue Jun 10 01:25:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 10 01:25:00 2003
Subject: =?gb2312?b?tPC4tA==?=: new config language.
In-Reply-To: <Pine.LNX.4.44.0306092258580.15036-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306092258580.15036-100000@maxroach.lanl.gov>
Message-ID: <m3of165wm1.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On Mon, 9 Jun 2003, YhLu wrote:
> 
> > How about the status of freebios2 support on K8?
> 
> we're working on it. 
> 
> There are 3 big efforts going on. First, Eric is working on romcc for K8 
> so that it works well. Suse is trying to get it to boot. I am working on a 
> new config language which I hope is rich enough to capture the needs of 
> freebios2.

Just to clarify it boots and works with the apics disabled.
 
> Where are we? We are all collectively close. But we're not done.

Yep that sounds like a good summary.

Eric



From ts1 at cma.co.jp  Tue Jun 10 01:31:01 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Tue Jun 10 01:31:01 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306092331020.26009@gw.linespeed.net>
References: <Pine.LNX.4.44.0306092031480.14278-100000@maxroach.lanl.gov> <Pine.LNX.4.53.0306092331020.26009@gw.linespeed.net>
Message-ID: <20030610053451.GA2104@cma.co.jp>

On Mon, Jun 09, 2003 at 11:31:47PM -0500, Brian G. Rhodes wrote:
> I am using BOCHS because I need to be able to load an initrd, and it
> looked like the most straight forward way of doing so.  Is there another
> way to accomplish that?

"--initrd" option to mkelfImage adds initrd to ELF boot image, which
can be loaded by Etherboot or BOOT_IDE of LinuxBIOS.


--
Takeshi


From ebiederman at lnxi.com  Tue Jun 10 01:32:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 10 01:32:00 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306092331020.26009@gw.linespeed.net>
References: <Pine.LNX.4.44.0306092031480.14278-100000@maxroach.lanl.gov>
	<Pine.LNX.4.53.0306092331020.26009@gw.linespeed.net>
Message-ID: <m3fzmi5w9x.fsf@maxwell.lnxi.com>

"Brian G. Rhodes" <bgr at gw.linespeed.net> writes:

> I am using BOCHS because I need to be able to load an initrd, and it
> looked like the most straight forward way of doing so.  Is there another
> way to accomplish that?

mkelfImage handles initrds just fine.

Eric



From ebiederman at lnxi.com  Tue Jun 10 01:32:02 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 10 01:32:02 2003
Subject: =?gb2312?b?tPC4tA==?=: =?gb2312?b?tPC4tA==?=: new config
  language.
In-Reply-To: <3174569B9743D511922F00A0C943142302C43618@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43618@TYANWEB>
Message-ID: <m3k7bu5waj.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Ron,
> 
> Is there any MB can boot to execute into LinuxBIOS after copying it to RAM?
> 
> The _RAMBASE WE use for E7501 is 0x8000, and the FreeBIOS2 default for K8 is
> 0x4000. How should I set the value to make the LinuxBIOS can boot into
> hardwaremain.c.
> It seems MB only execute the auto.c and crt0.base and can not jump to the
> right address.

???????????????

I think there is a fundamental disconnect here.  Except when
I miscompile auto.c the AMD reference board boots fine.  And in this
aspect the code is fundamentally the same as earlier revision of
LinuxBIOS.  auto.c just gets compiles into auto.inc

And I can't think of a board where I have had problems with jumping
to hardwaremain.  _RAMBASE should not strongly affect anything, it
just need to be in a location where the ram initialization code
always puts ram.  Only with respect to stack size, and the LinuxBIOS
tables should it have any issues with various locations in ram.

Eric



From YhLu at tyan.com  Tue Jun 10 02:27:01 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Jun 10 02:27:01 2003
Subject: =?GB2312?B?tPC4tDogtPC4tDogtPC4tDogbmV3IGNvbmZpZyBsYW5ndWFnZS4=?=
Message-ID: <3174569B9743D511922F00A0C943142302C4361B@TYANWEB>

I changeg the stack size from 0x2000 to 0x10000, and the result is that it
retrys more times.

I have got 1.5G memory installed and I found the code in ramtest only hard
code that to 512M, is cause the problem?

LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting...
Bootstrap cpu
setting up coherent ht domain....
done.
PCI: 00:01.00
PCI: 00:01.01
PCI: 00:02.00
PCI: 00:02.01
PCI: 00:03.00
PCI: 00:04.00
PCI: 00:04.01
PCI: 00:04.02
PCI: 00:04.03
PCI: 00:04.05
PCI: 00:04.06
PCI: 00:18.00
PCI: 00:18.01
PCI: 00:18.02
PCI: 00:18.03
SMBus controller enabled
Ram1
setting up CPU0 northbridge registers
done.
Ram2
Ram3
dcl: 080c8000
Initializing memory:  done
Ram4
Ram5
Ram6
dimm: 50
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

dimm: 5080
dimm: 5180
dimm: 5280
dimm: 5380
DRAM fill: 00000000-00001000
00001000
DRAM filled
DRAM verify: 00000000-00001000
00001000
DRAM verified
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.


LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting...


LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting...
Bootstrap cpu
CPU INIT Detected.
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.


LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting...


LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting...
Bootstrap cpu
CPU INIT Detected.
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.



So I would find one AMD to verify the code.

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?6?9? 22:36
???: YhLu
??: ron minnich; linuxbios at clustermatic.org
??: Re: ??: ??: new config language.

YhLu <YhLu at tyan.com> writes:

> Ron,
> 
> Is there any MB can boot to execute into LinuxBIOS after copying it to
RAM?
> 
> The _RAMBASE WE use for E7501 is 0x8000, and the FreeBIOS2 default for K8
is
> 0x4000. How should I set the value to make the LinuxBIOS can boot into
> hardwaremain.c.
> It seems MB only execute the auto.c and crt0.base and can not jump to the
> right address.

???????????????

I think there is a fundamental disconnect here.  Except when
I miscompile auto.c the AMD reference board boots fine.  And in this
aspect the code is fundamentally the same as earlier revision of
LinuxBIOS.  auto.c just gets compiles into auto.inc

And I can't think of a board where I have had problems with jumping
to hardwaremain.  _RAMBASE should not strongly affect anything, it
just need to be in a location where the ram initialization code
always puts ram.  Only with respect to stack size, and the LinuxBIOS
tables should it have any issues with various locations in ram.

Eric

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From bgr at gw.linespeed.net  Tue Jun 10 09:48:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Tue Jun 10 09:48:01 2003
Subject: linuxbios and bochs
In-Reply-To: <20030610053451.GA2104@cma.co.jp>
References: <Pine.LNX.4.44.0306092031480.14278-100000@maxroach.lanl.gov>
 <Pine.LNX.4.53.0306092331020.26009@gw.linespeed.net> <20030610053451.GA2104@cma.co.jp>
Message-ID: <Pine.LNX.4.53.0306100838540.2525@gw.linespeed.net>

SONE,

I had not been able to find any documentation on BOOT_IDE, so I tried
using Eric's mkelfImage with etherboot and the ide_disk loader.  The only
problem I have there is it requires me to leave an empty chunk of disk at
the beginning of the drive to place the elf kernel+initrd image.  That
doesn't inherently cause the problem, but the fact that I can't just leave
an empty space at the beginning, but rather have to create an
unformatted partition does.

It requires changing both the initrd, any software which uses devices
directly, and the installer.  Using an elf loader and a kernel+initrd
image is a suitable fallback position, but something which is more of a
drop in replacement on the eeprom is still a goal for me.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Tue, 10 Jun 2003, SONE Takeshi wrote:

> On Mon, Jun 09, 2003 at 11:31:47PM -0500, Brian G. Rhodes wrote:
> > I am using BOCHS because I need to be able to load an initrd, and it
> > looked like the most straight forward way of doing so.  Is there another
> > way to accomplish that?
>
> "--initrd" option to mkelfImage adds initrd to ELF boot image, which
> can be loaded by Etherboot or BOOT_IDE of LinuxBIOS.
>
>
> --
> Takeshi
>


From rminnich at lanl.gov  Tue Jun 10 10:59:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 10 10:59:01 2003
Subject: linuxbios and bochs
In-Reply-To: <20030610053451.GA2104@cma.co.jp>
Message-ID: <Pine.LNX.4.44.0306100902320.19248-100000@maxroach.lanl.gov>

On Tue, 10 Jun 2003, SONE Takeshi wrote:

> "--initrd" option to mkelfImage adds initrd to ELF boot image, which
> can be loaded by Etherboot or BOOT_IDE of LinuxBIOS.

yes, I forgot to mention that with the new 1 MB 82802ac parts, I can put 
linuxbios, kernel and initrd directly into FLASH.

ron



From bgr at gw.linespeed.net  Tue Jun 10 11:07:00 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Tue Jun 10 11:07:00 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.44.0306100902320.19248-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306100902320.19248-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.53.0306101007110.3681@gw.linespeed.net>

Ron,

Those are intel flash parts correct?  My initrd is 1.3MB right now.  I'm
not using it for libraries. I am using it to set up the root filesystem.

It mounts hda1 which has a tarball containing the fs for the root fs.
extracts that to a ramdisk, switches teh root device, and exits.  I would
love to boot the kernel from flash, but it's not to be.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Tue, 10 Jun 2003, ron minnich wrote:

> On Tue, 10 Jun 2003, SONE Takeshi wrote:
>
> > "--initrd" option to mkelfImage adds initrd to ELF boot image, which
> > can be loaded by Etherboot or BOOT_IDE of LinuxBIOS.
>
> yes, I forgot to mention that with the new 1 MB 82802ac parts, I can put
> linuxbios, kernel and initrd directly into FLASH.
>
> ron
>


From rminnich at lanl.gov  Tue Jun 10 11:11:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 10 11:11:01 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306101007110.3681@gw.linespeed.net>
Message-ID: <Pine.LNX.4.44.0306100914050.19248-100000@maxroach.lanl.gov>

On Tue, 10 Jun 2003, Brian G. Rhodes wrote:

> Those are intel flash parts correct?  My initrd is 1.3MB right now.  I'm
> not using it for libraries. I am using it to set up the root filesystem.

yes, you are too big. Is there an problem with kernel in flash, which 
mounts hda1 and does all those things you mentioned?

Why is that initrd so big?

ron



From bgr at gw.linespeed.net  Tue Jun 10 11:45:00 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Tue Jun 10 11:45:00 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.44.0306100914050.19248-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306100914050.19248-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.53.0306101035130.4028@gw.linespeed.net>

The initrd is 3MB uncompressed.  I require a few utilities (bash, echo,
mount, tar, and umount).

When the system boots and loads the initrd, it mounts hda1 which contains
a root tarball.  It then extracts the tar into the ramdisk.  So it
requires a few system libraries. c, ld, dl, rt (tar), termcap, pthread.

I think what I am going to do is just use linuxbios + etherboot to boot an
elf image from the ide disk, and move the partitions down.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Tue, 10 Jun 2003, ron minnich wrote:

> On Tue, 10 Jun 2003, Brian G. Rhodes wrote:
>
> > Those are intel flash parts correct?  My initrd is 1.3MB right now.  I'm
> > not using it for libraries. I am using it to set up the root filesystem.
>
> yes, you are too big. Is there an problem with kernel in flash, which
> mounts hda1 and does all those things you mentioned?
>
> Why is that initrd so big?
>
> ron
>


From rminnich at lanl.gov  Tue Jun 10 11:49:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 10 11:49:01 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306101035130.4028@gw.linespeed.net>
Message-ID: <Pine.LNX.4.44.0306100952010.19248-100000@maxroach.lanl.gov>

On Tue, 10 Jun 2003, Brian G. Rhodes wrote:

> I think what I am going to do is just use linuxbios + etherboot to boot an
> elf image from the ide disk, and move the partitions down.

you can do that, but another option is to have linuxbios+linux kexec an 
elf image from the disk. This allows you to (e.g.) put the elf image on an 
ext3 partition, for example. 

ron



From aip at cwlinux.com  Tue Jun 10 12:04:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jun 10 12:04:00 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306101035130.4028@gw.linespeed.net>; from Brian G. Rhodes on Tue, Jun 10, 2003 at 10:49:02AM -0500
References: <Pine.LNX.4.44.0306100914050.19248-100000@maxroach.lanl.gov> <Pine.LNX.4.53.0306101035130.4028@gw.linespeed.net>
Message-ID: <20030611000751.A25333@mail.cwlinux.com>

Hi Brian,

> The initrd is 3MB uncompressed.  I require a few utilities (bash, echo,
> mount, tar, and umount).
Have you tried busybox and uclibc?  You can safe quite alot storage area.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From stepan at suse.de  Tue Jun 10 12:06:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Jun 10 12:06:00 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.53.0306101035130.4028@gw.linespeed.net>
References: <Pine.LNX.4.44.0306100914050.19248-100000@maxroach.lanl.gov> <Pine.LNX.4.53.0306101035130.4028@gw.linespeed.net>
Message-ID: <20030610161002.GB8587@suse.de>

* Brian G. Rhodes <bgr at gw.linespeed.net> [030610 17:49]:
> The initrd is 3MB uncompressed.  I require a few utilities (bash, echo,
> mount, tar, and umount).

Some of the stuff is probably implemented in busybox, which is a lot
smaller than bash, mount, umount,... 
Also, using dietlibc or uclibc might give you quite a win. Static
binaries compiled with those are often smaller than dynamic glibc
binaries.
 
Best regards,
  Stefan Reinauer
  
-- 
Architecture Team
    SuSE Linux AG


From ebiederman at lnxi.com  Tue Jun 10 21:06:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 10 21:06:01 2003
Subject: romcc progress.
Message-ID: <m3wuftto66.fsf@maxwell.lnxi.com>

I have just implemented inline assembly 
and a better allocator in romcc.

It will now use sse and mmx registers when you give
it the appropriate -mcpu= option.  I am not happy with
the command line options but fixing them is easy.

In addition the quality of the register allocations has improved
to the point that it looks quite a bit like it was done by
hand.  There are limits but there are fewer stupid things happening.

The inline assembly is syntactically the same as gcc's.  But
it is not 100% compatible with gcc.  The goal is to be as compatible
with gcc as gcc is compatible with gcc between ports.  In practice
this means that romcc supports a subset of what gcc does on x86, with
respect to constraints. 

On inline assembly versus builtin operations.  A compiler has a lot
more potential to optimize code in a builtin so I will continue to
implement builtins.  Support wise inline assembly with parameters is a
pain to initially implement but there really is not a support burden
after that.  And there are some operations where there is not gain
making them a builtin.

The code is now checked into the freebios2 tree.  And I can get back
to exercising romcc by writing code with it.

Eric



From rogerxxmaillist at san.rr.com  Wed Jun 11 01:02:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Wed Jun 11 01:02:01 2003
Subject: doc ipl image
Message-ID: <1055307163.31819.6.camel@localhost3.localdomain>

ok. wew. searched, read, reboots (did this in a loop for 10x's).

i've gotten p5 images built and have been able to recognize and write to
the DoC (many thanx to a kernel oops w/ devbios project and it's
apperant incompatability with apm).


After erasing the DoC, I'm realizing that I need an ipl image burned
prior to burning linuxbios.image & linuxkernel.image images to the rom.

Ipl is needed to boot linuxbios.
Linuxbios is needed to boot linuxkernel.
(And so on...)

I see that the ipl.asm is provided only by m-sys on a NDA.  

(btw, using an Intel 440bx chipset here). 
-- 

Roger
http://www.eskimo.com/~roger/index.html



From rogerxxmaillist at san.rr.com  Wed Jun 11 01:36:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Wed Jun 11 01:36:01 2003
Subject: doc ipl image
In-Reply-To: <1055307163.31819.6.camel@localhost3.localdomain>
References: <1055307163.31819.6.camel@localhost3.localdomain>
Message-ID: <1055309179.28330.14.camel@localhost3.localdomain>

Just a quick follow-up.  I noticed that I had to add the following line
in the config file:

docipl /pathto/ipl.S

ok. now for ipl.S  (for a 440BX chipset?)

-- 

Roger
http://www.eskimo.com/~roger/index.html



From agnew at cs.umd.edu  Wed Jun 11 02:24:01 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Wed Jun 11 02:24:01 2003
Subject: linuxbios and bochs
In-Reply-To: <Pine.LNX.4.44.0306100952010.19248-100000@maxroach.lanl.gov>
Message-ID: <20030611022748.I63736-100000@www.missl.cs.umd.edu>

>
> > I think what I am going to do is just use linuxbios + etherboot to boot an
> > elf image from the ide disk, and move the partitions down.

You can also use the etherboot 5.0.6 ide patch solution, which contains
file system support (ext2, ext3, and vfat) so you don't have to move your
partitions. I store it at http://www.missl.cs.umd.edu/~agnew/


------------------
Adam Agnew
Independent Contractor
www.adamagnew.com



From rogerxxmaillist at san.rr.com  Wed Jun 11 03:00:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Wed Jun 11 03:00:01 2003
Subject: doc ipl image
In-Reply-To: <1055309050.28330.10.camel@localhost3.localdomain>
References: <1055307163.31819.6.camel@localhost3.localdomain>
	 <1055309050.28330.10.camel@localhost3.localdomain>
Message-ID: <1055314263.31819.26.camel@localhost3.localdomain>

ok.

docipl /path/to/src/mainboard/asus/cua/ipl.S

and Python configure made the Makefiles, however dd fails with a
negative number with "docipl" in the config file.

So i'm doing this seperately and copying the created dociple to another
folder and then re-running the configure/make without the "docipl"
option to build the linuxbios.image and linuxkernel.image images.

I'm rebuilding the kernel again for the DoC (looks like it might be wise
to build mtd/mtdchar/doc2001 modules into the kernel) and am working on
a serial console for remote console.

So far, i've gotten nothing to boot.  Just the same scenario as a box
without a bios chip.  Although, I could have sworn i had some additional
hdd activity on the last attempt.

One additional question, if HAVE_FRAMEBUFFER=0, there still is console
activity on the monitor right?  (-i think i'm interpretting this
correctly-).

wew!  ain't google grand?!?  one can actually have a one-way conversion
with himself via email!!!


On Tue, 2003-06-10 at 22:24, roger wrote:
> Just a quick follow-up.  I noticed that I had to add the following line
> in the config file:
> 
> docipl /pathto/ipl.S
> 
> ok. now for ipl.S  (for a 440BX chipset?)
-- 

Roger
http://www.eskimo.com/~roger/index.html



From ebiederman at lnxi.com  Wed Jun 11 03:12:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 11 03:12:01 2003
Subject: doc ipl image
In-Reply-To: <1055314263.31819.26.camel@localhost3.localdomain>
References: <1055307163.31819.6.camel@localhost3.localdomain>
	<1055309050.28330.10.camel@localhost3.localdomain>
	<1055314263.31819.26.camel@localhost3.localdomain>
Message-ID: <m3he6xozic.fsf@maxwell.lnxi.com>

roger <rogerxxmaillist at san.rr.com> writes:

> ok.
> 
> docipl /path/to/src/mainboard/asus/cua/ipl.S

But note that is for a sis630 chipset.

ipl.S must enable memory or there is no room to put LinuxBIOS,
and enabling memory is 512 bytes is a very challenging problem.

You can probably manage it if you are just hard coding the
necessary steps for one brand of memory.  Being more general
than that on a 440BX I suspect will be quite difficult..

Eric



From rminnich at lanl.gov  Wed Jun 11 09:57:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 11 09:57:00 2003
Subject: doc ipl image
In-Reply-To: <1055314263.31819.26.camel@localhost3.localdomain>
Message-ID: <Pine.LNX.4.44.0306110800390.28225-100000@maxroach.lanl.gov>

On 10 Jun 2003, roger wrote:

> One additional question, if HAVE_FRAMEBUFFER=0, there still is console
> activity on the monitor right?  (-i think i'm interpretting this
> correctly-).

depends on the type of mainboard. Mostly, no.

ron



From rminnich at lanl.gov  Wed Jun 11 10:01:41 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 11 10:01:41 2003
Subject: doc ipl image
In-Reply-To: <m3he6xozic.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306110801120.28225-100000@maxroach.lanl.gov>

On 11 Jun 2003, Eric W. Biederman wrote:

> > docipl /path/to/src/mainboard/asus/cua/ipl.S
> 
> But note that is for a sis630 chipset.

no, that is our asus cua support.

But, yes, ipl for a 440bx is going to REALLY be hard.


kron



From rsmith at bitworks.com  Wed Jun 11 14:32:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Wed Jun 11 14:32:00 2003
Subject: doc ipl image
In-Reply-To: <Pine.LNX.4.44.0306110801120.28225-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306110801120.28225-100000@maxroach.lanl.gov>
Message-ID: <3EE77662.2010502@bitworks.com>

ron minnich wrote:

> 
> no, that is our asus cua support.
> 
> But, yes, ipl for a 440bx is going to REALLY be hard.
> 

If he needs to read the spd to get the DIMM settings I'd guess its not 
going to happen.

There's 512 bytes of code just in all the necesary PCI_CONFIG_WRITE 
macros alone much less reading the spd.

-- 
Richard A. Smith
rsmith at bitworks.com




From bgr at gw.linespeed.net  Wed Jun 11 15:55:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Wed Jun 11 15:55:01 2003
Subject: linuxbios and bochs
In-Reply-To: <20030611000751.A25333@mail.cwlinux.com>
References: <Pine.LNX.4.44.0306100914050.19248-100000@maxroach.lanl.gov>
 <Pine.LNX.4.53.0306101035130.4028@gw.linespeed.net> <20030611000751.A25333@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.53.0306111411480.22683@gw.linespeed.net>

Andrew,

I settled on linuxbios with etherboot and Adam Agnew's polled ide patch
for etherboot using mkelfImage to create the ELF binary with the kernel
and initrd.

Here is the code I added to handle PCI bridge cards in newpci.c in
pci_assign_irqs

          else
	    {
	      u16 x;

	      pci_read_config_word(pdev, PCI_CLASS_DEVICE, &x);
	      if (x == PCI_CLASS_BRIDGE_PCI)
		{

		  printk_debug("PCI device is a bridge\n");
		  // cross bridge
		  if (pdev->children)
		    {
		      struct pci_dev *cdev;
		      printk_debug("PCI devices behind bridge. Bus %d\n",
pdev->secondary);

		      cdev = pdev->children;
		      while (cdev)
			{
			  pci_assign_irqs(pdev->secondary,
PCI_SLOT(cdev->devfn), pIntAtoD);
			  cdev = cdev->next;
			}
		    }
		}
	    }

And included pci_ids.h...

I am still not getting interrupts on any cards I put in the PCI slot on
the EPIA.

Bus  0, device  20, function  0:
    PCI bridge: Hint Corp HB1-SE33 PCI-PCI Bridge (rev 20).
      Master Capable.  Latency=64.
  Bus  2, device   0, function  0:
    Multimedia controller: Sigma Designs, Inc. EM840x REALmagic DVD/MPEG-2
Audio/V.
      IRQ 5.
      Master Capable.  Latency=64.
      Non-prefetchable 32 bit memory at 0xfe700000 [0xfe7fffff].
  Bus  2, device   4, function  0:
    Multimedia controller: Sigma Designs, Inc. EM840x REALmagic DVD/MPEG-2
Audio/V.
      IRQ 5.
      Master Capable.  Latency=64.
      Non-prefetchable 32 bit memory at 0xfe800000 [0xfe8fffff].
  Bus  2, device   8, function  0:
    Multimedia controller: Sigma Designs, Inc. EM840x REALmagic DVD/MPEG-2
Audio/V.
      IRQ 5.
      Master Capable.  Latency=64.
      Non-prefetchable 32 bit memory at 0xfe900000 [0xfe9fffff].
  Bus  2, device  12, function  0:
    Multimedia controller: Sigma Designs, Inc. EM840x REALmagic DVD/MPEG-2
Audio/V.
      IRQ 5.
      Master Capable.  Latency=64.
      Non-prefetchable 32 bit memory at 0xfea00000 [0xfeafffff].

cat /proc/interrupts
           CPU0
  0:      38836          XT-PIC  timer
  1:          2          XT-PIC  keyboard
  2:          0          XT-PIC  cascade
  4:       8370          XT-PIC  serial
  5:          0          XT-PIC  Harmony, Harmony, Harmony, Harmony
 11:        216          XT-PIC  eth0
 14:        944          XT-PIC  ide0
 15:         15          XT-PIC  ide1
NMI:          0
ERR:          0


Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Wed, 11 Jun 2003, Andrew Ip wrote:

> Hi Brian,
>
> > The initrd is 3MB uncompressed.  I require a few utilities (bash, echo,
> > mount, tar, and umount).
> Have you tried busybox and uclibc?  You can safe quite alot storage area.
>
> -Andrew
>
> --
> Andrew Ip
> Email:  aip at cwlinux.com
> Tel:    (852) 2542 2046
> Fax:    (852) 2542 2036
> Mobile: (852) 9201 9866
>
> Cwlinux Limited
> Unit 202B 2/F Lai Cheong Factory Building,
> 479-479A Castle Peak Road,
> Lai Chi Kok, Kowloon,
> Hong Kong.
>
> Tel: (852)2542 2046
> Fax: (852)2542 2036
>
> For public pgp key, please obtain it from http://www.keyserver.net/en.
>


From john-at-thinman at nyc.rr.com  Wed Jun 11 21:31:00 2003
From: john-at-thinman at nyc.rr.com (John van Vlaanderen)
Date: Wed Jun 11 21:31:00 2003
Subject: config language
In-Reply-To: <E19IV7g-0004hr-00@the-beast.sychron.com>
References: <E19IV7g-0004hr-00@the-beast.sychron.com>
Message-ID: <1055381734.4221.11.camel@localhost.localdomain>

Hi, 
Years before XML, In perl, I developed a kind of complex structure to
store user state information at the NY Stock Exchange for if/when the
systems went down all the users could be restored to what they were
doing beforehand.

Later I wrote a dataserver which accepts something like a URL string
with a serialized data structure on the end of it, freezes it to disk
and the returns an sub or super set of that structure in serialized
form.  I think created a way to put code in it as text, and now I have
promised myself that I will actually embed code in them someday.

XML came along and showed how inefficiently this could be done.  I think
the parsing complexity is becasue it is a markup language and has
attributes and stuff that are comical by normal language standards.

I went to a lisp meeting last night, and suddenly realized I had been
using lisp to teach perl to kids...  now I wish there was a C-Lisp-AN.

I think perl structures are about as readable as a config can get,
though there is a slight learning curve.  I am also wondering how
Perl6's Parrot VM can be integrated into LinuxBIOS.

Here is a quick tutorial for perl with structures that I wrote,
http://thinman.com/perl_primer/

John

 
On Wed, 2003-05-21 at 11:03, prl-linuxbios at sychron.com wrote:
> > This is functionality we need in the LinuxBIOS table especially
> > for devices that cannot be detected by the OS.  Like temperature
> > sensors.  This should be easy to add in the 1.1 development tree.
> > 
> > This is information we cannot transmit via DHCP.  A DHCP packet
> > is to small.  In DHCP we just need enough information to bootstrap.
> 
> I was not suggesting that the tables must of necessity all be munged
> into a DHCP packet, though I observe that with a reasonable encoding,
> most descriptions probably *would* fit in a single DHCP options field of
> 312 bytes. In practise I agree that one would use only those parts which
> were relevant to (network) booting in a real DHCP packet.
> 
> But... reading through the recent discussions about XML, it took me some
> time to release that people were talking about parsing IN LinuxBIOS, as
> opposed using XML as an input file to a build or config process. XML or
> similar in LinuxBIOS itself seems like overkill to me.
> 
> Please consider using DHCP encapsulated option format as an internal
> format for LinuxBIOS in the first instance, even if DHCP (the protocol)
> is not used. I see several reasons...
> 
> - Compatibility with the DHCP protocol
> 
> OK, I understand that not everything wants to use DHCP for network
> configuration, but even the most ardent boot-from-the-bare-metal
> embedded fan must appreciate that many do use DHCP, even if only for
> testing code via DHCP / TFTP before a final product is burned in.
> 
> Or, put another way, why would you make a *point* of being different?
> 
> - Code exists
> 
> DHCP option parsing code exists in Etherboot (so Etherboot-on-LinuxBIOS
> users have it anyway). As I say, a hardware description has been
> discussed (and I *think* implemented) in Etherboot in the particular
> case of PCI nics.
> 
> - Compact parser and encoding
> 
> DHCP hardware descriptions (i.e. individual chipsets) should be encoded
> numerically. There are reasons why existing DHCP options and SNMP MIBs
> do it this way - 32 bits encodes a HELL of a lot of possible hardware
> types in only 4 bytes. Doubtless someone will tell me that DHCP isn't
> the most efficient method or that they have a *really* neat parser for
> their favourite format. Big deal - refer to "Code exists".
> 
> - Do the hard stuff outside LinuxBIOS
> 
> Register the encodings centrally held table (like other DHCP options or
> an SNMP MIB), so that when building, tables can be built as appropriate
> from XML definitions. A DHCP server or a small amount of perl in the
> build process can translate raw numbers to and from human readable form
> using boilerplate derived from the central table. Where possible (e.g.
> PCI IDs), use an existing registry anyway.
> 
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios




From rminnich at lanl.gov  Thu Jun 12 00:35:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 12 00:35:01 2003
Subject: config language
In-Reply-To: <1055381734.4221.11.camel@localhost.localdomain>
Message-ID: <Pine.LNX.4.44.0306112238230.1258-100000@maxroach.lanl.gov>

thanks, we have (for now) settled on a python-based ELL parser generator. 
There is a bit more error handling in python than perl objects, which I 
like.

But thanks for the info.

ron



From ts1 at cma.co.jp  Thu Jun 12 01:00:01 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Thu Jun 12 01:00:01 2003
Subject: ELF boot and Multiboot
Message-ID: <20030612050407.GA4220@cma.co.jp>

Eric,
In the source of mkelfImage, linux-i386/convert_params.c,
there is some code to retrieve information like memory map
from Multiboot information structure.
However, ELF images created by mkelfImage does not have
Multiboot header, according to 'mbchk' of GRUB boot loader.
In what situation is this code supposed to run (and tested)?
If one added a (trivial) Multiboot header in the head.S,
the resulting kernel could be loaded from GRUB, while it could also
be loaded by ELF boot of LinuxBIOS and Etherboot?
-- 
Takeshi


From fedorowp at earthlink.net  Thu Jun 12 01:14:00 2003
From: fedorowp at earthlink.net (Peter Fedorow)
Date: Thu Jun 12 01:14:00 2003
Subject: High-End Desktop Support
Message-ID: <3EE80CD8.8090509@earthlink.net>

I hope this is an appropriate question to ask here.

Does LinuxBIOS support any of the current high-end desktop chipsets?  I 
checked the LinuxBIOS status page, but I didn't see any matches.

I'm looking for a fully supported motherboard that can accept at least a 
2 GHz Pentium 4 or AMD Athlon.

Peter



From ebiederman at lnxi.com  Thu Jun 12 01:15:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Jun 12 01:15:00 2003
Subject: ELF boot and Multiboot
In-Reply-To: <20030612050407.GA4220@cma.co.jp>
References: <20030612050407.GA4220@cma.co.jp>
Message-ID: <m3vfvbvpm0.fsf@maxwell.lnxi.com>

SONE Takeshi <ts1 at cma.co.jp> writes:

> Eric,
> In the source of mkelfImage, linux-i386/convert_params.c,
> there is some code to retrieve information like memory map
> from Multiboot information structure.
> However, ELF images created by mkelfImage does not have
> Multiboot header, according to 'mbchk' of GRUB boot loader.
> In what situation is this code supposed to run (and tested)?

The partial multiboot support in etherboot, is where it was used.

> If one added a (trivial) Multiboot header in the head.S,
> the resulting kernel could be loaded from GRUB, while it could also
> be loaded by ELF boot of LinuxBIOS and Etherboot?

It probably could.  And I would not have a problem with something
like that in theory.  The multiboot spec is quite poorly done,
so I am not a major fan.  I think I would prefer to just add a
dummy elf segment at the start of the file with that information
in it.  From mkelfImage 2.5 that would probably be the easiest thing
to do.

I would almost rather fix GRUB to use something sensible and portable
like ELF notes.  The multiboot data structure is  a disaster in terms
of both future expansion, and of expansion by multiple groups.

What I will not support is GRUB hack at dynamic linking, via the
multiboot spec.  With respect to a.out the multiboot stuff was not
bad.  With respect to ELF there are much better ways to do just about
everything it attempts.

My apologies for ranting.  GRUB is not a bootloader I admire.

Eric



From rminnich at lanl.gov  Thu Jun 12 11:32:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 12 11:32:00 2003
Subject: High-End Desktop Support
In-Reply-To: <3EE80CD8.8090509@earthlink.net>
Message-ID: <Pine.LNX.4.44.0306120936290.5602-100000@maxroach.lanl.gov>

On Thu, 12 Jun 2003, Peter Fedorow wrote:

> I'm looking for a fully supported motherboard that can accept at least a 
> 2 GHz Pentium 4 or AMD Athlon.

intel e7500, 7501, etc. are supported.

ron



From bgr at gw.linespeed.net  Thu Jun 12 12:21:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Thu Jun 12 12:21:01 2003
Subject: EPIA PCI slot
Message-ID: <Pine.LNX.4.53.0306121121350.2827@gw.linespeed.net>

The reason I was not getting interrupts on devices in the pci slot on the
EPIA is because they were not set to be bus masters, so they would never
generate interrupts.  A quick write to the command register fixed the
problem.  Command register is being set to 0x02.  It should be set to
0x06.  a 6 to 4.

I haven't looked to see if this is pervasive throughout linuxbios, or if
for other boards this is handled specifically, but it is a bug.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191



From aip at cwlinux.com  Thu Jun 12 12:48:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Thu Jun 12 12:48:01 2003
Subject: EPIA PCI slot
In-Reply-To: <Pine.LNX.4.53.0306121121350.2827@gw.linespeed.net>; from Brian G. Rhodes on Thu, Jun 12, 2003 at 11:25:53AM -0500
References: <Pine.LNX.4.53.0306121121350.2827@gw.linespeed.net>
Message-ID: <20030613005218.A22923@mail.cwlinux.com>

Hi Brian,

> The reason I was not getting interrupts on devices in the pci slot on the
> EPIA is because they were not set to be bus masters, so they would never
> generate interrupts.  A quick write to the command register fixed the
> problem.  Command register is being set to 0x02.  It should be set to
> 0x06.  a 6 to 4.
Thanks for the catch.  IIRC, I did have extra ethernet card working before.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Thu Jun 12 14:31:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 12 14:31:01 2003
Subject: EPIA PCI slot
In-Reply-To: <Pine.LNX.4.53.0306121121350.2827@gw.linespeed.net>
Message-ID: <Pine.LNX.4.44.0306121235040.6719-100000@maxroach.lanl.gov>

On Thu, 12 Jun 2003, Brian G. Rhodes wrote:

> I haven't looked to see if this is pervasive throughout linuxbios, or if
> for other boards this is handled specifically, but it is a bug.


This is not a bug. Linuxbios should never bus master PCI devices; that is 
for the OS to do. 

ron



From rminnich at lanl.gov  Thu Jun 12 14:34:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 12 14:34:01 2003
Subject: EPIA PCI slot
In-Reply-To: <20030613005218.A22923@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.44.0306121238060.6719-100000@maxroach.lanl.gov>

On Fri, 13 Jun 2003, Andrew Ip wrote:

> > The reason I was not getting interrupts on devices in the pci slot on the
> > EPIA is because they were not set to be bus masters, so they would never
> > generate interrupts.  A quick write to the command register fixed the
> > problem.  Command register is being set to 0x02.  It should be set to
> > 0x06.  a 6 to 4.
> Thanks for the catch.  IIRC, I did have extra ethernet card working before.

PLEASE do not patch linuxbios to enable this.

thanks

ron



From bgr at gw.linespeed.net  Thu Jun 12 14:39:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Thu Jun 12 14:39:01 2003
Subject: EPIA PCI slot
In-Reply-To: <Pine.LNX.4.44.0306121235040.6719-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306121235040.6719-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.53.0306121339210.5445@gw.linespeed.net>

Ron,

Other BIOS do.  Or if you look at it this way...

02:0c.0 Multimedia controller: Sigma Designs, Inc.: Unknown device 8400
(rev 01)
00: 05 11 00 84 06 00 10 02 01 00 80 04 00 20 00 00
10: 00 00 30 e3 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 7a 16 e3 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0c 01 00 00


Is correct.


02:0c.0 Multimedia controller: Sigma Designs, Inc.: Unknown device 8400
(rev 01)
00: 05 11 00 84 02 00 10 02 01 00 80 04 00 40 00 00
10: 00 00 a0 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 7a 16 e3 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0c 01 00 00

Is not correct.


The first is award BIOS, the second is linuxbios.


Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Thu, 12 Jun 2003, ron minnich wrote:

> On Thu, 12 Jun 2003, Brian G. Rhodes wrote:
>
> > I haven't looked to see if this is pervasive throughout linuxbios, or if
> > for other boards this is handled specifically, but it is a bug.
>
>
> This is not a bug. Linuxbios should never bus master PCI devices; that is
> for the OS to do.
>
> ron
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From bgr at gw.linespeed.net  Thu Jun 12 14:53:00 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Thu Jun 12 14:53:00 2003
Subject: EPIA PCI slot
In-Reply-To: <Pine.LNX.4.44.0306121238060.6719-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306121238060.6719-100000@maxroach.lanl.gov>
Message-ID: <Pine.LNX.4.53.0306121351310.5625@gw.linespeed.net>

Ron,

I was always under the impression that the BIOS should enable a device
(bus master) always.  And slaves would not be able to be set.  Some
devices set a capability which you can read this from to know whether the
device should be a master or not.

Why, or where, should the OS do it?  Driver?

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Thu, 12 Jun 2003, ron minnich wrote:

> On Fri, 13 Jun 2003, Andrew Ip wrote:
>
> > > The reason I was not getting interrupts on devices in the pci slot on the
> > > EPIA is because they were not set to be bus masters, so they would never
> > > generate interrupts.  A quick write to the command register fixed the
> > > problem.  Command register is being set to 0x02.  It should be set to
> > > 0x06.  a 6 to 4.
> > Thanks for the catch.  IIRC, I did have extra ethernet card working before.
>
> PLEASE do not patch linuxbios to enable this.
>
> thanks
>
> ron
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From rminnich at lanl.gov  Thu Jun 12 15:11:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 12 15:11:01 2003
Subject: EPIA PCI slot
In-Reply-To: <Pine.LNX.4.53.0306121339210.5445@gw.linespeed.net>
Message-ID: <Pine.LNX.4.44.0306121314140.7006-100000@maxroach.lanl.gov>

On Thu, 12 Jun 2003, Brian G. Rhodes wrote:

> Other BIOS do.  Or if you look at it this way...

It is true that (some) other BIOSes do this. But many do not. 

There is danger in enabling this bit in the bios, which is why we don't do 
it. 

We have this discussion about once a year, but the last 3 times we have 
decided not to set the bit.

ron



From rminnich at lanl.gov  Thu Jun 12 15:15:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 12 15:15:01 2003
Subject: EPIA PCI slot
In-Reply-To: <Pine.LNX.4.53.0306121351310.5625@gw.linespeed.net>
Message-ID: <Pine.LNX.4.44.0306121318010.7006-100000@maxroach.lanl.gov>

On Thu, 12 Jun 2003, Brian G. Rhodes wrote:

> Why, or where, should the OS do it?  Driver?

the os driver should do it, I think.

Many linux drivers do it, e.g.:


        if (pci_flags & PCI_USES_MASTER)
                pci_set_master (pdev);


see drivers/net/*.c

ron



From ebiederman at lnxi.com  Thu Jun 12 15:18:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Jun 12 15:18:01 2003
Subject: EPIA PCI slot
In-Reply-To: <Pine.LNX.4.53.0306121351310.5625@gw.linespeed.net>
References: <Pine.LNX.4.44.0306121238060.6719-100000@maxroach.lanl.gov>
	<Pine.LNX.4.53.0306121351310.5625@gw.linespeed.net>
Message-ID: <m3d6hj2j9g.fsf@maxwell.lnxi.com>

"Brian G. Rhodes" <bgr at gw.linespeed.net> writes:

> Ron,
> 
> I was always under the impression that the BIOS should enable a device
> (bus master) always.  And slaves would not be able to be set. 

Nope.  The BIOS only needs to do this for devices needed to boot.

>  Some
> devices set a capability which you can read this from to know whether the
> device should be a master or not.
> 
> Why, or where, should the OS do it?  Driver?

Yes, in the driver.  Under linux this is the pci_set_master call.

Eric



From YhLu at tyan.com  Thu Jun 12 19:58:01 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jun 12 19:58:01 2003
Subject: =?GB2312?B?tPC4tDogSGlnaC1FbmQgRGVza3RvcCBTdXBwb3J0?=
Message-ID: <3174569B9743D511922F00A0C943142302C4392B@TYANWEB>

Ron, 

Any plan to make it support ICH5. It has USB 2.0 support and Serial ATA
support.

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?6?12? 8:37
???: Peter Fedorow
??: linuxbios at clustermatic.org
??: Re: High-End Desktop Support

On Thu, 12 Jun 2003, Peter Fedorow wrote:

> I'm looking for a fully supported motherboard that can accept at least a 
> 2 GHz Pentium 4 or AMD Athlon.

intel e7500, 7501, etc. are supported.

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From ebiederman at lnxi.com  Thu Jun 12 22:48:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Jun 12 22:48:01 2003
Subject: romcc progress.
In-Reply-To: <1055466905.4791.9.camel@localhost.localdomain>
References: <m3wuftto66.fsf@maxwell.lnxi.com>
	<1055466905.4791.9.camel@localhost.localdomain>
Message-ID: <m34r2uk7s6.fsf@maxwell.lnxi.com>

John van Vlaanderen <john-at-thinman at nyc.rr.com> writes:

> Hi Eric,
> 
> I think it's really incredible that you are developing this, and once
> it's done I am sure we will all wonder how we lived w/ out it.
> 
> But, as embarrassed as I am to ask, what is it for ??

I suspect others who have not followed this to closely probably
have the same question.  

romcc is a C compiler that does not use a stack.  Instead it keeps
all variables in registers.

Currently LinuxBIOS has a lot of assembly code simply because memory
initialization is difficult in the general case.  This code cannot be
written with a standard compiler because there is no memory to put
a stack in.  Nor on x86 are there cache blocks that can be locked into
place.  As code generated with romcc does not use a stack it can be
used during memory initialization.

It is true romcc is not *done*,  it is quite usable at this point.

In the freebios2 I have been gradually making the primary API ones
that can be used before  memory is initialized.

The biggest difference is that if you want to return multiple values
instead of passing in the address of a variable the a multi valued
structure must be returned.

The biggest current known bug is that if you have a small type
like short when it is stored in a register nothing ensures it does not
take on a larger value than will fit in a short.

unsigned short i;
i = 65535;
i = i + 1;  /* i == 65536 oops */

The biggest shortcoming comes from it's nature and 

I have used it enough at this point I don't want to live without it
again.

Eric



From YhLu at tyan.com  Fri Jun 13 03:12:00 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jun 13 03:12:00 2003
Subject: =?GB2312?B?tPC4tDogSGlnaC1FbmQgRGVza3RvcCBTdXBwb3J0?=
Message-ID: <3174569B9743D511922F00A0C943142302C43965@TYANWEB>

Eric,

I am working on porting linuxbios to Tyan s2725. The southbridge is ICH5.

I have copied 82801ca to 82801er. And update pci_ids.h to add some ICH5
device id.

I compare the Intel whitepaper, only need to comment out several line in
ich5_ioapi.c. because ICH5 has no operation to index 3 reg.

I didn't initialize USB and Serial ATA. 

I used e1000.ebi from Etherboot 5.0.8. 

I only got the following result. The ebi size is 18164, so I set
ROM_IMAGE_SIZE to 46*1024. 

I wonder why the size if not right: 0x4564 = 17764. But the EBI is 18164.

Regards

Yinghai Lu

Console output:

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    37:init_bytes() - zkernel_start:0xffff0000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x94000 size 0x7168 offset 0x60 filesize 0x4564
(cleaned up) New segment addr 0x94000 size 0x7168 offset 0x60 filesize
0x4564
Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007168 filesz:
0x00
00000000004564
Clearing Segment: addr: 0x0000000000098564 memsz: 0x0000000000002c04
Jumping to boot code at
0x??????????????????????????????????????????????????????
????????????????????????????????????????????????????????????????????????????

-----????????-----
??????: YhLu 
????????: 2003??6??12?? 17:12
??????: ron minnich; Peter Fedorow
????: linuxbios at clustermatic.org
????: ????: High-End Desktop Support

Ron, 

Any plan to make it support ICH5. It has USB 2.0 support and Serial ATA
support.

Yinghai Lu

-----????????-----
??????: ron minnich [mailto:rminnich at lanl.gov] 
????????: 2003??6??12?? 8:37
??????: Peter Fedorow
????: linuxbios at clustermatic.org
????: Re: High-End Desktop Support

On Thu, 12 Jun 2003, Peter Fedorow wrote:

> I'm looking for a fully supported motherboard that can accept at least a 
> 2 GHz Pentium 4 or AMD Athlon.

intel e7500, 7501, etc. are supported.

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From ts1 at cma.co.jp  Fri Jun 13 05:44:01 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Fri Jun 13 05:44:01 2003
Subject: ELF boot and Multiboot
In-Reply-To: <m3vfvbvpm0.fsf@maxwell.lnxi.com>
References: <20030612050407.GA4220@cma.co.jp> <m3vfvbvpm0.fsf@maxwell.lnxi.com>
Message-ID: <20030613094855.GA6017@cma.co.jp>

On Wed, Jun 11, 2003 at 11:20:23PM -0600, Eric W. Biederman wrote:
> > In the source of mkelfImage, linux-i386/convert_params.c,
> > there is some code to retrieve information like memory map
> > from Multiboot information structure.
> > However, ELF images created by mkelfImage does not have
> > Multiboot header, according to 'mbchk' of GRUB boot loader.
> > In what situation is this code supposed to run (and tested)?
> 
> The partial multiboot support in etherboot, is where it was used.

Thanks for the information.

> > If one added a (trivial) Multiboot header in the head.S,
> > the resulting kernel could be loaded from GRUB, while it could also
> > be loaded by ELF boot of LinuxBIOS and Etherboot?
> 
> It probably could.  And I would not have a problem with something
> like that in theory.  The multiboot spec is quite poorly done,
> so I am not a major fan.  I think I would prefer to just add a
> dummy elf segment at the start of the file with that information
> in it.  From mkelfImage 2.5 that would probably be the easiest thing
> to do.

I couldn't find an easy way to do it.
What PT_* type would that segment have?

> I would almost rather fix GRUB to use something sensible and portable
> like ELF notes.  The multiboot data structure is  a disaster in terms
> of both future expansion, and of expansion by multiple groups.

I considered to add ELFboot support to GRUB, but adding Multiboot
header to ELF kernel looked much easier.

--
Takeshi


From ts1 at cma.co.jp  Fri Jun 13 08:13:00 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Fri Jun 13 08:13:00 2003
Subject: ELF boot and Multiboot
In-Reply-To: <20030613094855.GA6017@cma.co.jp>
References: <20030612050407.GA4220@cma.co.jp> <m3vfvbvpm0.fsf@maxwell.lnxi.com> <20030613094855.GA6017@cma.co.jp>
Message-ID: <20030613121720.GA13080@cma.co.jp>

On Fri, Jun 13, 2003 at 06:48:55PM +0900, SONE Takeshi wrote:
> > > If one added a (trivial) Multiboot header in the head.S,
> > > the resulting kernel could be loaded from GRUB, while it could also
> > > be loaded by ELF boot of LinuxBIOS and Etherboot?
> > It probably could.

Turns out it can't.
GRUB can't load Multiboot (or other ELF) kernel below 1MB!
Since bzImage kernel starts at just 1MB, placing 'converter' and
gdt elsewhere after 1MB is not a trivial task..

Interesting(?) discussion on this issue:
http://mail.gnu.org/archive/html/bug-grub/2001-08/msg00083.html
-- 
Takeshi


From rminnich at lanl.gov  Fri Jun 13 09:49:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 13 09:49:01 2003
Subject: =?GB2312?B?tPC4tDogSGlnaC1FbmQgRGVza3RvcCBTdXBwb3J0?=
In-Reply-To: <3174569B9743D511922F00A0C943142302C4392B@TYANWEB>
Message-ID: <Pine.LNX.4.44.0306130752530.14135-100000@maxroach.lanl.gov>

On Thu, 12 Jun 2003, YhLu wrote:

> Any plan to make it support ICH5. It has USB 2.0 support and Serial ATA
> support.

sure, soon as somebody gets a board and wants to commit the time.

ron



From john-at-thinman at nyc.rr.com  Fri Jun 13 11:27:00 2003
From: john-at-thinman at nyc.rr.com (John van Vlaanderen)
Date: Fri Jun 13 11:27:00 2003
Subject: romcc progress.
In-Reply-To: <m34r2uk7s6.fsf@maxwell.lnxi.com>
References: <m3wuftto66.fsf@maxwell.lnxi.com>
	<1055466905.4791.9.camel@localhost.localdomain> 
	<m34r2uk7s6.fsf@maxwell.lnxi.com>
Message-ID: <1055518275.2087.19.camel@localhost.localdomain>

Haha, I thought so,

Eric wrote:
> I have used it enough at this point I don't want to live without it
> again.

I did spend the better part of last night reading the thread, though
that got to the why but not how.

Uses registers, not stacks -- like the Perl6 Parrot VM, I am going to
have to tell them :)

============
Eric's text
============
> Currently LinuxBIOS has a lot of assembly code simply because memory
> initialization is difficult in the general case.  This code cannot be
> written with a standard compiler because there is no memory to put
> a stack in.  Nor on x86 are there cache blocks that can be locked into
> place.  As code generated with romcc does not use a stack it can be
> used during memory initialization.
> 
> It is true romcc is not *done*,  it is quite usable at this point.
> 
> In the freebios2 I have been gradually making the primary API ones
> that can be used before  memory is initialized.
> 
> The biggest difference is that if you want to return multiple values
> instead of passing in the address of a variable the a multi valued
> structure must be returned.
> 
> The biggest current known bug is that if you have a small type
> like short when it is stored in a register nothing ensures it does not
> take on a larger value than will fit in a short.
> 
> unsigned short i;
> i = 65535;
> i = i + 1;  /* i == 65536 oops */
> 
> The biggest shortcoming comes from it's nature and 
> 
> I have used it enough at this point I don't want to live without it
> again.
> 
> Eric
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios




From ebiederman at lnxi.com  Fri Jun 13 13:19:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 13 13:19:00 2003
Subject: ELF boot and Multiboot
In-Reply-To: <20030613121720.GA13080@cma.co.jp>
References: <20030612050407.GA4220@cma.co.jp>
	<m3vfvbvpm0.fsf@maxwell.lnxi.com> <20030613094855.GA6017@cma.co.jp>
	<20030613121720.GA13080@cma.co.jp>
Message-ID: <m38ys5evre.fsf@maxwell.lnxi.com>

SONE Takeshi <ts1 at cma.co.jp> writes:

> On Fri, Jun 13, 2003 at 06:48:55PM +0900, SONE Takeshi wrote:
> > > > If one added a (trivial) Multiboot header in the head.S,
> > > > the resulting kernel could be loaded from GRUB, while it could also
> > > > be loaded by ELF boot of LinuxBIOS and Etherboot?
> > > It probably could.
> 
> Turns out it can't.
And now you see one of the many reasons GRUB has not yet been
ported to run under LinuxBIOS.

> GRUB can't load Multiboot (or other ELF) kernel below 1MB!
> Since bzImage kernel starts at just 1MB, placing 'converter' and
> gdt elsewhere after 1MB is not a trivial task..

A bzImage had a real mode component that must be run below 1MB.

Currently I place the ramdisk at 8MB, and the converter and the real
mode code could be placed on top of that.  I do something like this
for the Itanium.

Still it is less than satisfactory to require that to happen. 0-640K
is always known to be there so we should be able to use it.

Hopefully some time will open up and I can put out another ELF
booting specification.  

Eric



From ebiederman at lnxi.com  Fri Jun 13 13:22:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 13 13:22:00 2003
Subject: EPIA PCI slot
In-Reply-To: <Pine.LNX.4.53.0306121121350.2827@gw.linespeed.net>
References: <Pine.LNX.4.53.0306121121350.2827@gw.linespeed.net>
Message-ID: <m34r2tevmt.fsf@maxwell.lnxi.com>

"Brian G. Rhodes" <bgr at gw.linespeed.net> writes:

> The reason I was not getting interrupts on devices in the pci slot on the
> EPIA is because they were not set to be bus masters, so they would never
> generate interrupts.  A quick write to the command register fixed the
> problem.  Command register is being set to 0x02.  It should be set to
> 0x06.  a 6 to 4.

Actually this is an interesting symptom.  Being a Bus Master means you
can initiate transactions on the PCI bus i.e. DMA.  There is no requirement
that I know of that the bus master bit applies to IRQ's.  Those are out
of band signals.

Eric



From rminnich at lanl.gov  Fri Jun 13 13:25:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 13 13:25:01 2003
Subject: EPIA PCI slot
In-Reply-To: <m34r2tevmt.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306131129070.15453-100000@maxroach.lanl.gov>

On 13 Jun 2003, Eric W. Biederman wrote:

> "Brian G. Rhodes" <bgr at gw.linespeed.net> writes:
> 
> > The reason I was not getting interrupts on devices in the pci slot on the
> > EPIA is because they were not set to be bus masters, so they would never
> > generate interrupts.  A quick write to the command register fixed the
> > problem.  Command register is being set to 0x02.  It should be set to
> > 0x06.  a 6 to 4.
> 
> Actually this is an interesting symptom.  Being a Bus Master means you
> can initiate transactions on the PCI bus i.e. DMA.  There is no requirement
> that I know of that the bus master bit applies to IRQ's.  Those are out
> of band signals.

Seems like a hardware bug to me.

ron



From ebiederman at lnxi.com  Fri Jun 13 13:36:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 13 13:36:00 2003
Subject: romcc progress.
In-Reply-To: <1055518275.2087.19.camel@localhost.localdomain>
References: <m3wuftto66.fsf@maxwell.lnxi.com>
	<1055466905.4791.9.camel@localhost.localdomain>
	<m34r2uk7s6.fsf@maxwell.lnxi.com>
	<1055518275.2087.19.camel@localhost.localdomain>
Message-ID: <m3znkldgf2.fsf@maxwell.lnxi.com>

John van Vlaanderen <john-at-thinman at nyc.rr.com> writes:

> Haha, I thought so,
> 
> Eric wrote:
> > I have used it enough at this point I don't want to live without it
> > again.
> 
> I did spend the better part of last night reading the thread, though
> that got to the why but not how.
> 
> Uses registers, not stacks -- like the Perl6 Parrot VM, I am going to
> have to tell them :)

Actually quite a bit different.

Parrot will just not use stack oriented byte codes.   But a call/return
stack will still be required.  romcc does not use a call/return stack,
but romcc still implement subroutines.

Eric



From bgr at gw.linespeed.net  Fri Jun 13 16:54:00 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Fri Jun 13 16:54:00 2003
Subject: EPIA PCI slot
In-Reply-To: <m34r2tevmt.fsf@maxwell.lnxi.com>
References: <Pine.LNX.4.53.0306121121350.2827@gw.linespeed.net>
 <m34r2tevmt.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.53.0306131438340.22623@gw.linespeed.net>

Eric,

It was a side effect.  Since they were not initiating any tranfers.. DMA
from system memory on the pci bus, they were never low on data, and hence
never needed to generate an interrupt.  Initially I believed it to be a
pci routing problem, but when I saw the chips were not generating
interrupts, I looked at the scope.


Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Fri, 13 Jun 2003, Eric W. Biederman wrote:

> "Brian G. Rhodes" <bgr at gw.linespeed.net> writes:
>
> > The reason I was not getting interrupts on devices in the pci slot on the
> > EPIA is because they were not set to be bus masters, so they would never
> > generate interrupts.  A quick write to the command register fixed the
> > problem.  Command register is being set to 0x02.  It should be set to
> > 0x06.  a 6 to 4.
>
> Actually this is an interesting symptom.  Being a Bus Master means you
> can initiate transactions on the PCI bus i.e. DMA.  There is no requirement
> that I know of that the bus master bit applies to IRQ's.  Those are out
> of band signals.
>
> Eric
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From YhLu at tyan.com  Sat Jun 14 02:40:01 2003
From: YhLu at tyan.com (YhLu)
Date: Sat Jun 14 02:40:01 2003
Subject: =?gb2312?B?tPC4tDogSGlnaC1FbmQgRGVza3RvcCBTdXBwb3J0?=
Message-ID: <3174569B9743D511922F00A0C943142302C43A3A@TYANWEB>

Eric and Ron,

I can get into the Etherboot now.  But I meet problem again:

Etherboot 5.0.10 (Last Product version) only support Intel 82544. Tyan s2725
uses Intel 82646EB. (DeviceID is ox1010).
So It said" No Adapter found". 

Etherboot 5.1.8 seems support 82546, But I found
1. can not make EBI, have to use ELF. It is around 30KB.
2. If disable RELOCATION : got error: NO HEAP FOUND.
3. If enable RELOCATION: got error: It can not calculate the file size, and
keep print " 61:rom_read_bytes() - skipping block 16"

My Question is:
1. When do you plan to support 82546? In 5.0.11 or 5.2.0.
2. Is there any easy way to modify 5.0.10 to make it work with Intel 82546?


Thanks and regards

Yinghai Lu




222222222222222222222222222222222222222222222222222
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    37:init_bytes() - zkernel_start:0xffff0000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
Dropping non PT_LOAD segment
New segment addr 0x20000 size 0x10e80c3 offset 0xb0 filesize 0x755c
(cleaned up) New segment addr 0x20000 size 0x10e80c3 offset 0xb0 filesize
0x755c

Loading Segment: addr: 0x000000003ffca7e8 memsz: 0x000000000000ec0c filesz:
0x00
0000000000755c
Clearing Segment: addr: 0x000000003ffd1d44 memsz: 0x00000000000076b0
Loading Segment: addr: 0x000000000002ec0c memsz: 0x00000000010d94b7 filesz:
0x00
00000000000000
Clearing Segment: addr: 0x000000000002ec0c memsz: 0x00000000010d94b7
Jumping to boot code at 0x20000
ROM segment 0x0000 length 0xfbf8 reloc 0x00020000
CPU 1343 Mhz
Etherboot 5.1.8 (GPL) Tagged ELF (Multiboot) for [E1000]
init_heap: No heap found.

22222222222222222222222222222222222222222222222222222222222222222

33333333333333333333333333333333333333333333333333333333333333333333333333
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    37:init_bytes() - zkernel_start:0xffff0000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
Dropping non PT_LOAD segment
New segment addr 0x20000 size 0x1106000 offset 0xb0 filesize 0x76bcc3
(cleaned up) New segment addr 0x20000 size 0x1106000 offset 0xb0 filesize
0x76bc
c3
Loading Segment: addr: 0x000000003ffca7e8 memsz: 0x000000000000ec0c filesz:
0x00
0000000000ec0c
Loading Segment: addr: 0x000000000002ec0c memsz: 0x00000000010f73f4 filesz:
0x00
0000000075d0b7
    61:rom_read_bytes() - skipping block 16
    61:rom_read_bytes() - skipping block 16
    61:rom_read_bytes() - skipping block 16
    61:rom_read_bytes() - skipping block 16
    61:rom_read_bytes() - skipping block 16
    61:rom_read_bytes() - skipping block 16
    61:rom_read_bytes() - skipping block 16
3333333333333333333333333333333333333333333333333333333333333333333333333333
3

-----????????-----
??????: YhLu 
????????: 2003??6??13?? 0:27
??????: ron minnich; ebiederman at lnxi.com
????: linuxbios at clustermatic.org
????: ????: High-End Desktop Support

Eric,

I am working on porting linuxbios to Tyan s2725. The southbridge is ICH5.

I have copied 82801ca to 82801er. And update pci_ids.h to add some ICH5
device id.

I compare the Intel whitepaper, only need to comment out several line in
ich5_ioapi.c. because ICH5 has no operation to index 3 reg.

I didn't initialize USB and Serial ATA. 

I used e1000.ebi from Etherboot 5.0.8. 

I only got the following result. The ebi size is 18164, so I set
ROM_IMAGE_SIZE to 46*1024. 

I wonder why the size if not right: 0x4564 = 17764. But the EBI is 18164.

Regards

Yinghai Lu

Console output:

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    37:init_bytes() - zkernel_start:0xffff0000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x94000 size 0x7168 offset 0x60 filesize 0x4564
(cleaned up) New segment addr 0x94000 size 0x7168 offset 0x60 filesize
0x4564
Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007168 filesz:
0x00
00000000004564
Clearing Segment: addr: 0x0000000000098564 memsz: 0x0000000000002c04
Jumping to boot code at
0x??????????????????????????????????????????????????????
????????????????????????????????????????????????????????????????????????????

-----????????-----
??????: YhLu 
????????: 2003??6??12?? 17:12
??????: ron minnich; Peter Fedorow
????: linuxbios at clustermatic.org
????: ????: High-End Desktop Support

Ron, 

Any plan to make it support ICH5. It has USB 2.0 support and Serial ATA
support.

Yinghai Lu

-----????????-----
??????: ron minnich [mailto:rminnich at lanl.gov] 
????????: 2003??6??12?? 8:37
??????: Peter Fedorow
????: linuxbios at clustermatic.org
????: Re: High-End Desktop Support

On Thu, 12 Jun 2003, Peter Fedorow wrote:

> I'm looking for a fully supported motherboard that can accept at least a 
> 2 GHz Pentium 4 or AMD Athlon.

intel e7500, 7501, etc. are supported.

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From ebiederman at lnxi.com  Sat Jun 14 12:18:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sat Jun 14 12:18:01 2003
Subject: =?gb2312?b?tPC4tA==?=: High-End Desktop Support
In-Reply-To: <3174569B9743D511922F00A0C943142302C43A3A@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43A3A@TYANWEB>
Message-ID: <m3he6sy6fj.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric and Ron,
> 
> I can get into the Etherboot now.  But I meet problem again:
> 
> Etherboot 5.0.10 (Last Product version) only support Intel 82544. Tyan s2725
> uses Intel 82646EB. (DeviceID is ox1010).
> So It said" No Adapter found". 
> 
> Etherboot 5.1.8 seems support 82546, But I found
> 1. can not make EBI, have to use ELF. It is around 30KB.

Correct.  You can also make zelf if that helps.  There was
a naming cleanup in the extensions used by etherboot.

> 2. If disable RELOCATION : got error: NO HEAP FOUND.
Something is very wrong here even though etherboot got
loaded.  There are PT_LOAD segments.  Etherboot only has one.
Something looks corrupted.

> 3. If enable RELOCATION: got error: It can not calculate the file size, and
> keep print " 61:rom_read_bytes() - skipping block 16"

The only difference in the loader that looks relevant
is the second PT_LOAD segment now has a size.


You are not running mkelfImage on the etherboot file are you?
That is only need for the Linux kernel.

> My Question is:
> 1. When do you plan to support 82546? In 5.0.11 or 5.2.0.
5.0.x never.  GigE drivers are to large, to easily support there.
Plus the LinuxBIOS support isn't half as good in 5.0.x.  

As for 5.2.x whenever there is enough consensus among the developers
that we are there.  We are quite close but...

p.s. Someone remind me to put calculate the checksum on the
etherboot image in apply_elf_prefix...

> 2. Is there any easy way to modify 5.0.10 to make it work with Intel 82546?

No.


Here is a snippet of what the loader Loading etherboot should look like.
------------------------------

Found ELF candiate at offset 0
Loading Etherboot version: 5.1.8pre5
Dropping non PT_LOAD segment
New segment addr 0x20000 size 0x21aa2 offset 0xc0 filesize 0x61de
(cleaned up) New segment addr 0x20000 size 0x21aa2 offset 0xc0 filesize 0x61de
Loading Segment: addr: 0x0000000000020000 memsz: 0x0000000000021aa2 filesz: 0x00000000000061de
Clearing Segment: addr: 0x00000000000261de memsz: 0x000000000001b8c4
Jumping to boot code at 0x20000
ROM segment 0xdffe length 0xd050 reloc 0x00020000

> 
> 222222222222222222222222222222222222222222222222222
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.2
> 
>     37:init_bytes() - zkernel_start:0xffff0000  zkernel_mask:0x0000ffff
> Found ELF candiate at offset 0
> Dropping non PT_LOAD segment
> New segment addr 0x20000 size 0x10e80c3 offset 0xb0 filesize 0x755c
> (cleaned up) New segment addr 0x20000 size 0x10e80c3 offset 0xb0 filesize
> 0x755c
> 
> Loading Segment: addr: 0x000000003ffca7e8 memsz: 0x000000000000ec0c filesz:
> 0x00
> 0000000000755c
> Clearing Segment: addr: 0x000000003ffd1d44 memsz: 0x00000000000076b0
> Loading Segment: addr: 0x000000000002ec0c memsz: 0x00000000010d94b7 filesz:
> 0x00
> 00000000000000
> Clearing Segment: addr: 0x000000000002ec0c memsz: 0x00000000010d94b7
> Jumping to boot code at 0x20000
> ROM segment 0x0000 length 0xfbf8 reloc 0x00020000
> CPU 1343 Mhz
> Etherboot 5.1.8 (GPL) Tagged ELF (Multiboot) for [E1000]
> init_heap: No heap found.
> 
> 22222222222222222222222222222222222222222222222222222222222222222
> 
> 33333333333333333333333333333333333333333333333333333333333333333333333333
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.2
> 
>     37:init_bytes() - zkernel_start:0xffff0000  zkernel_mask:0x0000ffff
> Found ELF candiate at offset 0
> Dropping non PT_LOAD segment
> New segment addr 0x20000 size 0x1106000 offset 0xb0 filesize 0x76bcc3
> (cleaned up) New segment addr 0x20000 size 0x1106000 offset 0xb0 filesize
> 0x76bc
> c3
> Loading Segment: addr: 0x000000003ffca7e8 memsz: 0x000000000000ec0c filesz:
> 0x00
> 0000000000ec0c
> Loading Segment: addr: 0x000000000002ec0c memsz: 0x00000000010f73f4 filesz:
> 0x00
> 0000000075d0b7
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
> 3333333333333333333333333333333333333333333333333333333333333333333333333333
> 3
> 
> -----????????-----
> ??????: YhLu 
> ????????: 2003??6??13?? 0:27
> ??????: ron minnich; ebiederman at lnxi.com
> ????: linuxbios at clustermatic.org
> ????: ????: High-End Desktop Support
> 
> Eric,
> 
> I am working on porting linuxbios to Tyan s2725. The southbridge is ICH5.
> 
> I have copied 82801ca to 82801er. And update pci_ids.h to add some ICH5
> device id.
> 
> I compare the Intel whitepaper, only need to comment out several line in
> ich5_ioapi.c. because ICH5 has no operation to index 3 reg.
> 
> I didn't initialize USB and Serial ATA. 
> 
> I used e1000.ebi from Etherboot 5.0.8. 
> 
> I only got the following result. The ebi size is 18164, so I set
> ROM_IMAGE_SIZE to 46*1024. 
> 
> I wonder why the size if not right: 0x4564 = 17764. But the EBI is 18164.
> 
> Regards
> 
> Yinghai Lu
> 
> Console output:
> 
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.2
> 
>     37:init_bytes() - zkernel_start:0xffff0000  zkernel_mask:0x0000ffff
> Found ELF candiate at offset 0
> New segment addr 0x94000 size 0x7168 offset 0x60 filesize 0x4564
> (cleaned up) New segment addr 0x94000 size 0x7168 offset 0x60 filesize
> 0x4564
> Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007168 filesz:
> 0x00
> 00000000004564
> Clearing Segment: addr: 0x0000000000098564 memsz: 0x0000000000002c04
> Jumping to boot code at
> 0x??????????????????????????????????????????????????????
> 
> ????????????????????????????????????????????????????????????????????????????
> 



From yhlu at tyan.com  Sat Jun 14 16:54:00 2003
From: yhlu at tyan.com (Yinghai Lu)
Date: Sat Jun 14 16:54:00 2003
Subject: =?gb2312?B?tPC4tDogtPC4tDogSGlnaC1FbmQgRGVza3RvcCBTdXBwb3J0?=
In-Reply-To: <m3he6sy6fj.fsf@maxwell.lnxi.com>
Message-ID: <000001c332b7$6b3e12e0$ddb5ca3f@yhlunb>

Eric,

Thanks for the quick response.
>> 3. If enable RELOCATION: got error: It can not calculate the file
size, and
>> keep print " 61:rom_read_bytes() - skipping block 16"
>The only difference in the loader that looks relevant
>is the second PT_LOAD segment now has a size.
>You are not running mkelfImage on the etherboot file are you?
>That is only need for the Linux kernel.

Yes, I didn't mkelfImage, I only use that to transfer kernel and add
some tags, at last the ELF files is put into the boot server's
/tftpboot.

In the Config, You said that 5.2 need all drivers to support RELOCATION.
So Does the E1000 driver support RELOCATION yet?

Your snippet is for RELOCATION or not?

Regards

Yinghai Lu

-----????????-----
??????: Eric W. Biederman [mailto:eric at lnxi.com] ???? Eric W. Biederman
????????: 2003??6??14?? 9:23
??????: YhLu
????: ron minnich; linuxbios at clustermatic.org; Etherboot Developers
????: Re: ????: High-End Desktop Support

YhLu <YhLu at tyan.com> writes:

> Eric and Ron,
> 
> I can get into the Etherboot now.  But I meet problem again:
> 
> Etherboot 5.0.10 (Last Product version) only support Intel 82544. Tyan
s2725
> uses Intel 82646EB. (DeviceID is ox1010).
> So It said" No Adapter found". 
> 
> Etherboot 5.1.8 seems support 82546, But I found
> 1. can not make EBI, have to use ELF. It is around 30KB.

Correct.  You can also make zelf if that helps.  There was
a naming cleanup in the extensions used by etherboot.

> 2. If disable RELOCATION : got error: NO HEAP FOUND.
Something is very wrong here even though etherboot got
loaded.  There are PT_LOAD segments.  Etherboot only has one.
Something looks corrupted.

> 3. If enable RELOCATION: got error: It can not calculate the file
size, and
> keep print " 61:rom_read_bytes() - skipping block 16"

The only difference in the loader that looks relevant
is the second PT_LOAD segment now has a size.


You are not running mkelfImage on the etherboot file are you?
That is only need for the Linux kernel.

> My Question is:
> 1. When do you plan to support 82546? In 5.0.11 or 5.2.0.
5.0.x never.  GigE drivers are to large, to easily support there.
Plus the LinuxBIOS support isn't half as good in 5.0.x.  

As for 5.2.x whenever there is enough consensus among the developers
that we are there.  We are quite close but...

p.s. Someone remind me to put calculate the checksum on the
etherboot image in apply_elf_prefix...

> 2. Is there any easy way to modify 5.0.10 to make it work with Intel
82546?

No.


Here is a snippet of what the loader Loading etherboot should look like.
------------------------------

Found ELF candiate at offset 0
Loading Etherboot version: 5.1.8pre5
Dropping non PT_LOAD segment
New segment addr 0x20000 size 0x21aa2 offset 0xc0 filesize 0x61de
(cleaned up) New segment addr 0x20000 size 0x21aa2 offset 0xc0 filesize
0x61de
Loading Segment: addr: 0x0000000000020000 memsz: 0x0000000000021aa2
filesz: 0x00000000000061de
Clearing Segment: addr: 0x00000000000261de memsz: 0x000000000001b8c4
Jumping to boot code at 0x20000
ROM segment 0xdffe length 0xd050 reloc 0x00020000

> 
> 222222222222222222222222222222222222222222222222222
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.2
> 
>     37:init_bytes() - zkernel_start:0xffff0000
zkernel_mask:0x0000ffff
> Found ELF candiate at offset 0
> Dropping non PT_LOAD segment
> New segment addr 0x20000 size 0x10e80c3 offset 0xb0 filesize 0x755c
> (cleaned up) New segment addr 0x20000 size 0x10e80c3 offset 0xb0
filesize
> 0x755c
> 
> Loading Segment: addr: 0x000000003ffca7e8 memsz: 0x000000000000ec0c
filesz:
> 0x00
> 0000000000755c
> Clearing Segment: addr: 0x000000003ffd1d44 memsz: 0x00000000000076b0
> Loading Segment: addr: 0x000000000002ec0c memsz: 0x00000000010d94b7
filesz:
> 0x00
> 00000000000000
> Clearing Segment: addr: 0x000000000002ec0c memsz: 0x00000000010d94b7
> Jumping to boot code at 0x20000
> ROM segment 0x0000 length 0xfbf8 reloc 0x00020000
> CPU 1343 Mhz
> Etherboot 5.1.8 (GPL) Tagged ELF (Multiboot) for [E1000]
> init_heap: No heap found.
> 
> 22222222222222222222222222222222222222222222222222222222222222222
> 
>
333333333333333333333333333333333333333333333333333333333333333333333333
33
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.2
> 
>     37:init_bytes() - zkernel_start:0xffff0000
zkernel_mask:0x0000ffff
> Found ELF candiate at offset 0
> Dropping non PT_LOAD segment
> New segment addr 0x20000 size 0x1106000 offset 0xb0 filesize 0x76bcc3
> (cleaned up) New segment addr 0x20000 size 0x1106000 offset 0xb0
filesize
> 0x76bc
> c3
> Loading Segment: addr: 0x000000003ffca7e8 memsz: 0x000000000000ec0c
filesz:
> 0x00
> 0000000000ec0c
> Loading Segment: addr: 0x000000000002ec0c memsz: 0x00000000010f73f4
filesz:
> 0x00
> 0000000075d0b7
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>     61:rom_read_bytes() - skipping block 16
>
333333333333333333333333333333333333333333333333333333333333333333333333
3333
> 3
> 
> -----????????-----
> ??????: YhLu 
> ????????: 2003??6??13?? 0:27
> ??????: ron minnich; ebiederman at lnxi.com
> ????: linuxbios at clustermatic.org
> ????: ????: High-End Desktop Support
> 
> Eric,
> 
> I am working on porting linuxbios to Tyan s2725. The southbridge is
ICH5.
> 
> I have copied 82801ca to 82801er. And update pci_ids.h to add some
ICH5
> device id.
> 
> I compare the Intel whitepaper, only need to comment out several line
in
> ich5_ioapi.c. because ICH5 has no operation to index 3 reg.
> 
> I didn't initialize USB and Serial ATA. 
> 
> I used e1000.ebi from Etherboot 5.0.8. 
> 
> I only got the following result. The ebi size is 18164, so I set
> ROM_IMAGE_SIZE to 46*1024. 
> 
> I wonder why the size if not right: 0x4564 = 17764. But the EBI is
18164.
> 
> Regards
> 
> Yinghai Lu
> 
> Console output:
> 
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.2
> 
>     37:init_bytes() - zkernel_start:0xffff0000
zkernel_mask:0x0000ffff
> Found ELF candiate at offset 0
> New segment addr 0x94000 size 0x7168 offset 0x60 filesize 0x4564
> (cleaned up) New segment addr 0x94000 size 0x7168 offset 0x60 filesize
> 0x4564
> Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007168
filesz:
> 0x00
> 00000000004564
> Clearing Segment: addr: 0x0000000000098564 memsz: 0x0000000000002c04
> Jumping to boot code at
> 0x??????????????????????????????????????????????????????
> 
>
????????????????????????????????????????????????????????????????????????
????
> 



From ebiederman at lnxi.com  Sat Jun 14 17:19:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sat Jun 14 17:19:01 2003
Subject: =?gb2312?b?tPC4tA==?=: =?gb2312?b?tPC4tA==?=: High-End Desktop
  Support
In-Reply-To: <000001c332b7$6b3e12e0$ddb5ca3f@yhlunb>
References: <000001c332b7$6b3e12e0$ddb5ca3f@yhlunb>
Message-ID: <m3llw4wdxa.fsf@maxwell.lnxi.com>

"Yinghai Lu" <yhlu at tyan.com> writes:

> Eric,
> 
> Thanks for the quick response.
> >> 3. If enable RELOCATION: got error: It can not calculate the file
> size, and
> >> keep print " 61:rom_read_bytes() - skipping block 16"
> >The only difference in the loader that looks relevant
> >is the second PT_LOAD segment now has a size.
> >You are not running mkelfImage on the etherboot file are you?
> >That is only need for the Linux kernel.
> 
> Yes, I didn't mkelfImage, I only use that to transfer kernel and add
> some tags, at last the ELF files is put into the boot server's
> /tftpboot.

Hmm.  Then you have something corrupted.
 
> In the Config, You said that 5.2 need all drivers to support RELOCATION.
> So Does the E1000 driver support RELOCATION yet?

Yes.
 
> Your snippet is for RELOCATION or not?

RELOCATION but that should not matter this early in the startup
because you die before the code is relocated.

Seriously the ELF header information was very wrong.  Multiple
PT_LOAD segments.  And addresses and sizes that don't make
any sense at all.  I don't know where to start but it looks
very strongly like your ELF image is corrupted.

Eric



From yhlu at tyan.com  Sat Jun 14 20:52:00 2003
From: yhlu at tyan.com (Yinghai Lu)
Date: Sat Jun 14 20:52:00 2003
Subject: =?utf-8?B?562U5aSNOiDnrZTlpI06IOetlOWkjTogSGlnaC1FbmQgRGVza3RvcCAgU3VwcA==?=
	=?utf-8?B?b3J0?=
In-Reply-To: <m3llw4wdxa.fsf@maxwell.lnxi.com>
Message-ID: <000001c332d8$be5397e0$ebb6ca3f@yhlunb>

Thanks, I will try again with zelf.

I have used strip make ebi, 
# strip -R comment -R note e1000.elf
The EBI file only 92 bytes ???

-----????-----
???: Eric W. Biederman [mailto:eric at lnxi.com] ?? Eric W. Biederman
????: 2003?6?14? 14:24
???: Yinghai Lu
??: 'ron minnich'; linuxbios at clustermatic.org; 'Etherboot Developers'
??: Re: ????: ????: High-End Desktop Support

"Yinghai Lu" <yhlu at tyan.com> writes:

> Eric,
> 
> Thanks for the quick response.
> >> 3. If enable RELOCATION: got error: It can not calculate the file
> size, and
> >> keep print " 61:rom_read_bytes() - skipping block 16"
> >The only difference in the loader that looks relevant
> >is the second PT_LOAD segment now has a size.
> >You are not running mkelfImage on the etherboot file are you?
> >That is only need for the Linux kernel.
> 
> Yes, I didn't mkelfImage, I only use that to transfer kernel and add
> some tags, at last the ELF files is put into the boot server's
> /tftpboot.

Hmm.  Then you have something corrupted.
 
> In the Config, You said that 5.2 need all drivers to support RELOCATION.
> So Does the E1000 driver support RELOCATION yet?

Yes.
 
> Your snippet is for RELOCATION or not?

RELOCATION but that should not matter this early in the startup
because you die before the code is relocated.

Seriously the ELF header information was very wrong.  Multiple
PT_LOAD segments.  And addresses and sizes that don't make
any sense at all.  I don't know where to start but it looks
very strongly like your ELF image is corrupted.

Eric



From ebiederman at lnxi.com  Sat Jun 14 21:11:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sat Jun 14 21:11:01 2003
Subject: [Etherboot-developers] ç­å¤: ç­å¤: ç­å¤: High-End Desktop  Support
In-Reply-To: <000001c332d8$be5397e0$ebb6ca3f@yhlunb>
References: <000001c332d8$be5397e0$ebb6ca3f@yhlunb>
Message-ID: <m3of10b0mt.fsf@maxwell.lnxi.com>

"Yinghai Lu" <yhlu at tyan.com> writes:

> Thanks, I will try again with zelf.
> 
> I have used strip make ebi, 
> # strip -R comment -R note e1000.elf
> The EBI file only 92 bytes ???

There should be nothing worth stripping by the time the etherboot
build gets that far, at least for 5.1.x.  It is desirable to
keep the notes we have placed there.

Beyond that it looks like by trying to strip etherboot you have
hit one of the many binutils bugs that crop up from time to time.

Eric



From yhlu at tyan.com  Sat Jun 14 21:57:00 2003
From: yhlu at tyan.com (Yinghai Lu)
Date: Sat Jun 14 21:57:00 2003
Subject: [Etherboot-developers]  High-End Desktop  Support
In-Reply-To: <m3of10b0mt.fsf@maxwell.lnxi.com>
Message-ID: <000001c332e1$ca809280$ebb6ca3f@yhlunb>

Eric,

But it works for 5.0.8 and 5.0.9. and I have tried it on RH 8 and RH 9.

1. strip e1000.elf : 92 bytes
2. strip -R comment e1000.elf : 92 bytes.
3. strip -R note e1000.elf : 92 bytes.
4. strip -R comment -R note e1000.elf : 92 bytes.

Anyway I will use zelf format.

Regards

Yinghai Lu

-----????-----
???: linuxbios-admin at clustermatic.org
[mailto:linuxbios-admin at clustermatic.org] ?? Eric W. Biederman
????: 2003?6?14? 18:17
???: Yinghai Lu
??: 'ron minnich'; linuxbios at clustermatic.org; 'Etherboot Developers'
??: Re: [Etherboot-developers] g-e$: g-e$: g-e$: High-End Desktop
Support

"Yinghai Lu" <yhlu at tyan.com> writes:

> Thanks, I will try again with zelf.
> 
> I have used strip make ebi, 
> # strip -R comment -R note e1000.elf
> The EBI file only 92 bytes ???

There should be nothing worth stripping by the time the etherboot
build gets that far, at least for 5.1.x.  It is desirable to
keep the notes we have placed there.

Beyond that it looks like by trying to strip etherboot you have
hit one of the many binutils bugs that crop up from time to time.

Eric

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Mon Jun 16 01:01:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 16 01:01:01 2003
Subject: AMD SC520
Message-ID: <Pine.LNX.4.44.0306152305230.18581-100000@maxroach.lanl.gov>

I'm starting a port. Anyone with info on this part that could be helpful 
let me know. 

I'm doing this on my own time to help support: http://psas.pdx.edu. 

Booting a flight computer in 5 seconds is better than booting one in 90 
seconds -- esp. in mid flight.

ron



From ebiederman at lnxi.com  Mon Jun 16 02:13:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jun 16 02:13:00 2003
Subject: AMD SC520
In-Reply-To: <Pine.LNX.4.44.0306152305230.18581-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306152305230.18581-100000@maxroach.lanl.gov>
Message-ID: <m365n6k0hr.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> I'm starting a port. Anyone with info on this part that could be helpful 
> let me know. 

Say something like:
http://www.amd.com/epd/processors/4.32bitcont/14.lan5xxfam/24.lansc520/index.html

And in case you hadn't noticed you have about a 100 of them in Pink...

> I'm doing this on my own time to help support: http://psas.pdx.edu. 
> 
> Booting a flight computer in 5 seconds is better than booting one in 90 
> seconds -- esp. in mid flight.

Certainly.

Eric



From ollie at sis.com.tw  Mon Jun 16 03:18:00 2003
From: ollie at sis.com.tw (ollie lho)
Date: Mon Jun 16 03:18:00 2003
Subject: AMD SC520
In-Reply-To: <Pine.LNX.4.44.0306152305230.18581-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306152305230.18581-100000@maxroach.lanl.gov>
Message-ID: <1055747543.986.45.camel@ollie>

On Mon, 2003-06-16 at 13:06, ron minnich wrote:
> I'm starting a port. Anyone with info on this part that could be helpful 
> let me know. 
> 
> I'm doing this on my own time to help support: http://psas.pdx.edu. 
> 

Are they building their own private rockets ?
-- 
ollie lho <ollie at sis.com.tw>



From adam at cfar.umd.edu  Mon Jun 16 09:29:00 2003
From: adam at cfar.umd.edu (Adam Sulmicki)
Date: Mon Jun 16 09:29:00 2003
Subject: AMD SC520
In-Reply-To: <1055747543.986.45.camel@ollie>
Message-ID: <20030616093813.O86593-100000@www.missl.cs.umd.edu>

> > I'm starting a port. Anyone with info on this part that could be helpful
> > let me know.
> >
> > I'm doing this on my own time to help support: http://psas.pdx.edu.
>
> Are they building their own private rockets ?

Yeah. They were demoing all this during USENIX 03. Pretty damn cool.
And they try to use Open Source whenver possible.

I hope to post some pictures from USENIX soon.

-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers



From ebiederman at lnxi.com  Mon Jun 16 12:54:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jun 16 12:54:01 2003
Subject: romcc progress.
In-Reply-To: <3EEDBA2D.6040807@austin.rr.com>
References: <m3wuftto66.fsf@maxwell.lnxi.com>
	<1055466905.4791.9.camel@localhost.localdomain>
	<m34r2uk7s6.fsf@maxwell.lnxi.com> <3EEDBA2D.6040807@austin.rr.com>
Message-ID: <m3he6qklf4.fsf@maxwell.lnxi.com>

Please don't do html mail...
And please CC the linuxBIOS list.  I admit it is not a real
substitute for documentation but with these kinds of discussions
happening in public the information is distributed more widely
and more people can answer question or take action based on
a conversation.

Jeff Pipkins <jpipkins at austin.rr.com> writes:

> This is a really cool concept, and a very useful tool. &nbsp;<br>
> <br>
> It took me a while to figure out what romcc was from reading the romcc code
> and the LinuxBIOS code. &nbsp;I think it would be worthwhile to put a copy of
> the email below in the romcc directory in the source tree, especially if
> you think it'll be a while before any formal documenation exists. &nbsp;

That sounds like a good idea.  I will see about that.

> It would
> also be helpful to have a short comment in the C code that depends on romcc
> to say so. &nbsp;Otherwise, it's a real head-twister to see a C program setting
> up mtrr's! &nbsp;;^)<br>

Well changing mtrrs is not romcc specific.  We do that even in
the freebios1 tree.  With romcc you can just run the C code earlier.
The real difference is that with romcc rdmsr wrmsr are done with
builtins whereas with gcc you need to do inline asm.  

I am in the processes of setting of the APIs in LinuxBIOS so
that most code will work with or without romcc.  You comment
reminds me that I still have to sync of the rdmsr/wrmsr APIs...

> <br>
> Nice piece of work, thanks in advance for the fun I'm going to have with
> it!<br>

Welcome. 

And BTW I have just committed a change that reduces the algorithmic
complexity of parts of the register allocator.  So the compiler now
should have a much more reasonable runtime.

Eric



From YhLu at tyan.com  Mon Jun 16 13:49:00 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jun 16 13:49:00 2003
Subject: High-End Desktop  Support
Message-ID: <3174569B9743D511922F00A0C943142302C43AC2@TYANWEB>

Eric and Ron,

Thanks for the direction.

After I use zelf format, the NIC is OK and can download kernel from thr TFTP
server now.

Regards

Yinghai Lu

-----????-----
???: linuxbios-admin at clustermatic.org
[mailto:linuxbios-admin at clustermatic.org] ?? Yinghai Lu
????: 2003?6?14? 19:00
???: 'Eric W. Biederman'
??: 'ron minnich'; linuxbios at clustermatic.org; 'Etherboot Developers'
??: Re: [Etherboot-developers] High-End Desktop Support

Eric,

But it works for 5.0.8 and 5.0.9. and I have tried it on RH 8 and RH 9.

1. strip e1000.elf : 92 bytes
2. strip -R comment e1000.elf : 92 bytes.
3. strip -R note e1000.elf : 92 bytes.
4. strip -R comment -R note e1000.elf : 92 bytes.

Anyway I will use zelf format.

Regards

Yinghai Lu

-----????-----
???: linuxbios-admin at clustermatic.org
[mailto:linuxbios-admin at clustermatic.org] ?? Eric W. Biederman
????: 2003?6?14? 18:17
???: Yinghai Lu
??: 'ron minnich'; linuxbios at clustermatic.org; 'Etherboot Developers'
??: Re: [Etherboot-developers] g-e$: g-e$: g-e$: High-End Desktop
Support

"Yinghai Lu" <yhlu at tyan.com> writes:

> Thanks, I will try again with zelf.
> 
> I have used strip make ebi, 
> # strip -R comment -R note e1000.elf
> The EBI file only 92 bytes ???

There should be nothing worth stripping by the time the etherboot
build gets that far, at least for 5.1.x.  It is desirable to
keep the notes we have placed there.

Beyond that it looks like by trying to strip etherboot you have
hit one of the many binutils bugs that crop up from time to time.

Eric

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From jalton at olsh.cx  Tue Jun 17 03:19:01 2003
From: jalton at olsh.cx (James Alton)
Date: Tue Jun 17 03:19:01 2003
Subject: Looking for a motherboard for linuxbios
Message-ID: <1055834639.1163.664.camel@localhost.localdomain>

Hi,
I'd like to find a the model number of a stable LinuxBIOS motherboard
that supports DDR. I'd prefer a pcchips board, but I would like the
cheapest DDR board that works with LinuxBIOS.

Thank you for any help you can provide,
James Alton





From jalton at olsh.cx  Tue Jun 17 16:14:00 2003
From: jalton at olsh.cx (James Alton)
Date: Tue Jun 17 16:14:00 2003
Subject: Looking for a motherboard for linuxbios
In-Reply-To: <20030617160001.1487.72783.Mailman@nwn.definitive.org>
References: <20030617160001.1487.72783.Mailman@nwn.definitive.org>
Message-ID: <1055881164.1670.670.camel@localhost.localdomain>

I would like to add that the PCCHIPS m935DLU looks like the board meets
most of my criteria, but is the chipset supported? (It uses a SiS 650GX
& 962L chipset) It's a P4 478-pin motherboard with 2 DDR slots capable
of 2GB ram with built in LAN/Sound/Video/etc. Here is the pcchips URL I
am looking at:

http://www.pcchips.com.tw/product/M935DLUv12.html

James Alton


> Subject: Looking for a motherboard for linuxbios
> From: James Alton <jalton at olsh.cx>
> To: linuxbios at clustermatic.org
> Date: 17 Jun 2003 00:23:58 -0700
> 
> Hi,
> I'd like to find a the model number of a stable LinuxBIOS motherboard
> that supports DDR. I'd prefer a pcchips board, but I would like the
> cheapest DDR board that works with LinuxBIOS.
> 
> Thank you for any help you can provide,
> James Alton



From ijpriya at hotmail.com  Wed Jun 18 03:32:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Wed Jun 18 03:32:01 2003
Subject: sc1200!
Message-ID: <BAY2-F155FcxT5nwZvI0001d971@hotmail.com>

Hello,

         I want to use LinuxBIOS for my SC1200. I dont know where to start 
and how to start? If I have to build for sc1200, can I use the same build 
instructions for the sis motherboard? Plz help me!

_________________________________________________________________
Gift yourself a holiday. Treat your family like royalty. 
http://www.flexihols.com/2003/index.php



From paul.wong at digitalview.com  Wed Jun 18 07:55:01 2003
From: paul.wong at digitalview.com (Paul Wong)
Date: Wed Jun 18 07:55:01 2003
Subject: sc1200!
References: <BAY2-F155FcxT5nwZvI0001d971@hotmail.com>
Message-ID: <001201c33590$cde89380$6400a8c0@mobile>

it is similar with nano , find it folder in src.

Paul
----- Original Message -----
From: "Devi Priya" <ijpriya at hotmail.com>
To: <linuxbios at clustermatic.org>
Sent: Wednesday, June 18, 2003 3:37 AM
Subject: sc1200!


> Hello,
>
>          I want to use LinuxBIOS for my SC1200. I dont know where to start
> and how to start? If I have to build for sc1200, can I use the same build
> instructions for the sis motherboard? Plz help me!
>
> _________________________________________________________________
> Gift yourself a holiday. Treat your family like royalty.
> http://www.flexihols.com/2003/index.php
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>
>



From Phreak_Show at gmx.de  Wed Jun 18 08:15:01 2003
From: Phreak_Show at gmx.de (Stefan)
Date: Wed Jun 18 08:15:01 2003
Subject: Gigabyte GA-7DXR
Message-ID: <3EF0590D.90907@gmx.de>

Hi there, does anyone know if this LinuxBIOS works on my GA-7DXR from 
Gigabyte?



From rminnich at lanl.gov  Wed Jun 18 08:33:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 18 08:33:00 2003
Subject: Gigabyte GA-7DXR
In-Reply-To: <3EF0590D.90907@gmx.de>
Message-ID: <Pine.LNX.4.44.0306180638090.7756-100000@maxroach.lanl.gov>

lspci first :-0

lspci
lspci -v

ron



From adam at cfar.umd.edu  Wed Jun 18 11:02:01 2003
From: adam at cfar.umd.edu (Adam Sulmicki)
Date: Wed Jun 18 11:02:01 2003
Subject: USENIX [was : Re: AMD SC520]
In-Reply-To: <20030616093813.O86593-100000@www.missl.cs.umd.edu>
Message-ID: <20030618111016.L98692-100000@www.missl.cs.umd.edu>

> > > I'm starting a port. Anyone with info on this part that could be helpful
> > > let me know.
> > >
> > > I'm doing this on my own time to help support: http://psas.pdx.edu.
> >
> > Are they building their own private rockets ?
>
> Yeah. They were demoing all this during USENIX 03. Pretty damn cool.
> And they try to use Open Source whenver possible.
>
> I hope to post some pictures from USENIX soon.

You can find the pictures at http://www.eax.com

You can find there also our paper.

I would like to use this opportunity to express thanks to all LinuxBIOS
developers for this wondefull product without which our work wouldn't be
possible.

-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers



From tcook at promicrosystems.com  Wed Jun 18 13:51:00 2003
From: tcook at promicrosystems.com (tcook)
Date: Wed Jun 18 13:51:00 2003
Subject: super micro P4DPR-IGM 
Message-ID: <001c01c335c2$b5f648d0$1901a8c0@tcook>

I know there is a port for the super micro  P4DPE but I need to know if
there is a port for the P4DPR-IGM mb on the e7500 chipset 
And where I can find it.
 
 
 Tim Cook
 
 ""A man is not idle because he is absorbed in thought. 
There is a visible labor and there is an invisible labor ""
"Victor Hugo <http://www.promicrosystems.com/> "
 
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From rminnich at lanl.gov  Wed Jun 18 16:18:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 18 16:18:00 2003
Subject: super micro P4DPR-IGM 
In-Reply-To: <001c01c335c2$b5f648d0$1901a8c0@tcook>
Message-ID: <Pine.LNX.4.44.0306181423410.2803-100000@maxroach.lanl.gov>

On Wed, 18 Jun 2003, tcook wrote:

> I know there is a port for the super micro  P4DPE but I need to know if
> there is a port for the P4DPR-IGM mb on the e7500 chipset 
> And where I can find it.

Let me look when I get home, and get back to me if I don't respond, but I 
think out "p4dpr" boards are actually P4DPR-IGM

ron



From Phreak_Show at gmx.de  Thu Jun 19 06:56:01 2003
From: Phreak_Show at gmx.de (Stefan)
Date: Thu Jun 19 06:56:01 2003
Subject: Gigabyte GA-7DXR
In-Reply-To: <Pine.LNX.4.44.0306180638090.7756-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306180638090.7756-100000@maxroach.lanl.gov>
Message-ID: <3EF1982A.9080902@gmx.de>

What does this mean, I'm a newbie ;)


ron minnich wrote:

>lspci first :-0
>
>lspci
>lspci -v
>
>ron
>
>
>  
>




From stepan at suse.de  Thu Jun 19 07:14:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jun 19 07:14:00 2003
Subject: Gigabyte GA-7DXR
In-Reply-To: <3EF1982A.9080902@gmx.de>; from Phreak_Show@gmx.de on Thu, Jun 19, 2003 at 01:02:02PM +0200
References: <Pine.LNX.4.44.0306180638090.7756-100000@maxroach.lanl.gov> <3EF1982A.9080902@gmx.de>
Message-ID: <20030619132005.A23590@suse.de>

* Stefan <Phreak_Show at gmx.de> [030619 13:02]:
> What does this mean, I'm a newbie ;)
> 
> >lspci
> >lspci -v

You are supposed to execute these commands and send the output to the
list. It lists all PCI devices in your system, making sure that the
north and southbridge you have is supported _before_ you flash
something. 
If you never heard of lspci, take some time for LinuxBIOS, it'll
probably need it.

Stefan(, too)

  
-- 
Architecture Team
    SuSE Linux AG


From dkotian3 at vsnl.net  Thu Jun 19 07:15:01 2003
From: dkotian3 at vsnl.net (dkotian3 at vsnl.net)
Date: Thu Jun 19 07:15:01 2003
Subject: Gigabyte GA-7DXR
Message-ID: <20030619115415.C3C7F4FE39@bom6.vsnl.net.in>

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From rezso at rdsor.ro  Thu Jun 19 07:21:01 2003
From: rezso at rdsor.ro (Balint Cristian)
Date: Thu Jun 19 07:21:01 2003
Subject: Gigabyte GA-7DXR
In-Reply-To: <3EF1982A.9080902@gmx.de>
References: <Pine.LNX.4.44.0306180638090.7756-100000@maxroach.lanl.gov> <3EF1982A.9080902@gmx.de>
Message-ID: <200306191427.08098.rezso@rdsor.ro>

On Thursday 19 June 2003 14:02, Stefan wrote:
> What does this mean, I'm a newbie ;)

:)))

No pleast type in your linux system:
lspci
and then:
lspci -v

And copy paste the output of these 2 command and send it here to
analyse exact ly what chipset have you MB !!

	We dont know what chipsed has GA-7DXR called MB has until
you dont tell us !!


Cristian

>
> ron minnich wrote:
> >lspci first :-0
> >
> >lspci
> >lspci -v
> >
> >ron
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From Antony at Soft-Solutions.co.uk  Thu Jun 19 07:24:00 2003
From: Antony at Soft-Solutions.co.uk (Antony Stone)
Date: Thu Jun 19 07:24:00 2003
Subject: Gigabyte GA-7DXR
In-Reply-To: <3EF1982A.9080902@gmx.de>
References: <Pine.LNX.4.44.0306180638090.7756-100000@maxroach.lanl.gov> <3EF1982A.9080902@gmx.de>
Message-ID: <200306191129.h5JBTwD18392@onyx.rockstone.co.uk>

On Thursday 19 June 2003 12:02 pm, Stefan wrote:

> What does this mean, I'm a newbie ;)

It means you should type the two commands "lspci" and "lspci -v" on the 
machine you would like to run LinuxBIOS on, and then post the results back to 
this list so we can see what bits are on the motherboard you want to use.

Antony.

> ron minnich wrote:
> >lspci first :-0
> >
> >lspci
> >lspci -v
> >
> >ron
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 

Never write it in Perl if you can do it in Awk.
Never do it in Awk if sed can handle it.
Never use sed when tr can do the job.
Never invoke tr when cat is sufficient.
Avoid using cat whenever possible.


From rminnich at lanl.gov  Thu Jun 19 15:41:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 19 15:41:01 2003
Subject: Gigabyte GA-7DXR
In-Reply-To: <3EF1982A.9080902@gmx.de>
Message-ID: <Pine.LNX.4.44.0306191346230.2272-100000@maxroach.lanl.gov>

On Thu, 19 Jun 2003, Stefan wrote:

> What does this mean, I'm a newbie ;)

these are linux commands.

man lspci

ron



From rsmith at bitworks.com  Thu Jun 19 16:23:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Thu Jun 19 16:23:01 2003
Subject: Mouse function
In-Reply-To: <200306191427.08098.rezso@rdsor.ro>
References: <Pine.LNX.4.44.0306180638090.7756-100000@maxroach.lanl.gov> <3EF1982A.9080902@gmx.de> <200306191427.08098.rezso@rdsor.ro>
Message-ID: <3EF21CD9.9060907@bitworks.com>

I can't seem to get my freakin PS/2 mouse to work.

The mouse is attached to the NSC pc87351 superIO and as far as I can 
tell is fully enabled.  But when I run gpm I never see any activity on 
MClk and MData.   strace reports that gpm alarms out on a read waiting 
for the mouse to respond to the detect command.

Keyboard works so I know ports 60 and 64 are up and working and 
forwarded to the ISA bus.

I see reference to a enable auxilliary device command (0xa8) for the 
KBC.  Anyone know if there is some init sequence that you have to send 
the KBC to make the aux device go and actually toggle MClk and MDat?

I tried sending a 0xa8 but it didn't seem to make a difference.

-- 
Richard A. Smith
rsmith at bitworks.com




From rminnich at lanl.gov  Thu Jun 19 16:40:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 19 16:40:01 2003
Subject: Welcome to Stefan Reinauer
Message-ID: <Pine.LNX.4.44.0306191444540.2272-100000@maxroach.lanl.gov>

The newest LinuxBIOS developer is Stefan Reinauer, who has been a 
supporter for years and is now heavily involved in K8 development (along, 
of course, with Eric Biederman). 

Welcome, Stefan!

thanks

ron




From hansolofalcon at worldnet.att.net  Thu Jun 19 18:30:01 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Thu Jun 19 18:30:01 2003
Subject: Welcome to Stefan Reinauer
In-Reply-To: <Pine.LNX.4.44.0306191444540.2272-100000@maxroach.lanl.gov>
Message-ID: <000601c336b3$42de0bc0$239efea9@who5>

Hello again from Gregg C Levine
Then he, and Eric, (Who I've met.), have my blessings. And yes,
Welcome Stefan.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of ron minnich
> Sent: Thursday, June 19, 2003 4:46 PM
> To: linuxbios at clustermatic.org
> Cc: Stefan Reinauer
> Subject: Welcome to Stefan Reinauer
> 
> 
> The newest LinuxBIOS developer is Stefan Reinauer, who has been a
> supporter for years and is now heavily involved in K8 development
(along,
> of course, with Eric Biederman).
> 
> Welcome, Stefan!
> 
> thanks
> 
> ron
> 
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From YhLu at tyan.com  Thu Jun 19 18:53:01 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jun 19 18:53:01 2003
Subject: new config language.
Message-ID: <3174569B9743D511922F00A0C943142302C43E25@TYANWEB>

Ron,

I have tried the romimage in AMD solo 7 MB, and the LinuxBIOS can boot until
Etherboot. So the ROM image I built should be OK.

The Tyan s2880 has two CPUs and supported dual channel DDR. The Opteron CPU
is for Server/workstation and The cpu for AMD solo is for desktop
(Crawhammer).

Any advise.

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?6?9? 22:17
???: YhLu
??: linuxbios at clustermatic.org
??: Re: ??: ??: new config language.

On Mon, 9 Jun 2003, YhLu wrote:

> Is there any MB can boot to execute into LinuxBIOS after copying it to
> RAM?

yes, many.

> 
> The _RAMBASE WE use for E7501 is 0x8000, and the FreeBIOS2 default for K8
is
> 0x4000. How should I set the value to make the LinuxBIOS can boot into
> hardwaremain.c.
> It seems MB only execute the auto.c and crt0.base and can not jump to the
> right address.

I'm not sure what's wrong here. You may have to start checking the object 
code to see if it is correct.

For what it is worth the new config tool is almost working ... just trying 
to get the sizing of the romimage correct.

Hopefully I can start paying attention to linuxbios itself soon, now that 
I can bulid it.

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From ebiederman at lnxi.com  Thu Jun 19 23:09:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Jun 19 23:09:00 2003
Subject: new config language.
In-Reply-To: <3174569B9743D511922F00A0C943142302C43E25@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43E25@TYANWEB>
Message-ID: <m3wufhbfrh.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Ron,
> 
> I have tried the romimage in AMD solo 7 MB, and the LinuxBIOS can boot until
> Etherboot. So the ROM image I built should be OK.

There are a lot of hard codes that need to removed, in that code.
It is only appropriate for developers wanting to improve it.  It
is not appropriate for general purpose use yet.
 
> The Tyan s2880 has two CPUs and supported dual channel DDR. The Opteron CPU
> is for Server/workstation and The cpu for AMD solo is for desktop
> (Crawhammer).
> 
> Any advise.
Read the fine cpu documentation.

Beyond that if you get to the point where you are actively working
and contributing this I would be happy to synchronize with you.
Until that point all I can say is that the code is coming along,
but the code is quite a ways from being general purpose yet.

Eric



From YhLu at tyan.com  Thu Jun 19 23:16:00 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jun 19 23:16:00 2003
Subject: new config language.
Message-ID: <3174569B9743D511922F00A0C943142302C43E5F@TYANWEB>

Eric,

Yes, I'm reading the CPU documentation now.

I found the code in northbridge/amd/amdk8 seems only support single node
now. So step you will add SMP support via MACRO define. ( CONFIG_SMP and
CPU_NUM ). Is it right?

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?6?19? 20:16
???: YhLu
??: ron minnich; linuxbios at clustermatic.org
??: Re: new config language.

YhLu <YhLu at tyan.com> writes:

> Ron,
> 
> I have tried the romimage in AMD solo 7 MB, and the LinuxBIOS can boot
until
> Etherboot. So the ROM image I built should be OK.

There are a lot of hard codes that need to removed, in that code.
It is only appropriate for developers wanting to improve it.  It
is not appropriate for general purpose use yet.
 
> The Tyan s2880 has two CPUs and supported dual channel DDR. The Opteron
CPU
> is for Server/workstation and The cpu for AMD solo is for desktop
> (Crawhammer).
> 
> Any advise.
Read the fine cpu documentation.

Beyond that if you get to the point where you are actively working
and contributing this I would be happy to synchronize with you.
Until that point all I can say is that the code is coming along,
but the code is quite a ways from being general purpose yet.

Eric


From ebiederman at lnxi.com  Fri Jun 20 05:04:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 20 05:04:01 2003
Subject: new config language.
In-Reply-To: <3174569B9743D511922F00A0C943142302C43E5F@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43E5F@TYANWEB>
Message-ID: <m3y8zxxgd9.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Yes, I'm reading the CPU documentation now.
> 
> I found the code in northbridge/amd/amdk8 seems only support single node
> now. So step you will add SMP support via MACRO define. ( CONFIG_SMP and
> CPU_NUM ). Is it right?

Something like that.  

Picking what to do next really depends on which pieces make sense,
for the individual developer.

An added complication is that we are busily performing some pretty
significant cleanups in the code base.  And so sometimes we get some
pretty significant changes going on.

Eric



From rminnich at lanl.gov  Fri Jun 20 09:50:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 09:50:00 2003
Subject: Mouse function
In-Reply-To: <3EF21CD9.9060907@bitworks.com>
Message-ID: <Pine.LNX.4.44.0306200755520.9453-100000@maxroach.lanl.gov>

richard, is it time for a user-mode program or hacks to gpm to see what's 
up? 

I'm not checked out on this particular problem, most of my nodes don't do 
mice. :-(

ron



From rminnich at lanl.gov  Fri Jun 20 10:34:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 10:34:01 2003
Subject: power connectors for mainboards
Message-ID: <Pine.LNX.4.44.0306200839320.9687-100000@maxroach.lanl.gov>

I have four K7SEMs which I would like to run from one PC power supply. 

Does anyone know if there are off-the-shelf cables available to do this 
type of thing? Essentially a "Y" connector for the mainboard power 
connector.

ron



From vincent at ulyssis.org  Fri Jun 20 10:41:01 2003
From: vincent at ulyssis.org (Vincent Touquet)
Date: Fri Jun 20 10:41:01 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306200839320.9687-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306200839320.9687-100000@maxroach.lanl.gov>
Message-ID: <20030620144711.GA24530@lea.ulyssis.org>

On Fri, Jun 20, 2003 at 08:40:18AM -0600, ron minnich wrote:
>
>I have four K7SEMs which I would like to run from one PC power supply. 
>Does anyone know if there are off-the-shelf cables available to do this 
>type of thing? Essentially a "Y" connector for the mainboard power 
>connector.

I don't think the power supply can handle four  K7SEMs,
they are designed for one ...

I would advise against doing this.
I wouldn't know where to get an Y connector like that.

v


From rminnich at lanl.gov  Fri Jun 20 11:00:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 11:00:01 2003
Subject: power connectors for mainboards
In-Reply-To: <20030620144711.GA24530@lea.ulyssis.org>
Message-ID: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>

On Fri, 20 Jun 2003, Vincent Touquet wrote:

> I would advise against doing this.
> I wouldn't know where to get an Y connector like that.

ok, that's good to know. 

Now I need to find four cheap, compact power supplies :-)

no disk in this system, no cdrom, no nothing save for motherboards. I'm 
looking for small, cheap, good supplies. Probably don't exist but anybody 
know for sure?

ron



From vincent at ulyssis.org  Fri Jun 20 11:04:01 2003
From: vincent at ulyssis.org (Vincent Touquet)
Date: Fri Jun 20 11:04:01 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
References: <20030620144711.GA24530@lea.ulyssis.org> <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
Message-ID: <20030620150958.GB25468@lea.ulyssis.org>

On Fri, Jun 20, 2003 at 09:06:07AM -0600, ron minnich wrote:
>ok, that's good to know. 
>Now I need to find four cheap, compact power supplies :-)
:)

>no disk in this system, no cdrom, no nothing save for motherboards. I'm 
>looking for small, cheap, good supplies. Probably don't exist but anybody 
>know for sure?
I don't know for sure what the requirements are for the K7SEM,
but I think any 350W supply would do. Don't think you can go
any lower than that (if it were an MP board, you would need
a 450 W supply).

Shop around :)

v


From vincent at ulyssis.org  Fri Jun 20 11:06:01 2003
From: vincent at ulyssis.org (Vincent Touquet)
Date: Fri Jun 20 11:06:01 2003
Subject: power connectors for mainboards
In-Reply-To: <20030620150958.GB25468@lea.ulyssis.org>
References: <20030620144711.GA24530@lea.ulyssis.org> <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov> <20030620150958.GB25468@lea.ulyssis.org>
Message-ID: <20030620151221.GC25468@lea.ulyssis.org>

On Fri, Jun 20, 2003 at 05:10:01PM +0200, Vincent Touquet wrote:
>>looking for small, cheap, good supplies. Probably don't exist but anybody 
>>know for sure?
>but I think any 350W supply would do. Don't think you can go

Any is an over statement of course, make sure the connectors match :)
Sometimes the connectors even change during the life cycle of one
and the same boardname.

v


From bari at onelabs.com  Fri Jun 20 11:33:00 2003
From: bari at onelabs.com (Bari Ari)
Date: Fri Jun 20 11:33:00 2003
Subject: power connectors for mainboards
References: <Pine.LNX.4.44.0306200839320.9687-100000@maxroach.lanl.gov>
Message-ID: <3EF32B15.8060504@onelabs.com>

ron minnich wrote:

>I have four K7SEMs which I would like to run from one PC power supply. 
>
>Does anyone know if there are off-the-shelf cables available to do this 
>type of thing? Essentially a "Y" connector for the mainboard power 
>connector.
>
>  
>
I've never seen any for ATX power supplies since you'd have to deal with 
a couple control signals.

ATX supply has a PWR_OK ouput and also PS_ON# input.

"PWR_OK is a ?power good? signal. It should be asserted high by the 
power supply to
indicate that the +12 VDC, +5VDC, and +3.3VDC outputs are above the 
undervoltage
thresholds. Conversely, PWR_OK should be de-asserted
to a low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output voltages
falls below its undervoltage threshold, or when mains power has been 
removed for a time
sufficiently long such that power supply operation cannot be guaranteed 
beyond the power-down
warning time."

"PS_ON# is an active-low, TTL-compatible signal that allows a 
motherboard to remotely
control the power supply in conjunction with features such as soft 
on/off, Wake on LAN ? ,
or wake-on-modem. When PS_ON# is pulled to TTL low, the power supply 
should turn on
the five main DC output rails: +12VDC, +5VDC, +3.3VDC, -5VDC, and 
-12VDC. When
PS_ON# is pulled to TTL high or open-circuited, the DC output rails 
should not deliver
current and should be held at zero potential with respect to ground. 
PS_ON# has no effect
on the +5VSB output, which is always enabled whenever the AC power is 
present.
The power supply shall provide an internal pull-up to TTL high. The 
power supply shall
also provide debounce circuitry on PS_ON# to prevent it from oscillating 
on/off at startup
when activated by a mechanical switch. The DC output enable circuitry 
must be SELV-compliant.
The power supply shall not latch into a shutdown state when PS_ON# is 
driven active by
pulses between 10ms to 100ms during the decay of the power rails."

PS_ON# could just be pulled low with a jumper or switch to ground if you 
didn't care about power control by the motherboard since the ATX supply 
would be always on.

-Bari




From steve at nexpath.com  Fri Jun 20 11:47:01 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Fri Jun 20 11:47:01 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
Message-ID: <3EF32FC8.1080604@nexpath.com>

ron minnich wrote:

> Now I need to find four cheap, compact power supplies :-)
> 

Maybe buy.com:

http://www.buy.com/retail/product.asp?sku=10254765&hdwt=0&loc=101

I would carefully check the mobo current requirements; you might get 
away with one of the tiny ones:

http://www.buy.com/retail/product.asp?sku=10272555&hdwt=0&loc=101

But it would be necessary to compare specs, startech web site says
DC OUTPUT:
     * +3.3(8A)
     * +5V(14A)
     * +12V(5.5A)
     * -12V(0.3A)
     * +5VSB(1A)

But the bottom line sometimes is you have to try it, since surge 
currents on startup can cause the supply to trip even though it can 
handle the steady load.

-Steve



From adam at cfar.umd.edu  Fri Jun 20 11:51:01 2003
From: adam at cfar.umd.edu (Adam Sulmicki)
Date: Fri Jun 20 11:51:01 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
Message-ID: <20030620120058.G7408-100000@www.missl.cs.umd.edu>

> > I would advise against doing this.
> > I wouldn't know where to get an Y connector like that.
>
> ok, that's good to know.
>
> Now I need to find four cheap, compact power supplies :-)
>
> no disk in this system, no cdrom, no nothing save for motherboards. I'm
> looking for small, cheap, good supplies. Probably don't exist but anybody
> know for sure?

Maybe try one of those 1U power supplies.
Similar to the one I had with me during USENIX
Something like:

	http://www.gtweb.net/ps-1u.html

and the power supply in action:

	http://www.eax.com/usenix03/image/101_0138.JPG

	http://www.eax.com/usenix03/

It should be fairly easy to stack 4 of them side by side and tie together.

-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers



From rsmith at bitworks.com  Fri Jun 20 11:54:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Fri Jun 20 11:54:00 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
Message-ID: <3EF32F62.8070002@bitworks.com>

ron minnich wrote:

>>I would advise against doing this.
>>I wouldn't know where to get an Y connector like that.

Ditto.  Just a couple of days ago we had this new nifty 2Ghz Athlon 
motherboard that wouldn't boot beacuse the 350W powersupply we had 
connected to it didn't have enough juice on the 3.3V rail.  AMD white 
paper claims that the power supply must be able to provide peak CPU draw 
  for 10 seconds at boot.  These new processors need lots of juice when 
they startup.  You would need a pretty hoss supply to boot 4 cpus at once.

> Now I need to find four cheap, compact power supplies :-)
> no disk in this system, no cdrom, no nothing save for motherboards. I'm 

What CPU is it and how much current does it need on the rails?  You 
might be able to get by with some of those Mini-ATX supplys.  They are 
small and cheap but pretty thin on wattage.

-- 
Richard A. Smith
rsmith at bitworks.com




From bgr at gw.linespeed.net  Fri Jun 20 11:57:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Fri Jun 20 11:57:01 2003
Subject: power connectors for mainboards
In-Reply-To: <20030620120058.G7408-100000@www.missl.cs.umd.edu>
References: <20030620120058.G7408-100000@www.missl.cs.umd.edu>
Message-ID: <Pine.LNX.4.53.0306201059390.24123@gw.linespeed.net>

Ron,

How about 4 of these...

http://www.seanm.ca/eden/psu.html

Or if that's not enough power for the processor, sparkle (great name)
makes some 150W powersupplies which are 1U and smaller than average 1U
power supplies.

FSP150-50PL is the model I have been using for pIII rackmount systems.

Their website is www.sparklepower.com.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Fri, 20 Jun 2003, Adam Sulmicki wrote:

> > > I would advise against doing this.
> > > I wouldn't know where to get an Y connector like that.
> >
> > ok, that's good to know.
> >
> > Now I need to find four cheap, compact power supplies :-)
> >
> > no disk in this system, no cdrom, no nothing save for motherboards. I'm
> > looking for small, cheap, good supplies. Probably don't exist but anybody
> > know for sure?
>
> Maybe try one of those 1U power supplies.
> Similar to the one I had with me during USENIX
> Something like:
>
> 	http://www.gtweb.net/ps-1u.html
>
> and the power supply in action:
>
> 	http://www.eax.com/usenix03/image/101_0138.JPG
>
> 	http://www.eax.com/usenix03/
>
> It should be fairly easy to stack 4 of them side by side and tie together.
>
> --
> Adam Sulmicki
> http://www.eax.com 	The Supreme Headquarters of the 32 bit registers
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From rminnich at lanl.gov  Fri Jun 20 11:59:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 11:59:00 2003
Subject: power connectors for mainboards
In-Reply-To: <20030620120058.G7408-100000@www.missl.cs.umd.edu>
Message-ID: <Pine.LNX.4.44.0306201005080.9687-100000@maxroach.lanl.gov>

I need something that comes in at ca. $25 ...

ron



From bari at onelabs.com  Fri Jun 20 12:00:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Fri Jun 20 12:00:01 2003
Subject: power connectors for mainboards
References: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
Message-ID: <3EF33134.8090103@onelabs.com>

ron minnich wrote:

>Now I need to find four cheap, compact power supplies :-)
>
>no disk in this system, no cdrom, no nothing save for motherboards. I'm 
>looking for small, cheap, good supplies. Probably don't exist but anybody 
>know for sure?
>  
>
Take a look at

http://www.sparklepower.com/

They tend to run in the $10 -$15 ea range.

-Bari




From rminnich at lanl.gov  Fri Jun 20 12:52:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 12:52:00 2003
Subject: power connectors for mainboards
In-Reply-To: <3EF32F62.8070002@bitworks.com>
Message-ID: <Pine.LNX.4.44.0306201058000.9687-100000@maxroach.lanl.gov>

On Fri, 20 Jun 2003, Richard Smith wrote:

> What CPU is it and how much current does it need on the rails?  

Duron 1300

The one supply I found from Sparkle was $155!

ron



From agnew at cs.umd.edu  Fri Jun 20 13:06:00 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Fri Jun 20 13:06:00 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306201058000.9687-100000@maxroach.lanl.gov>
Message-ID: <20030620131417.E9428-100000@www.missl.cs.umd.edu>

These appear to be some small, dirt cheap supplies. Not 100% sure a
FlexATX power supply uses the same standard ATX power connector, but i
suspect it does.

http://www.aaronix.com/catalog/default.php/cPath/131_132


On Fri, 20 Jun 2003, ron minnich wrote:

> On Fri, 20 Jun 2003, Richard Smith wrote:
>
> > What CPU is it and how much current does it need on the rails?
>
> Duron 1300
>
> The one supply I found from Sparkle was $155!
>
> ron
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>



From rminnich at lanl.gov  Fri Jun 20 13:15:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 13:15:01 2003
Subject: power connectors for mainboards
In-Reply-To: <000501c3374c$c4bfc450$6414a8c0@office.linwave.co.uk>
Message-ID: <Pine.LNX.4.44.0306201120040.9687-100000@maxroach.lanl.gov>

Thanks Alex. 

I am trying to find a way to build these low-cost for educational and 
tutorial uses. Anything custom is pretty much out. But thanks for the 
idea.

ron



From YhLu at tyan.com  Fri Jun 20 14:40:01 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jun 20 14:40:01 2003
Subject: =?gb2312?B?tPC4tDogbmV3IGNvbmZpZyBsYW5ndWFnZS4=?=
Message-ID: <3174569B9743D511922F00A0C943142302C43EAC@TYANWEB>

Eric,

So If I want to SMP support, I have added the corresponding code by myself
at this time.

Regards

Yinghai Lu


-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?6?20? 2:12
???: YhLu
??: ron minnich; linuxbios at clustermatic.org
??: Re: new config language.

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Yes, I'm reading the CPU documentation now.
> 
> I found the code in northbridge/amd/amdk8 seems only support single node
> now. So step you will add SMP support via MACRO define. ( CONFIG_SMP and
> CPU_NUM ). Is it right?

Something like that.  

Picking what to do next really depends on which pieces make sense,
for the individual developer.

An added complication is that we are busily performing some pretty
significant cleanups in the code base.  And so sometimes we get some
pretty significant changes going on.

Eric

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From bari at onelabs.com  Fri Jun 20 14:41:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Fri Jun 20 14:41:01 2003
Subject: power connectors for mainboards
References: <Pine.LNX.4.44.0306201058000.9687-100000@maxroach.lanl.gov>
Message-ID: <3EF35724.3040707@onelabs.com>

ron minnich wrote:

>The one supply I found from Sparkle was $155!
>
>  
>
$9 - $16  350W - 550W
http://www.str8buy.com/powersupplyups.html

250W Sparkle  $11, 350W Powmax $15
http://3btech.net/cases2.html

-Bari






From rsmith at bitworks.com  Fri Jun 20 14:51:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Fri Jun 20 14:51:01 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306201058000.9687-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306201058000.9687-100000@maxroach.lanl.gov>
Message-ID: <3EF35892.6000800@bitworks.com>

ron minnich wrote:

>>What CPU is it and how much current does it need on the rails?  

> Duron 1300

Looks like a 1300 needs a little over 60 watts peak.  So if one of those 
  70 watt micro ATX supplys can do 19 amps on the 3.3V rail it might 
work.  Depnds on how much juice the northbridge needs.


-- 
Richard A. Smith
rsmith at bitworks.com




From Phreak_Show at gmx.de  Fri Jun 20 15:15:01 2003
From: Phreak_Show at gmx.de (Stefan)
Date: Fri Jun 20 15:15:01 2003
Subject: Gigabyte GA-7DXR
In-Reply-To: <200306191129.h5JBTwD18392@onyx.rockstone.co.uk>
References: <Pine.LNX.4.44.0306180638090.7756-100000@maxroach.lanl.gov> <3EF1982A.9080902@gmx.de> <200306191129.h5JBTwD18392@onyx.rockstone.co.uk>
Message-ID: <3EF35E93.1030709@gmx.de>

Antony Stone wrote:

>On Thursday 19 June 2003 12:02 pm, Stefan wrote:
>
>  
>
>>What does this mean, I'm a newbie ;)
>>    
>>
>
>It means you should type the two commands "lspci" and "lspci -v" on the 
>machine you would like to run LinuxBIOS on, and then post the results back to 
>this list so we can see what bits are on the motherboard you want to use.
>
>Antony.
>  
>

Hi!

I wrote lspci in the console, here are the results:

linux:~ # lspci 
00:00.0 Host bridge: Advanced Micro Devices [AMD] AMD-760 [Irongate] 
System Controller (rev 13) 
00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-760 [Irongate] AGP 
Bridge 
00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] 
(rev 40) 
00:07.1 IDE interface: VIA Technologies, Inc. Bus Master IDE (rev 06) 
00:07.2 USB Controller: VIA Technologies, Inc. UHCI USB (rev 1a) 
00:07.3 USB Controller: VIA Technologies, Inc. UHCI USB (rev 1a) 
00:07.4 SMBus: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 
40) 
00:0a.0 Network controller: AVM Audiovisuelles MKTG & Computer System GmbH 
A1 ISDN [Fritz] (rev 02) 
00:0c.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 
07) 
00:0c.1 Input device controller: Creative Labs SB Live! (rev 07) 
00:0d.0 Multimedia video controller: Brooktree Corporation Bt878 (rev 02) 
00:0d.1 Multimedia controller: Brooktree Corporation Bt878 (rev 02) 
00:0f.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139 (rev 
10) 
00:10.0 RAID bus controller: Promise Technology, Inc. 20265 (rev 02) 
01:05.0 VGA compatible controller: nVidia Corporation: Unknown device 0202 
(rev a3) 
linux:~ # lspci -v 
00:00.0 Host bridge: Advanced Micro Devices [AMD] AMD-760 [Irongate] 
System Controller (rev 13) 
        Flags: bus master, medium devsel, latency 32 
        Memory at c0000000 (32-bit, prefetchable) [size=256M] 
        Memory at db023000 (32-bit, prefetchable) [size=4K] 
        I/O ports at 9000 [disabled] [size=4] 
        Capabilities: [a0] AGP version 2.0 
 
00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-760 [Irongate] AGP 
Bridge (prog-if 00 [Normal decode]) 
        Flags: bus master, 66Mhz, medium devsel, latency 32 
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 
        Memory behind bridge: d8000000-d9ffffff 
        Prefetchable memory behind bridge: d0000000-d7ffffff 
 
00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] 
(rev 40) 
        Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge 
        Flags: bus master, stepping, medium devsel, latency 0 
        Capabilities: [c0] Power Management version 2 
 
00:07.1 IDE interface: VIA Technologies, Inc. Bus Master IDE (rev 06) 
(prog-if 8a [Master SecP PriP]) 
        Subsystem: VIA Technologies, Inc. Bus Master IDE 
        Flags: bus master, medium devsel, latency 32 
        I/O ports at 9400 [size=16] 
        Capabilities: [c0] Power Management version 2 
 
00:07.2 USB Controller: VIA Technologies, Inc. UHCI USB (rev 1a) (prog-if 
00 [UHCI]) 
        Subsystem: Unknown device 0925:1234 
        Flags: bus master, medium devsel, latency 32, IRQ 11 
        I/O ports at 9800 [size=32] 
        Capabilities: [80] Power Management version 2 
 
00:07.3 USB Controller: VIA Technologies, Inc. UHCI USB (rev 1a) (prog-if 
00 [UHCI]) 
        Subsystem: Unknown device 0925:1234 
        Flags: bus master, medium devsel, latency 32, IRQ 11 
        I/O ports at 9c00 [size=32] 
        Capabilities: [80] Power Management version 2 
 
00:07.4 SMBus: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 
40) 
        Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] 
        Flags: medium devsel, IRQ 9 
        Capabilities: [68] Power Management version 2 
 
00:0a.0 Network controller: AVM Audiovisuelles MKTG & Computer System GmbH 
A1 ISDN [Fritz] (rev 02) 
        Subsystem: AVM Audiovisuelles MKTG & Computer System GmbH 
FRITZ!Card ISDN Controller 
        Flags: medium devsel, IRQ 10 
        Memory at db024000 (32-bit, non-prefetchable) [size=32] 
        I/O ports at a000 [size=32] 
 
00:0c.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 
07) 
        Subsystem: Creative Labs: Unknown device 8064 
        Flags: bus master, medium devsel, latency 32, IRQ 5 
        I/O ports at a400 [size=32] 
        Capabilities: [dc] Power Management version 1 
 
00:0c.1 Input device controller: Creative Labs SB Live! (rev 07) 
        Subsystem: Creative Labs Gameport Joystick 
        Flags: bus master, medium devsel, latency 32 
        I/O ports at a800 [size=8] 
        Capabilities: [dc] Power Management version 1 
 
00:0d.0 Multimedia video controller: Brooktree Corporation Bt878 (rev 02) 
        Subsystem: Hauppauge computer works Inc. WinTV/GO 
        Flags: bus master, medium devsel, latency 32, IRQ 7 
        Memory at db020000 (32-bit, prefetchable) [size=4K] 
 
00:0d.1 Multimedia controller: Brooktree Corporation Bt878 (rev 02) 
        Subsystem: Hauppauge computer works Inc. WinTV/GO 
        Flags: bus master, medium devsel, latency 32, IRQ 7 
        Memory at db021000 (32-bit, prefetchable) [size=4K] 
 
00:0f.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139 (rev 
10) 
        Subsystem: Realtek Semiconductor Co., Ltd. RT8139 
        Flags: bus master, medium devsel, latency 32, IRQ 11 
        I/O ports at ac00 [size=256] 
        Memory at db022000 (32-bit, non-prefetchable) [size=256] 
        Capabilities: [50] Power Management version 2 
 
00:10.0 RAID bus controller: Promise Technology, Inc. 20265 (rev 02) 
        Subsystem: Promise Technology, Inc. Ultra100 
        Flags: bus master, medium devsel, latency 32, IRQ 11 
        I/O ports at b000 [size=8] 
        I/O ports at b400 [size=4] 
        I/O ports at b800 [size=8] 
        I/O ports at bc00 [size=4] 
        I/O ports at c000 [size=64] 
        Memory at db000000 (32-bit, non-prefetchable) [size=128K] 
        Expansion ROM at <unassigned> [disabled] [size=128K] 
        Capabilities: [58] Power Management version 1 
 
01:05.0 VGA compatible controller: nVidia Corporation: Unknown device 0202 
(rev a3) (prog-if 00 [VGA]) 
        Subsystem: Micro-star International Co Ltd: Unknown device 5305 
        Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 5 
        Memory at d8000000 (32-bit, non-prefetchable) [size=16M] 
        Memory at d0000000 (32-bit, prefetchable) [size=64M] 
        Memory at d4000000 (32-bit, prefetchable) [size=512K] 
        Expansion ROM at <unassigned> [disabled] [size=64K] 
        Capabilities: [60] Power Management version 2 
        Capabilities: [44] AGP version 2.0 


thx & greetings, Stefan
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From ebiederman at lnxi.com  Fri Jun 20 15:18:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 20 15:18:00 2003
Subject: : new config language.
In-Reply-To: <3174569B9743D511922F00A0C943142302C43EAC@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43EAC@TYANWEB>
Message-ID: <m3wufg1rg8.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> So If I want to SMP support, I have added the corresponding code by myself
> at this time.

Or at least work with the others working on it and it can be a cooperative
venture.

Basically it is the nature of open source if something isn't implemented
you can wait or you can write it.

So far what I have seen is a talented user figuring out LinuxBIOS.
I have not seen a developer giving constructive giving constructive
feedback or helping in the development.

My general advise to people who want to just use the Opteron port
is stay away.

For developers the advice is dig in, just be aware everything is
undergoing active development, and there are a lot of pieces
that have been stubbed in but have not been written correctly yet.
SMP support is one of those.

Eric



From YhLu at tyan.com  Fri Jun 20 15:28:01 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jun 20 15:28:01 2003
Subject: =?gb2312?B?tPC4tDogOiBuZXcgY29uZmlnIGxhbmd1YWdlLg==?=
Message-ID: <3174569B9743D511922F00A0C943142302C43EB3@TYANWEB>

Eric,

Thanks for the advice.
I will try to add the SMP support in the northbridge/amd/amdk8 at first.

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?6?20? 12:26
???: YhLu
??: ron minnich; linuxbios at clustermatic.org
??: Re:: new config language.

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> So If I want to SMP support, I have added the corresponding code by myself
> at this time.

Or at least work with the others working on it and it can be a cooperative
venture.

Basically it is the nature of open source if something isn't implemented
you can wait or you can write it.

So far what I have seen is a talented user figuring out LinuxBIOS.
I have not seen a developer giving constructive giving constructive
feedback or helping in the development.

My general advise to people who want to just use the Opteron port
is stay away.

For developers the advice is dig in, just be aware everything is
undergoing active development, and there are a lot of pieces
that have been stubbed in but have not been written correctly yet.
SMP support is one of those.

Eric

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From ebiederman at lnxi.com  Fri Jun 20 16:00:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 20 16:00:01 2003
Subject: new config language.
In-Reply-To: <3174569B9743D511922F00A0C943142302C43EB3@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43EB3@TYANWEB>
Message-ID: <m3n0gcy0kq.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Thanks for the advice.
> I will try to add the SMP support in the northbridge/amd/amdk8 at first.

OK.

There are few levels of this.

Coherent Hypertransport setup.

Mapping resources to their location in the coherent HT domain.

Memory Initialization on secondary cpus.

Starting up the secondary cpus.

Stefan Reinauer is currently working on Coherent Hypertransport initialization.
And there is a hardcoded version of it in northbridge/amd/amdk8/coherent_ht.c

Ron is currently working on getting the new Config language going and probably
in the week or two we will switch over to that.

While not writing memory initialization code I am busily getting the kinks
out of romcc.  I think I have just squashed the last of the bugs in register
allocator.  I thought I was there earlier but a few extra ones cropped up
after I rewrote the algorithms so they ran in a reasonable amount of time.

And since the reasons for my original hesitation are no longer valid I have
implemented goto support in romcc.  I think I am only short enumeration constants,
macros with arguments, and switch statements to have a full implementation of
C.  Admittedly there are some things I cannot support like non const
static variables.  And I still have to fix the limits on variables,
currently I don't limit chars and shorts when stored in larger
integers to just the low bits of the register.

Eric



From fedorowp at earthlink.net  Fri Jun 20 16:21:01 2003
From: fedorowp at earthlink.net (Peter Fedorow)
Date: Fri Jun 20 16:21:01 2003
Subject: power connectors for mainboards
Message-ID: <3EF36DD8.8020404@earthlink.net>

I also have a need for multicomputer (motherboard only) ATX power 
supplies.  Chances are we aren't the only ones, so perhaps it wouldn't 
hurt to suggest such a product to a high quality power supply manufacturer?

My requirements don't necessitate the motherboard being able to turn off 
it's power.

Within the next 6 months I expect to need:

20-60 units : At up to $30 / computer

When I have the budget approved for them I'm thinking of contacting PC 
Power and Cooling to see if they're interested.  Their Turbo-Cool 425 
ATX/ATX12V in 12-31 units is on sale for $125.74 each right now, and its 
rated at:
+5V @ 40A
+12V @ 20A
-5V @ .3A
-12V @ 1A
+3.3v @ 40A
+5VSB @ 2A
(With +5 and +3.3 combined < 300W)

They're very conservatively rated power supplies, and I've never had one 
fail, (even in the most brutal environment I know of on computers schools.)

The only power output limitation I see for the purpose is the 5VSB 
power.  Some NICs (particularly Gigabit, and older 100 Mbs ones,) draw 
more than that for the WOL.  But as the computers are diskless I don't 
have a need for that feature.

How many quad output power supplies do you expect to need?



From YhLu at tyan.com  Fri Jun 20 16:23:01 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jun 20 16:23:01 2003
Subject: new config language.
Message-ID: <3174569B9743D511922F00A0C943142302C43EBD@TYANWEB>

Eric,

Thanks for the info about ROMCC.

The code about mem init in northbridge/amd/amdk8/coherent_ht.c and
northbridge/amd/amdk8/raminit.c had some overlap. On bus 0, dev 0x18 and f
1.

I will add something at northbridge/amd/amdk8/coherent_ht.c

regards

Yinghai Lu
-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?6?20? 13:08
???: YhLu
??: ron minnich; linuxbios at clustermatic.org
??: Re: new config language.

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Thanks for the advice.
> I will try to add the SMP support in the northbridge/amd/amdk8 at first.

OK.

There are few levels of this.

Coherent Hypertransport setup.

Mapping resources to their location in the coherent HT domain.

Memory Initialization on secondary cpus.

Starting up the secondary cpus.

Stefan Reinauer is currently working on Coherent Hypertransport
initialization.
And there is a hardcoded version of it in northbridge/amd/amdk8/coherent_ht.
c

Ron is currently working on getting the new Config language going and
probably
in the week or two we will switch over to that.

While not writing memory initialization code I am busily getting the kinks
out of romcc.  I think I have just squashed the last of the bugs in register
allocator.  I thought I was there earlier but a few extra ones cropped up
after I rewrote the algorithms so they ran in a reasonable amount of time.

And since the reasons for my original hesitation are no longer valid I have
implemented goto support in romcc.  I think I am only short enumeration
constants,
macros with arguments, and switch statements to have a full implementation
of
C.  Admittedly there are some things I cannot support like non const
static variables.  And I still have to fix the limits on variables,
currently I don't limit chars and shorts when stored in larger
integers to just the low bits of the register.

Eric


From rminnich at lanl.gov  Fri Jun 20 16:44:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 16:44:01 2003
Subject: power connectors for mainboards
In-Reply-To: <3EF36DD8.8020404@earthlink.net>
Message-ID: <Pine.LNX.4.44.0306201449410.11515-100000@maxroach.lanl.gov>

On Fri, 20 Jun 2003, Peter Fedorow wrote:

> How many quad output power supplies do you expect to need?

not sure, possibly 30 to start.

ron



From ebiederman at lnxi.com  Fri Jun 20 17:03:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 20 17:03:00 2003
Subject: new config language.
In-Reply-To: <3174569B9743D511922F00A0C943142302C43EBD@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43EBD@TYANWEB>
Message-ID: <m37k7gsbdv.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Thanks for the info about ROMCC.

Welcome.  Given that we are switching to writing all of the code before
memory is initialized knowing how stable  the main tool for doing the job
is useful.  And the list was copied so I don't have to mention it multiple
times.

> The code about mem init in northbridge/amd/amdk8/coherent_ht.c and
> northbridge/amd/amdk8/raminit.c had some overlap. On bus 0, dev 0x18 and f
> 1.

Very peculiar as I don't see that code and the actual coherent HT mapping
is just concerned with function 0.    The mapping which specifies which
resources go where is on function 1.
 
> I will add something at northbridge/amd/amdk8/coherent_ht.c

There are some peculiarities as the code is a first pass at properly 
factoring it.  I think I made a good stab at it but the code still
needs to be generalized.   

An important thing to not is that when the code is done there should
be no board specific hard codes, excpet in code that lives in auto.c

Do you have a 4P case or just 2P?

Eric



From YhLu at tyan.com  Fri Jun 20 17:15:01 2003
From: YhLu at tyan.com (YhLu)
Date: Fri Jun 20 17:15:01 2003
Subject: =?gb2312?B?tPC4tDogbmV3IGNvbmZpZyBsYW5ndWFnZS4=?=
Message-ID: <3174569B9743D511922F00A0C943142302C43ED7@TYANWEB>

Eric,

S2880 is 2P and it is ready.
S4880 is 4P and it is on-going.

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?6?20? 14:11
???: YhLu
??: ron minnich; linuxbios at clustermatic.org
??: Re: new config language.

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Thanks for the info about ROMCC.

Welcome.  Given that we are switching to writing all of the code before
memory is initialized knowing how stable  the main tool for doing the job
is useful.  And the list was copied so I don't have to mention it multiple
times.

> The code about mem init in northbridge/amd/amdk8/coherent_ht.c and
> northbridge/amd/amdk8/raminit.c had some overlap. On bus 0, dev 0x18 and f
> 1.

Very peculiar as I don't see that code and the actual coherent HT mapping
is just concerned with function 0.    The mapping which specifies which
resources go where is on function 1.
 
> I will add something at northbridge/amd/amdk8/coherent_ht.c

There are some peculiarities as the code is a first pass at properly 
factoring it.  I think I made a good stab at it but the code still
needs to be generalized.   

An important thing to not is that when the code is done there should
be no board specific hard codes, excpet in code that lives in auto.c

Do you have a 4P case or just 2P?

Eric


From tcook at promicrosystems.com  Fri Jun 20 17:18:01 2003
From: tcook at promicrosystems.com (tcook)
Date: Fri Jun 20 17:18:01 2003
Subject: newbie question 
Message-ID: <002b01c33772$1936ff60$1901a8c0@tcook>

I am working on the  Super Micro P4DPR-IGM I am trying to get linuxbios
installed 
I run cmos_util -d > $filename 
And when it creates $filename 
 
It gives me this message at the top.
************************************************************************
*********************************************************
# The CMOS Definition table was not found in ram
# CMOS definition table was not found in RAM memory
# Looking for definitions in cmos.layout file
# WARNING - Select only one option per entry
# reserved_memory =
185445500431042106032602508000004066f08803800200fc010019eb231aeb1b100010
b28102000000f500f8ff0a28
************************************************************************
***********************************************************
 Like I said I am fairly new to this I am still trying to figure out how
it works and if there is a howto for the super micro MB's or if the
howto's for the older boards will work. could some please help me.  
Thank you 
 
 Tim Cook
 
 ""A man is not idle because he is absorbed in thought. 
There is a visible labor and there is an invisible labor ""
"Victor Hugo <http://www.promicrosystems.com/> "
 
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From rminnich at lanl.gov  Fri Jun 20 17:22:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 17:22:01 2003
Subject: new config language.
In-Reply-To: <m37k7gsbdv.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306201527150.11515-100000@maxroach.lanl.gov>

re the parts used on these boards: they are the 49f040. I did program an 
SST28SF040 (which I have a lot of) but it did not work. 

I am not trying to see how to program the 49F040, since my smartcore board 
can not read or write this part. 

Do you use MTD to program the part?

ron



From rminnich at lanl.gov  Fri Jun 20 17:27:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 17:27:00 2003
Subject: newbie question 
In-Reply-To: <002b01c33772$1936ff60$1901a8c0@tcook>
Message-ID: <Pine.LNX.4.44.0306201532100.11515-100000@maxroach.lanl.gov>

On Fri, 20 Jun 2003, tcook wrote:

> I am working on the  Super Micro P4DPR-IGM I am trying to get linuxbios
> installed 
> I run cmos_util -d > $filename 

running the normal bios? there is no linuxbios cmos table in that case. 
Or are you up in linuxbios?

ron



From ebiederman at lnxi.com  Fri Jun 20 17:29:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 20 17:29:01 2003
Subject: new config language.
In-Reply-To: <Pine.LNX.4.44.0306201527150.11515-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306201527150.11515-100000@maxroach.lanl.gov>
Message-ID: <m3r85ol9cj.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> re the parts used on these boards: they are the 49f040. I did program an 
> SST28SF040 (which I have a lot of) but it did not work. 
> 
> I am not trying to see how to program the 49F040, since my smartcore board 
> can not read or write this part. 
> 
> Do you use MTD to program the part?

Ron I have been using the MTD drivers and we have been having good luck
here.   

With respect to the differences from the smartcore.  The Opteron is LPC
all the way.  And given it's age I believe the smartcore still uses
and ISA bus.  So I don't think parts are compatible.

Eric



From rminnich at lanl.gov  Fri Jun 20 17:39:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Jun 20 17:39:00 2003
Subject: new config language.
In-Reply-To: <m3r85ol9cj.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306201544250.11515-100000@maxroach.lanl.gov>

On 20 Jun 2003, Eric W. Biederman wrote:

> Ron I have been using the MTD drivers and we have been having good luck
> here.   

so from e.g. a 2.4.19 kernel I should be able to modprobe the right mtd 
bits and get a /dev/mtd0, right? 

What's the physical address of the flash part? 0xfff8xxxx? This box I have 
is in 64-bit mode and I'm no longer sure of what is addressed where.

ron



From ebiederman at lnxi.com  Fri Jun 20 19:52:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri Jun 20 19:52:00 2003
Subject: new config language.
In-Reply-To: <Pine.LNX.4.44.0306201544250.11515-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306201544250.11515-100000@maxroach.lanl.gov>
Message-ID: <m3u1akgv0a.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On 20 Jun 2003, Eric W. Biederman wrote:
> 
> > Ron I have been using the MTD drivers and we have been having good luck
> > here.   
> 
> so from e.g. a 2.4.19 kernel I should be able to modprobe the right mtd 
> bits and get a /dev/mtd0, right? 

Pretty close the latest code is not in 2.4.19.  There should
be more in 2.4.21.  It is a challenge getting a kernel with drivers
for the latest hardware.

> What's the physical address of the flash part? 0xfff8xxxx? This box I have 
> is in 64-bit mode and I'm no longer sure of what is addressed where.

On the opteron, fun.  The answer is that the map drivers handles that part.
But you will probably need the latest from the mtd cvs tree.

The modules I think you want are:
mtdchar
amd76x
jedec_probe
cfi_cmdset_2

I'm a little fuzzy as I usually build everything but the map drivers
into the kernel.  Basically you don't want the map driver loaded when
you hot swap chips as that confuses it, because it doesn't have the
concept of hot-plug.

Eric



From YhLu at tyan.com  Sat Jun 21 03:19:00 2003
From: YhLu at tyan.com (YhLu)
Date: Sat Jun 21 03:19:00 2003
Subject: =?GB2312?B?tPC4tDogbmV3IGNvbmZpZyBsYW5ndWFnZS4=?=
Message-ID: <3174569B9743D511922F00A0C943142302C43F34@TYANWEB>

Eric,

I have added some hardcode to northbridge/amd/amdk8/coherent_ht.c.

Till now, I can not change NodeID from 7 to 1 for the second Node.

Do I need to send the coherent_ht.c to Stefan to check or after I finished
the debug?

Regards

Yinghai Lu

-----????-----
???: YhLu 
????: 2003?6?20? 14:23
???: ebiederman at lnxi.com
??: ron minnich; linuxbios at clustermatic.org
??: ??: new config language.

Eric,

S2880 is 2P and it is ready.
S4880 is 4P and it is on-going.

Regards

Yinghai Lu

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?6?20? 14:11
???: YhLu
??: ron minnich; linuxbios at clustermatic.org
??: Re: new config language.

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Thanks for the info about ROMCC.

Welcome.  Given that we are switching to writing all of the code before
memory is initialized knowing how stable  the main tool for doing the job
is useful.  And the list was copied so I don't have to mention it multiple
times.

> The code about mem init in northbridge/amd/amdk8/coherent_ht.c and
> northbridge/amd/amdk8/raminit.c had some overlap. On bus 0, dev 0x18 and f
> 1.

Very peculiar as I don't see that code and the actual coherent HT mapping
is just concerned with function 0.    The mapping which specifies which
resources go where is on function 1.
 
> I will add something at northbridge/amd/amdk8/coherent_ht.c

There are some peculiarities as the code is a first pass at properly 
factoring it.  I think I made a good stab at it but the code still
needs to be generalized.   

An important thing to not is that when the code is done there should
be no board specific hard codes, excpet in code that lives in auto.c

Do you have a 4P case or just 2P?

Eric
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From spirit at reactor.ru  Sat Jun 21 04:27:00 2003
From: spirit at reactor.ru (Alexander Amelkin)
Date: Sat Jun 21 04:27:00 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306200905230.9687-100000@maxroach.lanl.gov>
Message-ID: <1091012572472.20030621123130@reactor.ru>

Hello Ron!

Friday, June 20, 2003, 7:06:07 PM, you wrote:

rm> Now I need to find four cheap, compact power supplies :-)

rm> no disk in this system, no cdrom, no nothing save for motherboards. I'm 
rm> looking for small, cheap, good supplies. Probably don't exist but anybody 
rm> know for sure?

I'd go for In-Win (Powerman) power supplies. They go for about US$15-20
here in Russia. The best supplies and the best cases too, IMHO. Check
your local In-Win dealer for availability and prices. See
http://www.in-win.com.tw/home/english/power_supply.htm or just
www.in-win.com

With best regards,
Alexander  mailto:spirit at reactor.ru



From stepan at suse.de  Sat Jun 21 10:12:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Sat Jun 21 10:12:00 2003
Subject: coherent hypertransport enumeration on opteron
In-Reply-To: <3174569B9743D511922F00A0C943142302C43F34@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43F34@TYANWEB>
Message-ID: <20030621141756.GB21904@suse.de>

* YhLu <YhLu at tyan.com> [030621 09:27]:
> I have added some hardcode to northbridge/amd/amdk8/coherent_ht.c.
> 
> Till now, I can not change NodeID from 7 to 1 for the second Node.
> 
> Do I need to send the coherent_ht.c to Stefan to check or after I finished
> the debug?

as far as i can tell you need to set up a link to node 7 before you can
rename it to node 1. I'm going to release my code somewhen next week as
soon as I figured out all the details of mp capability detection.
Feel free to send your code to me or the list for discussion.

  Stefan

-- 
Architecture Team
    SuSE Linux AG


From Phreak_Show at gmx.de  Sat Jun 21 15:36:00 2003
From: Phreak_Show at gmx.de (Stefan)
Date: Sat Jun 21 15:36:00 2003
Subject: Gigabyte GA-7DXR
Message-ID: <3EF4B52E.7090606@gmx.de>

Hi!
Does anyone know if LinuxBIOS works on a GA-7DXR? SuSE 8.0 is working 
perfect! Here are the lspci results:

linux:~ # lspci 
00:00.0 Host bridge: Advanced Micro Devices [AMD] AMD-760 [Irongate] 
System Controller (rev 13) 
00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-760 [Irongate] AGP 
Bridge 
00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] 
(rev 40) 
00:07.1 IDE interface: VIA Technologies, Inc. Bus Master IDE (rev 06) 
00:07.2 USB Controller: VIA Technologies, Inc. UHCI USB (rev 1a) 
00:07.3 USB Controller: VIA Technologies, Inc. UHCI USB (rev 1a) 
00:07.4 SMBus: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 
40) 
00:0a.0 Network controller: AVM Audiovisuelles MKTG & Computer System GmbH 
A1 ISDN [Fritz] (rev 02) 
00:0c.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 
07) 
00:0c.1 Input device controller: Creative Labs SB Live! (rev 07) 
00:0d.0 Multimedia video controller: Brooktree Corporation Bt878 (rev 02) 
00:0d.1 Multimedia controller: Brooktree Corporation Bt878 (rev 02) 
00:0f.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139 (rev 
10) 
00:10.0 RAID bus controller: Promise Technology, Inc. 20265 (rev 02) 
01:05.0 VGA compatible controller: nVidia Corporation: Unknown device 0202 
(rev a3) 
linux:~ # lspci -v 
00:00.0 Host bridge: Advanced Micro Devices [AMD] AMD-760 [Irongate] 
System Controller (rev 13) 
        Flags: bus master, medium devsel, latency 32 
        Memory at c0000000 (32-bit, prefetchable) [size=256M] 
        Memory at db023000 (32-bit, prefetchable) [size=4K] 
        I/O ports at 9000 [disabled] [size=4] 
        Capabilities: [a0] AGP version 2.0 
 
00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-760 [Irongate] AGP 
Bridge (prog-if 00 [Normal decode]) 
        Flags: bus master, 66Mhz, medium devsel, latency 32 
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 
        Memory behind bridge: d8000000-d9ffffff 
        Prefetchable memory behind bridge: d0000000-d7ffffff 
 
00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] 
(rev 40) 
        Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge 
        Flags: bus master, stepping, medium devsel, latency 0 
        Capabilities: [c0] Power Management version 2 
 
00:07.1 IDE interface: VIA Technologies, Inc. Bus Master IDE (rev 06) 
(prog-if 8a [Master SecP PriP]) 
        Subsystem: VIA Technologies, Inc. Bus Master IDE 
        Flags: bus master, medium devsel, latency 32 
        I/O ports at 9400 [size=16] 
        Capabilities: [c0] Power Management version 2 
 
00:07.2 USB Controller: VIA Technologies, Inc. UHCI USB (rev 1a) (prog-if 
00 [UHCI]) 
        Subsystem: Unknown device 0925:1234 
        Flags: bus master, medium devsel, latency 32, IRQ 11 
        I/O ports at 9800 [size=32] 
        Capabilities: [80] Power Management version 2 
 
00:07.3 USB Controller: VIA Technologies, Inc. UHCI USB (rev 1a) (prog-if 
00 [UHCI]) 
        Subsystem: Unknown device 0925:1234 
        Flags: bus master, medium devsel, latency 32, IRQ 11 
        I/O ports at 9c00 [size=32] 
        Capabilities: [80] Power Management version 2 
 
00:07.4 SMBus: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 
40) 
        Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] 
        Flags: medium devsel, IRQ 9 
        Capabilities: [68] Power Management version 2 
 
00:0a.0 Network controller: AVM Audiovisuelles MKTG & Computer System GmbH 
A1 ISDN [Fritz] (rev 02) 
        Subsystem: AVM Audiovisuelles MKTG & Computer System GmbH 
FRITZ!Card ISDN Controller 
        Flags: medium devsel, IRQ 10 
        Memory at db024000 (32-bit, non-prefetchable) [size=32] 
        I/O ports at a000 [size=32] 
 
00:0c.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 
07) 
        Subsystem: Creative Labs: Unknown device 8064 
        Flags: bus master, medium devsel, latency 32, IRQ 5 
        I/O ports at a400 [size=32] 
        Capabilities: [dc] Power Management version 1 
 
00:0c.1 Input device controller: Creative Labs SB Live! (rev 07) 
        Subsystem: Creative Labs Gameport Joystick 
        Flags: bus master, medium devsel, latency 32 
        I/O ports at a800 [size=8] 
        Capabilities: [dc] Power Management version 1 
 
00:0d.0 Multimedia video controller: Brooktree Corporation Bt878 (rev 02) 
        Subsystem: Hauppauge computer works Inc. WinTV/GO 
        Flags: bus master, medium devsel, latency 32, IRQ 7 
        Memory at db020000 (32-bit, prefetchable) [size=4K] 
 
00:0d.1 Multimedia controller: Brooktree Corporation Bt878 (rev 02) 
        Subsystem: Hauppauge computer works Inc. WinTV/GO 
        Flags: bus master, medium devsel, latency 32, IRQ 7 
        Memory at db021000 (32-bit, prefetchable) [size=4K] 
 
00:0f.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139 (rev 
10) 
        Subsystem: Realtek Semiconductor Co., Ltd. RT8139 
        Flags: bus master, medium devsel, latency 32, IRQ 11 
        I/O ports at ac00 [size=256] 
        Memory at db022000 (32-bit, non-prefetchable) [size=256] 
        Capabilities: [50] Power Management version 2 
 
00:10.0 RAID bus controller: Promise Technology, Inc. 20265 (rev 02) 
        Subsystem: Promise Technology, Inc. Ultra100 
        Flags: bus master, medium devsel, latency 32, IRQ 11 
        I/O ports at b000 [size=8] 
        I/O ports at b400 [size=4] 
        I/O ports at b800 [size=8] 
        I/O ports at bc00 [size=4] 
        I/O ports at c000 [size=64] 
        Memory at db000000 (32-bit, non-prefetchable) [size=128K] 
        Expansion ROM at <unassigned> [disabled] [size=128K] 
        Capabilities: [58] Power Management version 1 
 
01:05.0 VGA compatible controller: nVidia Corporation: Unknown device 0202 
(rev a3) (prog-if 00 [VGA]) 
        Subsystem: Micro-star International Co Ltd: Unknown device 5305 
        Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 5 
        Memory at d8000000 (32-bit, non-prefetchable) [size=16M] 
        Memory at d0000000 (32-bit, prefetchable) [size=64M] 
        Memory at d4000000 (32-bit, prefetchable) [size=512K] 
        Expansion ROM at <unassigned> [disabled] [size=64K] 
        Capabilities: [60] Power Management version 2 
        Capabilities: [44] AGP version 2.0 

thx & greetings



From yhlu at tyan.com  Sat Jun 21 16:16:01 2003
From: yhlu at tyan.com (Yinghai Lu)
Date: Sat Jun 21 16:16:01 2003
Subject: =?gb2312?B?tPC4tDogY29oZXJlbnQgaHlwZXJ0cmFuc3BvcnQgZW51bWVyYXRpb24gb24=?=
	=?gb2312?B?IG9wdGVyb24=?=
In-Reply-To: <20030621141756.GB21904@suse.de>
Message-ID: <000001c33832$880e61b0$21c8a140@yhlunb>

Please refer the program cut.

static void setup_coherent_ht_domain(void)
{
	static const unsigned int register_values[] = {
	PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00050101,
	PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010404,
	PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010404,


	PCI_ADDR(0, 0x1f, 0, 0x6C), 0xfffffffd, 0x00000002, 

     PCI_ADDR(0, 0x1f, 0, 0x40), 0xfff0f0f0, 0x00010404,
     PCI_ADDR(0, 0x1f, 0, 0x44), 0xfff0f0f0, 0x00050101,

	PCI_ADDR(0, 0x1f, 0, 0x60), 0xfffffff8, 0x00000001, // Can not
change NodeID to 1 here

	PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,

     PCI_ADDR(0, 0x18, 0, 0x60), 0xfff8ff8f, 0x00010010,
     PCI_ADDR(0, 0x19, 0, 0x60), 0xfff8ff8f, 0x00010010,

     PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00c800,
     PCI_ADDR(0, 0x19, 0, 0x68), 0x00800000, 0x0f00c800,
 
	PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000070, //1C
	PCI_ADDR(0, 0x19, 0, 0x6C), 0xffffff8c, 0x00000070,//14
	PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020,
	PCI_ADDR(0, 0x19, 0, 0x84), 0x00009c05, 0x771100d0,

	PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000500,
	PCI_ADDR(0, 0x19, 0, 0x88), 0xfffff0ff, 0x00000500,

	PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000,
	PCI_ADDR(0, 0x19, 0, 0x94), 0xff000000, 0x00000000,
	};
	int i;
	int max;
	int j;
	print_debug("setting up coherent ht domain....\r\n");
	max = sizeof(register_values)/sizeof(register_values[0]);
	for(i = 0; i < max; i += 3) {
		device_t dev;
		unsigned where;
		unsigned long reg;
#if 1
		print_debug_hex32(i);
		print_debug(": ");
		print_debug_hex32(register_values[i]);
		print_debug(" <-");
		print_debug_hex32(register_values[i+2]);
		print_debug("\r\n");
#endif
		dev = register_values[i] & ~0xff;
		where = register_values[i] & 0xff;
		reg = pci_read_config32(dev, where);
		reg &= register_values[i+1];
		reg |= register_values[i+2];
		pci_write_config32(dev, where, reg);
		if(i==3*3) {
			for(j=0;j<300000;j++) {	  // make sure request
diable bit is set
				reg = pci_read_config32(dev,where);
				reg &= ~(register_values[i+1]);
		 		if(reg==register_values[i+2]) {  
//					print_debug("request disable bit
set \r\n");
					break;
				}
			}

		}
		if(i==2*3) {
			reg = pci_read_config32(PCI_ADDR(0, 0x1f, 0,
0)&~0xff,PCI_ADDR(0, 0x1f, 0, 0) & 0xff); // read Vender ID
//			print_debug("1f DeviceID readed ");
//			print_debug_hex32(reg);
//			print_debug("\r\n");
		}
 
	}
	print_debug("done.\r\n");
}


-----????-----
???: linuxbios-admin at clustermatic.org
[mailto:linuxbios-admin at clustermatic.org] ?? Stefan Reinauer
????: 2003?6?21? 7:18
???: YhLu
??: ebiederman at lnxi.com; ron minnich; linuxbios at clustermatic.org
??: coherent hypertransport enumeration on opteron

* YhLu <YhLu at tyan.com> [030621 09:27]:
> I have added some hardcode to northbridge/amd/amdk8/coherent_ht.c.
> 
> Till now, I can not change NodeID from 7 to 1 for the second Node.
> 
> Do I need to send the coherent_ht.c to Stefan to check or after I
finished
> the debug?

as far as i can tell you need to set up a link to node 7 before you can
rename it to node 1. I'm going to release my code somewhen next week as
soon as I figured out all the details of mp capability detection.
Feel free to send your code to me or the list for discussion.

  Stefan

-- 
Architecture Team
    SuSE Linux AG
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Sun Jun 22 01:04:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun 22 01:04:01 2003
Subject: Gigabyte GA-7DXR
In-Reply-To: <3EF4B52E.7090606@gmx.de>
Message-ID: <Pine.LNX.4.44.0306212310030.25490-100000@maxroach.lanl.gov>

seems like that's a supported chipset to me.

But what kind of flash part?

ron



From justin at street-vision.com  Sun Jun 22 06:19:00 2003
From: justin at street-vision.com (Justin Cormack)
Date: Sun Jun 22 06:19:00 2003
Subject: power connectors for mainboards
In-Reply-To: <Pine.LNX.4.44.0306200839320.9687-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306200839320.9687-100000@maxroach.lanl.gov>
Message-ID: <1056277545.13239.9.camel@lotte>

On Fri, 2003-06-20 at 15:40, ron minnich wrote:
> 
> I have four K7SEMs which I would like to run from one PC power supply. 
> 
> Does anyone know if there are off-the-shelf cables available to do this 
> type of thing? Essentially a "Y" connector for the mainboard power 
> connector.

Sun Power (www.sunpower.com) will make up power supplies with custom
connectors (extremely quickly). You could ask them to make one up with 4
ATX connectors on (modulo sorting out the power on lines). Their PSUs
are pretty good, I reckon you might get away with 600W for 4 Durons,
maybe a little more.

Justin




From rminnich at lanl.gov  Sun Jun 22 16:11:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun 22 16:11:00 2003
Subject: power connectors for mainboards
In-Reply-To: <1056277545.13239.9.camel@lotte>
Message-ID: <Pine.LNX.4.44.0306221417120.12011-100000@maxroach.lanl.gov>

On 22 Jun 2003, Justin Cormack wrote:

> Sun Power (www.sunpower.com) will make up power supplies with custom

I think that's the wrong URL? get's me some technology company with 
refrigeration or something.

ron



From rminnich at lanl.gov  Sun Jun 22 16:13:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun 22 16:13:01 2003
Subject: power connectors for mainboards
In-Reply-To: <1056277545.13239.9.camel@lotte>
Message-ID: <Pine.LNX.4.44.0306221419310.12011-100000@maxroach.lanl.gov>

On 22 Jun 2003, Justin Cormack wrote:

> Sun Power (www.sunpower.com) will make up power supplies with custom

ah. 

sunpower.com.tw

ron



From linuxbios at techfreakz.net  Sun Jun 22 18:34:00 2003
From: linuxbios at techfreakz.net (Alex Scarbro)
Date: Sun Jun 22 18:34:00 2003
Subject: K7SEM Serial Boot Log....What next...
Message-ID: <2003622234026.687475@techfreakz>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20030622/3e20140c/attachment.html>

From rminnich at lanl.gov  Sun Jun 22 21:15:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun 22 21:15:00 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <2003622234026.687475@techfreakz>
Message-ID: <Pine.LNX.4.44.0306221921270.14262-100000@maxroach.lanl.gov>

On Sun, 22 Jun 2003, Alex Scarbro wrote:

> using hyperterm), however,
        ^^^^^^^^^

nope. Don't use hyperterm, it's useless. You've got to use minicom on 
linux or youu will find that you are dropping huge amounts of output.

ron



From rminnich at lanl.gov  Sun Jun 22 21:16:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun 22 21:16:01 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <2003622234026.687475@techfreakz>
Message-ID: <Pine.LNX.4.44.0306221920320.14262-100000@maxroach.lanl.gov>

OK, I am now seeing these K7SEM lockups I think from more than one person, 
happening in that 'set UC on the fixed MTRRs' step. 

Is there any chance that recent changes to improve boot time have caused 
trouble in the K7-based boards? 

ron




From rminnich at lanl.gov  Sun Jun 22 21:20:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sun Jun 22 21:20:00 2003
Subject: Trying to freeze and failing ...
Message-ID: <Pine.LNX.4.44.0306221925150.14262-100000@maxroach.lanl.gov>

Can anyone who has built a k7sem recently verify that the 'FIXED MTRR set 
to UC' code is not fouling up the K7sem? 

I really do want to freeze the 1.0 tree but we're not converging. Or we 
almost are save for "the last few bugs". I just got some K7SEM's but won't 
have time to look at this for a bit -- if anyone can test this for me with 
the latest CVS that would be helpful. 

Andrew Ip, you are probably the best person to test this, can you take a 
look?

ron



From ijpriya at hotmail.com  Mon Jun 23 00:40:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Mon Jun 23 00:40:01 2003
Subject: Which Kernel to be used?
Message-ID: <BAY2-F10869yfB4mvo900005541@hotmail.com>

Hello,
                  I want to build LinuxBIOS for SC1200. I have the kernel 
2.4.18-14 (Redhat 8.0). Can I use the same kernel to be used by linuxbios? 
If I use this kernel then what patch should I apply from 
freebios/src/kernel_patches/ directory to build for sc1200? Or else should I 
use the kernel linux-2.4.0-test12?(ie is it mandatory to use this kernel?) 
For this what patch should I apply to build it for the sc1200?

Thanks for any help in advance.

_________________________________________________________________
Gift yourself a holiday. Treat your family like royalty. 
http://www.flexihols.com/2003/index.php



From ijpraveen1 at yahoo.com  Mon Jun 23 01:58:01 2003
From: ijpraveen1 at yahoo.com (John Praveen)
Date: Mon Jun 23 01:58:01 2003
Subject: patch for my mainboard?
Message-ID: <20030623060435.16141.qmail@web41713.mail.yahoo.com>

Hi,

       I am new to LinuxBios. I got the source for
Linuxbios through CVS. It is given in the doc that
some patch has to be applied to the kernel. Is
applying this patch is a compulsory one even if we use
the kernel version 2.4.17 or higher? I guess that the
patches are related to the mainboard. I dont find a
patch corresponding to my mainboard. What should be
done then?

Plz help me.

__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
http://sbc.yahoo.com


From linuxbios at techfreakz.net  Mon Jun 23 03:10:01 2003
From: linuxbios at techfreakz.net (Alex Scarbro)
Date: Mon Jun 23 03:10:01 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <Pine.LNX.4.44.0306221921270.14262-100000@maxroach.lanl.gov>
Message-ID: <200362381617.272729@techfreakz>

An HTML attachment was scrubbed...
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From ts1 at cma.co.jp  Mon Jun 23 03:25:01 2003
From: ts1 at cma.co.jp (SONE Takeshi)
Date: Mon Jun 23 03:25:01 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <Pine.LNX.4.44.0306221920320.14262-100000@maxroach.lanl.gov>
References: <2003622234026.687475@techfreakz> <Pine.LNX.4.44.0306221920320.14262-100000@maxroach.lanl.gov>
Message-ID: <20030623073144.GA6972@cma.co.jp>

On Sun, Jun 22, 2003 at 07:22:45PM -0600, ron minnich wrote:
> OK, I am now seeing these K7SEM lockups I think from more than one person, 
> happening in that 'set UC on the fixed MTRRs' step. 

I've seen this symptom on EPIA when the RAM is not correctly
initialized.
I thought that until MTRR is set to UnCacheable, linuxbios_c runs on
cache, not RAM.

> Is there any chance that recent changes to improve boot time have caused 
> trouble in the K7-based boards? 

At least my modification to enable cache on 0xF0000-0xFFFFF area
is not in CVS.

--
Takeshi


From rogerxxmaillist at san.rr.com  Mon Jun 23 05:44:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Mon Jun 23 05:44:01 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <200362381617.272729@techfreakz>
References: <200362381617.272729@techfreakz>
Message-ID: <1056361734.17096.5.camel@localhost3.localdomain>

This is my setup using kermit.  I prefer kermit over minicom.  I have
yet to be able to get linuxbios booting (due to mtd issues), however,
here's my setup that works with the normal kernel boot.  You might need
to augment the speed to 9600 or 19200 instead of 115200.


/etc/lilo.conf contains:
append="console=ttyS1,115200"

~/.kermrc
set modem type none
set line /dev/ttyS1
set speed 115200
set flow rts/cts
set carrier-watch off

You also need to set the speed of the com port via setserial before
starting minicom or kermit.

ie:

# setserial /dev/ttyS1 baud_base 115200



On Mon, 2003-06-23 at 00:16, Alex Scarbro wrote:
> On Sun, 22 Jun 2003 19:22:11 -0600 (MDT), ron minnich wrote:
> >On Sun, 22 Jun 2003, Alex Scarbro wrote:
> >
> >>using hyperterm), however,
> >^^^^^^^^^
> >
> >nope. Don't use hyperterm, it's useless. You've got to use minicom on
> >linux or youu will find that you are dropping huge amounts of output.
> >
> >ron
> >
> >_______________________________________________
> >Linuxbios mailing list
> >Linuxbios at clustermatic.org
> >http://www.clustermatic.org/mailman/listinfo/linuxbios
>  
> hi there, 
> 
>   Cheers for the reply.  I'll get minicom setup.  It was late at night
> that i finally got the K7sem booting, and hyperterm  was the only
> terminal on hand.  BTW, do you use any handshaking on the terminal (ie
> hardware/software/none)?
> 
>  
> Thanks again
> 
> -- 
> 
> Alex Scarbro, linuxbios at techfreakz.net on 23/06/2003
> 
> _______________________________________________ Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
-- 

Roger
http://www.eskimo.com/~roger/index.html



From rogerxxmaillist at san.rr.com  Mon Jun 23 05:50:01 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Mon Jun 23 05:50:01 2003
Subject: mtd drivers and diskonchip millenium
Message-ID: <1056362077.17096.9.camel@localhost3.localdomain>

hey all. just dropping a note here that I'm having a problem getting the
doc2001 module(s) to recognize a diskonchip millenium being placed in
the old motherboard bios chip socket.

seems I have to induce a kernel oops to get the diskonchip recognized.

i've already emailed the problem to the mtd mailling lists and david
mentioned something about using a memory map module prior to loading.

so my installation of linuxbios has been stalled.  basically, on reboot,
the both boxes act similar to as if there is no bios chip installed.
also have the docipl + 440bx support issue.  As a work around tho, I
plan on buying spare bios chips.  However, mtd is still buggy.  So far,
openbios/devbios is the only thing that will actively let me read/write
to the device.

(Tyan Tiger 1832DL 440BX with a second 440BX board laying around. Both
with the same problem.  So much for spending the extra buck on intel
boards to ensure compatability eh?)

-- 

Roger
http://www.eskimo.com/~roger/index.html



From rminnich at lanl.gov  Mon Jun 23 09:50:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 09:50:01 2003
Subject: Which Kernel to be used?
In-Reply-To: <BAY2-F10869yfB4mvo900005541@hotmail.com>
Message-ID: <Pine.LNX.4.44.0306230755410.19442-100000@maxroach.lanl.gov>

use the 2.4.18, for geode, as it doesn't have the broken IRQ mapping.

If you are going to use IDE disks, you MAY need the ide-spinup.patch.

ron



From rminnich at lanl.gov  Mon Jun 23 09:53:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 09:53:01 2003
Subject: patch for my mainboard?
In-Reply-To: <20030623060435.16141.qmail@web41713.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0306230759430.19442-100000@maxroach.lanl.gov>

what's your mainboard? 

On a new board, I always try to see if I can get by with zero patches. 

ron



From rminnich at lanl.gov  Mon Jun 23 09:53:07 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 09:53:07 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <200362381617.272729@techfreakz>
Message-ID: <Pine.LNX.4.44.0306230800090.19442-100000@maxroach.lanl.gov>

On Mon, 23 Jun 2003, Alex Scarbro wrote:

> ? Cheers for the reply.? I'll get minicom setup.? It was late at night
> that i finally got the K7sem booting, and hyperterm was the only terminal
> on hand.? BTW, do you use any handshaking on the terminal (ie
> hardware/software/none)?

I usually turn all handshaking off.

ron



From rminnich at lanl.gov  Mon Jun 23 09:55:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 09:55:01 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <20030623073144.GA6972@cma.co.jp>
Message-ID: <Pine.LNX.4.44.0306230801070.19442-100000@maxroach.lanl.gov>

On Mon, 23 Jun 2003, SONE Takeshi wrote:

> At least my modification to enable cache on 0xF0000-0xFFFFF area
> is not in CVS.

I still owe you that patch. 

I'll commit it, I guess, but this will have to be the last one. 

Let's try to all make sure it works ...

ron



From rminnich at lanl.gov  Mon Jun 23 09:57:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 09:57:01 2003
Subject: mtd drivers and diskonchip millenium
In-Reply-To: <1056362077.17096.9.camel@localhost3.localdomain>
Message-ID: <Pine.LNX.4.44.0306230803320.19442-100000@maxroach.lanl.gov>

On 23 Jun 2003, roger wrote:

> (Tyan Tiger 1832DL 440BX with a second 440BX board laying around. Both
> with the same problem.  So much for spending the extra buck on intel
> boards to ensure compatability eh?)


OK, you could try enabling the flash write from the setpci command, and 
then using MTD. 

ron



From rminnich at lanl.gov  Mon Jun 23 12:01:18 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 12:01:18 2003
Subject: new config language.
In-Reply-To: <m3u1akgv0a.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov>

On 20 Jun 2003, Eric W. Biederman wrote:

> The modules I think you want are:
> mtdchar
> amd76x

hmm, not on an 8111.

I'm looking at a map driver for that now. 

ron



From rsmith at bitworks.com  Mon Jun 23 12:49:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Mon Jun 23 12:49:01 2003
Subject: 440bx Mouse function (fixed)
In-Reply-To: <Pine.LNX.4.44.0306200755520.9453-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306200755520.9453-100000@maxroach.lanl.gov>
Message-ID: <3EF730A9.7010909@bitworks.com>

ron minnich wrote:

> I'm not checked out on this particular problem, most of my nodes don't do 
> mice. :-(
> 

I solved my no mouse issues.  The problem was that the keyboard_on() in 
  southbridge.c was setting the KBCSS# enable bit and I didn't realize it.

The KBCSS# enable causes the piix4e to assert KBCS# and XOE# upon access 
to io ports 60 and 64.  These are basically chip selects for a setup 
that dosn't have decoding of these io port build in.  Our NSC PC87351 
superio dosen't need these lines as it does its own IO decodeing of 
these ports.  And even though these lines aren't hooked to anything on 
our board if this bit is enabled then the mouse won't work.  Kinda of 
wierd since the keyboard works fine and they both use the same IO addresses.

So this enable needs to be an option rather than hardcoded as its 
motherboard dependant if you need this bit set or not.  I suspect that 
almost all modern superios will _not_ need any help with IO decode so 
I'll default this to off.

Ron: did you ever attempt to sync the 440bx code with patch file I sent 
you?  If not then don't worry about it as I have change quite a bit 
since then.  Most of it is just a lot of addtional prink_debugs to show 
what the code is doing and where it happens but there is a fix or 2 in 
there as well.  I'm also adding some things like getting the USB bridge 
setup right.  Linux still whines about not being able to get the irq.

-- 
Richard A. Smith
rsmith at bitworks.com




From rsmith at bitworks.com  Mon Jun 23 12:50:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Mon Jun 23 12:50:01 2003
Subject: 440bx Mouse function (fixed)
Message-ID: <3EF7311B.2030509@bitworks.com>

Oops... Sent this dirctly to ron instead of the list like I wanted.


ron minnich wrote:

> I'm not checked out on this particular problem, most of my nodes don't do 
> mice. :-(
> 

I solved my no mouse issues.  The problem was that the keyboard_on() in
  southbridge.c was setting the KBCSS# enable bit and I didn't realize it.

The KBCSS# enable causes the piix4e to assert KBCS# and XOE# upon access
to io ports 60 and 64.  These are basically chip selects for a setup
that dosn't have decoding of these io port build in.  Our NSC PC87351
superio dosen't need these lines as it does its own IO decodeing of
these ports.  And even though these lines aren't hooked to anything on
our board if this bit is enabled then the mouse won't work.  Kinda of
wierd since the keyboard works fine and they both use the same IO addresses.

So this enable needs to be an option rather than hardcoded as its
motherboard dependant if you need this bit set or not.  I suspect that
almost all modern superios will _not_ need any help with IO decode so
I'll default this to off.

Ron: did you ever attempt to sync the 440bx code with patch file I sent
you?  If not then don't worry about it as I have change quite a bit
since then.  Most of it is just a lot of addtional prink_debugs to show
what the code is doing and where it happens but there is a fix or 2 in
there as well.  I'm also adding some things like getting the USB bridge
setup right.  Linux still whines about not being able to get the irq.


-- 
Richard A. Smith
rsmith at bitworks.com




From linuxbios at techfreakz.net  Mon Jun 23 13:41:00 2003
From: linuxbios at techfreakz.net (Alex Scarbro)
Date: Mon Jun 23 13:41:00 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <Pine.LNX.4.44.0306230800270.19442-100000@maxroach.lanl.gov>
Message-ID: <2003623184715.410024@techfreakz>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20030623/893f984b/attachment.html>
-------------- next part --------------
Based on the Sis 630 HOWTO by Ron Minnich.
HOWTO written by Brenden Bixler 

This file contains instructions for the K7SEM, Socket 7 (k7/Duron) based mainboards.

Unfortunately, there is a step in this HOWTO that could be hazardous. The 
hazards include (but are not limited to)
	1) destroying your motherboard
	2) hurting yourself
	3) killing yourself

Because of these hazards, you must take full responsibility if you
decide to install LinuxBIOS following these procedures. Neither Los
Alamos National Labs or any lab personnel can be held responsible for
any adverse consequences of your attempt to follow these procedures.

WARNING: We assume you've built kernels, know how to open up your PC,
and how to yank the flash part out while power is on and put in a
different part. There is NO WARRANTY, express or implied, with this
software. In fact, if you don't know what you're doing, and you get
careless, you're going to end up with a nice paperweight instead of a
motherboard, an emergency room bill, or a funeral service.

			YOU HAVE BEEN WARNED.

Additional information available at: http://www.acl.lanl.gov/linuxbios/

Linux distribution: Most modern distributions are supported. This HOWTO tested using RedHat 7.2

Other software notes: You MUST have 'as' version 2.9.5 or later. You MUST have ssh
to connect to sourceforge

Recommended: you might want to get a 32-DIP Zero Insertion Force (ZIF)
socket for the flash part. This makes taking out flash and putting in Disk
On Chip much easier. 

You need to have a LinuxBIOS machine (the machine that runs LinuxBIOS)
and a build machine (which will let you build LinuxBIOS). These can be
one and the same machine. In this HOWTO we assume they're the same. 
We nevertheless refer to a 'build' machine and 'LinuxBIOS' machine in case you
want to use a different machine. 

Also, freebios and LinuxBIOS still share the same source tree. We use the 
name 'LinuxBIOS' where it makes sense, and 'freebios' otherwise. But they 
are the same source base. 

----
The steps for loading LinuxBIOS are simple:
1) Get Linux installed on your LinuxBIOS machine.
2) Get LinuxBIOS source from Sourceforge.
3) Get a 2.4.0 kernel, patch it, then compile.
4) Configure and build LinuxBIOS.
5) Get the MTD utilities from http://www.linux-mtd.infradead.org/ 
	and build the 'erase' utility.
6) Set up the 'flash_on' program in your path.
7) Put a Disk On Chip into the flash socket.
8) Burn the chip.
9) Reset the machine -- did it work?

---
Step 1) 
	Get Linux installed on your LinuxBIOS machine. Tested on RedHat 7.2
	Note: Do not format disk partitions as ext3! It's not supported by the LinuxBIOS kernel patch for 2.		4.7. Stick with ext2 -- it makes things much easier.

Step 2)
	Grab the LinuxBIOS source.
	cd to the directory you want the source tree to be.

Note: This HOWTO uses /usr/src as the base directory. After running the following commands from this directory, you should have a directory (/usr/src/freebios) with all the source code.

export CVS_RSH=ssh (or in tcsh setenv CVS_RSH ssh)


cvs -d:pserver:anonymous at cvs.freebios.sourceforge.net:/cvsroot/freebios login 
	(at the password prompt, just hit <return>)

cvs -z3 -d:pserver:anonymous at cvs.freebios.sourceforge.net:/cvsroot/freebios co freebios 


Step 3)
 	Surf to www.kernel.org and get linux-2.4.7.tar.gz from the kernel archives.

	Once you have pulled this file down and untar'ed it, 
	apply the proper patch from the freebios/src/kernel_patches 
	directory. (tar xzvf linux-2.4.7.tar.gz; mv linux linux_2.4.7; cd /usr/src/linux_2.4.7) 
		
	The patch is:

        linux-2.4.7-sis.patch

	Your patch command will look like this:
	 
	patch -p1 < /usr/src/freebios/src/kernel_patches/linux-2.4.7-sis.patch
	Now cp /usr/src/freebios/src/kernel_patches/config-2.4.7-sis to .config
	make oldconfig
	make dep
	make vmlinux
	make modules
	make modules_install
	make bzdisk (You should test boot this floppy disk just to be safe)

	You now have a kernel for LinuxBIOS. Now, try booting the floppy to ensure that
	the LinuxBIOS kernel works. On our machine, we received a few errors but the
	machine did boot completely. We were without networking, so you certainly want
	to keep your original kernel if you need to boot back to pull files of the Internet.

	If you want, you can also install this kernel on the LinuxBIOS machine,
	and install the modules as well, since you will need the Disk On Chip
	modules to burn the Disk On Chip part. In our experience, we found it's easiest to
	work within your stock kernel and only boot the LinuxBIOS kernel off the floppy 
	when you're ready to burn the DOC.

Step 4)

	You now need to figure out where you want to put your build images. We used /usr/src/build
	a directory we created.
 
	DO NOT PUT THESE IN THE LinuxBIOS SOURCE TREE. 
	
	You want to put them OUTSIDE THE TREE, so you can always
	cvs update 	and not lose any of your build directory. LinuxBIOS does all the builds in
	a single directory, much as BSD does. 
	
	To build LinuxBIOS requires a Makefile, a crt0.S file, and a ld script
	file. These are generated by a config tool located in 
	freebios/utils/config. 	The config tool is a Python program originally written by 
	Dean Risinger of the ACL. 	

	To build the initial Makefile, assembly stub, and ld script, 
	you need to build a config file, run the config tool,
	cd to the build directory, and type 'make'. That said, first create your config file using
	the text editor of your choice. This file can be located anywhere... we used /usr/src/sis.config.

	Here is the config file for the k7SEM:

	# This will dump all the files in /usr/src/build
	target /usr/src/build

	# Elitegroup K7sem
	mainboard elitegroup/k7sem

	# Request this level of debugging output
	option DEFAULT_CONSOLE_LOGLEVEL=8
	# At a maximum only compile in this level of debugging
	option MAXIMUM_CONSOLE_LOGLEVEL=8
	#option DEBUG

	# Enable Serial Console for debugging
	# It will come up at 115200,8n1
	option SERIAL_CONSOLE=1
	option SERIAL_POST=1

	# Use the internal VGA frame buffer device
	option HAVE_FRAMEBUFFER=1

	#floppy is nice
	option MUST_ENABLE_FLOPPY=1

	# We're using disk on chip. Tell it where to find the docipl code
	option USE_DOC_MIL=1
	docipl northsouthbridge/sis/730/ipl.S

	# Path to your kernel (vmlinux)
	# NOTE; you need a path to your kernel here.
	linux /usr/src/linux_2.4.7/

	# Kernel command line parameters
	commandline root=/dev/hda3 single console=ttyS0,115200 console=tty0 video=sisfb:1024x768-8 at 60
	
	The target command names the build directory. The mainboard command
	names the mainboard. We have set options for a serial console which
	will get you LinuxBIOS debug output via the serial port. You have to tell it where
	to find the vmlinux	you build (the 'linux' command); and finally you need a commandline
	for now. 

	To run the config tool, you need two arguments: the first is the
	name of a config file, and the second is the (absolute) pathname
	of the freebios source tree. The config tool is NLBConfig.py. Make sure you use that and not
	LBConfig.py, the older version. 

	Now, just run the configuration tool to generate the Makefile. 

 	python /usr/src/freebios/util/config/NLBConfig.py sis.config /usr/src/freebios

	Assuming no errors, cd into /usr/src/build and type make. If you receive an error message
	then verify your configuration file is correct and/or consult the LinuxBios website.

	After running make, we now have three files to be loaded into the Disk On Chip. The first
	is called docipl. It is 512 bytes. The second is called LinuxBIOS.strip,
	and is the binary image of the LinuxBIOS that gets loaded into Doc. 
	The third file  is your kernel, and is stripped and compressed, 
	linux.bin.gz

	-rw-------    1 rminnich CIC-ACL       512 Dec 20 08:41 docipl
	-rwx------    1 rminnich CIC-ACL     33494 Dec 20 08:41 LinuxBIOS.strip*
	-rwx------    1 rminnich CIC-ACL    756069 Dec 20 08:41 linux.bin.gz*

	Ensure that all of the above files exist. Very important: mv linux.bin.gz vmlinux.bin.gz
	This is your compressed kernel image.

	You're now ready to burn the Disk On Chip, but first .... 

Step 5) Get the MTD utilities from http://www.linux-mtd.infradead.org/ 
	cd /usr/src (this is going to create another sub-directory)
	cvs -d :pserver:anoncvs at cvs.infradead.org:/home/cvs login (password: anoncvs)
	cvs -d :pserver:anoncvs at cvs.infradead.org:/home/cvs co mtd
	cd /mtd/util/
    	sh -x MAKEDEV
	make
	This creates the 'erase' utility.
	Install the erase utility where it is in your path.
	One such method is to use vi and edit the .bashrc
		PATH=$PATH:/usr/src/mtd/util; export PATH
	. .bashrc (run in the same directory as the .bashrc file is located) 

Step 6) Set up flash_on utility. cd /usr/src/freebios/util/sis/
	flash_on.c is found in freebios/util/sis/flash_on.c
	Make the utility, and put it in your path.
	Path in the .bashrc file should look like this now:
	PATH=$PATH:/usr/src/mtd/util:/usr/src/freebios/util/sis; export PATH
	Make sure to re-read the path by running the file again:
	. .bashrc
	echo $PATH to ensure both directories are included.

Step 7) 
	NOTE: BE ADVISED THAT THIS STEP CAN HURT OR KILL YOU!
	YOU ARE WORKING WITH A POWERED-ON COMPUTER AT THIS POINT. 
	THE COMPUTER NEEDS TO BE OPENED  UP, AND YOU NEED TO REMOVE A CHIP
	WHILE THE COMPUTER IS ON. IF YOU HAVE NOT DONE THIS TYPE OF WORK, DO NOT DO IT!
	WE TAKE NO RESPONSIBILITY FOR ANYTHING THAT HAPPENS AT THIS STEP.
	BEFORE DOING THIS STEP WITH POWER ON, YOU SHOULD TRY IT WITH POWER OFF.

	Reboot the machine and boot off the floppy. You need to be running the LinuxBIOS
	kernel with all the loaded DOC modules to successfully burn the chip. 

	Open the machine (LEAVE THE POWER ON), yank the flash, and 
	plug in the DoC. We recommend you practice this first with the 
	power off. Make sure that whatever you do, you are not shorting 
	things out. Avoid using a metal tool!

	NOTE: YOU CAN HURT YOURSELF AT THIS STEP. We can't take any
	responsibility for what happens to you here. If you haven't 
	done this, or are not trained, or have a history of getting
	hurt by hardware, DON'T DO IT.

Step 8) cd to /usr/src/build (imperative -- won't burn correctly unless you run the script
	while inside this directory)
	Run /usr/src/freebios/util/mtd/burn_mtd
	
Step 9) POWER OFF THE MACHINE. DoC requires this. 
	Turn it back on. LinuxBIOS should come up in a few seconds. 

DEBUGGING
___________

   If you can, hook up a serial line to your LinuxBIOS machine, 
   settings 115200,8n1 and see what messages come out. If you can capture them, send them
   to linuxbios at lanl.gov with a description of your problem. 




From stepan at suse.de  Mon Jun 23 14:06:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Jun 23 14:06:01 2003
Subject: new config language.
In-Reply-To: <Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov>; from rminnich@lanl.gov on Mon, Jun 23, 2003 at 10:07:40AM -0600
References: <m3u1akgv0a.fsf@maxwell.lnxi.com> <Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov>
Message-ID: <20030623201301.A28590@suse.de>

* ron minnich <rminnich at lanl.gov> [030623 18:07]:
> On 20 Jun 2003, Eric W. Biederman wrote:
> 
> > The modules I think you want are:
> > mtdchar
> > amd76x
> 
> hmm, not on an 8111.

in /dev/bios 8111 shares the code with the amd 7xx chipsets..
Maybe some other problem? What board is it?

-- 
Architecture Team
    SuSE Linux AG


From rminnich at lanl.gov  Mon Jun 23 14:22:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 14:22:00 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <2003623184715.410024@techfreakz>
Message-ID: <Pine.LNX.4.44.0306231228120.1964-100000@maxroach.lanl.gov>

ok, stick with the howto for now. 

We need howto with a mkelfimage in it.

ron



From rminnich at lanl.gov  Mon Jun 23 14:28:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 14:28:01 2003
Subject: new config language.
In-Reply-To: <20030623201301.A28590@suse.de>
Message-ID: <Pine.LNX.4.44.0306231234020.1964-100000@maxroach.lanl.gov>

On Mon, 23 Jun 2003, Stefan Reinauer wrote:

> in /dev/bios 8111 shares the code with the amd 7xx chipsets..
> Maybe some other problem? What board is it?

it's an ARIMA HDAMA. 

If the code really is the same then there is an easy fix.

I will try just adding the 8111 vendor/device to the set of devices it 
looks for. 

ron



From rminnich at lanl.gov  Mon Jun 23 15:57:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 15:57:00 2003
Subject: linuxbios
In-Reply-To: <3EF74D08.8060601@supereva.it>
Message-ID: <Pine.LNX.4.44.0306231403550.2560-100000@maxroach.lanl.gov>

On Mon, 23 Jun 2003, rickytato wrote:

> Hi Ron, I'm rickytato, I want to know if the pc-chips M830LR are
> supported by linuxbios. on the web site the status are unstable, but I
> think that web site aren't upgrade.

I am not sure any more. We'll have to ask the list. Who owns that board?

ron



From tobby at tobbynet.de  Mon Jun 23 16:48:01 2003
From: tobby at tobbynet.de (Tobias Kloss)
Date: Mon Jun 23 16:48:01 2003
Subject: no docipl after make
Message-ID: <3ECE3DC4.40900@tobbynet.de>

Hi,

i have an old gigabyte board with the 430TX chipset on it. For 
configuration i used the example from 
src/mainborads/digitallogic/smartcore-p5/config.example, because it uses 
the 430tx as northbridge and the piix4 as southbridge as my board does.
After running the python program, i started to make a romimage. But i 
don't get the docipl file after make finshed. What can i do?

Thanks,
Tobias Kloss

This is my lspci output:
00:00.0 Host bridge: Intel Corp. 430TX - 82439TX MTXC (rev 01)
00:07.0 ISA bridge: Intel Corp. 82371AB/EB/MB PIIX4 ISA (rev 01)
00:07.1 IDE interface: Intel Corp. 82371AB/EB/MB PIIX4 IDE (rev 01)
00:07.2 USB Controller: Intel Corp. 82371AB/EB/MB PIIX4 USB (rev 01)
00:07.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 01)
00:08.0 VGA compatible controller: Matrox Graphics, Inc. MGA 2164W 
[Millennium II]
00:0a.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone] 
(rev 24)



From jcarr at wit.org  Mon Jun 23 16:50:04 2003
From: jcarr at wit.org (Jeff Carr)
Date: Mon Jun 23 16:50:04 2003
Subject: Laptops?
In-Reply-To: <Pine.LNX.4.44.0305221512350.20341-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0305221512350.20341-100000@maxroach.lanl.gov>
Message-ID: <1053648071.976.95.camel@jcenote>

I'm lucky enough to have one of these and would be willing to
experiment. I have experience with working with firmware(u-boot in
particular). I have to figure out a way to open up the case enough to
see if I can find out what kind of flash chip is on this board. I've
heard of boards with dual-flash parts so if you screw up one you can
still boot. Is there any strategy out there for doing this with pc
motherboards yet? Don't tell me I have to lift the flash to burn it and
put it back on the board...
Jeff

On Thu, 2003-05-22 at 16:13, ron minnich wrote:
> On Thu, 8 May 2003, Klemens Mantzos wrote:
> 
> > What i want to know is: "Does anybody think about using in 
> > Workstations/Laptops?????".
> 
> 
> we've been trying to find a good laptop for a few years for this purpose.
> 
> One possibility is the $700 lindows laptop, which does use a supported 
> chipset.
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 




From David.Eliasson at delagardie.lidkoping.se  Mon Jun 23 16:50:13 2003
From: David.Eliasson at delagardie.lidkoping.se (David Eliasson)
Date: Mon Jun 23 16:50:13 2003
Subject: LinuxBios PPC-support.. U-Boot project
Message-ID: <sedceb64.084@gate2.delagardie.lidkoping.se>

I read on the linuxbios webpage about PPC-support.. Aren t you guys
aware of the U-boot project? They ve been running the GNU Linux kernel
2.4.19 and 2.4 21 in firmware for a while now.. Maybe I m just missing
something, but I thought some merging of efforts might be in place..
http://sourceforge.net/projects/u-boot/

Regards

/David




From bitz-loetsysteme at t-online.de  Mon Jun 23 16:50:21 2003
From: bitz-loetsysteme at t-online.de (Martin Bitz)
Date: Mon Jun 23 16:50:21 2003
Subject: ASUS CUA and Linuxbios
Message-ID: <3EECD11E.7040600@t-online.de>

Hello everybody.

I?m new to Linuxbios and to the list.
In german Linux Magazin I read an article about this project.
I was so fascinated that I bought at EBAY an ASUS CUA motherboard, an 
Intel PIII 700 and a DOC MD 2800-D08 X.
I build Linuxbios refering to the HOWTO for my motherboard.
Burning the DOC seems to work okay for me.
But when I reboot, nothing happens. Connecting to the ASUS with another 
PC using minicom provides no output at all.
As I`m not very familiar to programming and the basics of Linuxbios I 
hope to get some help from the list. Maybe someone who has this board 
running with Linuxbios can send me the files for the DOC so that I can 
get a first success.
I also attach the output I got when I build Linuxbios and the configfile.
Maybe somebody of you can find a mistake there.

Thanks in advance
Martin Bitz




# Sample config file for ACER M1631 CHIPSET ON A ASUS
# with DoC Millennium (as root)

# This will make a target directory of ./asus-cua
target asus-cua

# ASUS CUA  main board
mainboard asus/cua

# ****************** NEED CORRECT DOC IPL
# use DOC MIL
option USE_DOC_MIL
docipl mainboard/asus/cua/ipl.S

# Enable Serial Console for debugging
option SERIAL_CONSOLE=1

# Enable IRQ Routing table stuff
option HAVE_PIRQ_TABLE=1

# Enable MicroCode update and L2 Cache init for PII and PIII
option UPDATE_MICROCODE
option CONFIGURE_L2_CACHE

# Use the internal VGA frame buffer device - DISABLED FOR NOW!
# option HAVE_FRAMEBUFFER

# I want that floppy ...
option MUST_ENABLE_FLOPPY

# Path to your kernel (vmlinux)
linux /mnt/disk/linux

commandline root=/dev/hda5 console=ttyS0,115200 floppy=nodma










[root at martin linux]# python /mnt/disk/freebios/util/config/NLBConfig.py 
/mnt/disk/linuxbios/asus-config /mnt/disk/freebios
Will place Makefile, crt0.S, etc. in  /mnt/disk/linuxbios/asus-cua
Process config file:  /mnt/disk/freebios/src/mainboard/asus/cua/Config
Now Process the  i386  base files
Added ldscript init file: 
/mnt/disk/freebios/src/arch/i386/config/ldscript.base
Process config file:  /mnt/disk/freebios/src/config/Config
Process config file:  /mnt/disk/freebios/src/lib/Config
Process config file:  /mnt/disk/freebios/src/boot/Config
Process config file:  /mnt/disk/freebios/src/rom/Config
Process config file:  /mnt/disk/freebios/src/pc80/Config
Process config file:  /mnt/disk/freebios/src/pc80/ide/Config
Process config file:  /mnt/disk/freebios/src/arch/i386/Config
Process config file:  /mnt/disk/freebios/src/arch/i386/boot/Config
Process config file:  /mnt/disk/freebios/src/arch/i386/lib/Config
Process config file:  /mnt/disk/freebios/src/arch/i386/smp/Config
Added mainboard init file:  cpu/i386/entry16.inc
Added mainboard init file:  cpu/i386/entry32.inc
Added ldscript init file:  /mnt/disk/freebios/src/cpu/i386/entry16.lds
Added ldscript init file:  /mnt/disk/freebios/src/cpu/i386/entry32.lds
Added mainboard init file:  northbridge/acer/m1631/chipset_init.inc
Added mainboard init file:  superio/acer/m1535/setup_serial.inc
Added mainboard init file:  pc80/serial.inc
Added mainboard init file:  arch/i386/lib/console.inc
Process config file:  /mnt/disk/freebios/src/northbridge/acer/m1631/Config
Process config file:  /mnt/disk/freebios/src/southbridge/acer/m1535/Config
Added mainboard init file:  cpu/p6/earlymtrr.inc
Process config file:  /mnt/disk/freebios/src/cpu/p5/Config
Process config file:  /mnt/disk/freebios/src/cpu/p6/Config
===> Warning:
/mnt/disk/linuxbios/asus-config:12: Invalid option specifcation: 
USE_DOC_MIL assuming you meant USE_DOC_MIL=1
===> Warning:
/mnt/disk/linuxbios/asus-config:22: Invalid option specifcation: 
UPDATE_MICROCODE assuming you meant UPDATE_MICROCODE=1
===> Warning:
/mnt/disk/linuxbios/asus-config:23: Invalid option specifcation: 
CONFIGURE_L2_CACHE assuming you meant CONFIGURE_L2_CACHE=1
===> Warning:
/mnt/disk/linuxbios/asus-config:29: Invalid option specifcation: 
MUST_ENABLE_FLOPPY assuming you meant MUST_ENABLE_FLOPPY=1
Creating /mnt/disk/linuxbios/asus-cua/Makefile.settings
Creating /mnt/disk/linuxbios/asus-cua/Makefile
Creating /mnt/disk/linuxbios/asus-cua/crt0_includes.h
Creating /mnt/disk/linuxbios/asus-cua/nsuperio.c
Creating /mnt/disk/linuxbios/asus-cua/LinuxBIOSDoc.config
[root at martin linux]# cd  ..
[root at martin disk]# cd linuxbios
[root at martin linuxbios]# cd asus-cua
[root at martin asus-cua]#
[root at martin asus-cua]# make
Makefile:507: Warnung: ?berschreibe die Kommandos f?r das Target 
?keyboard.o?.
Makefile:417: Warnung: Ignoriere alte Kommandos f?r das Target ?keyboard.o?.
cp /mnt/disk/freebios/src/arch/i386/config/crt0.base crt0.S
gcc -x assembler-with-cpp -DASSEMBLY -E ... crt0.S > crt0.s
gcc ... -o crt0.o crt0.s
crt0.s: Assembler messages:
crt0.s:689: Warning: indirect jmp without `*'
gcc ... -o docmil_fill_inbuf.o 
/mnt/disk/freebios/src/rom/docmil_fill_inbuf.c
gcc ... -o linuxbiosmain.o /mnt/disk/freebios/src/lib/linuxbiosmain.c
gcc ... -o linuxpci.o /mnt/disk/freebios/src/lib/linuxpci.c
/mnt/disk/freebios/src/lib/linuxpci.c:13: warning: `rcsid' defined but 
not used
gcc ... -o newpci.o /mnt/disk/freebios/src/lib/newpci.c
/mnt/disk/freebios/src/lib/newpci.c:14: warning: `rcsid' defined but not 
used
gcc ... -o clog2.o /mnt/disk/freebios/src/lib/clog2.c
gcc ... -o printk.o /mnt/disk/freebios/src/lib/printk.c
/mnt/disk/freebios/src/lib/printk.c:9: warning: `rcsid' defined but not used
gcc ... -o serial_subr.o /mnt/disk/freebios/src/lib/serial_subr.c
/mnt/disk/freebios/src/lib/serial_subr.c:2: warning: `rcsid' defined but 
not used
gcc ... -o subr.o /mnt/disk/freebios/src/lib/subr.c
/mnt/disk/freebios/src/lib/subr.c:8: warning: `rcsid' defined but not used
gcc ... -o vsprintf.o /mnt/disk/freebios/src/lib/vsprintf.c
/mnt/disk/freebios/src/lib/vsprintf.c:13: warning: `rcsid' defined but 
not used
gcc ... -o memset.o /mnt/disk/freebios/src/lib/memset.c
gcc ... -o memcpy.o /mnt/disk/freebios/src/lib/memcpy.c
gcc ... -o memcmp.o /mnt/disk/freebios/src/lib/memcmp.c
gcc ... -o malloc.o /mnt/disk/freebios/src/lib/malloc.c
gcc ... -o do_inflate.o /mnt/disk/freebios/src/lib/do_inflate.c
In file included from /mnt/disk/freebios/src/lib/do_inflate.c:67:
/mnt/disk/freebios/src/lib/inflate.c: In function `gunzip':
/mnt/disk/freebios/src/lib/inflate.c:1100: warning: value computed is 
not used
/mnt/disk/freebios/src/lib/inflate.c:1101: warning: value computed is 
not used
/mnt/disk/freebios/src/lib/inflate.c:1102: warning: value computed is 
not used
gcc ... -o delay.o /mnt/disk/freebios/src/lib/delay.c
gcc ... -o compute_ip_checksum.o 
/mnt/disk/freebios/src/lib/compute_ip_checksum.c
gcc ... -o version.o /mnt/disk/freebios/src/lib/version.c
gcc ... -o keyboard.o /mnt/disk/freebios/src/pc80/keyboard.c
/mnt/disk/freebios/src/pc80/keyboard.c:2: warning: `rcsid' defined but 
not used
gcc ... -o mc146818rtc.o /mnt/disk/freebios/src/pc80/mc146818rtc.c
/mnt/disk/freebios/src/pc80/mc146818rtc.c: In function `rtc_init':
/mnt/disk/freebios/src/pc80/mc146818rtc.c:139: warning: unused variable `i'
gcc ... -o isa-dma.o /mnt/disk/freebios/src/pc80/isa-dma.c
gcc ... -o ide.o /mnt/disk/freebios/src/pc80/ide/ide.c
gcc ... -o boot.o /mnt/disk/freebios/src/arch/i386/boot/boot.c
gcc ... -o linuxbios_table.o 
/mnt/disk/freebios/src/arch/i386/boot/linuxbios_table.c
/mnt/disk/freebios/src/arch/i386/boot/linuxbios_table.c: In function 
`lb_strings':
/mnt/disk/freebios/src/arch/i386/boot/linuxbios_table.c:122: warning: 
assignment from incompatible pointer type
/mnt/disk/freebios/src/arch/i386/boot/linuxbios_table.c: In function 
`write_linuxbios_table':
/mnt/disk/freebios/src/arch/i386/boot/linuxbios_table.c:230: warning: 
unused variable `rec_src'
/mnt/disk/freebios/src/arch/i386/boot/linuxbios_table.c:230: warning: 
unused variable `rec_dest'
gcc ... -o i386_subr.o /mnt/disk/freebios/src/arch/i386/lib/i386_subr.c
gcc ... -o params.o /mnt/disk/freebios/src/arch/i386/lib/params.c
/mnt/disk/freebios/src/arch/i386/lib/params.c:30: warning: `rcsid' 
defined but not used
gcc ... -o hardwaremain.o 
/mnt/disk/freebios/src/arch/i386/lib/hardwaremain.c
/mnt/disk/freebios/src/arch/i386/lib/hardwaremain.c:32: warning: `rcsid' 
defined but not used
gcc ... -o pirq_routing.o 
/mnt/disk/freebios/src/arch/i386/lib/pirq_routing.c
gcc ... -o c_start.o c_start.s
c_start.s: Assembler messages:
c_start.s:16: Warning: using `%eax' instead of `%ax' due to `l' suffix
gcc ... -o northbridge.o 
/mnt/disk/freebios/src/northbridge/acer/m1631/northbridge.c
gcc ... -o southbridge.o 
/mnt/disk/freebios/src/southbridge/acer/m1535/southbridge.c
/mnt/disk/freebios/src/southbridge/acer/m1535/southbridge.c: In function 
`southbridge_fixup':
/mnt/disk/freebios/src/southbridge/acer/m1535/southbridge.c:10: warning: 
unused variable `c'
gcc ... -o superio.o /mnt/disk/freebios/src/superio/acer/m1535/superio.c
/mnt/disk/freebios/src/superio/acer/m1535/superio.c:2: warning: `rcsid' 
defined but not used
gcc ... -o mainboard.o /mnt/disk/freebios/src/mainboard/asus/cua/mainboard.c
gcc ... -o irq_tables.o 
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:24: warning: 
excess elements in array initializer
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:24: warning: 
(near initialization for `intel_irq_routing_table.slots')
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:25: warning: 
excess elements in array initializer
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:25: warning: 
(near initialization for `intel_irq_routing_table.slots')
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:26: warning: 
excess elements in array initializer
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:26: warning: 
(near initialization for `intel_irq_routing_table.slots')
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:27: warning: 
excess elements in array initializer
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:27: warning: 
(near initialization for `intel_irq_routing_table.slots')
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:28: warning: 
excess elements in array initializer
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:28: warning: 
(near initialization for `intel_irq_routing_table.slots')
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:29: warning: 
excess elements in array initializer
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:29: warning: 
(near initialization for `intel_irq_routing_table.slots')
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:30: warning: 
excess elements in array initializer
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:30: warning: 
(near initialization for `intel_irq_routing_table.slots')
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:31: warning: 
excess elements in array initializer
/mnt/disk/freebios/src/mainboard/asus/cua/irq_tables.c:31: warning: 
(near initialization for `intel_irq_routing_table.slots')
gcc ... -o cpuid.o /mnt/disk/freebios/src/cpu/p5/cpuid.c
/mnt/disk/freebios/src/cpu/p5/cpuid.c:3: warning: `rcsid' defined but 
not used
gcc ... -o microcode.o /mnt/disk/freebios/src/cpu/p6/microcode.c
/mnt/disk/freebios/src/cpu/p6/microcode.c:7: warning: `rcsid' defined 
but not used
gcc ... -o mtrr.o /mnt/disk/freebios/src/cpu/p6/mtrr.c
/mnt/disk/freebios/src/cpu/p6/mtrr.c: In function `set_var_mtrr':
/mnt/disk/freebios/src/cpu/p6/mtrr.c:132: warning: unused variable `tmp'
/mnt/disk/freebios/src/cpu/p6/mtrr.c: At top level:
/mnt/disk/freebios/src/cpu/p6/mtrr.c:29: warning: `rcsid' defined but 
not used
gcc ... -o l2_cache.o /mnt/disk/freebios/src/cpu/p6/l2_cache.c
/mnt/disk/freebios/src/cpu/p6/l2_cache.c:33: warning: `rcsid' defined 
but not used
rm -f linuxbios.a
ar cr linuxbios.a  linuxbiosmain.o linuxpci.o newpci.o clog2.o printk.o 
serial_subr.o subr.o vsprintf.o memset.o memcpy.o memcmp.o malloc.o 
do_inflate.o delay.o compute_ip_checksum.o version.o keyboard.o 
mc146818rtc.o isa-dma.o ide.o boot.o linuxbios_table.o i386_subr.o 
params.o hardwaremain.o pirq_routing.o c_start.o northbridge.o 
southbridge.o superio.o mainboard.o irq_tables.o keyboard.o cpuid.o 
microcode.o mtrr.o l2_cache.o
gcc -nostdlib -r -o linuxbios_c.o c_start.o  docmil_fill_inbuf.o 
linuxbios.a /usr/lib/gcc-lib/i586-mandrake-linux/2.96/libgcc.a
perl -e 'foreach $var (split(" ", $ENV{VARIABLES})) { if ($ENV{$var} =~ 
m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$/) { print "$var = $ENV{$var};\n"; 
}}' > ldoptions
gcc -nostdlib -nostartfiles -static -o linuxbios_c -T 
/mnt/disk/freebios/src/config/linuxbios_c.ld linuxbios_c.o
nm -n linuxbios_c | sort > linuxbios_c.map
objcopy -O binary linuxbios_c linuxbios_payload.bin
gcc -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 
-DENDIAN=0 /mnt/disk/freebios/util/nrv2b/nrv2b.c -o nrv2b
./nrv2b e linuxbios_payload.bin linuxbios_payload.nrv2b
input/output = 41188/22780 = 1.808
cp linuxbios_payload.nrv2b linuxbios_payload
echo "INCLUDE ldoptions" > ldscript.ld ; for file in 
/mnt/disk/freebios/src/arch/i386/config/ldscript.base 
/mnt/disk/freebios/src/cpu/i386/entry16.lds 
/mnt/disk/freebios/src/cpu/i386/entry32.lds ; do echo "INCLUDE $file" >> 
ldscript.ld ; done
gcc -nostdlib -nostartfiles -static -o linuxbios -T ldscript.ld crt0.o
nm -n linuxbios | sort > linuxbios.map
objcopy -O binary linuxbios linuxbios.strip
export size=`ls -l linuxbios.strip | (read p c u g size r ; echo $size)` ; \
echo $size ; \
dd if=linuxbios.strip of=linuxbios.rom bs=1 seek=`expr 65536 - $size`
24448
24448+0 Records ein
24448+0 Records aus
objcopy -O binary -R .note -R .comment -S /mnt/disk/linux/vmlinux linux.bin
gzip -f -3 linux.bin
dd conv=sync bs=458752 if=linux.bin.gz of=payload.block
1+1 Records ein
2+0 Records aus
cat payload.block linuxbios.rom > romimage
gcc  -I/mnt/disk/freebios/src/include 
-I/mnt/disk/freebios/src/arch/i386/include 
-I/usr/lib/gcc-lib/i586-mandrake-linux/2.96/include -DCC='gcc' 
-DCMD_LINE='"root=/dev/hda5 console=ttyS0,115200 floppy=nodma"' 
-DCONFIGURE_L2_CACHE='1' -DCONFIG_ASSIGNIRQ='0' -DCONFIG_COMPRESS='1' 
-DCONFIG_LOGICAL_CPUS='1' -DCONFIG_MC146818RTC='1' 
-DCONFIG_PCIBIOS_IRQ='0' -DCONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2='0' 
-DCONFIG_UNCOMPRESSED='0' 
-DCRT0='/mnt/disk/freebios/src/arch/i386/config/crt0.base' 
-DENABLE_FIXED_AND_VARIABLE_MTRRS='1' -DFINAL_MAINBOARD_FIXUP='1' 
-DHAVE_PIRQ_TABLE='1' -DHEAP_SIZE='0x40000' -DHOSTCC='gcc' 
-DINTEL_PPRO_MTRR='1' -DLINUXBIOS_ASSEMBLER='GNU assembler version 
2.10.91 (i586-mandrake-linux) using BFD version 2.10.1.0.2' 
-DLINUXBIOS_BUILD='Sam Jun 14 23:11:58 UTC 2003' 
-DLINUXBIOS_COMPILER='gcc version 2.96 20000731 (Linux-Mandrake 8.0 
2.96-0.48mdk)' -DLINUXBIOS_COMPILE_BY='root' 
-DLINUXBIOS_COMPILE_DOMAIN='bitz.de' 
-DLINUXBIOS_COMPILE_HOST='martin.bitz.de' 
-DLINUXBIOS_COMPILE_TIME='23:11:58' -DLINUXBIOS_LINKER='GNU ld version 
2.10.91 (with BFD 2.10.1.0.2)' -DLINUXBIOS_VERSION='1.0.0' 
-DMAINBOARD_PART_NUMBER='cua' -DMAINBOARD_VENDOR='asus' -DMAX_CPUS='1' 
-DMEMORY_HOLE='1' -DMUST_ENABLE_FLOPPY='1' -DOBJCOPY='objcopy' 
-DPAYLOAD_SIZE='458752' -DROM_IMAGE_SIZE='65536' -DSERIAL_CONSOLE='1' 
-DSTACK_SIZE='0x2000' -DUPDATE_MICROCODE='1' -DUSE_DOC='1' 
-DUSE_DOC_2000_TSOP='0' -DUSE_DOC_MIL='1' -D_RAMBASE='0x4000' 
-D_ROMBASE='0x80000' -Di586='1' -Di686='1' -Os -nostdinc -nostdlib 
-fno-builtin  -Wall -I/mnt/disk/freebios/src/mainboard/asus/cua -c 
/mnt/disk/freebios/src/mainboard/asus/cua/ipl.S
objcopy -O binary -R .note -R .comment -S ipl.o docipl
[root at martin asus-cua]# ls -l
insgesamt 2962
-rw-r--r--    1 root     root        29396 Jun 14 23:07 LinuxBIOSDoc.config
-rw-r--r--    1 root     root        22468 Jun 14 23:07 Makefile
-rw-r--r--    1 root     root         2732 Jun 14 23:07 Makefile.settings
-rw-r--r--    1 root     root         1408 Jun 14 23:12 boot.o
-rw-r--r--    1 root     root          948 Jun 14 23:12 c_start.o
-rw-r--r--    1 root     root         1789 Jun 14 23:12 c_start.s
-rw-r--r--    1 root     root          832 Jun 14 23:11 clog2.o
-rw-r--r--    1 root     root          967 Jun 14 23:12 
compute_ip_checksum.o
-rw-r--r--    1 root     root         5744 Jun 14 23:12 cpuid.o
-rw-r--r--    1 root     root         3751 Jun 14 23:11 crt0.S
-rw-r--r--    1 root     root         3760 Jun 14 23:11 crt0.o
-rw-r--r--    1 root     root        16679 Jun 14 23:11 crt0.s
-rw-r--r--    1 root     root          258 Jun 14 23:07 crt0_includes.h
-rw-r--r--    1 root     root          940 Jun 14 23:12 delay.o
-rw-r--r--    1 root     root         9124 Jun 14 23:12 do_inflate.o
-rw-r--r--    1 root     root          512 Jun 14 23:12 docipl
-rw-r--r--    1 root     root         3072 Jun 14 23:11 docmil_fill_inbuf.o
-rw-r--r--    1 root     root         3324 Jun 14 23:12 hardwaremain.o
-rw-r--r--    1 root     root         1272 Jun 14 23:12 i386_subr.o
-rw-r--r--    1 root     root         4184 Jun 14 23:12 ide.o
-rw-r--r--    1 root     root         1816 Jun 14 23:12 ipl.o
-rw-r--r--    1 root     root         1013 Jun 14 23:12 irq_tables.o
-rw-r--r--    1 root     root          767 Jun 14 23:12 isa-dma.o
-rw-r--r--    1 root     root         1224 Jun 14 23:12 keyboard.o
-rw-r--r--    1 root     root         5932 Jun 14 23:12 l2_cache.o
-rw-r--r--    1 root     root          616 Jun 14 23:12 ldoptions
-rw-r--r--    1 root     root          184 Jun 14 23:12 ldscript.ld
-rwxr-xr-x    1 root     root       474511 Jun 14 23:12 linux.bin.gz*
-rwxr-xr-x    1 root     root        31685 Jun 14 23:12 linuxbios*
-rw-r--r--    1 root     root       100514 Jun 14 23:12 linuxbios.a
-rw-r--r--    1 root     root         2151 Jun 14 23:12 linuxbios.map
-rw-r--r--    1 root     root        65536 Jun 14 23:12 linuxbios.rom
-rwxr-xr-x    1 root     root        24448 Jun 14 23:12 linuxbios.strip*
-rwxr-xr-x    1 root     root       335208 Jun 14 23:12 linuxbios_c*
-rw-r--r--    1 root     root         8738 Jun 14 23:12 linuxbios_c.map
-rw-r--r--    1 root     root        62887 Jun 14 23:12 linuxbios_c.o
-rw-r--r--    1 root     root        22784 Jun 14 23:12 linuxbios_payload
-rwxr-xr-x    1 root     root        41188 Jun 14 23:12 
linuxbios_payload.bin*
-rw-r--r--    1 root     root        22784 Jun 14 23:12 
linuxbios_payload.nrv2b
-rw-r--r--    1 root     root         3856 Jun 14 23:12 linuxbios_table.o
-rw-r--r--    1 root     root         2356 Jun 14 23:11 linuxbiosmain.o
-rw-r--r--    1 root     root         7948 Jun 14 23:11 linuxpci.o
-rw-r--r--    1 root     root         1064 Jun 14 23:12 mainboard.o
-rw-r--r--    1 root     root         1528 Jun 14 23:11 malloc.o
-rw-r--r--    1 root     root         1548 Jun 14 23:12 mc146818rtc.o
-rw-r--r--    1 root     root          784 Jun 14 23:11 memcmp.o
-rw-r--r--    1 root     root          780 Jun 14 23:11 memcpy.o
-rw-r--r--    1 root     root          772 Jun 14 23:11 memset.o
-rw-r--r--    1 root     root         5652 Jun 14 23:12 microcode.o
-rw-r--r--    1 root     root         3092 Jun 14 23:12 mtrr.o
-rw-r--r--    1 root     root         9388 Jun 14 23:11 newpci.o
-rw-r--r--    1 root     root         2448 Jun 14 23:12 northbridge.o
-rwxr-xr-x    1 root     root        23461 Jun 14 23:12 nrv2b*
-rw-r--r--    1 root     root           81 Jun 14 23:07 nsuperio.c
-rw-r--r--    1 root     root         1352 Jun 14 23:12 params.o
-rw-r--r--    1 root     root       917504 Jun 14 23:12 payload.block
-rw-r--r--    1 root     root         1144 Jun 14 23:12 pirq_routing.o
-rw-r--r--    1 root     root         1268 Jun 14 23:11 printk.o
-rw-r--r--    1 root     root       983040 Jun 14 23:12 romimage
-rw-r--r--    1 root     root         1334 Jun 14 23:11 serial_subr.o
-rw-r--r--    1 root     root         1484 Jun 14 23:12 southbridge.o
-rw-r--r--    1 root     root         1448 Jun 14 23:11 subr.o
-rw-r--r--    1 root     root         1160 Jun 14 23:12 superio.o
-rw-r--r--    1 root     root         1531 Jun 14 23:12 version.o
-rw-r--r--    1 root     root         4464 Jun 14 23:11 vsprintf.o
[root at martin asus-cua]#



From rminnich at lanl.gov  Mon Jun 23 17:40:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 17:40:00 2003
Subject: Laptops?
In-Reply-To: <1053648071.976.95.camel@jcenote>
Message-ID: <Pine.LNX.4.44.0306231545460.2560-100000@maxroach.lanl.gov>

On 22 May 2003, Jeff Carr wrote:

> I'm lucky enough to have one of these and would be willing to
> experiment. I have experience with working with firmware(u-boot in
> particular). I have to figure out a way to open up the case enough to
> see if I can find out what kind of flash chip is on this board. I've
> heard of boards with dual-flash parts so if you screw up one you can
> still boot. Is there any strategy out there for doing this with pc
> motherboards yet? Don't tell me I have to lift the flash to burn it and
> put it back on the board...

on the RLX, Suravee put the linuxbios in the fallback area, and we ran 
normal bios in the normal area. Then when we tested we would tell it to 
use fallback (linuxbios) via a jumper. 

ron



From rminnich at lanl.gov  Mon Jun 23 17:41:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 17:41:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <sedceb64.084@gate2.delagardie.lidkoping.se>
Message-ID: <Pine.LNX.4.44.0306231546310.2560-100000@maxroach.lanl.gov>

On Tue, 3 Jun 2003, David Eliasson wrote:

> I read on the linuxbios webpage about PPC-support.. Aren t you guys
> aware of the U-boot project? 

Sure. 

> They've been running the GNU Linux kernel 2.4.19 and 2.4 21 in firmware
> for a while now.. Maybe I m just missing something, but I thought some
> merging of efforts might be in place..

I tried to have a conversation with somebody from u-boot about some sort
of merge, but it never got beyond the "why u-boot is better than
linuxbios" stage, so I dropped it.

ron



From agnew at cs.umd.edu  Mon Jun 23 17:42:00 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Mon Jun 23 17:42:00 2003
Subject: Laptops?
In-Reply-To: <1053648071.976.95.camel@jcenote>
Message-ID: <20030623173507.B23784-100000@www.missl.cs.umd.edu>

The best solution for that is the "BIOS Savior". Check the Linuxbios
archives or the web to learn more about that. On many of our boards, you
don't have to lift the prom to write it, they can be programmed in place,
you'll just have to lift them when you screw up (expect to) :) Or, there
are EPROM emulators. Many solutions..

However, I doubt your laptop has a DIP32 socket and is more likely to
have a TSOP40 directly on the board. You should definitely check first.

If you have a TSOP40, you will need to have the TSOP40 extracted and a
"coffin" put in its place. For that, some of us have used Century
Technology, Inc in San Fransisco (the guys name is Henry Ho,
hho at century-technology.com) though i'm sure there are other places which
will do it.

You can mail them just the mainboard, and they'll extract your TSOP40 and
put a socket in its place for a pretty reasonable price. That's just so
you can program your TSOP40 in a prom programmer, or get a backup TSOP40
so you'll have a working BIOS if you mess up and then you could switch
the two.


------------------
Adam Agnew
Independent Contractor
www.adamagnew.com


On 22 May 2003, Jeff Carr wrote:

> I'm lucky enough to have one of these and would be willing to
> experiment. I have experience with working with firmware(u-boot in
> particular). I have to figure out a way to open up the case enough to
> see if I can find out what kind of flash chip is on this board. I've
> heard of boards with dual-flash parts so if you screw up one you can
> still boot. Is there any strategy out there for doing this with pc
> motherboards yet? Don't tell me I have to lift the flash to burn it and
> put it back on the board...
> Jeff
>
> On Thu, 2003-05-22 at 16:13, ron minnich wrote:
> > On Thu, 8 May 2003, Klemens Mantzos wrote:
> >
> > > What i want to know is: "Does anybody think about using in
> > > Workstations/Laptops?????".
> >
> >
> > we've been trying to find a good laptop for a few years for this purpose.
> >
> > One possibility is the $700 lindows laptop, which does use a supported
> > chipset.
> >
> > ron
> >
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
>
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>






From YhLu at tyan.com  Mon Jun 23 17:49:00 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jun 23 17:49:00 2003
Subject: =?GB2312?B?tPC4tDogY29oZXJlbnQgaHlwZXJ0cmFuc3BvcnQgZW51bWVyYXRp?=
	=?GB2312?B?b24gb24gb3B0ZXJvbg==?=
Message-ID: <3174569B9743D511922F00A0C943142302C43FE8@TYANWEB>

Stefan,

I swap the 

	PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000070, //1C

The 4th line. It can go through setup_coherent_ht_domain.

But seems then both CPU all works. Please refer the attached.


Any problem.

Regards

Yinghai Lu

LinuxBIOS-1.1.02.0Fallback Mon Jun 23 21:39:13 EDT 2003 starting...
Bootstrap cpu
setting up coherent ht domain....
done.
P

LinuxBIOS-1.1.02.0Fallback Mon Jun 23 21:39:13 EDT 2003 starting...

I
 :L i0n0u:x0B1.I0O0S-
1.P1C.I0:2 .000F:a0l1.l0b1ac
k MoPnC IJ:u n0 02:30 2.2010:3
9:P1C3I :E D0T0 :2002.0031 s
:artPCinIg:. .0.0
 03Copying LinuxBIOS to ram.
.00
PCI: 00:04




From rminnich at lanl.gov  Mon Jun 23 17:59:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 17:59:00 2003
Subject: =?GB2312?B?tPC4tDogY29oZXJlbnQgaHlwZXJ0cmFuc3BvcnQgZW51bWVyYXRp?=
 =?GB2312?B?b24gb24gb3B0ZXJvbg==?=
In-Reply-To: <3174569B9743D511922F00A0C943142302C43FE8@TYANWEB>
Message-ID: <Pine.LNX.4.44.0306231605380.2560-100000@maxroach.lanl.gov>

what is pci_def.h BTW? I can't build now.

ron



From frannk_m1 at yahoo.com  Mon Jun 23 18:02:00 2003
From: frannk_m1 at yahoo.com (Frank)
Date: Mon Jun 23 18:02:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <Pine.LNX.4.44.0306231546310.2560-100000@maxroach.lanl.gov>
Message-ID: <20030623220909.65514.qmail@web13801.mail.yahoo.com>

I have been porting u-boot to different processors for 2 years
and just started looking at linuxbios. IMHO, u-boot is ok if you
are bringing up hardware for the first time and you need an
intermediate stage to peek and poke the hardware before trying
to bring up Linux. With u-boot you get to a command prompt
before booting Linux so you can examine things and complete the
conguration code before bypassing the command prompt and going
directly to Linux. If your hardware is stable and you don't need
the command prompt then linuxbios is probably the best way to
go...

--- ron minnich <rminnich at lanl.gov> wrote:
> On Tue, 3 Jun 2003, David Eliasson wrote:
> 
> > I read on the linuxbios webpage about PPC-support.. Aren t
> you guys
> > aware of the U-boot project? 
> 
> Sure. 
> 
> > They've been running the GNU Linux kernel 2.4.19 and 2.4 21
> in firmware
> > for a while now.. Maybe I m just missing something, but I
> thought some
> > merging of efforts might be in place..
> 
> I tried to have a conversation with somebody from u-boot about
> some sort
> of merge, but it never got beyond the "why u-boot is better
> than
> linuxbios" stage, so I dropped it.
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios


__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
http://sbc.yahoo.com


From YhLu at tyan.com  Mon Jun 23 18:05:00 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jun 23 18:05:00 2003
Subject: coherent hypertransport enumeration on opteron
Message-ID: <3174569B9743D511922F00A0C943142302C43FEB@TYANWEB>

I remember there is one type error on arch/i386/lib/pci_ops.c.

Change one *val --> value

How about your new build script progress?

Regards

Yinghai Lu
-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?6?23? 15:06
???: YhLu
??: Stefan Reinauer; ebiederman at lnxi.com; linuxbios at clustermatic.org
??: Re: ??: coherent hypertransport enumeration on opteron

what is pci_def.h BTW? I can't build now.

ron


From rminnich at lanl.gov  Mon Jun 23 18:06:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 18:06:00 2003
Subject: coherent hypertransport enumeration on opteron
In-Reply-To: <3174569B9743D511922F00A0C943142302C43FEB@TYANWEB>
Message-ID: <Pine.LNX.4.44.0306231612210.2560-100000@maxroach.lanl.gov>

On Mon, 23 Jun 2003, YhLu wrote:

> How about your new build script progress?

greg is making huge improvements and I think we will release this or next 
week for comments. 

ron



From gwatson at lanl.gov  Mon Jun 23 18:18:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Mon Jun 23 18:18:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <Pine.LNX.4.44.0306231546310.2560-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306231546310.2560-100000@maxroach.lanl.gov>
Message-ID: <p05210624bb1d2a8d65b8@[10.0.1.2]>

At 3:47 PM -0600 23/6/03, ron minnich wrote:
>On Tue, 3 Jun 2003, David Eliasson wrote:
>
>>  I read on the linuxbios webpage about PPC-support.. Aren t you guys
>>  aware of the U-boot project?
>
>Sure.
>
>>  They've been running the GNU Linux kernel 2.4.19 and 2.4 21 in firmware
>>  for a while now.. Maybe I m just missing something, but I thought some
>>  merging of efforts might be in place..
>
>I tried to have a conversation with somebody from u-boot about some sort
>of merge, but it never got beyond the "why u-boot is better than
>linuxbios" stage, so I dropped it.

I spent some time looking at PPCBoot (now called u-boot) before I did 
the PPC port of linuxbios, but in the end I didn't use much. Most of 
the "hard" stuff came from another open source bios project called 
GBios, particularly the PCI code.

The major advantages that linuxbios has over u-boot is the 
flexibility it provides in configuration management, and now that it 
has been ported to 3+ architectures, the architecture dependencies 
are particularly well defined.

Greg


From bari at onelabs.com  Mon Jun 23 18:30:00 2003
From: bari at onelabs.com (Bari Ari)
Date: Mon Jun 23 18:30:00 2003
Subject: Laptops?
References: <Pine.LNX.4.44.0305221512350.20341-100000@maxroach.lanl.gov> <1053648071.976.95.camel@jcenote>
Message-ID: <3EF78167.1060308@onelabs.com>

Jeff Carr wrote:

>I'm lucky enough to have one of these and would be willing to
>experiment. I have experience with working with firmware(u-boot in
>particular). I have to figure out a way to open up the case enough to
>see if I can find out what kind of flash chip is on this board. I've
>heard of boards with dual-flash parts so if you screw up one you can
>still boot. Is there any strategy out there for doing this with pc
>motherboards yet? Don't tell me I have to lift the flash to burn it and
>put it back on the board...
>Jeff
>
>  
>
What are they using in the Lindows laptop for a keyboard/power managment 
controller? The keyboard scan, power managment (power buttons, cover 
open/closed) is typically done with a micro with its own firmware. The 
chipset is the Via 8606 and 82C686B with the C3 Ezra CPU.

--Bari




From YhLu at tyan.com  Mon Jun 23 18:42:00 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jun 23 18:42:00 2003
Subject: =?GB2312?B?tPC4tDogY29oZXJlbnQgaHlwZXJ0cmFuc3BvcnQgZW51bWVyYXRp?=
	=?GB2312?B?b24gb24gb3B0ZXJvbg==?=
Message-ID: <3174569B9743D511922F00A0C943142302C43FFF@TYANWEB>

Change 0x19, 0x6c init code to 0x00000072, can goto Jumping step.

But this time, it just hung there and not reboot again and again.

I will init the RAM for second CPU.

Regards

Yinghai Lu

Output:

LinuxBIOS-1.1.02.0Fallback Mon Jun 23 22:34:00 EDT 2003 starting...

LinuxBIOS-1.1.02.0Fallback Mon Jun 23 22:34:00 EDT 2003 starting...
Bootstrap cpu
setting up coherent ht domain....
done.
PCI: 00:01.00
PCI: 00:01.01
PCI: 00:02.00
PCI: 00:02.01
PCI: 00:03.00
PCI: 00:04.00
PCI: 00:04.01
PCI: 00:04.02
PCI: 00:04.03
PCI: 00:04.05
PCI: 00:04.06
PCI: 00:18.00
PCI: 00:18.01
PCI: 00:18.02
PCI: 00:18.03
PCI: 00:19.00
PCI: 00:19.01
PCI: 00:19.02
PCI: 00:19.03
SMBus controller enabled
Ram1
setting up CPU0 northbridge registers
done.
Ram2
Ram3
dcl: 08038000
Initializing memory:  done
Ram4
Ram5
Ram6

dimm: 50
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 51
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 52
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 53
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
DRAM fill: 00000000-00001000
00001000
DRAM filled
DRAM verify: 00000000-00001000
00001000
DRAM verified
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.


From rminnich at lanl.gov  Mon Jun 23 19:06:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 23 19:06:00 2003
Subject: ASUS CUA and Linuxbios
In-Reply-To: <3EECD11E.7040600@t-online.de>
Message-ID: <Pine.LNX.4.44.0306231712330.3871-100000@maxroach.lanl.gov>

did you power cycle after the burn of the DOC? 

boot with the normal bios and then put the doc in and dump it. Did it burn 
correctly?

ron



From steve at nexpath.com  Mon Jun 23 19:18:00 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Mon Jun 23 19:18:00 2003
Subject: Laptops?
In-Reply-To: <20030623173507.B23784-100000@www.missl.cs.umd.edu>
References: <20030623173507.B23784-100000@www.missl.cs.umd.edu>
Message-ID: <3EF78E33.3000008@nexpath.com>

Adam Agnew wrote:

> If you have a TSOP40, you will need to have the TSOP40 extracted and a
> "coffin" put in its place. For that, some of us have used Century
> Technology, Inc in San Fransisco (the guys name is Henry Ho,
> hho at century-technology.com) though i'm sure there are other places which
> will do it.

Just curious, what is a "coffin" socket?  I have had some really bad 
luck with ET's zif socket for TSOPs.  After a few insertions the traces 
start to lift, since there is nothing else mechanically holding it on 
the board but the tiny SM traces.

-Steve



From agnew at cs.umd.edu  Mon Jun 23 20:29:01 2003
From: agnew at cs.umd.edu (Adam Agnew)
Date: Mon Jun 23 20:29:01 2003
Subject: Laptops?
In-Reply-To: <3EF78E33.3000008@nexpath.com>
Message-ID: <20030623194613.T23784-100000@www.missl.cs.umd.edu>

Let me see if i can dig around and find you a picture.. Basically its TSOP
socket with a lid which locks the tsop into place. It has worked really
well for me, i don't recall having trouble making the connection.
http://www.missl.cs.umd.edu/~agnew/t23pictures/

You'll see the socket open and closed there. It's got a little latch you
pry open with your finger to release the chip.

------------------
Adam Agnew
Independent Contractor
www.adamagnew.com

On Mon, 23 Jun 2003, Steve Gehlbach wrote:

> Adam Agnew wrote:
>
> > If you have a TSOP40, you will need to have the TSOP40 extracted and a
> > "coffin" put in its place. For that, some of us have used Century
> > Technology, Inc in San Fransisco (the guys name is Henry Ho,
> > hho at century-technology.com) though i'm sure there are other places which
> > will do it.
>
> Just curious, what is a "coffin" socket?  I have had some really bad
> luck with ET's zif socket for TSOPs.  After a few insertions the traces
> start to lift, since there is nothing else mechanically holding it on
> the board but the tiny SM traces.
>
> -Steve
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>




From YhLu at tyan.com  Mon Jun 23 22:57:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Jun 23 22:57:01 2003
Subject: =?GB2312?B?tPC4tDogY29oZXJlbnQgaHlwZXJ0cmFuc3BvcnQgZW51bWVyYXRp?=
	=?GB2312?B?b24gb24gb3B0ZXJvbg==?=
Message-ID: <3174569B9743D511922F00A0C943142302C4405F@TYANWEB>

Eric,

After update raminit.c now MB can boot into linuxbios.

The s2880 has six memory slot: 4 for CPU0 ,and 2 for CPU 1.
I can only init 4 for CPU0. I have tried:
#cp raminit.c raminit1.c
and rename all function in the raminit1.c to xxxxx_1
copy genric_sdram.c to generic_sdram1.c in the sdram dir.
Also add the calling function in auto1.c. and can not pass the test.

Any advice on init RAM on second cpu northbridge?

I have try to enable SMP support in LinuxBIOS and can not compile it
through.
Miss severl function. (Spin for Only CPU and start second CPU.S). When do
you plan to add it? Or can tell me your idea and I can add it right now.

Regards

Yinghai Lu

LinuxBIOS-1.1.02.0Fallback Tue Jun 24 02:16:37 EDT 2003 starting...

LinuxBIOS-1.1.02.0Fallback Tue Jun 24 02:16:37 EDT 2003 starting...
Bootstrap cpu
setting up coherent ht domain....
done.
PCI: 00:01.00
PCI: 00:01.01
PCI: 00:02.00
PCI: 00:02.01
PCI: 00:03.00
PCI: 00:04.00
PCI: 00:04.01
PCI: 00:04.02
PCI: 00:04.03
PCI: 00:04.05
PCI: 00:04.06
PCI: 00:18.00
PCI: 00:18.01
PCI: 00:18.02
PCI: 00:18.03
PCI: 00:19.00
PCI: 00:19.01
PCI: 00:19.02
PCI: 00:19.03
SMBus controller enabled
Ram1
setting up CPU0 northbridge registers
done.
Ram2
Ram3
dcl: 08018000
Initializing memory:  done
Ram4
Ram5
Ram6

dimm: 50
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 51
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 52
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 53
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 54
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 55
00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01
10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40
20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
DRAM fill: 00000000-00001000
00001000
DRAM filled
DRAM verify: 00000000-00001000
00001000
DRAM verified
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
LinuxBIOS-1.1.02.0Fallback Tue Jun 24 02:16:37 EDT 2003 booting...
Finding PCI configuration type.
PCI: Using configuration type 1
Enumerating buses...PCI: pci_scan_bus for bus 0
PCI: 00:01.0 [1022/7450]
PCI: 00:01.1 [1022/7451]
PCI: 00:02.0 [1022/7450]
PCI: 00:02.1 [1022/7451]
PCI: 00:03.0 [1022/7460]
PCI: 00:04.0 [1022/7468] ops
PCI: 00:04.0 [1022/7468]
PCI: 00:04.1 [1022/7469] ops
PCI: 00:04.1 [1022/7469]
PCI: 00:04.2 [1022/746a]
PCI: 00:04.3 [1022/746b] ops
PCI: 00:04.3 [1022/746b]
PCI: 00:04.5 [1022/746d]
PCI: 00:04.6 [1022/746e]
PCI: 00:18.0 [1022/1100]
PCI: 00:18.1 [1022/1101]
PCI: 00:18.2 [1022/1102]
PCI: 00:18.3 [1022/1103]
PCI: 00:19.0 [1022/1100]
PCI: 00:19.1 [1022/1101]
PCI: 00:19.2 [1022/1102]
PCI: 00:19.3 [1022/1103]
PCI: pci_scan_bus for bus 1
PCI: 01:09.0 [14e4/1648]
PCI: 01:09.1 [14e4/1648]
PCI: 01:0a.0 [1000/0030]
PCI: 01:0a.1 [1000/0030]
PCI: pci_scan_bus returning with max=01
PCI: pci_scan_bus for bus 2
PCI: pci_scan_bus returning with max=02
PCI: pci_scan_bus for bus 3
PCI: 03:00.0 [1022/7464] ops
PCI: 03:00.0 [1022/7464]
PCI: 03:00.1 [1022/7464] ops
PCI: 03:00.1 [1022/7464]
PCI: 03:00.2 [1022/7463]
PCI: 03:01.0 [1022/7462]
PCI: 03:05.0 [105a/3373]
PCI: 03:06.0 [1002/4752]
PCI: pci_scan_bus returning with max=03
PCI: pci_scan_bus returning with max=03
done
Allocating resources...
ASSIGN RESOURCES, bus 0
PCI: 00:01.0 1c <- [0x00001000 - 0x00001fff] bus 1 io
PCI: 00:01.0 24 <- [0xfe200000 - 0xfe1fffff] bus 1 prefmem
PCI: 00:01.0 20 <- [0xfe100000 - 0xfe1fffff] bus 1 mem
ASSIGN RESOURCES, bus 1
PCI: 01:09.0 10 <- [0xfe100000 - 0xfe10ffff] mem
PCI: 01:09.0 18 <- [0xfe110000 - 0xfe11ffff] mem
PCI: 01:09.1 10 <- [0xfe120000 - 0xfe12ffff] mem
PCI: 01:09.1 18 <- [0xfe130000 - 0xfe13ffff] mem
PCI: 01:0a.0 10 <- [0x00001000 - 0x000010ff] io
PCI: 01:0a.0 14 <- [0xfe140000 - 0xfe14ffff] mem
PCI: 01:0a.0 1c <- [0xfe150000 - 0xfe15ffff] mem
PCI: 01:0a.1 10 <- [0x00001400 - 0x000014ff] io
PCI: 01:0a.1 14 <- [0xfe160000 - 0xfe16ffff] mem
PCI: 01:0a.1 1c <- [0xfe170000 - 0xfe17ffff] mem
ASSIGNED RESOURCES, bus 1
PCI: 00:02.0 1c <- [0x00003000 - 0x00002fff] bus 2 io
PCI: 00:02.0 24 <- [0xfe200000 - 0xfe1fffff] bus 2 prefmem
PCI: 00:02.0 20 <- [0xfe200000 - 0xfe1fffff] bus 2 mem
PCI: 00:03.0 1c <- [0x00002000 - 0x00002fff] bus 3 io
PCI: 00:03.0 24 <- [0xfe200000 - 0xfe1fffff] bus 3 prefmem
PCI: 00:03.0 20 <- [0xfd000000 - 0xfe0fffff] bus 3 mem
ASSIGN RESOURCES, bus 3
PCI: 03:00.0 10 <- [0xfe020000 - 0xfe020fff] mem
PCI: 03:00.1 10 <- [0xfe021000 - 0xfe021fff] mem
PCI: 03:00.2 10 <- [0xfe025000 - 0xfe0250ff] mem
PCI: 03:00.2 14 <- [0xfe026000 - 0xfe02601f] mem
PCI: 03:01.0 10 <- [0xfe022000 - 0xfe022fff] mem
PCI: 03:05.0 10 <- [0x00002480 - 0x000024bf] io
PCI: 03:05.0 14 <- [0x000024c0 - 0x000024cf] io
PCI: 03:05.0 18 <- [0x00002400 - 0x0000247f] io
PCI: 03:05.0 1c <- [0xfe023000 - 0xfe023fff] mem
PCI: 03:05.0 20 <- [0xfe000000 - 0xfe01ffff] mem
PCI: 03:06.0 10 <- [0xfd000000 - 0xfdffffff] mem
PCI: 03:06.0 14 <- [0x00002000 - 0x000020ff] io
PCI: 03:06.0 18 <- [0xfe024000 - 0xfe024fff] mem
ASSIGNED RESOURCES, bus 3
PCI: 00:04.1 20 <- [0x000038e0 - 0x000038ef] io
PCI: 00:04.2 10 <- [0x000038c0 - 0x000038df] io
PCI: 00:04.5 10 <- [0x00003000 - 0x000030ff] io
PCI: 00:04.5 14 <- [0x00003880 - 0x000038bf] io
PCI: 00:04.6 10 <- [0x00003400 - 0x000034ff] io
PCI: 00:04.6 14 <- [0x00003800 - 0x0000387f] io
ASSIGNED RESOURCES, bus 0
Allocating VGA resource
done.
Enabling resourcess...DEV: 00:01.0 cmd <- 07
DEV: 00:01.1 cmd <- 00
DEV: 00:02.0 cmd <- 07
DEV: 00:02.1 cmd <- 00
DEV: 00:03.0 cmd <- 07
DEV: 00:04.0 cmd <- 0f
DEV: 00:04.1 cmd <- 01
DEV: 00:04.2 cmd <- 01
DEV: 00:04.3 cmd <- 00
DEV: 00:04.5 cmd <- 01
DEV: 00:04.6 cmd <- 01
DEV: 00:18.0 cmd <- 00
DEV: 00:18.1 cmd <- 00
DEV: 00:18.2 cmd <- 00
DEV: 00:18.3 cmd <- 00
DEV: 00:19.0 cmd <- 00
DEV: 00:19.1 cmd <- 00
DEV: 00:19.2 cmd <- 00
DEV: 00:19.3 cmd <- 00
DEV: 01:09.0 cmd <- 02
DEV: 01:09.1 cmd <- 02
DEV: 01:0a.0 cmd <- 03
DEV: 01:0a.1 cmd <- 03
DEV: 03:00.0 cmd <- 02
DEV: 03:00.1 cmd <- 02
DEV: 03:00.2 cmd <- 02
DEV: 03:01.0 cmd <- 02
DEV: 03:05.0 cmd <- 03
DEV: 03:06.0 cmd <- 83
done.
Initializing devices...
PCI: 00:04.0 init
lpc_init
PCI: 00:04.1 init
ide_init
IDE1 IDE0 PCI: 00:04.3 init
PCI: 03:00.0 init
USB: Setting up controller.. done.
PCI: 03:00.1 init
USB: Setting up controller.. done.
Devices initialized
totalram: 1024M
Initializing CPU #0
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) type: WB
Setting fixed MTRRs(72-88) type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 1024MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
call intel_enable_fixed_mtrr()
call intel_enable_var_mtrr()
Leave setup_mtrrs
done.

Max cpuid index    : 1
Vendor ID          : AuthenticAMD
Processor Type     : 0x00
Processor Family   : 0x0f
Processor Model    : 0x05
Processor Mask     : 0x00
Processor Stepping : 0x08
Feature flags      : 0x078bf9ff


MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0 done.
CPU #0 Initialized
Checking IRQ routing tables...
/root/xx/xx/freebios2/src/arch/i386/boot/pirq_routing.c:
29:check_pirq_routin
g_table() - irq_routing_table located at: 0x00008a20
done.
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...succeed
Wrote linuxbios table at: 00000500 - 00000b0c  checksum 916

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

Found ELF candiate at offset 0
Loading Etherboot version: 5.1.8
Dropping non PT_LOAD segment
New segment addr 0x20000 size 0x34718 offset 0xb0 filesize 0x56d6
(cleaned up) New segment addr 0x20000 size 0x34718 offset 0xb0 filesize
0x56d6
Loading Segment: addr: 0x0000000000020000 memsz: 0x0000000000034718 filesz:
0x00
000000000056d6
Clearing Segment: addr: 0x00000000000256d6 memsz: 0x000000000002f042
Jumping to boot code at 0x20000
ROM segment 0x0400 length 0x03ea reloc 0x00020000
CPU 1870 Mhz
Etherboot 5.1.8 (GPL) Tagged ELF (Multiboot) for [TG3]
Relocating _text from: [000256e0,00054d50) to [3ffd0990,40000000)
Probing pci nic...
[TG3]Cannot find PowerManagement capability, aborting.
[TG3]Ethernet addr: 00:E0:81:F0:18:CD
Tigon3 [partno(BCM95704A7) rev 2002 PHY(5704)] (PCIX:100MHz:64-bit)
Link is up at 100 Mbps, half duplex.
Searching for server (DHCP)...
..Me: 192.168.1.198, Server: 192.168.1.1, Gateway 192.168.1.1
Loading 192.168.1.1:ram0_2.5_2.4.21_k8_lsi_mydisk4.elf ...(ELF)...
.............
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
............................................................................
................................................................done
Firmware type: LinuxBIOS
Linux version 2.4.21 (root at tst2723_rh9) (gcc version 3.2.2 20030222 (Red Hat
Lin
ux 3.2.2-5)) #11 SMP Wed Jun 18 13:51:49 EDT 2003
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 0000000000000b6c (reserved)
 BIOS-e820: 0000000000000b6c - 00000000000a0000 (usable)
 BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
 BIOS-e820: 0000000000100000 - 0000000040000000 (usable)
128MB HIGHMEM available.
896MB LOWMEM available.
hm, page 00000000 reserved twice.
On node 0 totalpages: 262144
zone(0): 4096 pages.
zone(1): 225280 pages.
zone(2): 32768 pages.
Kernel command line: root=/dev/ram0 rw ram0_2.5_2.4.21_k8_lsi_mydisk4.elf
-retad
dr 0X3FFD0B34
Found and enabled local APIC!
Initializing CPU#0
Detected 1793.412 MHz processor.
Calibrating delay loop... 3578.26 BogoMIPS
Memory: 1029284k/1048576k available (1525k kernel code, 18904k reserved,
338k da
ta, 292k init, 131072k highmem)
Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
Inode cache hash table entries: 65536 (order: 7, 524288 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer-cache hash table entries: 65536 (order: 6, 262144 bytes)
Page-cache hash table entries: 262144 (order: 8, 1048576 bytes)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
mtrr: v1.40 (20010327) Richard Gooch (rgooch at atnf.csiro.au)
mtrr: detected mtrr type: Intel
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
Intel machine check reporting enabled on CPU#0.
CPU0: AMD 02/05 stepping 08
per-CPU timeslice cutoff: 2925.75 usecs.
SMP motherboard not detected.
enabled ExtINT on CPU#0
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1793.4469 MHz.
..... host bus clock speed is 199.2718 MHz.
cpu: 0, clocks: 1992718, slice: 996359
CPU0<T0:1992704,T1:996336,D:9,S:996359,C:1992718>
Waiting on wait_init_idle (map = 0x0)
All processors have done init_idle
CPU 0: Machine Check Exception: 0000000000000007
Bank 3: b40000000000083b at 000000fdfc000cfe
Kernel panic: Unable to continue


From steve at nexpath.com  Mon Jun 23 23:01:01 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Mon Jun 23 23:01:01 2003
Subject: Laptops?
In-Reply-To: <20030623194613.T23784-100000@www.missl.cs.umd.edu>
References: <20030623194613.T23784-100000@www.missl.cs.umd.edu>
Message-ID: <3EF7C4C6.4000000@nexpath.com>

Adam Agnew wrote:
> http://www.missl.cs.umd.edu/~agnew/t23pictures/
> 
> You'll see the socket open and closed there. It's got a little latch you
> pry open with your finger to release the chip.

Yep, that looks like the Emulation Technolgy zif socket (or at least 
that's what I call it).  Never heard the term "coffin" but it seems 
appropriate for a couple of reasons.

http://www.emulation.com/catalog/off-the-shelf_solutions/sockets/tsop/

I guess it depends on how well you install it, but I had one of these 
lift the traces on a board I was working on, after a few dozen cycles of 
in and out.  Almost put me in a "coffin" since I was debugging a program 
where the bug turned out to be an intermittent on the socket.  So I 
would be very gentle with it.  I never tried it, but epoxying it to the 
PCB might make it more rugged.

TSOPs are neat for their size, but they sure are delicate for R&D use. 
I have found them to be tempermental on my EMP programmer as well.

I don't know of a better solution, BTW, just an FYI.

-Steve




From aip at cwlinux.com  Mon Jun 23 23:22:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jun 23 23:22:00 2003
Subject: linuxbios
In-Reply-To: <Pine.LNX.4.44.0306231403550.2560-100000@maxroach.lanl.gov>; from ron minnich on Mon, Jun 23, 2003 at 02:04:14PM -0600
References: <3EF74D08.8060601@supereva.it> <Pine.LNX.4.44.0306231403550.2560-100000@maxroach.lanl.gov>
Message-ID: <20030624112905.A7111@mail.cwlinux.com>

Hi,

> > Hi Ron, I'm rickytato, I want to know if the pc-chips M830LR are
> > supported by linuxbios. on the web site the status are unstable, but I
> > think that web site aren't upgrade.
> I am not sure any more. We'll have to ask the list. Who owns that board?
AFAIK, it works ok with regular flash, but I haven't tried it recently.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From aip at cwlinux.com  Tue Jun 24 00:44:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jun 24 00:44:01 2003
Subject: Trying to freeze and failing ...
In-Reply-To: <Pine.LNX.4.44.0306221925150.14262-100000@maxroach.lanl.gov>; from ron minnich on Sun, Jun 22, 2003 at 07:26:51PM -0600
References: <Pine.LNX.4.44.0306221925150.14262-100000@maxroach.lanl.gov>
Message-ID: <20030624125105.A7637@mail.cwlinux.com>

Hi,

> Can anyone who has built a k7sem recently verify that the 'FIXED MTRR set 
> to UC' code is not fouling up the K7sem? 
The problem is confirmed, and it is related to enabling ecc in msr.
If you comment the code, you should be fine.  I guess we need better
mechanism to enable or disable in config file.

--- freebios/src/cpu/k7/cpufixup.c.bak      2003-04-09 08:01:08.000000000 +0800
+++ freebios/src/cpu/k7/cpufixup.c  2003-06-24 12:41:43.000000000 +0800
@@ -51,7 +51,7 @@
        rdmsr(SYSCFG_MSR, lo, hi);
        printk_spew("SYSCFG was 0x%x:0x%x\n", hi, lo);
        lo |= SYSCFG_MSR_MtrrVarDramEn;
-       lo |= SYSCFG_MSR_SysEccEn;
+//     lo |= SYSCFG_MSR_SysEccEn;
        wrmsr(SYSCFG_MSR, lo, hi);
        rdmsr(SYSCFG_MSR, lo, hi);
        printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", hi, lo);


-Andrew


-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Tue Jun 24 01:36:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 01:36:00 2003
Subject: Trying to freeze and failing ...
In-Reply-To: <20030624125105.A7637@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.44.0306232342100.6576-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Andrew Ip wrote:

> Hi,
> 
> > Can anyone who has built a k7sem recently verify that the 'FIXED MTRR set 
> > to UC' code is not fouling up the K7sem? 
> The problem is confirmed, and it is related to enabling ecc in msr.
> If you comment the code, you should be fine.  I guess we need better
> mechanism to enable or disable in config file.

Thanks andrew. Anybody know what about the K7 is making this explode? 

I am going to put an #if around this tomorrow, I hope someone will test. 

ron



From ebiederman at lnxi.com  Tue Jun 24 02:18:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 02:18:00 2003
Subject: Trying to freeze and failing ...
In-Reply-To: <Pine.LNX.4.44.0306232342100.6576-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306232342100.6576-100000@maxroach.lanl.gov>
Message-ID: <m3of0of0ts.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On Tue, 24 Jun 2003, Andrew Ip wrote:
> 
> > Hi,
> > 
> > > Can anyone who has built a k7sem recently verify that the 'FIXED MTRR set 
> > > to UC' code is not fouling up the K7sem? 
> > The problem is confirmed, and it is related to enabling ecc in msr.
> > If you comment the code, you should be fine.  I guess we need better
> > mechanism to enable or disable in config file.
> 
> Thanks andrew. Anybody know what about the K7 is making this explode? 
> 
> I am going to put an #if around this tomorrow, I hope someone will test. 

Doing this in the config file is inappropriate.  We need a test to see
if ECC is enabled elsewhere on the motherboard.  

A config option may make sense if ECC on/off is a global property of
the motherboard.  Otherwise is should be a callback function that checks
to see if ecc is enabled.

My apologies for not coding that way initially.

As far as what makes this explode putting in non-ECC memory and then
testing the ECC bits should cause a machine check.  Since we don't
trap machine check it would look like an unexpected machine death.

For machines with ECC support we want the explosion if something goes
badly wrong.  So we do no compute with bad data.

Eric



From aip at cwlinux.com  Tue Jun 24 02:38:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jun 24 02:38:00 2003
Subject: Trying to freeze and failing ...
In-Reply-To: <m3of0of0ts.fsf@maxwell.lnxi.com>; from Eric W. Biederman on Tue, Jun 24, 2003 at 12:26:23AM -0600
References: <Pine.LNX.4.44.0306232342100.6576-100000@maxroach.lanl.gov> <m3of0of0ts.fsf@maxwell.lnxi.com>
Message-ID: <20030624144439.A8389@mail.cwlinux.com>

> Doing this in the config file is inappropriate.  We need a test to see
> if ECC is enabled elsewhere on the motherboard.  
> A config option may make sense if ECC on/off is a global property of
> the motherboard.  Otherwise is should be a callback function that checks
> to see if ecc is enabled.
I think we can do the following,
if ecc option is on, then 
check for ecc availibility
if ecc is availible, then enable ecc; otherwise, skip ecc.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From ebiederman at lnxi.com  Tue Jun 24 03:45:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 03:45:01 2003
Subject: Trying to freeze and failing ...
In-Reply-To: <20030624144439.A8389@mail.cwlinux.com>
References: <Pine.LNX.4.44.0306232342100.6576-100000@maxroach.lanl.gov>
	<m3of0of0ts.fsf@maxwell.lnxi.com>
	<20030624144439.A8389@mail.cwlinux.com>
Message-ID: <m3fzlzc3ns.fsf@maxwell.lnxi.com>

Andrew Ip <aip at cwlinux.com> writes:

> > Doing this in the config file is inappropriate.  We need a test to see
> > if ECC is enabled elsewhere on the motherboard.  
> > A config option may make sense if ECC on/off is a global property of
> > the motherboard.  Otherwise is should be a callback function that checks
> > to see if ecc is enabled.

> I think we can do the following,
> if ecc option is on, then 
> check for ecc availibility
> if ecc is availible, then enable ecc; otherwise, skip ecc.

Sounds reasonable if we have chipsets that do not support ECC.
The conditional logic should be a function defined in a header so
it does not clutter up the code.

Eric



From janek at thenut.eti.pg.gda.pl  Tue Jun 24 08:49:00 2003
From: janek at thenut.eti.pg.gda.pl (Janek Kozicki)
Date: Tue Jun 24 08:49:00 2003
Subject: I new here
Message-ID: <20030624145335.24e371eb.janek@thenut.eti.pg.gda.pl>

Hello,

I just stumbled over your new webpage http://www.linuxbios.org/
I've read some of the stuff there, and I simply loved that idea.

I subscribed to get a grasp of what currently is going on at the
linuxBIOS development. My motherboard is Abit VP6 dual PIII, maybe at
some point in the future it will get support. And I'll be the first
tester ;) Anyway I must get a grasp of all this stuff to understand
what's going on :)

First of all - May I make some notices to the LinuxBIOS team? ;)

1. I've read FAQ. But althought I've read the whole FAQ I didn't get the
answer for one question. 
- what is DoS ?
(there are answers about how to prepare DoS, but not what is DoS by itself)
- on second thought - wouldn't it be nice if you place some email addres
on the webpage. for example in the FAQ section. "do you have a question
not answered in the FAQ? email this question to us". If you don't want
spambots to collect this email address - display it as an image with
text written on it. Spambots cannot (yet) collect email addresses from
images.


2. If you are interested I can offer you some little help with LinuxBIOS
webpage. I'm currently working on some php scripts designed to make easy
management of webpage contents (I called it GNU/enjine ;).

The easy management is achieved by creating a menu file, which contains
information about what is to be displayed. Now you don't have to edit
the html, but just the menu.

Short descripton with testing of some features is here:
http://absurd.kozicki.pl:2345/~www/engine/current/

An example usage of enjine (my computer usage/load graphs made with
rrdtools):
http://absurd.kozicki.pl:2345/~www/rrd.eng/


best regards

-- 
# Janek Kozicki
# janek at thenut.eti.pg.gda.pl


From rminnich at lanl.gov  Tue Jun 24 08:59:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 08:59:00 2003
Subject: Trying to freeze and failing ...
In-Reply-To: <m3of0of0ts.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306240704570.9880-100000@maxroach.lanl.gov>

On 24 Jun 2003, Eric W. Biederman wrote:

> ron minnich <rminnich at lanl.gov> writes:
> 
> > I am going to put an #if around this tomorrow, I hope someone will test. 
> 
> Doing this in the config file is inappropriate.  We need a test to see
> if ECC is enabled elsewhere on the motherboard.  

obviously, but I would like to get to the point that people can at least
boot from linuxbios instead of watching the explosions. I don't have the
time to do any more than this right now.  Maybe later.

If anybody wants to look at this it's fine by me.

ron



From rminnich at lanl.gov  Tue Jun 24 09:00:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 09:00:01 2003
Subject: Trying to freeze and failing ...
In-Reply-To: <20030624144439.A8389@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.44.0306240706360.9880-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Andrew Ip wrote:

> I think we can do the following,
> if ecc option is on, then 
> check for ecc availibility
> if ecc is availible, then enable ecc; otherwise, skip ecc.

can you write the code real quick and run it by me for a sanity check?

ron




From rminnich at lanl.gov  Tue Jun 24 09:40:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 09:40:00 2003
Subject: the freeze
Message-ID: <Pine.LNX.4.44.0306240745460.9880-100000@maxroach.lanl.gov>

OK, I just committed the earlymtrr patch for faster boots. 

I think at this point we stop taking patches to the core stuff, with one 
remaining issue: we need the ecc patch so K7s won't blow up. So, once 
that's in, I think we should try to declare 1.0.1 closed.

People who own various mainboards, please test with the latest cvs, save 
for those of you with K7 boards.

ron



From ebiederman at lnxi.com  Tue Jun 24 10:49:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 10:49:00 2003
Subject: =?gb2312?b?tPC4tA==?=: coherent hypertransport enumeration on
  opteron
In-Reply-To: <3174569B9743D511922F00A0C943142302C4405F@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C4405F@TYANWEB>
Message-ID: <m31xxj8qw7.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> After update raminit.c now MB can boot into linuxbios.
> 
> The s2880 has six memory slot: 4 for CPU0 ,and 2 for CPU 1.
> I can only init 4 for CPU0. I have tried:
> #cp raminit.c raminit1.c
> and rename all function in the raminit1.c to xxxxx_1
> copy genric_sdram.c to generic_sdram1.c in the sdram dir.
> Also add the calling function in auto1.c. and can not pass the test.

I am not certain which test is failing.  

The only test that really matters is memtest86.  The builtin test
of LinuxBIOS are just enough to see if the memory has been seriously
misconfigured.

> Any advice on init RAM on second cpu northbridge?

That is going to be a challenge.  I am pretty certain we can reuse
much of the code.  But it needs to get cleaned up first.  

I am about a day or two out before I am satisfied with the memory
initialization code I am working on.  I was starting to make progress
and then I got distracted by the lack of support for structures in
memory by romcc, so I have just finished implementing that.  They are
needed for some lookup tables based on memory speed.

> I have try to enable SMP support in LinuxBIOS and can not compile it
> through.
> Miss severl function. (Spin for Only CPU and start second CPU.S). When do
> you plan to add it? Or can tell me your idea and I can add it right now.

I don't think it is going to change much from the freebios tree, although
there is a little of that in my wish list.  If there are some missing functions
it should be possible to get them out of the freebios tree.  And a
patch doing that would be appreciated.

If I read your boot log properly you have enabled ecc support for you memory.
The memory timings you are using are not solid, and you are getting a machine
check because the memory is not stable.

Eric



From ebiederman at lnxi.com  Tue Jun 24 10:51:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 10:51:01 2003
Subject: coherent hypertransport enumeration on opteron
In-Reply-To: <3174569B9743D511922F00A0C943142302C43FEB@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43FEB@TYANWEB>
Message-ID: <m3wufb7c8e.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> I remember there is one type error on arch/i386/lib/pci_ops.c.
> 
> Change one *val --> value

Thanks.  I rarely compile the spew messages in, so I didn't notice.


Eric



From ebiederman at lnxi.com  Tue Jun 24 10:53:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 10:53:01 2003
Subject: =?gb2312?b?tPC4tA==?=: coherent hypertransport enumeration on
  opteron
In-Reply-To: <Pine.LNX.4.44.0306231605380.2560-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306231605380.2560-100000@maxroach.lanl.gov>
Message-ID: <m3smpz7c4m.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> what is pci_def.h BTW? I can't build now.


??? What is the error.

pci_def.h is a factor of pci.h .   I slit it out so I t could be used
by the romcc compiled code as well as in the normal pci.h.  It just
allows me to avoid duplicate definitions.

Eric



From ebiederman at lnxi.com  Tue Jun 24 11:00:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 11:00:01 2003
Subject: =?gb2312?b?tPC4tA==?=: coherent hypertransport enumeration on
  opteron
In-Reply-To: <3174569B9743D511922F00A0C943142302C43FE8@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C43FE8@TYANWEB>
Message-ID: <m3of0n7bum.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Stefan,
> 
> I swap the 
> 
> 	PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000070, //1C
> 
> The 4th line. It can go through setup_coherent_ht_domain.
> 
> But seems then both CPU all works. Please refer the attached.

Congratulations.

I refuse to put any more hard codes in the tree at this point.  The code
should at least be trying to solve the problems generically.  But at least
someone has made this work.  So when failures happen there is
something to compare against.

Eric



From ebiederman at lnxi.com  Tue Jun 24 11:04:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 11:04:00 2003
Subject: new config language.
In-Reply-To: <20030623201301.A28590@suse.de>
References: <m3u1akgv0a.fsf@maxwell.lnxi.com>
	<Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov>
	<20030623201301.A28590@suse.de>
Message-ID: <m3k7bb7bs0.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * ron minnich <rminnich at lanl.gov> [030623 18:07]:
> > On 20 Jun 2003, Eric W. Biederman wrote:
> > 
> > > The modules I think you want are:
> > > mtdchar
> > > amd76x
> > 
> > hmm, not on an 8111.

amd76xrom handles it.  It is just a pci id difference.  However
older version of it don't have the pci id in it.

Eric



From ebiederman at lnxi.com  Tue Jun 24 11:04:07 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 11:04:07 2003
Subject: hidden IC2 bus on ASUS
In-Reply-To: <Pine.VMS.3.91-2 (vms).1030622224218.1026A-100000@cs.felk.cvut.cz>
References: <Pine.VMS.3.91-2 (vms).1030622224218.1026A-100000@cs.felk.cvut.cz>
Message-ID: <m3el1j7bmi.fsf@maxwell.lnxi.com>

I am bouncing this to the LinuxBIOS list because most of the
discusion happens there.  And I am extremely busy at the moment.

Rudolf Marek <MAREKR2 at cs.felk.cvut.cz> writes:

> Hello,
> 
> I have ASUS A7S333 (Sis745).
> 
> On I2C I got only one winbond chip and one unknown device. 
> No SPD eeprom no PLL.
> 
> I read somewhere that you are curios to know if other ASUS mainboards
> got this feature. So here is my answer.
> 
> I want to enable the SPD i2c in case I can read the SPD timings.
> (I wrote i2c driver patch for my 745 into lm_sensors, ten to my surprise
> theese SPD and PLL devices "missing")
> 
> Unfortunatelly I dont have SiS745 spec so I dont know where to trigger
> this back. Would you give me some hint please?

The only hint I have is that boards like this tend to have a mux
on the i2c line.  Either controlled by a gpio line.  Or I have seen
the controlled by an i2c device.

> Thank you.
> 
> Rudolf Marek
> 
> CTU prague student.

Welcome,

Eric



From ebiederman at lnxi.com  Tue Jun 24 11:09:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 11:09:00 2003
Subject: new config language.
In-Reply-To: <20030623201301.A28590@suse.de>
References: <m3u1akgv0a.fsf@maxwell.lnxi.com>
	<Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov>
	<20030623201301.A28590@suse.de>
Message-ID: <m365mv7bdo.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * ron minnich <rminnich at lanl.gov> [030623 18:07]:
> > On 20 Jun 2003, Eric W. Biederman wrote:
> > 
> > > The modules I think you want are:
> > > mtdchar
> > > amd76x
> > 
> > hmm, not on an 8111.
> 
> in /dev/bios 8111 shares the code with the amd 7xx chipsets..
> Maybe some other problem? What board is it?

Stefan.  Do you have a recent URL for /dev/bios.

I am seeing some odd problems with SST LPC flash chips and any other
data point would be interesting...  The chips look like they are dropping
commands for no good reason.

Eric



From rminnich at lanl.gov  Tue Jun 24 11:13:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 11:13:00 2003
Subject: =?gb2312?b?tPC4tA==?=: coherent hypertransport enumeration on 
 opteron
In-Reply-To: <m3smpz7c4m.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306240919220.10666-100000@maxroach.lanl.gov>

On 24 Jun 2003, Eric W. Biederman wrote:

> ??? What is the error.

that file is not in my freebios2 tree. I just wanted to make sure it 
should be. 

ron



From stepan at suse.de  Tue Jun 24 11:13:06 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Jun 24 11:13:06 2003
Subject: new config language.
In-Reply-To: <m3k7bb7bs0.fsf@maxwell.lnxi.com>
References: <m3u1akgv0a.fsf@maxwell.lnxi.com> <Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov> <20030623201301.A28590@suse.de> <m3k7bb7bs0.fsf@maxwell.lnxi.com>
Message-ID: <20030624152254.GA2972@suse.de>

* Eric W. Biederman <ebiederman at lnxi.com> [030624 17:09]:
 
> amd76xrom handles it.  It is just a pci id difference.  However
> older version of it don't have the pci id in it.

when "porting" devbios I even tried to access the flash devices
right below 0x10000000000000000 (like on Alpha), giving strange 
results. Using the normal below 4G space worked fine though

Best regards,
  Stefan Reinauer
  
-- 
Architecture Team
    SuSE Linux AG


From rminnich at lanl.gov  Tue Jun 24 11:15:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 11:15:00 2003
Subject: new config language.
In-Reply-To: <m3k7bb7bs0.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306240921190.10666-100000@maxroach.lanl.gov>

On 24 Jun 2003, Eric W. Biederman wrote:

> amd76xrom handles it.  It is just a pci id difference.  However
> older version of it don't have the pci id in it.

Yes, I plugged the PCI ID in and all is well. Forgot to send a message to 
that effect yesterday.

ron



From rminnich at lanl.gov  Tue Jun 24 11:16:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 11:16:01 2003
Subject: new config language.
In-Reply-To: <m365mv7bdo.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306240922410.10666-100000@maxroach.lanl.gov>

On 24 Jun 2003, Eric W. Biederman wrote:

> I am seeing some odd problems with SST LPC flash chips and any other
> data point would be interesting...  The chips look like they are dropping
> commands for no good reason.

I heard a similar report recently but the chip was an 82802ab, and the 
mobo was a supermicro x5 series ... seems like timing problems are "going 
around"

ron



From stepan at suse.de  Tue Jun 24 11:18:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Jun 24 11:18:00 2003
Subject: new config language.
In-Reply-To: <m365mv7bdo.fsf@maxwell.lnxi.com>
References: <m3u1akgv0a.fsf@maxwell.lnxi.com> <Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov> <20030623201301.A28590@suse.de> <m365mv7bdo.fsf@maxwell.lnxi.com>
Message-ID: <20030624152744.GB2972@suse.de>

* Eric W. Biederman <ebiederman at lnxi.com> [030624 17:17]:
> Stefan.  Do you have a recent URL for /dev/bios.
 
http://www.openbios.info/development/devbios.html contains some
information.

Please use the CVS version, I haven't done a release in quite a
while even though the 0.3.2 code has problems on most motherboards.
Check it out from openbios cvs, or use the "download tarball" link 
on http://openbios.ph-freiburg.de/cgi-dom/viewcvs.cgi/devbios/

> I am seeing some odd problems with SST LPC flash chips and any other
> data point would be interesting...  The chips look like they are dropping
> commands for no good reason.

One of my solo machines had weird read errors after a write, at changing
addresses with every read. (sometimes an address returns the correct
value, sometimes not, but there's always between 1 and some dozens read
errors) Didnt change any of the read code at all..
Maybe a hardware problem?

Best regards,
  Stefan Reinauer
  
-- 
Architecture Team
    SuSE Linux AG


From stepan at suse.de  Tue Jun 24 11:20:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Jun 24 11:20:01 2003
Subject: new config language.
In-Reply-To: <Pine.LNX.4.44.0306240922410.10666-100000@maxroach.lanl.gov>
References: <m365mv7bdo.fsf@maxwell.lnxi.com> <Pine.LNX.4.44.0306240922410.10666-100000@maxroach.lanl.gov>
Message-ID: <20030624152938.GC2972@suse.de>

* ron minnich <rminnich at lanl.gov> [030624 17:23]:
> On 24 Jun 2003, Eric W. Biederman wrote:
> 
> > I am seeing some odd problems with SST LPC flash chips and any other
> > data point would be interesting...  The chips look like they are dropping
> > commands for no good reason.
> 
> I heard a similar report recently but the chip was an 82802ab, and the 
> mobo was a supermicro x5 series ... seems like timing problems are "going 
> around"

With devbios you _have_ to disable the nmi watchdog, otherwise it will
just kick the dd command out of a write or erase cycle. I hope mtd is 
written cleaner, but i dont know.

Best regards,
  Stefan Reinauer
  
-- 
Architecture Team
    SuSE Linux AG


From rminnich at lanl.gov  Tue Jun 24 11:24:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 11:24:01 2003
Subject: I just updated the web page at www.linuxbios.org
Message-ID: <Pine.LNX.4.44.0306240931010.10666-100000@maxroach.lanl.gov>

look at any STATUS you might own and see if it is right. Sorry for the 
delay. 

ron



From ebiederman at lnxi.com  Tue Jun 24 11:29:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 11:29:01 2003
Subject: new config language.
In-Reply-To: <20030624152938.GC2972@suse.de>
References: <m365mv7bdo.fsf@maxwell.lnxi.com>
	<Pine.LNX.4.44.0306240922410.10666-100000@maxroach.lanl.gov>
	<20030624152938.GC2972@suse.de>
Message-ID: <m3fzlzwkor.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * ron minnich <rminnich at lanl.gov> [030624 17:23]:
> > On 24 Jun 2003, Eric W. Biederman wrote:
> > 
> > > I am seeing some odd problems with SST LPC flash chips and any other
> > > data point would be interesting...  The chips look like they are dropping
> > > commands for no good reason.
> > 
> > I heard a similar report recently but the chip was an 82802ab, and the 
> > mobo was a supermicro x5 series ... seems like timing problems are "going 
> > around"

I have seen one or two problems on the x5. But it is quite rare, I'd say
a 1 in 100 or so.  With the SST I am seeing problems on every chip of the
appropriate model every time I flash.  Though with 64bit kernels I see
fewer problems. 

> With devbios you _have_ to disable the nmi watchdog, otherwise it will
> just kick the dd command out of a write or erase cycle. I hope mtd is 
> written cleaner, but i dont know.

Yes mtd is.  The code calls schedule has smp locks etc.  I'm not certain
another data point will do me any good.  But I can hope.  When code
is stable and you start putting it to more use you see a whole new
set of problems, because it is being used more.  And I am at that
stage with the MTD drivers.  

I really appreciate the good factoring of the code.  So far there are
only 3 real drivers for NOR flash.   One for the Intel command set,
one for the AMD command set, and one for some weird command set.
Then you have them map drivers which know how to find the flash
devices.  And then there is jedec_probe which knows how to map
the device id's to the command set, and chip size.  Or cfi_probe if
you are so lucky on having and a nice flash chip.

Eric



From ebiederman at lnxi.com  Tue Jun 24 11:45:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 11:45:01 2003
Subject: new config language.
In-Reply-To: <20030624152744.GB2972@suse.de>
References: <m3u1akgv0a.fsf@maxwell.lnxi.com>
	<Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov>
	<20030623201301.A28590@suse.de> <m365mv7bdo.fsf@maxwell.lnxi.com>
	<20030624152744.GB2972@suse.de>
Message-ID: <m3u1afpj3y.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * Eric W. Biederman <ebiederman at lnxi.com> [030624 17:17]:
> > Stefan.  Do you have a recent URL for /dev/bios.
>  
> http://www.openbios.info/development/devbios.html contains some
> information.
> 
> Please use the CVS version, I haven't done a release in quite a
> while even though the 0.3.2 code has problems on most motherboards.
> Check it out from openbios cvs, or use the "download tarball" link 
> on http://openbios.ph-freiburg.de/cgi-dom/viewcvs.cgi/devbios/
> 
> > I am seeing some odd problems with SST LPC flash chips and any other
> > data point would be interesting...  The chips look like they are dropping
> > commands for no good reason.
> 
> One of my solo machines had weird read errors after a write, at changing
> addresses with every read. (sometimes an address returns the correct
> value, sometimes not, but there's always between 1 and some dozens read
> errors) Didnt change any of the read code at all..
> Maybe a hardware problem?

Peculiar.  Once I sorted out the probe code the native SOLO rom chips
have been rock solid for me.

Eric



From stepan at suse.de  Tue Jun 24 11:49:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Jun 24 11:49:01 2003
Subject: new config language.
In-Reply-To: <m3u1afpj3y.fsf@maxwell.lnxi.com>
References: <m3u1akgv0a.fsf@maxwell.lnxi.com> <Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov> <20030623201301.A28590@suse.de> <m365mv7bdo.fsf@maxwell.lnxi.com> <20030624152744.GB2972@suse.de> <m3u1afpj3y.fsf@maxwell.lnxi.com>
Message-ID: <20030624155954.GA26667@suse.de>

* Eric W. Biederman <ebiederman at lnxi.com> [030624 17:53]:
> Peculiar.  Once I sorted out the probe code the native SOLO rom chips
> have been rock solid for me.

The problems I had on Solo were with an SST 49LF080, not with the 
Winbond 2MBit types. Maybe that explains it ;)

Best regards,
  Stefan Reinauer
  
-- 
Architecture Team
    SuSE Linux AG


From ebiederman at lnxi.com  Tue Jun 24 11:54:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 11:54:00 2003
Subject: new config language.
In-Reply-To: <20030624155954.GA26667@suse.de>
References: <m3u1akgv0a.fsf@maxwell.lnxi.com>
	<Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov>
	<20030623201301.A28590@suse.de> <m365mv7bdo.fsf@maxwell.lnxi.com>
	<20030624152744.GB2972@suse.de> <m3u1afpj3y.fsf@maxwell.lnxi.com>
	<20030624155954.GA26667@suse.de>
Message-ID: <m3k7bbmpjf.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * Eric W. Biederman <ebiederman at lnxi.com> [030624 17:53]:
> > Peculiar.  Once I sorted out the probe code the native SOLO rom chips
> > have been rock solid for me.
> 
> The problems I had on Solo were with an SST 49LF080, not with the 
> Winbond 2MBit types. Maybe that explains it ;)

Ah yes.  I have problems but only an occasional dropped write byte, or
erase block command.  I have had no read errors.

I currently have a slightly modified cfi_comset_0002.c that performs
a single retry when those commands fail and I not had the command fail
after a single retry.  We have asked SST about the 49LF080 but we have
not been able to provide them with a smoking gun yet...

Eric



From ebiederman at lnxi.com  Tue Jun 24 11:56:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 11:56:00 2003
Subject: new config language.
In-Reply-To: <20030624152254.GA2972@suse.de>
References: <m3u1akgv0a.fsf@maxwell.lnxi.com>
	<Pine.LNX.4.44.0306231007150.924-100000@maxroach.lanl.gov>
	<20030623201301.A28590@suse.de> <m3k7bb7bs0.fsf@maxwell.lnxi.com>
	<20030624152254.GA2972@suse.de>
Message-ID: <m3fzlzmph9.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * Eric W. Biederman <ebiederman at lnxi.com> [030624 17:09]:
>  
> > amd76xrom handles it.  It is just a pci id difference.  However
> > older version of it don't have the pci id in it.
> 
> when "porting" devbios I even tried to access the flash devices
> right below 0x10000000000000000 (like on Alpha), giving strange 
> results. Using the normal below 4G space worked fine though

Given the way LPC flash works (the flash chip does the decode and it only
sees a 32bit address) I can't see anything over 4G working.

Eric



From rminnich at lanl.gov  Tue Jun 24 11:57:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 11:57:01 2003
Subject: new config language.
In-Reply-To: <20030624155954.GA26667@suse.de>
Message-ID: <Pine.LNX.4.44.0306241004120.10666-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Stefan Reinauer wrote:

> The problems I had on Solo were with an SST 49LF080, not with the 
> Winbond 2MBit types. Maybe that explains it ;)

uh oh. I just ordered 30 of those SST parts :-(

ron



From rminnich at lanl.gov  Tue Jun 24 11:58:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 11:58:01 2003
Subject: =?gb2312?b?tPC4tA==?=: coherent hypertransport enumeration on 
  opteron
In-Reply-To: <m3brwnmpfk.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306241005070.10666-100000@maxroach.lanl.gov>

On 24 Jun 2003, Eric W. Biederman wrote:

> Yes.  It has been in the repository in src/include/device/pci_def.h
> for a month now.  At least according to CVS.

gag. It came down to my machine here at work and not my x24. 

OK, more fun.

ron



From ebiederman at lnxi.com  Tue Jun 24 12:01:04 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Jun 24 12:01:04 2003
Subject: new config language.
In-Reply-To: <Pine.LNX.4.44.0306241004120.10666-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306241004120.10666-100000@maxroach.lanl.gov>
Message-ID: <m31xxjjw2v.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> On Tue, 24 Jun 2003, Stefan Reinauer wrote:
> 
> > The problems I had on Solo were with an SST 49LF080, not with the 
> > Winbond 2MBit types. Maybe that explains it ;)
> 
> uh oh. I just ordered 30 of those SST parts :-(

Perfectly usable for development.  Most of the chips I have seen
have been from the same lot so the investigation continues.

Eric



From rsmith at bitworks.com  Tue Jun 24 12:34:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Tue Jun 24 12:34:00 2003
Subject: I just updated the web page at www.linuxbios.org
In-Reply-To: <Pine.LNX.4.44.0306240931010.10666-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306240931010.10666-100000@maxroach.lanl.gov>
Message-ID: <3EF87ED1.2040505@bitworks.com>

ron minnich wrote:
> look at any STATUS you might own and see if it is right. Sorry for the 
> delay. 

The 440bx info says unsupported and you as the owner.  I'll be happy to 
be listed as the owner and take over support of that chipset.

-- 
Richard A. Smith
rsmith at bitworks.com




From rsmith at bitworks.com  Tue Jun 24 12:45:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Tue Jun 24 12:45:01 2003
Subject: the freeze
In-Reply-To: <Pine.LNX.4.44.0306240745460.9880-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306240745460.9880-100000@maxroach.lanl.gov>
Message-ID: <3EF8816A.2080900@bitworks.com>

ron minnich wrote:

> I think at this point we stop taking patches to the core stuff, with one 
> remaining issue: we need the ecc patch so K7s won't blow up. So, once 
> that's in, I think we should try to declare 1.0.1 closed.

I have a core change for 440bx that adds a mouse option into the superio 
structure.  Too late?

> People who own various mainboards, please test with the latest cvs, save 

Well looks like I'm just in time.  I now have full operation of our 
board under linuxbios+ADLO.  Everything works just like it did under the 
old COTS bios.  Yah!

I'll send in a patch today vs the latest CVS.

What does the freeze mean for work on the 1.x tree?  Is there going to 
be a 1.1.x?  I still have a few things I would like to work on like 
getting the video bios to work without ADLO.  Last I checked myself and 
at least one other person were having problems getting that to compile.

-- 
Richard A. Smith
rsmith at bitworks.com




From rminnich at lanl.gov  Tue Jun 24 13:02:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 13:02:00 2003
Subject: the freeze
In-Reply-To: <3EF8816A.2080900@bitworks.com>
Message-ID: <Pine.LNX.4.44.0306241108090.10666-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Richard Smith wrote:

> I have a core change for 440bx that adds a mouse option into the superio 
> structure.  Too late?

no, I guess not. It's too important and I doubt will cause trouble. 

Send patch. 

> What does the freeze mean for work on the 1.x tree?  Is there going to 
> be a 1.1.x?  I still have a few things I would like to work on like 
> getting the video bios to work without ADLO.  Last I checked myself and 
> at least one other person were having problems getting that to compile.

I think there will have to be. 2.x is a big change for people and I think 
1.x will continue for a while.

ron



From rsmith at bitworks.com  Tue Jun 24 13:15:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Tue Jun 24 13:15:01 2003
Subject: the freeze
In-Reply-To: <Pine.LNX.4.44.0306241108090.10666-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306241108090.10666-100000@maxroach.lanl.gov>
Message-ID: <3EF8885C.7010406@bitworks.com>

ron minnich wrote:

>>I have a core change for 440bx that adds a mouse option into the superio 
>>structure.  Too late?
>  
> no, I guess not. It's too important and I doubt will cause trouble. 
> 
> Send patch. 
> 

I'm doing a cvs update now.  Sourceforge is _slow_ today.

-- 
Richard A. Smith
rsmith at bitworks.com




From rminnich at lanl.gov  Tue Jun 24 13:32:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 13:32:01 2003
Subject: the freeze
In-Reply-To: <3EF8885C.7010406@bitworks.com>
Message-ID: <Pine.LNX.4.44.0306241138290.10666-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Richard Smith wrote:

> I'm doing a cvs update now.  Sourceforge is _slow_ today.

broken too.

ron



From rsmith at bitworks.com  Tue Jun 24 13:41:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Tue Jun 24 13:41:01 2003
Subject: the freeze
In-Reply-To: <Pine.LNX.4.44.0306241138290.10666-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306241138290.10666-100000@maxroach.lanl.gov>
Message-ID: <3EF88E93.6010308@bitworks.com>

ron minnich wrote:

> On Tue, 24 Jun 2003, Richard Smith wrote:
> 
>>I'm doing a cvs update now.  Sourceforge is _slow_ today.
> 
> broken too.

Are you refering to all the EOF's you get when trying to update or check 
out?  If so then its a try-try-again thing.  I suspect sf is reaching 
the limit on the number of concurrent CVS sessions it can handle.

I just continued to do a 'cvs update' until it finally took.  Took about 
20 re-tries or so.

Big time slow though... It's _still_ updateing.

-- 
Richard A. Smith
rsmith at bitworks.com




From rminnich at lanl.gov  Tue Jun 24 15:39:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 15:39:00 2003
Subject: freebios2: pcibios_read_config_*
Message-ID: <Pine.LNX.4.44.0306241345190.11898-100000@maxroach.lanl.gov>

these appear to be deprecated? Just checking as they are not in my 
freebios2 tree any more but code that uses them is still there.

ron



From rogerxxmaillist at san.rr.com  Tue Jun 24 15:53:00 2003
From: rogerxxmaillist at san.rr.com (roger)
Date: Tue Jun 24 15:53:00 2003
Subject: mtd drivers and diskonchip millenium
In-Reply-To: <Pine.LNX.4.44.0306230803320.19442-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306230803320.19442-100000@maxroach.lanl.gov>
Message-ID: <1056484639.4025.7.camel@localhost3.localdomain>

On Mon, 2003-06-23 at 07:04, ron minnich wrote:
> On 23 Jun 2003, roger wrote:
> 
> > (Tyan Tiger 1832DL 440BX with a second 440BX board laying around. Both
> > with the same problem.  So much for spending the extra buck on intel
> > boards to ensure compatability eh?)
> 
> 
> OK, you could try enabling the flash write from the setpci command, and 
> then using MTD. 

yes. i started researching setpci data and the addresses to mingle with
are probably addressed in the openbios/devbios project as "devbios" does
apparently allow writing (including reading) the bios chip -- but not
the mtd doc -- this is probably why a kernel oops allowed the setpci
address to not be reset (or turn-off write access) before unloading the
devbios module. ...very possible.

however, once I'm able to do this, the problem is, how to get the DOC to
be recognized via linuxbios on a machine cold start?  I'm guessing some
changes will have to be introduced into the mtd kernel drivers (setpci
write enable on the intel 440bx board before attempting to mount the mtd
device).

I'm guessing the best thing to do is to probably buy extra original
motherboard bios chips first.  then once there's a successful boot, then
try converging stuff to a DOC.

well. i will  continue to dabble into this -- but the sun is *finally*
out in San Diego... finally.

-- 

Roger
http://www.eskimo.com/~roger/index.html



From linuxbios at techfreakz.net  Tue Jun 24 15:58:00 2003
From: linuxbios at techfreakz.net (Alex Scarbro)
Date: Tue Jun 24 15:58:00 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <20030623073144.GA6972@cma.co.jp>
Message-ID: <200362421430.693124@techfreakz>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20030624/69ebf05b/attachment.html>

From linuxbios at techfreakz.net  Tue Jun 24 16:57:00 2003
From: linuxbios at techfreakz.net (Alex Scarbro)
Date: Tue Jun 24 16:57:00 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <Pine.LNX.4.44.0306231228120.1964-100000@maxroach.lanl.gov>
Message-ID: <200362422358.291232@techfreakz>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20030624/b87bb524/attachment.html>

From rminnich at lanl.gov  Tue Jun 24 17:38:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 17:38:00 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <200362421430.693124@techfreakz>
Message-ID: <Pine.LNX.4.44.0306241544280.15957-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Alex Scarbro wrote:

> rock n roll n compile, that will contribute/help in getting the K7SEM up
> and running in light of the recent changes to LInuxBIOS. Also, can i
> access an earlier version of the linuxbios CVS tree that might be more
> fruitfull?

Please see Andrew's small hack from yesterday and try it. It is a *very* 
short-term solution and we need a real answer, but it should help you.

ron



From rminnich at lanl.gov  Tue Jun 24 17:41:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 17:41:01 2003
Subject: K7SEM Serial Boot Log....What next...
In-Reply-To: <200362422358.291232@techfreakz>
Message-ID: <Pine.LNX.4.44.0306241547400.15957-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Alex Scarbro wrote:

> LinuxBIOS-1.0.0 Sat Jun 21 00:09:20 BST 2003 starting...
> Copying LinuxBIOS to ram.
> Jumping to LinuxBIOS.
> POST: 0x39
> ?
> ?? BLAH!!
> ?
> POST: 0x60
> Enabling cache...
> Setting fixed MTRRs(0-88) type: UC
> 0ype: UC
> 0-88)
> ?
> LinuxBIOS-1.0.0 Sat Jun 21 00:09:20 BST 2003 starting...
> Copying LinuxBIOS to ram.
> Jumping to LinuxBIOS.
> POST: 0x39
> ?
> ?? BLAH!!
> ?
> POST: 0x60
> Enabling cache...
> Setting fixed MTRRs(0-88) type: UC
> 0ype: UC
> 0-88)
> ?
> LinuxBIOS-1.0.0 Sat Jun 21 00:09:20 BST 2003 starting...
> Copying LinuxBIOS to ram.
> Jumping to LinuxBIOS.
> POST: 0x39
> ?
> ?? BLAH!!
> ?
> POST: 0x60
> Enabling cache...
> Setting fixed MTRRs(0-88) type: UC
> ?


I used to have this if there was a watchdog timer on. 

Also used to see it on SMP sometimes but you don't have that.

ron



From rsmith at bitworks.com  Tue Jun 24 19:27:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Tue Jun 24 19:27:01 2003
Subject: 440bx patches
In-Reply-To: <200362422358.291232@techfreakz>
References: <200362422358.291232@techfreakz>
Message-ID: <3EF8DF79.4030808@bitworks.com>

Here's my patches for syncing up with my tree

This is a 'diff -u -N -r --exclude=CVS --exclude=ADLO' of my tree synced 
to cvs vs the current cvs tree.  'cvs diff -u -N' keep hanging on me.

I excluded my ADLO dual head video init since it's specific to our board 
and hardcoded.

Includes:

- Config file for the bitworks IMS board. (Not really usefull to anyone 
execept for example.

- Rework of raminit.inc for the 440bx.  Current CVS is broken and will 
not work in the general case.   New code works for every different DIMM 
I had here at Bitworks.

- Support for the NSC PC87351 superIO

- Addition of 'mouse' into new superIO struct

- Various mods to piix4e to enable/disable some features and some fixes

- A sprinkleing of printk_debugs that helped me figure out what code was 
being called where.

Most everything I did I tried to wrap with some sort of Config option 
except in bug fix or incorrect settings cases.

Some of the stuff in the PC87351 superIO is kinda specific to our 
motherboard and not truly generic but I imagine that anyone else using 
this superIO would have it setup the same way.  In the timeframe between 
1.x and 2.x I doubt there will be any need for additional config options.


-- 
Richard A. Smith
rsmith at bitworks.com

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From YhLu at tyan.com  Tue Jun 24 19:32:00 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Jun 24 19:32:00 2003
Subject: coherent hypertransport enumeration on opteron
Message-ID: <3174569B9743D511922F00A0C943142302C44109@TYANWEB>

Eric,

The RAM on CPU1's northbridge can go through now. I mistype several 0x19 to
0x18.

I have enabled the SMP support in Config file. 
option CONFIG_SMP=1
option MAX_CPUS=2
option SMP=1

As for the missing functions.
 I have copied secondCPU.S and udelay related files to the freebios2.

The result is it can not jumping into LinuxBIOS again.

In the Config last line you said something need to be fixed up.
Do I need to change the START_CPU_SEG ?

Regards

Yinghai Lu



From rminnich at lanl.gov  Tue Jun 24 19:34:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 19:34:00 2003
Subject: 440bx patches
In-Reply-To: <3EF8DF79.4030808@bitworks.com>
Message-ID: <Pine.LNX.4.44.0306241740260.23238-100000@maxroach.lanl.gov>

These are committed. 

I will test against Smartcore PIII as soon as I can. 

This is the last big patch I want to add except for the K7 fix.

ron



From rminnich at lanl.gov  Tue Jun 24 19:35:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 19:35:00 2003
Subject: coherent hypertransport enumeration on opteron
In-Reply-To: <3174569B9743D511922F00A0C943142302C44109@TYANWEB>
Message-ID: <Pine.LNX.4.44.0306241741170.23238-100000@maxroach.lanl.gov>

FYI, Greg Watson has improved the config tool, I am integrating the 
changes, and almost have an image built for Arima HDAMA. 

Hope to test tomorrow, if I can fix this last nagging problem ...

ron



From hansolofalcon at worldnet.att.net  Tue Jun 24 20:51:01 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Tue Jun 24 20:51:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <Pine.LNX.4.44.0306231546310.2560-100000@maxroach.lanl.gov>
Message-ID: <000101c33ab4$eb5ef8e0$239efea9@who5>

Hello again from Gregg C Levine
I agree in principle Ron, but I am curious as to why they thought
that. After all, Linux BIOS does more for a system then U-Boot. It's
my guess that after seeing the appropriate demonstrations that group
will change their minds, collectively or otherwise. For that matter,
Greg W, I applaud your efforts regarding the PPC port.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of ron minnich
> Sent: Monday, June 23, 2003 5:47 PM
> To: David Eliasson
> Cc: linuxbios at clustermatic.org
> Subject: Re: LinuxBios PPC-support.. U-Boot project
> 
> On Tue, 3 Jun 2003, David Eliasson wrote:
> 
> > I read on the linuxbios webpage about PPC-support.. Aren t you
guys
> > aware of the U-boot project?
> 
> Sure.
> 
> > They've been running the GNU Linux kernel 2.4.19 and 2.4 21 in
firmware
> > for a while now.. Maybe I m just missing something, but I thought
some
> > merging of efforts might be in place..
> 
> I tried to have a conversation with somebody from u-boot about some
sort
> of merge, but it never got beyond the "why u-boot is better than
> linuxbios" stage, so I dropped it.
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From frannk_m1 at yahoo.com  Tue Jun 24 20:57:01 2003
From: frannk_m1 at yahoo.com (Frank)
Date: Tue Jun 24 20:57:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <000101c33ab4$eb5ef8e0$239efea9@who5>
Message-ID: <20030625010351.311.qmail@web13808.mail.yahoo.com>

As I said before, If you want to convert the u-boot users, you
have to provide an option to go to a command line instead of
just unconditionally booting linux. Getting to a command line is
not rocket science...

--- Gregg C Levine <hansolofalcon at worldnet.att.net> wrote:
> Hello again from Gregg C Levine
> I agree in principle Ron, but I am curious as to why they
> thought
> that. After all, Linux BIOS does more for a system then
> U-Boot. It's
> my guess that after seeing the appropriate demonstrations that
> group
> will change their minds, collectively or otherwise. For that
> matter,
> Greg W, I applaud your efforts regarding the PPC port.
> -------------------
> Gregg C Levine hansolofalcon at worldnet.att.net
> ------------------------------------------------------------
> "The Force will be with you...Always." Obi-Wan Kenobi
> "Use the Force, Luke."? Obi-Wan Kenobi
> (This company dedicates this E-Mail to General Obi-Wan Kenobi
> )
> (This company dedicates this E-Mail to Master Yoda )
> 
> 
> 
> > -----Original Message-----
> > From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> > admin at clustermatic.org] On Behalf Of ron minnich
> > Sent: Monday, June 23, 2003 5:47 PM
> > To: David Eliasson
> > Cc: linuxbios at clustermatic.org
> > Subject: Re: LinuxBios PPC-support.. U-Boot project
> > 
> > On Tue, 3 Jun 2003, David Eliasson wrote:
> > 
> > > I read on the linuxbios webpage about PPC-support.. Aren t
> you
> guys
> > > aware of the U-boot project?
> > 
> > Sure.
> > 
> > > They've been running the GNU Linux kernel 2.4.19 and 2.4
> 21 in
> firmware
> > > for a while now.. Maybe I m just missing something, but I
> thought
> some
> > > merging of efforts might be in place..
> > 
> > I tried to have a conversation with somebody from u-boot
> about some
> sort
> > of merge, but it never got beyond the "why u-boot is better
> than
> > linuxbios" stage, so I dropped it.
> > 
> > ron
> > 
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios


__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
http://sbc.yahoo.com


From gwatson at lanl.gov  Tue Jun 24 21:27:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Tue Jun 24 21:27:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <20030625010351.311.qmail@web13808.mail.yahoo.com>
References: <20030625010351.311.qmail@web13808.mail.yahoo.com>
Message-ID: <p05210604bb1ea9db0a32@[10.0.1.2]>

Yes, and the nice thing about the linuxbios architecture is that the 
CLI can just be a payload, so you can have any CLI that you want - 
forth, tcl, whatever. No changes are required to linuxbios at all.

Greg

At 6:03 PM -0700 24/6/03, Frank wrote:
>As I said before, If you want to convert the u-boot users, you
>have to provide an option to go to a command line instead of
>just unconditionally booting linux. Getting to a command line is
>not rocket science...
>
>--- Gregg C Levine <hansolofalcon at worldnet.att.net> wrote:
>>  Hello again from Gregg C Levine
>>  I agree in principle Ron, but I am curious as to why they
>>  thought
>>  that. After all, Linux BIOS does more for a system then
>>  U-Boot. It's
>>  my guess that after seeing the appropriate demonstrations that
>>  group
>>  will change their minds, collectively or otherwise. For that
>>  matter,
>>  Greg W, I applaud your efforts regarding the PPC port.
>>  -------------------
>>  Gregg C Levine hansolofalcon at worldnet.att.net
>>  ------------------------------------------------------------
>>  "The Force will be with you...Always." Obi-Wan Kenobi
>>  "Use the Force, Luke."? Obi-Wan Kenobi
>>  (This company dedicates this E-Mail to General Obi-Wan Kenobi
>>  )
>>  (This company dedicates this E-Mail to Master Yoda )
>>
>>
>>
>>  > -----Original Message-----
>>  > From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
>>  > admin at clustermatic.org] On Behalf Of ron minnich
>>  > Sent: Monday, June 23, 2003 5:47 PM
>>  > To: David Eliasson
>>  > Cc: linuxbios at clustermatic.org
>>  > Subject: Re: LinuxBios PPC-support.. U-Boot project
>>  >
>>  > On Tue, 3 Jun 2003, David Eliasson wrote:
>>  >
>>  > > I read on the linuxbios webpage about PPC-support.. Aren t
>>  you
>>  guys
>>  > > aware of the U-boot project?
>>  >
>>  > Sure.
>>  >
>>  > > They've been running the GNU Linux kernel 2.4.19 and 2.4
>>  21 in
>>  firmware
>>  > > for a while now.. Maybe I m just missing something, but I
>>  thought
>>  some
>>  > > merging of efforts might be in place..
>>  >
>>  > I tried to have a conversation with somebody from u-boot
>>  about some
>>  sort
>>  > of merge, but it never got beyond the "why u-boot is better
>>  than
>>  > linuxbios" stage, so I dropped it.
>>  >
>>  > ron
>>  >
>>  > _______________________________________________
>>  > Linuxbios mailing list
>>  > Linuxbios at clustermatic.org
>>  > http://www.clustermatic.org/mailman/listinfo/linuxbios
>>
>>  _______________________________________________
>>  Linuxbios mailing list
>>  Linuxbios at clustermatic.org
>>  http://www.clustermatic.org/mailman/listinfo/linuxbios
>
>
>__________________________________
>Do you Yahoo!?
>SBC Yahoo! DSL - Now only $29.95 per month!
>http://sbc.yahoo.com
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From frannk_m1 at yahoo.com  Tue Jun 24 21:30:01 2003
From: frannk_m1 at yahoo.com (Frank)
Date: Tue Jun 24 21:30:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <p05210604bb1ea9db0a32@[10.0.1.2]>
Message-ID: <20030625013727.97838.qmail@web13806.mail.yahoo.com>

Interesting, I didn't know that. So I can write my own cli and
jump to it from LinuxBios instead of booting Linux?
--- Greg Watson <gwatson at lanl.gov> wrote:
> Yes, and the nice thing about the linuxbios architecture is
> that the
> CLI can just be a payload, so you can have any CLI that you
> want -
> forth, tcl, whatever. No changes are required to linuxbios at
> all.
> 
> Greg
> 
> At 6:03 PM -0700 24/6/03, Frank wrote:
> >As I said before, If you want to convert the u-boot users,
> you
> >have to provide an option to go to a command line instead of
> >just unconditionally booting linux. Getting to a command line
> is
> >not rocket science...
> >
> >--- Gregg C Levine <hansolofalcon at worldnet.att.net> wrote:
> >>  Hello again from Gregg C Levine
> >>  I agree in principle Ron, but I am curious as to why they
> >>  thought
> >>  that. After all, Linux BIOS does more for a system then
> >>  U-Boot. It's
> >>  my guess that after seeing the appropriate demonstrations
> that
> >>  group
> >>  will change their minds, collectively or otherwise. For
> that
> >>  matter,
> >>  Greg W, I applaud your efforts regarding the PPC port.
> >>  -------------------
> >>  Gregg C Levine hansolofalcon at worldnet.att.net
> >> 
> ------------------------------------------------------------
> >>  "The Force will be with you...Always." Obi-Wan Kenobi
> >>  "Use the Force, Luke."? Obi-Wan Kenobi
> >>  (This company dedicates this E-Mail to General Obi-Wan
> Kenobi
> >>  )
> >>  (This company dedicates this E-Mail to Master Yoda )
> >>
> >>
> >>
> >>  > -----Original Message-----
> >>  > From: linuxbios-admin at clustermatic.org
> [mailto:linuxbios-
> >>  > admin at clustermatic.org] On Behalf Of ron minnich
> >>  > Sent: Monday, June 23, 2003 5:47 PM
> >>  > To: David Eliasson
> >>  > Cc: linuxbios at clustermatic.org
> >>  > Subject: Re: LinuxBios PPC-support.. U-Boot project
> >>  >
> >>  > On Tue, 3 Jun 2003, David Eliasson wrote:
> >>  >
> >>  > > I read on the linuxbios webpage about PPC-support..
> Aren t
> >>  you
> >>  guys
> >>  > > aware of the U-boot project?
> >>  >
> >>  > Sure.
> >>  >
> >>  > > They've been running the GNU Linux kernel 2.4.19 and
> 2.4
> >>  21 in
> >>  firmware
> >>  > > for a while now.. Maybe I m just missing something,
> but I
> >>  thought
> >>  some
> >>  > > merging of efforts might be in place..
> >>  >
> >>  > I tried to have a conversation with somebody from u-boot
> >>  about some
> >>  sort
> >>  > of merge, but it never got beyond the "why u-boot is
> better
> >>  than
> >>  > linuxbios" stage, so I dropped it.
> >>  >
> >>  > ron
> >>  >
> >>  > _______________________________________________
> >>  > Linuxbios mailing list
> >>  > Linuxbios at clustermatic.org
> >>  > http://www.clustermatic.org/mailman/listinfo/linuxbios
> >>
> >>  _______________________________________________
> >>  Linuxbios mailing list
> >>  Linuxbios at clustermatic.org
> >>  http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
> >
> >__________________________________
> >Do you Yahoo!?
> >SBC Yahoo! DSL - Now only $29.95 per month!
> >http://sbc.yahoo.com
> >_______________________________________________
> >Linuxbios mailing list
> >Linuxbios at clustermatic.org
> >http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
http://sbc.yahoo.com


From aip at cwlinux.com  Tue Jun 24 21:53:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Jun 24 21:53:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <20030625013727.97838.qmail@web13806.mail.yahoo.com>; from Frank on Tue, Jun 24, 2003 at 06:37:27PM -0700
References: <p05210604bb1ea9db0a32@[10.0.1.2]> <20030625013727.97838.qmail@web13806.mail.yahoo.com>
Message-ID: <20030625100027.A20011@mail.cwlinux.com>

> Interesting, I didn't know that. So I can write my own cli and
> jump to it from LinuxBios instead of booting Linux?
I think Adam has done LinuxBIOS + Redboot before.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Tue Jun 24 22:03:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 22:03:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <20030625010351.311.qmail@web13808.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0306242009480.24213-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Frank wrote:

> As I said before, If you want to convert the u-boot users, you
> have to provide an option to go to a command line instead of
> just unconditionally booting linux. Getting to a command line is
> not rocket science...

One option is to just take their command-line interpreter and make it a 
payload. I'd like to see someone try that.

ron




From rminnich at lanl.gov  Tue Jun 24 22:05:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Jun 24 22:05:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <20030625013727.97838.qmail@web13806.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0306242010450.24213-100000@maxroach.lanl.gov>

On Tue, 24 Jun 2003, Frank wrote:

> Interesting, I didn't know that. So I can write my own cli and
> jump to it from LinuxBios instead of booting Linux?

absolutely. In essence, that's what etherboot does. See the bare metal 
toolkit for other interesting applications.

This is why the name 'linuxbios' gives us trouble. We've been trying to 
figure out if a name change would cause us more trouble, and so far the 
answer has been 'yes it will cause more trouble'.

ron



From bari at onelabs.com  Tue Jun 24 22:49:00 2003
From: bari at onelabs.com (Bari Ari)
Date: Tue Jun 24 22:49:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
References: <000101c33ab4$eb5ef8e0$239efea9@who5>
Message-ID: <3EF90FAD.7090805@onelabs.com>

Gregg C Levine wrote:

>Hello again from Gregg C Levine
>I agree in principle Ron, but I am curious as to why they thought
>that. After all, Linux BIOS does more for a system then U-Boot. It's
>my guess that after seeing the appropriate demonstrations that group
>will change their minds, collectively or otherwise. 
>
There was quite a bit of bickering on the U-Boot list at the time. 
Things seem to have settled down since last fall and theU-Boot list 
seems to be getting along now. Here are some snippets from last falls 
discussion about this:

LinuxBIOS was designed to use Linux to boot the OS of choice.

> >
> >So was PPCBoot, but without excluding the resto of the world.

>
> So was LinuxBIOS, it currently also boots Plan9 and WinCE.


Bragging about each other's feats won't take us anywhere....


>>>> >>It uses some assembly to do some basic init and config and then jumps to
>>>> >>Linux to fully configure the rest of the system, after that LinuxBIOS
>>>> >>jumps to whatever OS kernel is wanted.
>>>      
>>>
>>> >
>>> >So your boot sequence is LinuxBIOS => Linux => LinuxBIOS => Target OS?
>>    
>>
>>
>> LinuxBIOS (a few lines of assembly and then a Linux kernel) => TargetOS
>>
>  
>

That means in order to use LinuxBIOS on a platform, you first need to have at 
least a basic Linux Kernel that runs on that platform. Thus, if you want to 
port to a new platform, you have to struggle with interrupts, MMU 
initialization, caches, possibly DMA before you get *anything* to run. This 
approach makes perfect sense when the kernel is already there, but to *begin* 
porting at this level -- no thanks!


>> it also supports this boot sequence:
>>
>> LinuxBIOS (few lines of assembly and no Linux kernel)=> EtherBoot =>
>> TargetOS. Linux itself is basically not needed.
>  
>

So where is the gain over e.g. Etherboot without LinuxBIOS ?


I believe it's safe to say that a _merge_ of PPCboot/ARMboot/Blob and 
LinuxBIOS is not going to happen. And rightly so IMHO since they are (valid) 
tools to solve different problems. Even an x86 port of PPCboot would make a 
lot of sense because nothing of this kind exists in the x86 world (at least 
not under GPL). This has been discussed here before (BTW: what's the status 
of the PPCboot/x86 project ?).

Of course the bootloaders contain code which the LinuxBIOS people might find 
useful to rip^H^H^Hre-use (and vice versa). This shouldn't be a problem since 
they are license compatible.

LinuxBIOS was designed to use Linux to boot the OS of choice.

>
> So was PPCBoot, but without excluding the resto of the world.



this is not the forum for PPCBoot vs. LinuxBIOS arguments. I Just Don't
Care. I am sure PPCBoot is wonderful software!


>> So your boot sequence is LinuxBIOS => Linux => LinuxBIOS => Target OS?
>
>  
>

no. The boot sequence is:
- LinuxBIOS -> Linux -> OS (i.e. on Pink)
- LinuxBIOS -> 9load -> Plan 9
- LinuxBIOS -> Etherboot built in to linuxbios -> OS of choice
- LinuxBios -> Etherboot (external ) -> OS of choice

In other words, we have lots of boot sequences depending on the target
system and OS.

The issue of *BSD is not that we can't boot it. We can. The issue is that
*BSD wants to make BIOS calls we don't support.


>> Seems a bit overkill to  me.  Especially  in  systems  where  (flash)
>> memory  is  tight  it  might be a PITA to have to reserve space for a
>> Linux kernel just to initialize the hardware.
>
>  
>

We Have Our Reasons. And, we don't always load linux in flash.


>> The current version of PPCBoot boots Linux, VxWorks, QNX, and NetBSD.
>
>  
>

terrific! I'm happy for you. But this is not a competition.


>> It seems you do not know much about PPCBoot.
>
>  
>

funny, as it seem syou don't know much about linuxbios. So we all need to
read more :-)

>> PPCBoot also provides powerful scripting capabilties; busybox' "hush"
>> shell has been integrated, so you can write standard shell scripts or
>> run  conditional  command  sequences  using  "if...then...else...fi",
>> "for...do...done", "while...do...done", "until...do...done", or using
>> shortcuts like "cmd1 && cmd2" or "cmd1 || cmd2".
>
>  
>

I really don't much like firmware that starts taking on the attributes of
an OS, but to each his own. If you're going to put an OS in firmware, just
make it an OS, not a pseudo-OS. But that's just my opinion.

anyway, I am sure PPCBoot is wonderful, and we should be sharing code, not
getting out our rulers to see whose BIOS is bigger.


-Bari

From bari at onelabs.com  Tue Jun 24 22:51:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Tue Jun 24 22:51:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
References: <Pine.LNX.4.44.0306242010450.24213-100000@maxroach.lanl.gov>
Message-ID: <3EF91031.8080706@onelabs.com>

ron minnich wrote:

>This is why the name 'linuxbios' gives us trouble. We've been trying to 
>figure out if a name change would cause us more trouble, and so far the 
>answer has been 'yes it will cause more trouble'.
>
>  
>
If the situation changes, I parked  www.omniboot.org in case it's ever 
needed.

-Bari




From YhLu at tyan.com  Tue Jun 24 23:27:01 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Jun 24 23:27:01 2003
Subject: coherent hypertransport enumeration on opteron
Message-ID: <3174569B9743D511922F00A0C943142302C44148@TYANWEB>

Eric,

Do you plan use CONFIG_SMP to substitute SMP?

Regards

Yinghai Lu

-----????-----
???: YhLu 
????: 2003?6?24? 16:37
???: 'ebiederman at lnxi.com'
??: ron minnich; Stefan Reinauer; linuxbios at clustermatic.org
??: re: coherent hypertransport enumeration on opteron

Eric,

The RAM on CPU1's northbridge can go through now. I mistype several 0x19 to
0x18.

I have enabled the SMP support in Config file. 
option CONFIG_SMP=1
option MAX_CPUS=2
option SMP=1

As for the missing functions.
 I have copied secondCPU.S and udelay related files to the freebios2.

The result is it can not jumping into LinuxBIOS again.

In the Config last line you said something need to be fixed up.
Do I need to change the START_CPU_SEG ?

Regards

Yinghai Lu



From bari at onelabs.com  Tue Jun 24 23:32:01 2003
From: bari at onelabs.com (Bari Ari)
Date: Tue Jun 24 23:32:01 2003
Subject: Laptops?
References: <Pine.LNX.4.44.0305221512350.20341-100000@maxroach.lanl.gov>	<1053648071.976.95.camel@jcenote>  <3EF78167.1060308@onelabs.com> <1056473190.638.17.camel@jcenote>
Message-ID: <3EF919C7.3060900@onelabs.com>

Jeff Carr wrote:

>I don't know any more than the output of lspci. I've not tried to open
>up the case to see the full board. I've still not been able to get power
>management to work after re-installing it with debian. (sound, USB 2.0
>and ethernet work ok.)
>
>Jeff
>
>FYI: The portable came without any sources. I sent a inquiry about how
>to get them on the website of the people that sold the machine to me,
>but no one responded. (A HUGE GPL violation.) When I re-installed with
>debian, I found the power management(and several other drivers) were
>only in the lindows kernel and I not been able to get them to work
>since. It doens't look like they drivers from the lindows kernel are in
>any of the kernel sources I can find. So, in that regard, angry about
>how "linux support" was provided for this portable would be too light of
>a description.
>  
>
Not surprising on the loss of power management when you dropped Lindows. 
They are probably using a laptop super I/O with a keyboard controller 
(8051 micro with lots of GPIO) by SMSC or a micro by Renasas or Fujitsu 
to handle the keyboard scan and power management.

Some descriptions of the firmware and what they use these micros for:

http://www.insydesw.com/solutions/pc/keyboard.htm

http://www.phoenix.com/en/products/phoenix+cme+firstbios/system+firmware/technologies/phoenix+multikey.htm

-Bari




From ebiederman at lnxi.com  Wed Jun 25 02:41:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 02:41:01 2003
Subject: freebios2: pcibios_read_config_*
In-Reply-To: <Pine.LNX.4.44.0306241345190.11898-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306241345190.11898-100000@maxroach.lanl.gov>
Message-ID: <m3r85iejne.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> these appear to be deprecated? Just checking as they are not in my 
> freebios2 tree any more but code that uses them is still there.

I thought I had removed all of the uses when I made the
changed.  What is there looks like primarily you and Greg.

I see pc80/ide/ide.c.
I see amd8111/amd8111_smbus.c
I see mainboard/arima/1/auto.c

All of those uses are dead code.  The arima/1 has never
really gotten used.  And as the model number of the board
is hdama that directory number needs to change.

The goal is to get us to using a single set of functions in
the tree.  And I think that has been achieved in the active
part of the code.

Eric



From ebiederman at lnxi.com  Wed Jun 25 04:39:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 04:39:00 2003
Subject: coherent hypertransport enumeration on opteron
In-Reply-To: <3174569B9743D511922F00A0C943142302C44148@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C44148@TYANWEB>
Message-ID: <m3el1iczmg.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> Do you plan use CONFIG_SMP to substitute SMP?

Yes.  One of the details that has been problematic is that
our CONFIG defines are not explicitly marked as such.  So in the freebios2
tree I am trying to get things a little more uniform.

Eric



From ebiederman at lnxi.com  Wed Jun 25 04:52:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 04:52:00 2003
Subject: coherent hypertransport enumeration on opteron
In-Reply-To: <3174569B9743D511922F00A0C943142302C44109@TYANWEB>
References: <3174569B9743D511922F00A0C943142302C44109@TYANWEB>
Message-ID: <m3adc6cz00.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> The RAM on CPU1's northbridge can go through now. I mistype several 0x19 to
> 0x18.
> 
> I have enabled the SMP support in Config file. 
> option CONFIG_SMP=1
> option MAX_CPUS=2
> option SMP=1
> 
> As for the missing functions.
>  I have copied secondCPU.S and udelay related files to the freebios2.
> 
> The result is it can not jumping into LinuxBIOS again.
> 
> In the Config last line you said something need to be fixed up.
> Do I need to change the START_CPU_SEG ?

Not that is fine.  It is an old cut and past bug.  I actually don't
think START_CPU_SEG is used anymore.

Eric



From ebiederman at lnxi.com  Wed Jun 25 08:47:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 08:47:00 2003
Subject: romcc ramblings...
Message-ID: <m3k7bas4dx.fsf@maxwell.lnxi.com>

Romcc is coming along quite nicely.  I keep fixing a corner
case here and there but it quite usable and getting more so.

One area where it falls short is in it's handling of lots of small
variables.  The classic question is:  If I declare my small variables
to be chars will romcc be able to store them in both AL and AH?

And unfortunately the answer is no.  Using the AH, BH, CH, and DH
at least when I tried it did not work well.  Treating all of the
registers the same seems to work much better.

A similar question is can romcc pack 2 byte values in a random
register?  The answer again is no.  But for a different reason
extracting and reinserting the values requires an extra register,
so it is not a transformation I want to perform automatically.

With that being said I do think it is worth having romcc support
keeping multiple values in a register.  Otherwise I will wind
up writing a bunch of macros like:

#define LATENCY(MIN) (((MIN) >> 8) & 0xff)
#define SET_LATENCY(MIN, LATENCY) ((MIN) = (((MIN) & ~(0xff << 8)) | (((LATENCY) & 0xFF) << 8)))
#define CYCLE_TIME(MIN) ((MIN) & 0xff)
#define SET_CYCLE_TIME(MIN, CYCLE_TIME) ((MIN) = (((MIN) & ~0xff) |
#((CYCLE_TIME) & 0xFF)))











So many times while in your registers you have enough bits to hold everything
you want to hold
Theoretically 



From ebiederman at lnxi.com  Wed Jun 25 09:03:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 09:03:01 2003
Subject: romcc ramblings...
Message-ID: <m3he6es3nm.fsf@maxwell.lnxi.com>

Romcc is coming along quite nicely.  I keep fixing a corner
case here and there but it quite usable and getting more so.

One area where it falls short is in it's handling of lots of small
variables.  The classic question is:  If I declare my small variables
to be chars will romcc be able to store them in both AL and AH?

And unfortunately the answer is no.  Using the AH, BH, CH, and DH
at least when I tried it did not work well.  Treating all of the
registers the same seems to work much better.

A similar question is can romcc pack 2 byte values in a random
register?  The answer again is no.  But for a different reason
extracting and reinserting the values requires an extra register,
so it is not a transformation I want to perform automatically.

With that being said I do think it is worth having romcc support
keeping multiple values in a register.  Otherwise I will wind
up writing a bunch of macros like:

#define LATENCY(MIN) (((MIN) >> 8) & 0xff)
#define SET_LATENCY(MIN, LATENCY) ((MIN) = (((MIN) & ~(0xff << 8)) | (((LATENCY) & 0xFF) << 8)))
#define CYCLE_TIME(MIN) ((MIN) & 0xff)
#define SET_CYCLE_TIME(MIN, CYCLE_TIME) ((MIN) = (((MIN) & ~0xff) | ((CYCLE_TIME) & 0xFF)))


Which look ugly are a bit of a pain to write.  I looked an C actually
has a mechanism to do this already.  bit fields in structures.  For
doing I/O to the outside world they are not portable.  So their use
is discouraged.

For internal values that are just going to be used internally by
a program, say packing multiple values in a single register they are 
portable and a decent way to describe what is going on.

So to keep 2 byte values in I register I could do:
struct {
        unsigned latency:8;
        unsigned cycle_time:8;
} min;

I have not implemented this but I plan to.  For both programmer control and 
ease of use it looks like a win.


Eric




From rminnich at lanl.gov  Wed Jun 25 10:17:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 25 10:17:01 2003
Subject: freebios2: pcibios_read_config_*
In-Reply-To: <m3r85iejne.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306250823070.30061-100000@maxroach.lanl.gov>

On 25 Jun 2003, Eric W. Biederman wrote:

> All of those uses are dead code.  The arima/1 has never
> really gotten used.  And as the model number of the board
> is hdama that directory number needs to change.

I changed that now; it became clear that use of that name was acceptable. 
1 is going to go.


ron



From tyson at irobot.com  Wed Jun 25 10:54:00 2003
From: tyson at irobot.com (tyson at irobot.com)
Date: Wed Jun 25 10:54:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <Pine.LNX.4.44.0306242009480.24213-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306242009480.24213-100000@maxroach.lanl.gov>
Message-ID: <3EF9B90C.5080408@irobot.com>

A command line is a key part of how we use our (now very old) version of 
linuxbios.  Though what we are using is from the dark ages, based on 
what I've seen linxbios become, I think that making a command line 
utility be a payload is the right solution.

Ty

ron minnich wrote:
> On Tue, 24 Jun 2003, Frank wrote:
> 
> 
>>As I said before, If you want to convert the u-boot users, you
>>have to provide an option to go to a command line instead of
>>just unconditionally booting linux. Getting to a command line is
>>not rocket science...
> 
> 
> One option is to just take their command-line interpreter and make it a 
> payload. I'd like to see someone try that.
> 
> ron
> 
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios


-- 
Tyson D Sawyer                             iRobot Corporation
Senior Systems Engineer                    Military Systems Division
tsawyer at irobot.com                         Robots for the Real World
603-654-3400 ext 206                       http://www.irobot.com



From rminnich at lanl.gov  Wed Jun 25 11:05:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 25 11:05:01 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
Message-ID: <Pine.LNX.4.44.0306250910580.30061-100000@maxroach.lanl.gov>

The above combination works pretty well until I try to program the part, 
at which point the kernel takes an oops and dies. 

I'm wondering if anyone else has either:
- seen this work 
- seen this fail

thanks

ron



From ebiederman at lnxi.com  Wed Jun 25 11:47:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 11:47:01 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
In-Reply-To: <Pine.LNX.4.44.0306250910580.30061-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306250910580.30061-100000@maxroach.lanl.gov>
Message-ID: <m3y8zqkv6z.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> The above combination works pretty well until I try to program the part, 
> at which point the kernel takes an oops and dies. 
> 
> I'm wondering if anyone else has either:
> - seen this work 
> - seen this fail

That is what I have working right now.  

I haven't used it much on the hdama more on the solo.  But kernel wise
it is the same hardware.

OTOH 2.4.19 started with some old MTD drivers.  So I don't know how current
you are.

Eric



From rminnich at lanl.gov  Wed Jun 25 12:00:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 25 12:00:01 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
In-Reply-To: <m3y8zqkv6z.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0306251007070.31015-100000@maxroach.lanl.gov>

On 25 Jun 2003, Eric W. Biederman wrote:

> That is what I have working right now.  

just checking, you're running the 64-bit kernel? 

I guess I'll yank down the newest MTD cvs and try again.

ron



From YhLu at tyan.com  Wed Jun 25 12:58:00 2003
From: YhLu at tyan.com (YhLu)
Date: Wed Jun 25 12:58:00 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
Message-ID: <3174569B9743D511922F00A0C943142302C4417D@TYANWEB>

Ron,

Did you use SMP support or not?

I use NON-SMP support in Tyan S2880 and it die in the Kernel too.

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?6?25? 8:13
???: linuxbios at clustermatic.org
??: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD


The above combination works pretty well until I try to program the part, 
at which point the kernel takes an oops and dies. 

I'm wondering if anyone else has either:
- seen this work 
- seen this fail

thanks

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From YhLu at tyan.com  Wed Jun 25 13:00:00 2003
From: YhLu at tyan.com (YhLu)
Date: Wed Jun 25 13:00:00 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
Message-ID: <3174569B9743D511922F00A0C943142302C4417F@TYANWEB>

Ron,

I use 16M ramdisk that will downloaded into Node with Kernel at the same
time. So didn't use MTD etc.

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?6?25? 9:08
???: Eric W. Biederman
??: linuxbios at clustermatic.org
??: Re: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD

On 25 Jun 2003, Eric W. Biederman wrote:

> That is what I have working right now.  

just checking, you're running the 64-bit kernel? 

I guess I'll yank down the newest MTD cvs and try again.

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From frannk_m1 at yahoo.com  Wed Jun 25 13:09:00 2003
From: frannk_m1 at yahoo.com (Frank)
Date: Wed Jun 25 13:09:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <3EF90FAD.7090805@onelabs.com>
Message-ID: <20030625171636.35640.qmail@web13804.mail.yahoo.com>

u-boot's weakness is that it primarily supports arm and ppc
processors. There is only one x86 board in the source tree and
it won't even compile! If u-boot had more support for x86
platforms, it would give linuxbios a serious run for it's money.

--- Bari Ari <bari at onelabs.com> wrote:
> Gregg C Levine wrote:
> 
> >Hello again from Gregg C Levine
> >I agree in principle Ron, but I am curious as to why they
> thought
> >that. After all, Linux BIOS does more for a system then
> U-Boot. It's
> >my guess that after seeing the appropriate demonstrations
> that group
> >will change their minds, collectively or otherwise. 
> >
> There was quite a bit of bickering on the U-Boot list at the
> time. 
> Things seem to have settled down since last fall and theU-Boot
> list 
> seems to be getting along now. Here are some snippets from
> last falls 
> discussion about this:
> 
> LinuxBIOS was designed to use Linux to boot the OS of choice.
> 
> > >
> > >So was PPCBoot, but without excluding the resto of the
> world.
> 
> >
> > So was LinuxBIOS, it currently also boots Plan9 and WinCE.
> 
> 
> Bragging about each other's feats won't take us anywhere....
> 
> 
> >>>> >>It uses some assembly to do some basic init and config
> and then jumps to
> >>>> >>Linux to fully configure the rest of the system, after
> that LinuxBIOS
> >>>> >>jumps to whatever OS kernel is wanted.
> >>>      
> >>>
> >>> >
> >>> >So your boot sequence is LinuxBIOS => Linux => LinuxBIOS
> => Target OS?
> >>    
> >>
> >>
> >> LinuxBIOS (a few lines of assembly and then a Linux kernel)
> => TargetOS
> >>
> >  
> >
> 
> That means in order to use LinuxBIOS on a platform, you first
> need to have at 
> least a basic Linux Kernel that runs on that platform. Thus,
> if you want to 
> port to a new platform, you have to struggle with interrupts,
> MMU 
> initialization, caches, possibly DMA before you get *anything*
> to run. This 
> approach makes perfect sense when the kernel is already there,
> but to *begin* 
> porting at this level -- no thanks!
> 
> 
> >> it also supports this boot sequence:
> >>
> >> LinuxBIOS (few lines of assembly and no Linux kernel)=>
> EtherBoot =>
> >> TargetOS. Linux itself is basically not needed.
> >  
> >
> 
> So where is the gain over e.g. Etherboot without LinuxBIOS ?
> 
> 
> I believe it's safe to say that a _merge_ of
> PPCboot/ARMboot/Blob and 
> LinuxBIOS is not going to happen. And rightly so IMHO since
> they are (valid) 
> tools to solve different problems. Even an x86 port of PPCboot
> would make a 
> lot of sense because nothing of this kind exists in the x86
> world (at least 
> not under GPL). This has been discussed here before (BTW:
> what's the status 
> of the PPCboot/x86 project ?).
> 
> Of course the bootloaders contain code which the LinuxBIOS
> people might find 
> useful to rip^H^H^Hre-use (and vice versa). This shouldn't be
> a problem since 
> they are license compatible.
> 
> LinuxBIOS was designed to use Linux to boot the OS of choice.
> 
> >
> > So was PPCBoot, but without excluding the resto of the
> world.
> 
> 
> 
> this is not the forum for PPCBoot vs. LinuxBIOS arguments. I
> Just Don't
> Care. I am sure PPCBoot is wonderful software!
> 
> 
> >> So your boot sequence is LinuxBIOS => Linux => LinuxBIOS =>
> Target OS?
> >
> >  
> >
> 
> no. The boot sequence is:
> - LinuxBIOS -> Linux -> OS (i.e. on Pink)
> - LinuxBIOS -> 9load -> Plan 9
> - LinuxBIOS -> Etherboot built in to linuxbios -> OS of choice
> - LinuxBios -> Etherboot (external ) -> OS of choice
> 
> In other words, we have lots of boot sequences depending on
> the target
> system and OS.
> 
> The issue of *BSD is not that we can't boot it. We can. The
> issue is that
> *BSD wants to make BIOS calls we don't support.
> 
> 
> >> Seems a bit overkill to  me.  Especially  in  systems 
> where  (flash)
> >> memory  is  tight  it  might be a PITA to have to reserve
> space for a
> >> Linux kernel just to initialize the hardware.
> >
> >  
> >
> 
> We Have Our Reasons. And, we don't always load linux in flash.
> 
> 
> >> The current version of PPCBoot boots Linux, VxWorks, QNX,
> and NetBSD.
> >
> >  
> >
> 
> terrific! I'm happy for you. But this is not a competition.
> 
> 
> >> It seems you do not know much about PPCBoot.
> >
> >  
> >
> 
> funny, as it seem syou don't know much about linuxbios. So we
> all need to
> read more :-)
> 
> >> PPCBoot also provides powerful scripting capabilties;
> busybox' "hush"
> >> shell has been integrated, so you can write standard shell
> scripts or
> >> run  conditional  command  sequences  using 
> "if...then...else...fi",
> >> "for...do...done", "while...do...done",
> "until...do...done", or using
> >> shortcuts like "cmd1 && cmd2" or "cmd1 || cmd2".
> >
> >  
> >
> 
> I really don't much like firmware that starts taking on the
> attributes of
> an OS, but to each his own. If you're going to put an OS in
> firmware, just
> make it an OS, not a pseudo-OS. But that's just my opinion.
> 
> anyway, I am sure PPCBoot is wonderful, and we should be
> sharing code, not
> getting out our rulers to see whose BIOS is bigger.
> 
> 
> -Bari
> 


__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
http://sbc.yahoo.com


From rminnich at lanl.gov  Wed Jun 25 13:15:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 25 13:15:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <20030625171636.35640.qmail@web13804.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0306251120590.31015-100000@maxroach.lanl.gov>

On Wed, 25 Jun 2003, Frank wrote:

> u-boot's weakness is that it primarily supports arm and ppc
> processors. There is only one x86 board in the source tree and
> it won't even compile! If u-boot had more support for x86
> platforms, it would give linuxbios a serious run for it's money.

yeah but why do it this way. With the openbios guys, we've ended up 
splitting the work: linuxbios does the cruft, openbios does the forth 
stuff. IF uboot wants that command interpreter, why not combine forces and 
make the CLI a payload, and linuxbios sucks in all that good u-boot cpu 
stuff. 

seems like we'd get twice as far.

ron



From frannk_m1 at yahoo.com  Wed Jun 25 13:23:00 2003
From: frannk_m1 at yahoo.com (Frank)
Date: Wed Jun 25 13:23:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <Pine.LNX.4.44.0306251120590.31015-100000@maxroach.lanl.gov>
Message-ID: <20030625173045.19863.qmail@web13805.mail.yahoo.com>

Very good idea...
--- ron minnich <rminnich at lanl.gov> wrote:
> On Wed, 25 Jun 2003, Frank wrote:
> 
> > u-boot's weakness is that it primarily supports arm and ppc
> > processors. There is only one x86 board in the source tree
> and
> > it won't even compile! If u-boot had more support for x86
> > platforms, it would give linuxbios a serious run for it's
> money.
> 
> yeah but why do it this way. With the openbios guys, we've
> ended up 
> splitting the work: linuxbios does the cruft, openbios does
> the forth 
> stuff. IF uboot wants that command interpreter, why not
> combine forces and 
> make the CLI a payload, and linuxbios sucks in all that good
> u-boot cpu 
> stuff. 
> 
> seems like we'd get twice as far.
> 
> ron
> 


__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
http://sbc.yahoo.com


From ebiederman at lnxi.com  Wed Jun 25 13:34:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 13:34:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <20030625171636.35640.qmail@web13804.mail.yahoo.com>
References: <20030625171636.35640.qmail@web13804.mail.yahoo.com>
Message-ID: <m34r2edper.fsf@maxwell.lnxi.com>

Frank <frannk_m1 at yahoo.com> writes:

> u-boot's weakness is that it primarily supports arm and ppc
> processors. There is only one x86 board in the source tree and
> it won't even compile! If u-boot had more support for x86
> platforms, it would give linuxbios a serious run for it's money.

There is also the fact that all of the platforms U-Boot runs
on appear to be very simple ones.  No complicated
SPD base memory initialization, etc.

LinuxBIOS supports much more complicated hardware.

That is the other reason for the design skew.  If you can write
proper memory initialization code in a day.  You can put it in
your bootloader.  If it takes a week or two, separating board
initialization and your bootloader makes a lot more sense.

Eric



From frannk_m1 at yahoo.com  Wed Jun 25 13:45:01 2003
From: frannk_m1 at yahoo.com (Frank)
Date: Wed Jun 25 13:45:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <m34r2edper.fsf@maxwell.lnxi.com>
Message-ID: <20030625175238.41109.qmail@web13803.mail.yahoo.com>

No, I beg to differ. I have ported u-boot to more then one ppc
based platform. Thye do have SPD support. I ported over to the
ppc750fx (with a Marvel 64360 system controller) and the 440gp
based platforms
--- "Eric W. Biederman" <ebiederman at lnxi.com> wrote:
> Frank <frannk_m1 at yahoo.com> writes:
> 
> > u-boot's weakness is that it primarily supports arm and ppc
> > processors. There is only one x86 board in the source tree
> and
> > it won't even compile! If u-boot had more support for x86
> > platforms, it would give linuxbios a serious run for it's
> money.
> 
> There is also the fact that all of the platforms U-Boot runs
> on appear to be very simple ones.  No complicated
> SPD base memory initialization, etc.
> 
> LinuxBIOS supports much more complicated hardware.
> 
> That is the other reason for the design skew.  If you can
> write
> proper memory initialization code in a day.  You can put it in
> your bootloader.  If it takes a week or two, separating board
> initialization and your bootloader makes a lot more sense.
> 
> Eric
> 


__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
http://sbc.yahoo.com


From ebiederman at lnxi.com  Wed Jun 25 14:23:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 14:23:01 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <20030625175238.41109.qmail@web13803.mail.yahoo.com>
References: <20030625175238.41109.qmail@web13803.mail.yahoo.com>
Message-ID: <m3ptl280w3.fsf@maxwell.lnxi.com>

Frank <frannk_m1 at yahoo.com> writes:

> No, I beg to differ. I have ported u-boot to more then one ppc
> based platform. Thye do have SPD support. I ported over to the
> ppc750fx (with a Marvel 64360 system controller) and the 440gp
> based platforms

Oh interesting.  I still think LinuxBIOS runs on more challenging
platforms, but the dividing line seems to farther out than
I thought.

Eric



From rminnich at lanl.gov  Wed Jun 25 18:00:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Jun 25 18:00:00 2003
Subject: freebios2 + k8 users
Message-ID: <Pine.LNX.4.44.0306251606100.1241-100000@maxroach.lanl.gov>

Just to make sure I'm in sync, I'm assuming you all are building fallback 
images only? Or are you building normal images? I'm building fallback but 
...

ron



From ebiederman at lnxi.com  Wed Jun 25 18:21:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Jun 25 18:21:01 2003
Subject: freebios2 + k8 users
In-Reply-To: <Pine.LNX.4.44.0306251606100.1241-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306251606100.1241-100000@maxroach.lanl.gov>
Message-ID: <m3k7b97pt3.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> Just to make sure I'm in sync, I'm assuming you all are building fallback 
> images only? Or are you building normal images? I'm building fallback but 
> ...

I have them both working.  inling everything in romcc generates quite
a bit of code bloat so I had to bump my fallback image to 128K.  But
it is working quite nicely.  So far I am not using the HDAMA though...

Eric



From stepan at suse.de  Thu Jun 26 03:59:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Jun 26 03:59:00 2003
Subject: LinuxBios PPC-support.. U-Boot project
In-Reply-To: <Pine.LNX.4.44.0306251120590.31015-100000@maxroach.lanl.gov>
References: <20030625171636.35640.qmail@web13804.mail.yahoo.com> <Pine.LNX.4.44.0306251120590.31015-100000@maxroach.lanl.gov>
Message-ID: <20030626080538.GC5220@suse.de>

* ron minnich <rminnich at lanl.gov> [030625 19:22]:
> yeah but why do it this way. With the openbios guys, we've ended up 
> splitting the work: linuxbios does the cruft, openbios does the forth 
> stuff. IF uboot wants that command interpreter, why not combine forces and 

I've gotten OpenBIOS a bit further last weekend, seperating architecture 
dependent and independent code and getting the dictionary from a fixed
address in flash. Still missing is the code to load the forth dictionary
right from an elf segment.
On the interpreter front I have all the forth words working that are
needed for the interpreter, and the interpreter loop already reads and
outputs things, but thats about it. 
Being busy with LinuxBIOS during the week made me enjoying the sun
rather than my suns on the weekend :-)

  Stefan

-- 
Architecture Team
    SuSE Linux AG


From tuguangxiu at yahoo.com  Thu Jun 26 05:42:00 2003
From: tuguangxiu at yahoo.com (tu guangxiu)
Date: Thu Jun 26 05:42:00 2003
Subject: kernel 2.4.21 patch for sis630
Message-ID: <20030626094910.55728.qmail@web13303.mail.yahoo.com>

Dear lists,
   who have kernel 2.4.21 patch for sis630?  patch of 2.4.19 has several rejects.
 
  thanks
    tu
 


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From faraway at eyou.com  Thu Jun 26 06:17:00 2003
From: faraway at eyou.com (Ivan)
Date: Thu Jun 26 06:17:00 2003
Subject: i&nbsp;can&nbsp;flash&nbsp;the&nbsp;doc&nbsp;successfully,&nbsp;but&nbsp;it&nbsp;doesn't&nbsp;boot
Message-ID: <20030626182552.38485.qmail@eyou.com>

Hi all:
    I reinstall my rh8.0 today, and i try to flash the image(the one i
download from cwlinux) to the doc on my m810lmr board, nothing error
message(the same as before, all seem normal), and when i reboot, it cannot
boot.
    I try another DOC, and the same problem.
    I'm sure no problem with the image.
    I got the same trouble when i upgrade my linux to rh9.0 before, so i
changed 
something, then it ok, but i can't remmber what i have done.....
    Any advices?
    Thanks in advance!

                                                                 ivan 
    





--http://www.eyou.com
--??????????????????????  ????????  ????????  ????????  ????????...????????




From rminnich at lanl.gov  Thu Jun 26 09:24:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Jun 26 09:24:00 2003
Subject: kernel 2.4.21 patch for sis630
In-Reply-To: <20030626094910.55728.qmail@web13303.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0306260730340.9691-100000@maxroach.lanl.gov>

On Thu, 26 Jun 2003, tu guangxiu wrote:

>    who have kernel 2.4.21 patch for sis630?  patch of 2.4.19 has several
> rejects.

no one has it. I am afraid you will have to fix the rejects. If you can 
forward me a 2.4.21 patch in time I will committ it.

ron



From amits at myrealbox.com  Thu Jun 26 13:07:01 2003
From: amits at myrealbox.com (Amit Shirodkar)
Date: Thu Jun 26 13:07:01 2003
Subject: Is the via apollo pro133 supported?
References: <Pine.LNX.4.44.0306260730340.9691-100000@maxroach.lanl.gov>
Message-ID: <000e01c33b3d$283f8080$364a013d@LocalHost>

Hi Guys,

I am new to this list....i plan to do a linux bios on my  elite p6bap-me
mainboard this is a via 693a +596b based board....i know this chipset sucks
but i own it...so i have to use it!Has some one tried linux bios with this
chipset?

well thanks in advance.

rgds,
Amit.



From lpacheco at netvisao.pt  Thu Jun 26 14:38:00 2003
From: lpacheco at netvisao.pt (Luis Pacheco)
Date: Thu Jun 26 14:38:00 2003
Subject: Problem CPU Clock
Message-ID: <1056656715.18614.4.camel@toshiba>

Hi there,

I'm running linuxbios with motherboard pcchips 810mlr..
But there is an little problem.. :)
I've an Athlon 2000+ XP but with linuxbios we puts the processor with an
clock like an 1200+ XP :(

Does anyone known howto to change that...?

Thanks

-- 
Luis Andr?? Pacheco
http://www.neuralbit.com



From YhLu at tyan.com  Thu Jun 26 22:25:01 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Jun 26 22:25:01 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
Message-ID: <3174569B9743D511922F00A0C943142302DD0685@TYANWEB>

Eric,

I have some questions about the APIC.
How can I change the Second Opteron's  APIC_ID? DO I need to make the second
CPU run and its process access (APIC_DEFAULT_BASE+APIC_ID) and set (1<<24)
to it.

Then When should start the process in auto.c or hardwaremain.c (
startup_other_cpus function)?  I have tried to add one branch in auto.c and
seems the second cpu start only from crt0.base. and it try copy LinBIOS and
Jump

Regards

Yinghai Lu

-----????-----
???: ron minnich [mailto:rminnich at lanl.gov] 
????: 2003?6?25? 8:13
???: linuxbios at clustermatic.org
??: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD


The above combination works pretty well until I try to program the part, 
at which point the kernel takes an oops and dies. 

I'm wondering if anyone else has either:
- seen this work 
- seen this fail

thanks

ron

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From Phreak_Show at gmx.de  Fri Jun 27 11:28:00 2003
From: Phreak_Show at gmx.de (Stefan)
Date: Fri Jun 27 11:28:00 2003
Subject: Problem CPU Clock
In-Reply-To: <1056656715.18614.4.camel@toshiba>
References: <1056656715.18614.4.camel@toshiba>
Message-ID: <3EFC6397.9080509@gmx.de>

There might be problem with the FrontSideBus, make sure that is doesn't 
run at 100MHz

Luis Pacheco wrote:

>Hi there,
>
>I'm running linuxbios with motherboard pcchips 810mlr..
>But there is an little problem.. :)
>I've an Athlon 2000+ XP but with linuxbios we puts the processor with an
>clock like an 1200+ XP :(
>
>Does anyone known howto to change that...?
>
>Thanks
>
>  
>




From lpacheco at netvisao.pt  Fri Jun 27 14:12:01 2003
From: lpacheco at netvisao.pt (Luis Pacheco)
Date: Fri Jun 27 14:12:01 2003
Subject: Problem CPU Clock
In-Reply-To: <3EFC6397.9080509@gmx.de>
References: <1056656715.18614.4.camel@toshiba>  <3EFC6397.9080509@gmx.de>
Message-ID: <1056741601.1884.1.camel@pa-217-129-59-99.netvisao.pt>

Sorry for asking.. but how can i force that on linuxbios compilation?
Because this board dont have jumpers....

On Fri, 2003-06-27 at 15:32, Stefan wrote:
> There might be problem with the FrontSideBus, make sure that is doesn't 
> run at 100MHz
> 
> Luis Pacheco wrote:
> 
> >Hi there,
> >
> >I'm running linuxbios with motherboard pcchips 810mlr..
> >But there is an little problem.. :)
> >I've an Athlon 2000+ XP but with linuxbios we puts the processor with an
> >clock like an 1200+ XP :(
> >
> >Does anyone known howto to change that...?
> >
> >Thanks
> >
> >  
> >
-- 
Luis Andr?? Pacheco
http://www.neuralbit.com



From tuguangxiu at yahoo.com  Sat Jun 28 01:33:01 2003
From: tuguangxiu at yahoo.com (tu guangxiu)
Date: Sat Jun 28 01:33:01 2003
Subject: Problem CPU Clock
In-Reply-To: <3EFC6397.9080509@gmx.de>
Message-ID: <20030628054056.77164.qmail@web13306.mail.yahoo.com>

can linuxbios support 100M FSB for sis630?  
thanks


Stefan <Phreak_Show at gmx.de> wrote:
There might be problem with the FrontSideBus, make sure that is doesn't 
run at 100MHz

Luis Pacheco wrote:

>Hi there,
>
>I'm running linuxbios with motherboard pcchips 810mlr..
>But there is an little problem.. :)
>I've an Athlon 2000+ XP but with linuxbios we puts the processor with an
>clock like an 1200+ XP :(
>
>Does anyone known howto to change that...?
>
>Thanks
>
> 
>


_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


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From Phreak_Show at gmx.de  Sat Jun 28 06:46:01 2003
From: Phreak_Show at gmx.de (Stefan)
Date: Sat Jun 28 06:46:01 2003
Subject: Problem CPU Clock
In-Reply-To: <20030628054056.77164.qmail@web13306.mail.yahoo.com>
References: <20030628054056.77164.qmail@web13306.mail.yahoo.com>
Message-ID: <3EFD72F4.3040506@gmx.de>

Sorry, but I don't know!

tu guangxiu wrote:

> can linuxbios support 100M FSB for sis630? 
> thanks
>
>
> */Stefan <Phreak_Show at gmx.de>/* wrote:
>
>     There might be problem with the FrontSideBus, make sure that is
>     doesn't
>     run at 100MHz
>
>     Luis Pacheco wrote:
>
>     >Hi there,
>     >
>     >I'm running linuxbios with motherboard pcchips 810mlr..
>     >But there is an little problem.. :)
>     >I've an Athlon 2000+ XP but with linuxbios we puts the processor
>     with an
>     >clock like an 1200+ XP :(
>     >
>     >Does anyone known howto to change that...?
>     >
>     >Thanks
>     >
>     >
>     >
>
>
>     _______________________________________________
>     Linuxbios mailing list
>     Linuxbios at clustermatic.org
>     http://www.clustermatic.org/mailman/listinfo/linuxbios
>
> ------------------------------------------------------------------------
> Do you Yahoo!?
> SBC Yahoo! DSL 
> <http://pa.yahoo.com/*http://rd.yahoo.com/evt=1207/*http://promo.yahoo.com/sbc/> 
> - Now only $29.95 per month! 





From ebiederman at lnxi.com  Sat Jun 28 12:06:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sat Jun 28 12:06:01 2003
Subject: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
In-Reply-To: <3174569B9743D511922F00A0C943142302DD0685@TYANWEB>
References: <3174569B9743D511922F00A0C943142302DD0685@TYANWEB>
Message-ID: <m3llvmjhza.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> Eric,
> 
> I have some questions about the APIC.
> How can I change the Second Opteron's  APIC_ID? DO I need to make the second
> CPU run and its process access (APIC_DEFAULT_BASE+APIC_ID) and set (1<<24)
> to it.

You need to know the apic id before you can start code on the second
cpu.  I recall seeing how how this is set in the BIOS programmers guide.
Look under unit id.

> Then When should start the process in auto.c or hardwaremain.c (
> startup_other_cpus function)?  I have tried to add one branch in auto.c and
> seems the second cpu start only from crt0.base. and it try copy LinBIOS and
> Jump

You definitely want to use the code in startup_other_cpus.
There is no good reason to run to multiple cpus in auto.c

Eric



From root at hamburg.de  Sat Jun 28 18:18:01 2003
From: root at hamburg.de (Felix Kloeckner)
Date: Sat Jun 28 18:18:01 2003
Subject: Problem CPU Clock
In-Reply-To: <3EFD72F4.3040506@gmx.de>; from Phreak_Show@gmx.de on Sat, Jun 28, 2003 at 12:50:28 +0200
References: <20030628054056.77164.qmail@web13306.mail.yahoo.com> <3EFD72F4.3040506@gmx.de>
Message-ID: <20030629002347.C31426@synapse.pentanet>

take a look at
"/freebios/src/northsouthbridge/sis/630/630_regs.inc"
"/freebios/src/northsouthbridge/sis/630/630s_regs.inc"

dont't have my board at home to test, but should be worth trying

On 2003.06.28 12:50 Stefan wrote:
> Sorry, but I don't know!
> 
> tu guangxiu wrote:
> 
> > can linuxbios support 100M FSB for sis630? 
> > thanks
> >
> >
> > */Stefan <Phreak_Show at gmx.de>/* wrote:
> >
> >     There might be problem with the FrontSideBus, make sure that is
> >     doesn't
> >     run at 100MHz
> >
> >     Luis Pacheco wrote:
> >
> >     >Hi there,
> >     >
> >     >I'm running linuxbios with motherboard pcchips 810mlr..
> >     >But there is an little problem.. :)
> >     >I've an Athlon 2000+ XP but with linuxbios we puts the processor
> >     with an
> >     >clock like an 1200+ XP :(
> >     >
> >     >Does anyone known howto to change that...?
> >     >
> >     >Thanks
> >     >
> >     >
> >     >
> >
> >
> >     _______________________________________________
> >     Linuxbios mailing list
> >     Linuxbios at clustermatic.org
> >     http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
> > ------------------------------------------------------------------------
> > Do you Yahoo!?
> > SBC Yahoo! DSL 
> > <http://pa.yahoo.com/*http://rd.yahoo.com/evt=1207/*http://promo.yahoo.com/sbc/> 
> > - Now only $29.95 per month! 
> 
> 
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
> 


From tuguangxiu at yahoo.com  Mon Jun 30 08:23:00 2003
From: tuguangxiu at yahoo.com (tu guangxiu)
Date: Mon Jun 30 08:23:00 2003
Subject: linux 2.4.21 patch for sis630
In-Reply-To: <20030629002347.C31426@synapse.pentanet>
Message-ID: <20030630123109.44292.qmail@web13304.mail.yahoo.com>

I have made one patch for linux 2.4.21 for winfast6300 mb.  please test it.
 
 



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From rminnich at lanl.gov  Mon Jun 30 09:32:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 30 09:32:01 2003
Subject: [commit] epia-m again (fwd)
Message-ID: <Pine.LNX.4.44.0306300740200.29922-100000@maxroach.lanl.gov>


---------- Forwarded message ----------
Date: Mon, 30 Jun 2003 16:09:02 +0800
From: Andrew Ip <aip at cwlinux.com>
Subject: [commit] epia-m again

Hi,

	Since I'm no cvs expert in un-remove file from the source tree,
it took much longer than I thought.  Also, Sourceforge is slow and unstable 
lately.  My checkins weren't shown up from either cvs view and cvs co
'till I looked at it again this afternoon.  Anyway, epia-m is just committed.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.



From rminnich at lanl.gov  Mon Jun 30 11:14:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 30 11:14:01 2003
Subject: move to bitkeeper?
Message-ID: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>

sourceforge is really having trouble nowadays. Half my browsers think the 
web pages are to be downloaded for some reason; cvs updates are seeing 
24-hour delays; and random outages are a daily occurence. 

I've noticed that lots of high-profile projects are now mastering on 
bitkeeper.com, including the linux kernel and the infiniband project.

Any comments or objections to me at least looking into a move to 
bitkeeper.com? It has lots of advantages, not the least that it supports 
distributed repositories. 

Anyone have anything to say about this, pro or con?

ron



From hansolofalcon at worldnet.att.net  Mon Jun 30 12:29:00 2003
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Mon Jun 30 12:29:00 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
Message-ID: <!~!UENERkVCMDkAAQACAAAAAAAAAAAAAAAAABgAAAAAAAAAJX/cR7931hGLXAABAjrE9eKAAAAQAAAAKZD2/vWq1xGLZwABAjrE9QEAAAAA@worldnet.att.net>

Hello from Gregg C Levine
Good question. However, I haven't had any problems visiting the
project pages for the project. I agree, that the CVS stores indicate
that there's an unnecessary delay of about a day, but that's only on
the view function for CVS. They say that the problems are being
corrected. That they are busy pruning a lot of the dead projects, and
otherwise cleaning things up. 

Now the other question. Ron, which browsers are telling you this? I
can view all of the project pages without difficulty, on MSIE, and the
version of Netscape delivered on Slackware 8.0, also with the browsers
that came with Gnome.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
(This company dedicates this E-Mail to General Obi-Wan Kenobi )
(This company dedicates this E-Mail to Master Yoda )



> -----Original Message-----
> From: linuxbios-admin at clustermatic.org [mailto:linuxbios-
> admin at clustermatic.org] On Behalf Of ron minnich
> Sent: Monday, June 30, 2003 11:22 AM
> To: linuxbios at clustermatic.org
> Subject: move to bitkeeper?
> 
> 
> sourceforge is really having trouble nowadays. Half my browsers
think the
> web pages are to be downloaded for some reason; cvs updates are
seeing
> 24-hour delays; and random outages are a daily occurence.
> 
> I've noticed that lots of high-profile projects are now mastering on
> bitkeeper.com, including the linux kernel and the infiniband
project.
> 
> Any comments or objections to me at least looking into a move to
> bitkeeper.com? It has lots of advantages, not the least that it
supports
> distributed repositories.
> 
> Anyone have anything to say about this, pro or con?
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Mon Jun 30 12:45:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 30 12:45:01 2003
Subject: move to bitkeeper?
In-Reply-To: <!~!UENERkVCMDkAAQACAAAAAAAAAAAAAAAAABgAAAAAAAAAJX/cR7931hGLXAABAjrE9eKAAAAQAAAAKZD2/vWq1xGLZwABAjrE9QEAAAAA@worldnet.att.net>
Message-ID: <Pine.LNX.4.44.0306301052020.30054-100000@maxroach.lanl.gov>

On Mon, 30 Jun 2003, Gregg C Levine wrote:

> Now the other question. Ron, which browsers are telling you this? I
> can view all of the project pages without difficulty, on MSIE, and the
> version of Netscape delivered on Slackware 8.0, also with the browsers
> that came with Gnome.

opera (latest)
konqueror (3.0.5a-4)

ron



From aip at cwlinux.com  Mon Jun 30 13:10:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Mon Jun 30 13:10:00 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306301052020.30054-100000@maxroach.lanl.gov>; from ron minnich on Mon, Jun 30, 2003 at 10:52:53AM -0600
References: <!~!UENERkVCMDkAAQACAAAAAAAAAAAAAAAAABgAAAAAAAAAJX/cR7931hGLXAABAjrE9eKAAAAQAAAAKZD2/vWq1xGLZwABAjrE9QEAAAAA@worldnet.att.net> <Pine.LNX.4.44.0306301052020.30054-100000@maxroach.lanl.gov>
Message-ID: <20030701011746.A25538@mail.cwlinux.com>

Hi Gregg,

> > Now the other question. Ron, which browsers are telling you this? I
> > can view all of the project pages without difficulty, on MSIE, and the
> > version of Netscape delivered on Slackware 8.0, also with the browsers
> > that came with Gnome.
> opera (latest)
> konqueror (3.0.5a-4)
mozilla 1.3.1
I don't think the problem is from the browser but sourceforge itself.
My last checkin didn't appear 'till hours later.  It also takes many times
of retries in order to checkout code from cvs tree.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

Tel: (852)2542 2046
Fax: (852)2542 2036

For public pgp key, please obtain it from http://www.keyserver.net/en.


From bos at serpentine.com  Mon Jun 30 13:19:01 2003
From: bos at serpentine.com (Bryan O'Sullivan)
Date: Mon Jun 30 13:19:01 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
Message-ID: <1056994053.12084.3.camel@serpentine.internal.keyresearch.com>

On Mon, 2003-06-30 at 08:22, ron minnich wrote:

> Any comments or objections to me at least looking into a move to 
> bitkeeper.com? It has lots of advantages, not the least that it supports 
> distributed repositories. 

Things with Sourceforge are obviously only going to get worse, as VA is
in terrible shape financially.

Independent of that, BK is so much better at branching and merging than
any other SCM tool, it isn't even funny.  Couple that with the fact that
it's distributed, and that bkbits.net works pretty well, and I'd say
you're much better off than with CVS.

(No, I'm not a BitMover employee, but I do pay them money.)

	<b



From peter at trusteddebian.org  Mon Jun 30 13:28:00 2003
From: peter at trusteddebian.org (Peter Busser)
Date: Mon Jun 30 13:28:00 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
Message-ID: <20030630173000.GB23904@trusteddebian.org>

Hello!

> Anyone have anything to say about this, pro or con?

The most heard objection against bitkeeper is that it is not free software.

Aegis (aegis.sourceforge.net) is free software.

Groetjes,
Peter Busser
-- 
The Adamantix Project
Taking trustworthy software out of the labs, and into the real world
http://www.adamantix.org/


From ts1 at tsn.or.jp  Mon Jun 30 14:15:00 2003
From: ts1 at tsn.or.jp (SONE Takeshi)
Date: Mon Jun 30 14:15:00 2003
Subject: [PATCH] Fix to elfboot checksum problem
Message-ID: <20030630182331.GA12910@tsn.or.jp>

Hi,
I think I've at last found a bug in elfboot.c.
Until this fix, I had always needed to disable verify code in
elfboot.c to get it work.
Now it boots ELF kernel with BOOT_IDE perfectly.

One of doubly-linked chain was not initialized.
I think it did not cause problem when memory near address 0 comes
up with zeroes.
But my raminit.inc leaves gabages there so some bogus memory ranges
have been included in checksum.

-- 
Takeshi



Index: src/lib/elfboot.c
===================================================================
RCS file: /cvsroot/freebios/freebios/src/lib/elfboot.c,v
retrieving revision 1.15
diff -u -r1.15 elfboot.c
--- src/lib/elfboot.c	10 Oct 2002 22:23:43 -0000	1.15
+++ src/lib/elfboot.c	30 Jun 2003 18:11:26 -0000
@@ -368,6 +368,7 @@
 	int i;
 	memset(head, 0, sizeof(*head));
 	head->next = head->prev = head;
+	head->phdr_next = head->phdr_prev = head;
 	for(i = 0; i < headers; i++) {
 		struct segment *new;
 		/* Ignore data that I don't need to handle */


From rminnich at lanl.gov  Mon Jun 30 14:46:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 30 14:46:01 2003
Subject: move to bitkeeper?
In-Reply-To: <20030630173000.GB23904@trusteddebian.org>
Message-ID: <Pine.LNX.4.44.0306301253270.30054-100000@maxroach.lanl.gov>

On Mon, 30 Jun 2003, Peter Busser wrote:

> The most heard objection against bitkeeper is that it is not free software.

yeah, but that's actually ok by me. It's good software, and Larry's source 
policy is actually very reasonable.

Plus he has a viable business, which means that they will probably be 
there in a few years.

ron



From clark at bit63.org  Mon Jun 30 15:00:01 2003
From: clark at bit63.org (Clark Rawlins)
Date: Mon Jun 30 15:00:01 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306301253270.30054-100000@maxroach.lanl.gov>
References: <20030630173000.GB23904@trusteddebian.org> <Pine.LNX.4.44.0306301253270.30054-100000@maxroach.lanl.gov>
Message-ID: <20030630190536.GA12159@master.bit63.org>

The real problem with Larry's policy is that if you work on 
any other SCM code free or not you must buy the full version
of the tools.  That would lock out some of us who have worked
on subversion/cvs/etc who want to work on LinuxBIOS.

Before making the jump to bitkeeper a real consideration of the
alternitives should be considered.

One that hasn't come up yet is subversion and/or tigris.org.

On Mon, Jun 30, 2003 at 12:53:58PM -0600, ron minnich wrote:
> On Mon, 30 Jun 2003, Peter Busser wrote:
> 
> > The most heard objection against bitkeeper is that it is not free software.
> 
> yeah, but that's actually ok by me. It's good software, and Larry's source 
> policy is actually very reasonable.
> 
> Plus he has a viable business, which means that they will probably be 
> there in a few years.
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 
"The two enemies of the people are criminals and government, so let us tie the
second down with the chains of the constitution so the second will not become
the legalized version of the first."
     -- Thomas Jefferson
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From rminnich at lanl.gov  Mon Jun 30 15:15:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Jun 30 15:15:01 2003
Subject: move to bitkeeper?
In-Reply-To: <20030630190536.GA12159@master.bit63.org>
Message-ID: <Pine.LNX.4.44.0306301323100.32466-100000@maxroach.lanl.gov>

On Mon, 30 Jun 2003, Clark Rawlins wrote:

> The real problem with Larry's policy is that if you work on 
> any other SCM code free or not you must buy the full version
> of the tools.  That would lock out some of us who have worked
> on subversion/cvs/etc who want to work on LinuxBIOS.

that locks out the project, but not the person, right?

ron



From clark at bit63.org  Mon Jun 30 15:25:00 2003
From: clark at bit63.org (Clark Rawlins)
Date: Mon Jun 30 15:25:00 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306301323100.32466-100000@maxroach.lanl.gov>
References: <20030630190536.GA12159@master.bit63.org> <Pine.LNX.4.44.0306301323100.32466-100000@maxroach.lanl.gov>
Message-ID: <20030630193136.GA13185@master.bit63.org>

It prevents the person from using the prefered tools of the project
to contribute to the project.  So when someone wants to get the 
latest sources and there is no daily snapshot tarball the user 
either has to fork over $4K (I think it costs that much I haven't
checked recently) or violate the licence or forgo working 
on the project until either a snapshot is available.

Clark

On Mon, Jun 30, 2003 at 01:23:23PM -0600, ron minnich wrote:
> On Mon, 30 Jun 2003, Clark Rawlins wrote:
> 
> > The real problem with Larry's policy is that if you work on 
> > any other SCM code free or not you must buy the full version
> > of the tools.  That would lock out some of us who have worked
> > on subversion/cvs/etc who want to work on LinuxBIOS.
> 
> that locks out the project, but not the person, right?
> 
> ron
> 

-- 
"They that can give up essential liberty to obtain a little temporary safety
  deserve neither liberty nor safety."
  - Benjamin Franklin, Historical Review of Pennsylvania, 1759.
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From ebiederman at lnxi.com  Mon Jun 30 15:39:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Jun 30 15:39:01 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
Message-ID: <m3znjzpcp4.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> sourceforge is really having trouble nowadays. Half my browsers think the 
> web pages are to be downloaded for some reason; cvs updates are seeing 
> 24-hour delays; and random outages are a daily occurence. 

Agreed.  So something needs to be done.
 
> I've noticed that lots of high-profile projects are now mastering on 
> bitkeeper.com, including the linux kernel and the infiniband project.
> 
> Any comments or objections to me at least looking into a move to 
> bitkeeper.com? It has lots of advantages, not the least that it supports 
> distributed repositories. 
> 
> Anyone have anything to say about this, pro or con?

A significant con is that with the zero dollar license a developer
cannot work on source code control projects.  Which is a stiff
imposition.  The kernel avoids problems of this nature by with
regular releases and a patch submission process that does not
require you to use bk.  We don't have the infrastructure in place
to do that.

Subversion has the problem that it is not a distributed version
control system.  CVS isn't either but it is well understood.

With LANL potentially being behind a government firewall Ron I don't
think it makes sense for you to host a CVS sever correct?

We probably want to accumulate a list of other sites like sourceforge.
One is http://berlios.de

Eric



From ian.castle at coldcomfortfarm.net  Mon Jun 30 16:21:01 2003
From: ian.castle at coldcomfortfarm.net (Ian Castle)
Date: Mon Jun 30 16:21:01 2003
Subject: move to bitkeeper?
In-Reply-To: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0306300920140.30054-100000@maxroach.lanl.gov>
Message-ID: <1057004933.1205.17.camel@kerberos.sunnyroyd.coldcomfortfarm.org>

You seem to be conflating two separate issues:

1) Source Forge is failing
2) CVS needs to be replaced 

1. This may or may not be true - it seems to be working OK at the moment
for me (I commit to other projects than Linuxbios - which are probably
less active). But I would agree that SF is probably something that VA
can't afford to continue to run...

Alternatives: Use another hosting site (savannah? find a sponsor - IBM?,
OSDL? lnxi?, SiS? LANL pay for an offsite server away from the
firewall?)

2. BitKeeper seems to have advantages for _vast_ fluid projects like the
Linux kernel - where it is important to deal with a "patch" (something
that affects a lot of different sources) as a single unit - Most kernels
are made up of different patches choosen to meet the particular needs of
the hardware etc). The linux kernel also has a lot of people submitting
patches.

I'm not convinced that LinuxBIOS has outgrown the capabilities of CVS -
but I'm not necessarily best placed to judge that - not being a
committer.

The big attraction of Open Source/Free Software is, for me, having the
ability to fix things myself if I want to. I use many different projects
and have submitted changes to a variety of different projects over the
years. Many of which I could not have predicted submitting patches to. I
am deeply suspicious of a licence that forbids me from using my own
resources to supply fixes to other quite separate projects. It is
galling that the "first party" attempts to control relationships between
the "second" and "third" parties.

Anyway, you seem to be saying that there is a problem with sourceforge
so LinuxBios should not use CVS. I'm not sure about this argument.

If CVS is deemed unsatisfactory, I'm not sure that BitKeeper is the most
appropriate solution to the problem.


On Mon, 2003-06-30 at 16:22, ron minnich wrote:
> sourceforge is really having trouble nowadays. Half my browsers think the 
> web pages are to be downloaded for some reason; cvs updates are seeing 
> 24-hour delays; and random outages are a daily occurence. 
> 
> I've noticed that lots of high-profile projects are now mastering on 
> bitkeeper.com, including the linux kernel and the infiniband project.
> 
> Any comments or objections to me at least looking into a move to 
> bitkeeper.com? It has lots of advantages, not the least that it supports 
> distributed repositories. 
> 
> Anyone have anything to say about this, pro or con?
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
-- 
Ian Castle <ian.castle at coldcomfortfarm.net>



From RSmith at bitworks.com  Tue Jun 24 19:27:01 2003
From: RSmith at bitworks.com (Richard Smith)
Date: Tue Jun 24 19:27:01 2003
Subject: 440bx patches
In-Reply-To: <200362422358.291232@techfreakz>
References: <200362422358.291232@techfreakz>
Message-ID: <3EF8DF79.4030808@bitworks.com>

This is a multi-part message in MIME format.
--------------080608060305040407040705
Content-Type: text/plain; charset=us-ascii; format=flowed
Content-Transfer-Encoding: 7bit

Here's my patches for syncing up with my tree

This is a 'diff -u -N -r --exclude=CVS --exclude=ADLO' of my tree synced 
to cvs vs the current cvs tree.  'cvs diff -u -N' keep hanging on me.

I excluded my ADLO dual head video init since it's specific to our board 
and hardcoded.

Includes:

- Config file for the bitworks IMS board. (Not really usefull to anyone 
execept for example.

- Rework of raminit.inc for the 440bx.  Current CVS is broken and will 
not work in the general case.   New code works for every different DIMM 
I had here at Bitworks.

- Support for the NSC PC87351 superIO

- Addition of 'mouse' into new superIO struct

- Various mods to piix4e to enable/disable some features and some fixes

- A sprinkleing of printk_debugs that helped me figure out what code was 
being called where.

Most everything I did I tried to wrap with some sort of Config option 
except in bug fix or incorrect settings cases.

Some of the stuff in the PC87351 superIO is kinda specific to our 
motherboard and not truly generic but I imagine that anyone else using 
this superIO would have it setup the same way.  In the timeframe between 
1.x and 2.x I doubt there will be any need for additional config options.


-- 
Richard A. Smith
rsmith at bitworks.com

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