答复: coherent hypertransport enumeration on opteron

[Yinghai Lu]

Please refer the program cut.

static void setup_coherent_ht_domain(void)
{
	static const unsigned int register_values[] = {
	PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00050101,
	PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010404,
	PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010404,


	PCI_ADDR(0, 0x1f, 0, 0x6C), 0xfffffffd, 0x00000002, 

     PCI_ADDR(0, 0x1f, 0, 0x40), 0xfff0f0f0, 0x00010404,
     PCI_ADDR(0, 0x1f, 0, 0x44), 0xfff0f0f0, 0x00050101,

	PCI_ADDR(0, 0x1f, 0, 0x60), 0xfffffff8, 0x00000001, // Can not
change NodeID to 1 here

	PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,

     PCI_ADDR(0, 0x18, 0, 0x60), 0xfff8ff8f, 0x00010010,
     PCI_ADDR(0, 0x19, 0, 0x60), 0xfff8ff8f, 0x00010010,

     PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00c800,
     PCI_ADDR(0, 0x19, 0, 0x68), 0x00800000, 0x0f00c800,
 
	PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000070, //1C
	PCI_ADDR(0, 0x19, 0, 0x6C), 0xffffff8c, 0x00000070,//14
	PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020,
	PCI_ADDR(0, 0x19, 0, 0x84), 0x00009c05, 0x771100d0,

	PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000500,
	PCI_ADDR(0, 0x19, 0, 0x88), 0xfffff0ff, 0x00000500,

	PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000,
	PCI_ADDR(0, 0x19, 0, 0x94), 0xff000000, 0x00000000,
	};
	int i;
	int max;
	int j;
	print_debug("setting up coherent ht domain....\r\n");
	max = sizeof(register_values)/sizeof(register_values[0]);
	for(i = 0; i < max; i += 3) {
		device_t dev;
		unsigned where;
		unsigned long reg;
#if 1
		print_debug_hex32(i);
		print_debug(": ");
		print_debug_hex32(register_values[i]);
		print_debug(" <-");
		print_debug_hex32(register_values[i+2]);
		print_debug("\r\n");
#endif
		dev = register_values[i] & ~0xff;
		where = register_values[i] & 0xff;
		reg = pci_read_config32(dev, where);
		reg &= register_values[i+1];
		reg |= register_values[i+2];
		pci_write_config32(dev, where, reg);
		if(i==3*3) {
			for(j=0;j<300000;j++) {	  // make sure request
diable bit is set
				reg = pci_read_config32(dev,where);
				reg &= ~(register_values[i+1]);
		 		if(reg==register_values[i+2]) {  
//					print_debug("request disable bit
set \r\n");
					break;
				}
			}

		}
		if(i==2*3) {
			reg = pci_read_config32(PCI_ADDR(0, 0x1f, 0,
0)&~0xff,PCI_ADDR(0, 0x1f, 0, 0) & 0xff); // read Vender ID
//			print_debug("1f DeviceID readed ");
//			print_debug_hex32(reg);
//			print_debug("\r\n");
		}
 
	}
	print_debug("done.\r\n");
}


-----邮件原件-----
发件人: linuxbios-admin at clustermatic.org
[mailto:linuxbios-admin at clustermatic.org] 代表 Stefan Reinauer
发送时间: 2003年6月21日 7:18
收件人: YhLu
抄送: ebiederman at lnxi.com; ron minnich; linuxbios at clustermatic.org
主题: coherent hypertransport enumeration on opteron

* YhLu <YhLu at tyan.com> [030621 09:27]:
> I have added some hardcode to northbridge/amd/amdk8/coherent_ht.c.
> 
> Till now, I can not change NodeID from 7 to 1 for the second Node.
> 
> Do I need to send the coherent_ht.c to Stefan to check or after I
finished
> the debug?

as far as i can tell you need to set up a link to node 7 before you can
rename it to node 1. I'm going to release my code somewhen next week as
soon as I figured out all the details of mp capability detection.
Feel free to send your code to me or the list for discussion.

  Stefan

-- 
Architecture Team
    SuSE Linux AG
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