From ts1 at tsn.or.jp  Sun Nov  2 10:47:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Sun Nov  2 10:47:01 2003
Subject: filo on Tyan s2880
In-Reply-To: <20031031210308.GB28576@suse.de>
References: <20031030103428.GC15606@suse.de> <20031030104057.GA17698@tsn.or.jp> <20031030114002.GB17018@suse.de> <20031030122508.GA20783@tsn.or.jp> <20031030123249.GC18558@suse.de> <20031030173610.GA32387@tsn.or.jp> <20031031210308.GB28576@suse.de>
Message-ID: <20031102161754.GA317@tsn.or.jp>

On Fri, Oct 31, 2003 at 10:03:09PM +0100, Stefan Reinauer wrote:
> Hm.. just had the idea.. maybe it makes sense to use no-pci mode if no
> pci controller can be found? 

That sounds like a symptomatic treatment.
Maybe I can do this but with a big fat warning would be displayed.
We have to fix the PCI, not the symptom (IDE).
-- 
Takeshi


From linuxbios at xdr.com  Sun Nov  2 11:12:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Sun Nov  2 11:12:01 2003
Subject: RomCC
Message-ID: <200311021643.hA2GhlG3011272@xdr.com>

These discussions on romcc running out of registers, optimizations, inline
and all are surprising. Isn't the point of romcc to just get the system ram
up right at the beginning? Then once that is done any compiler (gcc) can be
used to write code. Because dram configuration is so complicated and
interpreting the SPD data from the dram, people would rather code that in 'C'
than in x86 asm, so that's the purpose of romcc?

-Dave


From ebiederman at lnxi.com  Sun Nov  2 14:25:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sun Nov  2 14:25:01 2003
Subject: RomCC
In-Reply-To: <200311021643.hA2GhlG3011272@xdr.com>
References: <200311021643.hA2GhlG3011272@xdr.com>
Message-ID: <m3he1mwnmg.fsf@maxwell.lnxi.com>

Dave Ashley <linuxbios at xdr.com> writes:

> These discussions on romcc running out of registers, optimizations, inline
> and all are surprising. Isn't the point of romcc to just get the system ram
> up right at the beginning? 

Yes.  

> Then once that is done any compiler (gcc) can be
> used to write code. Because dram configuration is so complicated and
> interpreting the SPD data from the dram, people would rather code that in 'C'
> than in x86 asm, so that's the purpose of romcc?

Yes.

The most common problem is for people to write a piece of code
that romcc cannot figure out how to make fit in only
a limited set of registers.  That is fairly rare at
the moment but it does happen.

To reduce register pressure romcc inlines all functions.  So there
is no need to store a return address anywhere.

Inlining everything leads to a case where code generated by
romcc is 3x larger than hand coded assembly for a similar problem.
Last I checked when using both sse and mmx registers on the Opteron
port I had about 8 free registers most of the time.  And my average
call depth is less than 8. So it looks reasonable to actually store
a return address and cut down on register pressure.

The reason register allocation is hard is that it is an NP complete
problem, which would take exponential time in the size of the program
if I was to implement a perfect algorithm.  Given that a O(N^2)
algorithm takes a full minute using the perfect algorithm is
unreasonable given that my current heuristic works almost every time.
Taking any longer would mess up a programmers productivity.  There is
one known corner case where the current heuristic fails that I would
like very much to improve. 

But these are the only problems.  And once I have finished exploring
them romcc will be pretty much done.  I would not work quite as
much on them except I find solving the problems quite fun :)

Eric


From stepan at suse.de  Mon Nov  3 06:15:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Nov  3 06:15:01 2003
Subject: RomCC
In-Reply-To: <200311021643.hA2GhlG3011272@xdr.com>
References: <200311021643.hA2GhlG3011272@xdr.com>
Message-ID: <20031103114621.GD5449@suse.de>

* Dave Ashley <linuxbios at xdr.com> [031102 17:43]:
> These discussions on romcc running out of registers, optimizations, inline
> and all are surprising. Isn't the point of romcc to just get the system ram
> up right at the beginning? Then once that is done any compiler (gcc) can be
> used to write code. Because dram configuration is so complicated and
> interpreting the SPD data from the dram, people would rather code that in 'C'
> than in x86 asm, so that's the purpose of romcc?

Yes. The problem that makes romcc run out of registers in my case can be
circumvented by some small restructures in the code. 

Given that not all spd roms of all modules are visible at the same time,
but switched via an smbus hub, I have to make sure that before trying to
access spd rom data with smbus_read_byte() the smbus hub is switched to
the correct rom. 

The current approach is to do this in spd_read_byte, which is used as a
wrapper function around smbus_read_byte. It always sends a "switch"
command to the smbus hub before actually reading from the rom. Since the
function for switching parses the information from the ram controller
struct and does an smbus_write_byte, it eats quite some registers all
the time, in addition to the already used ones.

Since the dram controllers are initialized one after the other, we don't
need to switch the smbus hub every time we do an access, but only before
starting dram initialization on a given controller. This lowers register
usage noticably and especially only uses registers at a point when we
have plenty of them.

Therefore I suggest adding a function 
activate_spd_rom(const struct mem_controller *ctrl) that is called as
the first command in sdram_set_spd_registers() that can be implemented
by the motherboard specific code if needed, similar to memreset() now.

As far as I can see, all spd accesses done by sdram_set_spd_registers()
end up on the same spd rom, making it safe to switch only one time per
call to this function.

I'll change the code to reflect this and see if it works out.
 
Stefan

 
-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From xpegenaute at telepolis.es  Mon Nov  3 17:28:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Mon Nov  3 17:28:01 2003
Subject: rom for epia m-10000
Message-ID: <1067900389.5780.7.camel@p-133>

Hi,

finally! I obtained  the flash memories for epia m 10000, now i'm trying
to put LinuxBios, but in all the tests that i made no one printed
somethig throught serial line.

I have no idea about the problem. I know that serial line work because
if i put "console=tty0 console=ttyS0,115200" in lilo with the normal
bios i can see the msgs of kernel.

Any one have some binry image for an epia m-10000 ? or some other idea?

Thanks.
Xavi.
PD: I bought them in www.progshop.com




From rminnich at lanl.gov  Mon Nov  3 17:36:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov  3 17:36:01 2003
Subject: arima/hdama fails from current cvs
Message-ID: <Pine.LNX.4.44.0311031606030.22111-100000@maxroach.lanl.gov>

I am finally getting time to do K8s again.

I just did a cvs update, built linuxbios for the arima/hdama, and tested 
it out. It failed. 

Looks like the ethernet is now back on bus 2, and linux does not see the 
ethernets at all. 

Anyone else tried this lately? The K8 platforms seem, overall, to be not 
quite working at present.

ron



From rminnich at lanl.gov  Mon Nov  3 17:40:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov  3 17:40:01 2003
Subject: rom for epia m-10000
In-Reply-To: <1067900389.5780.7.camel@p-133>
Message-ID: <Pine.LNX.4.44.0311031611070.22111-100000@maxroach.lanl.gov>

which version of linuxbios are you using?

ron



From xpegenaute at telepolis.es  Mon Nov  3 17:45:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Mon Nov  3 17:45:01 2003
Subject: rom for epia m-10000
In-Reply-To: <Pine.LNX.4.44.0311031611070.22111-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311031611070.22111-100000@maxroach.lanl.gov>
Message-ID: <1067901413.5782.9.camel@p-133>

I tried with freebios2 of today in CVS and now i'm trying with freebios
also from today.

Xavi.
On Tue, 2003-11-04 at 00:11, ron minnich wrote:
> which version of linuxbios are you using?
> 
> ron
> 



From rminnich at lanl.gov  Mon Nov  3 17:49:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov  3 17:49:00 2003
Subject: rom for epia m-10000
In-Reply-To: <1067901413.5782.9.camel@p-133>
Message-ID: <Pine.LNX.4.44.0311031619550.22111-100000@maxroach.lanl.gov>

On 4 Nov 2003, Xavier Pegenaute wrote:

> I tried with freebios2 of today in CVS and now i'm trying with freebios
> also from today.

I don't know, so, what's the chispet on m10000

ron



From xpegenaute at telepolis.es  Mon Nov  3 17:59:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Mon Nov  3 17:59:00 2003
Subject: rom for epia m-10000
In-Reply-To: <Pine.LNX.4.44.0311031619550.22111-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311031619550.22111-100000@maxroach.lanl.gov>
Message-ID: <1067902251.5777.13.camel@p-133>

Hi,

here i send you the lspci.

Xavi.

On Tue, 2003-11-04 at 00:20, ron minnich wrote:
> On 4 Nov 2003, Xavier Pegenaute wrote:
> 
> > I tried with freebios2 of today in CVS and now i'm trying with freebios
> > also from today.
> 
> I don't know, so, what's the chispet on m10000
> 
> ron
> 
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From stepan at suse.de  Mon Nov  3 19:08:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Nov  3 19:08:01 2003
Subject: arima/hdama fails from current cvs
In-Reply-To: <Pine.LNX.4.44.0311031606030.22111-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311031606030.22111-100000@maxroach.lanl.gov>
Message-ID: <20031104003930.GA8817@suse.de>

* ron minnich <rminnich at lanl.gov> [031104 00:07]:
> I just did a cvs update, built linuxbios for the arima/hdama, and tested 
> it out. It failed. 
 
Any problems besides the bus problem on hdama? It seems that LinuxBIOS
goes some way of emerge and pucker on K8 lately. 

> Looks like the ethernet is now back on bus 2, and linux does not see the 
> ethernets at all. 

Maybe an additional entry in irq_tables.c helps?
 /* Let Linux know about bus 1 */
 {0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xde
f8}, {0x00, 0xdef8}}, 0x00, 0},

seems to do it's job for bus1. bus2 has entries for device 3 and 4. Are
these correct for the current tree? 
All these infrastructural changes seem to cry for automatic irq-table
generation..

Another thing, when talking about tables: Is there anything serious 
speaking against including a minimal set of ACPI tables to get things
like HPET timers working? Or is there another viable way for enabling
these?

   Stefan
 
-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From gwatson at lanl.gov  Mon Nov  3 20:53:00 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Mon Nov  3 20:53:00 2003
Subject: device configuration
Message-ID: <p06010201bbccb6c1d8db@[10.0.1.2]>

Hi,

Can someone please provide some assistance on the new device 
configuration setup? For example, how do I configure the IDE 
controller on a Winbond chip? I used to do this through the enable 
routine in the chip_control structure but this is no longer used. 
I've tried using the enable_dev routine, but it never seems to get 
called. Do I need to do something with the 'pci' configuration 
statement? What is the purpose of these? I've tried defining 'pci 
0:9.0 on' and 'pci 0:9.1 on' but it doesn't make any difference.

Thanks,

Greg


From eddyfu at pchome.com.tw  Mon Nov  3 22:45:01 2003
From: eddyfu at pchome.com.tw (eddyfu at pchome.com.tw)
Date: Mon Nov  3 22:45:01 2003
Subject: EPIA-M10000 can't work properly with VGA from HD
Message-ID: <20031104041655.D88CD657221@msx.pchome.com.tw>

Hi ,

Have any one can help me?

I used EPIA-M10000 + LinuxBIOS+ Filo 0.4.1 + mkelfImage 1.6 on Red Hat 8.0.
I needed VGABIOS to use.
But it can't work properly.
Serial port msgs show some unknow codes.

The POST number is 96.

epia config file:

#
# LinuxBIOS config file for: VIA epia-m mini-itx
#

target /epia-m

# via epia
mainboard via/epia-m

# Enable Serial Console for debugging
option SERIAL_CONSOLE=1
#option SERIAL_POST=1
#option TTYS0_BAUD=115200
option TTYS0_BAUD=57600
option DEFAULT_CONSOLE_LOGLEVEL=9
option DEBUG=1

# Use 256KB Standard Flash as Normal BIOS 
option RAMTEST=1
option USE_GENERIC_ROM=1
option STD_FLASH=1
option VGABIOS_START=0xfffc0000
option ZKERNEL_START=0xfffd0000
option ROM_SIZE=262144

# FrameBuffer
option HAVE_FRAMEBUFFER=1
option SMA_SIZE=16
option CONFIG_VGABIOS=1
option CONFIG_REALMODE_IDT=1
option CONFIG_PCIBIOS=1
option CONFIG_PCIPIOS_IRQ=1
dir src/bioscall

# payload size = 192KB
option PAYLOAD_SIZE=196608

# use ELF Loader to load Etherboot
option USE_ELF_BOOT=1

# Use Filo as our payload 
payload /vga+filo.bin

filo config:

# !!! NOTE !!!
# Do NOT add spaces or comments at the end of option lines.
# It confuses some versions of make.

# Image filename for automatic boot and optional command line parameter
AUTOBOOT_FILE = "hda2:/vmlinuz.epia root=/dev/hda2 console=tty0 console=ttyS0,57600"

# Time in second before booting AUTOBOOT_FILE
AUTOBOOT_DELAY = 2

# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus
IDE_DISK = 1

# VGA text console
VGA_CONSOLE = 1
PC_KEYBOARD = 1

# Serial console
SERIAL_CONSOLE = 1
SERIAL_IOBASE = 0x3f8
SERIAL_SPEED = 57600

# Filesystems
FSYS_EXT2FS = 1
FSYS_FAT = 1
FSYS_JFS = 1
FSYS_MINIX = 1
FSYS_REISERFS = 1
FSYS_XFS = 1
FSYS_ISO9660 = 1

# Support for boot disk image in bootable CD-ROM (El Torito)
ELTORITO = 1

# PCI support
SUPPORT_PCI = 1

# Sound support (needs SUPPORT_PCI)
SUPPORT_SOUND = 1

# Sound drivers
VIA_SOUND = 1

# Debugging
DEBUG_ALL = 1
DEBUG_ELFBOOT = 1
DEBUG_ELFNOTE = 1
DEBUG_LINUXBIOS = 1
#DEBUG_MALLOC = 1
DEBUG_MULTIBOOT = 1
#DEBUG_SEGMENT = 1
#DEBUG_SYS_INFO = 1
#DEBUG_TIMER = 1
#DEBUG_BLOCKDEV = 1
DEBUG_PCI = 1
#DEBUG_VIA_SOUND = 1
DEBUG_LINUXLOAD = 1
DEBUG_IDE = 1
#DEBUG_ELTORITO = 1

# i386 options

# Loader for standard Linux kernel image, a.k.a. /vmlinuz
LINUX_LOADER = 1

# Boot FILO from Multiboot loader (eg. GRUB)
MULTIBOOT_IMAGE = 1

# Use PCI Configuration Mechanism #1 (most boards)
PCI_CONFIG_1 = 1

************************************************************
 
Any suggestion, please tell me.
 
Best regards,
Eddy
==========================================================
 ?????????? eBay ???
 http://edm-prg.epaper.com.tw/click.php?ad_code=31602
==========================================================
 PChome??~~????? \*^o^*//
 http://love.pchome.com.tw/
==========================================================


From rminnich at lanl.gov  Mon Nov  3 23:00:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov  3 23:00:00 2003
Subject: EPIA-M10000 can't work properly with VGA from HD [PMX:##]
In-Reply-To: <20031104041655.D88CD657221@msx.pchome.com.tw>
Message-ID: <Pine.LNX.4.44.0311032131170.26533-100000@maxroach.lanl.gov>

can you send serial port output?

ron



From joshua at joshuawise.com  Mon Nov  3 23:29:00 2003
From: joshua at joshuawise.com (Joshua Wise)
Date: Mon Nov  3 23:29:00 2003
Subject: LAB (LinuxBIOS-like thing for embedded ARM-based devices)
Message-ID: <200311040000.26263.joshua@joshuawise.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hey all,

Some of you may remember me as the LAB guy (Linux As Bootldr). Just wanted to 
let you all know that LAB is booting on the iPAQ h3900. It's currently 
512kbytes, and I don't expect it to go over that, although I'm aiming for 
256kbytes. Code is in handhelds.org CVS. Does anyone have any suggestions for 
fitting a kernel 2.6 in sub-256k?

/joshua

(Also, I've got me an ABIT KG7-RAID here. I've been sick and tired of the crap 
BIOS that comes with it. What information do I need to collect so I can start 
working on this board, and what hardware do you all think I should use? Does 
a DOC work through a bios savior?)

- -- 
Joshua Wise | www.joshuawise.com
GPG Key     | 0xEA80E0B3
Quote       | <lilo> I akilled *@* by mistake
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.2 (GNU/Linux)

iD8DBQE/pzJpPn9tWOqA4LMRAoD1AJ44XfwpaPgOdsko+EsD7+53A2dVMwCgtO2A
VlBPvGui1Hm5+Xu5SE4AjkI=
=GquT
-----END PGP SIGNATURE-----



From eddyfu at pchome.com.tw  Tue Nov  4 01:19:00 2003
From: eddyfu at pchome.com.tw (eddyfu at pchome.com.tw)
Date: Tue Nov  4 01:19:00 2003
Subject: EPIA-M10000 can't work properly with VGA from HD [PMX:##]
Message-ID: <20031104065028.F0041657056@msx.pchome.com.tw>


?? ??????? ??
From: ron minnich <rminnich at lanl.gov>
To: eddyfu at pchome.com.tw
Cc: linuxbios at clustermatic.org
Subject: Re: EPIA-M10000 can't work properly with VGA from HD [PMX:##]


can you send serial port output?

ron

Hi Ron
 
Sorry!!
They are some large mess codes.
 
Best regards,
Eddy
==========================================================
 ?????????? eBay ???
 http://edm-prg.epaper.com.tw/click.php?ad_code=31602
==========================================================
 PChome??~~????? \*^o^*//
 http://love.pchome.com.tw/
==========================================================


From mirenna at mi.ingv.it  Tue Nov  4 01:42:00 2003
From: mirenna at mi.ingv.it (mirenna at mi.ingv.it)
Date: Tue Nov  4 01:42:00 2003
Subject: EPIA-M10000 can't work properly with VGA from HD  
Message-ID: <200311040713.hA47DRQ8004009@ambroeus.mi.ingv.it>

Hi,
i had problem to compile linuxbios for EPIA-M 10000.
Can you tell me please which version of linuxbios are you using,
and the way you obtain VGA+filo image.
Can you sen me tree to compile, or the bios image you obtail.
Thanks.

Santi
Mirenna






From eddyfu at pchome.com.tw  Tue Nov  4 02:54:01 2003
From: eddyfu at pchome.com.tw (eddyfu at pchome.com.tw)
Date: Tue Nov  4 02:54:01 2003
Subject: EPIA-M10000 can't work properly with VGA from HD [PMX:##] 
Message-ID: <20031104082513.496C86572A4@msx.pchome.com.tw>

>Hi,
>i had problem to compile linuxbios for EPIA-M 10000.
>Can you tell me please which version of linuxbios are you using,
>and the way you obtain VGA+filo image.
>Can you sen me tree to compile, or the bios image you obtail.
>Thanks.

>Santi
>Mirenna

The LinuxBIOS is CVS version.

The following steps are getting VGA image(vga+filo.bin).
#setpci -s 0:11.0 40.b=54  (accessing bios rom on EPIA-M)
#dd if=/proc/kcore of=vgabios.bin bs=1 count=65536 skip=790528
#cp vgabios.bin vga+filo.bin
#dd if=/filo.elf of=/vga+filo.bin bs=1 seek=65536

My romimage file used partition /dev/hda2 and kernel image named /vmlinuz.epia 


Regards,
Eddy

==========================================================
 ?????????? eBay ???
 http://edm-prg.epaper.com.tw/click.php?ad_code=31602
==========================================================
 PChome??~~????? \*^o^*//
 http://love.pchome.com.tw/
==========================================================
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From aip at cwlinux.com  Tue Nov  4 03:46:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Nov  4 03:46:01 2003
Subject: EPIA-M10000 can't work properly with VGA from HD [PMX:##]
In-Reply-To: <20031104082513.496C86572A4@msx.pchome.com.tw>; from eddyfu@pchome.com.tw on Tue, Nov 04, 2003 at 04:25:08PM +0000
References: <20031104082513.496C86572A4@msx.pchome.com.tw>
Message-ID: <20031104171711.A3599@mail.cwlinux.com>

Hi,

The default baudrate is 57600 not 115200.  Although serial port is set to
115200 by LinuxBIOS, EPIA-M still users 57600.  I guess LinuBIOS misses 
some secret registers which we don't know.

-Andrew

On Tue, Nov 04, 2003 at 04:25:08PM +0000, eddyfu at pchome.com.tw wrote:
> >Hi,
> >i had problem to compile linuxbios for EPIA-M 10000.
> >Can you tell me please which version of linuxbios are you using,
> >and the way you obtain VGA+filo image.
> >Can you sen me tree to compile, or the bios image you obtail.
> >Thanks.
> 
> >Santi
> >Mirenna
> 
> The LinuxBIOS is CVS version.
> 
> The following steps are getting VGA image(vga+filo.bin).
> #setpci -s 0:11.0 40.b=54  (accessing bios rom on EPIA-M)
> #dd if=/proc/kcore of=vgabios.bin bs=1 count=65536 skip=790528
> #cp vgabios.bin vga+filo.bin
> #dd if=/filo.elf of=/vga+filo.bin bs=1 seek=65536
> 
> My romimage file used partition /dev/hda2 and kernel image named /vmlinuz.epia 
> 
> 
> Regards,
> Eddy
> 
> ==========================================================
>  ?S?????????????H???W eBay ???K?y
>  http://edm-prg.epaper.com.tw/click.php?ad_code=31602
> ==========================================================
>  PChome????~~?????????? \*^o^*//
>  http://love.pchome.com.tw/
> ==========================================================
> U??\?
???`D??IBM COMPATIBLEBCPOST10/25/02??
PCIR"1@Q
?
   VIA Tec.Inc.            VER.VT3123    
VIA              ?
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89:;<=>?

 $(-28?

(-2 $8?/?'/7?-16:?




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???}IIN_i????!?! "D"?!O"77v77?7%s version %s
> Unsupported image format
> boot: %s
> boot: %dtimed out
>  %#016Lx %#016Lx %d
> convert_memmap%s: Found canidate at: %p
> header checksum o.k.
> table checksum o.k.
> record count o.k.
> find_lb_tableFound LinuxBIOS table at: %p
> LinuxBIOScollect_linuxbios_infoOut of heap space
> Attempt to free NULL
> malloc_diagsuccessive free blocks: %p
> malloc_checkinvalid size: %#lx at %p
> calloc overflow: %u, %u
> strtoull_with_suffix%s must be called with endp
> <NULL>%02x%c%04x: %s occupies [%#lx-%#lx]
> ELFBootImage checksum: %#04x
> process_image_notesCan't read note segment
> load_segmentsloading... clearing... clearing checksum... ok
> add_boot_noteBoot notes too big
> Can't read ELF header
> elf_loadNot a bootable ELF image
> Can't read program header
> Loading %scurrent time: %lu
> entry point is %#x
> Jumping to entry point...
>  version %sBootloader: %s
> collect_elfboot_infoVersion: %s
> Image name: %s
> Broken ELF boot notes
> Scanning PCI: found %d devices
> pci_initNo sound device found
> hda2:/vmlinuz.epia root=/dev/hda2 console=tty0 console=ttyS0,57600Press <Enter> for default boot, or <Esc> for boot prompt... Searching for LinuxBIOS tables...
> Attempt to free non-allocated memory: %p
> alloc: %lu bytes (%u blocks), free: %lu bytes (%u blocks)
> count_alloc incorrect: %u vs %u
> total_alloc incorrect: %lu vs %lu
> count_free incorrect: %u vs %u
> total_free incorrect: %lu vs %lu
> sizes mismatch: %#lx vs %#lx at %p
> invalid head->prev_size: %#lx
> 0123456789abcdefghijklmnopqrstuvwxyz0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZSegment %d [%#lx-%#lx] doesn't fit into memory
> Loaded %lu bytes in %ums (%luKB/s)
> segment %d addr:%#x file:%#x mem:%#x Can't read program segment %d
> Verify FAILED (image:%#04x vs computed:%#04x)
> expanding boot note size to %u
> Image returned with return value %#x
> %02x:%02x.%x %04x:%04x %04x %02x
> device read failed
> open_pc_partitionPartition %d does not exist
> Extended partition not found
> Extended partition at %d
> cur_part=%d at %lu
> no link
> Partition %d is empty
> no magic
> hdCan't parse device name
> offset=%#Lx length=%#Lx
> parse_device_nameInvalid drive
> memUnknown device type
> already open
> devopenUnknown device type %d
> Device offset is too high
> after length: length %lu
> can't open partition %d
> failed to open ide
> read_sector: device not open
> read sector failed
> devreadfatext2fsminixreiserfsjfsxfsiso9660can't have a named file
> nullfs_dirnullfsUnknown filesystem type
> Mounted %s
> dev=%s, path=%s
> File not found
> No filename is given
> file_openNo El-Torito signature
> open_eltorito_imageCD001EL TORITO SPECIFICATIONid='%.*s'
> offset=%#lx length=%#lx
> ReIsErLBReIsEr2FsReIsErFspc partition magic number not found
> Logical partition %d not exist
> failed to parse device name: %s
> after offset: start %lu, length %lu
> Specified length exceeds the size of device
> Partition %d start %lu length %lu
> Unrecognized partitioning scheme
> WARNING: length is rounded up to multiple of 512
> Device offset must be multiple of 512
> Disk read error dev=%d drive=%d sector=%lu
> Attempt to read out of device/partition
> sector=%lu part_length=%lu byte_len=%lu
> El-Torito entries other than Initial/Default is not supported
> El-Torito boot catalog at sector %u
> Invalid El Torito boot catalog
> WARNING: Default boot entry is not bootable
> Disc doesn't use boot disk emulation
> Disc uses hard disk emulation - not supported
> WARNING: Boot disk for different platform: %d
> El Torito boot catalog verify failed
> IDE time out
> IDE: status=%#x, err=%#x
> print_statuside_software_resetno drq after PACKET
> pio_packetdrq after non-data command
> no drq after sending packet
> drq after insw
> Testing for hd%c
> Probing for hd%c
> LBA mode, sectors=%Ld
> LBA48 mode, sectors=%Ld
> Init device params... CHSLBALBA48ATAPI???hd%c: %s %uGB %uMB %uKBinit_drivefailed (ok for newer drives)
> Cannot power up CFA device
> Detected floating bus
> %02x atapi_request_senseatapi_detect_mediumblock_len=%u
> Unsupported sector size %u
> sectors=%u
> %uMB medium detected
> read capacity failed
> secodaryprimary%s channel: native PCI mode
> cmd_base=%#x ctrl_base=%#x
> find_ide_controllercompatibility mode
> PCI IDE #%d not found
> Media detection failed
> Drive %d does not exist
> IDE channel %d not found
> Unsupported drive number
> read error
> ide_read_sector_packetnot our reg
> DAC rate set to %dHz
> viasnd_initWaiting for ide%d to become ready for reset... CHS mode, sectors_per_track=[%d], heads=[%d], cylinders=[%d]
> Invalid IDE Configuration: %hx
> Waiting for drive to detect the medium... Device reports MEDIUM NOT PRESENT
> not implemented for non-ATAPI device
> found PCI IDE controller %04x:%04x prog_if=%#x
> No drive detected on IDE channel %d
> Found VIA sound device at %#x
> Current location: %#lx-%#lx
> Relocating to %#lx-%#lx... relocateMoving GDT to %#lx...reloading GDT...reloading CS for fun...move_gdtCPU %Ld MHz
> setup_timersboot eax = %#lx
> boot ebx = %#lx
> boot arg = %#lx
> %016Lx-%016Lx
> RAM %Ld MB
> collect_sys_infoCan't read Linux header
> load_linux_headerNot a Linux kernel image
> HdrSPossible very old Linux (protocol %#x) (loadflags %#x) bzImage zImage or ImageFound LinuxSetting up paramters at %#lx
> init_linux_params%016Lx - %016Lx
> ramtop=%#x
> ext_mem_k=%d, alt_mem_k=%d
> set_memory_sizeoriginal command line: "%s"
> kernel command line at %#lx
> parse_command_lineinitrd=%s
> mem=%Lu
> Invalid mem option, ignored
> offset=%#x addr=%#x size=%#x
> Loading kernel... Can't read kernel
> load_linux_kernelstart=%#x end=%#x
> Loading initrd... Can't read initrd
> load_initrdCan't open initrd: %s
> eip=%#x
> Returned with eax=%#x
> start_linux%08x%08x %08x%08x (%d)
> Multiboot mmap is broken
> collect_multiboot_infoCan't find address to relocate
> Can't get memory map from firmware. Using hardcoded default.
> This looks like a bootdisk image but not like Linux...
> kernel command line (%d bytes): "%s"
> Missing filename to initrd parameter
> Kernel command line is too long; truncated to %d bytes
> Missing value for mem parameter
> Garbage after mem=<size>, ignored
> Attempt to load up to end of device as kernel; specify the image size
> Attempt to load up to end of device as initrd; specify the image size
> Initrd is too big to fit in memory
> Using Multiboot information at %#lx
> Can't get memory information from Multiboot
> ???44P???????????BD??7b:.;??Q
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???[??



-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
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For public pgp key, please obtain it from http://www.keyserver.net/en.


From mirenna at mi.ingv.it  Tue Nov  4 05:39:01 2003
From: mirenna at mi.ingv.it (mirenna at mi.ingv.it)
Date: Tue Nov  4 05:39:01 2003
Subject: EPIA-M10000 can't work properly with VGA from HD [PMX:##] 
Message-ID: <200311041110.hA4BAKQ8009374@ambroeus.mi.ingv.it>

Hi,
can you tell me if the ammount of RAM DDR have you and if this ammount is
hardcoded on linuxbios ... and where.
Best Regards

Santi
Mirenna






From xpegenaute at telepolis.es  Tue Nov  4 06:25:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Nov  4 06:25:00 2003
Subject: proces to flash on epia m10000
Message-ID: <1067946944.567.20.camel@p-133>

Hi, 

may be i'm wrong in the process and this is the reason for don't work.
I'll show you the exact process to do it: (first I want filo, at least i
have to see something in serial line)

#### freebios2

- cp targets/via/epia/Config.filo.lb to targets/via/epia/Config.lb
- edit targets/via/epia/Config.lb and add:

uses TTYS0_BAUD

option TTYS0_BAUD=115200

- ./buildtarget via/epia/
- make in targets/via/epia/epia (yes filo.elf is where he thought),
linuxbios.rom is generated
- util/flash_and_burn/flash_rom
../../targets/via/epia/epia/linuxbios.rom
- reboot


Is it right ?
Xavi.



From xpegenaute at telepolis.es  Tue Nov  4 08:43:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Nov  4 08:43:00 2003
Subject: LinuxBios in epia m-10000 (freebios2)
Message-ID: <1067955280.568.46.camel@p-133>

Hi,

now i know more things :-)

Yes was there some thing printed in serial line, but i was so nervious
and i did'nt see it, i'm sorry.

The line that is printed is: "Serial controller not found", if i search
for this line in the code i find it only in:

src/southbridge/via/vt8231/vt8231_early_serial.c, inside this code the
lines are:

static void enable_vt8231_serial(void) 
{
	unsigned long x;
	uint8_t c;
	device_t dev;
	outb(6, 0x80);
	dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
	
	if (dev == PCI_DEV_INVALID) {
		outb(7, 0x80);
		die("Serial controller not found\r\n");
... etc.


if i'm not wrong, the first problem is the southbridge, the code for
epia is looking for vt8231, and i have vt8235 :-)

Ok. I saw in "freebios" that there is code for vt8235, then i think that
i'm going to try first with the old version, and once that i see how
LinuxBios is in live, if i have enough (i hope, at least for curiosity)
time i'll port it to the new one if nobody made it before.

By the other hand, the northbridge in the manual is CLE266, that axactly
i don't know how is named in the standard way (vt8633 may be ?), i don't
know if i'll have the same problem (probably i think).

------------------------------------------------------------------
My lspci, is this:

00:00.0 Host bridge: VIA Technologies, Inc.: Unknown device 3123
00:01.0 PCI bridge: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP]
00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. OHCI Compliant IEEE
1394 Host Controller (rev 80)
00:10.0 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80)
00:10.1 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80)
00:10.2 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80)
00:10.3 USB Controller: VIA Technologies, Inc.: Unknown device 3104 (rev
82)
00:11.0 ISA bridge: VIA Technologies, Inc.: Unknown device 3177
00:11.1 IDE interface: VIA Technologies, Inc. Bus Master IDE (rev 06)
00:11.5 Multimedia audio controller: VIA Technologies, Inc. AC97 Audio
Controller (rev 50)
00:12.0 Ethernet controller: VIA Technologies, Inc. Ethernet Controller
(rev 74)
01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown
device 3122 (rev 03)
------------------------------------------------------------------
And lspci -n, is this one:
00:00.0 Class 0600: 1106:3123
00:01.0 Class 0604: 1106:b091
00:0d.0 Class 0c00: 1106:3044 (rev 80)
00:10.0 Class 0c03: 1106:3038 (rev 80)
00:10.1 Class 0c03: 1106:3038 (rev 80)
00:10.2 Class 0c03: 1106:3038 (rev 80)
00:10.3 Class 0c03: 1106:3104 (rev 82)
00:11.0 Class 0601: 1106:3177
00:11.1 Class 0101: 1106:0571 (rev 06)
00:11.5 Class 0401: 1106:3059 (rev 50)
00:12.0 Class 0200: 1106:3065 (rev 74)
01:00.0 Class 0300: 1106:3122 (rev 03)
------------------------------------------------------------------


Thanks a lot.
Xavi.
PD: Sorry by the long text.



From rminnich at lanl.gov  Tue Nov  4 09:04:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov  4 09:04:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <1067955280.568.46.camel@p-133>
Message-ID: <Pine.LNX.4.44.0311040734040.28164-100000@maxroach.lanl.gov>

the problem is you are building for the wrong kind of machine. I need to 
know more about this board and we can put a new tree for it in linuxbios. 

Andrew or Takeshita, is the M-10000 different in some way important from 
the standard EPIA-M? Or should we just start a port for the epia-m and 
that will work for the 10000? 

ron



From linuxbios at xdr.com  Tue Nov  4 09:35:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Tue Nov  4 09:35:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
Message-ID: <200311041507.hA4F77bm017810@xdr.com>

>is the M-10000 different in some way important from the standard EPIA-M?

My take is the 10000 is different only in that it has a bigger heat sink
that covers the southbridge chip, and there is a cpu fan, and it runs at
1 ghz. Otherwise it is identical. My lspci -n matched exactly.

Regarding epia-m, I'm not sure if the changes I posted were incorporated
into the freebios tree. These consisted of
1) VGA working fully at least for going into linux/XFree86
2) Fixed vga bug where it would get in an endless loop and not exit in the
init (actually came up with a workaround).
3) Improved the reboot procedure so it does a pci reset to reset the pci bus.
This is for a clean soft reset.

Other people don't seem to experience the epia-m problems we have. We are
using them without any cooling fans, just the 600 mhz version. With the
stock bios some percentage of boards are really touchy as regards overheating.
They can be running fine, then you power it off and power it on again, and
it will just sit there beeping forever. If I blow a fan on the motherboard
that fixes it.

I also don't understand the interest in the epia (Not M). We tried these first
and found them unsatisfactory because the composite/svideo output had awful
color banding. VIA upscaled us to the epia-m.

Our current epia-m status: as far as I know everything is working
100% except the serial port is 1/2 the baud rate it should be (57600 max
instead of 115200). We even have a watchdog timer that reboots the epia-m
in case of lockup. Oh, and we don't have the auto SPD ddr configuration.
We're running the original freebios, not freebios2.

A lot of people seem to have epia-m spd configuration on their roadmap but
no one has jumped into it. I recently tried building freebios2 now that
the linuxbios cvs server appears working again. My system was redhat 7.1
and so wouldn't build. I've upgraded to slackware 9.1 now and am ready to
try again.

What I'm hoping to find is that the SPD configuration is similiar/identical
across the 2 VIA chipsets. Also that there is little difference between
SDRAM + DDR configuration. So that hopefully just changing a few constants
will get SPD auto configuration working for the epia-m...I got as far as
being able to read out the SPD contents on the epia-m (freebios) but didn't
take it any further.

It sounds like freebios2 is what everyone wants to work on and freebios is
going to get left behind, so I'd better go along...

-Dave



From ts1 at tsn.or.jp  Tue Nov  4 09:46:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Tue Nov  4 09:46:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <Pine.LNX.4.44.0311040734040.28164-100000@maxroach.lanl.gov>
References: <1067955280.568.46.camel@p-133> <Pine.LNX.4.44.0311040734040.28164-100000@maxroach.lanl.gov>
Message-ID: <20031104151729.GA18001@tsn.or.jp>

On Tue, Nov 04, 2003 at 07:35:22AM -0700, ron minnich wrote:
> Andrew or Takeshita, is the M-10000 different in some way important from 
> the standard EPIA-M? Or should we just start a port for the epia-m and 
> that will work for the 10000? 

As far as I know EPIA-M10000 is the EPIA-M board with 1GHz CPU on.
-- 
Takeshi


From aip at cwlinux.com  Tue Nov  4 09:50:00 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Nov  4 09:50:00 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <Pine.LNX.4.44.0311040734040.28164-100000@maxroach.lanl.gov>; from ron minnich on Tue, Nov 04, 2003 at 07:35:22AM -0700
References: <1067955280.568.46.camel@p-133> <Pine.LNX.4.44.0311040734040.28164-100000@maxroach.lanl.gov>
Message-ID: <20031104232153.A7314@mail.cwlinux.com>

Hi,

> Andrew or Takeshita, is the M-10000 different in some way important from 
> the standard EPIA-M? Or should we just start a port for the epia-m and 
> that will work for the 10000? 
It is the same.  10000 means 1GHz, 800 means 800MHz.  BTW, VIA has a new
board which is the same as epia-m but with 2 lan's and pcmcia slot for wireless.

-Andrew

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From rminnich at lanl.gov  Tue Nov  4 10:39:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov  4 10:39:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <20031104232153.A7314@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.44.0311040910010.32465-100000@maxroach.lanl.gov>

On Tue, 4 Nov 2003, Andrew Ip wrote:

> Hi,
> 
> > Andrew or Takeshita, is the M-10000 different in some way important from 
> > the standard EPIA-M? Or should we just start a port for the epia-m and 
> > that will work for the 10000? 
> It is the same.  10000 means 1GHz, 800 means 800MHz.  BTW, VIA has a new
> board which is the same as epia-m but with 2 lan's and pcmcia slot for wireless.

ok, time to bring epia-m in to the linuxbios v2 world. I'll start on that 
soon, unless someone beats me to it (please, somebody, beat me to it :) 

ron



From xpegenaute at telepolis.es  Tue Nov  4 10:51:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Nov  4 10:51:00 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <200311041507.hA4F77bm017810@xdr.com>
References: <200311041507.hA4F77bm017810@xdr.com>
Message-ID: <1067962986.565.55.camel@p-133>

Hi,

> Regarding epia-m, I'm not sure if the changes I posted were incorporated
> into the freebios tree. These consisted of
> 1) VGA working fully at least for going into linux/XFree86
> 2) Fixed vga bug where it would get in an endless loop and not exit in the
> init (actually came up with a workaround).
> 3) Improved the reboot procedure so it does a pci reset to reset the pci bus.
> This is for a clean soft reset.

Please can you send me the patch ?

Thanks.
Xavi.



From bgr at gw.linespeed.net  Tue Nov  4 11:04:01 2003
From: bgr at gw.linespeed.net (Brian G. Rhodes)
Date: Tue Nov  4 11:04:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <20031104232153.A7314@mail.cwlinux.com>
References: <1067955280.568.46.camel@p-133> <Pine.LNX.4.44.0311040734040.28164-100000@maxroach.lanl.gov>
 <20031104232153.A7314@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.58.0311041021280.13832@gw.linespeed.net>

Andrew,

Is this board currently in production/released?  The most recent board I
have seen from VIA on the same epia-m reference design is the CL series
with 2 Network connections.  It doesn't mention a PC Card interface.

Brian G Rhodes
bgr at linespeed.net
brhodes at visualcircuits.com
+1 612-741-1191


On Tue, 4 Nov 2003, Andrew Ip wrote:

> Hi,
>
> > Andrew or Takeshita, is the M-10000 different in some way important from
> > the standard EPIA-M? Or should we just start a port for the epia-m and
> > that will work for the 10000?
> It is the same.  10000 means 1GHz, 800 means 800MHz.  BTW, VIA has a new
> board which is the same as epia-m but with 2 lan's and pcmcia slot for wireless.
>
> -Andrew
>
> --
> Andrew Ip
> Email:  aip at cwlinux.com
> Tel:    (852) 2542 2046
> Fax:    (852) 2542 2036
> Mobile: (852) 9201 9866
>
> Cwlinux Limited
> Unit 202B 2/F Lai Cheong Factory Building,
> 479-479A Castle Peak Road,
> Lai Chi Kok, Kowloon,
> Hong Kong.
>
> For public pgp key, please obtain it from http://www.keyserver.net/en.
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From rminnich at lanl.gov  Tue Nov  4 11:06:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov  4 11:06:00 2003
Subject: arima/hdama fails from current cvs
In-Reply-To: <20031104003930.GA8817@suse.de>
Message-ID: <Pine.LNX.4.44.0311040936430.32465-100000@maxroach.lanl.gov>

On Tue, 4 Nov 2003, Stefan Reinauer wrote:

> Maybe an additional entry in irq_tables.c helps?
>  /* Let Linux know about bus 1 */
>  {0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xde
> f8}, {0x00, 0xdef8}}, 0x00, 0},

that is already in there. It did not help. Linux is not scanning all the 
busses again. 

Time for debug printks I guess. 

ron



From rminnich at lanl.gov  Tue Nov  4 11:07:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov  4 11:07:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <1067962986.565.55.camel@p-133>
Message-ID: <Pine.LNX.4.44.0311040938260.32465-100000@maxroach.lanl.gov>

On 4 Nov 2003, Xavier Pegenaute wrote:

> Hi,
> 
> > Regarding epia-m, I'm not sure if the changes I posted were incorporated
> > into the freebios tree. These consisted of
> > 1) VGA working fully at least for going into linux/XFree86
> > 2) Fixed vga bug where it would get in an endless loop and not exit in the
> > init (actually came up with a workaround).
> > 3) Improved the reboot procedure so it does a pci reset to reset the pci bus.
> > This is for a clean soft reset.
> 
> Please can you send me the patch ?
> 
> Thanks.

Please send them to me as well, I will push them in.

thanks

ron



From ts1 at tsn.or.jp  Tue Nov  4 11:15:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Tue Nov  4 11:15:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <Pine.LNX.4.44.0311040910010.32465-100000@maxroach.lanl.gov>
References: <20031104232153.A7314@mail.cwlinux.com> <Pine.LNX.4.44.0311040910010.32465-100000@maxroach.lanl.gov>
Message-ID: <20031104164624.GA20797@tsn.or.jp>

On Tue, Nov 04, 2003 at 09:10:42AM -0700, ron minnich wrote:
> ok, time to bring epia-m in to the linuxbios v2 world. I'll start on that 
> soon, unless someone beats me to it (please, somebody, beat me to it :) 

Shouldn't we fix the RAM configuration of EPIA first?
As Dave said, this code should be easily ported from EPIA to EPIA-M.
But current code is not fully SPD (uses probing for MA mapping type)
and does not correctly handle the second bank and so on.

I thought you are doing this since we talked about how to do this.
Maybe I can do it if you are too busy.
-- 
Takeshi


From rminnich at lanl.gov  Tue Nov  4 12:35:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov  4 12:35:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <20031104164624.GA20797@tsn.or.jp>
Message-ID: <Pine.LNX.4.44.0311041105340.32465-100000@maxroach.lanl.gov>

On Wed, 5 Nov 2003, Takeshi Sone wrote:

> On Tue, Nov 04, 2003 at 09:10:42AM -0700, ron minnich wrote:
> > ok, time to bring epia-m in to the linuxbios v2 world. I'll start on that 
> > soon, unless someone beats me to it (please, somebody, beat me to it :) 
> 
> Shouldn't we fix the RAM configuration of EPIA first?

yes.

> As Dave said, this code should be easily ported from EPIA to EPIA-M.

maybe. DDR is different.

> But current code is not fully SPD (uses probing for MA mapping type)
> and does not correctly handle the second bank and so on.

OK. 

> I thought you are doing this since we talked about how to do this.
> Maybe I can do it if you are too busy.


If you could that would help. I got pulled off to another emergency for a 
week or so.

ron



From linuxbios at xdr.com  Tue Nov  4 16:17:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Tue Nov  4 16:17:01 2003
Subject: LinuxBios in epia m-10000 (freebios2)
Message-ID: <200311042148.hA4LmPYU019278@xdr.com>

>Please can you send me the patch ?

This is problematic...my version is probably way out of date.
Here are my original posts though:
http://www.clustermatic.org/pipermail/linuxbios/2003-July/004061.html

I vaguely remember sending a small tarball but I think that was to Andrew
directly.

The stuff in the above link doesn't have the VGA bios crash fix I came
up with. It seems like no one else had any trouble with it crashing though.
I can dig that up if necessary.

I'll try to get a complete diff of my tree against the snapshot I started
with...maybe that will be most helpful.

-Dave


From linuxbios at xdr.com  Tue Nov  4 16:29:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Tue Nov  4 16:29:00 2003
Subject: NXTV's current linuxbios patch
Message-ID: <200311042200.hA4M0kEq019341@xdr.com>

I did a clean cvs checkout of freebios, then updated to 2003/7/5, and
did a diff between what's in our cvs and that, and this is the result.
It appears to be everything I touched. I got rid of all the CVS tree
differences.

Hope this is useful...I'm including a uuencoded gzip file. Sort of
dating myself here...
begin 644 freebios-nxtv-patch-20030705.gz
M'XL(""L at J#\``V9R965B:6]S+6YX='8M<&%T8V at M,C`P,S`W,#4`O#MK<]K(
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M9.6'P;P?(OL#G['8X[/CNB5US30/<C)!NFCUDGRU7(YL<V%UA?B=H-I)MRN=
M@,+^#X+JW1\VEU&U;&FHBOV9^L/N#ZO0U8#891#4C7N'E)WG21[_:TH^U?WL
M_'9W&$#<JAEM9<(_-&1/*K-T[6!TBYK!8"CZ(-NCU\<U:!8BMUOF9K.]=J/;
M52]Z>XU>9U8DNYJ-6E8D+WC).OQPKZ*<0O\56+4K7+*S,X=5]>\N:OW?A?UZ
M.S6H%]O&CF9#3!N9_VR\+V-]^^X<%3.\/>38[ERM10C82]FM"*&*^-P;/C)`
MMF2A+,ONOQ*WE5==6".Y><FHV-_`4,Q!YWR&&:E!>:@-D5I[>?SFX-<-%&,$
M#G8/3)!^3F[0$"?AKCR!8'.5@;2K`Y%^SR[>+^V at XV((I[&U6D-G^L_DD?8H
M]<,-?/'.<T_UJ]XH2''[0(26YJD_8J?MCI39F#Z=]DZO]5"<F?1F)M);.(\M
M?P2MWK(1F'GW%DR[MWC6+^K[G(\EGY^*+\9003U#'1V^5T?W%&`O[69'L]5[
M$*/'H7RQHE1U%DA5&U*U`HR=)X"Q^P0PND\`8^\)8%1Y]#$P?G@"&.$R&(_0
M7#@RJ87ZGZ.#"_6&(@A8Z@"U/^1XT"_>X^:NKQ,ZNROI-FI6CGO at JY^R>46)
MM4K at JKZ]-FARN/N%^,78/#9OSKMPUNRQ:Z5;9.Z.V&E];^\DT5%N>?G"S$^X
M&(0-JQL&R>&IXA'8:JC0E$/-#DQ<B5X7`UL4,(T'O18.5/\-)\13F/6Q>D)Y
M38,Y(5%-2QVKX"([7#^Y(V<N+XN!'@M(KL/;PV%,>_HZO,?_V7OES&VYSFCX
M'KU`7X>)J_3HHXSI<^[1JYGVPR[-FP?`S(0O`0A5,>;K"^3,?'&W%#7F.R'D
M)CU<0#PHY)((WO.8H6HO&2$9B8L/L$/V9I3=V:WWS0?P&*H/%S.9M%B)RZ3I
M[&6)JQQW_VA(<L0]GW"_IP^XWZ[C%0$Y[]+%H/5TS&)[>C2W.!`,NS!K@!?X
M]A!U at _.C4]E%BP-S^")J!;I at PX`ZC$?J_"HD+H"[<QY/<O4S?<JS#_%@1?9`
M#@BG?L[ECK+!,N8H6WXF;SP0T,(;.7UX7Y at OO(X>PQ85`(8KB-CR_\4DIHCT
MK*E>Q<.TCZ*:/Q=X]->;N`AQ(MU/WQPF(UPNR[U4J#6=).GVP<LW[V@<@V'!
F=X9L$\/9BSW`179 at 2UN#O^)\48?NI2$>;/<'#>;?4(N]P*"&````
`
end


From riskin at esinosoft.com  Tue Nov  4 20:10:01 2003
From: riskin at esinosoft.com (riskin at esinosoft.com)
Date: Tue Nov  4 20:10:01 2003
Subject: migrate VIA vt5426 to PCChip M787CL(not M787CL+)
Message-ID: <200311050109.hA519F832733@nwn.definitive.org>

Hello ron,

After I migrated VIA vt5426 to new mainboard(PCChips M787CL,not M787CL+: NB is  VT8601,SB is VT82C686B),when probing PCI devices,the kernel halted.So is there any option in LinuxBIOS need to be configed to avoid the kernel halt? But the kernel can work well on PCChips M/B bios.

I used freebios 1.x,not 2.x because I knew about 1.x more than 2.x.

Could you help me?thanks!

riskin

The boot messages:

LinuxBIOS-1.0.0 Tue Nov 4 17:39:15 CST 2003 starting...
Enabled first bank of RAM: 0x04000000 bytes
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
VGA not ready yet.
POST: 0x39
LinuxBIOS-1.0.0 Tue Nov 4 17:39:15 CST 2003 booting...
POST: 0x40
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f
Scanning PCI bus...PCI: pci_scan_bus for bus 0
POST: 0x24
PCI: 00:00.0 [1106/0601]
PCI: 00:01.0 [1106/8601]
PCI: 00:07.0 [1106/0686]
PCI: 00:07.2 [1106/3038]
PCI: 00:07.3 [1106/3038]
PCI: 00:07.4 [1106/3057]
PCI: 00:07.5 [1106/3058]
PCI: 00:07.6 [1106/3068]
PCI: 00:0e.0 [10ec/8139]
POST: 0x25
PCI: pci_scan_bus for bus 1
POST: 0x24
PCI: 01:00.0 [1023/8500]
POST: 0x25
PCI: pci_scan_bus returning with max=01
POST: 0x55
PCI: pci_scan_bus returning with max=01
POST: 0x55
done
POST: 0x66
Allocating PCI resources...
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
ASSIGN RESOURCES, bus 0
PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io
PCI: 00:01.0 24 <- [0xfe900000 - 0xfe8fffff] bus 1 prefmem
PCI: 00:01.0 20 <- [0xfd800000 - 0xfe8fffff] bus 1 mem
ASSIGN RESOURCES, bus 1
PCI: 01:00.0 10 <- [0xfd800000 - 0xfdffffff] mem
PCI: 01:00.0 14 <- [0xfe800000 - 0xfe81ffff] mem
PCI: 01:00.0 18 <- [0xfe000000 - 0xfe7fffff] mem
ASSIGNED RESOURCES, bus 1
PCI: 00:07.2 20 <- [0x00001c00 - 0x00001c1f] io
PCI: 00:07.3 20 <- [0x00001c20 - 0x00001c3f] io
PCI: 00:07.5 10 <- [0x00001000 - 0x000010ff] io
PCI: 00:07.5 14 <- [0x00001c40 - 0x00001c43] io
PCI: 00:07.5 18 <- [0x00001c50 - 0x00001c53] io
PCI: 00:07.6 10 <- [0x00001400 - 0x000014ff] io
PCI: 00:0e.0 10 <- [0x00001800 - 0x000018ff] io
PCI: 00:0e.0 14 <- [0xfe900000 - 0xfe9000ff] mem
ASSIGNED RESOURCES, bus 0
Allocating VGA resource
done.
POST: 0x88
Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 cmd <- 07
PCI: 00:07.0 cmd <- 87
PCI: 00:07.2 cmd <- 01
PCI: 00:07.3 cmd <- 01
PCI: 00:07.4 cmd <- 00
PCI: 00:07.5 cmd <- 01
PCI: 00:07.6 cmd <- 01
PCI: 00:0e.0 cmd <- 03
PCI: 01:00.0 cmd <- 03
done.
Initializing PCI devices...
PCI devices initialized
POST: 0x89
Disable Cache
Bank2 64MB (MA type 0x8)
bank 4 MA 0x0: 0 bytes
bank 4 MA 0x8: 0 bytes
bank 4 MA 0xe: 0 bytes
Enable Cache
Total 56MB + frame buffer 8MB
Enabling shadow DRAM at 0xC0000-0xFFFFF: done
POST: 0x70
totalram: 56M
Initializing CPU #0
POST: 0x60
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) type: WB
Setting fixed MTRRs(24-88) type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:   32MB, type WB
Setting variable MTRR 1, base:   32MB, range:   16MB, type WB
Setting variable MTRR 2, base:   48MB, range:    8MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
call intel_enable_fixed_mtrr()
call intel_enable_var_mtrr()
Leave setup_mtrrs
POST: 0x6a
done.

Max cpuid index    : 1
Vendor ID          : CentaurHauls
Processor Type     : 0x00
Processor Family   : 0x06
Processor Model    : 0x07
Processor Mask     : 0x00
Processor Stepping : 0x03
Feature flags      : 0x00803035

POST: 0x92

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Disabling local apic...done.
POST: 0x9b
CPU #0 Initialized
Mainboard fixup
IDE enable in reg. 48 is 0x3
set IDE reg. 48 to 0x1
IRQs in reg. 4a are 0x4
setting reg. 4a to 0x44
enables in reg 0x42 0xc9
enables in reg 0x42 read back as 0x9
IDE enable in reg.1-40 is 0x8
set IDE reg.1-40 to 0xb
IDE enable in reg.1-40 read back is 0xb
enables in reg 0x9 0x8f
enables in reg 0x9 read back as 0x8a
command in reg 0x4 0x80
command in reg 0x4 reads back as 0x7
POST: 0x75
POST: 0x77
POST: 0x91
POST: 0x92
keyboard_on
POST: 0x05
POST: 0x05
POST: 0x05
POST: 0x05
POST: 0x05
POST: 0x95
Final mainboard fixup
Southbridge fixup
keyboard_on
POST: 0x05
POST: 0x05
POST: 0x05
POST: 0x05
IDE enable in reg. 48 is 0x5
set IDE reg. 48 to 0x5
IRQs in reg. 4a are 0x4
setting reg. 4a to 0x44
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
IDE enable in reg.1-40 is 0xb
set IDE reg.1-40 to 0xb
IDE enable in reg.1-40 read back is 0xb
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8a
command in reg 0x4 0x7
command in reg 0x4 reads back as 0x7
Initializing vt8601 vga...POST: 0xa0
done.
Setting graphics mode...
pcx file at fffe0004 length 0
vga_load_pcx: not a compatible .pcx file.
clocks_per_usec: 911
alpha mode set.
POST: 0xa1
POST: 0xec
POST: 0x9a
Checking IRQ routing tables...
/home/chenyq/linuxbios/NOW/freebios/src/arch/i386/lib/pirq_routing.c:    30:check_pirq_routing_table() - irq_routing_table located at: 0x0000c240
done.
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...succeed
POST: 0x96
Wrote linuxbios table at: 00000500 - 00000688  checksum 871a
Jumping to linuxbiosmain()...
POST: 0xed

Welcome to start32, the open sourced starter.
This space will eventually hold more diagnostic information.

January 2000, James Hendricks, Dale Webster, and Ron Minnich.
Version 0.1

POST: 0xf1
Trying polled ide
Waiting for ide disks to spin up
This is a hard coded delay and longer than necessary.
..
init_controller 0 at (1f0, 3f4)
Testing for disk 0
Probing for disk 0
disk0 31296k cap: 200
Gunzip setup
gunzip_setup
output data is 0x00100000
Gunzipping boot code
................flush 0x00100000 count 0x00008000
...................................flush 0x00108000 count 0x00008000
.....................................flush 0x00110000 count 0x00008000
..................................flush 0x00118000 count 0x00008000
....................................flush 0x00120000 count 0x00008000
.....................................flush 0x00128000 count 0x00008000
.....................................flush 0x00130000 count 0x00008000
....................................flush 0x00138000 count 0x00008000
..................................flush 0x00140000 count 0x00008000
......................................flush 0x00148000 count 0x00008000
.....................................flush 0x00150000 count 0x00008000
...................................flush 0x00158000 count 0x00008000
.....................................flush 0x00160000 count 0x00008000
.................................flush 0x00168000 count 0x00008000
.................................flush 0x00170000 count 0x00008000
........................flush 0x00178000 count 0x00008000
....................................flush 0x00180000 count 0x00008000
....................................flush 0x00188000 count 0x00008000
..................................flush 0x00190000 count 0x00008000
.....................................flush 0x00198000 count 0x00008000
.....................................flush 0x001a0000 count 0x00008000
................................flush 0x001a8000 count 0x00008000
...............................flush 0x001b0000 count 0x00008000
................................flush 0x001b8000 count 0x00008000
..............................flush 0x001c0000 count 0x00008000
....................................flush 0x001c8000 count 0x00008000
....................................flush 0x001d0000 count 0x00008000
.....................................flush 0x001d8000 count 0x00008000
..................................flush 0x001e0000 count 0x00008000
......................................flush 0x001e8000 count 0x00008000
...................................flush 0x001f0000 count 0x00008000
...............................flush 0x001f8000 count 0x00008000
.......................................flush 0x00200000 count 0x00008000
......................................flush 0x00208000 count 0x00008000
....................................flush 0x00210000 count 0x00008000
......................................flush 0x00218000 count 0x00008000
....................................flush 0x00220000 count 0x00008000
....................................flush 0x00228000 count 0x00008000
....................................flush 0x00230000 count 0x00008000
....................................flush 0x00238000 count 0x00008000
..................................flush 0x00240000 count 0x00008000
..................................flush 0x00248000 count 0x00008000
.....................................flush 0x00250000 count 0x00008000
.....................................flush 0x00258000 count 0x00008000
....................................flush 0x00260000 count 0x00008000
...................................flush 0x00268000 count 0x00008000
....................................flush 0x00270000 count 0x00008000
...................................flush 0x00278000 count 0x00008000
.................................flush 0x00280000 count 0x00008000
...................................flush 0x00288000 count 0x00008000
.................................flush 0x00290000 count 0x00008000
.............................flush 0x00298000 count 0x00008000
.......................flush 0x002a0000 count 0x00008000
................flush 0x002a8000 count 0x00008000
......................flush 0x002b0000 count 0x00008000
...........flush 0x002b8000 count 0x00008000
....................flush 0x002c0000 count 0x00008000
..................flush 0x002c8000 count 0x00008000
........................flush 0x002d0000 count 0x00008000
...................flush 0x002d8000 count 0x00008000
.................flush 0x002e0000 count 0x00008000
...............flush 0x002e8000 count 0x00008000
............flush 0x002f0000 count 0x00008000
............................flush 0x002f8000 count 0x00008000
................................flush 0x00300000 count 0x00008000
....................flush 0x00308000 count 0x00008000
..............flush 0x00310000 count 0x00008000
......................flush 0x00318000 count 0x00008000
........................flush 0x00320000 count 0x00008000
.........................flush 0x00328000 count 0x00008000
....................flush 0x00330000 count 0x00008000
................................flush 0x00338000 count 0x00008000
....................flush 0x00340000 count 0x00008000
.................flush 0x00348000 count 0x00008000
.......................................flush 0x00350000 count 0x00008000
....................................flush 0x00358000 count 0x00008000
...............................flush 0x00360000 count 0x00008000
.....flush 0x00368000 count 0x00002c10
<1029> POST: 0xf8
POST: 0xf9
POST: 0xfa

command line - [root=/dev/hda2 rw console=ttyS0,115200n8 init=/linuxrc]
Jumping to boot code
POST: 0xfe
Linux version 2.4.20 (root at SETI) (gcc version egcs-2.91.66 19990314/Linux (egcs-1.1.2 release)) #19 Tue Sep 9 18:04:04 CST 2003
BIOS-provided physical RAM map:
 BIOS-e801: 0000000000000000 - 000000000009f000 (usable)
 BIOS-e801: 0000000000100000 - 0000000003700000 (usable)
55MB LOWMEM available.
On node 0 totalpages: 14080
zone(0): 4096 pages.
zone(1): 9984 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/hda2 rw console=ttyS0,115200n8 init=/linuxrc
Initializing CPU#0
Detected 800.049 MHz processor.
Calibrating delay loop... 1595.80 BogoMIPS
Memory: 52592k/56320k available (1656k kernel code, 3340k reserved, 690k data, 112k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Dentry cache hash table entries: 8192 (order: 4, 65536 bytes)
Inode cache hash table entries: 4096 (order: 3, 32768 bytes)
Mount-cache hash table entries: 1024 (order: 1, 8192 bytes)
Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line)
CPU: L2 Cache: 64K (32 bytes/line)
CPU: Centaur VIA Samuel 2 stepping 03
Checking 'hlt' instruction... OK.
Checking for popad bug... OK.
POSIX conformance testing by UNIFIX
PCI: Using configuration type 1
PCI: Probing PCI hardware


From rminnich at lanl.gov  Tue Nov  4 21:01:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov  4 21:01:01 2003
Subject: migrate VIA vt5426 to PCChip M787CL(not M787CL+)
In-Reply-To: <200311050141.hA51fqtp012747@mailproxy2.lanl.gov>
Message-ID: <Pine.LNX.4.44.0311041931340.4387-100000@maxroach.lanl.gov>

On Wed, 5 Nov 2003 riskin at esinosoft.com wrote:

> After I migrated VIA vt5426 to new mainboard(PCChips M787CL,not M787CL+:
> NB is VT8601,SB is VT82C686B),when probing PCI devices,the kernel
> halted.So is there any option in LinuxBIOS need to be configed to avoid
> the kernel halt? But the kernel can work well on PCChips M/B bios.

This is an old bug with the chipset. I think we may still have a patch for 
it. If linux scans any devfn above (I think) 0x40, the chipset locks up. 

Sorry.

ron



From rminnich at lanl.gov  Wed Nov  5 00:23:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov  5 00:23:00 2003
Subject: Trying to get a handle on CMOS usage
Message-ID: <Pine.LNX.4.44.0311042250570.5938-100000@maxroach.lanl.gov>

I just found an issue with CMOS usage, and I am trying to figure out what 
tools use CMOS in which cases. 

So, can we summarize: 
- does etherboot do anything to bits in CMOS? If so, what? 

- what bits in CMOS is linuxbios V2 currently messing with?  (yeah, I
  should know this, but it turns out I don't currently; I'm still looking for 
  the place where linuxbios V2 writes to cmos nowadays)

Finally, is the CMOS really 256 bytes nowadays on something like the EPIA, 
or are we stuck at 128 still? I'm not sure at this point. 

Any and all information would be nice to have. The problem I've hit is 
that I'm storing authentication data for Plan 9 in cmos, and it appears 
that linuxbios/etherboot are storing to bytes at location 0x1f or so, 
which is bad for me. I need to find 112 bytes that will be unmolested by 
either linuxbios or etherboot.


thanks

ron



From ebiederman at lnxi.com  Wed Nov  5 04:30:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Nov  5 04:30:01 2003
Subject: [Etherboot-developers] Trying to get a handle on CMOS usage
In-Reply-To: <Pine.LNX.4.44.0311042250570.5938-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311042250570.5938-100000@maxroach.lanl.gov>
Message-ID: <m38ymvuo8r.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> I just found an issue with CMOS usage, and I am trying to figure out what 
> tools use CMOS in which cases. 
> 
> So, can we summarize: 
> - does etherboot do anything to bits in CMOS? If so, what? 

There are a couple of variables  that allow me to control the boot oder
from LinuxBIOS.  But those bits are all documented in the appropriate
LinuxBIOS table.  Etherboot just does a lookup and only uses them
if present.

> - what bits in CMOS is linuxbios V2 currently messing with?  (yeah, I
>   should know this, but it turns out I don't currently; I'm still looking for 
>   the place where linuxbios V2 writes to cmos nowadays)
> 
> Finally, is the CMOS really 256 bytes nowadays on something like the EPIA, 
> or are we stuck at 128 still? I'm not sure at this point. 

Using bits above 128 is interesting.

> Any and all information would be nice to have. The problem I've hit is 
> that I'm storing authentication data for Plan 9 in cmos, and it appears 
> that linuxbios/etherboot are storing to bytes at location 0x1f or so, 
> which is bad for me. 

Roughly that sounds like the real time clock.  Again check the cmos.layout
from the LinuxBIOS build that should have a lot of good information.

> I need to find 112 bytes that will be unmolested by 
> either linuxbios or etherboot.

After you do it probably makes sense to reserve them in cmos.layout
for whatever your purposes are so someone does not kill them.

Having to recompile your BIOS to get extra CMOS options is imperfect
but it ensures the reservations get honored. 

However I suggest you be very careful doing things that way.
CMOS batteries die, and various other odd ball things happen.
Long term we need a solution to store things in flash chips as
well as just in the CMOS.  I'd recommend jffs2 except I think it doesn't
scale down quite small enough.    But it certainly worth looking at.

Eric


From stepan at suse.de  Wed Nov  5 07:45:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov  5 07:45:01 2003
Subject: Trying to get a handle on CMOS usage
In-Reply-To: <Pine.LNX.4.44.0311042250570.5938-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311042250570.5938-100000@maxroach.lanl.gov>
Message-ID: <20031105115246.GA14509@suse.de>

* ron minnich <rminnich at lanl.gov> [031105 06:54]:
> - what bits in CMOS is linuxbios V2 currently messing with?  (yeah, I
>   should know this, but it turns out I don't currently; I'm still looking for 
>   the place where linuxbios V2 writes to cmos nowadays)
> 
> Finally, is the CMOS really 256 bytes nowadays on something like the EPIA, 
> or are we stuck at 128 still? I'm not sure at this point. 
 
Almost all machines nowadays come with 256 bytes.

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From peter.fox at aeroflex.com  Wed Nov  5 09:26:01 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Wed Nov  5 09:26:01 2003
Subject: Bug in am29f040b.c causes flash device not to be recognised
Message-ID: <NEBBJLECKKOPJEEKNGJOOEDCECAA.peter.fox@aeroflex.com>

The following patch needs to be applied to am29f040b.c in the
utils/flash_and_burn directory:

----------------------
--- am29f040b-nv.c	Wed Nov  5 14:33:34 2003
+++ am29f040b.c	Wed Nov  5 14:20:26 2003
@@ -76,8 +76,8 @@
 	*(bios + 0x2AA) = 0x55;
 	*(bios + 0x555) = 0x90;
 
-	id1 = *(unsigned char *) bios;
-	id2 = *(unsigned char *) (bios + 0x01);
+	id1 = *(volatile unsigned char *) bios;
+	id2 = *(volatile unsigned char *) (bios + 0x01);
 
 	*bios = 0xF0;

----------------------

My C compiler was reordering the writes and reads, so that
the flash wasn't ready to give an id when the reads occurred.

I notice that all the other flash devices already seem to have
this correct.

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200


From rminnich at lanl.gov  Wed Nov  5 11:06:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov  5 11:06:01 2003
Subject: Bug in am29f040b.c causes flash device not to be recognised
In-Reply-To: <NEBBJLECKKOPJEEKNGJOOEDCECAA.peter.fox@aeroflex.com>
Message-ID: <Pine.LNX.4.44.0311050937030.10127-100000@maxroach.lanl.gov>

I applied the fix in a slightly different way, can you test this for me?

It looks like this now:

int probe_29f040b (struct flashchip * flash)
{
        volatile unsigned char * bios = flash->virt_addr;
        unsigned char id1, id2;

        *(bios + 0x555) = 0xAA;
        *(bios + 0x2AA) = 0x55;
        *(bios + 0x555) = 0x90;
   
        id1 = * bios;
        id2 = * (bios + 0x01);

        *bios = 0xF0;

        myusec_delay(10);
   
        printf("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
        if (id1 == flash->manufacture_id && id2 == flash->model_id)
                return 1;

        return 0;
}


ron



From ts1 at tsn.or.jp  Wed Nov  5 13:22:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Wed Nov  5 13:22:00 2003
Subject: LinuxBios in epia m-10000 (freebios2)
In-Reply-To: <Pine.LNX.4.44.0311041105340.32465-100000@maxroach.lanl.gov>
References: <20031104164624.GA20797@tsn.or.jp> <Pine.LNX.4.44.0311041105340.32465-100000@maxroach.lanl.gov>
Message-ID: <20031105185342.GA9326@tsn.or.jp>

On Tue, Nov 04, 2003 at 11:06:08AM -0700, ron minnich wrote:
> > I thought you are doing this since we talked about how to do this.
> > Maybe I can do it if you are too busy.
> 
> 
> If you could that would help. I got pulled off to another emergency for a 
> week or so.

This is very rough but gets rid of the probing code.
It works with 64MB and 256MB DIMMs (single sided) at any slot, and
confirmed with memtest86 test#2.

romcc -O2 --> -O was needed because with -O2 romcc segfaults.
-- 
Takeshi
-------------- next part --------------
? src/northbridge/via/vt8601/raminit.c.ts1
? targets/epia
? targets/via/epia/epia
Index: src/mainboard/via/epia/Config.lb
===================================================================
RCS file: /cvsroot/freebios/freebios2/src/mainboard/via/epia/Config.lb,v
retrieving revision 1.8
diff -u -r1.8 Config.lb
--- src/mainboard/via/epia/Config.lb	23 Oct 2003 15:09:56 -0000	1.8
+++ src/mainboard/via/epia/Config.lb	5 Nov 2003 18:47:23 -0000
@@ -131,7 +131,7 @@
 
 makerule ./failover.inc
 	depends "./failover.E ./romcc"
-	action "./romcc -O2 -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
+	action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
 end
 
 makerule ./auto.E 
@@ -140,7 +140,7 @@
 end
 makerule ./auto.inc 
 	depends "./auto.E ./romcc"
-	action	"./romcc   -O2 -mcpu=c3 ./auto.E "
+	action	"./romcc   -O -mcpu=c3 ./auto.E "
 end
 
 ##
@@ -230,4 +230,3 @@
 ##
 mainboardinit pc80/serial.inc
 mainboardinit arch/i386/lib/console.inc
-
Index: src/mainboard/via/epia/auto.c
===================================================================
RCS file: /cvsroot/freebios/freebios2/src/mainboard/via/epia/auto.c,v
retrieving revision 1.17
diff -u -r1.17 auto.c
--- src/mainboard/via/epia/auto.c	23 Oct 2003 15:09:56 -0000	1.17
+++ src/mainboard/via/epia/auto.c	5 Nov 2003 18:47:23 -0000
@@ -1,7 +1,7 @@
 #define ASSEMBLY 1
 
-#define MAXIMUM_CONSOLE_LOGLEVEL 6
-#define DEFAULT_CONSOLE_LOGLEVEL 6
+//#define MAXIMUM_CONSOLE_LOGLEVEL 6
+//#define DEFAULT_CONSOLE_LOGLEVEL 6
 
 #include <stdint.h>
 #include <device/pci_def.h>
Index: src/northbridge/via/vt8601/raminit.c
===================================================================
RCS file: /cvsroot/freebios/freebios2/src/northbridge/via/vt8601/raminit.c,v
retrieving revision 1.13
diff -u -r1.13 raminit.c
--- src/northbridge/via/vt8601/raminit.c	23 Oct 2003 15:09:56 -0000	1.13
+++ src/northbridge/via/vt8601/raminit.c	5 Nov 2003 18:47:23 -0000
@@ -54,10 +54,6 @@
 	volatile unsigned long y;
 	eax =  x;
 	for(c = 0; c < 6; c++) {
-		
-		print_debug("dimms_read: ");
-		print_debug_hex32(eax);
-		print_debug("\r\n");
 		y = * (volatile unsigned long *) eax;
 		eax += 0x10000000;
 	}
@@ -68,9 +64,6 @@
 	uint8_t c;
 	unsigned long eax = x;
 	for(c = 0; c < 6; c++) {
-		print_debug("dimms_write: ");
-		print_debug_hex32(eax);
-		print_debug("\r\n");
 		*(volatile unsigned long *) eax = 0;
 		eax += 0x10000000;
 	}
@@ -109,14 +102,6 @@
 
 static void sdram_set_registers(const struct mem_controller *ctrl) 
 {
-	static const uint16_t raminit_ma_reg_table[] = {
-		/* Values for MA type register to try */
-		0x0000, 0x8088, 0xe0ee,
-		0xffff // end mark
-	};
-	static const unsigned char ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 
-	  				0x56, 0x57};
-
 	device_t north = (device_t) 0;
 	uint8_t c, r;
 
@@ -193,67 +178,64 @@
 	// high drive strength on MA[2:	13], we#, cas#, ras#
 	// As per Cindy Lee, set to 0x37, not 0x57
 	pci_write_config8(north,0x6D, 0x7f);
-
-	/* Initialize all banks at once */
-
 }
 
-/* slot is the dram slot. Base is the *8M base. */
-static unsigned char 
-do_module_size(unsigned char slot /*, unsigned char base) */) 
+/* slot is the dram slot. Return size of side0 in lower 16-bit,
+ * side1 in upper 16-bit, in units of 8MB */
+static unsigned long 
+spd_module_size(unsigned char slot) 
 { 
-	static const unsigned char log2[256] = {
-		[1] = 0, [2] = 1, [4] = 2, [8] = 3,
-		[16]=4, [32]=5, [64]=6, 
-		[128]=7
-	};
-	static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 
-					  0x56, 0x57};
-	device_t north = 0;
 	/* for all the DRAMS, see if they are there and get the size of each
 	 * module. This is just a very early first cut at sizing.
 	 */
 	/* we may run out of registers ... */
-	unsigned char width, banks, rows, cols, reg;
-	unsigned char value = 0;
-	unsigned char module = 0xa1 | (slot << 1);
+	unsigned int banks, rows, cols, reg;
+	unsigned int value = 0;
+	unsigned int module = ((0x50 + slot) << 1) + 1;
 	/* is the module there? if byte 2 is not 4, then we'll assume it 
 	 * is useless. 
 	 */
+	print_info("Slot "); 
+	print_info_hex8(slot); 
 	if (smbus_read_byte(module, 2) != 4) {
-		print_err("Slot "); 
-		print_err_hex8(slot); 
-		print_err(" is empty\r\n");
-		goto done;
+		print_info(" is empty\r\n");
+		return 0;
 	}
+	print_info(" is SDRAM ");
 	
-	//print_debug_hex8(slot);
-	//    print_debug(" is SDRAM\n");
-	width = smbus_read_byte(module, 6) | (smbus_read_byte(module,7)<<0);
 	banks = smbus_read_byte(module, 17);
 	/* we're going to assume symmetric banks. Sorry. */
 	cols = smbus_read_byte(module, 4)  & 0xf;
 	rows = smbus_read_byte(module, 3)  & 0xf;
 	/* grand total. You have rows+cols addressing, * times of banks, times
-	 * width of data in bytes*/
-	/* do this in terms of address bits. Then subtract 23 from it. 
-	 * That might do it.
-	 */
-	value = cols + rows + log2[banks] + log2[width];
-	value -= 23;
-	/* now subtract 3 more bits as these are 8-bit bytes */
-	value -= 3;
-	//    print_debug_hex8(value);
-	//    print_debug(" is the # bits for this bank\n");
-	/* now put that size into the correct register */
-	value = (1 << value);
- done:
-	reg = ramregs[slot];
-	
-	//    print_debug_hex8(value); print_debug(" would go into ");
-	//    print_debug_hex8(ramregs[reg]); print_debug("\n");
-	//    pci_write_config8(north, ramregs[reg], value);
+	 * width of data in bytes */
+	/* Width is assumed to be 64 bits == 8 bytes */
+	value = (1 << (cols + rows)) * banks * 8;
+	print_info_hex32(value);
+	print_info(" bytes ");
+	/* Return in 8MB units */
+	value >>= 23;
+
+	/* We should have single or double side */
+	if (smbus_read_byte(module, 5) == 2) {
+		print_info("x2");
+		value = (value << 16) | value;
+	}
+	print_info("\r\n");
 	return value;
+
+}
+
+static int
+spd_num_chips(unsigned char slot) 
+{ 
+	unsigned int module = ((0x50 + slot) << 1) + 1;
+	unsigned int width;
+
+	width = smbus_read_byte(module, 13);
+	if (width == 0)
+		width = 8;
+	return 64 / width;
 }
 
 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
@@ -283,20 +265,32 @@
 	 */
 }
 
+static void set_ma_mapping(device_t north, int slot, int type)
+{
+    unsigned char reg, val;
+    int shift;
+
+    reg = 0x58 + slot/2;
+    if (slot%2 >= 1)
+        shift = 0;
+    else
+        shift = 4;
+
+    val = pci_read_config8(north, reg);
+    val &= ~(0xf << shift);
+    val |= type << shift;
+    pci_write_config8(north, reg, val);
+}
+
+
 static void sdram_enable(int controllers, const struct mem_controller *ctrl) 
 {
 	unsigned char i;
-	static const uint16_t raminit_ma_reg_table[] = {
-		/* Values for MA type register to try */
-		0x0000, 0x8088, 0xe0ee,
-		0xffff // end mark
-	};
 	static const uint8_t ramregs[] = {
 		0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
 	};
-
 	device_t north = 0;
-	uint8_t c, r, base;
+	uint32_t size, base, slot, ma;
 	/* begin to initialize*/
 	// I forget why we need this, but we do
 	dimms_write(0xa55a5aa5);
@@ -363,125 +357,38 @@
 	// enable multi-page open
 	pci_write_config8(north,0x6B, 0x0d);
 	
-	/* Begin auto-detection
-	 * Find the first bank with DIMM equipped. */
-	
-	/* Maximum possible memory in bank 0, none in other banks.
-	 * Starting from bank 0, we fill 0 in these registers
-	 * until memory is found. */
-	pci_write_config8(north,0x5A, 0xff);
-	pci_write_config8(north,0x5B, 0xff);
-	pci_write_config8(north,0x5C, 0xff);
-	pci_write_config8(north,0x5D, 0xff);
-	pci_write_config8(north,0x5E, 0xff);
-	pci_write_config8(north,0x5F, 0xff);
-	pci_write_config8(north,0x56, 0xff);
-	pci_write_config8(north,0x57, 0xff);
-	dumpnorth(north);
-	print_debug("MA\r\n");
-	for(c = 0; c < 8; c++) {
-		/* Write different values to 0 and 8, then read from 0.
-		 * If values of address 0 match, we have something there. */
-		print_debug("write to 0\r\n");
-		*(volatile unsigned long *) 0 = 0x12345678;
-		
-		/* LEAVE THIS HERE. IT IS ESSENTIAL. OTHERWISE BUFFERING
-		 * WILL FOOL YOU!
-		 */
-		print_debug("write to 8\r\n");
-		*(volatile unsigned long *) 8 = 0x87654321;
-		
-		if (*(volatile unsigned long *) 0 != 0x12345678) {
-			print_debug("no memory in this bank\r\n");
-			/* No memory in this bank. Tell it to the bridge. */
-			pci_write_config8(north,ramregs[c], 0);
-		} 
-		/* found something */
-		{
-			uint8_t best = 0;
-			
-			/* Detect MA mapping type of the bank. */
-			
-			for(r = 0; r < 3; r++) {
-				volatile unsigned long esi = 0;
-				volatile unsigned long eax = 0;
-				pci_write_config8(north,0x58, raminit_ma_reg_table[r]);
-				
-				* (volatile unsigned long *) eax = 0;
-				print_debug(" done write to eax\r\n");
-				// Write to addresses with only one address bit
-				// on, from 0x80000000 to 0x00000008 (lower 3 bits
-				// are ignored, assuming 64-bit bus).  Then what
-				// is read at address 0 is the value written to
-				// the lowest address where it gets
-				// wrap-around. That address is either the size of
-				// the bank, or a missing bit due to incorrect MA
-				// mapping.
-				eax = 0x80000000;
-				while (eax !=  4) {
-					* (volatile unsigned long *) eax = eax;
-					//print_debug_hex32(eax);
-					outb(eax&0xff, 0x80);
-					eax >>= 1;
-				}
-				print_debug(" done read to eax\r\n");
-				eax = * (unsigned long *)0;
-				/* oh boy ... what is this. 
-				   movl 0, %eax
-				   cmpl %eax, %esi
-				   jnc 3f
-				*/
-				print_debug("eax and esi: ");
-				print_debug_hex32(eax); print_debug(" ");
-				print_debug_hex32(esi); print_debug("\r\n");
-				
-				if (eax > esi) { /* ??*/
-					
-					// This is the current best MA mapping.
-					// Save the address and its MA mapping value.
-					best = r;
-					esi = eax;
-				}
-			}
-		  
-			pci_write_config8(north,0x58, raminit_ma_reg_table[best]);
-			print_debug("enabled first bank of ram ... ma is ");
-			print_debug_hex8(pci_read_config8(north, 0x58));
-			print_debug("\r\n");
-		}
-	}
 	base = 0;
-	/* runs out of variable space. */
-	/* this is unrolled and constants used as much as possible to help
-	 * us not run out of registers.
-	 * we'll run out of code space instead :-)
-	 */
-	//  for(i = 0; i < 8; i++)
-	base = do_module_size(0); /*, base);*/
-	pci_write_config8(north, ramregs[0], base);
-	base += do_module_size(1); /*, base);*/
-	pci_write_config8(north, ramregs[1], base);
-	/* runs out of code space. */
-	for(i = 2; i < 8; i++){
-		pci_write_config8(north, ramregs[i], base);
-		/*
-		  pci_write_config8(north, ramregs[3], base);
-		  pci_write_config8(north, ramregs[4], base);
-		  pci_write_config8(north, ramregs[5], base);
-		  pci_write_config8(north, ramregs[6], base);
-		  pci_write_config8(north, ramregs[7], base);
-		*/
+	for(slot = 0; slot < 4; slot++) {
+		size = spd_module_size(slot);
+		/* side 0 */
+		base += size & 0xffff;
+		pci_write_config8(north, ramregs[2*slot], base);
+		/* side 1 */
+		base += size >> 16;
+		if (base > 0xff)
+			base = 0xff;
+		pci_write_config8(north, ramregs[2*slot + 1], base);
+
+		if (!size)
+			continue;
+
+		/* Calculate the value of MA mapping type register,
+		 * based on size of SDRAM chips. */
+		size = (size & 0xffff) << (3 + 3);
+			/* convert module size to be in Mbits */
+		size /= spd_num_chips(slot);
+		print_debug_hex16(size);
+		print_debug(" is the chip size\r\n");
+		if (size < 64)
+			ma = 0;
+		if (size < 256)
+			ma = 8;
+		else
+			ma = 0xe;
+		print_debug_hex16(ma);
+		print_debug(" is the MA type\r\n");
+		set_ma_mapping(north, slot, ma);
 	}
-	/*
-	  base = do_module_size(0xa0, base);
-	  base = do_module_size(0xa0, base);
-	  base = do_module_size(0xa0, base);
-	  base = do_module_size(0xa0, base);
-	  base = do_module_size(0xa0, base);
-	  base = do_module_size(0xa0, base);*/
 	print_err("vt8601 done\r\n");
-	/*
 	dumpnorth(north);
-	udelay(1000);
-	*/
 }

From peter.fox at aeroflex.com  Thu Nov  6 03:31:01 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Thu Nov  6 03:31:01 2003
Subject: Bug in am29f040b.c causes flash device not to be recognised
In-Reply-To: <Pine.LNX.4.44.0311050937030.10127-100000@maxroach.lanl.gov>
Message-ID: <NEBBJLECKKOPJEEKNGJOMEDHECAA.peter.fox@aeroflex.com>

That also works, here's the assembly difference between
my version with volatiles in the cast, and yours with
the bios type changed:

--- am29f040b-v.s       Wed Nov  5 14:20:34 2003
+++ am29f040b.s Thu Nov  6 08:54:13 2003
@@ -23,12 +23,12 @@
        subl    $24, %esp
        movl    8(%ebp), %edx
        movl    12(%edx), %eax
-       movb    $-86, 1365(%eax)
+       movb    $170, 1365(%eax)
        movb    $85, 682(%eax)
-       movb    $-112, 1365(%eax)
+       movb    $144, 1365(%eax)
        movzbl  (%eax), %esi
        movb    1(%eax), %bl
-       movb    $-16, (%eax)
+       movb    $240, (%eax)
        movzbl  %bl, %edi
        pushl   $10
        call    myusec_delay

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200

  -----Original Message-----
  From: linuxbios-admin at clustermatic.org
  [mailto:linuxbios-admin at clustermatic.org]On Behalf Of ron minnich
  Sent: 05 November 2003 16:38
  To: Peter Fox
  Cc: Linuxbios
  Subject: Re: Bug in am29f040b.c causes flash device not to be recognised
  
  
  I applied the fix in a slightly different way, can you test this for me?
  
  It looks like this now:
  
  int probe_29f040b (struct flashchip * flash)
  {
          volatile unsigned char * bios = flash->virt_addr;
          unsigned char id1, id2;
  
          *(bios + 0x555) = 0xAA;
          *(bios + 0x2AA) = 0x55;
          *(bios + 0x555) = 0x90;
     
          id1 = * bios;
          id2 = * (bios + 0x01);
  
          *bios = 0xF0;
  
          myusec_delay(10);
     
          printf("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
          if (id1 == flash->manufacture_id && id2 == flash->model_id)
                  return 1;
  
          return 0;
  }
  
  
  ron
  
  _______________________________________________
  Linuxbios mailing list
  Linuxbios at clustermatic.org
  http://www.clustermatic.org/mailman/listinfo/linuxbios


From peter.fox at aeroflex.com  Thu Nov  6 03:43:00 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Thu Nov  6 03:43:00 2003
Subject: Add size option and checks to flash_rom
Message-ID: <NEBBJLECKKOPJEEKNGJOEEDIECAA.peter.fox@aeroflex.com>

The patch below adds a size option to flash_rom, and also verifies
that the bios image being flashed matches the rom size.
(Previously, if the rom image was too small, the image would
be flashed at the beginning of the rom, so the reset vector
would be in the wrong place.)

The advantage of this change is that it is no longer necessary
to pack the bios image up to the rom size, thus saving programming
time. And it is also not necessary to hack the code if you've
wired the top bit to a switch as a BIOS saviour.

It still doesn't check for an image too big, though that should
be taken care of in the build process.

Index: flash_rom.c
===================================================================
RCS file: /home/fox/freebios-latest/freebios/util/flash_and_burn/flash_rom.c,v
retrieving revision 1.23
diff -u -r1.23 flash_rom.c
--- flash_rom.c	2003/09/12 22:41:53	1.23
+++ flash_rom.c	2003/11/06 08:41:33
@@ -272,11 +272,12 @@
   return 0;
 }

-struct flashchip * probe_flash(struct flashchip * flash)
+struct flashchip * probe_flash(struct flashchip * flash, int pretend_size)
 {
     int fd_mem;
     volatile char * bios;
     unsigned long size;
+    int total_size;

     if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
 	perror("Can not open /dev/mem");
@@ -288,15 +289,18 @@
 	    flash++;
 	    continue;
 	}
-	printf("Trying %s, %d KB\n", flash->name, flash->total_size);
-	size = flash->total_size * 1024;
+	total_size = flash->total_size;
+	if((pretend_size != -1)&&(pretend_size < total_size))
+	  total_size = pretend_size;
+	printf("Trying %s, %d KB\n", flash->name, total_size);
+	size = total_size * 1024;
 /* BUG? what happens if getpagesize() > size!?
    -> ``Error MMAP /dev/mem: Invalid argument'' NIKI */
 	if(getpagesize() > size)
 	{
 		size = getpagesize();
 		printf("%s: warning: size: %d -> %ld\n", __FUNCTION__,
-	 		flash->total_size * 1024, (unsigned long)size);
+	 		total_size * 1024, (unsigned long)size);
 	}
 	bios = mmap (0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
 		     fd_mem, (off_t) (0 - size));
@@ -310,6 +314,7 @@
 	if (flash->probe(flash) == 1) {
 	    printf ("%s found at physical address: 0x%lx\n",
 		    flash->name, (0 - size));
+	    flash->total_size = total_size;
 	    return flash;
 	}
 	munmap ((void *) bios, size);
@@ -441,11 +446,12 @@

 void usage(const char *name)
 {
-    printf("usage: %s [-rwv] [-c chipname][file]\n", name);
+    printf("usage: %s [-rwv] [-c chipname] [-s size] [file]\n", name);
     printf("-r: read flash and save into file\n"
         "-w: write file into flash (default when file is specified)\n"
         "-v: verify flash against file\n"
         "-c: probe only for specified flash chip\n"
+        "-s: pretend device is smaller, specify the size in k\n"
         " If no file is specified, then all that happens\n"
         " is that flash info is dumped\n");
     exit(1);
@@ -456,6 +462,7 @@
 {
     char * buf;
     unsigned long size;
+    int pretend_size = -1;
     FILE * image;
     struct flashchip * flash;
     int opt;
@@ -464,7 +471,7 @@

     setbuf(stdout, NULL);

-    while ((opt = getopt(argc, argv, "rwvc:")) != EOF) {
+    while ((opt = getopt(argc, argv, "rwvc:s:")) != EOF) {
         switch (opt) {
         case 'r':
             read_it = 1;
@@ -478,6 +485,9 @@
         case 'c':
             chip_to_probe = strdup(optarg);
             break;
+        case 's':
+            pretend_size = atoi(optarg);
+            break;
         default:
             usage(argv[0]);
             break;
@@ -500,7 +510,7 @@
      */
     (void) enable_flash_write();

-    if ((flash = probe_flash (flashchips)) == NULL) {
+    if ((flash = probe_flash (flashchips, pretend_size)) == NULL) {
 	printf("EEPROM not found\n");
 	exit(1);
     }
@@ -527,12 +537,18 @@
         fclose(image);
         printf("done\n");
     } else {
+      unsigned long filesize = 0;
         if ((image = fopen (filename, "r")) == NULL) {
             perror(filename);
             exit(1);
         }
-        fread (buf, sizeof(char), size, image);
+        filesize = fread (buf, sizeof(char), size, image);
         fclose(image);
+	if(filesize != size)
+	  {
+	    fprintf(stderr, "File size doesn't match device size\n");
+	    exit(1);
+	  }
     }

     if (write_it || (!read_it && !verify_it))

--
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200



From svante.signell at telia.com  Thu Nov  6 03:50:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Thu Nov  6 03:50:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <Pine.LNX.4.44.0310010736580.31770-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0310010736580.31770-100000@maxroach.lanl.gov>
Message-ID: <1068110538.10298.133.camel@em2.my.own.domain>

Hi,

Sorry for taking up this thread again but now I have made a test of the
l2_cache activation code and have some further questions. 

The files put together to make things build are l2_cache.c, printk.c,
vsprintf.c, subr.c and corresponding header files from the linuxbios CVS
tree. For subr.c I had to add an include (#include <sys/io.h>) to get
outb defined for linking. The result so far is a segfault, in the
cache_enable() inline assembly routine in l2_cache.c)

0. How to test this code after a _slow_ boot outside the BIOS? Is single
user mode sufficient, i.e. init 1?
 
1. How are these printk statements supposed to work? Is the output
directed to some system logfile, like kern.log? How to define this
logfile etc. What to change if I want to log debug outputs to the
standard out and/or standard err? I don't find any output when running
the main program, neither in the system log files or on the screen. 

2. Any special compiler and linker switches needed, like -nostdinc,
-nostdlib, -nostartfiles, etc? Your build system is Python based, right,
so I cannot easily look at Makefiles in the CVS tree.

3. I found where the program halts with gdb and compiling with debug
set. One way to trace is single stepping in gdb etc. What is supposed to
happen when the DEBUG is defined in l2_cache.c?

4. You state that the L2 cache stuff is only needed for P2 CPUs, not for
P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron
2 CPU (Tualatin), which is of P3 type. What if the BIOS does not
recognise the CPU and disables the L2 cache? People claim that AMI
BIOSes work this way. It the enabling code sufficient to make things
work.

5. If the slowness is not due to a disabled L2 cache (how to test this
properly btw?), can the  problems be solved by tying with the mtrr or
microcode update code? 

6. Maybe the problem is still hardware related, like the on-board
voltage regulator for the CPU is not working properly, even if there are
no indications at all from the on board sensors. However, if the
problems are software related and can be solved, do you think it is
feasible to replace the AMI BIOS with LinuxBIOS? The probability of
getting an updated BIOS from MSI supporting Coppermine and Tualatin
processors is probably zero.

Thanks,
Svante

On Wed, 2003-10-01 at 15:40, ron minnich wrote:
> On Wed, 1 Oct 2003, Svante Signell wrote:
> 
> > i) Does LinuxBIOS work for 440BX-based mother-boards, single and dual?
> > Downloading the code from CVS shows support for Intel L440GX+ and a
> > patch for linux-2.4.13, not 440BX or kernels later than 2.4.13. Also, I
> > did not find anything about MSI mainboards.
> 
> single are tested. Dual I don't know.
> 
> > ii) Does the cache activation code work for Mendocino, Coppermine,
> > Tualatin and newer Intel processors? Will it work for the VIA C3
> > Nehemiah?
> 
> It was only needed for PII. Coppermine and later -- "Just works". It is 
> extremely cpu-dependent.
> 
> > iii) How much of the boot process in GNU/Linux the BIOS responsible for?
> > I thought that the kernel was only dependent on the BIOS for a few
> > functions, such as different HW initialisations: CPU, memory, disks, etc
> > compared to Windows 9x etc. Any pointers?
> 
> that's about right.
> 
> > I will try. Which files do I need in addition to src/cpu/p6/l2_cache.c?
> 
> none. You have to turn that back into a main() but it should  be fine.
> 
> > With risks I meant the chance of being left with a dead motherboard...
> > I'm always nervous when flashing the BIOS that something will happen,
> > for example a sudden power loss, regardless of where the BIOS originates
> > from.
> 
> never do this kind of work without a spare bios part. Never.
> 
> > BTW: Why is this work called LinuxBIOS (except maybe for historical
> > reasons). Will other OSes (eg GNU/Hurd) boot with LinuxBIOS now or in
> > the future? Maybe then something like FreeBIOS should be used instead.
> 
> It was called linuxbios for a simple reason: linux was going to be the 
> bios. linux would be in flash, linux would boot the oses. 
> 
> Small flashes have caused changes in course in some cases, but the name 
> has stuck anyway. Now that vendors have joined in, changing the name would 
> be hard.
> 
> ron
> 


From mirenna at mi.ingv.it  Thu Nov  6 04:34:00 2003
From: mirenna at mi.ingv.it (Santi Mirenna)
Date: Thu Nov  6 04:34:00 2003
Subject: Help on config of "epia-m.config" file
Message-ID: <5.1.1.6.2.20031106105325.02116cb8@10.1.1.8>

Hi to all,
yesterday i make my first EPIA-M 10000 rom image.
With the help of Eddy i compile to have VGA and Filo.
In attach you have the output log ....
The problem is :
- LinuxBios tell that the RAM is 127Mbye (and i had 256Mbyte)
- LinuxBios tell that there is no VGA (and i add the VGA bios image in to)

Can someone tell me where i wrong?

**********************************************************************************************
  Santi Mirenna
  INGV - Istituto Nazionale di Geofisica e Vulcanologia
  Sezione di Milano
  via Bassini 15, 20133 Milano, Italy
  tel. +39-02-23699278
  fax +39-02-23699458
  e mail: santi.mirenna at mi.ingv.it
  **********************************************************************************************
Questo messaggio ? di carattere riservato ed ? indirizzato esclusivamente al
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lare immediatamente il messaggio, dandone conferma al mittente a mezzo e-mail.

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From ts1 at tsn.or.jp  Thu Nov  6 05:24:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Thu Nov  6 05:24:00 2003
Subject: Help on config of "epia-m.config" file
In-Reply-To: <5.1.1.6.2.20031106105325.02116cb8@10.1.1.8>
References: <5.1.1.6.2.20031106105325.02116cb8@10.1.1.8>
Message-ID: <20031106105532.GB9355@tsn.or.jp>

On Thu, Nov 06, 2003 at 11:03:58AM +0100, Santi Mirenna wrote:
> - LinuxBios tell that the RAM is 127Mbye (and i had 256Mbyte)

That's the hard coded part.

> - LinuxBios tell that there is no VGA (and i add the VGA bios image in to)

LinuxBIOS doesn't enable the VGA device.
You need some part of Dave Ashley's patch.

-- 
Takeshi


From mirenna at mi.ingv.it  Thu Nov  6 05:29:00 2003
From: mirenna at mi.ingv.it (Santi Mirenna)
Date: Thu Nov  6 05:29:00 2003
Subject: Help on config of "epia-m.config" file
In-Reply-To: <20031106105532.GB9355@tsn.or.jp>
References: <5.1.1.6.2.20031106105325.02116cb8@10.1.1.8>
 <5.1.1.6.2.20031106105325.02116cb8@10.1.1.8>
Message-ID: <5.1.1.6.2.20031106115732.020c2d58@10.1.1.8>

At 19.55 06/11/2003 +0900, you wrote:
>On Thu, Nov 06, 2003 at 11:03:58AM +0100, Santi Mirenna wrote:
> > - LinuxBios tell that the RAM is 127Mbye (and i had 256Mbyte)
>
>That's the hard coded part.

What is the file to edit ....to have 256Mbyte?


> > - LinuxBios tell that there is no VGA (and i add the VGA bios image in to)
>
>LinuxBIOS doesn't enable the VGA device.
>You need some part of Dave Ashley's patch.

where to find the patch?


>--
>Takeshi




From xpegenaute at telepolis.es  Thu Nov  6 06:02:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Thu Nov  6 06:02:01 2003
Subject: [Fwd: NXTV's current linuxbios patch]
Message-ID: <1068118453.1400.9.camel@p-133>

Hi, the patch is this one, is a message from Tue, probably you will have
also. If you don't have i'll send you the patch.

About the memory, after the patch, in
src/mainboard/via/epia-m/smbus.inc, at line 245, there is something i
didn't tryed yet but i think is it.

I think there is something more else...

I saw in your log, i have also epia-m 10000 and ,my VGA is:

lspci -n -> 01:00.0 Class 0300: 1106:3122 (rev 03)

lspci -> 01:00.0 VGA compatible controller: VIA Technologies, Inc.:
Unknown device 3122 (rev 03)

Xavi.


-----Forwarded Message-----

> From: Dave Ashley <linuxbios at xdr.com>
> To: linuxbios at clustermatic.org
> Subject: NXTV's current linuxbios patch
> Date: 04 Nov 2003 14:00:46 -0800
> 
> I did a clean cvs checkout of freebios, then updated to 2003/7/5, and
> did a diff between what's in our cvs and that, and this is the result.
> It appears to be everything I touched. I got rid of all the CVS tree
> differences.
> 



From mirenna at mi.ingv.it  Thu Nov  6 07:08:01 2003
From: mirenna at mi.ingv.it (Santi Mirenna)
Date: Thu Nov  6 07:08:01 2003
Subject: [Fwd: NXTV's current linuxbios patch]
In-Reply-To: <1068118453.1400.9.camel@p-133>
Message-ID: <5.1.1.6.2.20031106133559.02118148@10.1.1.8>

Hi,
please, now that i get the patch ...can you tell me how to apply it.

Tino.

At 12.34 06/11/2003 +0100, you wrote:
>Hi, the patch is this one, is a message from Tue, probably you will have
>also. If you don't have i'll send you the patch.
>
>About the memory, after the patch, in
>src/mainboard/via/epia-m/smbus.inc, at line 245, there is something i
>didn't tryed yet but i think is it.
>
>I think there is something more else...
>
>I saw in your log, i have also epia-m 10000 and ,my VGA is:
>
>lspci -n -> 01:00.0 Class 0300: 1106:3122 (rev 03)
>
>lspci -> 01:00.0 VGA compatible controller: VIA Technologies, Inc.:
>Unknown device 3122 (rev 03)
>
>Xavi.
>
>
>-----Forwarded Message-----
>
> > From: Dave Ashley <linuxbios at xdr.com>
> > To: linuxbios at clustermatic.org
> > Subject: NXTV's current linuxbios patch
> > Date: 04 Nov 2003 14:00:46 -0800
> >
> > I did a clean cvs checkout of freebios, then updated to 2003/7/5, and
> > did a diff between what's in our cvs and that, and this is the result.
> > It appears to be everything I touched. I got rid of all the CVS tree
> > differences.
> >




From pyro at linuxlabs.com  Thu Nov  6 08:27:00 2003
From: pyro at linuxlabs.com (steven james)
Date: Thu Nov  6 08:27:00 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1068110538.10298.133.camel@em2.my.own.domain>
Message-ID: <Pine.LNX.4.21.0311060857120.935-100000@ucontrol.mobiledns.com>

Greetings,

To run that code inside linux, you need to add a call to iopl to allow
direct hardware access like:

res = iopl(3);
if(res) {
	report_error();
	exit(-1);
}

or something to that effect.
G'day,
sjames


On Thu, 6 Nov 2003, Svante Signell wrote:

> Hi,
> 
> Sorry for taking up this thread again but now I have made a test of the
> l2_cache activation code and have some further questions. 
> 
> The files put together to make things build are l2_cache.c, printk.c,
> vsprintf.c, subr.c and corresponding header files from the linuxbios CVS
> tree. For subr.c I had to add an include (#include <sys/io.h>) to get
> outb defined for linking. The result so far is a segfault, in the
> cache_enable() inline assembly routine in l2_cache.c)
> 
> 0. How to test this code after a _slow_ boot outside the BIOS? Is single
> user mode sufficient, i.e. init 1?
>  
> 1. How are these printk statements supposed to work? Is the output
> directed to some system logfile, like kern.log? How to define this
> logfile etc. What to change if I want to log debug outputs to the
> standard out and/or standard err? I don't find any output when running
> the main program, neither in the system log files or on the screen. 
> 
> 2. Any special compiler and linker switches needed, like -nostdinc,
> -nostdlib, -nostartfiles, etc? Your build system is Python based, right,
> so I cannot easily look at Makefiles in the CVS tree.
> 
> 3. I found where the program halts with gdb and compiling with debug
> set. One way to trace is single stepping in gdb etc. What is supposed to
> happen when the DEBUG is defined in l2_cache.c?
> 
> 4. You state that the L2 cache stuff is only needed for P2 CPUs, not for
> P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron
> 2 CPU (Tualatin), which is of P3 type. What if the BIOS does not
> recognise the CPU and disables the L2 cache? People claim that AMI
> BIOSes work this way. It the enabling code sufficient to make things
> work.
> 
> 5. If the slowness is not due to a disabled L2 cache (how to test this
> properly btw?), can the  problems be solved by tying with the mtrr or
> microcode update code? 
> 
> 6. Maybe the problem is still hardware related, like the on-board
> voltage regulator for the CPU is not working properly, even if there are
> no indications at all from the on board sensors. However, if the
> problems are software related and can be solved, do you think it is
> feasible to replace the AMI BIOS with LinuxBIOS? The probability of
> getting an updated BIOS from MSI supporting Coppermine and Tualatin
> processors is probably zero.
> 
> Thanks,
> Svante
> 
> On Wed, 2003-10-01 at 15:40, ron minnich wrote:
> > On Wed, 1 Oct 2003, Svante Signell wrote:
> > 
> > > i) Does LinuxBIOS work for 440BX-based mother-boards, single and dual?
> > > Downloading the code from CVS shows support for Intel L440GX+ and a
> > > patch for linux-2.4.13, not 440BX or kernels later than 2.4.13. Also, I
> > > did not find anything about MSI mainboards.
> > 
> > single are tested. Dual I don't know.
> > 
> > > ii) Does the cache activation code work for Mendocino, Coppermine,
> > > Tualatin and newer Intel processors? Will it work for the VIA C3
> > > Nehemiah?
> > 
> > It was only needed for PII. Coppermine and later -- "Just works". It is 
> > extremely cpu-dependent.
> > 
> > > iii) How much of the boot process in GNU/Linux the BIOS responsible for?
> > > I thought that the kernel was only dependent on the BIOS for a few
> > > functions, such as different HW initialisations: CPU, memory, disks, etc
> > > compared to Windows 9x etc. Any pointers?
> > 
> > that's about right.
> > 
> > > I will try. Which files do I need in addition to src/cpu/p6/l2_cache.c?
> > 
> > none. You have to turn that back into a main() but it should  be fine.
> > 
> > > With risks I meant the chance of being left with a dead motherboard...
> > > I'm always nervous when flashing the BIOS that something will happen,
> > > for example a sudden power loss, regardless of where the BIOS originates
> > > from.
> > 
> > never do this kind of work without a spare bios part. Never.
> > 
> > > BTW: Why is this work called LinuxBIOS (except maybe for historical
> > > reasons). Will other OSes (eg GNU/Hurd) boot with LinuxBIOS now or in
> > > the future? Maybe then something like FreeBIOS should be used instead.
> > 
> > It was called linuxbios for a simple reason: linux was going to be the 
> > bios. linux would be in flash, linux would boot the oses. 
> > 
> > Small flashes have caused changes in course in some cases, but the name 
> > has stuck anyway. Now that vendors have joined in, changing the name would 
> > be hard.
> > 
> > ron
> > 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 

-- 
-------------------------steven james, director of research, linux labs
... ........ ..... ....                    230 peachtree st nw ste 2701
the original linux labs                             atlanta.ga.us 30303
      -since 1995                              http://www.linuxlabs.com
                                   office 404.577.7747 fax 404.577.7743
-----------------------------------------------------------------------





From rminnich at lanl.gov  Thu Nov  6 08:40:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Nov  6 08:40:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1068110538.10298.133.camel@em2.my.own.domain>
Message-ID: <Pine.LNX.4.44.0311060710090.18852-100000@maxroach.lanl.gov>

On Thu, 6 Nov 2003, Svante Signell wrote:

> Sorry for taking up this thread again but now I have made a test of the
> l2_cache activation code and have some further questions. 

you don't need this code any more. The last processor it mattered for is 
long dead. I am not removing it but if you are having trouble then you 
have a PII; do you?

> 4. You state that the L2 cache stuff is only needed for P2 CPUs, not for
> P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron
> 2 CPU (Tualatin), which is of P3 type. What if the BIOS does not
> recognise the CPU and disables the L2 cache? People claim that AMI
> BIOSes work this way. It the enabling code sufficient to make things
> work.

which BIOS?

> 5. If the slowness is not due to a disabled L2 cache (how to test this
> properly btw?), can the  problems be solved by tying with the mtrr or
> microcode update code? 

use lmbench to scope out your caches.

ron



From rminnich at lanl.gov  Thu Nov  6 08:43:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Nov  6 08:43:01 2003
Subject: Help on config of "epia-m.config" file
In-Reply-To: <5.1.1.6.2.20031106115732.020c2d58@10.1.1.8>
Message-ID: <Pine.LNX.4.44.0311060714000.18852-100000@maxroach.lanl.gov>

On Thu, 6 Nov 2003, Santi Mirenna wrote:

> At 19.55 06/11/2003 +0900, you wrote:
> >On Thu, Nov 06, 2003 at 11:03:58AM +0100, Santi Mirenna wrote:
> > > - LinuxBios tell that the RAM is 127Mbye (and i had 256Mbyte)
> >
> >That's the hard coded part.
> 
> What is the file to edit ....to have 256Mbyte?

Just as a reminder, this is the only hardware on linuxbios that you "patch 
a file" to get memory size, and we hope to fix this soon. The EPIA-M port 
is not a good example!

ron



From stepan at suse.de  Thu Nov  6 09:44:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Nov  6 09:44:01 2003
Subject: config -> default
Message-ID: <20031106151608.GA839@suse.de>

Hi,

most of the builds are broken again since "config" in the mainboard
config file now has to be renamed to "default". On the one hand I see 
the reason for most of these changes, even though I am not sure if
we want to suggest that some stuff can be overridden in the target 
config file, like:

-option CONFIG_IOAPIC=1
+default CONFIG_IOAPIC=1

Can those changing elementary stuff like this that breaks all builds try
to apply some regexps on the Config files so that other builds don't
break? Getting further is somewhat hard currently since the code almost
instantly breaks after the last fixes are checked in..

Stefan
  
-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From linuxbios at xdr.com  Thu Nov  6 10:21:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov  6 10:21:01 2003
Subject: [Fwd: NXTV's current linuxbios patch]
Message-ID: <200311061552.hA6FqojM026768@xdr.com>

>Hi,
>please, now that i get the patch ...can you tell me how to apply it.
>Tino.

The ability to apply patches is probably a reasonable prerequisite for
any hacking with freebios :^). But the posting was answering Ron's request
for the patch. The problem with my patch is it is like my own fork off of
an older version of freebios than what is available now. My patch would be
more for informational purposes, however it could be incorporated into the
freebios source in part or whole. I cut a few corners with my approach:
1) Cut and pasted some other spd/smbus code just to be able to view the DDR
spd contents. The actual ddr ram configuration is *not* done in this patch,
I left the code segments in hoping to study them and figure out how to do
it for the epia-m. Basically the code in the smbus.inc is a copy of code that
I found elsewhere in freebios. Right now it is just useless bloat.
2) I walk all over the CMOS ram contents just because I wanted a way to
carry over a version string from linuxbios to linux. Linuxbios compresses
everything so I couldn't easily scan the rom for a version string. There is
probably another way to address this problem. I just copied the version string
into the upper 128 bytes of the epia-m's cmos memory. I also use byte $0e of
cmos as a flag because I do a hard pci bus reset to get the system cleanly
setup. I need to keep track of whether I've already reset once so it doesn't
just endlessly reset.
3) The config file used to build the epia-m is built as part of an external
Makefile--I take the one inside the epia-m's directory and tack on a few
extra lines that say where the payload is. The payload is built in another
directory, based on etherboot code. This approach is foreign to freebios
but served our purposes. There is no toplevel Makefile in the normal freebios
tree.

The really critical code to consider bringing into freebios/epia-m is
A) VGA register init + setup
B) VGA bios stuff
C) VGA bios lockup fix, if an unacceptable INT is called, vga init is aborted.
D) Actual pci reset on startup to reset the pci card to known state. This
prevents lockups if the card is requesting an interrupt for example.
E) Code to access the smbus/SPD which is a starting point to auto config of DDR
F) VGA bios wants certain INT's implemented, these are implemented and seem to
be ok.
G) The pci firewire device comes up configured to respond to IO at 0 to 7f or
so, which means the cmos ram can't be accessed. This part has to be moved out
of the way. Normal pci configuration fixes this, but if you need to access
some other device at those io ports early on you need to move the pci firewire
device out of the way, this is a gotcha I had to get past.
H) Audio + usb irq's were not initialized properly.
I) The hardware status monitor was not initialized and activated.
J) Shadow ram for copying the vga bios over wasn't initialized
K) Shadow ram for vga bios wasn't write protected. Could be important.


That's about it. I don't know the status of epia-m freebios (not freebios2).
I don't know if vga is supported in the current CVS version, or any other
details.

-Dave


From gwatson at lanl.gov  Thu Nov  6 10:31:01 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Thu Nov  6 10:31:01 2003
Subject: config -> default
Message-ID: <p06010204bbd02126d38e@[10.0.1.2]>

Stefan,

Which builds are broken? I thought I checked all configurations built 
after the change (apart from the VIA which Ron was working on.) and 
modified any that had problems.

My hope was that this change would make the use of options more 
logical and consistent. The intention is that parts set default 
values for any options that they require or are specific to the part. 
Then when all the parts are put together in a target configuration 
file, these default values can be overridden for the specific build. 
I was also toying with the idea of allowing some options to be 
read-only, which I think would address your concern.

Apologies for breaking things. I try to build all targets after any 
change like this to make sure things are still working.

Greg

At 4:16 PM +0100 11/6/03, Stefan Reinauer wrote:
>Hi,
>
>most of the builds are broken again since "config" in the mainboard
>config file now has to be renamed to "default". On the one hand I see
>the reason for most of these changes, even though I am not sure if
>we want to suggest that some stuff can be overridden in the target
>config file, like:
>
>-option CONFIG_IOAPIC=1
>+default CONFIG_IOAPIC=1
>
>Can those changing elementary stuff like this that breaks all builds try
>to apply some regexps on the Config files so that other builds don't
>break? Getting further is somewhat hard currently since the code almost
>instantly breaks after the last fixes are checked in..
>
>Stefan
>
>--
>      Stefan Reinauer, SUSE LINUX AG
>Teamleader Architecture Development
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From peter.fox at aeroflex.com  Thu Nov  6 10:57:01 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Thu Nov  6 10:57:01 2003
Subject: How to use Filo as a payload ?
Message-ID: <NEBBJLECKKOPJEEKNGJOMEDLECAA.peter.fox@aeroflex.com>

I'm trying to get the STPC Elite development board to use
linuxbios with Filo, but after elfboot announces itself
the board reboots:

----------------------
.....
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2



LinuxBIOS-1.0.0 Thu Nov 6 16:13:37 GMT 2003 starting...
Copying LinuxBIOS to ram.
....
------------------------
My config file looks like this:

target /home/fox/build/freebios1/stpc
mainboard stpc/elite
biosbase 0xffff0000

option CONFIG_COMPRESS=0

option SERIAL_CONSOLE=1
option TTYS0_BAUD=38400
option DEFAULT_CONSOLE_LOGLEVEL=9
option DEBUG=1

# option ROM_IMAGE_SIZE=131072
option ROM_SIZE=131072
option USE_ELF_BOOT=1

option PAYLOAD_SIZE=65536
payload /home/fox/build/filo-0.4/filo.elf

Any ideas as to what I've missed ?

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200


From ts1 at tsn.or.jp  Thu Nov  6 11:13:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Thu Nov  6 11:13:01 2003
Subject: [Fwd: NXTV's current linuxbios patch]
In-Reply-To: <200311061552.hA6FqojM026768@xdr.com>
References: <200311061552.hA6FqojM026768@xdr.com>
Message-ID: <20031106164439.GA21065@tsn.or.jp>

On Thu, Nov 06, 2003 at 07:52:50AM -0800, Dave Ashley wrote:
> C) VGA bios lockup fix, if an unacceptable INT is called, vga init is aborted.

Similar functionality is already in the current CVS freebios tree.

> D) Actual pci reset on startup to reset the pci card to known state. This
> prevents lockups if the card is requesting an interrupt for example.

I like this idea.

Also I noticed hardwaremain() has the code to call hard_reset() 
when the boot_complete parameter is set, but I haven't figured out how
this parameter is set.
-- 
Takeshi


From ts1 at tsn.or.jp  Thu Nov  6 11:28:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Thu Nov  6 11:28:00 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <NEBBJLECKKOPJEEKNGJOMEDLECAA.peter.fox@aeroflex.com>
References: <NEBBJLECKKOPJEEKNGJOMEDLECAA.peter.fox@aeroflex.com>
Message-ID: <20031106165936.GB21065@tsn.or.jp>

On Thu, Nov 06, 2003 at 04:28:44PM -0000, Peter Fox wrote:
> I'm trying to get the STPC Elite development board to use
> linuxbios with Filo, but after elfboot announces itself
> the board reboots:

Maybe this item in filo/FAQ applies?

Q. LinuxBIOS (v1 tree) crashes or fails to verify checksum when booting FILO.
A. Make sure you are using the latest source of LinuxBIOS. It had a bug
   that interferes with checksum calculation, until recently.

-- 
Takeshi


From svante.signell at telia.com  Thu Nov  6 17:55:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Thu Nov  6 17:55:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <Pine.LNX.4.44.0311060710090.18852-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311060710090.18852-100000@maxroach.lanl.gov>
Message-ID: <1068161244.31620.53.camel@em2.my.own.domain>

On Thu, 2003-11-06 at 15:11, ron minnich wrote:
> On Thu, 6 Nov 2003, Svante Signell wrote:
> 
> > Sorry for taking up this thread again but now I have made a test of the
> > l2_cache activation code and have some further questions. 
> 
> you don't need this code any more. The last processor it mattered for is 
> long dead. I am not removing it but if you are having trouble then you 
> have a PII; do you?

No, I have a Pentium 2 1.3GHz Tualatin processor that works properly on other 
440BX-based main boards such as QDI BrillianX 1 and Compaq Presario 5670. I'm 
using a slot 1 to socket 370 converter, SLOT-T from Upgradeware for this CPU.
  
BTW: What do you mean by PIIs are long dead? I think _many_ people are
still using PIIs, especially with 400BX-based main boards. What I have
done is to extend the life of my old computers and their main boards by
exchanging the PIIs with PIIIs, specifically using Celeron2, with 1.4
GHz frequency (or 1.3GHz, since 1.4GHz versions are hard to find
currently).

Intel is phasing out these Celeron2s today, but compatible CPUs with
decent performance and clock frequencies are becoming available, e.g.
the VIA C3 Nehemiah, today at 1.2GHz. Versions up to 2GHz are coming
soon. Even SMP capable processors are in this years roadmap. Now we are
talking low power and cheap solutions (and maybe even fan-less). I plan
to use SMP-able processors from VIA for my currently problematic
motherboard when available.  The first step is to make things run with
one CPU. 

The motherboard is a dual CPU MSI-6120 with built-in SCSI interfaces. It
is currently equipped with two SMP-able PII-type Celerons (Mendocino)
300MHz at 468MHz. This motherboard have been working properly for four
years now and it would (in my opinion) be a big waste to throw it away.
I even consider to replace the problematic BIOS with a LinuxBIOS if the
problem is found not to be hardware related.

> > 4. You state that the L2 cache stuff is only needed for P2 CPUs, not for
> > P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron
> > 2 CPU (Tualatin), which is of P3 type. What if the BIOS does not
> > recognise the CPU and disables the L2 cache? People claim that AMI
> > BIOSes work this way. It the enabling code sufficient to make things
> > work.
> 
> which BIOS?

The BIOS is from AMI with version 2.0 (a6120v20.exe) supplied by MSI.

> > 5. If the slowness is not due to a disabled L2 cache (how to test this
> > properly btw?), can the  problems be solved by tying with the mtrr or
> > microcode update code? 
> 
> use lmbench to scope out your caches.

OK, I have now run lmbench on two boxes, one QDI box with a 1.4GHz
Celeron2 and the MSI-6120 with a 1.3GHz Celeron2, both with SLOT-T
adapters. How to find out where the bottleneck is, especially if the L2
cache is enabled or not? A lot of data is written on the log files. I'm
currently trying to find out what all numbers mean. One quick
observation though, the correctly working box is reported as: MHZ: 1409
MHz, 0.71 nanosec clock, while the problematic one is reported as: MHZ:
7 MHz, 142.86 nanosec clock. A factor of 200 in slowdown, welcome back
to the old 8086 clock speeds ;-)

> ron

Thanks,
Svante


From rminnich at lanl.gov  Thu Nov  6 23:32:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Nov  6 23:32:00 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1068161244.31620.53.camel@em2.my.own.domain>
Message-ID: <Pine.LNX.4.44.0311062203580.25908-100000@maxroach.lanl.gov>

Those lm bench memory tests with the plots of memory access times will 
show you l1, l2, and memory boundaries. 

ron



From svante.signell at telia.com  Fri Nov  7 02:09:00 2003
From: svante.signell at telia.com (Svante Signell)
Date: Fri Nov  7 02:09:00 2003
Subject: Level 2 cache activation code?
In-Reply-To: <Pine.LNX.4.21.0311060857120.935-100000@ucontrol.mobiledns.com>
References: <Pine.LNX.4.21.0311060857120.935-100000@ucontrol.mobiledns.com>
Message-ID: <1068190885.13114.11.camel@em2.my.own.domain>

Steven,

Thanks for the tip, I'll try adding this in. Preliminary estimations
with lmbench-2.0 shows like the problems are probably due to the missing
L2 cache. I'm currently compiling and running running lmbench-3, but
with an efficient speed of 7MHz instead of 1300MHz, things take time...

BTW: If one is picky, shouldn't the test be like if(res == -1)? The man
page of iopl says: 
On success, zero is returned.  On error, -1 is returned,  and  errno is
set appropriately. 
But of course, all values not equal to 0 means "true", right?


On Thu, 2003-11-06 at 14:59, steven james wrote:
> Greetings,
> 
> To run that code inside linux, you need to add a call to iopl to allow
> direct hardware access like:
> 
> res = iopl(3);
> if(res) {
> 	report_error();
> 	exit(-1);
> }
> 
> or something to that effect.
> G'day,
> sjames
> 
> 
> On Thu, 6 Nov 2003, Svante Signell wrote:
> 
> > Hi,
> > 
> > Sorry for taking up this thread again but now I have made a test of the
> > l2_cache activation code and have some further questions. 
> > 
> > The files put together to make things build are l2_cache.c, printk.c,
> > vsprintf.c, subr.c and corresponding header files from the linuxbios CVS
> > tree. For subr.c I had to add an include (#include <sys/io.h>) to get
> > outb defined for linking. The result so far is a segfault, in the
> > cache_enable() inline assembly routine in l2_cache.c)
> > 
> > 0. How to test this code after a _slow_ boot outside the BIOS? Is single
> > user mode sufficient, i.e. init 1?
> >  
> > 1. How are these printk statements supposed to work? Is the output
> > directed to some system logfile, like kern.log? How to define this
> > logfile etc. What to change if I want to log debug outputs to the
> > standard out and/or standard err? I don't find any output when running
> > the main program, neither in the system log files or on the screen. 
> > 
> > 2. Any special compiler and linker switches needed, like -nostdinc,
> > -nostdlib, -nostartfiles, etc? Your build system is Python based, right,
> > so I cannot easily look at Makefiles in the CVS tree.
> > 
> > 3. I found where the program halts with gdb and compiling with debug
> > set. One way to trace is single stepping in gdb etc. What is supposed to
> > happen when the DEBUG is defined in l2_cache.c?
> > 
> > 4. You state that the L2 cache stuff is only needed for P2 CPUs, not for
> > P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron
> > 2 CPU (Tualatin), which is of P3 type. What if the BIOS does not
> > recognise the CPU and disables the L2 cache? People claim that AMI
> > BIOSes work this way. It the enabling code sufficient to make things
> > work.
> > 
> > 5. If the slowness is not due to a disabled L2 cache (how to test this
> > properly btw?), can the  problems be solved by tying with the mtrr or
> > microcode update code? 
> > 
> > 6. Maybe the problem is still hardware related, like the on-board
> > voltage regulator for the CPU is not working properly, even if there are
> > no indications at all from the on board sensors. However, if the
> > problems are software related and can be solved, do you think it is
> > feasible to replace the AMI BIOS with LinuxBIOS? The probability of
> > getting an updated BIOS from MSI supporting Coppermine and Tualatin
> > processors is probably zero.
> > 
> > Thanks,
> > Svante 



From niki.waibel at newlogic.com  Fri Nov  7 04:56:00 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Fri Nov  7 04:56:00 2003
Subject: Help on config of "epia-m.config" file
In-Reply-To: <Pine.LNX.4.44.0311060714000.18852-100000@maxroach.lanl.gov>
Message-ID: <200311071027.hA7ARX84020352@enterprise2.newlogic.at>

>> > > - LinuxBios tell that the RAM is 127Mbye (and i had 256Mbyte)
>> >
>> >That's the hard coded part.
>> 
>> What is the file to edit ....to have 256Mbyte?
> 
> Just as a reminder, this is the only hardware on linuxbios that you "patch 
> a file" to get memory size, and we hope to fix this soon. The EPIA-M port 
> is not a good example!

the question was not answered.
i am interested in this too.

niki


From ts1 at tsn.or.jp  Fri Nov  7 05:50:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Fri Nov  7 05:50:00 2003
Subject: Help on config of "epia-m.config" file
In-Reply-To: <200311071027.hA7ARX84020352@enterprise2.newlogic.at>
References: <Pine.LNX.4.44.0311060714000.18852-100000@maxroach.lanl.gov> <200311071027.hA7ARX84020352@enterprise2.newlogic.at>
Message-ID: <20031107112212.GA26769@tsn.or.jp>

On Fri, Nov 07, 2003 at 11:27:33AM +0100, Niki Waibel wrote:
> >> > > - LinuxBios tell that the RAM is 127Mbye (and i had 256Mbyte)
> >> >
> >> >That's the hard coded part.
> >> 
> >> What is the file to edit ....to have 256Mbyte?
> > 
> > Just as a reminder, this is the only hardware on linuxbios that you "patch 
> > a file" to get memory size, and we hope to fix this soon. The EPIA-M port 
> > is not a good example!
> 
> the question was not answered.
> i am interested in this too.

Maybe I am wrong, because I don't have an EPIA-M, or the datasheet of the
northbridge.

There is code like this in freebios/src/northbridge/via/vt8623/raminit.inc:

        CS_WRITE($0x5a, $0x08)
        CS_WRITE($0x5b, $0x08)
        CS_WRITE($0x5c, $0x08)
        CS_WRITE($0x5d, $0x08)

Change all the 0x08's to 0x10 for 256MB, 0x20 for 512MB, etc.
If your DIMM is double-sided, halve the value of the first one.

Always test with memtest86 before running Linux, corrupt RAM
configuration may damage your filesystem.
-- 
Takeshi


From peter.fox at aeroflex.com  Fri Nov  7 05:59:00 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Fri Nov  7 05:59:00 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <20031106165936.GB21065@tsn.or.jp>
Message-ID: <NEBBJLECKKOPJEEKNGJOOEDOECAA.peter.fox@aeroflex.com>

I don't think it's that as I was using the cvs snapshot of
28-Oct-2003.

I was expecting elfboot to print something to say where it
was looking for the payload, at least, but it didn't...
I think that linuxbios can't find the payload, and was wondering
how it knew where to find it. I shall no doubt work it out
eventually, but was hoping for a quick pointer.

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200

  -----Original Message-----
  From: Takeshi Sone [mailto:ts1 at tsn.or.jp]
  Sent: 06 November 2003 17:00
  To: Peter Fox
  Cc: Linuxbios
  Subject: Re: How to use Filo as a payload ?
  
  
  On Thu, Nov 06, 2003 at 04:28:44PM -0000, Peter Fox wrote:
  > I'm trying to get the STPC Elite development board to use
  > linuxbios with Filo, but after elfboot announces itself
  > the board reboots:
  
  Maybe this item in filo/FAQ applies?
  
  Q. LinuxBIOS (v1 tree) crashes or fails to verify checksum when 
  booting FILO.
  A. Make sure you are using the latest source of LinuxBIOS. It had a bug
     that interferes with checksum calculation, until recently.
  
  -- 
  Takeshi


From ts1 at tsn.or.jp  Fri Nov  7 06:37:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Fri Nov  7 06:37:00 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <NEBBJLECKKOPJEEKNGJOOEDOECAA.peter.fox@aeroflex.com>
References: <20031106165936.GB21065@tsn.or.jp> <NEBBJLECKKOPJEEKNGJOOEDOECAA.peter.fox@aeroflex.com>
Message-ID: <20031107120912.GA28845@tsn.or.jp>

On Fri, Nov 07, 2003 at 11:30:02AM -0000, Peter Fox wrote:
> I don't think it's that as I was using the cvs snapshot of
> 28-Oct-2003.

Ok, the fix was committed at 2003/10/20.

> I was expecting elfboot to print something to say where it
> was looking for the payload, at least, but it didn't...

option DEFAULT_CONSOLE_LOGLEVEL=10
option MAXIMUM_CONSOLE_LOGLEVEL=10

> I think that linuxbios can't find the payload, and was wondering
> how it knew where to find it. I shall no doubt work it out
> eventually, but was hoping for a quick pointer.

option ZKERNEL_START=0xfffc0000

-- 
Takeshi


From pyro at linuxlabs.com  Fri Nov  7 09:10:00 2003
From: pyro at linuxlabs.com (steven james)
Date: Fri Nov  7 09:10:00 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1068190885.13114.11.camel@em2.my.own.domain>
Message-ID: <Pine.LNX.4.21.0311070939370.935-100000@ucontrol.mobiledns.com>

Greetings,

Yes, anything non 0 is true. Testing that way (or if(res<0) when the
function is to return a count) generally helps to catch wierdness (in the
bad old days, some functions returned -errno or even errno on error but
always 0 on success, this catches all of those cases).

G'day,
sjames



On Fri, 7 Nov 2003, Svante Signell wrote:

> Steven,
> 
> Thanks for the tip, I'll try adding this in. Preliminary estimations
> with lmbench-2.0 shows like the problems are probably due to the missing
> L2 cache. I'm currently compiling and running running lmbench-3, but
> with an efficient speed of 7MHz instead of 1300MHz, things take time...
> 
> BTW: If one is picky, shouldn't the test be like if(res == -1)? The man
> page of iopl says: 
> On success, zero is returned.  On error, -1 is returned,  and  errno is
> set appropriately. 
> But of course, all values not equal to 0 means "true", right?
> 
> 
> On Thu, 2003-11-06 at 14:59, steven james wrote:
> > Greetings,
> > 
> > To run that code inside linux, you need to add a call to iopl to allow
> > direct hardware access like:
> > 
> > res = iopl(3);
> > if(res) {
> > 	report_error();
> > 	exit(-1);
> > }
> > 
> > or something to that effect.
> > G'day,
> > sjames
> > 
> > 
> > On Thu, 6 Nov 2003, Svante Signell wrote:
> > 
> > > Hi,
> > > 
> > > Sorry for taking up this thread again but now I have made a test of the
> > > l2_cache activation code and have some further questions. 
> > > 
> > > The files put together to make things build are l2_cache.c, printk.c,
> > > vsprintf.c, subr.c and corresponding header files from the linuxbios CVS
> > > tree. For subr.c I had to add an include (#include <sys/io.h>) to get
> > > outb defined for linking. The result so far is a segfault, in the
> > > cache_enable() inline assembly routine in l2_cache.c)
> > > 
> > > 0. How to test this code after a _slow_ boot outside the BIOS? Is single
> > > user mode sufficient, i.e. init 1?
> > >  
> > > 1. How are these printk statements supposed to work? Is the output
> > > directed to some system logfile, like kern.log? How to define this
> > > logfile etc. What to change if I want to log debug outputs to the
> > > standard out and/or standard err? I don't find any output when running
> > > the main program, neither in the system log files or on the screen. 
> > > 
> > > 2. Any special compiler and linker switches needed, like -nostdinc,
> > > -nostdlib, -nostartfiles, etc? Your build system is Python based, right,
> > > so I cannot easily look at Makefiles in the CVS tree.
> > > 
> > > 3. I found where the program halts with gdb and compiling with debug
> > > set. One way to trace is single stepping in gdb etc. What is supposed to
> > > happen when the DEBUG is defined in l2_cache.c?
> > > 
> > > 4. You state that the L2 cache stuff is only needed for P2 CPUs, not for
> > > P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron
> > > 2 CPU (Tualatin), which is of P3 type. What if the BIOS does not
> > > recognise the CPU and disables the L2 cache? People claim that AMI
> > > BIOSes work this way. It the enabling code sufficient to make things
> > > work.
> > > 
> > > 5. If the slowness is not due to a disabled L2 cache (how to test this
> > > properly btw?), can the  problems be solved by tying with the mtrr or
> > > microcode update code? 
> > > 
> > > 6. Maybe the problem is still hardware related, like the on-board
> > > voltage regulator for the CPU is not working properly, even if there are
> > > no indications at all from the on board sensors. However, if the
> > > problems are software related and can be solved, do you think it is
> > > feasible to replace the AMI BIOS with LinuxBIOS? The probability of
> > > getting an updated BIOS from MSI supporting Coppermine and Tualatin
> > > processors is probably zero.
> > > 
> > > Thanks,
> > > Svante 
> 

-- 
-------------------------steven james, director of research, linux labs
... ........ ..... ....                    230 peachtree st nw ste 2701
the original linux labs                             atlanta.ga.us 30303
      -since 1995                              http://www.linuxlabs.com
                                   office 404.577.7747 fax 404.577.7743
-----------------------------------------------------------------------




From peter.fox at aeroflex.com  Mon Nov 10 03:51:01 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Mon Nov 10 03:51:01 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <20031107120912.GA28845@tsn.or.jp>
Message-ID: <NHBBJNOBEJCDFKDDBLLMIEAICIAA.peter.fox@aeroflex.com>

Thanks, but that didn't help. I've added some debug code, and it looks
like the payload stream is not set up - the stream->init()
call in elfboot.c blows up (reboots before seeing any printks
after the call to stream->init()).

The sources seem to imply the stream should be set up by the
linker script, but there is nothing in my linker script that
looks like it will do it.

Indeed looking at the linuxbios_c.map I see:

...
00008db8 T pc_keyboard_init
00008ec0 R epci_drivers
00008ec0 R estreams
00008ec0 R pci_drivers
00008ec0 R _rodata
00008ec0 R streams
00008ec0 T _etext
00009420 R intel_irq_routing_table
...

Which kind of implies there is no stream.

Any idea how the streams are supposed to be set up ?

I should have pointed out that my elite target is simply a clone
of the stpc consumer2 stuff, with all the VGA related bits
removed, at the moment.

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200

  -----Original Message-----
  From: Takeshi Sone [mailto:ts1 at tsn.or.jp]
  Sent: 07 November 2003 12:09
  To: Peter Fox
  Cc: Linuxbios
  Subject: Re: How to use Filo as a payload ?
  
  
  On Fri, Nov 07, 2003 at 11:30:02AM -0000, Peter Fox wrote:
  > I don't think it's that as I was using the cvs snapshot of
  > 28-Oct-2003.
  
  Ok, the fix was committed at 2003/10/20.
  
  > I was expecting elfboot to print something to say where it
  > was looking for the payload, at least, but it didn't...
  
  option DEFAULT_CONSOLE_LOGLEVEL=10
  option MAXIMUM_CONSOLE_LOGLEVEL=10
  
  > I think that linuxbios can't find the payload, and was wondering
  > how it knew where to find it. I shall no doubt work it out
  > eventually, but was hoping for a quick pointer.
  
  option ZKERNEL_START=0xfffc0000
  
  -- 
  Takeshi


From ts1 at tsn.or.jp  Mon Nov 10 04:06:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Mon Nov 10 04:06:00 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <NHBBJNOBEJCDFKDDBLLMIEAICIAA.peter.fox@aeroflex.com>
References: <20031107120912.GA28845@tsn.or.jp> <NHBBJNOBEJCDFKDDBLLMIEAICIAA.peter.fox@aeroflex.com>
Message-ID: <20031110093825.GA7101@tsn.or.jp>

On Mon, Nov 10, 2003 at 09:22:58AM -0000, Peter Fox wrote:
> The sources seem to imply the stream should be set up by the
> linker script, but there is nothing in my linker script that
> looks like it will do it.
> 
> Indeed looking at the linuxbios_c.map I see:
> 
> ...
> 00008db8 T pc_keyboard_init
> 00008ec0 R epci_drivers
> 00008ec0 R estreams
> 00008ec0 R pci_drivers
> 00008ec0 R _rodata
> 00008ec0 R streams
> 00008ec0 T _etext
> 00009420 R intel_irq_routing_table
> ...
> 
> Which kind of implies there is no stream.
> 
> Any idea how the streams are supposed to be set up ?

option USE_GENERIC_ROM=1
This will enable the rom_fill_inbuf.c and the rom_stream driver
will automagically show up in between the streams and estreams.

-- 
Takeshi


From stepan at suse.de  Mon Nov 10 06:22:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Nov 10 06:22:00 2003
Subject: (fwd) peer busses
Message-ID: <20031110115439.GD18620@suse.de>

Is this the same issue we were having with Linux not being able to see
bus 1?

  Stefan

----- Forwarded message from Matthew Wilcox <willy at debian.org> -----

Date: Sun, 9 Nov 2003 23:09:38 +0000
Subject: Re: PROBLEM: sym53c8xx is broken on HP LH 4 after Linux 2.2

On Sun, Nov 09, 2003 at 11:51:36AM -0500, Doug Ledford wrote:
> I can tell you what's going on here.  This is a 450NX based
> motherboard.  The 450NX chipset from Intel was the first chipset to
> have peer PCI busses.  For backwards compatibility, some machine
> makers hacked their PCI BIOS to have a fake bridge device on PCI bus 0
> that points to the same bus number as the peer bus.  This way if the
> OS didn't know about the peer bus registers it would still find the
> devices by scanning behind the bridge.
[..]
> In this case we are scanning behind this fake bridge and then also
> scanning based upon the peer bus registers in the chipset, and as a
> result we are finding the device twice.  In order to fix this problem
> you need to change the peer bus quirk code for the 450NX chipset to
> scan the list of bus 0 devices looking for a bridge that has the same
> config as the peer bus registers and if so delete the bridge from the
> list.  That will avoid double scanning and will avoid having the PCI
> code try and configure sub busses via a fake bridge when it should do
> all configurations via the 450NX peer bus registers.

Index: arch/i386/pci/fixup.c
===================================================================
RCS file: /var/cvs/linux-2.6/arch/i386/pci/fixup.c,v
retrieving revision 1.2
diff -u -p -r1.2 fixup.c
--- arch/i386/pci/fixup.c	12 Aug 2003 19:10:49 -0000	1.2
+++ arch/i386/pci/fixup.c	9 Nov 2003 23:07:17 -0000
@@ -6,27 +6,52 @@
 #include <linux/init.h>
 #include "pci.h"
 
+static void __devinit i450nx_scan_bus(struct pci_bus *parent, u8 busnr)
+{
+	struct list_head *tmp;
+
+	pci_scan_bus(busnr, &pci_root_ops, NULL);
+
+	list_for_each(tmp, &parent->children) {
+		u8 childnr;
+		struct pci_dev *dev = pci_dev_b(tmp);
+
+		if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
+			continue;
+		pci_read_config_byte(dev, PCI_PRIMARY_BUS, &childnr);
+		if (childnr != busnr)
+			continue;
+
+		printk(KERN_WARNING "PCI: Removing fake PCI bridge %s\n",
+				pci_name(dev));
+		pci_remove_bus_device(dev);
+		break;
+	}
+}
 
 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
 {
 	/*
 	 * i450NX -- Find and scan all secondary buses on all PXB's.
+	 * Some manufacturers added fake PCI-PCI bridges that also point
+	 * to the peer busses.  Look for them and delete them.
 	 */
 	int pxb, reg;
 	u8 busno, suba, subb;
 
-	printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
+	printk(KERN_NOTICE "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
 	reg = 0xd0;
-	for(pxb=0; pxb<2; pxb++) {
+	for (pxb = 0; pxb < 2; pxb++) {
 		pci_read_config_byte(d, reg++, &busno);
 		pci_read_config_byte(d, reg++, &suba);
 		pci_read_config_byte(d, reg++, &subb);
 		DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
 		if (busno)
-			pci_scan_bus(busno, &pci_root_ops, NULL);	/* Bus A */
+			i450nx_scan_bus(d->bus, busno);		/* Bus A */
 		if (suba < subb)
-			pci_scan_bus(suba+1, &pci_root_ops, NULL);	/* Bus B */
+			i450nx_scan_bus(d->bus, suba+1);	/* Bus B */
 	}
+
 	pcibios_last_bus = -1;
 }
 
----- End forwarded message -----
  
-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From peter.fox at aeroflex.com  Mon Nov 10 06:44:00 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Mon Nov 10 06:44:00 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <20031110093825.GA7101@tsn.or.jp>
Message-ID: <NHBBJNOBEJCDFKDDBLLMAEAJCIAA.peter.fox@aeroflex.com>

Thanks ! That's the one. I now get the FILO startup banner,
but then it reboots.

-----------------
...
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

Stream pointer is 0x00009020    34:init_bytes() - zkernel_start:0xfffe0000
zker
nel_mask:0x0000ffff
Stream initialised ok
Stream header read ok
Found ELF candiate at offset 0
header_offset is 0
Try to load at offset 0x0
malloc Enter, size 32, free_mem_ptr 00011768
malloc 0x00011768
New segment addr 0x100000 size 0x218b0 offset 0xa0 filesize 0x7920
(cleaned up) New segment addr 0x100000 size 0x218b0 offset 0xa0 filesize
0x7920
lb: [0x0000000000004000, 0x000000000005136c)
malloc Enter, size 32, free_mem_ptr 00011788
malloc 0x00011788
New segment addr 0x1218c0 size 0x60 offset 0x79c0 filesize 0x60
(cleaned up) New segment addr 0x1218c0 size 0x60 offset 0x79c0 filesize 0x60
lb: [0x0000000000004000, 0x000000000005136c)
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000218b0 filesz:
0x00
00000000007920
[ 0x0000000000100000, 0000000000107920, 0x00000000001218b0) <-
00000000000000a0
Clearing Segment: addr: 0x0000000000107920 memsz: 0x0000000000019f90
Loading Segment: addr: 0x00000000001218c0 memsz: 0x0000000000000060 filesz:
0x00
00000000000060
[ 0x00000000001218c0, 0000000000121920, 0x0000000000121920) <-
00000000000079c0
Loaded segments
verified segments
closed down stream
Jumping to boot code at 0x1053d0
entry    = 0x001053d0
lb_start = 0x00004000
lb_size  = 0x0004d36c
adjust   = 0x01faec94
buffer   = 0x01f65928
     elf_boot_notes = 0x0000b100
adjusted_boot_notes = 0x01fb9d94
FILO version 0.4 (fox at stpc.ifr.co.uk) Thu Nov  6 14:25:29 GMT 2003


LinuxBIOS-1.0.0 Mon Nov 10 09:52:46 GMT 2003 starting...
Copying LinuxBIOS to ram.
...
---------------------
I'm turning on debugging in Filo to see why. Here's the result..
---------------------
...
FILO version 0.4 (fox at stpc.ifr.co.uk) Mon Nov 10 12:04:52 GMT 2003
collect_sys_info: boot eax = 0xe1fb007
collect_sys_info: boot ebx = 0x1fb9d94
collect_sys_info: boot arg = 0x1fb9d94
malloc_diag: alloc: 0 bytes (0 blocks), free: 16376 bytes (1 blocks)
malloc_diag: alloc: 24 bytes (1 blocks), free: 16352 bytes (1 blocks)
collect_elfboot_info: Bootloader: elfboot
collect_elfboot_info: Version: 1.2
malloc_diag: alloc: 40 bytes (2 blocks), free: 16336 bytes (1 blocks)
collect_linuxbios_info: Searching for LinuxBIOS tables...
find_lb_table: Found canidate at: 00000500
find_lb_table: header checksum o.k.
find_lb_table: table checksum o.k.
find_lb_table: record count o.k.
collect_linuxbios_info: Found LinuxBIOS table at: 00000500
malloc_diag: alloc: 96 bytes (3 blocks), free: 16280 bytes (1 blocks)
convert_memmap: 0x00000000000000 0x000000000006d0 16
convert_memmap: 0x000000000006d0 0x0000000009f930 1
convert_memmap: 0x00000000100000 0x00000001f00000 1
collect_sys_info: 00000000000006d0-00000000000a0000
collect_sys_info: 0000000000100000-0000000002000000
collect_sys_info: RAM 32 MB
relocate: Current location: 0x100000-0x123fdf
relocate: Relocating to 0x1fdc020-0x1ffffff... ok


LinuxBIOS-1.0.0 Mon Nov 10 12:08:12 GMT 2003 starting...
Copying LinuxBIOS to ram.
...

--
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200

  -----Original Message-----
  From: Takeshi Sone [mailto:ts1 at tsn.or.jp]
  Sent: 10 November 2003 09:38
  To: Peter Fox
  Cc: Linuxbios
  Subject: Re: How to use Filo as a payload ?


  On Mon, Nov 10, 2003 at 09:22:58AM -0000, Peter Fox wrote:
  > The sources seem to imply the stream should be set up by the
  > linker script, but there is nothing in my linker script that
  > looks like it will do it.
  >
  > Indeed looking at the linuxbios_c.map I see:
  >
  > ...
  > 00008db8 T pc_keyboard_init
  > 00008ec0 R epci_drivers
  > 00008ec0 R estreams
  > 00008ec0 R pci_drivers
  > 00008ec0 R _rodata
  > 00008ec0 R streams
  > 00008ec0 T _etext
  > 00009420 R intel_irq_routing_table
  > ...
  >
  > Which kind of implies there is no stream.
  >
  > Any idea how the streams are supposed to be set up ?

  option USE_GENERIC_ROM=1
  This will enable the rom_fill_inbuf.c and the rom_stream driver
  will automagically show up in between the streams and estreams.

  --
  Takeshi



From ts1 at tsn.or.jp  Mon Nov 10 06:55:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Mon Nov 10 06:55:01 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <NHBBJNOBEJCDFKDDBLLMAEAJCIAA.peter.fox@aeroflex.com>
References: <20031110093825.GA7101@tsn.or.jp> <NHBBJNOBEJCDFKDDBLLMAEAJCIAA.peter.fox@aeroflex.com>
Message-ID: <20031110122728.GA12469@tsn.or.jp>

On Mon, Nov 10, 2003 at 12:16:11PM -0000, Peter Fox wrote:
> relocate: Current location: 0x100000-0x123fdf
> relocate: Relocating to 0x1fdc020-0x1ffffff... ok
> 
> 
> LinuxBIOS-1.0.0 Mon Nov 10 12:08:12 GMT 2003 starting...
> Copying LinuxBIOS to ram.

Does your CPU have RDTSC instruction?
FILO uses it for timing.

-- 
Takeshi


From peter.fox at aeroflex.com  Mon Nov 10 07:13:00 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Mon Nov 10 07:13:00 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <20031110122728.GA12469@tsn.or.jp>
Message-ID: <NHBBJNOBEJCDFKDDBLLMKEAJCIAA.peter.fox@aeroflex.com>

I don't think so. It is the 486 core in an stpc elite.
It just claims Industry standard 486 compatibility.

In their published instruction set summary, which
appears to be in alphabetical order, there is
RCR, then REP INS.

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200

  -----Original Message-----
  From: Takeshi Sone [mailto:ts1 at tsn.or.jp]
  Sent: 10 November 2003 12:27
  To: Peter Fox
  Cc: Linuxbios
  Subject: Re: How to use Filo as a payload ?
  
  
  On Mon, Nov 10, 2003 at 12:16:11PM -0000, Peter Fox wrote:
  > relocate: Current location: 0x100000-0x123fdf
  > relocate: Relocating to 0x1fdc020-0x1ffffff... ok
  > 
  > 
  > LinuxBIOS-1.0.0 Mon Nov 10 12:08:12 GMT 2003 starting...
  > Copying LinuxBIOS to ram.
  
  Does your CPU have RDTSC instruction?
  FILO uses it for timing.
  
  -- 
  Takeshi


From ts1 at tsn.or.jp  Mon Nov 10 07:27:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Mon Nov 10 07:27:00 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <NHBBJNOBEJCDFKDDBLLMKEAJCIAA.peter.fox@aeroflex.com>
References: <20031110122728.GA12469@tsn.or.jp> <NHBBJNOBEJCDFKDDBLLMKEAJCIAA.peter.fox@aeroflex.com>
Message-ID: <20031110130013.GA13990@tsn.or.jp>

On Mon, Nov 10, 2003 at 12:45:27PM -0000, Peter Fox wrote:
> I don't think so. It is the 486 core in an stpc elite.
> It just claims Industry standard 486 compatibility.
> 
> In their published instruction set summary, which
> appears to be in alphabetical order, there is
> RCR, then REP INS.

Maybe RDTSC causes invalid opcode exception, and since there is no
exception handler, the CPU resets.

filo/i386/timer.c must be re-written to support pre-Pentium CPUs.
-- 
Takeshi


From peter.fox at aeroflex.com  Mon Nov 10 09:58:01 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Mon Nov 10 09:58:01 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <20031110130013.GA13990@tsn.or.jp>
Message-ID: <NHBBJNOBEJCDFKDDBLLMCEAKCIAA.peter.fox@aeroflex.com>

That's it.

I hacked together a new timer.c based on freebios/src/pc80/udelay_timer2.c

You may want to offer it as an alternative, but then again, maybe not.

I can now boot linux using filo !

Thanks for all your help.

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200

  -----Original Message-----
  From: Takeshi Sone [mailto:ts1 at tsn.or.jp]
  Sent: 10 November 2003 13:00
  To: Peter Fox
  Cc: Linuxbios
  Subject: Re: How to use Filo as a payload ?
  
  
  On Mon, Nov 10, 2003 at 12:45:27PM -0000, Peter Fox wrote:
  > I don't think so. It is the 486 core in an stpc elite.
  > It just claims Industry standard 486 compatibility.
  > 
  > In their published instruction set summary, which
  > appears to be in alphabetical order, there is
  > RCR, then REP INS.
  
  Maybe RDTSC causes invalid opcode exception, and since there is no
  exception handler, the CPU resets.
  
  filo/i386/timer.c must be re-written to support pre-Pentium CPUs.
  -- 
  Takeshi
-------------- next part --------------
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From ts1 at tsn.or.jp  Mon Nov 10 11:07:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Mon Nov 10 11:07:01 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <NHBBJNOBEJCDFKDDBLLMCEAKCIAA.peter.fox@aeroflex.com>
References: <20031110130013.GA13990@tsn.or.jp> <NHBBJNOBEJCDFKDDBLLMCEAKCIAA.peter.fox@aeroflex.com>
Message-ID: <20031110163958.GA19827@tsn.or.jp>

On Mon, Nov 10, 2003 at 03:30:20PM -0000, Peter Fox wrote:
> I hacked together a new timer.c based on freebios/src/pc80/udelay_timer2.c
> 
> You may want to offer it as an alternative, but then again, maybe not.

Thanks a lot.
I will incorporate this code in the future release of FILO.

-- 
Takeshi


From steve at nexpath.com  Mon Nov 10 11:30:01 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Mon Nov 10 11:30:01 2003
Subject: How to use Filo as a payload ?
In-Reply-To: <NHBBJNOBEJCDFKDDBLLMCEAKCIAA.peter.fox@aeroflex.com>
References: <NHBBJNOBEJCDFKDDBLLMCEAKCIAA.peter.fox@aeroflex.com>
Message-ID: <3FAFC6AA.2010506@nexpath.com>

Peter Fox wrote:

> I hacked together a new timer.c based on freebios/src/pc80/udelay_timer2.c
> You may want to offer it as an alternative, but then again, maybe not.
> I can now boot linux using filo !

I was following this thread, and I meant to mention this earlier, but 
figured that it was not the issue.   None of the stpc versions AFAIK 
have the TSC, as you quickly discovered, and it resets if you reference 
any of these instructions.

-Steve



From a.nielsen at optushome.com.au  Thu Nov 13 01:39:01 2003
From: a.nielsen at optushome.com.au (Adam Nielsen)
Date: Thu Nov 13 01:39:01 2003
Subject: Questions about LinuxBIOS
Message-ID: <200311131712.14052@korath>

Hi,

I've been keeping an eye on the LinuxBIOS project for a while now, and I've 
recently got hold of a couple of old motherboards I'd like to use with 
LinuxBIOS.  I realise there will probably be quite a bit of work involved 
with getting them going, but I'd just like to check I'm on the right track 
first!

I've read through all the FAQs, and I have a few questions:

Since none of the boards have on-board networking, I'd really like to use 
LinuxBIOS to enable them to boot Linux over the network with a standard PCI 
network card - it seems possible, but there doesn't seem to be anywhere that 
gives a definite 'yes' to this with standard PC hardware.

Once LinuxBIOS is compiled and ready to go, Is it possible to flash it into 
the board's existing BIOS?  (Without any hardware modifications, ZIF sockets, 
etc.)

One of the motherboards has a recovery jumper which can be used to reflash the 
BIOS if there was a problem during a flash operation, do you think this could 
be used as a backup option in case something goes wrong with LinuxBIOS?  
(yes, I'm aware of all the dangers etc., but the boards only cost me $1 each 
so I'm not too worried if I render them unusable, it'll just be a bit of a 
waste...)

The reason I ask is that the flash chip on one of the boards is soldered on 
and physically very small.  I did get hold of a BIOS upgrade for it though, 
and the BIOS code itself appears to be supplied as four 64K files - is this 
large enough?

Sorry if my questions are very basic, I'm new to all this ;-)

Thanks,
Adam.



From sc at flagen.com  Thu Nov 13 03:00:01 2003
From: sc at flagen.com (David Hendricks)
Date: Thu Nov 13 03:00:01 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <200311131712.14052@korath>
References: <200311131712.14052@korath>
Message-ID: <20031113013352.08e492be.sc@flagen.com>

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> Since none of the boards have on-board networking, I'd really like to use 
> LinuxBIOS to enable them to boot Linux over the network with a standard PCI 
> network card - it seems possible, but there doesn't seem to be anywhere that 
> gives a definite 'yes' to this with standard PC hardware.

Yes. A variety of NICs can be used with Etherboot as your payload. Get etherboot, go into the src directory, make allelfs, and use the appropriate elf or bzipped elf (zelf) as your LinuxBIOS payload.

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> Once LinuxBIOS is compiled and ready to go, Is it possible to flash it into 
> the board's existing BIOS?  (Without any hardware modifications, ZIF sockets, 
> etc.)

Yes, but you'll lose your original BIOS. And since nothing is quite foolproof, it would be unwise to risk permanently losing your original BIOS. Unless you have another mainboard with a compatible ROM socket that you can use to recover your old BIOS in case LinuxBIOS fails, I would highly recommend that you get a BIOS Savior or a backup flash part before proceding.

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> One of the motherboards has a recovery jumper which can be used to reflash the 
> BIOS if there was a problem during a flash operation, do you think this could 
> be used as a backup option in case something goes wrong with LinuxBIOS?  
> (yes, I'm aware of all the dangers etc., but the boards only cost me $1 each 
> so I'm not too worried if I render them unusable, it'll just be a bit of a 
> waste...)

No, the recovery jumper will program some factory presets into a factory BIOS. It does not act as a recovery BIOS. 

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> The reason I ask is that the flash chip on one of the boards is soldered on 
> and physically very small.

Oh, then disregard what I said about getting a backup. Unless you switch projects and get a board with a removable ROM, of course :)

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> I did get hold of a BIOS upgrade for it though, 
> and the BIOS code itself appears to be supplied as four 64K files - is this 
> large enough?

LinuxBIOS will usually fit in a quarter meg ROM. 

Can you provide some more details about this specific board? Knowing the north/south bridge chipset would be most helpful in case Ron has easy answers for you.


From sc at flagen.com  Thu Nov 13 03:08:01 2003
From: sc at flagen.com (David Hendricks)
Date: Thu Nov 13 03:08:01 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <200311131712.14052@korath>
References: <200311131712.14052@korath>
Message-ID: <20031113014144.22be731d.sc@flagen.com>

My apologies for the spam, looks like I forgot to tell Sylpheed to word
wrap before sending a message. I hope this proves to be more readable,
otherwise I'll have to RTFM :(

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> Since none of the boards have on-board networking, I'd really like to
> use LinuxBIOS to enable them to boot Linux over the network with a
> standard PCI network card - it seems possible, but there doesn't seem
> to be anywhere that gives a definite 'yes' to this with standard PC
> hardware.

Yes. A variety of NICs can be used with Etherboot as your payload. Get
etherboot, go into the src directory, make allelfs, and use the
appropriate elf or bzipped elf (zelf) as your LinuxBIOS payload.

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> Once LinuxBIOS is compiled and ready to go, Is it possible to flash it
> into the board's existing BIOS?  (Without any hardware modifications,
> ZIF sockets, etc.)

Yes, but you'll lose your original BIOS. And since nothing is quite
foolproof, it would be unwise to risk permanently losing your original
BIOS. Unless you have another mainboard with a compatible ROM socket
that you can use to recover your old BIOS in case LinuxBIOS fails, I
would highly recommend that you get a BIOS Savior or a backup flash part
before proceding.

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> One of the motherboards has a recovery jumper which can be used to
> reflash the BIOS if there was a problem during a flash operation, do
> you think this could be used as a backup option in case something goes
> wrong with LinuxBIOS?  (yes, I'm aware of all the dangers etc., but
> the boards only cost me $1 each so I'm not too worried if I render
> them unusable, it'll just be a bit of a waste...)

No, the recovery jumper will program some factory presets into a factory
BIOS. It does not act as a recovery BIOS. 

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> The reason I ask is that the flash chip on one of the boards is
> soldered on and physically very small.

Oh, then disregard what I said about getting a backup. Unless you switch
projects and get a board with a removable ROM, of course :)

On Thu, 13 Nov 2003 17:12:13 +1000
Adam Nielsen <a.nielsen at optushome.com.au> wrote:
> I did get hold of a BIOS upgrade for it though, 
> and the BIOS code itself appears to be supplied as four 64K files - is
> this large enough?

LinuxBIOS will usually fit in a quarter meg ROM. 

Can you provide some more details about this specific board? Knowing the
north/south bridge chipset would be most helpful in case Ron has easy
answers for you.


From a.nielsen at optushome.com.au  Thu Nov 13 04:30:01 2003
From: a.nielsen at optushome.com.au (Adam Nielsen)
Date: Thu Nov 13 04:30:01 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <20031113014144.22be731d.sc@flagen.com>
References: <200311131712.14052@korath> <20031113014144.22be731d.sc@flagen.com>
Message-ID: <200311132003.27487@korath>

Thanks for your reply, it was most helpful!

> Yes. A variety of NICs can be used with Etherboot as your payload.

Oh good, I was hoping that would be the case ;-)

You mention booting Windows 2000 on the web site, does this mean it would be 
possible to boot other OSes such as DOS?  It seems that it would be possible, 
except that a lot of BIOS calls DOS uses haven't been implemented yet - if 
these were implemented, would that be enough to boot DOS?

> > One of the motherboards has a recovery jumper
> No, the recovery jumper will program some factory presets into a factory
> BIOS. It does not act as a recovery BIOS.

Are you sure?  I'm not talking about the CMOS reset jumper - all the docs I've 
read about this feature say that can be used to recover from a failed flash 
attempt, as it contains the bare minimum code needed to boot a floppy (which 
then courtesy of AUTOEXEC.BAT runs the flash program.)  The docs say to wait 
for a certain series of beeps to indicate the flash was successful (as there 
is no video.)  From this description it seems that if I have a properly 
configured disk handy, then should the new LinuxBIOS decide not to work, I 
should be able to recover by reflashing my original BIOS.  When I last tried 
enabling the jumper, as soon as the motherboard powered up it started reading 
the floppy drive, continously (as I had no disk in there) until it was 
powered off again.

The only thing I remember reading was something about the BIOS boot block 
never being overwritten during an upgrade, so if the LinuxBIOS flash 
procedure does overwrite the boot block I guess this procedure wouldn't work.

And for what it's worth, I've only ever seen this on Intel motherboards (which 
have soldered flash chips.)

> Oh, then disregard what I said about getting a backup. Unless you switch
> projects and get a board with a removable ROM, of course :)

I actually have two boards, and one of them does have a removable ROM so 
that's ok ;-)  It actually seems to be quite similar to the Gigabyte GA-6BXC, 
which it seems you used to use (I have one of these boards too, but not for 
fiddling with ;-))

> Can you provide some more details about this specific board? Knowing the
> north/south bridge chipset would be most helpful in case Ron has easy
> answers for you.

Yes, I didn't want to bombard you with too much stuff the first time ;-)

Board 1: Unknown brand, P6LX-A+.

According to the manual it has an "Intel 82440LX (PAC)" and an "Intel 82371AB 
(PIIX4)".  It's running a Celeron 300A at the moment.  Googling for "P6LX-A+" 
is where I found most of the info.  I haven't seen any references to 440LX, 
but I'm somewhat hopeful on the PIIX4...  This board has a pretty standard 
socketed BIOS chip (seems the same physically as the GA-6BXC.)

Board 2: Intel, unknown model.

This is definitely an Intel board (looks like an Intel, has an Intel AA model 
number [AA 666761-205], etc.) but according to Intel it doesn't exist - I 
think that's because it's sold through Gateway - the BIOS comes up with a 
"Gateway 2000" logo, and the only info I could find was on Gateway's website.  
Information on the board itself is a little sketchy but it seems fairly 
modern for its time - it's only a P133, but it's ATX and uses SDRAM.  
Googling for "MBDSAC071AAWW" gives a little info about it.  I can't find a 
manual, so I'll just list some of the larger chips I can see... ;-)

Intel PCIset SB82437VX
Intel PCIset SB82371SB
Intel E28F002 \n BCT80 \n U7050566D (this is the surface mounted flash chip)
SMC FDC37C932FR

Hopefully that's enough for you to tell me there's no support for this one
yet ;-)

Thanks,
Adam.



From pyro at linuxlabs.com  Thu Nov 13 08:16:00 2003
From: pyro at linuxlabs.com (steven james)
Date: Thu Nov 13 08:16:00 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <200311132003.27487@korath>
References: <200311131712.14052@korath> <20031113014144.22be731d.sc@flagen.com>
 <200311132003.27487@korath>
Message-ID: <Pine.LNX.4.58.0311130846071.29752@ucontrol.mobiledns.com>

Greetings,

The unfortunate thing about most BIOS recovery jumpers is that they are
simple GPIO inputs, meaning the boot block has to read a regisetr and
decide what to do. Naturally, that means that the boot block must not be
the part that needs recovery.

They COULD have that jumper actually toggle an address so that a true
backup boot block is used, but they don't. To make matters worse, some of
those same boards have a chipset with that feature built in, but that is
left unconnected and the rescue jumper is wired to GPIO instead.
</soapbox>

G'day,
sjames


-------------------------steven james, director of research, linux labs
... ........ ..... ....                    230 peachtree st nw ste 2701
the original linux labs                             atlanta.ga.us 30303
      -since 1995                              http://www.linuxlabs.com
                                   office 404.577.7747 fax 404.577.7743
-----------------------------------------------------------------------


On Thu, 13 Nov 2003, Adam Nielsen wrote:

> Thanks for your reply, it was most helpful!
>
> > Yes. A variety of NICs can be used with Etherboot as your payload.
>
> Oh good, I was hoping that would be the case ;-)
>
> You mention booting Windows 2000 on the web site, does this mean it would be
> possible to boot other OSes such as DOS?  It seems that it would be possible,
> except that a lot of BIOS calls DOS uses haven't been implemented yet - if
> these were implemented, would that be enough to boot DOS?
>
> > > One of the motherboards has a recovery jumper
> > No, the recovery jumper will program some factory presets into a factory
> > BIOS. It does not act as a recovery BIOS.
>
> Are you sure?  I'm not talking about the CMOS reset jumper - all the docs I've
> read about this feature say that can be used to recover from a failed flash
> attempt, as it contains the bare minimum code needed to boot a floppy (which
> then courtesy of AUTOEXEC.BAT runs the flash program.)  The docs say to wait
> for a certain series of beeps to indicate the flash was successful (as there
> is no video.)  From this description it seems that if I have a properly
> configured disk handy, then should the new LinuxBIOS decide not to work, I
> should be able to recover by reflashing my original BIOS.  When I last tried
> enabling the jumper, as soon as the motherboard powered up it started reading
> the floppy drive, continously (as I had no disk in there) until it was
> powered off again.
>
> The only thing I remember reading was something about the BIOS boot block
> never being overwritten during an upgrade, so if the LinuxBIOS flash
> procedure does overwrite the boot block I guess this procedure wouldn't work.
>
> And for what it's worth, I've only ever seen this on Intel motherboards (which
> have soldered flash chips.)
>
> > Oh, then disregard what I said about getting a backup. Unless you switch
> > projects and get a board with a removable ROM, of course :)
>
> I actually have two boards, and one of them does have a removable ROM so
> that's ok ;-)  It actually seems to be quite similar to the Gigabyte GA-6BXC,
> which it seems you used to use (I have one of these boards too, but not for
> fiddling with ;-))
>
> > Can you provide some more details about this specific board? Knowing the
> > north/south bridge chipset would be most helpful in case Ron has easy
> > answers for you.
>
> Yes, I didn't want to bombard you with too much stuff the first time ;-)
>
> Board 1: Unknown brand, P6LX-A+.
>
> According to the manual it has an "Intel 82440LX (PAC)" and an "Intel 82371AB
> (PIIX4)".  It's running a Celeron 300A at the moment.  Googling for "P6LX-A+"
> is where I found most of the info.  I haven't seen any references to 440LX,
> but I'm somewhat hopeful on the PIIX4...  This board has a pretty standard
> socketed BIOS chip (seems the same physically as the GA-6BXC.)
>
> Board 2: Intel, unknown model.
>
> This is definitely an Intel board (looks like an Intel, has an Intel AA model
> number [AA 666761-205], etc.) but according to Intel it doesn't exist - I
> think that's because it's sold through Gateway - the BIOS comes up with a
> "Gateway 2000" logo, and the only info I could find was on Gateway's website.
> Information on the board itself is a little sketchy but it seems fairly
> modern for its time - it's only a P133, but it's ATX and uses SDRAM.
> Googling for "MBDSAC071AAWW" gives a little info about it.  I can't find a
> manual, so I'll just list some of the larger chips I can see... ;-)
>
> Intel PCIset SB82437VX
> Intel PCIset SB82371SB
> Intel E28F002 \n BCT80 \n U7050566D (this is the surface mounted flash chip)
> SMC FDC37C932FR
>
> Hopefully that's enough for you to tell me there's no support for this one
> yet ;-)
>
> Thanks,
> Adam.
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From mirenna at mi.ingv.it  Thu Nov 13 09:22:00 2003
From: mirenna at mi.ingv.it (Santi Mirenna)
Date: Thu Nov 13 09:22:00 2003
Subject: Help on epia-m 10000 linuxbios VGA
Message-ID: <5.1.1.6.2.20031113155011.02a051f0@10.1.1.8>

Hi to all,
today i make EPIA-M 10000 rom image.
i compile to have VGA and Filo, after apply patch of  Dave Ashley
and info from Takeshi about RAM ammount
VGA now is found by the system but ....
In attach you have the output log ....


Can someone tell me where i wrong?

**********************************************************************************************
  Santi Mirenna
  INGV - Istituto Nazionale di Geofisica e Vulcanologia
  Sezione di Milano
  via Bassini 15, 20133 Milano, Italy
  tel. +39-02-23699278
  fax +39-02-23699458
  e mail: santi.mirenna at mi.ingv.it
  **********************************************************************************************
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From linuxbios at xdr.com  Thu Nov 13 11:11:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 13 11:11:01 2003
Subject: Help on epia-m 10000 linuxbios VGA
Message-ID: <200311131644.hADGiJvk017258@xdr.com>

>  Santi Mirenna
>In attach you have the output log ....
>Can someone tell me where i wrong?

You haven't applied all the patch, specifically the handler for the
unsupported bios interrupts. This is the bug where it just gets into an
endless loop of bios interrupts, so the program needs to exit the
bios somehow.

-Dave


From rsmith at bitworks.com  Thu Nov 13 11:34:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Thu Nov 13 11:34:00 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <200311132003.27487@korath>
References: <200311131712.14052@korath> <20031113014144.22be731d.sc@flagen.com> <200311132003.27487@korath>
Message-ID: <3FB3BA30.9070604@bitworks.com>

Adam Nielsen wrote:

> 
> Board 1: Unknown brand, P6LX-A+.
> 
> 
> Board 2: Intel, unknown model.
> 

Hook a cdrom up to the board and boot something like Morphix or Knoppix 
and then do a lspci -v.  That will tell us exactly what chipsets are on 
the board.


-- 
Richard A. Smith
rsmith at bitworks.com




From rogerxxmaillist at speakeasy.net  Thu Nov 13 15:04:01 2003
From: rogerxxmaillist at speakeasy.net (Roger)
Date: Thu Nov 13 15:04:01 2003
Subject: Recommended Motherboards to use w/ Linuxbios List
Message-ID: <1068755802.2596.5.camel@localhost3.localdomain>

One piece of data missing from the linuxbios status page (listing of
compatible motherboards), is a "recommended motherboards" section to use
with linuxbios.

It seems that some features of motherboards do not work fully currently
(ie vga, etc), and this data does not look to be fully documented on the
status page.

Basically, I'm planning on building a box for my parents to use
explicitly for email/web (rather then relying windowsxp virus prone
o/s).

I want to stick with the Intel cpu, however, per your recommendation, I
will sway to amd (although i currently have all intel cpu's with source
already complied for intel x86).

To make it simple, should i just buy a (intel) mobo from cwlinux?

-- 

Roger
http://www.speakeasy.net/~rogerxx/index.html



From xpegenaute at telepolis.es  Thu Nov 13 15:56:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Thu Nov 13 15:56:01 2003
Subject: LinuxBios + etherboot 5.0.11
Message-ID: <1068758948.2619.33.camel@p-133>

Hi,

now i'd like to try with etherboot, i just compiled bin32/via-rhine.elf
modifying the Config file like the FAQ of LinuxBios.

I put it like a payload but id does'nt work, just reboot.

The config file of linuxbios is the example.

And the output is this:
----------------------------------------------------------
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    37:init_bytes() - zkernel_start:0xfff00000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x94000 size 0x7188 offset 0x80 filesize 0x3680
(cleaned up) New segment addr 0x94000 size 0x7188 offset 0x80 filesize
0x3680
Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007188
filesz: 0x0000000000003680
Clearing Segment: addr: 0x0000000000097680 memsz: 0x0000000000003b08
Jumping to boot code at 0x94000
ROM segment 0xfdc4 length 0xfffe reloc 0x9400
Etherboot 5.0.11 (GPL) ELF for [VIA 86C100]
Boot from (N)etwork or from (L)ocal? 0

LinuxBIOS-1.0.0 Wed Nov 12 14:02:46 CET 2003 starting...
-----------------------------------------------------------

The 0 after (L)ocal? is just the start of reboot, is there any way to
debug in etherboot? I have'nt seen nothing about.

Some hint?

Thanks a lot.
Xavi.
PD: Changing etherboot by Filo works perfectly.



From stepan at suse.de  Thu Nov 13 16:24:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Nov 13 16:24:01 2003
Subject: LinuxBios + etherboot 5.0.11
In-Reply-To: <1068758948.2619.33.camel@p-133>
References: <1068758948.2619.33.camel@p-133>
Message-ID: <20031113215719.GA10927@suse.de>

* Xavier Pegenaute <xpegenaute at telepolis.es> [031113 22:29]:
> now i'd like to try with etherboot, i just compiled bin32/via-rhine.elf
> modifying the Config file like the FAQ of LinuxBios.
> 
> I put it like a payload but id does'nt work, just reboot.

Have you removed the -DPC_BIOS and replaced it with -DLINUXBIOS befroe
compiling etherboot? Have you tried a more recent version? i.e. 5.2

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From linuxbios at xdr.com  Thu Nov 13 16:26:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 13 16:26:00 2003
Subject: LinuxBios + etherboot 5.0.11
Message-ID: <200311132159.hADLxcGK018374@xdr.com>

>Boot from (N)etwork or from (L)ocal? 0

This is a bug in etherboot, it is getting a divide by zero error.
As I recall it was related to etherboot trying to use the normal pc bios
to get the current time, and the time isn't changing, so you get a divide
by zero or some such. Don't know if it is a bug or a configuration
setting.

Actually I dug deeper and found a patch to etherboot 5.0.10 that we're
using. In src/timer.c in the function currticks that doesn't just have
a single return, add this line:
 {
 	unsigned long clocks_high, clocks_low;
 	unsigned long currticks;
+setup_timers();
 	/* Read the Time Stamp Counter */
 	rdtsc(clocks_low, clocks_high);

The CONFIG_TSC_CURRTICKS seems to be related in some way.

-Dave


From riskin at esinosoft.com  Thu Nov 13 22:08:01 2003
From: riskin at esinosoft.com (riskin at esinosoft.com)
Date: Thu Nov 13 22:08:01 2003
Subject: LinuxBIOS and ISA slot on PCChips M787CL M/B
Message-ID: <200311140307.hAE370e14845@nwn.definitive.org>

Hello ron,

I am migrating LinuxBIOS from vt5426 to PCChips M787CL(
NB: VT8601 ,SB: VT82C686B),and I want to use ISA slot.I
think that LinuxBIOS doesn't need to initialize ISA slot,
the devices on ISA bus should work,but I am wrong.So
does LinuxBIOS need to  initialize the ISA slot?

Any advice is appreciated!

riskin


From rogerxxmaillist at speakeasy.net  Thu Nov 13 22:26:01 2003
From: rogerxxmaillist at speakeasy.net (Roger)
Date: Thu Nov 13 22:26:01 2003
Subject: Recommended Motherboards to use w/ Linuxbios List
Message-ID: <1068782366.10921.0.camel@localhost3.localdomain>

One piece of data missing from the linuxbios status page (listing of
compatible motherboards), is a "recommended motherboards" section to use
with linuxbios.

It seems that some features of motherboards do not work fully currently
(ie vga, etc), and this data does not look to be fully documented on the
status page.

Basically, I'm planning on building a box for my parents to use
explicitly for email/web (rather then relying windowsxp virus prone
o/s).

I want to stick with the Intel cpu, however, per your recommendation, I
will sway to amd (although i currently have all intel cpu's with source
already complied for intel x86).

To make it simple, should i just buy a (intel) mobo from cwlinux?

-- 

Roger
http://www.speakeasy.net/~rogerxx/index.html



From a.nielsen at optushome.com.au  Fri Nov 14 00:48:01 2003
From: a.nielsen at optushome.com.au (Adam Nielsen)
Date: Fri Nov 14 00:48:01 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <3FB3BA30.9070604@bitworks.com>
References: <200311131712.14052@korath> <200311132003.27487@korath> <3FB3BA30.9070604@bitworks.com>
Message-ID: <200311141621.38539@korath>

> Hook a cdrom up to the board and boot something like Morphix or Knoppix 
> and then do a lspci -v.  That will tell us exactly what chipsets are on 
> the board.

Ok, well it's easier for me to network boot Slackware (via an etherboot 
floppy), so this is what the first board says:  (P6LX-A+)

00:00.0 Host bridge: Intel Corp. 440LX/EX - 82443LX/EX Host bridge (rev 03)
00:01.0 PCI bridge: Intel Corp. 440LX/EX - 82443LX/EX AGP bridge (rev 03)
00:07.0 ISA bridge: Intel Corp. 82371AB/EB/MB PIIX4 ISA (rev 02)
00:07.1 IDE interface: Intel Corp. 82371AB/EB/MB PIIX4 IDE (rev 01)
00:07.2 USB Controller: Intel Corp. 82371AB/EB/MB PIIX4 USB (rev 01)
00:07.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02)
00:0a.0 VGA compatible controller: S3 Inc. 86c764/765 [Trio32/64/64V+] (rev 
43)
00:0c.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone] (rev 
24)

The last two items in the list are PCI cards.  I've yet to do the P133 board, 
but I think this one has the most chance of working.  I've attached the lspci 
-v output.

Thanks,
Adam.
-------------- next part --------------
00:00.0 Host bridge: Intel Corp. 440LX/EX - 82443LX/EX Host bridge (rev 03)
	Flags: bus master, medium devsel, latency 64
	Memory at e0000000 (32-bit, prefetchable) [size=64M]
	Capabilities: [a0] AGP version 1.0

00:01.0 PCI bridge: Intel Corp. 440LX/EX - 82443LX/EX AGP bridge (rev 03) (prog-if 00 [Normal decode])
	Flags: bus master, 66Mhz, medium devsel, latency 64
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=64
	I/O behind bridge: 0000d000-0000dfff

00:07.0 ISA bridge: Intel Corp. 82371AB/EB/MB PIIX4 ISA (rev 02)
	Flags: bus master, medium devsel, latency 0

00:07.1 IDE interface: Intel Corp. 82371AB/EB/MB PIIX4 IDE (rev 01) (prog-if 80 [Master])
	Flags: bus master, medium devsel, latency 64
	I/O ports at f000 [size=16]

00:07.2 USB Controller: Intel Corp. 82371AB/EB/MB PIIX4 USB (rev 01) (prog-if 00 [UHCI])
	Flags: bus master, medium devsel, latency 64, IRQ 10
	I/O ports at e000 [size=32]

00:07.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02)
	Flags: medium devsel, IRQ 9

00:0a.0 VGA compatible controller: S3 Inc. 86c764/765 [Trio32/64/64V+] (rev 43) (prog-if 00 [VGA])
	Flags: medium devsel, IRQ 12
	Memory at e4000000 (32-bit, non-prefetchable) [size=64M]
	Expansion ROM at e8000000 [disabled] [size=64K]

00:0c.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone] (rev 24)
	Subsystem: 3Com Corporation 3C905B Fast Etherlink XL 10/100
	Flags: bus master, medium devsel, latency 64, IRQ 10
	I/O ports at e400 [size=128]
	Memory at ea000000 (32-bit, non-prefetchable) [size=128]
	Expansion ROM at e9000000 [disabled] [size=128K]
	Capabilities: [dc] Power Management version 1


From svante.signell at telia.com  Fri Nov 14 01:13:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Fri Nov 14 01:13:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <Pine.LNX.4.21.0311070939370.935-100000@ucontrol.mobiledns.com>
References: <Pine.LNX.4.21.0311070939370.935-100000@ucontrol.mobiledns.com>
Message-ID: <1068792379.10185.14.camel@em2.my.own.domain>

I still do get a segfault when trying to activate the L2 cache, in the
cache_enable() inline assembly routine in l2_cache.c Anything else
neeeded to run this program inside GNU/Linux 

On Fri, 2003-11-07 at 15:42, steven james wrote:
> Greetings,
> 
> Yes, anything non 0 is true. Testing that way (or if(res<0) when the
> function is to return a count) generally helps to catch wierdness (in the
> bad old days, some functions returned -errno or even errno on error but
> always 0 on success, this catches all of those cases).
> 
> G'day,
> sjames
> 
> 
> On Thu, 2003-11-06 at 14:59, steven james wrote:
> > Greetings,
> > 
> > To run that code inside linux, you need to add a call to iopl to
allow
> > direct hardware access like:
> > 
> > res = iopl(3);
> > if(res) {
> >     report_error();
> >     exit(-1);
> > }
> > 
> > or something to that effect.
> > G'day,
> > sjames
> > 
> On Fri, 7 Nov 2003, Svante Signell wrote:
> 
> > Steven,
> > 
> > Thanks for the tip, I'll try adding this in. Preliminary estimations
> > with lmbench-2.0 shows like the problems are probably due to the missing
> > L2 cache. I'm currently compiling and running running lmbench-3, but
> > with an efficient speed of 7MHz instead of 1300MHz, things take time...
> > 
...
> > > > 5. If the slowness is not due to a disabled L2 cache (how to test this
> > > > properly btw?), can the  problems be solved by tying with the mtrr or
> > > > microcode update code? 
> > > > 
> > > > 6. Maybe the problem is still hardware related, like the on-board
> > > > voltage regulator for the CPU is not working properly, even if there are
> > > > no indications at all from the on board sensors. However, if the
> > > > problems are software related and can be solved, do you think it is
> > > > feasible to replace the AMI BIOS with LinuxBIOS? The probability of
> > > > getting an updated BIOS from MSI supporting Coppermine and Tualatin
> > > > processors is probably zero.
> > > > 
> > > > Thanks,
> > > > Svante 
> > 


From ijpriya at hotmail.com  Fri Nov 14 01:24:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Fri Nov 14 01:24:01 2003
Subject: Physical address mapping for Flash and SDRAM?
Message-ID: <BAY2-F115klMyLkEtpg00005b0c@hotmail.com>

Hi,


I am with sc1200. I like to use linuxbios. With linuxbios what is the 
physical address mapping for Flash memory and SDRAM? What part of the 
codings should I look into get more details.

Regards,
Johncy.

_________________________________________________________________
BharatMatrimony.com. http://www.bharatmatrimony.com/cgi-bin/bmclicks1.cgi?74 
India's premium matrimonial website.



From svante.signell at telia.com  Fri Nov 14 01:53:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Fri Nov 14 01:53:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <Pine.LNX.4.44.0311062203580.25908-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311062203580.25908-100000@maxroach.lanl.gov>
Message-ID: <1068794815.10185.57.camel@em2.my.own.domain>

Hi,

I have now run the lmbench3-0-a3 tests. For the correctly working 1.4
GHz Tualatin CPU the latency numbers shows jumps from 2ns to 6ns at 16k
array size and from 6ns to 120ns at 265k array size. I assume this
indicates correctly working level 1 and 2 caches. 

For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
around 400ns independent of array size. The only thing changig is that
the latency numbers increase to 440-460ns for large values of the
stride. My interpretation is that not even the L1 cache is working
properly. All other tests indicate a _very_ slow CPU, around 7MHz is
measured by lmbench (BTW how good is this value?)  compared to the
expected 1.3GHz. Two questions immediately arise.

1. Is this slowness reasonable if _no- caches are working properly?
2. If there is a problem with the on-chip voltage regulator and the CPU
clock speed is really 7MHz, as measured by lmbench, can the CPU operate
properly at this low speed. I thought there was a _lower_ limit as well
as an upper limit for the operating frequency?

Svante
 
On Fri, 2003-11-07 at 06:04, ron minnich wrote:
> Those lm bench memory tests with the plots of memory access times will 
> show you l1, l2, and memory boundaries. 
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios


From ts1 at tsn.or.jp  Fri Nov 14 02:08:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Fri Nov 14 02:08:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1068794815.10185.57.camel@em2.my.own.domain>
References: <Pine.LNX.4.44.0311062203580.25908-100000@maxroach.lanl.gov> <1068794815.10185.57.camel@em2.my.own.domain>
Message-ID: <20031114074118.GA12499@tsn.or.jp>

On Fri, Nov 14, 2003 at 08:26:55AM +0100, Svante Signell wrote:
> For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
> around 400ns independent of array size. The only thing changig is that
> the latency numbers increase to 440-460ns for large values of the
> stride. My interpretation is that not even the L1 cache is working
> properly. All other tests indicate a _very_ slow CPU, around 7MHz is
> measured by lmbench (BTW how good is this value?)  compared to the
> expected 1.3GHz. Two questions immediately arise.
> 
> 1. Is this slowness reasonable if _no- caches are working properly?
> 2. If there is a problem with the on-chip voltage regulator and the CPU
> clock speed is really 7MHz, as measured by lmbench, can the CPU operate
> properly at this low speed. I thought there was a _lower_ limit as well
> as an upper limit for the operating frequency?

What do these commands say?

    cat /proc/mtrr
    cat /proc/cpuinfo

-- 
Takeshi


From zuencap at yahoo.com  Fri Nov 14 02:32:00 2003
From: zuencap at yahoo.com (Erdem Guven)
Date: Fri Nov 14 02:32:00 2003
Subject: sis645dx
Message-ID: <20031114080512.42431.qmail@web41510.mail.yahoo.com>

Hi,
I want to run linuxbios on a sis645dx board. I think
there is no support for this chipset.
Can someone give me some advice about:
- compatibility with sis630 or other supported
chipsets
- Is it a good option to copy necessary parts from
original bios and past into linuxbios?

Regards


=====
Erdem G?ven
erdemus


__________________________________
Do you Yahoo!?
Protect your identity with Yahoo! Mail AddressGuard
http://antispam.yahoo.com/whatsnewfree


From stuge-linuxbios at cdy.org  Fri Nov 14 07:17:01 2003
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Fri Nov 14 07:17:01 2003
Subject: sis645dx
In-Reply-To: <20031114080512.42431.qmail@web41510.mail.yahoo.com>
References: <20031114080512.42431.qmail@web41510.mail.yahoo.com>
Message-ID: <20031114124443.GB19072@foo.birdnet.se>

On Fri, Nov 14, 2003 at 12:05:12AM -0800, Erdem Guven wrote:
> Hi,
> I want to run linuxbios on a sis645dx board. I think
> there is no support for this chipset.
> Can someone give me some advice about:
> - compatibility with sis630 or other supported
> chipsets

No idea about this one.


> - Is it a good option to copy necessary parts from
> original bios and past into linuxbios?

Absolutely not, since the original BIOS is not likely something you have the
right to duplicate, and even less put under the GPL. Please don't send us
code (disassembly) from it either. You are however more than welcome to
contribute fresh code that you've written yourself and put under the GPL,
that will get the chipset running. Look at the existing code for SiS
chipsets and start comparing datasheets, would be my suggestion to get it to
work.


//Peter


From xpegenaute at telepolis.es  Fri Nov 14 09:11:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Fri Nov 14 09:11:01 2003
Subject: ELF binaries
Message-ID: <1068821064.3532.7.camel@p-133>

Hi,

is there any document of how to generate ELF binaries of programs made
by myself runnable by LinuxBios,Filo,Etherboto loading ELF binaries ?

For example:
LinuxBios + myprogram, or
LinuxBios + Filo + myprogram_from_dsk or
LinuxBios + etherboot + myprogram_from_X

I was looking something in dietlibc but at the moment it does'nt work.


Xavi.
PD: I know it has to be static and stripped



From rminnich at lanl.gov  Fri Nov 14 09:37:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 14 09:37:00 2003
Subject: LinuxBIOS and ISA slot on PCChips M787CL M/B
In-Reply-To: <200311140341.hAE3fb8g023955@mailproxy2.lanl.gov>
Message-ID: <Pine.LNX.4.44.0311140809160.10505-100000@maxroach.lanl.gov>

On Fri, 14 Nov 2003 riskin at esinosoft.com wrote:

> I am migrating LinuxBIOS from vt5426 to PCChips M787CL( NB: VT8601 ,SB:
> VT82C686B),and I want to use ISA slot.I think that LinuxBIOS doesn't
> need to initialize ISA slot, the devices on ISA bus should work,but I am
> wrong.So does LinuxBIOS need to initialize the ISA slot?

You actually can't do much with that slot. ISA is a mess. There is no way 
for linuxbios to do anything because there are no configuration registers 
to read in ISA to help configure. So I am not sure what you should do.

ron



From rminnich at lanl.gov  Fri Nov 14 09:37:30 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 14 09:37:30 2003
Subject: Recommended Motherboards to use w/ Linuxbios List
In-Reply-To: <1068782366.10921.0.camel@localhost3.localdomain>
Message-ID: <Pine.LNX.4.44.0311140810370.10505-100000@maxroach.lanl.gov>

The easiest path to linuxbios is to buy a mobo from somebody who supports 
it. Right now, in lots of one, that means Tyan or cwlinux.com

ron



From rminnich at lanl.gov  Fri Nov 14 09:48:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 14 09:48:01 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <200311141621.38539@korath>
Message-ID: <Pine.LNX.4.44.0311140821400.10505-100000@maxroach.lanl.gov>

I don't think we ever did an LX northbridge. It should be similar to the 
TX I think. You might want to go for it.

ron



From stuge-linuxbios at cdy.org  Fri Nov 14 09:51:01 2003
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Fri Nov 14 09:51:01 2003
Subject: LinuxBIOS and ISA slot on PCChips M787CL M/B
In-Reply-To: <Pine.LNX.4.44.0311140809160.10505-100000@maxroach.lanl.gov>
References: <200311140341.hAE3fb8g023955@mailproxy2.lanl.gov> <Pine.LNX.4.44.0311140809160.10505-100000@maxroach.lanl.gov>
Message-ID: <20031114151828.GE19072@foo.birdnet.se>

On Fri, Nov 14, 2003 at 08:10:13AM -0700, ron minnich wrote:
> On Fri, 14 Nov 2003 riskin at esinosoft.com wrote:
> 
> > I am migrating LinuxBIOS from vt5426 to PCChips M787CL( NB: VT8601 ,SB:
> > VT82C686B),and I want to use ISA slot.I think that LinuxBIOS doesn't
> > need to initialize ISA slot, the devices on ISA bus should work,but I am
> > wrong.So does LinuxBIOS need to initialize the ISA slot?
> 
> You actually can't do much with that slot. ISA is a mess. There is no way 
> for linuxbios to do anything because there are no configuration registers 
> to read in ISA to help configure. So I am not sure what you should do.

The slot can't be configured, but the ISA bridge is on the PCI bus and thus
configurable. If it's configured appropriately at least the ISA bus will be
active. Whatever card is put in there will need further configuration
however, and that's not really standardized. There are two common ways that
I know of to do it, but neither is very good.
One is scanning for extension ROMs, card ROMs may need a full PC BIOS.
The other is ISA PnP that uses a couple of reserved ports for allocating
resources to the cards. Linux can do Plug-and-Play configuration in kernel
and in userspace.


//Peter


From rminnich at lanl.gov  Fri Nov 14 09:52:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 14 09:52:00 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1068794815.10185.57.camel@em2.my.own.domain>
Message-ID: <Pine.LNX.4.44.0311140824070.10505-100000@maxroach.lanl.gov>

On Fri, 14 Nov 2003, Svante Signell wrote:

> I have now run the lmbench3-0-a3 tests. For the correctly working 1.4
> GHz Tualatin CPU the latency numbers shows jumps from 2ns to 6ns at 16k
> array size and from 6ns to 120ns at 265k array size. I assume this
> indicates correctly working level 1 and 2 caches. 

yes.

> For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
> around 400ns independent of array size. The only thing changig is that
> the latency numbers increase to 440-460ns for large values of the
> stride. My interpretation is that not even the L1 cache is working
> properly. All other tests indicate a _very_ slow CPU, around 7MHz is
> measured by lmbench (BTW how good is this value?)  compared to the
> expected 1.3GHz. Two questions immediately arise.

weird. I have no idea what's going on here. Something is really wrong.

ron



From tyson at irobot.com  Fri Nov 14 10:32:00 2003
From: tyson at irobot.com (tyson at irobot.com)
Date: Fri Nov 14 10:32:00 2003
Subject: Level 2 cache activation code?
In-Reply-To: <Pine.LNX.4.44.0311140824070.10505-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311140824070.10505-100000@maxroach.lanl.gov>
Message-ID: <3FB4FD47.7010608@irobot.com>

ron minnich wrote:
> On Fri, 14 Nov 2003, Svante Signell wrote:
> 
> 
>>I have now run the lmbench3-0-a3 tests. For the correctly working 1.4
>>GHz Tualatin CPU the latency numbers shows jumps from 2ns to 6ns at 16k
>>array size and from 6ns to 120ns at 265k array size. I assume this
>>indicates correctly working level 1 and 2 caches. 
> 
> 
> yes.
> 
> 
>>For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
>>around 400ns independent of array size. The only thing changig is that
>>the latency numbers increase to 440-460ns for large values of the
>>stride. My interpretation is that not even the L1 cache is working
>>properly. All other tests indicate a _very_ slow CPU, around 7MHz is
>>measured by lmbench (BTW how good is this value?)  compared to the
>>expected 1.3GHz. Two questions immediately arise.
> 
> 
> weird. I have no idea what's going on here. Something is really wrong.

I don't think I can comment with much precision here, but...

My early experience with disabled cache is that the system gets REALLY 
slow.  PIII's (I  think) will read a full cache line for every word it 
needs.  That means that if you have a 32 byte cache line and read the 
entire line one 32 bit word at a time (8 accesses) the PIII will read 
that entire cache line 8 times, one for each word access.  This may 
apply only to code fetches.

It gets really rediculous when this is happening while executing code 
over the ISA bus (from ROM).

Cheers!
Ty

-- 
Tyson D Sawyer                             iRobot Corporation
Senior Systems Engineer                    Military Systems Division
tsawyer at irobot.com                         Robots for the Real World
603-654-3400 ext 206                       http://www.irobot.com



From gwatson at lanl.gov  Fri Nov 14 11:30:01 2003
From: gwatson at lanl.gov (Greg Watson)
Date: Fri Nov 14 11:30:01 2003
Subject: SC03
Message-ID: <p06010210bbdabade60b2@[10.0.1.2]>

If any LinuxBIOS'ers are planning to attend Supercomputing'03 in 
Phoenix next week, please drop by the LANL booth. Ron, Ollie and I 
will be there with various bits and pieces of hardware to look at, 
and it would be great to meet some of you in person. If there is 
enough interest, we could even have an informal BOF.

Cheers,

Greg


From rminnich at lanl.gov  Fri Nov 14 11:35:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 14 11:35:01 2003
Subject: Welcome to Ollie Lo
Message-ID: <Pine.LNX.4.44.0311141006330.10943-100000@maxroach.lanl.gov>

Ollie Lo is now working at LANL in the ACL with our team. We're very happy
to have him here. His email is not quite up yet but as Greg mentioned, you
can come by the LANL booth at SC '03 and say hello.

For those more recent joiners to this list, Ollie was one of the very 
early participants in LinuxBIOS and helped us get it working on the SiS 
chipsets; Ollie also came up with the idea of using DoC for LinuxBIOS.

Welcome Ollie!

ron



From stepan at suse.de  Fri Nov 14 12:01:23 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Fri Nov 14 12:01:23 2003
Subject: ELF binaries
In-Reply-To: <1068821064.3532.7.camel@p-133>
References: <1068821064.3532.7.camel@p-133>
Message-ID: <20031114173502.GB13660@suse.de>

* Xavier Pegenaute <xpegenaute at telepolis.es> [031114 15:44]:
> is there any document of how to generate ELF binaries of programs made
> by myself runnable by LinuxBios,Filo,Etherboto loading ELF binaries ?
 
The binary has to be self contained, i.e use no external services. And
it needs a defined entry point.. Stack setup and similar things are
wishful but not necessary iirc.

> For example:
> LinuxBios + myprogram, or
> LinuxBios + Filo + myprogram_from_dsk or
> LinuxBios + etherboot + myprogram_from_X
> 
> I was looking something in dietlibc but at the moment it does'nt work.
  
dietlibc will probably not work since it uses system calls..

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From joshua at joshuawise.com  Fri Nov 14 14:24:01 2003
From: joshua at joshuawise.com (Joshua Wise)
Date: Fri Nov 14 14:24:01 2003
Subject: Welcome to Ollie Lo
In-Reply-To: <Pine.LNX.4.44.0311141006330.10943-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311141006330.10943-100000@maxroach.lanl.gov>
Message-ID: <200311141457.27786.joshua@joshuawise.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On Friday 14 November 2003 12:08 pm, ron minnich wrote:
> Welcome Ollie!

Always good to have more people on board :) Welcome Ollie!

> ron
/j

- -- 
Joshua Wise | www.joshuawise.com
GPG Key     | 0xEA80E0B3
Quote       | <lilo> I akilled *@* by mistake
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.2 (GNU/Linux)

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=9bL3
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From svante.signell at telia.com  Fri Nov 14 16:12:00 2003
From: svante.signell at telia.com (Svante Signell)
Date: Fri Nov 14 16:12:00 2003
Subject: Level 2 cache activation code?
In-Reply-To: <20031114074118.GA12499@tsn.or.jp>
References: <Pine.LNX.4.44.0311062203580.25908-100000@maxroach.lanl.gov>
	 <1068794815.10185.57.camel@em2.my.own.domain>
	 <20031114074118.GA12499@tsn.or.jp>
Message-ID: <1068846360.10203.63.camel@em2.my.own.domain>

On Fri, 2003-11-14 at 08:41, Takeshi Sone wrote:
> On Fri, Nov 14, 2003 at 08:26:55AM +0100, Svante Signell wrote:
> > For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
> > around 400ns independent of array size. The only thing changig is that
> > the latency numbers increase to 440-460ns for large values of the
> > stride. My interpretation is that not even the L1 cache is working
> > properly. All other tests indicate a _very_ slow CPU, around 7MHz is
> > measured by lmbench (BTW how good is this value?)  compared to the
> > expected 1.3GHz. Two questions immediately arise.
> > 
> > 1. Is this slowness reasonable if _no- caches are working properly?
> > 2. If there is a problem with the on-chip voltage regulator and the CPU
> > clock speed is really 7MHz, as measured by lmbench, can the CPU operate
> > properly at this low speed. I thought there was a _lower_ limit as well
> > as an upper limit for the operating frequency?
> 
> What do these commands say?
> 
>     cat /proc/mtrr
>     cat /proc/cpuinfo
Normal output: 1.4GHz Tualatin 
cat/proc/mtrr:
reg00: base=0x00000000 (   0MB), size= 256MB: write-back, count=1
reg01: base=0xe4000000 (3648MB), size=   8MB: write-combining, count=1

# Faulty system:
cat /proc/mtrr
cat: /proc/mtrr: No such file or directory

Faulty system:
$ cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 11
model name      : Intel(R) Celeron(TM) CPU                1300MHz
stepping        : 4
cpu MHz         : 1340.197
cache size      : 256 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 mmx fxsr sse
bogomips        : 2641.10



From ijpriya at hotmail.com  Sat Nov 15 08:00:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Sat Nov 15 08:00:01 2003
Subject: Instruction set?
Message-ID: <BAY2-F132Zec08cD0Wx0000b4a1@hotmail.com>

Hi,

       What instruction set should i follow if I have to look into the 
source code of linuxbios assembly programming?

_________________________________________________________________
Access Hotmail from your mobile now. 
http://server1.msn.co.in/sp03/mobilesms/ Click here.



From ts1 at tsn.or.jp  Sat Nov 15 11:43:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Sat Nov 15 11:43:00 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1068846360.10203.63.camel@em2.my.own.domain>
References: <Pine.LNX.4.44.0311062203580.25908-100000@maxroach.lanl.gov> <1068794815.10185.57.camel@em2.my.own.domain> <20031114074118.GA12499@tsn.or.jp> <1068846360.10203.63.camel@em2.my.own.domain>
Message-ID: <20031115171649.GA24521@tsn.or.jp>

On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
> # Faulty system:
> cat /proc/mtrr
> cat: /proc/mtrr: No such file or directory

I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
(MTRR is the registers that tell CPU where to cache)

-- 
Takeshi


From ts1 at tsn.or.jp  Sat Nov 15 11:56:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Sat Nov 15 11:56:01 2003
Subject: ELF binaries
In-Reply-To: <20031114173502.GB13660@suse.de>
References: <1068821064.3532.7.camel@p-133> <20031114173502.GB13660@suse.de>
Message-ID: <20031115173006.GB24521@tsn.or.jp>

On Fri, Nov 14, 2003 at 06:35:02PM +0100, Stefan Reinauer wrote:
> * Xavier Pegenaute <xpegenaute at telepolis.es> [031114 15:44]:
> > is there any document of how to generate ELF binaries of programs made
> > by myself runnable by LinuxBios,Filo,Etherboto loading ELF binaries ?
>  
> The binary has to be self contained, i.e use no external services. And
> it needs a defined entry point.. Stack setup and similar things are
> wishful but not necessary iirc.
> 
> > For example:
> > LinuxBios + myprogram, or
> > LinuxBios + Filo + myprogram_from_dsk or
> > LinuxBios + etherboot + myprogram_from_X
> > 
> > I was looking something in dietlibc but at the moment it does'nt work.
>   
> dietlibc will probably not work since it uses system calls..

newlib might be used as a start point to build a libc replacement
for environment without OS.

However, the quick way I think is to use freebios/util/baremetal
or modifying FILO.  

I once tried to build an MP3 player inside BIOS, by modifying FILO.
It succeeded to play an MP3 file from hard disk in 3-4 seconds from reset.
-- 
Takeshi


From rminnich at lanl.gov  Sat Nov 15 14:21:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Nov 15 14:21:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <20031115171649.GA24521@tsn.or.jp>
Message-ID: <Pine.LNX.4.44.0311151253520.8662-100000@maxroach.lanl.gov>

On Sun, 16 Nov 2003, Takeshi Sone wrote:

> On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
> > # Faulty system:
> > cat /proc/mtrr
> > cat: /proc/mtrr: No such file or directory
> 
> I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
> (MTRR is the registers that tell CPU where to cache)


no, even if bios does not set mtrr, those registers exist, and are 
readable. Something weird is going on here!

ron
is going on here. 



From jarcher at pobox.com  Sat Nov 15 19:33:00 2003
From: jarcher at pobox.com (Jordan Archer)
Date: Sat Nov 15 19:33:00 2003
Subject: ROM section
Message-ID: <5.2.1.1.2.20031115165837.00b3bd80@cybermorph.com>

I'm trying to understand the relationship of these defines in freebios2

	ROM_IMAGE_SIZE
	ROM_SECTION_OFFSET
	ROM_SECTION_SIZE
	ROM_SIZE
	FALLBACK_SIZE
	PAYLOAD_SIZE

Jordan



From svante.signell at telia.com  Sun Nov 16 04:40:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Sun Nov 16 04:40:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <Pine.LNX.4.44.0311151253520.8662-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311151253520.8662-100000@maxroach.lanl.gov>
Message-ID: <1068977645.10203.76.camel@em2.my.own.domain>

I did boot another kernel and for that kernel there was one entry for
mtrr, so this seems to work. However, now I have tried executing both
the mtrr and cache activation code, and when coming to any inline
assembly code the program exits with a segfault :( All commented out
calls have been tried one after the other by single-stepping with gdb. 

Below is the main progam I used:

#include <mem.h>
main()
{
  struct mem_range mem;
  int res = iopl(3);
  if(res) {error();exit(-1);}
  //  cache_enable();
  //  p6_configure_l2_cache();
  cache_on(mem);
}
 
On Sat, 2003-11-15 at 20:54, ron minnich wrote:
> On Sun, 16 Nov 2003, Takeshi Sone wrote:
> 
> > On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
> > > # Faulty system:
> > > cat /proc/mtrr
> > > cat: /proc/mtrr: No such file or directory
> > 
> > I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
> > (MTRR is the registers that tell CPU where to cache)
> 
> 
> no, even if bios does not set mtrr, those registers exist, and are 
> readable. Something weird is going on here!
> 
> ron
> is going on here. 
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios


From niki.waibel at newlogic.com  Mon Nov 17 03:27:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Nov 17 03:27:01 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
Message-ID: <200311170900.hAH90j84010136@enterprise2.newlogic.at>

any chance to get /dev/ttyS1 (/dev/tts/1) working with freebios
on the emia-m?

(i need it for the smartcardreader ...)

niki


From rminnich at lanl.gov  Mon Nov 17 09:48:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov 17 09:48:00 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
In-Reply-To: <200311170900.hAH90j84010136@enterprise2.newlogic.at>
Message-ID: <Pine.LNX.4.44.0311170821390.1085-100000@maxroach.lanl.gov>

On Mon, 17 Nov 2003, Niki Waibel wrote:

> any chance to get /dev/ttyS1 (/dev/tts/1) working with freebios
> on the emia-m?
> 
> (i need it for the smartcardreader ...)

as soon as we get epia-m up under v2.

ron



From jarcher at pobox.com  Mon Nov 17 10:07:00 2003
From: jarcher at pobox.com (jarcher at pobox.com)
Date: Mon Nov 17 10:07:00 2003
Subject: Off by eight.
Message-ID: <5.2.1.1.2.20031117073804.03b83058@wheresmymailserver.com>

I'm generating an new CPU, SB and motherboard.  I got the build up and 
running, but my image is off by eight bytes.  The reset code that should be 
at the top of the ROM (xxxxFFF0) is at xxxxFFF8, so I'm short 8 bytes in 
the ROM image file.

Anyone have a clue as to what I should look at to trace this down?

Jordan



From niki.waibel at newlogic.com  Mon Nov 17 10:31:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Nov 17 10:31:01 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
In-Reply-To: <Pine.LNX.4.44.0311170821390.1085-100000@maxroach.lanl.gov>
Message-ID: <200311171605.hAHG5E84004998@enterprise2.newlogic.at>

>> any chance to get /dev/ttyS1 (/dev/tts/1) working with freebios
>> on the emia-m?
>> 
>> (i need it for the smartcardreader ...)
> 
> as soon as we get epia-m up under v2.

seems that that v2 will take some time.
i'd like to hack v1 to get it running.
is
        src/lib/serial_subr.c:
        void ttys0_init(void) {}
the right place to look at?

setserial seems to be fine:
===
~ # setserial /dev/tts/0 -a
/dev/tts/0, Line 0, UART: 16550A, Port: 0x03f8, IRQ: 4
        Baud_base: 115200, close_delay: 500, divisor: 0
        closing_wait: 30000
        Flags: spd_normal skip_test

~ # setserial /dev/tts/1 -a
/dev/tts/1, Line 1, UART: unknown, Port: 0x02f8, IRQ: 3
        Baud_base: 115200, close_delay: 500, divisor: 0
        closing_wait: 30000
        Flags: spd_normal skip_test
===

but the kernel has not recogn the serial ports:
===
~ # dmesg | grep tty
ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
===

ttyS0 (tts/0) is where i run the console...

niki


From rsmith at bitworks.com  Mon Nov 17 11:05:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Mon Nov 17 11:05:01 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <200311141621.38539@korath>
References: <200311131712.14052@korath> <200311132003.27487@korath> <3FB3BA30.9070604@bitworks.com> <200311141621.38539@korath>
Message-ID: <3FB8F977.8020701@bitworks.com>

Adam Nielsen wrote:

> 00:00.0 Host bridge: Intel Corp. 440LX/EX - 82443LX/EX Host bridge (rev 03)
> 00:01.0 PCI bridge: Intel Corp. 440LX/EX - 82443LX/EX AGP bridge (rev 03)
> 00:07.0 ISA bridge: Intel Corp. 82371AB/EB/MB PIIX4 ISA (rev 02)
> 00:07.1 IDE interface: Intel Corp. 82371AB/EB/MB PIIX4 IDE (rev 01)
> 00:07.2 USB Controller: Intel Corp. 82371AB/EB/MB PIIX4 USB (rev 01)
> 00:07.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02)

I don't know the exact differnce between the LX and BX parts but I 
believe that the LX only supported up to a Pentium II whereas the BX 
does a III and a celeron. I that the 440BX code should work for you.  I 
know I used a lot of the LX/TX code as reference when I was getting our 
board to work.  You should at least be able to get a serial port up.

Perhaps you can find a LX data sheet somewhere.

What superIO is on the board?  Look for a National Semi chip or a 
winbond or something similar.

-- 
Richard A. Smith
rsmith at bitworks.com




From rminnich at lanl.gov  Mon Nov 17 11:07:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov 17 11:07:00 2003
Subject: Off by eight.
In-Reply-To: <5.2.1.1.2.20031117073804.03b83058@wheresmymailserver.com>
Message-ID: <Pine.LNX.4.44.0311170941050.1085-100000@maxroach.lanl.gov>

what version of linuxbios?

ron



From linuxbios at xdr.com  Mon Nov 17 11:12:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Mon Nov 17 11:12:00 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
Message-ID: <200311171646.hAHGkEcQ029656@xdr.com>

>setserial seems to be fine:

In V1 the file to modify is src/superio/via/vt1211/setup_serial.inc
That code sets up ttyS0 which is the VT1211's logical device 2. You
want to add some similiar code for logical device 3 to get ttyS1 working.

Assuming you want it to be at 2f8 you'd merge in these lines:
	OUTPNPADDR($7)
	OUTPNPDATA($3)
	/* set the enable in reg. 0x30 */
	OUTPNPADDR($0x30)
	OUTPNPDATA($0x1)

	/* Serial Port 2 Base Address (BEh) */
	OUTPNPADDR($0x60)
	OUTPNPDATA($0xbe)
	/* Serial Port 2 IRQ (03h) */
	OUTPNPADDR($0x70)
	OUTPNPDATA($0x3)
	/* Serial Port 2 Control */
	OUTPNPADDR($0xf0)
	OUTPNPDATA($0x2)

...then do the turn off pnp
	/* turn off PnP */
	OUTPNPADDR($0xaa)

...then duplicate the serial setup except the address goes from 3f8 -> 2f8

That should do it.

-Dave


From rsmith at bitworks.com  Mon Nov 17 11:31:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Mon Nov 17 11:31:00 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
In-Reply-To: <200311171605.hAHG5E84004998@enterprise2.newlogic.at>
References: <200311171605.hAHG5E84004998@enterprise2.newlogic.at>
Message-ID: <3FB8FFBA.9030100@bitworks.com>

Niki Waibel wrote:

> 
> ~ # setserial /dev/tts/1 -a
> /dev/tts/1, Line 1, UART: unknown, Port: 0x02f8, IRQ: 3
>         Baud_base: 115200, close_delay: 500, divisor: 0
>         closing_wait: 30000
>         Flags: spd_normal skip_test
> ===

Are you sure setserial acutally reads the info from the device or is it 
just showing you what the current settings of the device should be?

Ah.. Never mind I just looked at the man page and answered my question.

from the man page
"It is important to note that setserial merely tells the Linux kernel 
where it should expect to find the I/O port and IRQ lines of a 
particular serial port. It does *not* configure the hardware....."

So I'm guessing the 2nd serial device isn't enabled.

-- 
Richard A. Smith
rsmith at bitworks.com




From niki.waibel at newlogic.com  Mon Nov 17 11:37:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Nov 17 11:37:01 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
In-Reply-To: <3FB8FFBA.9030100@bitworks.com>
Message-ID: <200311171710.hAHHAn84013406@enterprise2.newlogic.at>

On 17-Nov-2003 Richard Smith wrote:
> Niki Waibel wrote:
> 
>> 
>> ~ # setserial /dev/tts/1 -a
>> /dev/tts/1, Line 1, UART: unknown, Port: 0x02f8, IRQ: 3
>>         Baud_base: 115200, close_delay: 500, divisor: 0
>>         closing_wait: 30000
>>         Flags: spd_normal skip_test
>> ===
> 
> Are you sure setserial acutally reads the info from the device or is it 
> just showing you what the current settings of the device should be?
> 
> Ah.. Never mind I just looked at the man page and answered my question.
> 
> from the man page
> "It is important to note that setserial merely tells the Linux kernel 
> where it should expect to find the I/O port and IRQ lines of a 
> particular serial port. It does *not* configure the hardware....."
> 
> So I'm guessing the 2nd serial device isn't enabled.

so it is.
it is done in
src/superio/via/vt1211/setup_serial.inc
but there are too many fancy values :)

niki


From niki.waibel at newlogic.com  Mon Nov 17 11:39:00 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Nov 17 11:39:00 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
In-Reply-To: <200311171646.hAHGkEcQ029656@xdr.com>
Message-ID: <200311171713.hAHHDW84013458@enterprise2.newlogic.at>

On 17-Nov-2003 Dave Ashley wrote:
>>setserial seems to be fine:
> 
> In V1 the file to modify is src/superio/via/vt1211/setup_serial.inc
> That code sets up ttyS0 which is the VT1211's logical device 2. You
> want to add some similiar code for logical device 3 to get ttyS1 working.
> 
> Assuming you want it to be at 2f8 you'd merge in these lines:
>       OUTPNPADDR($7)
>       OUTPNPDATA($3)
>       /* set the enable in reg. 0x30 */
>       OUTPNPADDR($0x30)
>       OUTPNPDATA($0x1)
> 
>       /* Serial Port 2 Base Address (BEh) */
>       OUTPNPADDR($0x60)
>       OUTPNPDATA($0xbe)
>       /* Serial Port 2 IRQ (03h) */
>       OUTPNPADDR($0x70)
>       OUTPNPDATA($0x3)
>       /* Serial Port 2 Control */
>       OUTPNPADDR($0xf0)
>       OUTPNPDATA($0x2)
> 
> ...then do the turn off pnp
>       /* turn off PnP */
>       OUTPNPADDR($0xaa)
> 
> ...then duplicate the serial setup except the address goes from 3f8 -> 2f8
> 
> That should do it.

thanks a lot.
i'll give it a try.
how do you know that it is VT1211's logical device #3?

niki


From linuxbios at xdr.com  Mon Nov 17 11:50:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Mon Nov 17 11:50:01 2003
Subject: v2 via/epia target broken
Message-ID: <200311171724.hAHHO6oo029767@xdr.com>

dave.root% ./buildtarget via/epia 
build_dir=via/epia/epia
No linuxbios config script found. Rebuilding it..
Input Grammar: /ram/freebios2/util/newconfig/config.g
Output File: via/epia/epia/config.py
Configuring TARGET epia
Will place Makefile, crt0.S, etc. in via/epia/epia
Configuring ROMIMAGE normal
Configuring DIR /config/Config.lb
Configuring DIR /lib/Config.lb
Configuring DIR /console/Config.lb
Configuring DIR /stream/Config.lb
Configuring DIR /devices/Config.lb
Configuring DIR /pc80/Config.lb
Configuring DIR /boot/Config.lb
Configuring PART mainboard, path via/epia
Trying to find one of EQ on line 20:
>  default ROM_SIZE  256*1024
>                    ^
List of nearby tokens: 
  (@257)  USES  =  'uses'
  (@262)  ID  =  '_ROMBASE'
  (@271)  USES  =  'uses'
  (@276)  ID  =  'XIP_ROM_SIZE'
  (@289)  USES  =  'uses'
  (@294)  ID  =  'XIP_ROM_BASE'
  (@307)  USES  =  'uses'
  (@312)  ID  =  'HAVE_MP_TABLE'
  (@389)  DEFAULT  =  'default'
  (@397)  ID  =  'ROM_SIZE'
===> ERROR: Could not parse file
via/epia/Config.lb:0
mainboard/via/epia/Config.lb:0
dave.root% 


This broke as of a change 2003/10/13 -> 2003/10/14 in targets/buildtarget.

-Dave


From niki.waibel at newlogic.com  Mon Nov 17 11:57:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Mon Nov 17 11:57:01 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
In-Reply-To: <200311171646.hAHGkEcQ029656@xdr.com>
Message-ID: <200311171731.hAHHVQ84015938@enterprise2.newlogic.at>

perfect!!!
linux-2.6.0-test9-bk16 says:
===
Serial: 8250/16550 driver $Revision: 1.90 $ 8 ports, IRQ sharing disabled
ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
===
thanks a lot!!!
niki

On 17-Nov-2003 Dave Ashley wrote:
>>setserial seems to be fine:
> 
> In V1 the file to modify is src/superio/via/vt1211/setup_serial.inc
> That code sets up ttyS0 which is the VT1211's logical device 2. You
> want to add some similiar code for logical device 3 to get ttyS1 working.
> 
> Assuming you want it to be at 2f8 you'd merge in these lines:
>       OUTPNPADDR($7)
>       OUTPNPDATA($3)
>       /* set the enable in reg. 0x30 */
>       OUTPNPADDR($0x30)
>       OUTPNPDATA($0x1)
> 
>       /* Serial Port 2 Base Address (BEh) */
>       OUTPNPADDR($0x60)
>       OUTPNPDATA($0xbe)
>       /* Serial Port 2 IRQ (03h) */
>       OUTPNPADDR($0x70)
>       OUTPNPDATA($0x3)
>       /* Serial Port 2 Control */
>       OUTPNPADDR($0xf0)
>       OUTPNPDATA($0x2)
> 
> ...then do the turn off pnp
>       /* turn off PnP */
>       OUTPNPADDR($0xaa)
> 
> ...then duplicate the serial setup except the address goes from 3f8 -> 2f8
> 
> That should do it.
> 
> -Dave


From linuxbios at xdr.com  Mon Nov 17 11:57:28 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Mon Nov 17 11:57:28 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
Message-ID: <200311171731.hAHHVqbt029804@xdr.com>

Niki Waibel wrote:
>how do you know that it is VT1211's logical device #3?

ttyS0 is the VT1211's first serial port at logical device 2, the VT1211
has 2 serial ports, the next one is logical device 3, I'm assuming via
wired the motherboard up this way since that's the way I'd do it.

I have the VT1211 datasheet, but VIA only releases it under NDA as far as I
know.

-Dave


From rminnich at lanl.gov  Mon Nov 17 11:59:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov 17 11:59:01 2003
Subject: v2 via/epia target broken [PMX:#]
In-Reply-To: <200311171724.hAHHO6oo029767@xdr.com>
Message-ID: <Pine.LNX.4.44.0311171033200.6311-100000@maxroach.lanl.gov>

On Mon, 17 Nov 2003, Dave Ashley wrote:

> Configuring PART mainboard, path via/epia
> Trying to find one of EQ on line 20:
> >  default ROM_SIZE  256*1024
> >                    ^


fixed, our fault, please cvs update.

ron



From linuxbios at xdr.com  Mon Nov 17 12:16:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Mon Nov 17 12:16:00 2003
Subject: v2 via/epia target broken [PMX:#]
Message-ID: <200311171750.hAHHoR3e029878@xdr.com>

Ron Minnich wrote:
>fixed, our fault, please cvs update.

This reminds me of the Simpson's episode where they give homer the
correct number to call for emergencies--912.

When I cvs update nothing changes. I'm using the common pondscum cvs server
as described in this document:
http://www.linuxbios.org/developer/download/index.html

What is the procedure for the elite cvs server that the royalty use?

-Dave


From stepan at suse.de  Mon Nov 17 12:29:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Mon Nov 17 12:29:01 2003
Subject: v2 via/epia target broken [PMX:#]
In-Reply-To: <200311171750.hAHHoR3e029878@xdr.com>
References: <200311171750.hAHHoR3e029878@xdr.com>
Message-ID: <20031117180338.GB25490@suse.de>

* Dave Ashley <linuxbios at xdr.com> [031117 18:50]:
> Ron Minnich wrote:
> >fixed, our fault, please cvs update.
> 
> This reminds me of the Simpson's episode where they give homer the
> correct number to call for emergencies--912.
> 
> When I cvs update nothing changes. I'm using the common pondscum cvs server
> as described in this document:
> http://www.linuxbios.org/developer/download/index.html
> 
> What is the procedure for the elite cvs server that the royalty use?

Looks like Sourceforge is getting worse again.. Check
http://snapshots.linuxbios.org/

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From rminnich at lanl.gov  Mon Nov 17 12:33:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov 17 12:33:01 2003
Subject: v2 via/epia target broken [PMX:#]
In-Reply-To: <20031117180338.GB25490@suse.de>
Message-ID: <Pine.LNX.4.44.0311171106160.6311-100000@maxroach.lanl.gov>

On Mon, 17 Nov 2003, Stefan Reinauer wrote:

> > What is the procedure for the elite cvs server that the royalty use?
> 
> Looks like Sourceforge is getting worse again.. Check
> http://snapshots.linuxbios.org/

I just mailed Dave the file for now. 

Everyone, the change in the new config language is to the default keywork. 
You can tell I'm not a real language designer, as my syntax was:

default name value
option name=value

stupid.

changed to

default name=value
option name=value

thanks

ron



From linuxbios at xdr.com  Mon Nov 17 13:29:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Mon Nov 17 13:29:01 2003
Subject: v2 via/epia target broken [PMX:#]
Message-ID: <200311171903.hAHJ3ZCK030478@xdr.com>

Rom Minnich wrote:
>I just mailed Dave the file for now. 

I figured out the file needed to go in src/mainboard/via/epia/Config.lb
since diffing that one was a lot less different than
targets/via/epia/Config.lb.

However it still errors out with:

dave.root% ./buildtarget via/epia 
build_dir=via/epia/epia
No linuxbios config script found. Rebuilding it..
Input Grammar: /code/freebios2/util/newconfig/config.g
Output File: via/epia/epia/config.py
Configuring TARGET epia
Will place Makefile, crt0.S, etc. in via/epia/epia
Configuring ROMIMAGE normal
Configuring DIR /config/Config.lb
Configuring DIR /lib/Config.lb
Configuring DIR /console/Config.lb
Configuring DIR /stream/Config.lb
Configuring DIR /devices/Config.lb
Configuring DIR /pc80/Config.lb
Configuring DIR /boot/Config.lb
Configuring PART mainboard, path via/epia
===> WARNING: Changing default value of ROM_SIZE
===> ERROR: Options may only be set in target configuration file
via/epia/Config.lb:0
mainboard/via/epia/Config.lb:0

-Dave



From linuxbios at xdr.com  Mon Nov 17 18:27:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Mon Nov 17 18:27:01 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
Message-ID: <200311180001.hAI01kbL031367@xdr.com>

>perfect!!!

Can you verify something: On my epia-m ttyS0 is 1/2 the baud rate it should
be, so I can't get 115,200 baud, only 57,600. Can you verify if you can
get 115,200 on both serial ports?

-Dave


From aod at ponto-i.net  Mon Nov 17 19:26:00 2003
From: aod at ponto-i.net (Andre Dias)
Date: Mon Nov 17 19:26:00 2003
Subject: all sis730 mainboards
Message-ID: <1069117230.6723.3.camel@laptop>

In sis website it lists all sis730 mainboards that we can use with
linuxbios!

I personnaly have used ECS K7SEM and pcchips M810, M810LR, M810LMR and
M812.




From aod at ponto-i.net  Mon Nov 17 19:27:00 2003
From: aod at ponto-i.net (Andre Dias)
Date: Mon Nov 17 19:27:00 2003
Subject: ** all sis730 mainboards
Message-ID: <1069117297.6723.5.camel@laptop>

In sis website it lists all sis730 mainboards that we can use with
linuxbios!

I personnaly have used ECS K7SEM and pcchips M810, M810LR, M810LMR and
M812.

sorry, here is the link:

http://www.sis.com/wheretobuy/730cus.htm






From aod at ponto-i.net  Mon Nov 17 20:37:01 2003
From: aod at ponto-i.net (Andre Dias)
Date: Mon Nov 17 20:37:01 2003
Subject: sis730 motherboards with dip32 and plcc sockets
Message-ID: <1069121489.6723.17.camel@laptop>

I actually conducted a research to find which motherboards have plcc and
dip32 sockets and here is the result:

Pcchips: m810clr (dip), m810l (dip), m810lmr (dip), m810lr (plcc),
m810lr-xp
(dip), 812 (dip)
Ecs: K7SEM (dip)
Chaintech: 7SIV ou CT-7SIV (dip)
Gigabyte: GA-7SMZ (plcc)
Jetway: 830CN (plcc)
LeadTeK: winfast7300k7 (dip)
Asus: A7S-VM (dip)
Matsonic: ms8308ep266 (plcc)
                                                                                
                                                                                
                                                                                
                                                                                
                                                                                
                                                                                





From a.nielsen at optushome.com.au  Mon Nov 17 20:47:01 2003
From: a.nielsen at optushome.com.au (Adam Nielsen)
Date: Mon Nov 17 20:47:01 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <3FB8F977.8020701@bitworks.com>
References: <200311131712.14052@korath> <200311141621.38539@korath> <3FB8F977.8020701@bitworks.com>
Message-ID: <200311181221.01684@korath>

> I don't know the exact differnce between the LX and BX parts but I
> believe that the LX only supported up to a Pentium II whereas the BX 
> does a III and a celeron.

Yes, seems to be the main difference (at least from an end user's perspective 
like mine!)  The board only supports up to a 333MHz CPU and it does support a 
Celeron, but it can't do a 100MHz bus (only 66 officially, but it will go up 
to 83.)

> I that the 440BX code should work for you.  I know I used a lot of the LX/TX
> code as reference when I was getting our board to work.  You should at least
> be able to get a serial port up.

Great, I'll try that then.  It's looking more and more like I could just grab 
the GA-6BXC code and use that!  I'm just waiting to get hold of an extra BIOS 
chip, to extend the life of the motherboard should anything go wrong ;-)

> What superIO is on the board?  Look for a National Semi chip or a
> winbond or something similar.

Well, there's a Winbond W83977TF-AW and that seems to be the only Winbond 
chip.  Can't see any Nat. Semi. ones though, so hopefully that's the one 
you're looking for!

Thanks for your reply,
Adam.



From niki.waibel at newlogic.com  Tue Nov 18 04:08:00 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Tue Nov 18 04:08:00 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
In-Reply-To: <200311180001.hAI01kbL031367@xdr.com>
Message-ID: <200311180942.hAI9gq84008576@enterprise2.newlogic.at>

def sure 57600 is (currently) the max on /dev/ttyS0.
(but my setup is 115200).
i dont care much, but of course it should be fixed.

/dev/ttyS0 was at 115200 when i changed from the regular
bios to linuxbios. a soft reset was ok -- still 115200.
but after pressing the power switch the port was at
57600 max.

i have to check ttyS1...
(i am working with devfs so i might refer to tts/1 in furure...)

niki

On 18-Nov-2003 Dave Ashley wrote:
>>perfect!!!
> 
> Can you verify something: On my epia-m ttyS0 is 1/2 the baud rate it should
> be, so I can't get 115,200 baud, only 57,600. Can you verify if you can
> get 115,200 on both serial ports?
> 
> -Dave
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 
niki w. waibel - system administrator @ newlogic technologies ag


From aip at cwlinux.com  Tue Nov 18 06:25:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Nov 18 06:25:01 2003
Subject: epia-m (600mhz) -- /dev/ttyS1
In-Reply-To: <200311180942.hAI9gq84008576@enterprise2.newlogic.at>; from Niki Waibel on Tue, Nov 18, 2003 at 10:42:52AM +0100
References: <200311180001.hAI01kbL031367@xdr.com> <200311180942.hAI9gq84008576@enterprise2.newlogic.at>
Message-ID: <20031118195906.A17864@mail.cwlinux.com>

Hi,

I think there is a clock has to be set.  I have seen similar problem with
USB on a custom board.  After setting the clock gen which connected to USB,
USB works.

-Andrew

On Tue, Nov 18, 2003 at 10:42:52AM +0100, Niki Waibel wrote:
> def sure 57600 is (currently) the max on /dev/ttyS0.
> (but my setup is 115200).
> i dont care much, but of course it should be fixed.
> 
> /dev/ttyS0 was at 115200 when i changed from the regular
> bios to linuxbios. a soft reset was ok -- still 115200.
> but after pressing the power switch the port was at
> 57600 max.
> 
> i have to check ttyS1...
> (i am working with devfs so i might refer to tts/1 in furure...)
> 
> niki
> 
> On 18-Nov-2003 Dave Ashley wrote:
> >>perfect!!!
> > 
> > Can you verify something: On my epia-m ttyS0 is 1/2 the baud rate it should
> > be, so I can't get 115,200 baud, only 57,600. Can you verify if you can
> > get 115,200 on both serial ports?
> > 
> > -Dave
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
> -- 
> niki w. waibel - system administrator @ newlogic technologies ag
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From erikjson at linuxmail.org  Tue Nov 18 09:25:01 2003
From: erikjson at linuxmail.org (Erik Jansson)
Date: Tue Nov 18 09:25:01 2003
Subject: 440BX and SDRAM
Message-ID: <20031118145951.10855.qmail@linuxmail.org>

Hi all!

I have been playing with  LinuxBIOS on motherboards with Intel's 440BX
chipset. I have  a whole bunch of them: a Microbits Epox EP-61 BXA-M,
an MSI MS6120 (dual), an Intel development board and a custom designed
BX board). I have managed to get most of the stuff up and running. Two
things are missing though...

1. I can't manage to initiate more than 128 MB of SDRAM (ramtest
fails). I've tried a lot of different types and brands of memories,
standard DIMMs and SO-DIMMS, different sizes, etc. I'm thinking it has
something to do with "double sided" memory (or dual "module banks" or
whatever terminology you choose). Buffer strength settings maybe? But
I've tried the same settings as the standard BIOS uses (which sets up
the memory correctly btw) and still no go. Some obscure bit in some
obscure register? 

2. Dual CPU support on the MSI board.

My major concern is the memory support though.

I just thought that I'd throw out a question and see if somebody has been
or is working with the same thing and has bumped into something similar.
The archives tell me that there has been some fierce fighting with SDRAM
issues earlier and I see why... This stuff is complicated.

I'm running a LinuxBIOS from CVS dated 2003-11-04.

/Erik

-- 
______________________________________________
Check out the latest SMS services @ http://www.linuxmail.org 
This allows you to send and receive SMS through your mailbox.


Powered by Outblaze


From rsmith at bitworks.com  Tue Nov 18 10:47:01 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Tue Nov 18 10:47:01 2003
Subject: 440BX and SDRAM
In-Reply-To: <20031118145951.10855.qmail@linuxmail.org>
References: <20031118145951.10855.qmail@linuxmail.org>
Message-ID: <3FBA4653.3050502@bitworks.com>

Erik Jansson wrote:

> 
> 1. I can't manage to initiate more than 128 MB of SDRAM (ramtest 
> fails). I've tried a lot of different types and brands of memories, 
> standard DIMMs and SO-DIMMS, different sizes, etc. I'm thinking it
> has something to do with "double sided" memory (or dual "module
> banks" or whatever terminology you choose). Buffer strength settings
> maybe? But I've tried the same settings as the standard BIOS uses
> (which sets up the memory correctly btw) and still no go. Some
> obscure bit in some obscure register?

Are you trying 2 128 MB DIMMS or a 256 MB DIMM?  The 440bx does not
support 256Mbit dram so most 256 meg dimms won't work.  Of course now 
that I re-read you say the standard bios works so its probally not that.

What bus speed are you running at?  Intel claims that buffer strength 
becomes very critial at 100Mhz the board I did most testing on only runs 
66Mhz and the project that used a 100Mhz version died so I don't have 
much data on the subject but thats the word I got from intel.

I don't recall any non-documented registers.  Once I figured out the 
difference between the standard bios and what Linuxbios was doing our 
ram problems went away.    I guess it's still not totally fixed though, 
Bummer.  That's very tedious stuff to debug.  I can't help much either 
since our board only has 1 DIMM.

So things up to 128 Meg work but > 128 fails?

-- 
Richard A. Smith
rsmith at bitworks.com




From rsmith at bitworks.com  Tue Nov 18 10:51:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Tue Nov 18 10:51:00 2003
Subject: Questions about LinuxBIOS
In-Reply-To: <200311181221.01684@korath>
References: <200311131712.14052@korath> <200311141621.38539@korath> <3FB8F977.8020701@bitworks.com> <200311181221.01684@korath>
Message-ID: <3FBA47C7.6010205@bitworks.com>

Adam Nielsen wrote:

>>I that the 440BX code should work for you.  I know I used a lot of the LX/TX
>>code as reference when I was getting our board to work.  You should at least
>>be able to get a serial port up.
> 
> 
> Great, I'll try that then.  It's looking more and more like I could just grab 
> the GA-6BXC code and use that!  I'm just waiting to get hold of an extra BIOS 
> chip, to extend the life of the motherboard should anything go wrong ;-)

Hopefully it will be that simple, however I doubt it.

You might also try to use the Bitworks/IMS project.  But since we use a 
National Semi superIO rather than your Windbond you will have to hack on 
it to get any serial output.

-- 
Richard A. Smith
rsmith at bitworks.com




From rminnich at lanl.gov  Tue Nov 18 10:58:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 10:58:01 2003
Subject: 440BX and SDRAM
In-Reply-To: <3FBA4653.3050502@bitworks.com>
Message-ID: <Pine.LNX.4.44.0311180932170.18676-100000@maxroach.lanl.gov>

The right thing to do at this point is to bite the bullet, write the 
startup code in C, and bring the whole thing forward to V2. This stuff is 
really hard in assembly. 

ron



From maillists at petrolhead.com  Tue Nov 18 11:02:01 2003
From: maillists at petrolhead.com (maillists at petrolhead.com)
Date: Tue Nov 18 11:02:01 2003
Subject: Inline assembler problems with S2880 build
Message-ID: <10D204DE080CA744A64FC11EBC67A1770939A0@portacabin.no-ip.org>

Hi,

I'm a newbie to this, but I'm trying to build for a Tyan S2880 board.
However during the build I get;

....
eebios2/src/devices/hypertransport.c
/tmp/ccniyAWJ.s: Assembler messages:
/tmp/ccniyAWJ.s:120: Error: Incorrect register `%rcx' used with `l' suffix
/tmp/ccniyAWJ.s:122: Error: Incorrect register `%rcx' used with `l' suffix

This is built on a completely standard Suse 2.4.19 build
Linux Boco 2.4.19 #1 Wed Jun 25 21:34:14 UTC 2003 x86_64 unknown unknown
GNU/Linux

Any thoughts

Many thanks

Chris


From stepan at suse.de  Tue Nov 18 11:21:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Nov 18 11:21:00 2003
Subject: Inline assembler problems with S2880 build
In-Reply-To: <10D204DE080CA744A64FC11EBC67A1770939A0@portacabin.no-ip.org>
References: <10D204DE080CA744A64FC11EBC67A1770939A0@portacabin.no-ip.org>
Message-ID: <20031118165602.GA343@suse.de>

* maillists at petrolhead.com <maillists at petrolhead.com> [031118 17:35]:
> Hi,
> 
> I'm a newbie to this, but I'm trying to build for a Tyan S2880 board.
> However during the build I get;
> 
> ....
> eebios2/src/devices/hypertransport.c
> /tmp/ccniyAWJ.s: Assembler messages:
> /tmp/ccniyAWJ.s:120: Error: Incorrect register `%rcx' used with `l' suffix
> /tmp/ccniyAWJ.s:122: Error: Incorrect register `%rcx' used with `l' suffix
> 
> This is built on a completely standard Suse 2.4.19 build
> Linux Boco 2.4.19 #1 Wed Jun 25 21:34:14 UTC 2003 x86_64 unknown unknown
> GNU/Linux
 
You have to compile LinuxBIOS using the 32bit instruction set of the
AMD64 cpu. To do this, add the following to your target configuration
file (i.e. freebios2/targets/tyan/s2880/Config.lb):

uses CC
option CC="gcc -m32"

 Stefan


-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From maillists at petrolhead.com  Tue Nov 18 11:53:01 2003
From: maillists at petrolhead.com (maillists at petrolhead.com)
Date: Tue Nov 18 11:53:01 2003
Subject: Missing files from freebios2
Message-ID: <10D204DE080CA744A64FC11EBC67A1770939A2@portacabin.no-ip.org>

Hi,

So my last question referred to S2880, however just noticed a Quartet build
does exist, which is what I really want, saves me doing the port! What state
is this port in at the moment? Does it boot, I'm quite willing to help out
bringing it up.

The freebios2 cvs tree seems to be missing at least;

tg3.zelf
lsi_scsi.c

And more importantly for me
/suse/stepan/tg3--ide_disk.zelf
is missing, guess that's on Stefan's drive somewhere ;-)

Chris


From xpegenaute at telepolis.es  Tue Nov 18 11:58:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Nov 18 11:58:01 2003
Subject: ".config" file for epia-m
Message-ID: <1069176777.982.35.camel@p-133>

Hi,

anyone have a .config file for epia-m to put it as payload? at the
moment my bzImage.elf is about 319Kb. Is it possible with epia and
normal flash rom?

Thanks.



From maillists at petrolhead.com  Tue Nov 18 12:09:01 2003
From: maillists at petrolhead.com (maillists at petrolhead.com)
Date: Tue Nov 18 12:09:01 2003
Subject: Missing files from freebios2
Message-ID: <10D204DE080CA744A64FC11EBC67A1770939A3@portacabin.no-ip.org>

OK, ignore the last stupid question the zelf's are obviously the compressed
kernels, guess I was a bit surprised to be there already! Doh. CVS is still
missing lsi_scsi.c however.

Chris

> -----Original Message-----
> From: maillists at petrolhead.com 
> Sent: 18 November 2003 17:27
> To: 'linuxbios at clustermatic.org'
> Subject: Missing files from freebios2
> 
> 
> Hi,
> 
> So my last question referred to S2880, however just noticed a 
> Quartet build does exist, which is what I really want, saves 
> me doing the port! What state is this port in at the moment? 
> Does it boot, I'm quite willing to help out bringing it up.
> 
> The freebios2 cvs tree seems to be missing at least;
> 
> tg3.zelf
> lsi_scsi.c
> 
> And more importantly for me
> /suse/stepan/tg3--ide_disk.zelf
> is missing, guess that's on Stefan's drive somewhere ;-)
> 
> Chris
> 


From rminnich at lanl.gov  Tue Nov 18 12:18:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 12:18:01 2003
Subject: ".config" file for epia-m
In-Reply-To: <1069176777.982.35.camel@p-133>
Message-ID: <Pine.LNX.4.44.0311181052250.18676-100000@maxroach.lanl.gov>

On 18 Nov 2003, Xavier Pegenaute wrote:

> anyone have a .config file for epia-m to put it as payload? at the
> moment my bzImage.elf is about 319Kb. Is it possible with epia and
> normal flash rom?

WOW! what kernel version? I'm interested in your .config. 

512KB flash works fine on that board, so you should be ok with that 
kernel.

ron



From YhLu at tyan.com  Tue Nov 18 12:23:00 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Nov 18 12:23:00 2003
Subject: Missing files from freebios2
Message-ID: <3174569B9743D511922F00A0C9431423036D290C@TYANWEB>

Chris,

The S2880 can boot from the very beginning.

Lsi_scsi.c is about onboard scsi support. I don't know if you really need
that feature. I didn't get the permission from LSI to release the code yet.
So if you really need that feature, I will send the pre-built image to you.

Today I will verify the config can work without that file.

Regards

YH.


-----????-----
???: maillists at petrolhead.com [mailto:maillists at petrolhead.com] 
????: 2003?11?18? 9:43
???: 'linuxbios at clustermatic.org'
??: RE: Missing files from freebios2

OK, ignore the last stupid question the zelf's are obviously the compressed
kernels, guess I was a bit surprised to be there already! Doh. CVS is still
missing lsi_scsi.c however.

Chris

> -----Original Message-----
> From: maillists at petrolhead.com 
> Sent: 18 November 2003 17:27
> To: 'linuxbios at clustermatic.org'
> Subject: Missing files from freebios2
> 
> 
> Hi,
> 
> So my last question referred to S2880, however just noticed a 
> Quartet build does exist, which is what I really want, saves 
> me doing the port! What state is this port in at the moment? 
> Does it boot, I'm quite willing to help out bringing it up.
> 
> The freebios2 cvs tree seems to be missing at least;
> 
> tg3.zelf
> lsi_scsi.c
> 
> And more importantly for me
> /suse/stepan/tg3--ide_disk.zelf
> is missing, guess that's on Stefan's drive somewhere ;-)
> 
> Chris
> 
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From rsmith at bitworks.com  Tue Nov 18 12:37:00 2003
From: rsmith at bitworks.com (Richard Smith)
Date: Tue Nov 18 12:37:00 2003
Subject: 440BX and SDRAM
In-Reply-To: <Pine.LNX.4.44.0311180932170.18676-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311180932170.18676-100000@maxroach.lanl.gov>
Message-ID: <3FBA60D9.5080607@bitworks.com>

ron minnich wrote:

> The right thing to do at this point is to bite the bullet, write the 
> startup code in C, and bring the whole thing forward to V2. This stuff is 
> really hard in assembly. 
> 

Yuck.  It's really hard period just even more in assembly.  My biggest 
problem was that all the terms and algorithms are not documented 
anywhere and what documentation I found was confusing.

Are there general purpose SPD read and xlate functios in V2?  I know 
some people have been working on SDRAM for the EPIA.

-- 
Richard A. Smith
rsmith at bitworks.com




From xpegenaute at telepolis.es  Tue Nov 18 12:40:02 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Tue Nov 18 12:40:02 2003
Subject: ".config" file for epia-m
In-Reply-To: <Pine.LNX.4.44.0311181052250.18676-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311181052250.18676-100000@maxroach.lanl.gov>
Message-ID: <1069179305.981.46.camel@p-133>

Hi,

at the moment i used 2.2.20 by a mistake :-), now i'm trying with
linux-2.6.0-test7.tar.bz2, why not? and now also i want to try it with a
2.4.xx.

PD: I did'nt try if it really works but if it does'nt work it has to be
close to one working :-), good luck!
The size is after mkelImage.

Xavi
On Tue, 2003-11-18 at 18:52, ron minnich wrote:
> On 18 Nov 2003, Xavier Pegenaute wrote:
> 
> > anyone have a .config file for epia-m to put it as payload? at the
> > moment my bzImage.elf is about 319Kb. Is it possible with epia and
> > normal flash rom?
> 
> WOW! what kernel version? I'm interested in your .config. 
> 
> 512KB flash works fine on that board, so you should be ok with that 
> kernel.
> 
> ron
> 
-------------- next part --------------
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From rminnich at lanl.gov  Tue Nov 18 12:42:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 12:42:01 2003
Subject: 440BX and SDRAM
In-Reply-To: <3FBA60D9.5080607@bitworks.com>
Message-ID: <Pine.LNX.4.44.0311181115260.18676-100000@maxroach.lanl.gov>

On Tue, 18 Nov 2003, Richard Smith wrote:

> Are there general purpose SPD read and xlate functios in V2?  I know 
> some people have been working on SDRAM for the EPIA.

There are general functions and we're trying hard to make EPIA a 
reasonable example. It is way easier to do SPD in C. At the same time, 
EPIA chipset issues make it hard to use it as a "beautiful" example, but 
then again all chipsets are like that.

ron



From rminnich at lanl.gov  Tue Nov 18 12:42:24 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 12:42:24 2003
Subject: ".config" file for epia-m
In-Reply-To: <1069179305.981.46.camel@p-133>
Message-ID: <Pine.LNX.4.44.0311181116450.18676-100000@maxroach.lanl.gov>

ok, the 2.2 series will easily fit into 512KB. 2.4? Doubtful.

ron



From svante.signell at telia.com  Tue Nov 18 12:51:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Tue Nov 18 12:51:01 2003
Subject: 440BX and SDRAM
In-Reply-To: <20031118145951.10855.qmail@linuxmail.org>
References: <20031118145951.10855.qmail@linuxmail.org>
Message-ID: <1069179944.2833.52.camel@em2.my.own.domain>

On Tue, 2003-11-18 at 15:59, Erik Jansson wrote:
> Hi all!
> 
> I have been playing with  LinuxBIOS on motherboards with Intel's 440BX
> chipset. I have  a whole bunch of them: a Microbits Epox EP-61 BXA-M,
> an MSI MS6120 (dual), an Intel development board and a custom designed
> BX board). I have managed to get most of the stuff up and running. Two
> things are missing though...
> 
...
> 2. Dual CPU support on the MSI board.
...
> I'm running a LinuxBIOS from CVS dated 2003-11-04.
> 
> /Erik
Have you installed the LinuxBIOS on the MSI-6120. Interesting. I'm about
to do this when I get my Tualatin 1.3GHz running properly (single to
start with, dual later) on the MOBO with the AMI v2.0 BIOS installed. I
have serious problems with slowness when running with this CPU (and a
SLOT-T adapter), see my postings on the l2-cache activation code.  


From tyson at irobot.com  Tue Nov 18 13:10:01 2003
From: tyson at irobot.com (tyson at irobot.com)
Date: Tue Nov 18 13:10:01 2003
Subject: ".config" file for epia-m
In-Reply-To: <Pine.LNX.4.44.0311181116450.18676-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311181116450.18676-100000@maxroach.lanl.gov>
Message-ID: <3FBA688F.6020808@irobot.com>

ron minnich wrote:
> ok, the 2.2 series will easily fit into 512KB. 2.4? Doubtful.

I missed the message this is replying to but:

Though the kernel is rather stripped, we bootstrap our "virgin boards" 
with a 2.4 kernel using a 512K ROM emulator.

Cheers!
Ty

-- 
Tyson D Sawyer                             iRobot Corporation
Senior Systems Engineer                    Military Systems Division
tsawyer at irobot.com                         Robots for the Real World
603-654-3400 ext 206                       http://www.irobot.com



From rminnich at lanl.gov  Tue Nov 18 13:11:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 13:11:01 2003
Subject: question about amd8111_early_smbus.c
Message-ID: <Pine.LNX.4.44.0311181136380.18676-100000@maxroach.lanl.gov>

Here's some enable code

static void enable_smbus(void)
{
        device_t dev;
        dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
        if (dev == PCI_DEV_INVALID) {
                die("SMBUS controller not found\r\n");
        }
        uint8_t enable;
        print_debug("SMBus controller enabled\r\n");
        pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
        enable = pci_read_config8(dev, 0x41);
        pci_write_config8(dev, 0x41, enable | (1 << 7));
        /* clear any lingering errors, so the transaction will run */
        outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
}


Sounds OK, right? here's what I don't get:

#define SMBUS_IO_BASE 0x0f00

#define SMBGSTATUS 0xe0
#define SMBGCTL    0xe2
#define SMBHSTADDR 0xe4

etc.etc.

The io base is f00. The SMB registers get added to that: you get fe0, etc. 

I can interpret this two ways, one of them being that the IOBASE is fe0, 
and the way this is written is to optimize romcc behavior. But then I 
don't get this part:
        pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);

I would expect this to be set to SUMBUS_IO_BASE|0xE0|1 so that that the 
IOBASE in the register is 0xfe0. 

Or something else is going on here and I am *really* lost. Somebody want 
to clear my confusion :-)

ron



From linuxbios at xdr.com  Tue Nov 18 13:11:25 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Tue Nov 18 13:11:25 2003
Subject: linuxbios V2 on epia-m?
Message-ID: <200311181845.hAIIjQh6001590@xdr.com>

I'm interested in having this but there is only epia. Can someone outline
the steps involved in bringing V2 up on epia-m? I might tackle it if it
looks to be something I can handle. However last time I checked (yesterday)
I couldn't even build the v2 epia though.

Don't let my interest stop anyone else from jumping in and doing this.

-Dave


From rminnich at lanl.gov  Tue Nov 18 13:13:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 13:13:00 2003
Subject: ".config" file for epia-m
In-Reply-To: <3FBA688F.6020808@irobot.com>
Message-ID: <Pine.LNX.4.44.0311181147110.18676-100000@maxroach.lanl.gov>

Ty, I'll take that config file :-)

ron



From tyson at irobot.com  Tue Nov 18 15:38:00 2003
From: tyson at irobot.com (tyson at irobot.com)
Date: Tue Nov 18 15:38:00 2003
Subject: ".config" file for epia-m
In-Reply-To: <Pine.LNX.4.44.0311181147110.18676-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311181147110.18676-100000@maxroach.lanl.gov>
Message-ID: <3FBA8B49.6020501@irobot.com>

ron minnich wrote:
> Ty, I'll take that config file :-)
> 
> ron

This is for a 2.4.17 kernel.  ...just what I happened to be using back 
then and haven't changed it.

This kernel has no module support.  In this case I found that the 
overhead for module support was higher than just including the few 
features I needed.  This kernel is able to bootp config a network 
interface and nfs mount a root filesystem.  Other than that it has IDE 
disk, ext2fs, serial console support and not much else.

-rwxrwxr-x    1 tyson    tyson        426k Nov 18 14:56 
vmlinux-2.4.17-pbboot-1.0.0.bin.gz*

Cheers!
Ty

-- 
Tyson D Sawyer                             iRobot Corporation
Senior Systems Engineer                    Military Systems Division
tsawyer at irobot.com                         Robots for the Real World
603-654-3400 ext 206                       http://www.irobot.com
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From YhLu at tyan.com  Tue Nov 18 16:10:01 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Nov 18 16:10:01 2003
Subject: About Hardreset on Opteron MB
Message-ID: <3174569B9743D511922F00A0C9431423036D2943@TYANWEB>

Eric,

I have checked the latest code again for Opteron MB. The MB still needs to
reset three times to get it done.

1. Hyper transport scan link: 0 max: 1
PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003
PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007
HyperT reset needed
2. Initializing devices...
PCI: 00:18.3 init
NB: Function 3 Misc Control.. resetting cpu
3. Initializing devices...
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:19.3 init
NB: Function 3 Misc Control.. resetting cpu

Can we only reset the MB only time to make the HT work at the need
speed/width?

I mean only enable the reset in 
PCI: 00:19.3 init
NB: Function 3 Misc Control.. resetting cpu

Regards

YH


From stepan at suse.de  Tue Nov 18 16:25:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Nov 18 16:25:01 2003
Subject: About Hardreset on Opteron MB
In-Reply-To: <3174569B9743D511922F00A0C9431423036D2943@TYANWEB>
References: <3174569B9743D511922F00A0C9431423036D2943@TYANWEB>
Message-ID: <20031118220007.GA1070@suse.de>

* YhLu <YhLu at tyan.com> [031118 22:50]:
> I have checked the latest code again for Opteron MB. The MB still needs to
> reset three times to get it done.

> Can we only reset the MB only time to make the HT work at the need
> speed/width?
 
It should be enough to set a global variable "reset_needed" (maybe even
in CMOS) and check this, probably after all device drivers have been
executed and thus had the chance to set that flag.

> I mean only enable the reset in 
> PCI: 00:19.3 init
> NB: Function 3 Misc Control.. resetting cpu
  
When changing the parameters on Solo I always got it to one of the
reboots - My best result was to get it to the Misc Control reset before
it would hang hard.

   Stefan


-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From ebiederman at lnxi.com  Tue Nov 18 17:04:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Nov 18 17:04:01 2003
Subject: Off by eight.
In-Reply-To: <5.2.1.1.2.20031117073804.03b83058@wheresmymailserver.com>
References: <5.2.1.1.2.20031117073804.03b83058@wheresmymailserver.com>
Message-ID: <m3smkli9jv.fsf@maxwell.lnxi.com>

jarcher at pobox.com writes:

> I'm generating an new CPU, SB and motherboard.  I got the build up and running,
> but my image is off by eight bytes.  The reset code that should be at the top of
> 
> the ROM (xxxxFFF0) is at xxxxFFF8, so I'm short 8 bytes in the ROM image file.
> 
> Anyone have a clue as to what I should look at to trace this down?

Are you certain you don't have the 32 bit reset code, instead of the 16bit code?

Eric


From rminnich at lanl.gov  Tue Nov 18 17:12:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 17:12:01 2003
Subject: my question on the 8111
Message-ID: <Pine.LNX.4.44.0311181545380.18676-100000@maxroach.lanl.gov>

mea culpa. Yikes, I forgot that in addition to the smbus interface on 
one function of this chip there is a full smbus set on the PM interface. 
Ooops.

That makes much more sense now.

ron



From jarcher at pobox.com  Tue Nov 18 17:13:00 2003
From: jarcher at pobox.com (Jordan Archer)
Date: Tue Nov 18 17:13:00 2003
Subject: Off by eight.
In-Reply-To: <m3smkli9jv.fsf@maxwell.lnxi.com>
References: <5.2.1.1.2.20031117073804.03b83058@wheresmymailserver.com>
 <5.2.1.1.2.20031117073804.03b83058@wheresmymailserver.com>
Message-ID: <5.2.1.1.2.20031118144645.00bcfea8@cybermorph.com>

I'm pretty sure that it's not 32 bit reset code.  The problem appears if I 
try to build an image without a fallback.

Jordan

At 02:41 PM 11/18/2003, you wrote:
>jarcher at pobox.com writes:
>
> > I'm generating an new CPU, SB and motherboard.  I got the build up and 
> running,
> > but my image is off by eight bytes.  The reset code that should be at 
> the top of
> >
> > the ROM (xxxxFFF0) is at xxxxFFF8, so I'm short 8 bytes in the ROM 
> image file.
> >
> > Anyone have a clue as to what I should look at to trace this down?
>
>Are you certain you don't have the 32 bit reset code, instead of the 16bit 
>code?
>
>Eric
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Tue Nov 18 17:18:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 17:18:00 2003
Subject: Off by eight.
In-Reply-To: <5.2.1.1.2.20031118144645.00bcfea8@cybermorph.com>
Message-ID: <Pine.LNX.4.44.0311181552200.18676-100000@maxroach.lanl.gov>

On Tue, 18 Nov 2003, Jordan Archer wrote:

> I'm pretty sure that it's not 32 bit reset code.  The problem appears if I 
> try to build an image without a fallback.

oh. When I try to build an image without a fallback (this part is 
counterintuitive) I always just build a fallback. Possibly that's the 
wrong thing to do :0)

ron



From ebiederman at lnxi.com  Tue Nov 18 17:39:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Nov 18 17:39:00 2003
Subject: About Hardreset on Opteron MB
In-Reply-To: <20031118220007.GA1070@suse.de>
References: <3174569B9743D511922F00A0C9431423036D2943@TYANWEB>
	<20031118220007.GA1070@suse.de>
Message-ID: <m3y8udw9m9.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * YhLu <YhLu at tyan.com> [031118 22:50]:
> > I have checked the latest code again for Opteron MB. The MB still needs to
> > reset three times to get it done.
> 
> > Can we only reset the MB only time to make the HT work at the need
> > speed/width?
>  
> It should be enough to set a global variable "reset_needed" (maybe even
> in CMOS) and check this, probably after all device drivers have been
> executed and thus had the chance to set that flag.
> 
> > I mean only enable the reset in 
> > PCI: 00:19.3 init
> > NB: Function 3 Misc Control.. resetting cpu
>   
> When changing the parameters on Solo I always got it to one of the
> reboots - My best result was to get it to the Misc Control reset before
> it would hang hard.

Reducing the number of reboots definitely needs to happen.  I only coded
the way it is currently because that generates obviously correct code.

Right now I am looking at how to reduce problems when a board has
a noisy smbus.  So far I have not seen a single board without one.
In the noisy smbus the more traffic you have the more chances there
are you will have problems because of it.

So it might make sense to set everything up in a very early pass before
memory reset.  Reset the system, and then let the existing resets will
not trigger.

Either that or Stefans delayed scheme.   At this point I am not certain
which will be easier to maintain.  If we do implement the delayed reset
I want to move the memory clear code up into the generic framework so we
don't have to clear memory twice.  But if we can get the resets over with
before we initialize memory we are in better shape.  That plus something
like the kernels quirk interface to handle the various know bits of buggy
hardware and we should be ok.

Eric


From rminnich at lanl.gov  Tue Nov 18 17:55:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 17:55:00 2003
Subject: the really good news about i2c (smbus)
Message-ID: <Pine.LNX.4.44.0311181628010.18676-100000@maxroach.lanl.gov>

SMBUS/I2C is a noisy, glitchy, buggy mess that can hang motherboards. And
the motherboards, more and more, are depending on it working correctly for
all their management functions.

The PC world is really amazing sometimes.

ron



From Antony at Soft-Solutions.co.uk  Tue Nov 18 17:57:01 2003
From: Antony at Soft-Solutions.co.uk (Antony Stone)
Date: Tue Nov 18 17:57:01 2003
Subject: ".config" file for epia-m
In-Reply-To: <3FBA688F.6020808@irobot.com>
References: <Pine.LNX.4.44.0311181116450.18676-100000@maxroach.lanl.gov> <3FBA688F.6020808@irobot.com>
Message-ID: <200311182331.hAINVjj23426@agate.rockstone.co.uk>

On Tuesday 18 November 2003 6:44 pm, tyson at irobot.com wrote:

> ron minnich wrote:
> > ok, the 2.2 series will easily fit into 512KB. 2.4? Doubtful.
>
> I missed the message this is replying to but:
>
> Though the kernel is rather stripped, we bootstrap our "virgin boards"
> with a 2.4 kernel using a 512K ROM emulator.

I'd he interested to know exactly what you mean by "rather stripped", and I'd 
be keen to see a copy of your .config, too.

Antony.

-- 

Most people have more than the average number of legs.


From stepan at suse.de  Tue Nov 18 18:22:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Nov 18 18:22:00 2003
Subject: About Hardreset on Opteron MB
In-Reply-To: <m3y8udw9m9.fsf@maxwell.lnxi.com>
References: <3174569B9743D511922F00A0C9431423036D2943@TYANWEB> <20031118220007.GA1070@suse.de> <m3y8udw9m9.fsf@maxwell.lnxi.com>
Message-ID: <20031118235706.GB1446@suse.de>

* Eric W. Biederman <ebiederman at lnxi.com> [031119 00:16]:
> So it might make sense to set everything up in a very early pass before
> memory reset.  Reset the system, and then let the existing resets will
> not trigger.
> 
> Either that or Stefans delayed scheme.   At this point I am not certain
> which will be easier to maintain.  If we do implement the delayed reset
> I want to move the memory clear code up into the generic framework so we
> don't have to clear memory twice.  But if we can get the resets over with
> before we initialize memory we are in better shape.  That plus something
> like the kernels quirk interface to handle the various know bits of buggy
> hardware and we should be ok.

Would cache-as-ram be an alternative for AMD64 cpus to move the pretty
complex ht code to a point as early as possible? Romcc really does a
great job, but IIRC the current ht speed code is where it is now because
it is really hard to do before there is memory.

I also suspect AMD doing a better job in keeping cache as ram
initialization code the same over different cpu steppings than Intel
managed with their P-IV.

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From stepan at suse.de  Tue Nov 18 18:27:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Nov 18 18:27:00 2003
Subject: Off by eight.
In-Reply-To: <Pine.LNX.4.44.0311181552200.18676-100000@maxroach.lanl.gov>
References: <5.2.1.1.2.20031118144645.00bcfea8@cybermorph.com> <Pine.LNX.4.44.0311181552200.18676-100000@maxroach.lanl.gov>
Message-ID: <20031119000150.GC1446@suse.de>

* ron minnich <rminnich at lanl.gov> [031118 23:52]:
> On Tue, 18 Nov 2003, Jordan Archer wrote:
> 
> > I'm pretty sure that it's not 32 bit reset code.  The problem appears if I 
> > try to build an image without a fallback.
> 
> oh. When I try to build an image without a fallback (this part is 
> counterintuitive) I always just build a fallback. Possibly that's the 
> wrong thing to do :0)
 
It contains a small amount of overhead that is probably neglectable.
I played with building fallback-free images as well before just building
Fallback-only images instead. The concept is the same, just the code
that is used due to the make rules might change one or the other minor
startup file.

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From joshua at joshuawise.com  Tue Nov 18 18:33:00 2003
From: joshua at joshuawise.com (Joshua Wise)
Date: Tue Nov 18 18:33:00 2003
Subject: Porting
Message-ID: <200311181907.29633.joshua@joshuawise.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

I've got a ABIT KG7-RAID board here that I'd like to port LinuxBIOS to (and a 
school vacation coming up that I was planning to be bored over.) There used 
to be a page that had info on that, but my bookmark seems to be broken.

Can someone tell me what data I will need to gather to determine how much work 
I'll need to do, and what tools I'll need? I read that you guys use DoCs and 
BIOS saviors - do the DoCs work through the BIOS saviors? or will I have to 
hot-swap flash chips?

Thanks,
joshua

- -- 
Joshua Wise | www.joshuawise.com
GPG Key     | 0xEA80E0B3
Quote       | <lilo> I akilled *@* by mistake
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.2 (GNU/Linux)

iD8DBQE/urRAPn9tWOqA4LMRAoNAAJ9vCO9NyX1mO8ZoQWoSDp9kXVM0xwCeKHtb
emKr1TaOdJ1nYZFQSQ+gFIk=
=Vd/d
-----END PGP SIGNATURE-----



From rminnich at lanl.gov  Tue Nov 18 18:44:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 18:44:00 2003
Subject: About Hardreset on Opteron MB
In-Reply-To: <20031118235706.GB1446@suse.de>
Message-ID: <Pine.LNX.4.44.0311181718000.18676-100000@maxroach.lanl.gov>

I think we should ask for a working cache-as-ram solution for both future 
K8 chips and for the (rumored) K9

ron



From YhLu at tyan.com  Tue Nov 18 18:50:01 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Nov 18 18:50:01 2003
Subject: About Hardreset on Opteron MB
Message-ID: <3174569B9743D511922F00A0C9431423036D2975@TYANWEB>

noisy smbus?

-----????-----
???: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
????: 2003?11?18? 15:17
???: Stefan Reinauer
??: YhLu; 'linuxbios at clustermatic.org'
??: Re: About Hardreset on Opteron MB

Stefan Reinauer <stepan at suse.de> writes:

> * YhLu <YhLu at tyan.com> [031118 22:50]:
> > I have checked the latest code again for Opteron MB. The MB still needs
to
> > reset three times to get it done.
> 
> > Can we only reset the MB only time to make the HT work at the need
> > speed/width?
>  
> It should be enough to set a global variable "reset_needed" (maybe even
> in CMOS) and check this, probably after all device drivers have been
> executed and thus had the chance to set that flag.
> 
> > I mean only enable the reset in 
> > PCI: 00:19.3 init
> > NB: Function 3 Misc Control.. resetting cpu
>   
> When changing the parameters on Solo I always got it to one of the
> reboots - My best result was to get it to the Misc Control reset before
> it would hang hard.

Reducing the number of reboots definitely needs to happen.  I only coded
the way it is currently because that generates obviously correct code.

Right now I am looking at how to reduce problems when a board has
a noisy smbus.  So far I have not seen a single board without one.
In the noisy smbus the more traffic you have the more chances there
are you will have problems because of it.

So it might make sense to set everything up in a very early pass before
memory reset.  Reset the system, and then let the existing resets will
not trigger.

Either that or Stefans delayed scheme.   At this point I am not certain
which will be easier to maintain.  If we do implement the delayed reset
I want to move the memory clear code up into the generic framework so we
don't have to clear memory twice.  But if we can get the resets over with
before we initialize memory we are in better shape.  That plus something
like the kernels quirk interface to handle the various know bits of buggy
hardware and we should be ok.

Eric


From ebiederman at lnxi.com  Tue Nov 18 19:19:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Nov 18 19:19:01 2003
Subject: About Hardreset on Opteron MB
In-Reply-To: <3174569B9743D511922F00A0C9431423036D2975@TYANWEB>
References: <3174569B9743D511922F00A0C9431423036D2975@TYANWEB>
Message-ID: <m3ad6tqir0.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> noisy smbus?

smbus or i2c or iic whichever name you want.

Think what happens when you try to read the serial SPD eeprom on the memory
and the read fails or the smbus locks up.  Basically random peculiar failures.

It depends but when pushing the boot failure rate down from 1 in 100 to 1 in 1000
this is the most common issue that crops up.

This is one of the reason my smbus read code has a timeout on it.

Eric


From ebiederman at lnxi.com  Tue Nov 18 19:20:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Nov 18 19:20:01 2003
Subject: About Hardreset on Opteron MB
In-Reply-To: <Pine.LNX.4.44.0311181718000.18676-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311181718000.18676-100000@maxroach.lanl.gov>
Message-ID: <m365hhqio1.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> I think we should ask for a working cache-as-ram solution for both future 
> K8 chips and for the (rumored) K9

Go right ahead.  If you need leverage Intel has added a PAL opcode for
it to the Itanium.  And the latest Itaniums support it.  And the PEI
stage of EFI will require it or something equivalent.

Eric


From ebiederman at lnxi.com  Tue Nov 18 19:28:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Nov 18 19:28:01 2003
Subject: About Hardreset on Opteron MB
In-Reply-To: <20031118235706.GB1446@suse.de>
References: <3174569B9743D511922F00A0C9431423036D2943@TYANWEB>
	<20031118220007.GA1070@suse.de> <m3y8udw9m9.fsf@maxwell.lnxi.com>
	<20031118235706.GB1446@suse.de>
Message-ID: <m31xs5qiby.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * Eric W. Biederman <ebiederman at lnxi.com> [031119 00:16]:
> > So it might make sense to set everything up in a very early pass before
> > memory reset.  Reset the system, and then let the existing resets will
> > not trigger.
> > 
> > Either that or Stefans delayed scheme.   At this point I am not certain
> > which will be easier to maintain.  If we do implement the delayed reset
> > I want to move the memory clear code up into the generic framework so we
> > don't have to clear memory twice.  But if we can get the resets over with
> > before we initialize memory we are in better shape.  That plus something
> > like the kernels quirk interface to handle the various know bits of buggy
> > hardware and we should be ok.
> 
> Would cache-as-ram be an alternative for AMD64 cpus to move the pretty
> complex ht code to a point as early as possible? 

If I can get a commit from a cpu vendor to support it.

> Romcc really does a
> great job, but IIRC the current ht speed code is where it is now because
> it is really hard to do before there is memory.

In part at the time I was just using the 8 general purpose registers.
So we have a little more room.  It is also where it is because that is
a very good general purpose place to put it.  I have found an
instruction that will allow me to extract or insert a bit field into
one of the xmm registers.  Which may also help.

> I also suspect AMD doing a better job in keeping cache as ram
> initialization code the same over different cpu steppings than Intel
> managed with their P-IV.

Well I wrote that code not Intel.  Which was essentially the problem.

It is a support nightmare to have someone plug in a new processor and have
it totally fail because the cache acts differently.  

I have never tried hard on the AMD processors but the limited attempt
I made had problems because of the additional complexity of TOP_MEM
and the io range registers.

I like the idea.  I just rest easier at night with romcc because I
know so new thing won't cause me to rewrite everything.

Eric



From rminnich at lanl.gov  Tue Nov 18 19:29:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 18 19:29:01 2003
Subject: About Hardreset on Opteron MB
In-Reply-To: <3174569B9743D511922F00A0C9431423036D2975@TYANWEB>
Message-ID: <Pine.LNX.4.44.0311181803380.18676-100000@maxroach.lanl.gov>

On Tue, 18 Nov 2003, YhLu wrote:

> noisy smbus?

electrically noisy.

ron



From jarcher at pobox.com  Tue Nov 18 19:59:00 2003
From: jarcher at pobox.com (Jordan Archer)
Date: Tue Nov 18 19:59:00 2003
Subject: Off by eight.
In-Reply-To: <Pine.LNX.4.44.0311181552200.18676-100000@maxroach.lanl.gov
 >
References: <5.2.1.1.2.20031118144645.00bcfea8@cybermorph.com>
Message-ID: <5.2.1.1.2.20031118173148.00bca8a0@cybermorph.com>

How does the fallback version get executed?  Stepping through the reset 
sequence it looks from my image that that's the default.

Jordan

At 02:52 PM 11/18/2003, ron minnich wrote:
>On Tue, 18 Nov 2003, Jordan Archer wrote:
>
> > I'm pretty sure that it's not 32 bit reset code.  The problem appears if I
> > try to build an image without a fallback.
>
>oh. When I try to build an image without a fallback (this part is
>counterintuitive) I always just build a fallback. Possibly that's the
>wrong thing to do :0)
>
>ron



From ebiederman at lnxi.com  Tue Nov 18 20:46:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Nov 18 20:46:01 2003
Subject: Off by eight.
In-Reply-To: <5.2.1.1.2.20031118173148.00bca8a0@cybermorph.com>
References: <5.2.1.1.2.20031118144645.00bcfea8@cybermorph.com>
	<5.2.1.1.2.20031118173148.00bca8a0@cybermorph.com>
Message-ID: <m3n0atjduq.fsf@maxwell.lnxi.com>

Jordan Archer <jarcher at pobox.com> writes:

> How does the fallback version get executed?  Stepping through the reset sequence
> 
> it looks from my image that that's the default.

Possibly a better term would be failsafe image.

What happens is that if everything looks good the fallback image
hands control to the normal one.  Otherwise it keeps control.

The nice thing is that it is a general purpose technique that can all
be done in software.

Eric


From riskin at esinosoft.com  Tue Nov 18 21:00:00 2003
From: riskin at esinosoft.com (riskin at esinosoft.com)
Date: Tue Nov 18 21:00:00 2003
Subject: Etherboot fail to initialize RTL8139 on linuxbios
Message-ID: <200311190159.hAJ1xZe11940@nwn.definitive.org>

Hello all,

My etherboot(5.0.9) payload on linuxbios failed to 
initialize RTL8139 successfully,but the payload  
inculded RTL8139 codes.

But LinuxBIOS has already initialized the RTL8139
,because when the system was booted from IDE,RTL8139
can work well.

Could somebody help me?Thanks!

riskin


Boot Messages:

LinuxBIOS-1.0.0 Tue Nov 18 13:48:39 CST 2003 starting...
Enabled first bank of RAM: 0x04000000 bytes
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
POST: 0x39
LinuxBIOS-1.0.0 Tue Nov 18 13:48:39 CST 2003 booting...
POST: 0x40
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f
Scanning PCI bus...PCI: pci_scan_bus for bus 0
POST: 0x24
PCI: 00:00.0 [1106/0601]
PCI: 00:01.0 [1106/8601]
PCI: 00:07.0 [1106/0686]
PCI: 00:07.2 [1106/3038]
PCI: 00:07.3 [1106/3038]
PCI: 00:07.4 [1106/3057]
PCI: 00:07.5 [1106/3058]
PCI: 00:07.6 [1106/3068]
PCI: 00:0e.0 [10ec/8139]
POST: 0x25
PCI: pci_scan_bus for bus 1
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=01
POST: 0x55
PCI: pci_scan_bus returning with max=01
POST: 0x55
done
POST: 0x66
Allocating PCI resources...
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
ASSIGN RESOURCES, bus 0
PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io
PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmem
PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem
PCI: 00:07.2 20 <- [0x00001c00 - 0x00001c1f] io
PCI: 00:07.3 20 <- [0x00001c20 - 0x00001c3f] io
PCI: 00:07.5 10 <- [0x00001000 - 0x000010ff] io
PCI: 00:07.5 14 <- [0x00001c40 - 0x00001c43] io
PCI: 00:07.5 18 <- [0x00001c50 - 0x00001c53] io
PCI: 00:07.6 10 <- [0x00001400 - 0x000014ff] io
PCI: 00:0e.0 10 <- [0x00001800 - 0x000018ff] io
PCI: 00:0e.0 14 <- [0xfeb00000 - 0xfeb000ff] mem
ASSIGNED RESOURCES, bus 0
done.
POST: 0x88
Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 cmd <- 07
PCI: 00:07.0 cmd <- 87
PCI: 00:07.2 cmd <- 01
PCI: 00:07.3 cmd <- 01
PCI: 00:07.4 cmd <- 00
PCI: 00:07.5 cmd <- 01
PCI: 00:07.6 cmd <- 01
PCI: 00:0e.0 cmd <- 03
done.
Initializing PCI devices...
PCI devices initialized
POST: 0x89
Disable Cache
Bank4 64MB (MA type 0x8)
Enable Cache
Total 64MB + frame buffer 0MB
Enabling shadow DRAM at 0xC0000-0xFFFFF: done
POST: 0x70
totalram: 64M
Initializing CPU #0
POST: 0x60
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) type: WB
Setting fixed MTRRs(24-88) type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:   64MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
call intel_enable_fixed_mtrr()
call intel_enable_var_mtrr()
Leave setup_mtrrs
POST: 0x6a
done.

Max cpuid index    : 1
Vendor ID          : CentaurHauls
Processor Type     : 0x00
Processor Family   : 0x06
Processor Model    : 0x07
Processor Mask     : 0x00
Processor Stepping : 0x03
Feature flags      : 0x00803035

POST: 0x92

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Disabling local apic...done.
POST: 0x9b
CPU #0 Initialized
Mainboard fixup
IDE enable in reg. 48 is 0x3
set IDE reg. 48 to 0x1
IRQs in reg. 4a are 0x4
setting reg. 4a to 0xc4
enables in reg 0x42 0xc9
enables in reg 0x42 read back as 0x9
IDE enable in reg.1-40 is 0x8
set IDE reg.1-40 to 0xb
IDE enable in reg.1-40 read back is 0xb
enables in reg 0x9 0x8f
enables in reg 0x9 read back as 0x8a
command in reg 0x4 0x80
command in reg 0x4 reads back as 0x7
pci_routing_fixup: dev is 000125e4
setting southbridge
Assigning IRQ 11 to 0:7.2
  Readback = 11
Assigning IRQ 11 to 0:7.3
  Readback = 11
Assigning IRQ 12 to 0:7.5
  Readback = 12
setting ethernet
Assigning IRQ 11 to 0:e.0
  Readback = 11
setting pci slot
pci_routing_fixup: DONE
POST: 0x75
POST: 0x77
POST: 0x91
POST: 0x92
POST: 0x95
Final mainboard fixup
Southbridge fixup
IDE enable in reg. 48 is 0x1
set IDE reg. 48 to 0x1
IRQs in reg. 4a are 0x4
setting reg. 4a to 0xc4
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
IDE enable in reg.1-40 is 0xb
set IDE reg.1-40 to 0xb
IDE enable in reg.1-40 read back is 0xb
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8a
command in reg 0x4 0x7
command in reg 0x4 reads back as 0x7
pci_routing_fixup: dev is 000125e4
setting southbridge
Assigning IRQ 11 to 0:7.2
  Readback = 11
Assigning IRQ 11 to 0:7.3
  Readback = 11
Assigning IRQ 12 to 0:7.5
  Readback = 12
setting ethernet
Assigning IRQ 11 to 0:e.0
  Readback = 11
setting pci slot
pci_routing_fixup: DONE
POST: 0xec
POST: 0x9a
Checking IRQ routing tables...
/home/chenyq/linuxbios/filo+bios8601/bios8601/src/arch/i386/lib/pirq_routing.c:    30:check_pirq_routing_table() - irq_routing_table located at: 0x00009ac0
done.
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...succeed
POST: 0x96
Wrote linuxbios table at: 00000500 - 0000068c  checksum 98

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

POST: 0xf8
    37:init_bytes() - zkernel_start:0xfffc0000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x94000 size 0x7c68 offset 0x80 filesize 0x3474
(cleaned up) New segment addr 0x94000 size 0x7c68 offset 0x80 filesize 0x3474
Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007c68 filesz: 0x0000000000003474
Clearing Segment: addr: 0x0000000000097474 memsz: 0x00000000000047f4
Jumping to boot code at 0x94000
POST: 0xfe
ROM segment 0x7191 length 0xbffe reloc 0x9400
Etherboot 5.0.9 (GPL) ELF for [RTL8139]
routerd etherboot version 1.0.0
Probing...[RTL8139]Found Realtek 8139 ROM address 0x0000
 - to enable rtl8139
rtl8139  old command 263
rtl8139  new command 263
ioaddr 0X1800, addr 00:0D:87:36:2B:ED 10Mbps half-duplex
Cable not connected or other link failure
No adapter found
<sleep>
0

LinuxBIOS-1.0.0 Tue Nov 18 13:48:39 CST 2003 starting...
Enabled first bank of RAM: 0x04000000 bytes
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
POST: 0x39
LinuxBIOS-1.0.0 Tue Nov 18 13:48:39 C
...


From ebiederman at lnxi.com  Tue Nov 18 21:27:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Nov 18 21:27:00 2003
Subject: Porting
In-Reply-To: <200311181907.29633.joshua@joshuawise.com>
References: <200311181907.29633.joshua@joshuawise.com>
Message-ID: <m365hhhxew.fsf@maxwell.lnxi.com>

Joshua Wise <joshua at joshuawise.com> writes:

> Hi all,
> 
> I've got a ABIT KG7-RAID board here that I'd like to port LinuxBIOS to (and a 
> school vacation coming up that I was planning to be bored over.) There used 
> to be a page that had info on that, but my bookmark seems to be broken.
> 
> Can someone tell me what data I will need to gather to determine how much work 
> I'll need to do, and what tools I'll need? I read that you guys use DoCs and 
> BIOS saviors - do the DoCs work through the BIOS saviors? or will I have to 
> hot-swap flash chips?

The DoCs are optional, and actually one of the trickier cases.

lspci is the first step of determining which hardware you have.
The you need to find documentation for the hardware that needs
to be supported.

Eric


From joshua at joshuawise.com  Tue Nov 18 22:18:01 2003
From: joshua at joshuawise.com (Joshua Wise)
Date: Tue Nov 18 22:18:01 2003
Subject: Porting
In-Reply-To: <m365hhhxew.fsf@maxwell.lnxi.com>
References: <200311181907.29633.joshua@joshuawise.com> <m365hhhxew.fsf@maxwell.lnxi.com>
Message-ID: <200311182252.32901.joshua@joshuawise.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On Tuesday 18 November 2003 10:03 pm, Eric W. Biederman wrote:
> The DoCs are optional, and actually one of the trickier cases.
Ah, ok, cool. So I'll just need a BIOS savior and another flash chip? Or is there more?

> lspci is the first step of determining which hardware you have.
> The you need to find documentation for the hardware that needs
> to be supported.

sudo lspci -vv output follows after a few words from our sponsor (or at least a few more questions). I've turned off kmail's wordwrapping, sorry.

I've heard talk of having to look up SuperIOs. Do I need to do this? In the event that I do, where on the board would I be finding these SuperIO controllers? Are they SMT devices typically? BGA? What markings should I be looking for?

00:00.0 Host bridge: Advanced Micro Devices [AMD] AMD-760 [IGD4-1P] System Controller (rev 13)
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
        Latency: 32
        Region 0: Memory at e8000000 (32-bit, prefetchable) [size=64M]
        Region 1: Memory at f7001000 (32-bit, prefetchable) [size=4K]
        Region 2: I/O ports at c000 [disabled] [size=4]
        Capabilities: [a0] AGP version 2.0
                Status: RQ=16 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
                Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP+ GART64- 64bit- FW- Rate=x4

00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-760 [IGD4-1P] AGP Bridge (prog-if 00 [Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
        Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 32
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
        I/O behind bridge: 0000f000-00000fff
        Memory behind bridge: f4000000-f5ffffff
        Prefetchable memory behind bridge: ec000000-f3ffffff
        BridgeCtl: Parity- SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B-

00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 40)
        Subsystem: ABIT Computer Corp. KG7-Lite Mainboard
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP])
        Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 32
        Region 4: I/O ports at c400 [size=16]
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.2 USB Controller: VIA Technologies, Inc. USB (rev 1a) (prog-if 00 [UHCI])
        Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 32, cache line size 08
        Interrupt: pin D routed to IRQ 5
        Region 4: I/O ports at c800 [size=32]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.3 USB Controller: VIA Technologies, Inc. USB (rev 1a) (prog-if 00 [UHCI])
        Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 32, cache line size 08
        Interrupt: pin D routed to IRQ 5
        Region 4: I/O ports at cc00 [size=32]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:07.4 SMBus: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 40)
        Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI]
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Interrupt: pin ? routed to IRQ 9
        Capabilities: [68] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:09.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 07)
        Subsystem: Creative Labs SB Live! 5.1 Model SB0100
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 (500ns min, 5000ns max)
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at d000 [size=32]
        Capabilities: [dc] Power Management version 1
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:09.1 Input device controller: Creative Labs SB Live! MIDI/Game Port (rev 07)
        Subsystem: Creative Labs Gameport Joystick
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 32
        Region 0: I/O ports at d400 [size=8]
        Capabilities: [dc] Power Management version 1
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0d.0 Ethernet controller: Linksys Network Everywhere Fast Ethernet 10/100 model NC100 (rev 11)
        Subsystem: Linksys: Unknown device 0574
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 (63750ns min, 63750ns max), cache line size 08
        Interrupt: pin A routed to IRQ 10
        Region 0: I/O ports at d800 [size=256]
        Region 1: Memory at f7000000 (32-bit, non-prefetchable) [size=1K]
        Expansion ROM at <unassigned> [disabled] [size=128K]
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=100mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:13.0 Unknown mass storage controller: Triones Technologies, Inc. HPT366/368/370/370A/372 (rev 04)
        Subsystem: Triones Technologies, Inc. HPT370A
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 120 (2000ns min, 2000ns max)
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at dc00 [size=8]
        Region 1: I/O ports at e000 [size=4]
        Region 2: I/O ports at e400 [size=8]
        Region 3: I/O ports at e800 [size=4]
        Region 4: I/O ports at ec00 [size=256]
        Expansion ROM at <unassigned> [disabled] [size=128K]
        Capabilities: [60] Power Management version 2
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

01:05.0 VGA compatible controller: nVidia Corporation NV20 [GeForce3 Ti 200] (rev a3) (prog-if 00 [VGA])
        Subsystem: VISIONTEK: Unknown device 0030
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 248 (1250ns min, 250ns max)
        Interrupt: pin A routed to IRQ 12
        Region 0: Memory at f4000000 (32-bit, non-prefetchable) [size=16M]
        Region 1: Memory at ec000000 (32-bit, prefetchable) [size=64M]
        Region 2: Memory at f0000000 (32-bit, prefetchable) [size=512K]
        Expansion ROM at <unassigned> [disabled] [size=64K]
        Capabilities: [60] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [44] AGP version 2.0
                Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA- ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
                Command: RQ=16 ArqSz=0 Cal=0 SBA- AGP+ GART64- 64bit- FW- Rate=x4

> Eric
/joshua

- -- 
Joshua Wise | www.joshuawise.com
GPG Key     | 0xEA80E0B3
Quote       | <lilo> I akilled *@* by mistake
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From ijpriya at hotmail.com  Tue Nov 18 22:49:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Tue Nov 18 22:49:01 2003
Subject: Address mapping?
Message-ID: <BAY2-F54VSZ2wleBC5R000062f2@hotmail.com>

	I am using sc1200. To which physical address does the flash memory and 
sdram mapped in linuxbios?

_________________________________________________________________
Enjoy shopping online? Get this e credit card. 
http://server1.msn.co.in/features/amex/ It cuts cost & adds value!



From cforney at opus.com  Wed Nov 19 03:36:01 2003
From: cforney at opus.com (Craig C Forney)
Date: Wed Nov 19 03:36:01 2003
Subject: Arima HDAMA problems
Message-ID: <000301c3ae7c$fe908e10$0100a8c0@opusone>

Hi,

I haven't been able to get linuxbios working on a standard Arima HDAMA
system for the last month or so (including my latest try this morning
with the latest from sourceforge.net).  It hangs while enumerating the
PCI bus.  A few months ago, it was booting pretty well with FILO (nice
work!!!) Anybody have any ideas on what needs to be fixed?  (There may
be a few characters missing in the listing below.)

Thanks,

Craig Forney
Opus Innovations LLC


LinuxBIOS-1.1.5.0Fallback Wed Nov 19 00:09:00 PST 2003 starting...
setting up resource map....
 AMD8111 southbridge is connected to HT link 00000000
setting up resource map....
done.
Enabling routing table for node 00000000 done.
Enabling SMP settings
setup_remote_node
setup_remote_done
Renaming current temp node to 00000001 done.
Enabling routing table for node 00000001 done.
00000002 nodes initialized.
detect_mp_capabilities: 00000002
coherent_ht_finalize
done
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
disabling dimm01
disabling dimm01
166Mhz
disabling dimm01
Interleaved
RAM: 0x00100000 KB
Ram2.01
Enabling dual channel memory
disabling dimm00
disabling dimm01
disabling dimm00
disabling dimm01
200Mhz
disabling dimm00
disabling dimm01
RAM: 0x00100000 KB
Ram3
ECC enabled
ECC enabled
Initializing memory:  done
Clearing memory: addr 00000000-0000003f
----------------done
Initializing memory:  done
Clearing memory: addr 00000040-0000003f
done
Ram4
PCI: 00:01.00
00: 22 10 50 74 00 00 30 02 12 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f1 01 20 02
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: ff ff 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00
40: 07 00 1f 00 00 00 00 00 02 0c 00 00 00 2c 00 00
50: 00 00 03 00 00 00 04 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 07 b8 03 00 08 00 03 00 0e 00 ff ff 02 00 ff ff
b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 00
c0: 08 00 41 00 20 00 11 00 20 00 00 00 22 00 35 00
d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 08 08 0c 00 08 08 0d 00 0f 0f 13 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:01.01
00: 22 10 51 74 00 00 00 02 01 10 00 08 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:02.00
00: 22 10 50 74 00 00 30 02 12 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f1 01 20 02
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: ff ff 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00
40: 07 00 1f 00 00 00 00 00 00 00 00 00 00 2c 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 07 b8 03 00 10 00 03 00 0e 00 ff ff 02 00 ff ff
b0: 00 00 00 00 00 00 00 00 08 00 00 80 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:02.01
00: 22 10 51 74 00 00 00 02 01 10 00 08 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:03.00
00: 22 10 60 74 00 00 30 02 07 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 02
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 08 f0 83 00 20 00 00 00 d0 00 00 00 22 00 01 00
d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 08 00 0e 00 08 00 11 00 0f 00 1b 00 00 00 00 00
f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.00
00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 10 07 80 01 00 00 00 ff ff 00 00 00 00 00 c0
50: 00 00 00 00 85 01 00 00 44 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 de 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.01
00: 22 10 69 74 00 00 00 02 03 8a 01 01 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00
40: 00 00 00 00 00 00 00 00 a8 a8 a8 a8 ff 00 ff ff
50: 03 03 03 03 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.02
00: 22 10 6a 74 00 00 00 02 02 00 05 0c 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00
40: 02 00 05 0c 00 00 00 00 06 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.03
00: 22 10 6b 74 00 00 80 02 05 00 00 00 00 16 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 d1 00 67 00 00 00 00 20 14 10 00 00 00 00 00
50: 00 80 00 00 0f 00 00 00 01 0f 00 00 00 00 00 00
60: 00 00 00 00 13 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 92 75 03 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.05
00: 22 10 6d 74 00 00 00 02 03 00 01 04 00 00 00 00
10: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.06
00: 22 10 6e 74 00 00 00 02 03 00 03 07 00 00 00 00
10: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:18.00
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00
50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
60: 10 00 01 00 e4 00 00 00 00 80 00 0f 7c 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 08 a0 01 21 20 00 11 00 22 00 75 80 02 00 00 00
90: 56 04 51 02 00 00 00 00 07 00 00 00 00 00 00 00
a0: 08 c0 01 21 20 00 11 11 22 06 75 80 02 00 00 00
b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00
c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00
d0: 13 10 46 02 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:18.01
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 03 00 00 00 00 00 3f 00 03 00 40 00 01 00 3f 00
50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00
60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00
70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 03 00 fc 00 00 ff ff 00
c0: 03 00 00 00 00 f0 ff 01 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:18.02
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 00 00 00 01 10 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 ee e0 03 00 ee e0 03 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 03 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00
90: 00 80 03 08 08 0b 5b 06 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: fd 62 63 66 02 00 00 00 8f 5b b7 d7 e2 91 0f ef
c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 44 e6 05 20 e4 2e 6b 16 dc 4e 10 40 84 1b cc 40
e0: d9 86 0a 20 09 04 5c 10 38 6c 03 48 8c f4 2c 22
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:18.03
00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 c0 00 be fc 07 5f 73 80 7b 46
50: 08 a1 7f 1b 88 00 00 00 16 16 16 00 00 04 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 02 00 00 00 70 0f 00 00 00 83 06 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 01 00 00 e0 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 20 10 00 00 1b 01 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
LinuxBIOS-1.1.5.0Fallback Wed Nov 19 00:09:00 PST 2003 booting...
Finding PCI configuration type.
PCI: Using configuration type 1
Enumerating: AMD K8 Northbridge
Enumerating: AMD K8 Northbridge
Enumerating: AMD K8
Enumerating: AMD K8
Enumerating: AMD 8111
Enumerating: NSC 87360
Enumerating buses...PCI: pci_scan_bus for bus 0
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:19.0 [ffff/ffff] enabled
PCI: 00:19.1 [ffff/ffff/00ffff] has unknown header type ff, ignoring.
PCI: 00:19.1 No device operations




From stepan at suse.de  Wed Nov 19 04:23:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov 19 04:23:00 2003
Subject: Address mapping?
In-Reply-To: <BAY2-F54VSZ2wleBC5R000062f2@hotmail.com>
References: <BAY2-F54VSZ2wleBC5R000062f2@hotmail.com>
Message-ID: <20031119095754.GA3083@suse.de>

* Devi Priya <ijpriya at hotmail.com> [031119 05:23]:
> 	I am using sc1200. To which physical address does the flash memory 
> 	and sdram mapped in linuxbios?

flash is at the usual 0xfffc0000, memory at 0x00000000 I assume.

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From stepan at suse.de  Wed Nov 19 04:31:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov 19 04:31:00 2003
Subject: Off by eight.
In-Reply-To: <m3n0atjduq.fsf@maxwell.lnxi.com>
References: <5.2.1.1.2.20031118144645.00bcfea8@cybermorph.com> <5.2.1.1.2.20031118173148.00bca8a0@cybermorph.com> <m3n0atjduq.fsf@maxwell.lnxi.com>
Message-ID: <20031119100156.GB3083@suse.de>

* Eric W. Biederman <ebiederman at lnxi.com> [031119 03:23]:
> Possibly a better term would be failsafe image.
> 
> What happens is that if everything looks good the fallback image
> hands control to the normal one.  Otherwise it keeps control.
 
Note: IIRC, the "normal" image is called with protected mode already
running, so it needs a different startup code (entry32.s instead of
entry16.s?) 
Also, the failsafe image does not do cmos option handling afair?

Stefan

  
-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From ebiederman at lnxi.com  Wed Nov 19 04:54:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Nov 19 04:54:01 2003
Subject: Off by eight.
In-Reply-To: <20031119100156.GB3083@suse.de>
References: <5.2.1.1.2.20031118144645.00bcfea8@cybermorph.com>
	<5.2.1.1.2.20031118173148.00bca8a0@cybermorph.com>
	<m3n0atjduq.fsf@maxwell.lnxi.com> <20031119100156.GB3083@suse.de>
Message-ID: <m37k1w1wgj.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * Eric W. Biederman <ebiederman at lnxi.com> [031119 03:23]:
> > Possibly a better term would be failsafe image.
> > 
> > What happens is that if everything looks good the fallback image
> > hands control to the normal one.  Otherwise it keeps control.
>  
> Note: IIRC, the "normal" image is called with protected mode already
> running, so it needs a different startup code (entry32.s instead of
> entry16.s?) 

Yes.  

> Also, the failsafe image does not do cmos option handling afair?

Correct.  That is so the failsafe image will do a known thing.

Right now with etherboot I have been able to keep the two
fairly symmetrical.  But it is my intention to start sticking
a kernel in the flash now that 512KiB byte flash chips and
above are getting common.  Etherboot was to a large extent
about getting something small enough that it could always
be used.  Once I start sticking a kernel in flash the normal
image should start picking up some capabilities not available
otherwise.

Right now the big benefit of having the two images is that
once you have fallback image working, you can continue development
without the need to even remove ROM chips.

Eric


From stepan at suse.de  Wed Nov 19 05:11:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov 19 05:11:00 2003
Subject: PC2700 and funny effects.
Message-ID: <20031119104612.GA3354@suse.de>

When using PC2700 ECC memory in a Solo machine, it seems to clear
only the first 31 bytes(?) and then repeat jumping to it's rammed copy
endlessly


SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
disabling dimm01                                                                
disabling dimm01                                                                
166Mhz                                                                          
disabling dimm01                                                                
RAM: 0x00080000 KB                                                              
Ram3                                                                            
ECC enabled                                                                     
Initializing memory:  done                                                      
Clearing memory: addr 00000000-0000001f                                         
--------done                                                                    
Copying LinuxBIOS to ram.                                                       
Jumping to LinuxBIOS.                                                           
Copying LinuxBIOS to ram.                                                       
Jumping to LinuxBIOS.                                                           
Copying LinuxBIOS to ram.                                                       
Jumping to LinuxBIOS.                                                           
[ad nauseum]

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From ijpriya at hotmail.com  Wed Nov 19 06:32:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Wed Nov 19 06:32:01 2003
Subject: RAMBASE and ROMBASE?
Message-ID: <BAY2-F67znOxbkK0rGm00016900@hotmail.com>

Hi,
      What address does _RAMBASE and _ROMBASE represent?

_________________________________________________________________
Garfield on your mobile. Download now. http://server1.msn.co.in/sp03/gprs/ 
How cool can life get?



From ijpriya at hotmail.com  Wed Nov 19 06:35:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Wed Nov 19 06:35:01 2003
Subject: RAMBASE and ROMBASE?
Message-ID: <BAY2-F48bOLTCwCBhc100002683@hotmail.com>

Hi,
      What address does _RAMBASE and _ROMBASE represent?

_________________________________________________________________
Apply to 50,000 jobs now. http://go.msnserver.com/IN/36715.asp Post your CV 
on naukri.com today.



From stepan at suse.de  Wed Nov 19 06:51:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov 19 06:51:00 2003
Subject: RAMBASE and ROMBASE?
In-Reply-To: <BAY2-F67znOxbkK0rGm00016900@hotmail.com>
References: <BAY2-F67znOxbkK0rGm00016900@hotmail.com>
Message-ID: <20031119122258.GA6457@suse.de>

* Devi Priya <ijpriya at hotmail.com> [031119 13:06]:
> Hi,
>      What address does _RAMBASE and _ROMBASE represent?

_RAMBASE is the lowest address used by LinuxBIOS i guess.
_ROMBASE is the address of the flash rom.

I think the names are pretty expressive.

You find a description of all available options in 
freebios2/src/config/Options.lb btw.

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From ijpriya at hotmail.com  Wed Nov 19 08:07:00 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Wed Nov 19 08:07:00 2003
Subject: RAMBASE and ROMBASE?
Message-ID: <BAY2-F7o6AmX3qrB0Xn000022bd@hotmail.com>

Hi,
	RAMBASE address is given as 0x4000. Then if it is the lowest RAM address 
used by linuxbios. Is it right? If so the memory sizing in 
freebios/src/northbridge/raminit.inc is done based on address 0. The lower 
address ic 0 or 0x4000. I have an 32 MB SDRAM anf 4MB flash memory. Then in 
hardware, the SDRAM must be mapped from 0x0000000-0x1FFFFFF and Flash memory 
from 0xFFFFFFFF-0xFFC00000. Am i right at this point? Plz give me suggestion 
on this.


>From: Stefan Reinauer <stepan at suse.de>
>To: Devi Priya <ijpriya at hotmail.com>
>CC: linuxbios at clustermatic.org
>Subject: Re: RAMBASE and ROMBASE?
>Date: Wed, 19 Nov 2003 13:22:58 +0100
>
>* Devi Priya <ijpriya at hotmail.com> [031119 13:06]:
> > Hi,
> >      What address does _RAMBASE and _ROMBASE represent?
>
>_RAMBASE is the lowest address used by LinuxBIOS i guess.
>_ROMBASE is the address of the flash rom.
>
>I think the names are pretty expressive.
>
>You find a description of all available options in
>freebios2/src/config/Options.lb btw.
>
>   Stefan
>
>--
>      Stefan Reinauer, SUSE LINUX AG
>Teamleader Architecture Development
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios

_________________________________________________________________
Garfield on your mobile. Download now. http://server1.msn.co.in/sp03/gprs/ 
How cool can life get?



From stepan at suse.de  Wed Nov 19 08:43:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov 19 08:43:01 2003
Subject: RAMBASE and ROMBASE?
In-Reply-To: <BAY2-F7o6AmX3qrB0Xn000022bd@hotmail.com>
References: <BAY2-F7o6AmX3qrB0Xn000022bd@hotmail.com>
Message-ID: <20031119141754.GB6700@suse.de>

* Devi Priya <ijpriya at hotmail.com> [031119 14:42]:
> Hi,
> 	RAMBASE address is given as 0x4000. Then if it is the lowest RAM 
> 	address used by linuxbios. Is it right? If so the memory sizing in 
> freebios/src/northbridge/raminit.inc is done based on address 0. The lower 
> address ic 0 or 0x4000. I have an 32 MB SDRAM anf 4MB flash memory. Then in 
> hardware, the SDRAM must be mapped from 0x0000000-0x1FFFFFF and Flash 
> memory from 0xFFFFFFFF-0xFFC00000. Am i right at this point? Plz give me 
> suggestion on this.

Is the flash 4 MBit or 4 MByte? What part are you using?
Yes your assumption sounds right, if your part is really 4MByte, which
is doubtable. But I still don't exactly recognize your problem..

Best regards,
  Stefan Reinauer
  
-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From stepan at suse.de  Wed Nov 19 08:52:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov 19 08:52:01 2003
Subject: LinuxBIOS and 4G+ memory
Message-ID: <20031119142631.GC6700@suse.de>

Hi,

does LinuxBIOS on Opteron cleanly handle 4+G of memory? I have a machine
with 4G here for the first time, but I seem to end up with some of the
memory missing.

[..]
totalram: 3840M

How would Linux clear ECC memory >4G in this case? using PAE? Long mode
is not available yet..

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From jarcher at pobox.com  Wed Nov 19 10:36:01 2003
From: jarcher at pobox.com (jarcher at pobox.com)
Date: Wed Nov 19 10:36:01 2003
Subject: Off by eight.
Message-ID: <5.2.1.1.2.20031119080857.03c2ada0@cybermorph.com>

I think of the fallback as the recovery if the normal fails.  This is kind 
of an ideological point, but shouldn't the fallback be a minimal recovery 
version?

Jordan


At 03:52 PM 11/18/2003 -0700, you wrote:
>On Tue, 18 Nov 2003, Jordan Archer wrote:
>
> > I'm pretty sure that it's not 32 bit reset code.  The problem appears if I
> > try to build an image without a fallback.
>
>oh. When I try to build an image without a fallback (this part is
>counterintuitive) I always just build a fallback. Possibly that's the
>wrong thing to do :0)
>
>ron
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
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From linuxbios at xdr.com  Wed Nov 19 11:17:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Wed Nov 19 11:17:00 2003
Subject: Etherboot fail to initialize RTL8139 on linuxbios
Message-ID: <200311191652.hAJGqQ3j004985@xdr.com>

riskin at esinosoft.com wrote:
>My etherboot(5.0.9) payload on linuxbios failed to 
>initialize RTL8139 successfully,but the payload  

The only inialization linuxbios would need to do is assign the 8139 an
IRQ. But etherboot uses polling and doesn't depend on interrupts.
The problem you're experiencing isn't something I can recall, but this
patch might help. The etherboot driver for the 8139 and linux itself have
the meaning of the interrupt status bits wrong.
diff -Nur etherboot-5.0.10/src/misc.c etherboot-5.0.10-new/src/misc.c
--- etherboot-5.0.10/src/misc.c	Sun Mar  9 03:17:15 2003
+++ etherboot-5.0.10-new/src/misc.c	Wed Jul 16 09:45:26 2003
@@ -282,7 +282,7 @@
 enum { Disable_A20 = 0x2400, Enable_A20 = 0x2401, Query_A20_Status = 0x2402,
 	Query_A20_Support = 0x2403 } Int0x15Arg;
 
-#if defined(PCBIOS) && !defined(IBM_L40)
+#if defined(TAGGED_IMAGE) || (defined(PCBIOS) && !defined(IBM_L40))
 static void empty_8042(void)
 {
 	unsigned long time;
diff -Nur etherboot-5.0.10/src/rtl8139.c etherboot-5.0.10-new/src/rtl8139.c
--- etherboot-5.0.10/src/rtl8139.c	Tue Jul 23 17:50:53 2002
+++ etherboot-5.0.10-new/src/rtl8139.c	Wed Jul 16 09:45:42 2003
@@ -183,7 +183,6 @@
 static int rtl_poll(struct nic *nic);
 static void rtl_disable(struct nic*);
 
-
 struct nic *rtl8139_probe(struct nic *nic, unsigned short *probeaddrs,
 	struct pci_device *pci)
 {
@@ -252,6 +251,16 @@
 #define EE_READ_CMD     (6)
 #define EE_ERASE_CMD    (7)
 
+static unsigned short cintr=0;
+static unsigned short getstatus(void)
+{
+	return cintr|=inw(ioaddr + IntrStatus);
+}
+static void setstatus(unsigned short val)
+{
+	cintr&=~val;
+}
+
 static int read_eeprom(int location, int addr_len)
 {
 	int i;
@@ -340,7 +349,7 @@
 static void rtl_transmit(struct nic *nic, const char *destaddr,
 	unsigned int type, unsigned int len, const char *data)
 {
-	unsigned int status, to, nstype;
+	unsigned int status, to, nstype, st;
 	unsigned long txstatus;
 
 	/* nstype assignment moved up here to avoid gcc 3.0.3 compiler bug */
@@ -365,14 +374,15 @@
 	outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
 		ioaddr + TxStatus0 + cur_tx*4);
 
+	st= currticks();
 	to = currticks() + RTL_TIMEOUT;
 
 	do {
-		status = inw(ioaddr + IntrStatus);
+		status = getstatus();
 		/* Only acknlowledge interrupt sources we can properly handle
 		 * here - the RxOverflow/RxFIFOOver MUST be handled in the
 		 * rtl_poll() function.  */
-		outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
+		setstatus(status & (TxOK | TxErr | PCIErr));
 		if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
 	} while (currticks() < to);
 
@@ -382,12 +392,12 @@
 		cur_tx = (cur_tx + 1) % NUM_TX_DESC;
 #ifdef	DEBUG_TX
 		printf("tx done (%d ticks), status %hX txstatus %X\n",
-			to-currticks(), status, txstatus);
+			currticks()-st, status, txstatus);
 #endif
 	} else {
 #ifdef	DEBUG_TX
 		printf("tx timeout/error (%d ticks), status %hX txstatus %X\n",
-			currticks()-to, status, txstatus);
+			currticks()-st, status, txstatus);
 #endif
 		rtl_reset(nic);
 	}
@@ -403,9 +413,9 @@
 		return 0;
 	}
 
-	status = inw(ioaddr + IntrStatus);
+	status = getstatus();
 	/* See below for the rest of the interrupt acknowledges.  */
-	outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
+	setstatus(status & ~(RxFIFOOver | RxOverflow | RxOK));
 
 #ifdef	DEBUG_RX
 	printf("rtl_poll: int %hX ", status);
@@ -449,7 +459,7 @@
 	/* See RTL8139 Programming Guide V0.1 for the official handling of
 	 * Rx overflow situations.  The document itself contains basically no
 	 * usable information, except for a few exception handling rules.  */
-	outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
+	setstatus(status & (RxFIFOOver | RxOverflow | RxOK));
 	return 1;
 }
 
diff -Nur etherboot-5.0.10/src/timer.c etherboot-5.0.10-new/src/timer.c
--- etherboot-5.0.10/src/timer.c	Sat Mar 22 11:52:25 2003
+++ etherboot-5.0.10-new/src/timer.c	Wed Jul 16 09:45:46 2003
@@ -138,6 +138,8 @@
 {
 	unsigned long clocks_high, clocks_low;
 	unsigned long currticks;
+
+setup_timers();
 	/* Read the Time Stamp Counter */
 	rdtsc(clocks_low, clocks_high);




From YhLu at tyan.com  Wed Nov 19 12:07:01 2003
From: YhLu at tyan.com (YhLu)
Date: Wed Nov 19 12:07:01 2003
Subject: Arima HDAMA problems
Message-ID: <3174569B9743D511922F00A0C943142303990209@TYANWEB>

You may need to get the latest version from 

http://snapshots.linuxbios.org/

-----????-----
???: Craig C Forney [mailto:cforney at opus.com] 
????: 2003?11?19? 1:10
???: Linuxbios at clustermatic.org
??: Arima HDAMA problems


Hi,

I haven't been able to get linuxbios working on a standard Arima HDAMA
system for the last month or so (including my latest try this morning
with the latest from sourceforge.net).  It hangs while enumerating the
PCI bus.  A few months ago, it was booting pretty well with FILO (nice
work!!!) Anybody have any ideas on what needs to be fixed?  (There may
be a few characters missing in the listing below.)

Thanks,

Craig Forney
Opus Innovations LLC


LinuxBIOS-1.1.5.0Fallback Wed Nov 19 00:09:00 PST 2003 starting...
setting up resource map....
 AMD8111 southbridge is connected to HT link 00000000
setting up resource map....
done.
Enabling routing table for node 00000000 done.
Enabling SMP settings
setup_remote_node
setup_remote_done
Renaming current temp node to 00000001 done.
Enabling routing table for node 00000001 done.
00000002 nodes initialized.
detect_mp_capabilities: 00000002
coherent_ht_finalize
done
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
disabling dimm01
disabling dimm01
166Mhz
disabling dimm01
Interleaved
RAM: 0x00100000 KB
Ram2.01
Enabling dual channel memory
disabling dimm00
disabling dimm01
disabling dimm00
disabling dimm01
200Mhz
disabling dimm00
disabling dimm01
RAM: 0x00100000 KB
Ram3
ECC enabled
ECC enabled
Initializing memory:  done
Clearing memory: addr 00000000-0000003f
----------------done
Initializing memory:  done
Clearing memory: addr 00000040-0000003f
done
Ram4
PCI: 00:01.00
00: 22 10 50 74 00 00 30 02 12 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f1 01 20 02
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: ff ff 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00
40: 07 00 1f 00 00 00 00 00 02 0c 00 00 00 2c 00 00
50: 00 00 03 00 00 00 04 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 07 b8 03 00 08 00 03 00 0e 00 ff ff 02 00 ff ff
b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 00
c0: 08 00 41 00 20 00 11 00 20 00 00 00 22 00 35 00
d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 08 08 0c 00 08 08 0d 00 0f 0f 13 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:01.01
00: 22 10 51 74 00 00 00 02 01 10 00 08 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:02.00
00: 22 10 50 74 00 00 30 02 12 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f1 01 20 02
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: ff ff 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00
40: 07 00 1f 00 00 00 00 00 00 00 00 00 00 2c 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 07 b8 03 00 10 00 03 00 0e 00 ff ff 02 00 ff ff
b0: 00 00 00 00 00 00 00 00 08 00 00 80 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:02.01
00: 22 10 51 74 00 00 00 02 01 10 00 08 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:03.00
00: 22 10 60 74 00 00 30 02 07 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 02
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 08 f0 83 00 20 00 00 00 d0 00 00 00 22 00 01 00
d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 08 00 0e 00 08 00 11 00 0f 00 1b 00 00 00 00 00
f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.00
00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 10 07 80 01 00 00 00 ff ff 00 00 00 00 00 c0
50: 00 00 00 00 85 01 00 00 44 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 de 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.01
00: 22 10 69 74 00 00 00 02 03 8a 01 01 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00
40: 00 00 00 00 00 00 00 00 a8 a8 a8 a8 ff 00 ff ff
50: 03 03 03 03 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.02
00: 22 10 6a 74 00 00 00 02 02 00 05 0c 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00
40: 02 00 05 0c 00 00 00 00 06 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.03
00: 22 10 6b 74 00 00 80 02 05 00 00 00 00 16 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 d1 00 67 00 00 00 00 20 14 10 00 00 00 00 00
50: 00 80 00 00 0f 00 00 00 01 0f 00 00 00 00 00 00
60: 00 00 00 00 13 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 92 75 03 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.05
00: 22 10 6d 74 00 00 00 02 03 00 01 04 00 00 00 00
10: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:04.06
00: 22 10 6e 74 00 00 00 02 03 00 03 07 00 00 00 00
10: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:18.00
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00
50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
60: 10 00 01 00 e4 00 00 00 00 80 00 0f 7c 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 08 a0 01 21 20 00 11 00 22 00 75 80 02 00 00 00
90: 56 04 51 02 00 00 00 00 07 00 00 00 00 00 00 00
a0: 08 c0 01 21 20 00 11 11 22 06 75 80 02 00 00 00
b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00
c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00
d0: 13 10 46 02 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:18.01
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 03 00 00 00 00 00 3f 00 03 00 40 00 01 00 3f 00
50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00
60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00
70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 03 00 fc 00 00 ff ff 00
c0: 03 00 00 00 00 f0 ff 01 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:18.02
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 00 00 00 01 10 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 ee e0 03 00 ee e0 03 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 03 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00
90: 00 80 03 08 08 0b 5b 06 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: fd 62 63 66 02 00 00 00 8f 5b b7 d7 e2 91 0f ef
c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 44 e6 05 20 e4 2e 6b 16 dc 4e 10 40 84 1b cc 40
e0: d9 86 0a 20 09 04 5c 10 38 6c 03 48 8c f4 2c 22
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:18.03
00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 c0 00 be fc 07 5f 73 80 7b 46
50: 08 a1 7f 1b 88 00 00 00 16 16 16 00 00 04 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 02 00 00 00 70 0f 00 00 00 83 06 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 01 00 00 e0 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 20 10 00 00 1b 01 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
LinuxBIOS-1.1.5.0Fallback Wed Nov 19 00:09:00 PST 2003 booting...
Finding PCI configuration type.
PCI: Using configuration type 1
Enumerating: AMD K8 Northbridge
Enumerating: AMD K8 Northbridge
Enumerating: AMD K8
Enumerating: AMD K8
Enumerating: AMD 8111
Enumerating: NSC 87360
Enumerating buses...PCI: pci_scan_bus for bus 0
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:19.0 [ffff/ffff] enabled
PCI: 00:19.1 [ffff/ffff/00ffff] has unknown header type ff, ignoring.
PCI: 00:19.1 No device operations


_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From rminnich at lanl.gov  Wed Nov 19 13:42:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 19 13:42:01 2003
Subject: Arima HDAMA problems
In-Reply-To: <000301c3ae7c$fe908e10$0100a8c0@opusone>
Message-ID: <Pine.LNX.4.44.0311191216250.28541-100000@maxroach.lanl.gov>

Things are badly broken for K8 right now, our plan here next week is to 
try to fix this.

ron



From rminnich at lanl.gov  Wed Nov 19 14:35:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 19 14:35:01 2003
Subject: Off by eight.
In-Reply-To: <5.2.1.1.2.20031119080857.03c2ada0@cybermorph.com>
Message-ID: <Pine.LNX.4.44.0311191309280.28541-100000@maxroach.lanl.gov>

On Wed, 19 Nov 2003 jarcher at pobox.com wrote:

> I think of the fallback as the recovery if the normal fails.  This is kind 
> of an ideological point, but shouldn't the fallback be a minimal recovery 
> version?

why? the fallback could be one of two linux kernels. It all depends on how 
mmuch space is available.

ron



From jarcher at pobox.com  Wed Nov 19 14:44:00 2003
From: jarcher at pobox.com (Jordan Archer)
Date: Wed Nov 19 14:44:00 2003
Subject: Off by eight.
In-Reply-To: <Pine.LNX.4.44.0311191309280.28541-100000@maxroach.lanl.gov
 >
References: <5.2.1.1.2.20031119080857.03c2ada0@cybermorph.com>
Message-ID: <5.2.1.1.2.20031119121611.02403f50@cybermorph.com>

Conceptually I break it down into two separate pieces.  One being the boot 
portion and one being the payload.  The different kernels make sense as an 
option on which payload is run.  The boot portion should be pretty 
stable.  And the fallback boot would deal with a failed boot update.

Jordan

At 12:09 PM 11/19/2003, you wrote:
>On Wed, 19 Nov 2003 jarcher at pobox.com wrote:
>
> > I think of the fallback as the recovery if the normal fails.  This is kind
> > of an ideological point, but shouldn't the fallback be a minimal recovery
> > version?
>
>why? the fallback could be one of two linux kernels. It all depends on how
>mmuch space is available.
>
>ron



From rminnich at lanl.gov  Wed Nov 19 18:32:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 19 18:32:01 2003
Subject: Off by eight.
In-Reply-To: <5.2.1.1.2.20031119121611.02403f50@cybermorph.com>
Message-ID: <Pine.LNX.4.44.0311191706170.28541-100000@maxroach.lanl.gov>

the determination of whether to do a "fallback" or not is done in the 
"fallback". I have a writeup on this which I will get released and post.

ron



From riskin at esinosoft.com  Thu Nov 20 02:11:00 2003
From: riskin at esinosoft.com (riskin at esinosoft.com)
Date: Thu Nov 20 02:11:00 2003
Subject: Etherboot fail to initialize RTL8139 on linuxbios 
Message-ID: <200311200710.hAK7ARe17725@nwn.definitive.org>

Thanks!This patch can fix the issue.

riskin

>The only inialization linuxbios would need to do is assign the 8139 an
>IRQ. But etherboot uses polling and doesn't depend on interrupts.
>The problem you're experiencing isn't something I can recall, but this
>patch might help. The etherboot driver for the 8139 and linux itself have
>the meaning of the interrupt status bits wrong.
>diff -Nur etherboot-5.0.10/src/misc.c etherboot-5.0.10-new/src/misc.c
>--- etherboot-5.0.10/src/misc.c	Sun Mar  9 03:17:15 2003
>+++ etherboot-5.0.10-new/src/misc.c	Wed Jul 16 09:45:26 2003
>@@ -282,7 +282,7 @@
> enum { Disable_A20 = 0x2400, Enable_A20 = 0x2401, Query_A20_Status = 0x2402,
> 	Query_A20_Support = 0x2403 } Int0x15Arg;
> 
>-#if defined(PCBIOS) && !defined(IBM_L40)
>+#if defined(TAGGED_IMAGE) || (defined(PCBIOS) && !defined(IBM_L40))
> static void empty_8042(void)
> {
> 	unsigned long time;
>diff -Nur etherboot-5.0.10/src/rtl8139.c etherboot-5.0.10-new/src/rtl8139.c
>--- etherboot-5.0.10/src/rtl8139.c	Tue Jul 23 17:50:53 2002
>+++ etherboot-5.0.10-new/src/rtl8139.c	Wed Jul 16 09:45:42 2003
>@@ -183,7 +183,6 @@
> static int rtl_poll(struct nic *nic);
> static void rtl_disable(struct nic*);
> 
>-
> struct nic *rtl8139_probe(struct nic *nic, unsigned short *probeaddrs,
> 	struct pci_device *pci)
> {
>@@ -252,6 +251,16 @@
> #define EE_READ_CMD     (6)
> #define EE_ERASE_CMD    (7)
> 
>+static unsigned short cintr=0;
>+static unsigned short getstatus(void)
>+{
>+	return cintr|=inw(ioaddr + IntrStatus);
>+}
>+static void setstatus(unsigned short val)
>+{
>+	cintr&=~val;
>+}
>+
> static int read_eeprom(int location, int addr_len)
> {
> 	int i;
>@@ -340,7 +349,7 @@
> static void rtl_transmit(struct nic *nic, const char *destaddr,
> 	unsigned int type, unsigned int len, const char *data)
> {
>-	unsigned int status, to, nstype;
>+	unsigned int status, to, nstype, st;
> 	unsigned long txstatus;
> 
> 	/* nstype assignment moved up here to avoid gcc 3.0.3 compiler bug */
>@@ -365,14 +374,15 @@
> 	outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
> 		ioaddr + TxStatus0 + cur_tx*4);
> 
>+	st= currticks();
> 	to = currticks() + RTL_TIMEOUT;
> 
> 	do {
>-		status = inw(ioaddr + IntrStatus);
>+		status = getstatus();
> 		/* Only acknlowledge interrupt sources we can properly handle
> 		 * here - the RxOverflow/RxFIFOOver MUST be handled in the
> 		 * rtl_poll() function.  */
>-		outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
>+		setstatus(status & (TxOK | TxErr | PCIErr));
> 		if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
> 	} while (currticks() < to);
> 
>@@ -382,12 +392,12 @@
> 		cur_tx = (cur_tx + 1)  NUM_TX_DESC;
> #ifdef	DEBUG_TX
> 		printf("tx done (d ticks), status hX txstatus \n",
>-			to-currticks(), status, txstatus);
>+			currticks()-st, status, txstatus);
> #endif
> 	} else {
> #ifdef	DEBUG_TX
> 		printf("tx timeout/error (d ticks), status hX txstatus \n",
>-			currticks()-to, status, txstatus);
>+			currticks()-st, status, txstatus);
> #endif
> 		rtl_reset(nic);
> 	}
>@@ -403,9 +413,9 @@
> 		return 0;
> 	}
> 
>-	status = inw(ioaddr + IntrStatus);
>+	status = getstatus();
> 	/* See below for the rest of the interrupt acknowledges.  */
>-	outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
>+	setstatus(status & ~(RxFIFOOver | RxOverflow | RxOK));
> 
> #ifdef	DEBUG_RX
> 	printf("rtl_poll: int hX ", status);
>@@ -449,7 +459,7 @@
> 	/* See RTL8139 Programming Guide V0.1 for the official handling of
> 	 * Rx overflow situations.  The document itself contains basically no
> 	 * usable information, except for a few exception handling rules.  */
>-	outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
>+	setstatus(status & (RxFIFOOver | RxOverflow | RxOK));
> 	return 1;
> }
> 
>diff -Nur etherboot-5.0.10/src/timer.c etherboot-5.0.10-new/src/timer.c
>--- etherboot-5.0.10/src/timer.c	Sat Mar 22 11:52:25 2003
>+++ etherboot-5.0.10-new/src/timer.c	Wed Jul 16 09:45:46 2003
>@@ -138,6 +138,8 @@
> {
> 	unsigned long clocks_high, clocks_low;
> 	unsigned long currticks;
>+
>+setup_timers();
> 	/* Read the Time Stamp Counter */
> 	rdtsc(clocks_low, clocks_high);


From stepan at suse.de  Thu Nov 20 05:13:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Nov 20 05:13:01 2003
Subject: AMD64: LDTSTOP vs hard reset
Message-ID: <20031120104802.GA10480@suse.de>

Hi,

In addition to lowering the number of resets it would also be possible
to use an LDTSTOP (as I implemented it in older versions of the CVS) 
at least when doing the hypertransport link changes. 
I know that this does not work with some preproduction CPUs, but I don't
think that would really matter. BUT: Could we get rid of all CPU resets
when doing an LDTSTOP assertion (It's a lot quicker than a hard reset)
or would we still need to reset the CPU for some other reasons?


  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From stepan at suse.de  Thu Nov 20 06:35:00 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Nov 20 06:35:00 2003
Subject: [announce] LinuxBIOS on AMD64
Message-ID: <20031120120949.GA10860@suse.de>

Hi,

I wrote a paper on LinuxBIOS on the AMD64 platform that covers
some aspects on the following topics:

 * image configuration
 * porting LinuxBIOS to new AMD64 motherboards
 * debugging and tweaking hints
 * some internals 

The document is available at 
http://www.openbios.org/docs/LinuxBIOS-AMD64.pdf

I am very glad to announce that this document is released under the GPL,
so please go ahead and use it, spread it, change it. But please do
submit your changes back so everybody can benefit. I suggest putting the
document in the freebios2 documentation subdirectory, if nobody objects.
(What is the preferred file format for that? TeX? The document was
initially created using OpenOffice 1.1 8)

Don't hesitate to make suggestions on improvement, report typos, badly
written english, or whatever comes to your mind when reading the paper.

  Stefan


-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From stepan at suse.de  Thu Nov 20 07:12:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Nov 20 07:12:01 2003
Subject: AMD64 Solo Hang - news
Message-ID: <20031120124642.GA11352@suse.de>

Hi,

it seems that the Solo motherboard is the only motherboard tested so far
that is based on an Athlon64 instead of Opteron CPUs..

The following code in src/northbridge/amd/amdk8/misc_control.c relies on
more than one hypertransport link being available:

        cmd = pci_read_config32(dev, 0xdc);
        if((cmd & 0x0000ff00) != 0x02500) {
                cmd &= 0xffff00ff;
                cmd |= 0x00002500;
                pci_write_config32(dev, 0xdc, cmd );
                printk_debug("resetting cpu\n");
                hard_reset();
        }

This implicitly changes CPU0 Link1 FIFO Read Pointer Optimization, not
taking into regard that LDT1 might not be there.

It seems this code should rather check all links to see whether they are
connected and optimize _all_ of the connected.

Is the CPU reset here really needed for the setting to become active?
The BKDG does not state this explicitly ... (Therefore I vote for
removing it)

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From steve at nexpath.com  Thu Nov 20 11:58:01 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Thu Nov 20 11:58:01 2003
Subject: [announce] LinuxBIOS on AMD64
In-Reply-To: <20031120120949.GA10860@suse.de>
References: <20031120120949.GA10860@suse.de>
Message-ID: <3FBCFCF3.3010504@nexpath.com>

> The document is available at 
> http://www.openbios.org/docs/LinuxBIOS-AMD64.pdf
> 
> I suggest putting the
> document in the freebios2 documentation subdirectory, if nobody objects.
> (What is the preferred file format for that? TeX? The document was
> initially created using OpenOffice 1.1 8)
>   Stefan

Thanks for the excellent documentation.  I am not a big fan of Tex or 
troff, other people may be. I think OpenOffice is fine.  Other projects 
I work on code docs in plain HTML as well.  Where something like Word is 
used (and I assume compatible to OpenOffice), we use the rtf file 
format, so cvs can do its thing.

-Steve




From rminnich at lanl.gov  Thu Nov 20 12:05:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Nov 20 12:05:00 2003
Subject: [announce] LinuxBIOS on AMD64
In-Reply-To: <3FBCFCF3.3010504@nexpath.com>
Message-ID: <Pine.LNX.4.44.0311201039220.3611-100000@maxroach.lanl.gov>

I prefer latex for this, as cvs works on it well. 

I can't stand open office, sorry.

ron



From steve at nexpath.com  Thu Nov 20 12:20:01 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Thu Nov 20 12:20:01 2003
Subject: [announce] LinuxBIOS on AMD64
In-Reply-To: <Pine.LNX.4.44.0311201039220.3611-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311201039220.3611-100000@maxroach.lanl.gov>
Message-ID: <3FBD024B.5060300@nexpath.com>

ron minnich wrote:

> I prefer latex for this, as cvs works on it well. 
> 
> I can't stand open office, sorry.

Oh well I tried.  I learned troff long ago, and there isn't room in my 
brain for another typsetting language.  Brain cell death from old age 
and beer, perhaps.

-Steve




From rminnich at lanl.gov  Thu Nov 20 12:23:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Nov 20 12:23:01 2003
Subject: [announce] LinuxBIOS on AMD64
In-Reply-To: <3FBD024B.5060300@nexpath.com>
Message-ID: <Pine.LNX.4.44.0311201057210.3611-100000@maxroach.lanl.gov>

On Thu, 20 Nov 2003, Steve Gehlbach wrote:

> > I prefer latex for this, as cvs works on it well. 
> Oh well I tried.  I learned troff long ago, and there isn't room in my 
> brain for another typsetting language.  Brain cell death from old age 
> and beer, perhaps.
> 

I should be clearer. I prefer latex for this. That doesn't mean I 
actually *like* latex :-)

I do my real pubs in Frame on an ibook.

ron



From steve at nexpath.com  Thu Nov 20 12:30:01 2003
From: steve at nexpath.com (Steve Gehlbach)
Date: Thu Nov 20 12:30:01 2003
Subject: [announce] LinuxBIOS on AMD64
In-Reply-To: <Pine.LNX.4.44.0311201057210.3611-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311201057210.3611-100000@maxroach.lanl.gov>
Message-ID: <3FBD04A4.9000501@nexpath.com>

ron minnich wrote:

> I should be clearer. I prefer latex for this. That doesn't mean I 
> actually *like* latex :-)
> 
> I do my real pubs in Frame on an ibook.

Cool, on that we can agree, my real pubs are also done in Frame.  I 
didn't think that many people used Frame.  Adobe refuses to put it out 
for Linux, and it is not clear what the future of it is.  Recently the 
whole dev team was moved to India, much to the dismay of a few dozen 
unemployed sofware engrs in silicon valley.

-Steve



From YhLu at tyan.com  Thu Nov 20 12:51:01 2003
From: YhLu at tyan.com (YhLu)
Date: Thu Nov 20 12:51:01 2003
Subject: [announce] LinuxBIOS on AMD64
Message-ID: <3174569B9743D511922F00A0C943142303990306@TYANWEB>

Stefan,
Good work.

Ron,
How about VGABIOS progress now?

Regards

YH.

-----????-----
???: Stefan Reinauer [mailto:stepan at suse.de] 
????: 2003?11?20? 4:10
???: linuxbios at clustermatic.org
??: [announce] LinuxBIOS on AMD64

Hi,

I wrote a paper on LinuxBIOS on the AMD64 platform that covers
some aspects on the following topics:

 * image configuration
 * porting LinuxBIOS to new AMD64 motherboards
 * debugging and tweaking hints
 * some internals 

The document is available at 
http://www.openbios.org/docs/LinuxBIOS-AMD64.pdf

I am very glad to announce that this document is released under the GPL,
so please go ahead and use it, spread it, change it. But please do
submit your changes back so everybody can benefit. I suggest putting the
document in the freebios2 documentation subdirectory, if nobody objects.
(What is the preferred file format for that? TeX? The document was
initially created using OpenOffice 1.1 8)

Don't hesitate to make suggestions on improvement, report typos, badly
written english, or whatever comes to your mind when reading the paper.

  Stefan


-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From linuxbios at xdr.com  Thu Nov 20 13:57:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 20 13:57:00 2003
Subject: V1 trouble with gcc 3.2.3
Message-ID: <200311201932.hAKJWdxu008693@xdr.com>

I'm using a fairly old version of V1 (July or so) and when I have an
etherboot ebi payload and build linuxbios with gcc 3.2.3 linuxbios fails,
whereas an older gcc 2.96 works.

It gets to the part where it is going to load/launch the payload. Here
is what it does when it works, linuxbios built with gcc 2.96:
Wrote linuxbios table at: 00000500 - 00000674  checksum ea53

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    34:init_bytes() - zkernel_start:0xfff00000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x94000 size 0x7d48 offset 0x60 filesize 0x3538
(cleaned up) New segment addr 0x94000 size 0x7d48 offset 0x60 filesize 0x3538
Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007d48 filesz: 0x0000000000003538
Clearing Segment: addr: 0x0000000000097538 memsz: 0x0000000000004810
Jumping to boot code at 0x94000
ROM segment 0x5f5e length 0x86ba reloc 0x9400
etc.

--------------- Here is what it does when linuxbios is built with gcc 3.2.3:
Wrote linuxbios table at: 00000500 - 00000634  checksum eeae

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    37:init_bytes() - zkernel_start:0xfff00000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x94000 size 0x7b28 offset 0x60 filesize 0x3338
(cleaned up) New segment addr 0x94000 size 0x7b28 offset 0x60 filesize 0x3338
Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007b28 filesz: 0x0000000000003338
Clearing Segment: addr: 0x0000000000097338 memsz: 0x00000000000047f0
Jumping to boot code at 0x94000
0


---------------
The payload is the same in both cases. The filesizes are different by
0x200 bytes. My guess is it is something in elfboot. I remember
reading something about the -fno-merge-constants option which might
apply--older XFree86 servers have an ELF loader that doesn't like the
new default behaviour of gcc and you have to turn this option to get
their elf loading to work again.

This is probably something that has been hashed out already, sorry
about that.

Any advice would be welcome.

-Dave


From stepan at suse.de  Thu Nov 20 14:06:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Thu Nov 20 14:06:01 2003
Subject: [announce] LinuxBIOS on AMD64
In-Reply-To: <Pine.LNX.4.44.0311201057210.3611-100000@maxroach.lanl.gov>
References: <3FBD024B.5060300@nexpath.com> <Pine.LNX.4.44.0311201057210.3611-100000@maxroach.lanl.gov>
Message-ID: <20031120194102.GA15303@suse.de>

* ron minnich <rminnich at lanl.gov> [031120 18:58]:
> I should be clearer. I prefer latex for this. That doesn't mean I 
> actually *like* latex :-)
> 
> I do my real pubs in Frame on an ibook.

Last time I used latex was probably around '96 - since then I did most
of the text I wrote in HTML, plain, or some mainstream word processor.

I neither have an ibook nor Frame, otherwise I would have used that
combination.

But I'll have a look at converting the text. Can anyone recommend a
template?

Stefan
  
-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From linuxbios at xdr.com  Thu Nov 20 14:17:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 20 14:17:00 2003
Subject: V1 trouble with gcc 3.2.3
Message-ID: <200311201951.hAKJpx7Q008751@xdr.com>

More info:

It is something in the nrv2b utiltiy. The step that makes
linuxbios_payload.nrv2b from linuxbios_payload.bin is what causes the
problem. If I modify that to just copy in the linuxbios_payload.nrv2b
built from the gcc2.96 toolchin, the resulting romimage works.

I looked at the latest nrv2b.c in util/nrv2b directory but there are
only some printing changes...

-Dave


From linuxbios at xdr.com  Thu Nov 20 14:37:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 20 14:37:00 2003
Subject: V1 trouble with gcc 3.2.3
Message-ID: <200311202011.hAKKBtLT008834@xdr.com>

It isn't in nrv2b, it seems to be in some step before that.


From linuxbios at xdr.com  Thu Nov 20 15:08:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 20 15:08:00 2003
Subject: V1 trouble with gcc 3.2.3
Message-ID: <200311202043.hAKKhVgW008950@xdr.com>

I've tracked the problem down to src/arch/i386/lib/vgabios.c, if I
take the .o file built on gcc-2.96 instead of the .o file built
with gcc-3.2.3, everything works. That vgabios.c has a lot of inline
asm code.

-Dave


From rminnich at lanl.gov  Thu Nov 20 15:38:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Nov 20 15:38:00 2003
Subject: V1 trouble with gcc 3.2.3 [PMX:#]
In-Reply-To: <200311202043.hAKKhVgW008950@xdr.com>
Message-ID: <Pine.LNX.4.44.0311201412200.3611-100000@maxroach.lanl.gov>

On Thu, 20 Nov 2003, Dave Ashley wrote:

> I've tracked the problem down to src/arch/i386/lib/vgabios.c, if I
> take the .o file built on gcc-2.96 instead of the .o file built
> with gcc-3.2.3, everything works. That vgabios.c has a lot of inline
> asm code.

compile that .o with both compilers, and use objdump -D to disassemble and 
compare. That might help see what's going on.

ron



From linuxbios at xdr.com  Thu Nov 20 16:51:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 20 16:51:01 2003
Subject: V1 trouble with gcc 3.2.3
Message-ID: <200311202226.hAKMQLVu009348@xdr.com>

>compile that .o with both compilers, and use objdump -D to disassemble and 
>compare. That might help see what's going on.
>ron

Here is the side-by-side diff

obj/vgabios.o:     file format elf32-i386		      |	/build/xfer/vgabios.o:     file format elf32-i386

Disassembly of section .text:					Disassembly of section .text:

00000000 <real_mode_switch_call_vga>:				00000000 <real_mode_switch_call_vga>:
   0:	55                   	push   %ebp			   0:	55                   	push   %ebp
   1:	89 e5                	mov    %esp,%ebp		   1:	89 e5                	mov    %esp,%ebp
   3:	89 25 0b 00 00 00    	mov    %esp,0xb			   3:	89 25 0b 00 00 00    	mov    %esp,0xb
			5: R_386_32	.text						5: R_386_32	.text
   9:	eb 04                	jmp    f <__stack+0x4>		   9:	eb 04                	jmp    f <__stack+0x4>

0000000b <__stack>:						0000000b <__stack>:
   b:	00 00                	add    %al,(%eax)		   b:	00 00                	add    %al,(%eax)
   d:	00 00                	add    %al,(%eax)		   d:	00 00                	add    %al,(%eax)
   f:	ea 16 00 00 00 28 00 	ljmp   $0x28,$0x16		   f:	ea 16 00 00 00 28 00 	ljmp   $0x28,$0x16
			10: R_386_32	.text						10: R_386_32	.text

00000016 <__rms_16bit>:						00000016 <__rms_16bit>:
  16:	b8 30 00 8e d8       	mov    $0xd88e0030,%eax		  16:	b8 30 00 8e d8       	mov    $0xd88e0030,%eax
  1b:	8e c0                	mov    %eax,%es			  1b:	8e c0                	mov    %eax,%es
  1d:	8e e0                	mov    %eax,%fs			  1d:	8e e0                	mov    %eax,%fs
  1f:	8e e8                	mov    %eax,%gs			  1f:	8e e8                	mov    %eax,%gs
  21:	8e d0                	mov    %eax,%ss			  21:	8e d0                	mov    %eax,%ss
  23:	0f 20 c0             	mov    %cr0,%eax		  23:	0f 20 c0             	mov    %cr0,%eax
  26:	66 83 e0 fe          	and    $0xfffffffe,%ax		  26:	66 83 e0 fe          	and    $0xfffffffe,%ax
  2a:	0f 22 c0             	mov    %eax,%cr0		  2a:	0f 22 c0             	mov    %eax,%cr0
  2d:	ea 32 00 00 00 b8 00 	ljmp   $0xb8,$0x32		  2d:	ea 32 00 00 00 b8 00 	ljmp   $0xb8,$0x32
			2e: R_386_16	.text						2e: R_386_16	.text

00000032 <__rms_real>:						00000032 <__rms_real>:
  32:	b8 00 00 8e d0       	mov    $0xd08e0000,%eax		  32:	b8 00 00 8e d0       	mov    $0xd08e0000,%eax
  37:	66 b8 00 10          	mov    $0x1000,%ax		  37:	66 b8 00 10          	mov    $0x1000,%ax
  3b:	00 00                	add    %al,(%eax)		  3b:	00 00                	add    %al,(%eax)
  3d:	66 89 c4             	mov    %ax,%sp			  3d:	66 89 c4             	mov    %ax,%sp
  40:	b0 11                	mov    $0x11,%al		  40:	b0 11                	mov    $0x11,%al
  42:	e6 80                	out    %al,$0x80		  42:	e6 80                	out    %al,$0x80
  44:	31 c0                	xor    %eax,%eax		  44:	31 c0                	xor    %eax,%eax
  46:	8e d8                	mov    %eax,%ds			  46:	8e d8                	mov    %eax,%ds
  48:	8e c0                	mov    %eax,%es			  48:	8e c0                	mov    %eax,%es
  4a:	8e e0                	mov    %eax,%fs			  4a:	8e e0                	mov    %eax,%fs
  4c:	8e e8                	mov    %eax,%gs			  4c:	8e e8                	mov    %eax,%gs
  4e:	9a 03 00 00 c0 b0 55 	lcall  $0x55b0,$0xc0000003	  4e:	9a 03 00 00 c0 b0 55 	lcall  $0x55b0,$0xc0000003
  55:	e6 80                	out    %al,$0x80		  55:	e6 80                	out    %al,$0x80
  57:	0f 20 c0             	mov    %cr0,%eax		  57:	0f 20 c0             	mov    %cr0,%eax
  5a:	66 83 c8 01          	or     $0x1,%ax			  5a:	66 83 c8 01          	or     $0x1,%ax
  5e:	0f 22 c0             	mov    %eax,%cr0		  5e:	0f 22 c0             	mov    %eax,%cr0
  61:	66 ea 69 00 00 00    	ljmpw  $0x0,$0x69		  61:	66 ea 69 00 00 00    	ljmpw  $0x0,$0x69
			63: R_386_32	.text						63: R_386_32	.text
  67:	10 00                	adc    %al,(%eax)		  67:	10 00                	adc    %al,(%eax)

00000069 <vgarestart>:						00000069 <vgarestart>:
  69:	66 b8 18 00          	mov    $0x18,%ax		  69:	66 b8 18 00          	mov    $0x18,%ax
  6d:	8e d8                	mov    %eax,%ds			  6d:	8e d8                	mov    %eax,%ds
  6f:	8e c0                	mov    %eax,%es			  6f:	8e c0                	mov    %eax,%es
  71:	8e e0                	mov    %eax,%fs			  71:	8e e0                	mov    %eax,%fs
  73:	8e e8                	mov    %eax,%gs			  73:	8e e8                	mov    %eax,%gs
  75:	8e d0                	mov    %eax,%ss			  75:	8e d0                	mov    %eax,%ss
  77:	8b 25 0b 00 00 00    	mov    0xb,%esp			  77:	8b 25 0b 00 00 00    	mov    0xb,%esp
			79: R_386_32	.text						79: R_386_32	.text
  7d:	5d                   	pop    %ebp			  7d:	5d                   	pop    %ebp
  7e:	c3                   	ret    				  7e:	c3                   	ret    

0000007f <unsupportint_recover>:			      |	0000007f <real_mode_switch_end>:
  7f:	55                   	push   %ebp		      |	  7f:	90                   	nop    
  80:	89 e5                	mov    %esp,%ebp	      |
  82:	eb e5                	jmp    69 <vgarestart>	      |	00000080 <unsupportint_recover>:
  84:	5d                   	pop    %ebp		      |	  80:	55                   	push   %ebp
  85:	c3                   	ret    			      |	  81:	89 e5                	mov    %esp,%ebp
							      |	  83:	eb e4                	jmp    69 <vgarestart>
00000086 <do_vgabios>:					      |	  85:	5d                   	pop    %ebp
  86:	55                   	push   %ebp		      |	  86:	c3                   	ret    
  87:	89 e5                	mov    %esp,%ebp	      |	  87:	90                   	nop    
  89:	53                   	push   %ebx		      |
  8a:	6a 00                	push   $0x0		      |	00000088 <do_vgabios>:
  8c:	68 00 00 03 00       	push   $0x30000		      |	  88:	55                   	push   %ebp
  91:	e8 fc ff ff ff       	call   92 <do_vgabios+0xc>    |	  89:	89 e5                	mov    %esp,%ebp
			92: R_386_PC32	pci_find_class	      |	  8b:	56                   	push   %esi
  96:	89 c2                	mov    %eax,%edx	      |	  8c:	53                   	push   %ebx
  98:	85 d2                	test   %edx,%edx	      |	  8d:	53                   	push   %ebx
  9a:	58                   	pop    %eax		      |	  8e:	53                   	push   %ebx
  9b:	59                   	pop    %ecx		      |	  8f:	6a 00                	push   $0x0
  9c:	0f 84 91 00 00 00    	je     133 <do_vgabios+0xad>  |	  91:	68 00 00 03 00       	push   $0x30000
  a2:	0f b7 42 1e          	movzwl 0x1e(%edx),%eax	      |	  96:	e8 fc ff ff ff       	call   97 <do_vgabios+0xf>
  a6:	50                   	push   %eax		      |				97: R_386_PC32	pci_find_class
  a7:	0f b7 42 1c          	movzwl 0x1c(%edx),%eax	      |	  9b:	89 c2                	mov    %eax,%edx
  ab:	50                   	push   %eax		      |	  9d:	83 c4 10             	add    $0x10,%esp
  ac:	68 00 00 00 00       	push   $0x0		      |	  a0:	85 d2                	test   %edx,%edx
			ad: R_386_32	.rodata.str1.1	      |	  a2:	75 14                	jne    b8 <do_vgabios+0x30>
  b1:	6a 07                	push   $0x7		      |	  a4:	51                   	push   %ecx
  b3:	e8 fc ff ff ff       	call   b4 <do_vgabios+0x2e>   |	  a5:	51                   	push   %ecx
			b4: R_386_PC32	do_printk	      |	  a6:	68 00 00 00 00       	push   $0x0
  b8:	83 c4 10             	add    $0x10,%esp	      |				a7: R_386_32	.rodata
  bb:	80 3d 00 00 fe ff 55 	cmpb   $0x55,0xfffe0000	      |	  ab:	6a 07                	push   $0x7
  c2:	74 24                	je     e8 <do_vgabios+0x62>   |	  ad:	e8 fc ff ff ff       	call   ae <do_vgabios+0x26>
  c4:	0f b6 05 01 00 fe ff 	movzbl 0xfffe0001,%eax	      |				ae: R_386_PC32	do_printk
  cb:	50                   	push   %eax		      |	  b2:	e9 90 00 00 00       	jmp    147 <do_vgabios+0xbf>
  cc:	0f b6 05 00 00 fe ff 	movzbl 0xfffe0000,%eax	      |	  b7:	90                   	nop    
  d3:	50                   	push   %eax		      |	  b8:	0f b7 42 1e          	movzwl 0x1e(%edx),%eax
  d4:	68 1b 00 00 00       	push   $0x1b		      |	  bc:	50                   	push   %eax
			d5: R_386_32	.rodata.str1.1	      |	  bd:	0f b7 42 1c          	movzwl 0x1c(%edx),%eax
  d9:	6a 07                	push   $0x7		      |	  c1:	50                   	push   %eax
  db:	e8 fc ff ff ff       	call   dc <do_vgabios+0x56>   |	  c2:	68 0e 00 00 00       	push   $0xe
			dc: R_386_PC32	do_printk	      |				c3: R_386_32	.rodata
  e0:	83 c4 10             	add    $0x10,%esp	      |	  c7:	6a 07                	push   $0x7
  e3:	8b 5d fc             	mov    0xfffffffc(%ebp),%ebx  |	  c9:	e8 fc ff ff ff       	call   ca <do_vgabios+0x42>
  e6:	c9                   	leave  			      |				ca: R_386_PC32	do_printk
  e7:	c3                   	ret    			      |	  ce:	83 c4 10             	add    $0x10,%esp
  e8:	c6 05 01 00 fe ff aa 	movb   $0xaa,0xfffe0001	      |	  d1:	80 3d 00 00 fe ff 55 	cmpb   $0x55,0xfffe0000
  ef:	68 00 00 01 00       	push   $0x10000		      |	  d8:	be 00 00 fe ff       	mov    $0xfffe0000,%esi
  f4:	68 00 00 fe ff       	push   $0xfffe0000	      |	  dd:	75 49                	jne    128 <do_vgabios+0xa0>
  f9:	68 00 00 0c 00       	push   $0xc0000		      |	  df:	c6 05 01 00 fe ff aa 	movb   $0xaa,0xfffe0001
  fe:	e8 fc ff ff ff       	call   ff <do_vgabios+0x79>   |	  e6:	52                   	push   %edx
			ff: R_386_PC32	memcpy		      |	  e7:	68 00 00 01 00       	push   $0x10000
 103:	31 db                	xor    %ebx,%ebx	      |	  ec:	56                   	push   %esi
 105:	e8 fc ff ff ff       	call   106 <do_vgabios+0x80>  |	  ed:	68 00 00 0c 00       	push   $0xc0000
			106: R_386_PC32	write_protect_vgabios |	  f2:	e8 fc ff ff ff       	call   f3 <do_vgabios+0x6b>
 10a:	83 c4 0c             	add    $0xc,%esp	      |				f3: R_386_PC32	memcpy
 10d:	0f b6 83 00 00 fe ff 	movzbl 0xfffe0000(%ebx),%eax  |	  f7:	e8 fc ff ff ff       	call   f8 <do_vgabios+0x70>
 114:	50                   	push   %eax		      |				f8: R_386_PC32	write_protect_vgabios
 115:	68 34 00 00 00       	push   $0x34		      |	  fc:	31 db                	xor    %ebx,%ebx
			116: R_386_32	.rodata.str1.1	      |	  fe:	83 c4 10             	add    $0x10,%esp
 11a:	6a 07                	push   $0x7		      |	 101:	8d 76 00             	lea    0x0(%esi),%esi
 11c:	43                   	inc    %ebx		      |	 104:	50                   	push   %eax
 11d:	e8 fc ff ff ff       	call   11e <do_vgabios+0x98>  |	 105:	0f b6 04 33          	movzbl (%ebx,%esi,1),%eax
			11e: R_386_PC32	do_printk	      |	 109:	50                   	push   %eax
 122:	83 c4 0c             	add    $0xc,%esp	      |	 10a:	68 29 00 00 00       	push   $0x29
 125:	83 fb 0f             	cmp    $0xf,%ebx	      |				10b: R_386_32	.rodata
 128:	7e e3                	jle    10d <do_vgabios+0x87>  |	 10f:	6a 07                	push   $0x7
 12a:	8b 5d fc             	mov    0xfffffffc(%ebp),%ebx  |	 111:	43                   	inc    %ebx
 12d:	c9                   	leave  			      |	 112:	e8 fc ff ff ff       	call   113 <do_vgabios+0x8b>
 12e:	e9 cd fe ff ff       	jmp    0 <real_mode_switch_ca |				113: R_386_PC32	do_printk
 133:	68 3a 00 00 00       	push   $0x3a		      |	 117:	83 c4 10             	add    $0x10,%esp
			134: R_386_32	.rodata.str1.1	      |	 11a:	83 fb 0f             	cmp    $0xf,%ebx
 138:	6a 07                	push   $0x7		      |	 11d:	7e e5                	jle    104 <do_vgabios+0x7c>
 13a:	e8 fc ff ff ff       	call   13b <do_vgabios+0xb5>  |	 11f:	e8 dc fe ff ff       	call   0 <real_mode_switch_ca
			13b: R_386_PC32	do_printk	      |	 124:	eb 21                	jmp    147 <do_vgabios+0xbf>
 13f:	eb a2                	jmp    e3 <do_vgabios+0x5d>   |	 126:	89 f6                	mov    %esi,%esi
							      >	 128:	0f b6 05 01 00 fe ff 	movzbl 0xfffe0001,%eax
							      >	 12f:	50                   	push   %eax
							      >	 130:	0f b6 05 00 00 fe ff 	movzbl 0xfffe0000,%eax
							      >	 137:	50                   	push   %eax
							      >	 138:	68 2f 00 00 00       	push   $0x2f
							      >				139: R_386_32	.rodata
							      >	 13d:	6a 07                	push   $0x7
							      >	 13f:	e8 fc ff ff ff       	call   140 <do_vgabios+0xb8>
							      >				140: R_386_PC32	do_printk
							      >	 144:	83 c4 10             	add    $0x10,%esp
							      >	 147:	8d 65 f8             	lea    0xfffffff8(%ebp),%esp
							      >	 14a:	5b                   	pop    %ebx
							      >	 14b:	5e                   	pop    %esi
							      >	 14c:	5d                   	pop    %ebp
							      >	 14d:	c3                   	ret    
Disassembly of section .data:					Disassembly of section .data:

00000000 <rcsid>:						00000000 <rcsid>:
   0:	24 49                	and    $0x49,%al		   0:	24 49                	and    $0x49,%al
   2:	64 3a 20             	cmp    %fs:(%eax),%ah		   2:	64 3a 20             	cmp    %fs:(%eax),%ah
   5:	76 67                	jbe    6e <vgarestart+0x5>	   5:	76 67                	jbe    6e <vgarestart+0x5>
   7:	61                   	popa   				   7:	61                   	popa   
   8:	62 69 6f             	bound  %ebp,0x6f(%ecx)		   8:	62 69 6f             	bound  %ebp,0x6f(%ecx)
   b:	73 2e                	jae    3b <__rms_real+0x9>	   b:	73 2e                	jae    3b <__rms_real+0x9>
   d:	63 2c 76             	arpl   %bp,(%esi,%esi,2)	   d:	63 2c 76             	arpl   %bp,(%esi,%esi,2)
  10:	20 31                	and    %dh,(%ecx)		  10:	20 31                	and    %dh,(%ecx)
  12:	2e 31 30             	xor    %esi,%cs:(%eax)		  12:	2e 31 30             	xor    %esi,%cs:(%eax)
  15:	20 32                	and    %dh,(%edx)		  15:	20 32                	and    %dh,(%edx)
  17:	30 30                	xor    %dh,(%eax)		  17:	30 30                	xor    %dh,(%eax)
  19:	33 2f                	xor    (%edi),%ebp		  19:	33 2f                	xor    (%edi),%ebp
  1b:	30 37                	xor    %dh,(%edi)		  1b:	30 37                	xor    %dh,(%edi)
  1d:	2f                   	das    				  1d:	2f                   	das    
  1e:	32 32                	xor    (%edx),%dh		  1e:	32 32                	xor    (%edx),%dh
  20:	20 32                	and    %dh,(%edx)		  20:	20 32                	and    %dh,(%edx)
  22:	32 3a                	xor    (%edx),%bh		  22:	32 3a                	xor    (%edx),%bh
  24:	31 33                	xor    %esi,(%ebx)		  24:	31 33                	xor    %esi,(%ebx)
  26:	3a 30                	cmp    (%eax),%dh		  26:	3a 30                	cmp    (%eax),%dh
  28:	35 20 64 61 73       	xor    $0x73616420,%eax		  28:	35 20 64 61 73       	xor    $0x73616420,%eax
  2d:	68 20 45 78 70       	push   $0x70784520		  2d:	68 20 45 78 70       	push   $0x70784520
  32:	20 24 00             	and    %ah,(%eax,%eax,1)	  32:	20 24 00             	and    %ah,(%eax,%eax,1)
Disassembly of section .rodata.str1.1:			      |	Disassembly of section .note:

00000000 <.rodata.str1.1>:				      |	00000000 <.note>:
   0:	66 6f                	outsw  %ds:(%esi),(%dx)	      |	   0:	08 00                	or     %al,(%eax)
   2:	75 6e                	jne    72 <vgarestart+0x9>    |	   2:	00 00                	add    %al,(%eax)
   4:	64 20 56 47          	and    %dl,%fs:0x47(%esi)     |	   4:	00 00                	add    %al,(%eax)
   8:	41                   	inc    %ecx		      |	   6:	00 00                	add    %al,(%eax)
   9:	3a 20                	cmp    (%eax),%ah	      |	   8:	01 00                	add    %eax,(%eax)
   b:	76 69                	jbe    76 <vgarestart+0xd>    |	   a:	00 00                	add    %al,(%eax)
   d:	64                   	fs			      |	   c:	30 31                	xor    %dh,(%ecx)
   e:	3d 25 78 2c 20       	cmp    $0x202c7825,%eax	      |	   e:	2e 30 31             	xor    %dh,%cs:(%ecx)
  13:	64 69 64 3d 25 78 0a 	imul   $0x42000a78,%fs:0x25(% |	  11:	00 00                	add    %al,(%eax)
  1a:	00 42 						      |		...
  1c:	41                   	inc    %ecx		      |	Disassembly of section .rodata:
  1d:	44                   	inc    %esp		      |
  1e:	20 53 49             	and    %dl,0x49(%ebx)	      |	00000000 <.rodata>:
  21:	47                   	inc    %edi		      |	   0:	4e                   	dec    %esi
  22:	4e                   	dec    %esi		      |	   1:	4f                   	dec    %edi
  23:	41                   	inc    %ecx		      |	   2:	20 56 47             	and    %dl,0x47(%esi)
  24:	54                   	push   %esp		      |	   5:	41                   	inc    %ecx
  25:	55                   	push   %ebp		      |	   6:	20 46 4f             	and    %al,0x4f(%esi)
  26:	52                   	push   %edx		      |	   9:	55                   	push   %ebp
  27:	45                   	inc    %ebp		      |	   a:	4e                   	dec    %esi
  28:	20 30                	and    %dh,(%eax)	      |	   b:	44                   	inc    %esp
							      >	   c:	0a 00                	or     (%eax),%al
							      >	   e:	66 6f                	outsw  %ds:(%esi),(%dx)
							      >	  10:	75 6e                	jne    80 <unsupportint_recov
							      >	  12:	64 20 56 47          	and    %dl,%fs:0x47(%esi)
							      >	  16:	41                   	inc    %ecx
							      >	  17:	3a 20                	cmp    (%eax),%ah
							      >	  19:	76 69                	jbe    84 <unsupportint_recov
							      >	  1b:	64                   	fs
							      >	  1c:	3d 25 78 2c 20       	cmp    $0x202c7825,%eax
							      >	  21:	64 69 64 3d 25 78 0a 	imul   $0x30000a78,%fs:0x25(%
							      >	  28:	00 30 
  2a:	78 25                	js     51 <__rms_real+0x1f>	  2a:	78 25                	js     51 <__rms_real+0x1f>
  2c:	78 20                	js     4e <__rms_real+0x1c>	  2c:	78 20                	js     4e <__rms_real+0x1c>
  2e:	30 78 25             	xor    %bh,0x25(%eax)	      |	  2e:	00 42 41             	add    %al,0x41(%edx)
  31:	78 0a                	js     3d <.rodata.str1.1+0x3 |	  31:	44                   	inc    %esp
  33:	00 30                	add    %dh,(%eax)	      |	  32:	20 53 49             	and    %dl,0x49(%ebx)
  35:	78 25                	js     5c <__rms_real+0x2a>   |	  35:	47                   	inc    %edi
  37:	78 20                	js     59 <__rms_real+0x27>   |	  36:	4e                   	dec    %esi
  39:	00 4e 4f             	add    %cl,0x4f(%esi)	      |	  37:	41                   	inc    %ecx
  3c:	20 56 47             	and    %dl,0x47(%esi)	      |	  38:	54                   	push   %esp
  3f:	41                   	inc    %ecx		      |	  39:	55                   	push   %ebp
  40:	20 46 4f             	and    %al,0x4f(%esi)	      |	  3a:	52                   	push   %edx
  43:	55                   	push   %ebp		      |	  3b:	45                   	inc    %ebp
  44:	4e                   	dec    %esi		      |	  3c:	20 30                	and    %dh,(%eax)
  45:	44                   	inc    %esp		      |	  3e:	78 25                	js     65 <__rms_real+0x33>
  46:	0a 00                	or     (%eax),%al	      |	  40:	78 20                	js     62 <__rms_real+0x30>
							      >	  42:	30 78 25             	xor    %bh,0x25(%eax)
							      >	  45:	78 0a                	js     51 <__rms_real+0x1f>
							      >		...
Disassembly of section .comment:				Disassembly of section .comment:

00000000 <.comment>:						00000000 <.comment>:
   0:	00 47 43             	add    %al,0x43(%edi)		   0:	00 47 43             	add    %al,0x43(%edi)
   3:	43                   	inc    %ebx			   3:	43                   	inc    %ebx
   4:	3a 20                	cmp    (%eax),%ah		   4:	3a 20                	cmp    (%eax),%ah
   6:	28 47 4e             	sub    %al,0x4e(%edi)		   6:	28 47 4e             	sub    %al,0x4e(%edi)
   9:	55                   	push   %ebp			   9:	55                   	push   %ebp
   a:	29 20                	sub    %esp,(%eax)		   a:	29 20                	sub    %esp,(%eax)
   c:	33 2e                	xor    (%esi),%ebp	      |	   c:	32 2e                	xor    (%esi),%ch
   e:	32 2e                	xor    (%esi),%ch	      |	   e:	39 36                	cmp    %esi,(%esi)
  10:	33 00                	xor    (%eax),%eax	      |	  10:	20 32                	and    %dh,(%edx)
							      >	  12:	30 30                	xor    %dh,(%eax)
							      >	  14:	30 30                	xor    %dh,(%eax)
							      >	  16:	37                   	aaa    
							      >	  17:	33 31                	xor    (%ecx),%esi
							      >	  19:	20 28                	and    %ch,(%eax)
							      >	  1b:	52                   	push   %edx
							      >	  1c:	65 64 20 48 61       	and    %cl,%fs:%gs:0x61(%eax)
							      >	  21:	74 20                	je     43 <__rms_real+0x11>
							      >	  23:	4c                   	dec    %esp
							      >	  24:	69 6e 75 78 20 37 2e 	imul   $0x2e372078,0x75(%esi)
							      >	  2b:	32 20                	xor    (%eax),%ah
							      >	  2d:	32 2e                	xor    (%esi),%ch
							      >	  2f:	39 36                	cmp    %esi,(%esi)
							      >	  31:	2d 31 31 32 2e       	sub    $0x2e323131,%eax
							      >	  36:	37                   	aaa    
							      >	  37:	2e 31 29             	xor    %ebp,%cs:(%ecx)
							      >		...


The left side is the failure side, the right side is the working side.

Right side has nops in between functions, don't know if that matters.

-Dave


From linuxbios at xdr.com  Thu Nov 20 17:05:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 20 17:05:01 2003
Subject: V1 trouble with gcc 3.2.3
Message-ID: <200311202240.hAKMe9Te009391@xdr.com>

I found one minor bug but this isn't the cause of the problem. In
that vgabios.c file there is a typo, = instead of ==:
  if ((buf[0] == 0x55) && (buf[1] = 0xaa)) {
should be
  if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {

This is present in version2 as well. Someone ought to
fix that...

-Dave


From linuxbios at xdr.com  Thu Nov 20 17:33:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Thu Nov 20 17:33:00 2003
Subject: V1 trouble with gcc 3.2.3  SOLUTION!!!
Message-ID: <200311202308.hAKN80Sl009470@xdr.com>

Aside from the = vs == bug which probably wasn't too damaging,
the problem was caused because the newer compiler doesn't use
as many registers in its code, specifically the EBX register.
So at the start of the do_vgabios() function it doesn't bother
to push EBX on the stack to preserve it. However code higher
up that calls this function had stored something in EBX, which
the call to the vgabios happily trashes.

The fix is to push ebx within the real_mode_switch_call_vga function:
	/* save the stack */
 "push %ebx\n"
	"mov %esp, __stack\n"

...

       "    mov  %ax, %ss          \n"
       "    mov  __stack, %esp\n"
 "pop %ebx\n"
       );

It won't hurt to push other registers like %esi for example. In fact
why not push all the registers just to be safe...

This is a pretty subtle bug, people should understand what was
wrong and how the fix works.

-Dave


From rminnich at lanl.gov  Thu Nov 20 17:36:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Thu Nov 20 17:36:01 2003
Subject: V1 trouble with gcc 3.2.3 [PMX:#]
In-Reply-To: <200311202240.hAKMe9Te009391@xdr.com>
Message-ID: <Pine.LNX.4.44.0311201609120.3611-100000@maxroach.lanl.gov>

On Thu, 20 Nov 2003, Dave Ashley wrote:

> I found one minor bug but this isn't the cause of the problem. In
> that vgabios.c file there is a typo, = instead of ==:
>   if ((buf[0] == 0x55) && (buf[1] = 0xaa)) {
> should be
>   if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {

I don't see this in version 1, but it is in version 2 and I just fixed it. 

Thanks

ron



From ebiederman at lnxi.com  Thu Nov 20 18:48:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Nov 20 18:48:00 2003
Subject: V1 trouble with gcc 3.2.3  SOLUTION!!!
In-Reply-To: <200311202308.hAKN80Sl009470@xdr.com>
References: <200311202308.hAKN80Sl009470@xdr.com>
Message-ID: <m3u14y8t4i.fsf@maxwell.lnxi.com>

Dave Ashley <linuxbios at xdr.com> writes:

> Aside from the = vs == bug which probably wasn't too damaging,
> the problem was caused because the newer compiler doesn't use
> as many registers in its code, specifically the EBX register.
> So at the start of the do_vgabios() function it doesn't bother
> to push EBX on the stack to preserve it. However code higher
> up that calls this function had stored something in EBX, which
> the call to the vgabios happily trashes.
> 
> The fix is to push ebx within the real_mode_switch_call_vga function:
> 	/* save the stack */
>  "push %ebx\n"
> 	"mov %esp, __stack\n"
> 
> ...
> 
>        "    mov  %ax, %ss          \n"
>        "    mov  __stack, %esp\n"
>  "pop %ebx\n"
>        );
> 
> It won't hurt to push other registers like %esi for example. In fact
> why not push all the registers just to be safe...
> 
> This is a pretty subtle bug, people should understand what was
> wrong and how the fix works.

Well it is a little less subtle than it might be.  In the C calling
conventions frequently some of the registers are designated callee save.
Which means if you are going to use that register you must save it.
%ebx, %ebp, %esi, and %esi are the callee save registers on x86.

With inline assembly you can avoid some of that by telling the compiler
which registers you will be using and it will handle the nuances
of the calling conventions.  That is possibly the better approach.

Eric


From ebiederman at lnxi.com  Thu Nov 20 22:15:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Nov 20 22:15:01 2003
Subject: AMD64: LDTSTOP vs hard reset
In-Reply-To: <20031120104802.GA10480@suse.de>
References: <20031120104802.GA10480@suse.de>
Message-ID: <m31xs24btz.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> Hi,
> 
> In addition to lowering the number of resets it would also be possible
> to use an LDTSTOP (as I implemented it in older versions of the CVS) 
> at least when doing the hypertransport link changes. 
> I know that this does not work with some preproduction CPUs, but I don't
> think that would really matter. BUT: Could we get rid of all CPU resets
> when doing an LDTSTOP assertion (It's a lot quicker than a hard reset)
> or would we still need to reset the CPU for some other reasons?

When I was working with it I remember seeing some additional remaining
errata with regards to LDTSTOP.  So I decided not to mess with it.
There does seem to be a big delay in the phase that finds the rom chip
though.

Eric


From ebiederman at lnxi.com  Thu Nov 20 22:18:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Nov 20 22:18:01 2003
Subject: LinuxBIOS and 4G+ memory
In-Reply-To: <20031119142631.GC6700@suse.de>
References: <20031119142631.GC6700@suse.de>
Message-ID: <m3wu9u2x8b.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> Hi,
> 
> does LinuxBIOS on Opteron cleanly handle 4+G of memory? I have a machine
> with 4G here for the first time, but I seem to end up with some of the
> memory missing.
> 
> [..]
> totalram: 3840M
> 
> How would Linux clear ECC memory >4G in this case? using PAE? Long mode
> is not available yet..

Read the code it is handled for the Opteron.  We currently make the memory
hole for pci devices overly large but otherwise everything works well.

Eric


From ebiederman at lnxi.com  Thu Nov 20 22:28:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Nov 20 22:28:00 2003
Subject: AMD64 Solo Hang - news
In-Reply-To: <20031120124642.GA11352@suse.de>
References: <20031120124642.GA11352@suse.de>
Message-ID: <m3islez7pf.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> Hi,
> 
> it seems that the Solo motherboard is the only motherboard tested so far
> that is based on an Athlon64 instead of Opteron CPUs..
> 
> The following code in src/northbridge/amd/amdk8/misc_control.c relies on
> more than one hypertransport link being available:
> 
>         cmd = pci_read_config32(dev, 0xdc);
>         if((cmd & 0x0000ff00) != 0x02500) {
>                 cmd &= 0xffff00ff;
>                 cmd |= 0x00002500;
>                 pci_write_config32(dev, 0xdc, cmd );
>                 printk_debug("resetting cpu\n");
>                 hard_reset();
>         }
> 
> This implicitly changes CPU0 Link1 FIFO Read Pointer Optimization, not
> taking into regard that LDT1 might not be there.
> 
> It seems this code should rather check all links to see whether they are
> connected and optimize _all_ of the connected.

Agreed. That part should certainly be more dynamic.  It looks like
I missed that when I was syncing the trees.
 
> Is the CPU reset here really needed for the setting to become active?

I'm not certain.  But given that it is playing with hypertransport
link settings I would assume so.  But that is worth confirming.

> The BKDG does not state this explicitly ... (Therefore I vote for
> removing it)

I am starting to agree with you, but there must be some reason it is
in there...

Eric


From ebiederman at lnxi.com  Thu Nov 20 22:34:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Nov 20 22:34:00 2003
Subject: AMD64 Solo Hang - news
In-Reply-To: <20031120124642.GA11352@suse.de>
References: <20031120124642.GA11352@suse.de>
Message-ID: <m3ekw2z7gd.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> Hi,
> 
> it seems that the Solo motherboard is the only motherboard tested so far
> that is based on an Athlon64 instead of Opteron CPUs..
> 
> The following code in src/northbridge/amd/amdk8/misc_control.c relies on
> more than one hypertransport link being available:
> 
>         cmd = pci_read_config32(dev, 0xdc);
>         if((cmd & 0x0000ff00) != 0x02500) {
>                 cmd &= 0xffff00ff;
>                 cmd |= 0x00002500;
>                 pci_write_config32(dev, 0xdc, cmd );
>                 printk_debug("resetting cpu\n");
>                 hard_reset();
>         }
> 
> This implicitly changes CPU0 Link1 FIFO Read Pointer Optimization, not
> taking into regard that LDT1 might not be there.
> 
> It seems this code should rather check all links to see whether they are
> connected and optimize _all_ of the connected.
> 
> Is the CPU reset here really needed for the setting to become active?
> The BKDG does not state this explicitly ... (Therefore I vote for
> removing it)

The acid test for needing the reset would be to find a benchmark that
cares about this optimization and see if it just setting the bits is sufficient
or if it requires the hypertransport link to be shut off.  The fact
that the settings persist through reset hint that a reset is required.

I am dropping a #warning into my tree so I won't forget and I will see if
I can find the appropriate benchmark.

Eric


From jbors at mail.ru  Fri Nov 21 01:37:00 2003
From: jbors at mail.ru (Dmitry Borisov)
Date: Fri Nov 21 01:37:00 2003
Subject: EPIA-M 600 Cannot start
Message-ID: <004201c3affe$ce21a010$0300a8c0@amr.corp.intel.com>

My respect to all.
I've got problem trying to burn linuxbios into EPIA-M 600. 
Config file attached if it could help. When I burn image and restart mb, it does not say anything to the serial. Even single character.
Here is the output from flash_rom utility:

SST39SF020A found at physical address: 0xfffc0000
Part is SST39SF020A
Programming Page: 0063 at address: 0x0003f000

Sorry, that's pretty much I have from linuxbios to share.

I wonder if anyone having EPIA-M 600 could send me the correct config file and correct romimage as well or let me know when I'm wrong.
Appreciate your help,
Dmitry/
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From jbors at mail.ru  Fri Nov 21 02:03:00 2003
From: jbors at mail.ru (Dmitry Borisov)
Date: Fri Nov 21 02:03:00 2003
Subject: EPIA-M 600 Cannot start
References: <004201c3affe$ce21a010$0300a8c0@amr.corp.intel.com>
Message-ID: <00b301c3b002$6135e110$0300a8c0@amr.corp.intel.com>

Some additional info that might help.

gcc (GCC) 3.2 20020903 (Red Hat Linux 8.0 3.2-7)
GNU assembler 2.13.90.0.2 20020802

Dmitry/
  ----- Original Message ----- 
  From: Dmitry Borisov 
  To: linuxbios at clustermatic.org 
  Sent: Thursday, November 20, 2003 11:11 PM
  Subject: EPIA-M 600 Cannot start


  My respect to all.
  I've got problem trying to burn linuxbios into EPIA-M 600. 
  Config file attached if it could help. When I burn image and restart mb, it does not say anything to the serial. Even single character.
  Here is the output from flash_rom utility:

  SST39SF020A found at physical address: 0xfffc0000
  Part is SST39SF020A
  Programming Page: 0063 at address: 0x0003f000

  Sorry, that's pretty much I have from linuxbios to share.

  I wonder if anyone having EPIA-M 600 could send me the correct config file and correct romimage as well or let me know when I'm wrong.
  Appreciate your help,
  Dmitry/
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From ts1 at tsn.or.jp  Fri Nov 21 02:58:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Fri Nov 21 02:58:01 2003
Subject: V1 trouble with gcc 3.2.3  SOLUTION!!!
In-Reply-To: <200311202308.hAKN80Sl009470@xdr.com>
References: <200311202308.hAKN80Sl009470@xdr.com>
Message-ID: <20031121083328.GA26677@tsn.or.jp>

This bug has been already fixed in the CVS (v1) as of 2003/09/24.
(I remember you said you were using old source)

On Thu, Nov 20, 2003 at 03:08:00PM -0800, Dave Ashley wrote:
> Aside from the = vs == bug which probably wasn't too damaging,
> the problem was caused because the newer compiler doesn't use
> as many registers in its code, specifically the EBX register.
> So at the start of the do_vgabios() function it doesn't bother
> to push EBX on the stack to preserve it. However code higher
> up that calls this function had stored something in EBX, which
> the call to the vgabios happily trashes.
> 
> The fix is to push ebx within the real_mode_switch_call_vga function:
> 	/* save the stack */
>  "push %ebx\n"
> 	"mov %esp, __stack\n"
> 
> ...
> 
>        "    mov  %ax, %ss          \n"
>        "    mov  __stack, %esp\n"
>  "pop %ebx\n"
>        );
> 
> It won't hurt to push other registers like %esi for example. In fact
> why not push all the registers just to be safe...
> 
> This is a pretty subtle bug, people should understand what was
> wrong and how the fix works.
> 
> -Dave
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 
Takeshi


From niki.waibel at newlogic.com  Fri Nov 21 07:45:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Fri Nov 21 07:45:01 2003
Subject: EPIA-M 600 Cannot start
In-Reply-To: <00b301c3b002$6135e110$0300a8c0@amr.corp.intel.com>
Message-ID: <200311211320.hALDKT84005272@enterprise2.newlogic.at>

i am using a epia-m 600 with success.
current cvs of freebios/linuxbios version1 works fine.

i used:
===
$ cat ../example.config | grep -v ^# | grep -v ^$
target /home/niki/packages/freebios-20031024-build
mainboard via/epia-m
option SERIAL_CONSOLE=1
option TTYS0_BAUD=115200
option DEFAULT_CONSOLE_LOGLEVEL=9
option DEBUG=1
option RAMTEST=1
option USE_GENERIC_ROM=1
option STD_FLASH=1
option ROM_SIZE=262144
option PAYLOAD_SIZE=196608
option USE_ELF_BOOT=1
payload /home/niki/packages/filo-0.4/filo.elf
===

there is currently a problem with the speed of the serial port.
it might be a baudrate less (in my case it is 57600 although i
specified 115200).

i can send you my romimage for testing if you want.

gcc: 3.3.1
binutils: 2.14
(should not matter)

system: my own ;-)
===
busybox/1.0.0pre3
freeswan/2.04
gmp/4.1.2
ipsec-tools/0.2.2
iptables/1.2.9
libol/0.3.11
mawk/1.1.3
ntp/4.2.0
openssh/3.7.1p2
openssl/0.9.7c
pcsc-lite/1.2.0
ppp/20031029
rp-pppoe/3.5
setserial/2.17
syslog-ng/1.6.0rc4
tinylogin/1.4
uclibc/0.9.22
util-linux/2.12
zlib/1.1.4.1
===

niki

On 21-Nov-2003 Dmitry Borisov wrote:
> Some additional info that might help.
> 
> gcc (GCC) 3.2 20020903 (Red Hat Linux 8.0 3.2-7)
> GNU assembler 2.13.90.0.2 20020802
> 
> Dmitry/
>   ----- Original Message ----- 
>   From: Dmitry Borisov 
>   To: linuxbios at clustermatic.org 
>   Sent: Thursday, November 20, 2003 11:11 PM
>   Subject: EPIA-M 600 Cannot start
> 
> 
>   My respect to all.
>   I've got problem trying to burn linuxbios into EPIA-M 600. 
>   Config file attached if it could help. When I burn image and restart mb, it does not say anything to the serial. Even singl
e
> character.
>   Here is the output from flash_rom utility:
> 
>   SST39SF020A found at physical address: 0xfffc0000
>   Part is SST39SF020A
>   Programming Page: 0063 at address: 0x0003f000
> 
>   Sorry, that's pretty much I have from linuxbios to share.
> 
>   I wonder if anyone having EPIA-M 600 could send me the correct
> config file and correct romimage as well or let me know when I'm
> wrong.
>   Appreciate your help,
>   Dmitry/


From linuxbios at xdr.com  Fri Nov 21 10:59:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Nov 21 10:59:00 2003
Subject: V2 epia-m support
Message-ID: <200311211634.hALGYK9R011522@xdr.com>

I've embarked on adding epia-m support to v2 of linuxbios. I am at the point
where I have debug messages coming out the serial port. My plan of attack is
to clone the epia code but rename everything epiam, and add support for the
proper north + south bridges and mainboard init code. Which means porting
these components from v1:
vt8623 northbridge
vt8235 southbridge
vt1211 superio device

Currently to get serial output working I grabbed the vt1211 serial init
code and just shoved it into the auto.c of the epiam for now, calling it
enable_vt1211_serial...

Modified the default 19200 baud to 115200 baud (but I actually get 57600 baud).

If anyone can offer any warnings or advice it would be helpful.

I may get called off this project at any time though...

-Dave


From xpegenaute at telepolis.es  Fri Nov 21 11:11:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Fri Nov 21 11:11:00 2003
Subject: SST39SF040
Message-ID: <1069433168.507.19.camel@p-133>

Hi,

any one know why is not useful the SST39SF040 ? i'm using epia-m and it
works fine with SST39SF020 but with the other one the computer is dead.

I saw the technical papers and speak in the same way with 020 and 040
then it should be the same? or may be i don't know to read this papers
:-)

Xavi.



From jbors at mail.ru  Fri Nov 21 11:15:01 2003
From: jbors at mail.ru (Dmitry Borisov)
Date: Fri Nov 21 11:15:01 2003
Subject: EPIA-M 600 Cannot start
References: <200311211320.hALDKT84005272@enterprise2.newlogic.at>
Message-ID: <00d801c3b04f$4df4a710$0300a8c0@amr.corp.intel.com>

Thanks Niki,
It look almost the same as mine. Appreciate if you can send me working image
so I can narrow down the problem.
Dmitry/

----- Original Message ----- 
From: "Niki Waibel" <niki.waibel at newlogic.com>
To: "Dmitry Borisov" <jbors at mail.ru>
Cc: <linuxbios at clustermatic.org>
Sent: Friday, November 21, 2003 5:20 AM
Subject: Re: EPIA-M 600 Cannot start


> i am using a epia-m 600 with success.
> current cvs of freebios/linuxbios version1 works fine.
>
> i used:
> ===
> $ cat ../example.config | grep -v ^# | grep -v ^$
> target /home/niki/packages/freebios-20031024-build
> mainboard via/epia-m
> option SERIAL_CONSOLE=1
> option TTYS0_BAUD=115200
> option DEFAULT_CONSOLE_LOGLEVEL=9
> option DEBUG=1
> option RAMTEST=1
> option USE_GENERIC_ROM=1
> option STD_FLASH=1
> option ROM_SIZE=262144
> option PAYLOAD_SIZE=196608
> option USE_ELF_BOOT=1
> payload /home/niki/packages/filo-0.4/filo.elf
> ===
>
> there is currently a problem with the speed of the serial port.
> it might be a baudrate less (in my case it is 57600 although i
> specified 115200).
>
> i can send you my romimage for testing if you want.
>
> gcc: 3.3.1
> binutils: 2.14
> (should not matter)



From rminnich at lanl.gov  Fri Nov 21 11:29:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 21 11:29:01 2003
Subject: V2 epia-m support [PMX:#]
In-Reply-To: <200311211634.hALGYK9R011522@xdr.com>
Message-ID: <Pine.LNX.4.44.0311211004020.12385-100000@maxroach.lanl.gov>

get as far as you can and send me diffs. I will apply those which look 
like they fit into v2 ok, but make sure you understand the v2 epia port.

thanks very much

ron



From rminnich at lanl.gov  Fri Nov 21 11:32:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 21 11:32:00 2003
Subject: SST39SF040
In-Reply-To: <1069433168.507.19.camel@p-133>
Message-ID: <Pine.LNX.4.44.0311211004460.12385-100000@maxroach.lanl.gov>

On 21 Nov 2003, Xavier Pegenaute wrote:

> any one know why is not useful the SST39SF040 ? i'm using epia-m and it
> works fine with SST39SF020 but with the other one the computer is dead.

did you build a 512K image or just a 256K image? this is a common mistake.

ron



From xpegenaute at telepolis.es  Fri Nov 21 12:00:01 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Fri Nov 21 12:00:01 2003
Subject: SST39SF040
In-Reply-To: <Pine.LNX.4.44.0311211004460.12385-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311211004460.12385-100000@maxroach.lanl.gov>
Message-ID: <1069436094.504.32.camel@p-133>

Hi,

> did you build a 512K image or just a 256K image? this is a common mistake.

I'm not so sure but i think that I made it fine. But i have some questions:

-------------------------------------------------------------------

#
# LinuxBIOS config file for: VIA epia mini-itx
#

# via epia
mainboard via/epia-m

# Enable Serial Console for debugging
option SERIAL_CONSOLE=1
option TTYS0_BAUD=115200
option DEFAULT_CONSOLE_LOGLEVEL=9
option DEBUG=1

# Use 256KB Standard Flash as Normal BIOS
option RAMTEST=1
option USE_GENERIC_ROM=1
option STD_FLASH=1
#option ZKERNEL_START=0xfffc0000
#option ROM_SIZE=262144
option ROM_SIZE=524288

# payload size = 192KB
#option PAYLOAD_SIZE=196608
#option PAYLOAD_SIZE=458752 <-- I thougt that was this value because 
                            <-- 256K - 64K = 196608.
option PAYLOAD_SIZE=1      <-- I tried also with this because is the
                           <-- parameter "bs" of "dd". With the other
                           <-- one the size of romimage was too big.

# use ELF Loader to load Etherboot
option USE_ELF_BOOT=1

# Use Etherboot as our payload
#payload /home/xavi/via-rhine.elf
payload /home/xavi/filo-0.4.1/filo.elf
#payload /bzImage.elf

target /home/xavi/epia-m
------------------------------------------------------------

Is there some better manual for the actual options of "freebios" than
"configmanual.ps"  think this is too old ?

Xavi.




From linuxbios at xdr.com  Fri Nov 21 12:45:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Nov 21 12:45:01 2003
Subject: v2 epia-m progress
Message-ID: <200311211820.hALIKpeD011897@xdr.com>

I did a quick hack to enable the DDR memory just like v1's epia-m hack.
The northbridge.c just has a single function sizeram() which I implemented
to just return as if there is 64M of memory. I commented out the
attempts to init the smbus + sdram, and let everything proceed. It got
to the etherboot payload, requested a bootfile, loaded it, launched linux,
and initialized linux quite well, then crapped out trying to do network
activity. It is obviously an interrupt problem, packets are coming out of
the box but it can't receive them.

This is very encouraging after about 3 hours or so. I haven't really done
any initialization of either the north or south bridge, just the hack to
initialize the DDR memory. I converted the asm code to 'C' but it is
still hardcoded as opposed to reading the SPD contents.

This was actually a surprise, I was expecting it to fail further along in
linuxbios and suddenly all these linux messages were coming out.

-Dave


From rminnich at lanl.gov  Fri Nov 21 12:59:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 21 12:59:01 2003
Subject: v2 epia-m progress
In-Reply-To: <200311211820.hALIKpeD011897@xdr.com>
Message-ID: <Pine.LNX.4.44.0311211133340.12385-100000@maxroach.lanl.gov>

use the v2 epia port as a model on how to set up interrupts.

ron



From linuxbios at xdr.com  Fri Nov 21 13:40:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Nov 21 13:40:00 2003
Subject: v2 epia-m progress
Message-ID: <200311211915.hALJFsYu012074@xdr.com>

>use the v2 epia port as a model on how to set up interrupts.

Can you point me in the right direction? What I've done so far is go into
src/mainboard/via/epiam  (cloned from epia)
I regenerated irq_tables.c by flashing with award bios, booting up the board,
then running the getpir.c utility from version1 (note this utility isn't
present in version 2).

It is still calling the 8231 code. Is the interrupt stuff in with the
southbridge? Or is it the northbridge?

-Dave


From rminnich at lanl.gov  Fri Nov 21 13:56:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 21 13:56:00 2003
Subject: v2 epia-m progress [PMX:#]
In-Reply-To: <200311211915.hALJFsYu012074@xdr.com>
Message-ID: <Pine.LNX.4.44.0311211227450.12385-100000@maxroach.lanl.gov>

interrupts are set up in the mainboard (since that determines everything).

Following earlier work i erroneously put this in 
src/southbridge/vt8231/vt8231.c, which is wrong. I have to move this code 
to src/mainboard/via/epia/mainboard.c

here's the code

/* PIRQ init
 */
void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char 
pIntAtoD[4]);


static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };

/*
        Our IDSEL mappings are as follows
        PCI slot is AD31          (device 15) (00:14.0)
        Southbridge is AD28       (device 12) (00:11.0)
*/
static void pci_routing_fixup(void)
{
        device_t dev;

        dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 
0);
        printk_info("%s: dev is %p\n", __FUNCTION__, dev);
        if (dev) {
                /* initialize PCI interupts - these assignments depend
                   on the PCB routing of PINTA-D 

                   PINTA = IRQ11
                   PINTB = IRQ5
                   PINTC = IRQ10
                   PINTD = IRQ12
                */
                pci_write_config8(dev, 0x55, 0xb0);
                pci_write_config8(dev, 0x56, 0xa5);
                pci_write_config8(dev, 0x57, 0xc0);
        }

        // Standard southbridge components
        printk_info("setting southbridge\n");
        pci_assign_irqs(0, 0x11, southbridgeIrqs);

        // Ethernet built into southbridge
        printk_info("setting ethernet\n");
        pci_assign_irqs(0, 0x12, enetIrqs);

        // PCI slot
        printk_info("setting pci slot\n");
        pci_assign_irqs(0, 0x14, slotIrqs);
        printk_info("%s: DONE\n", __FUNCTION__);
}





From leon.woestenberg at gmx.net  Fri Nov 21 14:21:00 2003
From: leon.woestenberg at gmx.net (Leon Woestenberg)
Date: Fri Nov 21 14:21:00 2003
Subject: SST39SF040
References: <Pine.LNX.4.44.0311211004460.12385-100000@maxroach.lanl.gov>
Message-ID: <001401c3b069$97a455d0$a700a8c0@campus.tue.nl>

Hello,

> > any one know why is not useful the SST39SF040 ? i'm using epia-m and it
> > works fine with SST39SF020 but with the other one the computer is dead.
>
> did you build a 512K image or just a 256K image? this is a common mistake.
>
I think it is safe to build a 256kB image but you have to put it in the
UPPER
half of the SST39SF040.

This worked for me. See my scriblings here:

http://www.coredinal.nl/~leon/epia/gentoo/

Regards,

Leon.



From rminnich at lanl.gov  Fri Nov 21 14:31:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Fri Nov 21 14:31:01 2003
Subject: SST39SF040
In-Reply-To: <001401c3b069$97a455d0$a700a8c0@campus.tue.nl>
Message-ID: <Pine.LNX.4.44.0311211305370.12385-100000@maxroach.lanl.gov>

On Fri, 21 Nov 2003, Leon Woestenberg wrote:

> I think it is safe to build a 256kB image but you have to put it in the
> UPPER half of the SST39SF040.

yes, just do this:

cat romimage romimage > romimage.512k
flash_rom romimage.512k

done.

ron



From linuxbios at xdr.com  Fri Nov 21 15:48:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Fri Nov 21 15:48:01 2003
Subject: V2 epia-m link to tarball
Message-ID: <200311212123.hALLN4kL012498@xdr.com>

I got the interrupts working as per Ron's advice, also pulled the
irq fixup stuff out of the vt8235 source and stuck it in with mainboard.c.

I made a tarball of the changes, it can be downloaded here:
http://www.xdr.com/dash/linuxbios

I'll update that directory as I make changes.

I think the vt8623 code is pretty much finished except I need to turn on VGA.
The vt8235 tree is basically a clone of the vt8231 tree with all occurances
of 8231 changed to 8235, and the PCI ID's changed. This probably needs some
major rework (trying to initialize devices that aren't there + not initializing
devices that are there.

However I'm at a state where I can boot the system on the bios and get into
linux. DDR init is the same as V1 for now.

I'm planning on getting vga up and hopefully the vga bios. Once that is
functional I'll be pretty close to where I was on V1. Then I'll try to get
the smbus going to access the spd registers. Then hopefully someone else
can take it from there and do the actual ddr configuration from spd (I hope).

-Dave


From stepan at suse.de  Fri Nov 21 18:39:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Fri Nov 21 18:39:01 2003
Subject: [announce] LinuxBIOS on AMD64
In-Reply-To: <Pine.LNX.4.44.0311201039220.3611-100000@maxroach.lanl.gov>
References: <3FBCFCF3.3010504@nexpath.com> <Pine.LNX.4.44.0311201039220.3611-100000@maxroach.lanl.gov>
Message-ID: <20031122001425.GA19697@suse.de>

* ron minnich <rminnich at lanl.gov> [031120 18:39]:
> I prefer latex for this, as cvs works on it well. 
> 
> I can't stand open office, sorry.

It uses xml for storing it's files. I even got the tex export plugin to
work, but that is nothing you want to work on later on.

I'm almost done converting the document to LaTeX manually. Just the
graphics and some text formats are missing. And I have to find out how I
choose a less coltish font to get the document readable again ;)

  Stefan



From stepan at suse.de  Sat Nov 22 09:45:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Sat Nov 22 09:45:01 2003
Subject: [announce] LinuxBIOS on AMD64
In-Reply-To: <20031120120949.GA10860@suse.de>
References: <20031120120949.GA10860@suse.de>
Message-ID: <20031122152025.GA22170@suse.de>

* Stefan Reinauer <stepan at suse.de> [031120 13:09]:
> I wrote a paper on LinuxBIOS on the AMD64 platform that covers
> some aspects on the following topics:
> 
>  * image configuration
>  * porting LinuxBIOS to new AMD64 motherboards
>  * debugging and tweaking hints
>  * some internals 
[..]
> Don't hesitate to make suggestions on improvement, report typos, badly
> written english, or whatever comes to your mind when reading the paper.

In order to make this document easily changeable and enhanceable, I
converted it to LaTeX now. I was using pdflatex to convert it to pdf. 

The document is commited to LinuxBIOS CVS now (freebios2/documentation).
Just doing a make in that directory should do the job.

Hope this way people can contribute now ;-)

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From stepan at suse.de  Sat Nov 22 10:00:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Sat Nov 22 10:00:01 2003
Subject: AMD64 Solo Hang - news
In-Reply-To: <m3islez7pf.fsf@maxwell.lnxi.com>
References: <20031120124642.GA11352@suse.de> <m3islez7pf.fsf@maxwell.lnxi.com>
Message-ID: <20031122153527.GB22170@suse.de>

* Eric W. Biederman <ebiederman at lnxi.com> [031121 05:06]:
> > it seems that the Solo motherboard is the only motherboard tested so far
> > that is based on an Athlon64 instead of Opteron CPUs..
> > 
> > The following code in src/northbridge/amd/amdk8/misc_control.c relies on
> > more than one hypertransport link being available:
> > 
> >         cmd = pci_read_config32(dev, 0xdc);
> >         if((cmd & 0x0000ff00) != 0x02500) {
> >                 cmd &= 0xffff00ff;
> >                 cmd |= 0x00002500;
> >                 pci_write_config32(dev, 0xdc, cmd );
> >                 printk_debug("resetting cpu\n");
> >                 hard_reset();
> >         }
> > 
> > This implicitly changes CPU0 Link1 FIFO Read Pointer Optimization, not
> > taking into regard that LDT1 might not be there.
> > 
> > It seems this code should rather check all links to see whether they are
> > connected and optimize _all_ of the connected.
> 
> Agreed. That part should certainly be more dynamic.  It looks like
> I missed that when I was syncing the trees.
 
Should this be done for all connected links or coherent links only?
(BKDG suggests setting this to 0x25 for all coherent links and for all
non-coherent links to other AMD chips)

What's the preferred way of fixing this? Walking all links on all nodes
once again? Or adding some configurable hard codes?

> > Is the CPU reset here really needed for the setting to become active?
> 
> I'm not certain.  But given that it is playing with hypertransport
> link settings I would assume so.  But that is worth confirming.

I got some update here:
The CPU-Reset/LDTSTOP is needed.
If the read pointer is set to safe 3/7 cycles read accesses get 10
cycles quicker ( 25ns with a 400MHz HT-Device)

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From niki.waibel at newlogic.com  Sat Nov 22 11:28:00 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Sat Nov 22 11:28:00 2003
Subject: VIA EPIA MII
Message-ID: <200311221703.hAMH3584021587@enterprise2.newlogic.at>

seems to be almost the same as the epia-m + Onboard CardBus / CompactFlash...

http://www.viaembedded.com/product/epia_MII_spec.jsp?motherboardId=202

Processor 
- VIA C3/ VIA Eden ESP processor
Chipset 
- VIA CLE266 North Bridge
- VIA VT8235 South Bridge
System Memory   
- 1 DDR266 DIMM socket
- Up to 1GB memory size
VGA
- Integrated VIA Unichrome 2D/3D graphics with MPEG-2 Accelerator,
  motion compensation and duo-view support

niki


From linuxbios at xdr.com  Sat Nov 22 12:12:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Sat Nov 22 12:12:00 2003
Subject: V2 dependency problems
Message-ID: <200311221747.hAMHlruX015519@xdr.com>

The auto.c file has #includes for things like raminit.c. If I change
the auto.c file and rebuild, the changes "take". If I change raminit.c,
the changes don't take. I have to touch the auto.c to get it to work. Does
everyone have this problem?

I do
cd targets ; ./buildtarget via/epiam

(Above done only once)

Then to rebuild
make -C via/epiam/epiam


One other note that I kind of recall being discussed. I cloned the vt8231
directory to make the vt8235 directory, but a lot of the separate pci devices
that are inside both devices are identical. Isn't there some way of separating
out the support code for the individual components maybe based on the pci
device id's? This would avoid code duplication.

Like the southbridge/via/vt8231 directory would be the toplevel file that
would glue together all the separate components. It would be a list of what
individual drivers to include + no redundancy. Maybe there could be another
area like
components/via/1106-0571

One thing that would be convenient though is devices that are almost exactly
the same but have different pci device id's. CVS doesn't like symlinks though.
You'd like the handler code to support all equivalent devices. So maybe having
the directory name based on the pci id is no good.

Maybe instead
components/via/ide/id.h
components/via/ide/handler.c

The id.h file would list the pci device id's the handler supports.

Just some thoughts.

-Dave


From peter.fox at aeroflex.com  Mon Nov 24 03:31:00 2003
From: peter.fox at aeroflex.com (Peter Fox)
Date: Mon Nov 24 03:31:00 2003
Subject: SST39SF040
In-Reply-To: <Pine.LNX.4.44.0311211305370.12385-100000@maxroach.lanl.gov>
Message-ID: <NEBBJLECKKOPJEEKNGJOGEIOECAA.peter.fox@aeroflex.com>

If you apply my patch to flash_rom I sent 6-Nov with the subject
"Add size option and checks to flash_rom" you can just use the
-s option to say the rom is 256k.

I haven't checked to see it you've committed the patch yet.

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200

  -----Original Message-----
  From: linuxbios-admin at clustermatic.org
  [mailto:linuxbios-admin at clustermatic.org]On Behalf Of ron minnich
  Sent: 21 November 2003 20:06
  To: Leon Woestenberg
  Cc: linuxbios at clustermatic.org
  Subject: Re: SST39SF040
  
  
  On Fri, 21 Nov 2003, Leon Woestenberg wrote:
  
  > I think it is safe to build a 256kB image but you have to put it in the
  > UPPER half of the SST39SF040.
  
  yes, just do this:
  
  cat romimage romimage > romimage.512k
  flash_rom romimage.512k
  
  done.
  
  ron
  
  _______________________________________________
  Linuxbios mailing list
  Linuxbios at clustermatic.org
  http://www.clustermatic.org/mailman/listinfo/linuxbios


From xpegenaute at telepolis.es  Mon Nov 24 06:08:00 2003
From: xpegenaute at telepolis.es (Xavier Pegenaute)
Date: Mon Nov 24 06:08:00 2003
Subject: linuxbios and 512Kb
Message-ID: <1069674220.505.23.camel@p-133>

Hi,

i'm still trying with 512Kb, and i have this problem when i want to put
an elf kernel:
------------------------------------------------------------

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    37:init_bytes() - zkernel_start:0xfff00000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
Dropping non PT_LOAD segment
New segment addr 0x10000 size 0x125e4 offset 0x130 filesize 0x137c
(cleaned up) New segment addr 0x10000 size 0x125e4 offset 0x130 filesize
0x137c
New segment addr 0x91000 size 0x70 offset 0x14ac filesize 0x0
(cleaned up) New segment addr 0x91000 size 0x70 offset 0x14ac filesize
0x0
New segment addr 0x100000 size 0x700000 offset 0x14ac filesize 0x659da
(cleaned up) New segment addr 0x100000 size 0x700000 offset 0x14ac
filesize 0x659da
Loading Segment: addr: 0x0000000005f70fe8 memsz: 0x00000000000125e4
filesz: 0x000000000000137c
Clearing Segment: addr: 0x0000000005f72364 memsz: 0x0000000000011268
Loading Segment: addr: 0x0000000000091000 memsz: 0x0000000000000070
filesz: 0x0000000000000000
Clearing Segment: addr: 0x0000000000091000 memsz: 0x0000000000000070
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000700000
filesz: 0x00000000000659da
Clearing Segment: addr: 0x00000000001659da memsz: 0x000000000069a626
Image checksum: 604a != computed checksum: e8c1
Cannot Load ELF Image
------------------------------------------------------------

If i start it with filo it works perfectly (i don't need copy two times
an image of 256, i have ROM_IMAGE=458752). I use to record it the flash
utility but doing some dirty techniques (SST39SF040), the checksum if
i'm not wrong is not calculated in the flash_rom utility. Some idea ?

Xavi.
Thanks.



From rminnich at lanl.gov  Mon Nov 24 10:10:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Mon Nov 24 10:10:00 2003
Subject: SST39SF040
In-Reply-To: <NEBBJLECKKOPJEEKNGJOGEIOECAA.peter.fox@aeroflex.com>
Message-ID: <Pine.LNX.4.44.0311240845170.11449-100000@maxroach.lanl.gov>

i thought i had commoitted this but please check and resend patch if 
needed.

ron



From ebiederman at lnxi.com  Mon Nov 24 11:03:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Nov 24 11:03:01 2003
Subject: AMD64 Solo Hang - news
In-Reply-To: <20031122153527.GB22170@suse.de>
References: <20031120124642.GA11352@suse.de> <m3islez7pf.fsf@maxwell.lnxi.com>
	<20031122153527.GB22170@suse.de>
Message-ID: <m3ekvxafca.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * Eric W. Biederman <ebiederman at lnxi.com> [031121 05:06]:
> > > it seems that the Solo motherboard is the only motherboard tested so far
> > > that is based on an Athlon64 instead of Opteron CPUs..
> > > 
> > > The following code in src/northbridge/amd/amdk8/misc_control.c relies on
> > > more than one hypertransport link being available:
> > > 
> > >         cmd = pci_read_config32(dev, 0xdc);
> > >         if((cmd & 0x0000ff00) != 0x02500) {
> > >                 cmd &= 0xffff00ff;
> > >                 cmd |= 0x00002500;
> > >                 pci_write_config32(dev, 0xdc, cmd );
> > >                 printk_debug("resetting cpu\n");
> > >                 hard_reset();
> > >         }
> > > 
> > > This implicitly changes CPU0 Link1 FIFO Read Pointer Optimization, not
> > > taking into regard that LDT1 might not be there.
> > > 
> > > It seems this code should rather check all links to see whether they are
> > > connected and optimize _all_ of the connected.
> > 
> > Agreed. That part should certainly be more dynamic.  It looks like
> > I missed that when I was syncing the trees.
>  
> Should this be done for all connected links or coherent links only?
> (BKDG suggests setting this to 0x25 for all coherent links and for all
> non-coherent links to other AMD chips)
> 
> What's the preferred way of fixing this? Walking all links on all nodes
> once again? Or adding some configurable hard codes?

Given where the code is at I was just going to walk the links on the
local chip and assume we were connected to other AMD parts.  It may
be reasonable to move all of this to the general HT link setup if we
can reasonably abstract it into methods.

> > > Is the CPU reset here really needed for the setting to become active?
> > 
> > I'm not certain.  But given that it is playing with hypertransport
> > link settings I would assume so.  But that is worth confirming.
> 
> I got some update here:
> The CPU-Reset/LDTSTOP is needed.
> If the read pointer is set to safe 3/7 cycles read accesses get 10
> cycles quicker ( 25ns with a 400MHz HT-Device)

Ok That confirms the reset needs to happen.  Note I believe the
commented out hard_reset as part of one of the errata fixes also needs
to happen, and right now one is causing the other.

Eric


From ts1 at tsn.or.jp  Mon Nov 24 12:02:23 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Mon Nov 24 12:02:23 2003
Subject: linuxbios and 512Kb
In-Reply-To: <1069674220.505.23.camel@p-133>
References: <1069674220.505.23.camel@p-133>
Message-ID: <20031124173618.GB23903@tsn.or.jp>

On Mon, Nov 24, 2003 at 12:43:40PM +0100, Xavier Pegenaute wrote:
> Dropping non PT_LOAD segment
> New segment addr 0x10000 size 0x125e4 offset 0x130 filesize 0x137c
> (cleaned up) New segment addr 0x10000 size 0x125e4 offset 0x130 filesize
> 0x137c
> New segment addr 0x91000 size 0x70 offset 0x14ac filesize 0x0
> (cleaned up) New segment addr 0x91000 size 0x70 offset 0x14ac filesize
> 0x0
> New segment addr 0x100000 size 0x700000 offset 0x14ac filesize 0x659da
> (cleaned up) New segment addr 0x100000 size 0x700000 offset 0x14ac
> filesize 0x659da
> Loading Segment: addr: 0x0000000005f70fe8 memsz: 0x00000000000125e4
> filesz: 0x000000000000137c
> Clearing Segment: addr: 0x0000000005f72364 memsz: 0x0000000000011268
> Loading Segment: addr: 0x0000000000091000 memsz: 0x0000000000000070
> filesz: 0x0000000000000000
> Clearing Segment: addr: 0x0000000000091000 memsz: 0x0000000000000070
> Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000700000
> filesz: 0x00000000000659da
> Clearing Segment: addr: 0x00000000001659da memsz: 0x000000000069a626
> Image checksum: 604a != computed checksum: e8c1
> Cannot Load ELF Image
> ------------------------------------------------------------

The address of segment 0 is strange... (0x0000000005f70fe8)
Is your src/lib/elfboot.c up-to-date?

-- 
Takeshi


From mario.i at teol.net  Mon Nov 24 12:54:01 2003
From: mario.i at teol.net (Mario Ivancic)
Date: Mon Nov 24 12:54:01 2003
Subject: beeper on Epia 800
Message-ID: <000d01c3b381$fad63040$1ca9fea9@alfa>

Hi !

I would like to use beeper or paralell port for debugging in early
stages of IPL for DoC Millennium Plus. My question is how can I
enable beeper or parallel port on Epia 800 board?
I have VT8231 datasheet, and it seems to me that beeper is enabled by
default, but it makes no sound.

Best regards,

Mario




From tyson at irobot.com  Mon Nov 24 19:11:01 2003
From: tyson at irobot.com (tyson at irobot.com)
Date: Mon Nov 24 19:11:01 2003
Subject: Off topic CF questions
Message-ID: <3FC2A671.8090301@irobot.com>

This is a bit off topic, but I need some pointers and we seem to have 
quite a few really smart people on this list. ;-)

I'm trying to learn about the issues and solutions to using CF cards for 
data logging in appliances where the power may be pulled at any time.

There are sort of two classes of logging.  One would be classic "write 
only" logging.  The other would be things like total run time, an 
odometer, that sort of thing where you might want to something that 
amounts to erase the old value and over write it with a new one. 
Obviously the second case would degenerate a bit with at least "double 
buffering" and could get as "bad" as a "write only" log history.

I say write only, meaning that the download/reset/erase procedure could 
be under controlled conditions and not a concern.

My issue is that CF cards present and IDE abstraction that hides the 
underlying block sizes and the fact that FLASH is erased as a block (and 
unknown block) and rewritten from scratch.  I have absolutely no idea 
what size these blocks are such that I might separate my "read-only" 
partitions from my "write only" partitions with a buffer partition.  I 
also have absolutely no idea what happens to these things when the power 
is pulled, esp. in the middle of an erase/write cycle or how these 
erase/write cycles might be optimised.

Any pointers or suggestions would be greatly appreciated.

Thanks!
Ty

-- 
Tyson D Sawyer                             iRobot Corporation
Senior Systems Engineer                    Military Systems Division
tsawyer at irobot.com                         Robots for the Real World
603-654-3400 ext 206                       http://www.irobot.com



From YhLu at tyan.com  Mon Nov 24 20:54:01 2003
From: YhLu at tyan.com (YhLu)
Date: Mon Nov 24 20:54:01 2003
Subject: Tyan S4880
Message-ID: <3174569B9743D511922F00A0C9431423039905AE@TYANWEB>

Stefan,

I'm porting Tyan S4880 now. I found that the following building err, do you
meet it in AMD board?

Even I only enable the CPU0's memctrl in the auto.c

objcopy -O binary linuxbios linuxbios.strip
gcc -o buildrom /home/yhlu/xx/xx/freebios2/util/buildrom/buildrom.c
./buildrom linuxbios.strip linuxbios.rom ../../tg3.zelf 0x10000 0x18000
linuxbios image is 65854 bytes; only 65536 allowed
Linuxbios input file larger than allowed size!

Regards

YH.


From riskin at esinosoft.com  Tue Nov 25 01:33:01 2003
From: riskin at esinosoft.com (riskin at esinosoft.com)
Date: Tue Nov 25 01:33:01 2003
Subject: migrate VIA vt5426 to PCChip M787CL(not M787CL+)
Message-ID: <200311250632.hAP6Wge13198@nwn.definitive.org>

After doing test,I find that if linux kernel scans devfn above 0xA0,
the chipset locks up.

Could somebody please give me advice to fix the bug?

riskin

>>After I migrated VIA vt5426 to new mainboard(PCChips M787CL,not M787CL+:
>> NB is VT8601,SB is VT82C686B),when probing PCI devices,the kernel
>> halted.So is there any option in LinuxBIOS need to be configed to avoid
>> the kernel halt? But the kernel can work well on PCChips M/B bios.

>This is an old bug with the chipset. I think we may still have a patch for 
>it. If linux scans any devfn above (I think) 0x40, the chipset locks up. 

>Sorry.

>ron


From eddyfu at pchome.com.tw  Tue Nov 25 02:07:01 2003
From: eddyfu at pchome.com.tw (eddyfu at pchome.com.tw)
Date: Tue Nov 25 02:07:01 2003
Subject: Any one help me!! VIA EPIA MII boot from CF card(PCMCIA) with LinuxBIOS + filo problem
Message-ID: <20031125074249.73714657261@msx.pchome.com.tw>

Hi All:

  How to use VIA EPIA MII to boot from CF card(PCMCIA) with LinuxBIOS + filo problem?
  
  Could the LinuxBIOS CVS v1 work on EPIA MII?
     
Best regards,
Eddy
==========================================================
 ??????????
 http://edm-prg.epaper.com.tw/click.php?ad_code=36092
==========================================================
 PChome??~~????? \*^o^*//
 http://love.pchome.com.tw/
==========================================================


From aip at cwlinux.com  Tue Nov 25 02:26:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Tue Nov 25 02:26:01 2003
Subject: migrate VIA vt5426 to PCChip M787CL(not M787CL+)
In-Reply-To: <200311250632.hAP6Wge13198@nwn.definitive.org>; from riskin@esinosoft.com on Tue, Nov 25, 2003 at 03:09:11PM -0600
References: <200311250632.hAP6Wge13198@nwn.definitive.org>
Message-ID: <20031125160205.A23582@mail.cwlinux.com>

Hi,

> After doing test,I find that if linux kernel scans devfn above 0xA0,
> the chipset locks up.
> Could somebody please give me advice to fix the bug?
You can just skip it.  It is how I solved it.

-Andrew

> >>After I migrated VIA vt5426 to new mainboard(PCChips M787CL,not M787CL+:
> >> NB is VT8601,SB is VT82C686B),when probing PCI devices,the kernel
> >> halted.So is there any option in LinuxBIOS need to be configed to avoid
> >> the kernel halt? But the kernel can work well on PCChips M/B bios.
> 
> >This is an old bug with the chipset. I think we may still have a patch for 
> >it. If linux scans any devfn above (I think) 0x40, the chipset locks up. 
> 
> >Sorry.
> 
> >ron
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From ts1 at tsn.or.jp  Tue Nov 25 02:53:00 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Tue Nov 25 02:53:00 2003
Subject: Any one help me!! VIA EPIA MII boot from CF card(PCMCIA) with LinuxBIOS + filo problem
In-Reply-To: <20031125074249.73714657261@msx.pchome.com.tw>
References: <20031125074249.73714657261@msx.pchome.com.tw>
Message-ID: <20031125082927.GA28179@tsn.or.jp>

On Tue, Nov 25, 2003 at 03:42:13PM +0000, eddyfu at pchome.com.tw wrote:
>   How to use VIA EPIA MII to boot from CF card(PCMCIA) with LinuxBIOS + filo problem?

I don't think FILO can read files from CF card in the PCMCIA slot.
It can read CF on the IDE.

-- 
Takeshi


From stepan at suse.de  Tue Nov 25 04:18:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Tue Nov 25 04:18:01 2003
Subject: Tyan S4880
In-Reply-To: <3174569B9743D511922F00A0C9431423039905AE@TYANWEB>
References: <3174569B9743D511922F00A0C9431423039905AE@TYANWEB>
Message-ID: <20031125095338.GA5805@suse.de>

* YhLu <YhLu at tyan.com> [031125 03:37]:
> Stefan,
> 
> I'm porting Tyan S4880 now. I found that the following building err, do you
> meet it in AMD board?

No, the AMD boards build fine for me. 
gcc-3.3.1-29
binutils-2.14.90.0.6-8

> Even I only enable the CPU0's memctrl in the auto.c

It seems the struct itself in auto.c is pretty uncritical for size.
Other parts like the log level need a lot more tuning if you want the
image to be as verbose as possible. 

* Do you compile with romcc -O (not -O0 and not -O2)
* What's your max log level? The UP-build (Solo) allows me to 
  put MAXIMUM_CONSOLE_LOGLEVEL up to 10, other builds want less.

> objcopy -O binary linuxbios linuxbios.strip
> gcc -o buildrom /home/yhlu/xx/xx/freebios2/util/buildrom/buildrom.c
> ./buildrom linuxbios.strip linuxbios.rom ../../tg3.zelf 0x10000 0x18000
> linuxbios image is 65854 bytes; only 65536 allowed
> Linuxbios input file larger than allowed size!

Is this 64k including payload size? I use:
option ROM_SIZE=262144
option FALLBACK_SIZE=131072
option ROM_IMAGE_SIZE=0x10000

guess the size issue should be mentioned in the docs. Everybody
fiddling with LinuxBIOS on AMD64 _has_ seen it..


  Stefan


-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From linuxbios at xdr.com  Tue Nov 25 12:04:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Tue Nov 25 12:04:00 2003
Subject: V2 dependency problems
Message-ID: <200311251739.hAPHdKs0025239@xdr.com>

The auto.c file has #includes for things like raminit.c. If I change
the auto.c file and rebuild, the changes "take". If I change raminit.c,
the changes don't take. I have to touch the auto.c to get it to work. Does
everyone have this problem?

I do
cd targets ; ./buildtarget via/epiam

(Above done only once)

Then to rebuild
make -C via/epiam/epiam


One other note that I kind of recall being discussed. I cloned the vt8231
directory to make the vt8235 directory, but a lot of the separate pci devices
that are inside both devices are identical. Isn't there some way of separating
out the support code for the individual components maybe based on the pci
device id's? This would avoid code duplication.

Like the southbridge/via/vt8231 directory would be the toplevel file that
would glue together all the separate components. It would be a list of what
individual drivers to include + no redundancy. Maybe there could be another
area like
components/via/1106-0571

One thing that would be convenient though is devices that are almost exactly
the same but have different pci device id's. CVS doesn't like symlinks though.
You'd like the handler code to support all equivalent devices. So maybe having
the directory name based on the pci id is no good.

Maybe instead
components/via/ide/id.h
components/via/ide/handler.c

The id.h file would list the pci device id's the handler supports.

Just some thoughts.

-Dave
PS Sorry if this is a duplicate. The original message didn't seem to work.


From rminnich at lanl.gov  Tue Nov 25 12:47:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 25 12:47:00 2003
Subject: V2 dependency problems
In-Reply-To: <200311251739.hAPHdKs0025239@xdr.com>
Message-ID: <Pine.LNX.4.44.0311251121300.10477-100000@maxroach.lanl.gov>

On Tue, 25 Nov 2003, Dave Ashley wrote:

> The auto.c file has #includes for things like raminit.c. If I change
> the auto.c file and rebuild, the changes "take". If I change raminit.c,
> the changes don't take. I have to touch the auto.c to get it to work. Does
> everyone have this problem?
> 
> I do
> cd targets ; ./buildtarget via/epiam

This is a known problem, we probably need to do a makedepend on auto.c 
when we make the makefile.

> One other note that I kind of recall being discussed. I cloned the vt8231
> directory to make the vt8235 directory, but a lot of the separate pci devices
> that are inside both devices are identical. Isn't there some way of separating
> out the support code for the individual components maybe based on the pci
> device id's? This would avoid code duplication.

not sure. I don't want to go too far with this; we're trying to avoid 
putting a whole device driver layer into a bios.

ron



From a.mimms at f5.com  Tue Nov 25 13:34:00 2003
From: a.mimms at f5.com (Alan Mimms)
Date: Tue Nov 25 13:34:00 2003
Subject: Off topic CF questions
Message-ID: <B6DFCBE338DE6741A24ECEA890730A19E0DE58@exchtwo>

We have information from a Compact Flash manufacturer that says you
should have hardware to solve this problem - I do not believe there is a
software solution.  The problem is caused by the fact (as you state)
that CF stores metadata in the flash blocks along with the disk block
data.  If the metadata is corrupted by an aborted write, it can affect
all of the disk blocks stored in the flash block, and the metadata can
even be so corrupt that you lose unrelated blocks.  Our most common
scenario for failure is to lose disk block #0, which, of course, is the
boot block for our OS.
We solve this using hardware.  You need to use buffers to disconnect the
CF's ATA reset, output-enable and write-enable signals from their source
on the bus, and hold up DC power to the pull-ups, the buffers and the CF
itself for at least 10ms-20ms after detecting the imminent loss of
power.
This is being implemented in our new hardware designs, and we have not
yet gotten one back from fabrication to test.  But it sure looks like it
will work to solve the problem.
Alan Mimms, Senior Architect
F5 Networks, Inc.  Spokane Development Center
Liberty Lake, Washington
v: 509-343-3524   f: 509-343-3501


-----Original Message-----
From: linuxbios-admin at clustermatic.org
[mailto:linuxbios-admin at clustermatic.org] On Behalf Of tyson at irobot.com
Sent: Monday, November 24, 2003 4:47 PM
To: LinuxBIOS
Subject: Off topic CF questions

This is a bit off topic, but I need some pointers and we seem to have 
quite a few really smart people on this list. ;-)

I'm trying to learn about the issues and solutions to using CF cards for

data logging in appliances where the power may be pulled at any time.

There are sort of two classes of logging.  One would be classic "write 
only" logging.  The other would be things like total run time, an 
odometer, that sort of thing where you might want to something that 
amounts to erase the old value and over write it with a new one. 
Obviously the second case would degenerate a bit with at least "double 
buffering" and could get as "bad" as a "write only" log history.

I say write only, meaning that the download/reset/erase procedure could 
be under controlled conditions and not a concern.

My issue is that CF cards present and IDE abstraction that hides the 
underlying block sizes and the fact that FLASH is erased as a block (and

unknown block) and rewritten from scratch.  I have absolutely no idea 
what size these blocks are such that I might separate my "read-only" 
partitions from my "write only" partitions with a buffer partition.  I 
also have absolutely no idea what happens to these things when the power

is pulled, esp. in the middle of an erase/write cycle or how these 
erase/write cycles might be optimised.

Any pointers or suggestions would be greatly appreciated.

Thanks!
Ty

-- 
Tyson D Sawyer                             iRobot Corporation
Senior Systems Engineer                    Military Systems Division
tsawyer at irobot.com                         Robots for the Real World
603-654-3400 ext 206                       http://www.irobot.com

_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From svante.signell at telia.com  Tue Nov 25 13:58:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Tue Nov 25 13:58:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1068977645.10203.76.camel@em2.my.own.domain>
References: <Pine.LNX.4.44.0311151253520.8662-100000@maxroach.lanl.gov>
	 <1068977645.10203.76.camel@em2.my.own.domain>
Message-ID: <1069788862.15097.68.camel@em2.my.own.domain>

Do I need to use gcc-2.95.x instead of gcc-3.3.2 to make the inline
assembly run OK? Or is there something about 16bit mode versus 32bit
mode?

On Sun, 2003-11-16 at 11:14, Svante Signell wrote:
> I did boot another kernel and for that kernel there was one entry for
> mtrr, so this seems to work. However, now I have tried executing both
> the mtrr and cache activation code, and when coming to any inline
> assembly code the program exits with a segfault :( All commented out
> calls have been tried one after the other by single-stepping with gdb. 
> 
> Below is the main progam I used:
> 
> #include <mem.h>
> main()
> {
>   struct mem_range mem;
>   int res = iopl(3);
>   if(res) {error();exit(-1);}
>   //  cache_enable();
>   //  p6_configure_l2_cache();
>   cache_on(mem);
> }
>  
> On Sat, 2003-11-15 at 20:54, ron minnich wrote:
> > On Sun, 16 Nov 2003, Takeshi Sone wrote:
> > 
> > > On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
> > > > # Faulty system:
> > > > cat /proc/mtrr
> > > > cat: /proc/mtrr: No such file or directory
> > > 
> > > I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
> > > (MTRR is the registers that tell CPU where to cache)
> > 
> > 
> > no, even if bios does not set mtrr, those registers exist, and are 
> > readable. Something weird is going on here!
> > 
> > ron



From YhLu at tyan.com  Tue Nov 25 14:05:01 2003
From: YhLu at tyan.com (YhLu)
Date: Tue Nov 25 14:05:01 2003
Subject: Tyan S4880
Message-ID: <3174569B9743D511922F00A0C943142303990604@TYANWEB>

Thanks, Stefan, 
After I change 
MAXIMUM_CONSOLE_LOGLEVEL from 9 to 8 it works.

YH.


-----????-----
???: Stefan Reinauer [mailto:stepan at suse.de] 
????: 2003?11?25? 1:54
???: YhLu
??: Eric W. Biederman; linuxbios at clustermatic.org
??: Re: Tyan S4880

* YhLu <YhLu at tyan.com> [031125 03:37]:
> Stefan,
> 
> I'm porting Tyan S4880 now. I found that the following building err, do
you
> meet it in AMD board?

No, the AMD boards build fine for me. 
gcc-3.3.1-29
binutils-2.14.90.0.6-8

> Even I only enable the CPU0's memctrl in the auto.c

It seems the struct itself in auto.c is pretty uncritical for size.
Other parts like the log level need a lot more tuning if you want the
image to be as verbose as possible. 

* Do you compile with romcc -O (not -O0 and not -O2)
* What's your max log level? The UP-build (Solo) allows me to 
  put MAXIMUM_CONSOLE_LOGLEVEL up to 10, other builds want less.

> objcopy -O binary linuxbios linuxbios.strip
> gcc -o buildrom /home/yhlu/xx/xx/freebios2/util/buildrom/buildrom.c
> ./buildrom linuxbios.strip linuxbios.rom ../../tg3.zelf 0x10000 0x18000
> linuxbios image is 65854 bytes; only 65536 allowed
> Linuxbios input file larger than allowed size!

Is this 64k including payload size? I use:
option ROM_SIZE=262144
option FALLBACK_SIZE=131072
option ROM_IMAGE_SIZE=0x10000

guess the size issue should be mentioned in the docs. Everybody
fiddling with LinuxBIOS on AMD64 _has_ seen it..


  Stefan


-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From ts1 at tsn.or.jp  Tue Nov 25 15:24:01 2003
From: ts1 at tsn.or.jp (Takeshi Sone)
Date: Tue Nov 25 15:24:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1069788862.15097.68.camel@em2.my.own.domain>
References: <Pine.LNX.4.44.0311151253520.8662-100000@maxroach.lanl.gov> <1068977645.10203.76.camel@em2.my.own.domain> <1069788862.15097.68.camel@em2.my.own.domain>
Message-ID: <20031125210023.GA21472@tsn.or.jp>

On Tue, Nov 25, 2003 at 08:34:22PM +0100, Svante Signell wrote:
> Do I need to use gcc-2.95.x instead of gcc-3.3.2 to make the inline
> assembly run OK? Or is there something about 16bit mode versus 32bit
> mode?

I bet it's not the compiler problem.
I guess it's a kernel-mode vs. user-mode problem.
I'm not very sure but some instructions like cache manupilation
need to be run in kernel-mode, even if IOPL=3.
If such instructions executed in user-mode, it results in segfault.
So you have to run your cache activation code in the kernel, either
put that code in the kernel itself or to make a kernel module to do it.

However, I don't know what exact code you need to enable the cache,
given that MTRR is working..

> On Sun, 2003-11-16 at 11:14, Svante Signell wrote:
> > I did boot another kernel and for that kernel there was one entry for
> > mtrr, so this seems to work. However, now I have tried executing both
> > the mtrr and cache activation code, and when coming to any inline
> > assembly code the program exits with a segfault :( All commented out
> > calls have been tried one after the other by single-stepping with gdb. 
> > 
> > Below is the main progam I used:
> > 
> > #include <mem.h>
> > main()
> > {
> >   struct mem_range mem;
> >   int res = iopl(3);
> >   if(res) {error();exit(-1);}
> >   //  cache_enable();
> >   //  p6_configure_l2_cache();
> >   cache_on(mem);
> > }
> >  
> > On Sat, 2003-11-15 at 20:54, ron minnich wrote:
> > > On Sun, 16 Nov 2003, Takeshi Sone wrote:
> > > 
> > > > On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
> > > > > # Faulty system:
> > > > > cat /proc/mtrr
> > > > > cat: /proc/mtrr: No such file or directory
> > > > 
> > > > I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
> > > > (MTRR is the registers that tell CPU where to cache)
-- 
Takeshi


From rminnich at lanl.gov  Tue Nov 25 15:31:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Tue Nov 25 15:31:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <20031125210023.GA21472@tsn.or.jp>
Message-ID: <Pine.LNX.4.44.0311251406230.10874-100000@maxroach.lanl.gov>

what I did to test this code was to build a kernel module for my linux, 
with this code inside, and insmod the kernel module.

ron



From JJia at Fortinet.com  Tue Nov 25 16:17:00 2003
From: JJia at Fortinet.com (Jia Jianwei)
Date: Tue Nov 25 16:17:00 2003
Subject: DDR Bank1 is ont working on VT8623 northbrodge
Message-ID: <009d01c3b39d$ada895d0$3a4610ac@JiaJianwei>

I use the code of VT8623 to active DDR RAM, but only BANK 0 is working, BANK 1 is not working.If I only use BANK0 or BANK1, it is working well.  I tried to active it twice with only one bank setting, yes , It's working with memtest, but, PCI burst does not work, All PCI bus master device do not work.
Anybody can tell me Why?

Best Regards,
Jianwei
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From svante.signell at telia.com  Tue Nov 25 16:20:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Tue Nov 25 16:20:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <Pine.LNX.4.44.0311251406230.10874-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311251406230.10874-100000@maxroach.lanl.gov>
Message-ID: <1069797381.15097.72.camel@em2.my.own.domain>

Ron and Takeshi,

Thanks for the tip. I'll try that next. Any pointers how to create a
kernel module? So far I have only been writing code for user space.

On Tue, 2003-11-25 at 22:06, ron minnich wrote:
> what I did to test this code was to build a kernel module for my linux, 
> with this code inside, and insmod the kernel module.
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios


From riskin at esinosoft.com  Tue Nov 25 19:46:01 2003
From: riskin at esinosoft.com (riskin at esinosoft.com)
Date: Tue Nov 25 19:46:01 2003
Subject: migrate VIA vt5426 to PCChip M787CL(not M787CL+)
Message-ID: <200311260045.hAQ0j6e17275@nwn.definitive.org>

>> After doing test,I find that if linux kernel scans devfn above 0xA0,
>> the chipset locks up.
>> Could somebody please give me advice to fix the bug?

>You can just skip it.  It is how I solved it.

-Andrew



From linuxbios at xdr.com  Tue Nov 25 20:14:00 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Tue Nov 25 20:14:00 2003
Subject: DDR Bank1 is ont working on VT8623 northbrodge
Message-ID: <200311260150.hAQ1oCsY027017@xdr.com>

>I use the code of VT8623 to active DDR RAM, but only BANK 0 is working

epia-m doesn't configure the ddr automatically yet. Doubtful whether
version 1 will ever have it. Version 2 one day will...

I hacked freebios version 1 to configure 2 banks by adding a loop. You can
probably adapt this code to your needs.
http://www.xdr.com/dash/linuxbios

-Dave


From riskin at esinosoft.com  Tue Nov 25 20:49:01 2003
From: riskin at esinosoft.com (riskin at esinosoft.com)
Date: Tue Nov 25 20:49:01 2003
Subject: migrate VIA vt5426 to PCChip M787CL(not M787CL+)
Message-ID: <200311260148.hAQ1mMe17518@nwn.definitive.org>

Sorry for my bad mail! Thank you,Andrew!

Riskin


From rminnich at lanl.gov  Wed Nov 26 09:07:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 26 09:07:00 2003
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval (fwd)
Message-ID: <Pine.LNX.4.44.0311260742500.13880-100000@maxroach.lanl.gov>


---------- Forwarded message ----------
Date: Tue, 25 Nov 2003 23:18:53 -0800 (PST)
From: Bharata B Rao <bharata_rao at yahoo.com>
To: rminnich at lanl.gov
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval

Hello Ron,

Sorry for this unsolicited mail, but I am tempted to
request you to get me this moderator approval so that
this mail (see forwarded note) makes it to the list.
This mail of mine has been sitting with the moderator
for many days.

I am assuming that you are the moderator, if not
excuse me.

Regards,
Bharata.

--- Bharata B Rao <bharata_rao at yahoo.com> wrote:
> Date: Mon, 27 Oct 2003 00:10:32 -0800 (PST)
> From: Bharata B Rao <bharata_rao at yahoo.com>
> Subject: ACPI support in LinuxBIOS
> To: linuxbios at clustermatic.org
> 
> Hello,
> 
> I see from the archives that there was some talk
> about
> extracting ACPI tables from BIOS and implementing
> ACPI
> support in LinuxBIOS.
> 
> I would like to know, if there have been any
> attempts
> in this regard from anyone ?
> 
> Do you feel that this idea is still feasible ? Or
> should I assume that this is a dead idea as I see no
> mention about ACPI power management here since last
> year ?
> 
> Kindly CC your replies. Thanks for your time.
> 
> Regards,
> Bharata.
> 
> 
> __________________________________
> Do you Yahoo!?
> Exclusive Video Premiere - Britney Spears
> http://launch.yahoo.com/promos/britneyspears/
> 


__________________________________
Do you Yahoo!?
Protect your identity with Yahoo! Mail AddressGuard
http://antispam.yahoo.com/whatsnewfree



From niki.waibel at newlogic.com  Wed Nov 26 09:40:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Wed Nov 26 09:40:01 2003
Subject: intel dual netwokcard problem on epia-m
Message-ID: <200311261516.hAQFGH84008541@enterprise2.newlogic.at>

if use the dual nic with the award bios on the epia-m i get:
===
Intel(R) PRO/100 Network Driver - version 2.3.30-k1
Copyright (c) 2003 Intel Corporation
e100: eth0: Intel(R) PRO/100 Network Connection
  Hardware receive checksums enabled
  cpu cycle saver enabled
e100: eth1: Intel(R) PRO/100 Network Connection
  Hardware receive checksums enabled
  cpu cycle saver enabled
===

but if i use linuxbios:
===
Intel(R) PRO/100 Network Driver - version 2.3.30-k1
Copyright (c) 2003 Intel Corporation
PCI: No IRQ known for interrupt pin A of device 0000:02:04.0. Please try using pci=biosirq.
e100: eth0: Intel(R) PRO/100 Network Connection
  Hardware receive checksums enabled
  cpu cycle saver enabled
PCI: No IRQ known for interrupt pin A of device 0000:02:05.0. Please try using pci=biosirq.
e100: eth1: Intel(R) PRO/100 Network Connection
  Hardware receive checksums enabled
  cpu cycle saver enabled
===
and i cannot bring the interface up.
(i've not tried yet with pci=biosirq...)

everything is fine for a standard intel nic.

any idea?


From niki.waibel at newlogic.com  Wed Nov 26 09:52:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Wed Nov 26 09:52:01 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <200311261516.hAQFGH84008541@enterprise2.newlogic.at>
Message-ID: <200311261528.hAQFSh84010039@enterprise2.newlogic.at>

> and i cannot bring the interface up.
> (i've not tried yet with pci=biosirq...)

tried with pci=biosirq kernel commandline -- same result...
maybe it is the same result because my kernel supports
DIRECT pci access only? i am going to try a pci ANY access
kernel now...


From jarcher at pobox.com  Wed Nov 26 09:58:00 2003
From: jarcher at pobox.com (jarcher at pobox.com)
Date: Wed Nov 26 09:58:00 2003
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval (fwd)
In-Reply-To: <Pine.LNX.4.44.0311260742500.13880-100000@maxroach.lanl.gov
 >
Message-ID: <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>

I'll raise the question to the next level....

Has there been any discussion of putting any power management support into 
the LinuxBIOS.  I've got a possible need for some basics, like suspend to 
RAM.  Classic APM might be enough and simple to implement.  ACPI would be a 
good choice, but I'm not sure about how much ROM foot print would be needed.

Jordan

At 07:42 AM 11/26/2003 -0700, ron minnich wrote:

>---------- Forwarded message ----------
>Date: Tue, 25 Nov 2003 23:18:53 -0800 (PST)
>From: Bharata B Rao <bharata_rao at yahoo.com>
>To: rminnich at lanl.gov
>Subject: Fwd: ACPI support in LinuxBIOS - moderator approval
>
>Hello Ron,
>
>Sorry for this unsolicited mail, but I am tempted to
>request you to get me this moderator approval so that
>this mail (see forwarded note) makes it to the list.
>This mail of mine has been sitting with the moderator
>for many days.
>
>I am assuming that you are the moderator, if not
>excuse me.
>
>Regards,
>Bharata.
>
>--- Bharata B Rao <bharata_rao at yahoo.com> wrote:
> > Date: Mon, 27 Oct 2003 00:10:32 -0800 (PST)
> > From: Bharata B Rao <bharata_rao at yahoo.com>
> > Subject: ACPI support in LinuxBIOS
> > To: linuxbios at clustermatic.org
> >
> > Hello,
> >
> > I see from the archives that there was some talk
> > about
> > extracting ACPI tables from BIOS and implementing
> > ACPI
> > support in LinuxBIOS.
> >
> > I would like to know, if there have been any
> > attempts
> > in this regard from anyone ?
> >
> > Do you feel that this idea is still feasible ? Or
> > should I assume that this is a dead idea as I see no
> > mention about ACPI power management here since last
> > year ?
> >
> > Kindly CC your replies. Thanks for your time.
> >
> > Regards,
> > Bharata.
> >
> >
> > __________________________________
> > Do you Yahoo!?
> > Exclusive Video Premiere - Britney Spears
> > http://launch.yahoo.com/promos/britneyspears/
> >
>
>
>__________________________________
>Do you Yahoo!?
>Protect your identity with Yahoo! Mail AddressGuard
>http://antispam.yahoo.com/whatsnewfree
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
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From rminnich at lanl.gov  Wed Nov 26 10:23:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 26 10:23:01 2003
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval (fwd)
In-Reply-To: <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>
Message-ID: <Pine.LNX.4.44.0311260858460.13880-100000@maxroach.lanl.gov>

it's on the list, waiting for somebody to take a stab at it. 

ron



From jarcher at pobox.com  Wed Nov 26 10:26:01 2003
From: jarcher at pobox.com (jarcher at pobox.com)
Date: Wed Nov 26 10:26:01 2003
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval (fwd)
In-Reply-To: <Pine.LNX.4.44.0311260858460.13880-100000@maxroach.lanl.gov
 >
References: <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>
Message-ID: <5.2.1.1.2.20031126075900.03469880@mail.sizzard.com>

I may be making that stab in January.

Jordan

At 08:59 AM 11/26/2003 -0700, ron minnich wrote:
>it's on the list, waiting for somebody to take a stab at it.
>
>ron
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From stepan at suse.de  Wed Nov 26 10:43:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov 26 10:43:01 2003
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval (fwd)
In-Reply-To: <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>
References: <Pine.LNX.4.44.0311260742500.13880-100000@maxroach.lanl.gov> <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>
Message-ID: <20031126161853.GA19574@suse.de>

* jarcher at pobox.com <jarcher at pobox.com> [031126 16:32]:
> I'll raise the question to the next level....
> 
> Has there been any discussion of putting any power management support into 
> the LinuxBIOS.  I've got a possible need for some basics, like suspend to 
> RAM.  Classic APM might be enough and simple to implement.  ACPI would be a 
> good choice, but I'm not sure about how much ROM foot print would be needed.

Since ACPI is, similar to FCode, an interface based on abstracted binary
code, it would probably be easier to add ACPI support to LinuxBIOS than
supporting APM which needs code hooks.

The ACPI tables could be a) generated by or b) stored in LinuxBIOS as is
and will be found and interpreted by the Linux Kernel. But besides the
technical issues there's also a legal question when including ACPI tables
(some are patented by MS and not freely usable iirc, others might be
copyrighted by Awkward & Co.)
There are also kernel patches for Linux that allow attaching some of the
ACPI tables to an initial ramdisk. This can be used to override broken
bios ACPI tables with corrected ones without reflashing the bios.

Stefan

  
-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From jarcher at pobox.com  Wed Nov 26 11:10:00 2003
From: jarcher at pobox.com (jarcher at pobox.com)
Date: Wed Nov 26 11:10:00 2003
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval (fwd)
In-Reply-To: <20031126161853.GA19574@suse.de>
References: <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>
 <Pine.LNX.4.44.0311260742500.13880-100000@maxroach.lanl.gov>
 <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>
Message-ID: <5.2.1.1.2.20031126083812.035bd988@mail.sizzard.com>

I mentioned APM because it seemed the simplest.  Realisticaly you'd want to 
follow the LinuxBIOS approach and do minimal stuff at the BIOS level and 
move most of the information to a linux driver.  So really all the BIOS 
portion has to detect and support are the conditions where the CPU goes 
through reset.  This should only be the suspend to ram and the suspend to 
disk states.

So how about a new simple LinuxBIOS PM interface?

Jordan

At 05:18 PM 11/26/2003 +0100, Stefan Reinauer wrote:
>* jarcher at pobox.com <jarcher at pobox.com> [031126 16:32]:
> > I'll raise the question to the next level....
> >
> > Has there been any discussion of putting any power management support into
> > the LinuxBIOS.  I've got a possible need for some basics, like suspend to
> > RAM.  Classic APM might be enough and simple to implement.  ACPI would 
> be a
> > good choice, but I'm not sure about how much ROM foot print would be 
> needed.
>
>Since ACPI is, similar to FCode, an interface based on abstracted binary
>code, it would probably be easier to add ACPI support to LinuxBIOS than
>supporting APM which needs code hooks.
>
>The ACPI tables could be a) generated by or b) stored in LinuxBIOS as is
>and will be found and interpreted by the Linux Kernel. But besides the
>technical issues there's also a legal question when including ACPI tables
>(some are patented by MS and not freely usable iirc, others might be
>copyrighted by Awkward & Co.)
>There are also kernel patches for Linux that allow attaching some of the
>ACPI tables to an initial ramdisk. This can be used to override broken
>bios ACPI tables with corrected ones without reflashing the bios.
>
>Stefan
>
>
>--
>      Stefan Reinauer, SUSE LINUX AG
>Teamleader Architecture Development
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From rminnich at lanl.gov  Wed Nov 26 11:12:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 26 11:12:00 2003
Subject: send me your message directly: Dokumentation for creating
 LinuxBIOS for DL smartModule P5-266 (fwd)
Message-ID: <Pine.LNX.4.44.0311260947580.19296-100000@maxroach.lanl.gov>


---------- Forwarded message ----------
Date: Wed, 26 Nov 2003 17:28:31 +0100
From: Benjamin Mertke <b.mertke at bfad.de>
To: ron minnich <rminnich at lanl.gov>
Subject: Re: send me your message directly: Dokumentation for creating
    LinuxBIOS for DL smartModule P5-266


----- Original Message -----
From: "ron minnich" <rminnich at lanl.gov>
To: <b.mertke at bfad.de>
Sent: Wednesday, November 26, 2003 5:00 PM
Subject: send me your message directly

OK, I will do it ;-) Thank you.
------------------------------

Hi everybody,

first of all I?m new to the list and I?m trying to get
LinuxBIOS into Digital Logic?s smartModule.

Second, is there any documentaition how to build BIOS for
Digital Logic?s smartModule P5-266?

I?ve started to read the HOWTO/EPIA and HOWTO/L440GX
and then to do according to the discriptions in this
two different ways. But well, ... you guess, I wouldn?t
write to the list if I would success.

EPIA-HowTo uses etherboot and L440GX-HowTo boots
without any ethernet connection just from the local
disk. That?s what I would preffer also.

As I saw there is a patch file in src/kernel_patches/ \
linux-2.4.17-smartcore-p5. So it seems to be the way of
L440GX-HowTo. Is this correct, that I have to use this way
to build the BIOS? How it was done by you?

I?ve also tried to compile etherboot-5.2.2 and I got in
src/bin-directory many of files compiled. As I know, on
smartModule there is Intel 82559ER Ethernet controller
and normaly we use the eepro100.o kernel module for
communication. So I think if I would use etherboot I
should use for "payload"-entry of the config-file
eepro100.ebi. But ... in the mean time there were changes
in etherboot and this compiled files are maned
eepro100.o, eepro100.img and eepro100.zimg. Which of them
should be used in config.etherboot file?

Are there any prerared romimages for smatrModules around?
I would like just to flash it into the EEPRM and to see
the behaviour.
Btw, I?m using the development kit of DL with two EEPROMs
on it. One for core BIOS and second for VGA-BIOS. It is also
possible to set the jumper either to boot from
smartModule or from development kit. In this case it is a
perfect tool to flash BIOSes (with phlash utility).

Thank you for reading and answering my email.

Benjamin




From niki.waibel at newlogic.com  Wed Nov 26 11:25:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Wed Nov 26 11:25:01 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <200311261528.hAQFSh84010039@enterprise2.newlogic.at>
Message-ID: <200311261701.hAQH1B84021888@enterprise2.newlogic.at>

>> and i cannot bring the interface up.
>> (i've not tried yet with pci=biosirq...)
> 
> tried with pci=biosirq kernel commandline -- same result...
> maybe it is the same result because my kernel supports
> DIRECT pci access only? i am going to try a pci ANY access
> kernel now...

unfort it is the same if the kernel (linux-2.6.0-test10-bk1) has
bios pci enabled and i use pci=biosirq ...

what is the reason for
===
PCI: No IRQ known for interrupt pin A of device 0000:02:04.0.
PCI: No IRQ known for interrupt pin A of device 0000:02:05.0.
===
if i use linuxbios?

niki


From stepan at suse.de  Wed Nov 26 11:32:01 2003
From: stepan at suse.de (Stefan Reinauer)
Date: Wed Nov 26 11:32:01 2003
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval (fwd)
In-Reply-To: <5.2.1.1.2.20031126083812.035bd988@mail.sizzard.com>
References: <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com> <Pine.LNX.4.44.0311260742500.13880-100000@maxroach.lanl.gov> <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com> <5.2.1.1.2.20031126083812.035bd988@mail.sizzard.com>
Message-ID: <20031126170642.GA19774@suse.de>

* jarcher at pobox.com <jarcher at pobox.com> [031126 17:43]:
> I mentioned APM because it seemed the simplest.  Realisticaly you'd want to 
> follow the LinuxBIOS approach and do minimal stuff at the BIOS level and 
> move most of the information to a linux driver.  So really all the BIOS 
> portion has to detect and support are the conditions where the CPU goes 
> through reset.  This should only be the suspend to ram and the suspend to 
> disk states.
> 
> So how about a new simple LinuxBIOS PM interface?
 
Some information, like power management code, is fitting pretty well in
the firmware imo. Before inventing yet another interface I strongly
recommend to look at the existing ones and sort them out if they do not
work for some or another reason. ACPI may be ugly, but there's a big
chance to support a whole lot of hardware at once by supporting ACPI
table generation in LinuxBIOS. Otoh, creating an own table/format that
can be parsed by a Linux driver will basically do the same thing in yet
another implementation. Result is many people sit and parse ACPI tables
to create LinuxBIOS tables (or even convert it automatically) 

The cleanest way would be to create FCode drivers for such components
and use them in an Open Firmware environment - an OS can then decide to
call methods provided by each hardware device in the device tree.

Suspend to disk can be done in software (see swsusp for linux) - I guess 
suspend to ram involves a lot more system management mode (SMM)
programming

Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From rminnich at lanl.gov  Wed Nov 26 12:32:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 26 12:32:01 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <200311261701.hAQH1B84021888@enterprise2.newlogic.at>
Message-ID: <Pine.LNX.4.44.0311261005240.19296-100000@maxroach.lanl.gov>

> 
> what is the reason for
> ===
> PCI: No IRQ known for interrupt pin A of device 0000:02:04.0.
> PCI: No IRQ known for interrupt pin A of device 0000:02:05.0.
> ===
> if i use linuxbios?

i have not done epia-m. this problem is due to bad irq_tables.c

run getpir under the standard bios and see what you get.

ron




From linuxbios at xdr.com  Wed Nov 26 16:29:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Wed Nov 26 16:29:01 2003
Subject: epia-m results of getpir
Message-ID: <200311262205.hAQM5U2x029973@xdr.com>

>run getpir under the standard bios and see what you get.

I just happen to have that right here:
/* This file was generated by getpir.c, do not modify! 
   (but if you do, please run checkpir on it to verify)
   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up

   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/

#include <arch/pirq_routing.h>

const struct irq_routing_table intel_irq_routing_table = {
	PIRQ_SIGNATURE, /* u32 signature */
	PIRQ_VERSION,   /* u16 version   */
	32+16*5,        /* there can be total 5 devices on the bus */
	0,           /* Where the interrupt router lies (bus) */
	0,           /* Where the interrupt router lies (dev) */
	0x1c20,         /* IRQs devoted exclusively to PCI usage */
	0,         /* Vendor */
	0,         /* Device */
	0,         /* Crap (miniport) */
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
	0x58,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
	{
		{0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
		{0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0},
		{0,0x50, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x3, 0},
		{0,0x68, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
		{0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0},
	}
};


From donald.zoch at amd.com  Wed Nov 26 17:29:00 2003
From: donald.zoch at amd.com (Donald Zoch)
Date: Wed Nov 26 17:29:00 2003
Subject: arima hdama linuxbios
Message-ID: <20031126140928.B17280@lard.amd.com>

I've been trying to get Linuxbios working on Arima HDAMA, but
am not getting any output to the screen.   I'm using the latest
CVS code, and have tried various methods of flashing the bios.

My SST49LF040 on the motherboard is 512k .  By default the linuxbios.rom
is 256k.  I've tried flashing that to the device and it won't boot.

I've also tried catting that together twice to get a 512k rom and
flashing that to the chip....doesn't boot...no output to the screen.

I've tried building a 512k linuxbios.rom and flashing that...doesn't
work either.

I've tried using the Linux mtd drivers to do the flashing. Doing a diff
of /dev/mtd0 and linuxbios.rom after the flash seems to indicate that
the flash was successful.  Rebooting the system fails though.

I've also tried the dos program uniflash program with the same results.

What might I be doing wrong?

Does anyone have a working linuxbios.rom that they could send me? Or
some details on how to get it to work?

Any help would be greatly appreciated.

Thanks,

Donald
----
Donald Zoch                         5900 E. Ben White Blvd. MS 625
Advanced Micro Devices              Austin, Tx  78741
MPD Unix Systems Administrator      Phone: (512) 602-7945
donald.zoch at amd.com                 Pager: (512) 604-5401



From rminnich at lanl.gov  Wed Nov 26 17:34:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 26 17:34:00 2003
Subject: epia-m results of getpir [PMX:#]
In-Reply-To: <200311262205.hAQM5U2x029973@xdr.com>
Message-ID: <Pine.LNX.4.44.0311261609270.21656-100000@maxroach.lanl.gov>

On Wed, 26 Nov 2003, Dave Ashley wrote:

> >run getpir under the standard bios and see what you get.
> 
> I just happen to have that right here:

how does it compare to what's in linuxbios? same? different?

ron



From rminnich at lanl.gov  Wed Nov 26 17:35:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 26 17:35:00 2003
Subject: arima hdama linuxbios
In-Reply-To: <20031126140928.B17280@lard.amd.com>
Message-ID: <Pine.LNX.4.44.0311261610470.21656-100000@maxroach.lanl.gov>

do you mean screen or serial output?

there's no vga yet.

ron



From ebiederman at lnxi.com  Wed Nov 26 20:08:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Nov 26 20:08:01 2003
Subject: config -> default
In-Reply-To: <p06010204bbd02126d38e@[10.0.1.2]>
References: <p06010204bbd02126d38e@[10.0.1.2]>
Message-ID: <m37k1m4m6p.fsf@maxwell.lnxi.com>

Greg Watson <gwatson at lanl.gov> writes:

> Stefan,
> 
> Which builds are broken? I thought I checked all configurations built after the
> change (apart from the VIA which Ron was working on.) and modified any that had
> problems.
> 
> My hope was that this change would make the use of options more logical and
> consistent. The intention is that parts set default values for any options that
> they require or are specific to the part. Then when all the parts are put
> together in a target configuration file, these default values can be overridden
> for the specific build. I was also toying with the idea of allowing some options
> 
> to be read-only, which I think would address your concern.
> 
> Apologies for breaking things. I try to build all targets after any change like
> this to make sure things are still working.

Sorry for the great delay in checking this out.  But it actually is worse
than that.

The following totally fails with the new setup.  When USE_FALLBACK_IMAGE
is an option.

##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
	default ROM_SECTION_SIZE   = FALLBACK_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
	default ROM_SECTION_OFFSET = 0
end

Also this chunk where I over ride the default strings is necessary,
or I don't have matching motherboard vendor and part strings and I can't
flash my BIOS.

##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="HDAMA"
default MAINBOARD_VENDOR="ARIMA"
 



Eric


From ebiederman at lnxi.com  Wed Nov 26 20:12:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Nov 26 20:12:01 2003
Subject: (fwd) peer busses
In-Reply-To: <20031110115439.GD18620@suse.de>
References: <20031110115439.GD18620@suse.de>
Message-ID: <m33cca4m0r.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> Is this the same issue we were having with Linux not being able to see
> bus 1?

The other side of it but the root cause is still peer PCI busses.

Eric


From ebiederman at lnxi.com  Wed Nov 26 20:20:00 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Nov 26 20:20:00 2003
Subject: Fwd: ACPI support in LinuxBIOS - moderator approval (fwd)
In-Reply-To: <5.2.1.1.2.20031126083812.035bd988@mail.sizzard.com>
References: <5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>
	<Pine.LNX.4.44.0311260742500.13880-100000@maxroach.lanl.gov>
	<5.2.1.1.2.20031126072910.02cbd460@mail.sizzard.com>
	<5.2.1.1.2.20031126083812.035bd988@mail.sizzard.com>
Message-ID: <m3znei370y.fsf@maxwell.lnxi.com>

jarcher at pobox.com writes:

> I mentioned APM because it seemed the simplest.  Realisticaly you'd want to
> follow the LinuxBIOS approach and do minimal stuff at the BIOS level and move
> most of the information to a linux driver.  So really all the BIOS portion has
> to detect and support are the conditions where the CPU goes through reset.  This
> should only be the suspend to ram and the suspend to disk states.
> 
> So how about a new simple LinuxBIOS PM interface?

There are several pieces to this.

1) Telling operating systems what part it needs to play.
2) Switching to the suspend to RAM state.
3) Knowing in the BIOS we need to come out of suspend to RAM
   instead of doing a fresh initialization of the memory controller.

Thinking about Suspend to RAM I have some strange thoughts about setting
up hypertransport correctly.  I am wondering if a suspend to RAM would
be faster than a hard_reset?  Anyway...

On the LinuxBIOS side the communication can pretty much be accomplished
with a CMOS parameter I think.

As far as giving information to the running OS giving it the tables it
expects is not the worst way to go.  Most of the power management needs
to happen in the OS and in the drivers.   Ideally we would package the
ACPI table entries in the LinuxBIOS table as real tabular data (not
functions) and then convert them to real ACPI later.

The OS needs a little bit of help to do suspend to RAM but we should
keep it as minimal as possible.

Eric



From rminnich at lanl.gov  Wed Nov 26 20:25:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Wed Nov 26 20:25:01 2003
Subject: config -> default
In-Reply-To: <m37k1m4m6p.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.44.0311261900180.21656-100000@maxroach.lanl.gov>

this fixup is at the top of next week's list now that sc '03 is over.

sc '03 is a major event that pretty much eats up nov. for us, so sorry for 
the inconvenience. 

ron




From ebiederman at lnxi.com  Wed Nov 26 20:46:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Wed Nov 26 20:46:01 2003
Subject: config -> default
In-Reply-To: <Pine.LNX.4.44.0311261900180.21656-100000@maxroach.lanl.gov>
References: <Pine.LNX.4.44.0311261900180.21656-100000@maxroach.lanl.gov>
Message-ID: <m3fzgay2bs.fsf@maxwell.lnxi.com>

ron minnich <rminnich at lanl.gov> writes:

> this fixup is at the top of next week's list now that sc '03 is over.
> 
> sc '03 is a major event that pretty much eats up nov. for us, so sorry for 
> the inconvenience. 

Not a major problem.  Annoying to update config.g and not have your
BIOS flash for a multitude of reasons but not a major problem.  Mostly
I need the old expr or the equivalent to guarantee formulas and if
statements always use the final value of a variable.

The good news is that the default/option thing reverted I now am building
with the new build system and unless anyone else was using the old system
we can kill all of the Config files.

My focus right now is to get one last update for Lightning that is effectively
the current tree.  With better error handing for smbus failures and an optimized
number of resets so we have less exposure to smbus bugs.

While I am doing that I am finding that I am getting a lot of code review done
on things that I had to do quickly to get Lightning out the door and didn't quite
implement right.  

Once it looks like everything is in a reliable state for lightning
hopefully I can focus on what is needed to finish off the freebios2
core so we can freeze it at some point and start getting releases so
we can tell people where to look to build things.  I want to get the
pirq and mptables autogenerated.  And I think I want to do some
generalizations with respect to capabilities, so they can have methods
etc.  (Solving the problem of how to handle buggy HT devices).

Anyway I am rambling and I need to get home.  Talk to you after the Holidays.

Eric


From aip at cwlinux.com  Thu Nov 27 00:54:01 2003
From: aip at cwlinux.com (Andrew Ip)
Date: Thu Nov 27 00:54:01 2003
Subject: epia-m results of getpir [PMX:#]
In-Reply-To: <Pine.LNX.4.44.0311261609270.21656-100000@maxroach.lanl.gov>; from ron minnich on Wed, Nov 26, 2003 at 04:10:01PM -0700
References: <200311262205.hAQM5U2x029973@xdr.com> <Pine.LNX.4.44.0311261609270.21656-100000@maxroach.lanl.gov>
Message-ID: <20031127143005.A23275@mail.cwlinux.com>

Hi,

AFAIK, pirq table on EPIA doesn't work.  We fixed the irqs by writing irq#
to devices.

-Andrew

On Wed, Nov 26, 2003 at 04:10:01PM -0700, ron minnich wrote:
> On Wed, 26 Nov 2003, Dave Ashley wrote:
> 
> > >run getpir under the standard bios and see what you get.
> > 
> > I just happen to have that right here:
> 
> how does it compare to what's in linuxbios? same? different?
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 
Andrew Ip
Email:  aip at cwlinux.com
Tel:    (852) 2542 2046
Fax:    (852) 2542 2036
Mobile: (852) 9201 9866

Cwlinux Limited
Unit 202B 2/F Lai Cheong Factory Building,
479-479A Castle Peak Road,
Lai Chi Kok, Kowloon,
Hong Kong.

For public pgp key, please obtain it from http://www.keyserver.net/en.


From ijpriya at hotmail.com  Thu Nov 27 01:11:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Thu Nov 27 01:11:01 2003
Subject: Linuxbios with Diskonchip?
Message-ID: <BAY2-F15662iwZZiYYH000145c5@hotmail.com>

Hi,

I shall have my BIOS program, Linux kernel and filesystem in the same 
Diskonchip. I want to use linuxbios (for sc1200).  What is the physical 
memory mapping that should be done? SDRAM mapped to lower order address and 
Diskonchip to the higher order address. Is it correct?

_________________________________________________________________
Enjoy shopping online? Get this e credit card. 
http://server1.msn.co.in/features/amex/ It cuts cost & adds value!



From deyasis at yahoo.co.in  Thu Nov 27 01:38:00 2003
From: deyasis at yahoo.co.in (=?iso-8859-1?q?Deya?=)
Date: Thu Nov 27 01:38:00 2003
Subject: sc1200 with linuxbios possiblility?
Message-ID: <20031127071401.9250.qmail@web8201.mail.in.yahoo.com>

Hi,
 
         I am a newbie to this list. I like to use linuxbios for my project. I have sc1200 chip. I would have the BIOS program, linux kernel and file system in the same Flash memory (32 Mbit). Is it possible to use linuxbios to boot the linux OS from Flash to sdram though BIOS program, linux kernel and file system all existe in the same flash memory? I dont have a seperate Bios chip.
 
Any suggestions on this would help me to proceed further.


Yahoo! India Mobile: Ringtones, Wallpapers, Picture Messages and more.Download now.
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From deyasis at yahoo.co.in  Thu Nov 27 01:39:00 2003
From: deyasis at yahoo.co.in (=?iso-8859-1?q?Deya?=)
Date: Thu Nov 27 01:39:00 2003
Subject: sc1200 with linuxbios possiblility?
Message-ID: <20031127071512.47354.qmail@web8203.mail.in.yahoo.com>

Hi,
?
???????? I am a newbie to this list. I like to use
linuxbios for my project. I have sc1200 chip. I?would
have the BIOS program, linux kernel and file system
in?the same Flash memory (32 Mbit). Is it possible to
use linuxbios to boot the linux OS from Flash to sdram
though BIOS program, linux kernel and file system all
existe in the same flash memory? I dont have a
seperate Bios chip.
?
Any suggestions on this would help me to proceed
further.




________________________________________________________________________
Yahoo! India Mobile: Download the latest polyphonic ringtones.
Go to http://in.mobile.yahoo.com


From mirenna at mi.ingv.it  Thu Nov 27 05:22:01 2003
From: mirenna at mi.ingv.it (Santi Mirenna)
Date: Thu Nov 27 05:22:01 2003
Subject: Help on epia-m 10000 linuxbios VGA 
Message-ID: <5.1.1.6.2.20031127114414.021a2a68@10.1.1.8>

Hi to all, today i make EPIA-M 10000 rom image. i compile to have VGA and 
Filo,
after apply patch of Dave Ashley and info from Takeshi about RAM ammount
VGA now is found by the system but ....
In attach you have the output log ....
Can someone tell me where i wrong?

Dave Ashley reply:

You haven't applied all the patch, specifically the handler
for the unsupported bios interrupts.
This is the bug where it just gets into an endless loop
of bios interrupts, so the program needs to exit the
bios somehow. -Dave

Hi , can some one tell me where to look  ....
i made the patch ....where to look Dave to know if the patch is ok ?

Thanks.

Santi Mirenna
-------------- next part --------------
LinuxBIOS-1.0.0 Thu Nov 27 12:28:35 CET 2003 starting...
RB?0

LinuxBIOS-1.0.0 Thu Nov 27 12:28:35 CET 2003 starting...
80 08 07 0d 0a 01 40 00 04 60 70 00 82 08 00 01
0e 04 0c 01 02 20 00 75 70 00 00 48 30 48 2a 40
75 75 45 45 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0a
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
LinuxBIOS-1.0.0 Thu Nov 27 12:28:35 CET 2003 booting...
Finding PCI configuration type.
PCI: Using configuration type 1
Scanning PCI bus...PCI: pci_scan_bus for bus 0
PCI: 00:00.0 [1106/3123]
PCI: 00:01.0 [1106/b091]
PCI: 00:0d.0 [1106/3044]
PCI: 00:10.0 [1106/3038]
PCI: 00:10.1 [1106/3038]
PCI: 00:10.2 [1106/3038]
PCI: 00:10.3 [1106/3104]
PCI: 00:11.0 [1106/3177]
PCI: 00:11.1 [1106/0571]
PCI: 00:11.5 [1106/3059]
PCI: 00:12.0 [1106/3065]
PCI: pci_scan_bus for bus 1
PCI: 01:00.0 [1106/3122]
PCI: pci_scan_bus returning with max=01
PCI: pci_scan_bus returning with max=01
done
Allocating PCI resources...
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
ASSIGN RESOURCES, bus 0
PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io
PCI: 00:01.0 24 <- [0xf8000000 - 0xfbffffff] bus 1 prefmem
PCI: 00:01.0 20 <- [0xfc000000 - 0xfcffffff] bus 1 mem
ASSIGN RESOURCES, bus 1
PCI: 01:00.0 10 <- [0xf8000000 - 0xfbffffff] prefmem
PCI: 01:00.0 14 <- [0xfc000000 - 0xfcffffff] mem
ASSIGNED RESOURCES, bus 1
PCI: 00:0d.0 10 <- [0xfd000000 - 0xfd0007ff] mem
PCI: 00:0d.0 14 <- [0x00001800 - 0x0000187f] io
PCI: 00:10.0 20 <- [0x00001880 - 0x0000189f] io
PCI: 00:10.1 20 <- [0x000018a0 - 0x000018bf] io
PCI: 00:10.2 20 <- [0x000018c0 - 0x000018df] io
PCI: 00:10.3 10 <- [0xfd001000 - 0xfd0010ff] mem
PCI: 00:11.1 20 <- [0x000018e0 - 0x000018ef] io
PCI: 00:11.5 10 <- [0x00001000 - 0x000010ff] io
PCI: 00:12.0 10 <- [0x00001400 - 0x000014ff] io
PCI: 00:12.0 14 <- [0xfd002000 - 0xfd0020ff] mem
ASSIGNED RESOURCES, bus 0
Allocating VGA resource
done.
Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 cmd <- 07
PCI: 00:0d.0 cmd <- 07
PCI: 00:10.0 cmd <- 07
PCI: 00:10.1 cmd <- 07
PCI: 00:10.2 cmd <- 07
PCI: 00:10.3 cmd <- 07
PCI: 00:11.0 cmd <- 07
PCI: 00:11.1 cmd <- 07
PCI: 00:11.5 cmd <- 01
PCI: 00:12.0 cmd <- 07
PCI: 01:00.0 cmd <- 03
done.
Initializing PCI devices...
PCI devices initialized
totalram: 224M
Initializing CPU #0
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  128MB, type WB
Setting variable MTRR 1, base:  128MB, range:   64MB, type WB
Setting variable MTRR 2, base:  192MB, range:   32MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
call intel_enable_fixed_mtrr()
call intel_enable_var_mtrr()
Leave setup_mtrrs
done.

Max cpuid index    : 1
Vendor ID          : CentaurHauls
Processor Type     : 0x00
Processor Family   : 0x06
Processor Model    : 0x09
Processor Mask     : 0x00
Processor Stepping : 0x01
Feature flags      : 0x0380b135


MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Disabling local apic...done.
CPU #0 Initialized
Mainboard fixup
Final mainboard fixup
Southbridge fixup
setting firewire
Assigning IRQ 10 to 0:d.0
  Readback = 10
setting usb
Assigning IRQ 11 to 0:10.0
  Readback = 11
Assigning IRQ 10 to 0:10.1
  Readback = 10
Assigning IRQ 12 to 0:10.2
  Readback = 12
Assigning IRQ 5 to 0:10.3
  Readback = 5
setting vt8235
Assigning IRQ 5 to 0:11.1
  Readback = 255
Assigning IRQ 12 to 0:11.5
  Readback = 12
setting ethernet
Assigning IRQ 11 to 0:12.0
  Readback = 11
setting vga
Assigning IRQ 11 to 1:0.0
  Readback = 11
setting pci slot
4d0: 0x20
4d1: 0x1c
4d0: 0x20
4d1: 0x1c
INSTALL REAL-MODE IDT
DO THE VGA BIOS
found VGA: vid=1106, did=3122
write_protect_vgabios
0x55 0xaa 0x7f 0xe9 0x12 0x5c 0xb1 0x1d 0xa6 0xfc 0xde 0x60 0x0 0x0 0x0 0x0 biosint: # 0x1a, eax 0xb108 ebx 0x0 ecx 0xffff0000 edx 0x3d5
biosint: ebp 0x11804 esp 0xfcc edi 0xf6 esi 0xf58d8
biosint: ip 0x40a3 cs 0x58d8 flags 0x46
0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x3
biosint: # 0x15, eax 0x5f19 ebx 0x834 ecx 0xff20 edx 0x3d4
biosint: ebp 0x11804 esp 0xfca edi 0x44 esi 0xfb167
biosint: ip 0x4ef9 cs 0x44 flags 0x86
biosint: # 0x15, eax 0x5f19 ebx 0x404 ecx 0x0 edx 0x3d4
biosint: ebp 0x11804 esp 0xfb2 edi 0x44 esi 0xfb167
biosint: ip 0x51df cs 0x909 flags 0x2
biosint: # 0x15, eax 0x5f19 ebx 0xf004 ecx 0x0 edx 0x3c4
biosint: ebp 0x11804 esp 0xfca edi 0xb1a9 esi 0xfbcc5
biosint: ip 0x4fcb cs 0x44 flags 0x6
biosint: # 0x15, eax 0x5f19 ebx 0xf004 ecx 0x0 edx 0x3d4
biosint: ebp 0x11804 esp 0xfca edi 0xb1a9 esi 0xfbcc5
biosint: ip 0x5020 cs 0x44 flags 0x2
biosint: # 0x15, eax 0x5f0f ebx 0xb734 ecx 0xff20 edx 0x3d5
biosint: ebp 0x11804 esp 0xff0 edi 0x44 esi 0xf5c81
biosint: ip 0x5c98 cs 0x0 flags 0x2
biosint: # 0x15, eax 0x5f02 ebx 0x0 ecx 0x0 edx 0xd4
biosint: ebp 0x11804 esp 0xfde edi 0x44 esi 0xf5c81
biosint: ip 0x4008 cs 0x5c81 flags 0x46
biosint: # 0x15, eax 0x5f02 ebx 0x300 ecx 0x5 edx 0xd4
biosint: ebp 0x11804 esp 0xfcc edi 0x44 esi 0xf5c81
biosint: ip 0x4045 cs 0x5c81 flags 0x46
biosint: # 0x15, eax 0x5f19 ebx 0x1900 ecx 0x1 edx 0xd4
biosint: ebp 0x11804 esp 0xfde edi 0x44 esi 0xf5c81
biosint: ip 0x515d cs 0x5c81 flags 0x2
biosint: # 0x15, eax 0x5f19 ebx 0x1904 ecx 0x1 edx 0xd4
biosint: ebp 0x11804 esp 0xfda edi 0x44 esi 0xf5c81
biosint: ip 0x51df cs 0x909 flags 0x46
biosint: # 0x15, eax 0x5f02 ebx 0x0 ecx 0x0 edx 0xd4
biosint: ebp 0x11804 esp 0xff0 edi 0x44 esi 0xf5c81
biosint: ip 0x5ce8 cs 0x0 flags 0x46


biosint: # 0xf8, eax 0xc01b ebx 0x1000 ecx 0x100 edx 0x3ce
biosint: ebp 0x10fca esp 0xfc0 edi 0x9c8a esi 0xf77e0
biosint: ip 0x2bf cs 0x7 flags 0x246

biosint: Unsupport int #0xf8   <----- 


biosint: # 0xc8, eax 0xc01b ebx 0x1000 ecx 0x100 edx 0x3ce
biosint: ebp 0x10fca esp 0xfc0 edi 0x9c8a esi 0xf77e0
biosint: ip 0x2bf cs 0x7 flags 0x246
biosint: Unsupport int #0xc8
biosint: # 0xcd, eax 0xc01b ebx 0x1000 ecx 0x100 edx 0x3ce
biosint: ebp 0x10fca esp 0xfc0 edi 0x9c8a esi 0xf77e0
biosint: ip 0x2bf cs 0x7 flags 0x246
biosint: Unsupport int #0xcd

From niki.waibel at newlogic.com  Thu Nov 27 06:51:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Thu Nov 27 06:51:01 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <Pine.LNX.4.44.0311261005240.19296-100000@maxroach.lanl.gov>
Message-ID: <200311271227.hARCRl84008740@enterprise2.newlogic.at>

On 26-Nov-2003 ron minnich wrote:
>> 
>> what is the reason for
>> ===
>> PCI: No IRQ known for interrupt pin A of device 0000:02:04.0.
>> PCI: No IRQ known for interrupt pin A of device 0000:02:05.0.
>> ===
>> if i use linuxbios?
> 
> i have not done epia-m. this problem is due to bad irq_tables.c
> 
> run getpir under the standard bios and see what you get.

i get:
===
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
        PIRQ_SIGNATURE, /* u32 signature */
        PIRQ_VERSION,   /* u16 version   */
        32+16*5,        /* there can be total 5 devices on the bus */
        0,           /* Where the interrupt router lies (bus) */
        0,           /* Where the interrupt router lies (dev) */
        0x1c00,         /* IRQs devoted exclusively to PCI usage */
        0,         /* Vendor */
        0,         /* Device */
        0,         /* Crap (miniport) */
        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
        0x78,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this
structure (including checksum) */
        {
                {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
                {0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0},
                {0,0x50, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x3, 0},
                {0,0x68, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
                {0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0},
        }
};
===
which is quite different from src/mainboard/via/epia-m/irq_tables.c:
===
                /* ethernet */
                {0,0x90, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
                /* usb */
                {0,0x80, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
                /* pci */
                {0,0xa0, {{0x1, 0xdeb8}, {0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}}, 0x3, 0},
                /* audio */
                {0,0x8d, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x0, 0},
                /* 1394 */
                {0,0x68, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}
===
but almost the same as (also from src/mainboard/via/epia-m/irq_tables.c)
===
#if 0
        {
                {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
                {0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0},
                {0,0x50, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x3, 0},
                {0,0x68, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
                {0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0},
                {0x50,0, {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}
        }
#else
===

hmmm...
who did the src/mainboard/via/epia-m/irq_tables.c code?

does this mean that if i unplug the dual nic, that i cannot use the
same linuxbios anymore?

niki


From niki.waibel at newlogic.com  Thu Nov 27 07:46:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Thu Nov 27 07:46:01 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <200311271227.hARCRl84008740@enterprise2.newlogic.at>
Message-ID: <200311271322.hARDMo84015599@enterprise2.newlogic.at>

i have the same problem
===
PCI: No IRQ known for interrupt pin A of device 0000:02:04.0. Please try using pci=biosirq.
PCI: No IRQ known for interrupt pin A of device 0000:02:05.0. Please try using pci=biosirq.
===
with the linuxbios + the new generated irq_tables.c.

no matter if i use pci=biosirq or not (does this kernel option
affect the functionality of a linuxbios system at all?).

i get this from linuxbios:
===
LinuxBIOS-1.0.0 Thu Nov 27 13:30:41 CET 2003 starting...
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
LinuxBIOS-1.0.0 Thu Nov 27 13:30:41 CET 2003 booting...
Finding PCI configuration type.
PCI: Using configuration type 1
Scanning PCI bus...PCI: pci_scan_bus for bus 0
PCI: 00:00.0 [1106/3123]
PCI: 00:01.0 [1106/b091]
PCI: 00:0d.0 [1106/3044]
PCI: 00:10.0 [1106/3038]
PCI: 00:10.1 [1106/3038]
PCI: 00:10.2 [1106/3038]
PCI: 00:10.3 [1106/3104]
PCI: 00:11.0 [1106/3177]
PCI: 00:11.1 [1106/0571]
PCI: 00:11.5 [1106/3059]
PCI: 00:12.0 [1106/3065]
PCI: 00:14.0 [8086/b154]
PCI: pci_scan_bus for bus 1
PCI: pci_scan_bus returning with max=01
PCI: pci_scan_bus for bus 2
PCI: 02:04.0 [8086/1229]
PCI: 02:05.0 [8086/1229]
PCI: pci_scan_bus returning with max=02
PCI: pci_scan_bus returning with max=02
done
Allocating PCI resources...
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:00.0 register 10(00000008), read-only ignoring it
ASSIGN RESOURCES, bus 0
PCI: 00:01.0 1c <- [0x00002000 - 0x00001fff] bus 1 io
PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmem
PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem
PCI: 00:0d.0 10 <- [0xfeb00000 - 0xfeb007ff] mem
PCI: 00:0d.0 14 <- [0x00002800 - 0x0000287f] io
PCI: 00:10.0 20 <- [0x00002880 - 0x0000289f] io
PCI: 00:10.1 20 <- [0x000028a0 - 0x000028bf] io
PCI: 00:10.2 20 <- [0x000028c0 - 0x000028df] io
PCI: 00:10.3 10 <- [0xfeb01000 - 0xfeb010ff] mem
PCI: 00:11.1 20 <- [0x000028e0 - 0x000028ef] io
PCI: 00:11.5 10 <- [0x00002000 - 0x000020ff] io
PCI: 00:12.0 10 <- [0x00002400 - 0x000024ff] io
PCI: 00:12.0 14 <- [0xfeb02000 - 0xfeb020ff] mem
PCI: 00:14.0 1c <- [0x00001000 - 0x00001fff] bus 2 io
PCI: 00:14.0 24 <- [0xfeb00000 - 0xfeafffff] bus 2 prefmem
PCI: 00:14.0 20 <- [0xfea00000 - 0xfeafffff] bus 2 mem
ASSIGN RESOURCES, bus 2
PCI: 02:04.0 10 <- [0xfea40000 - 0xfea40fff] mem
PCI: 02:04.0 14 <- [0x00001000 - 0x0000103f] io
PCI: 02:04.0 18 <- [0xfea00000 - 0xfea1ffff] mem
PCI: 02:05.0 10 <- [0xfea41000 - 0xfea41fff] mem
PCI: 02:05.0 14 <- [0x00001040 - 0x0000107f] io
PCI: 02:05.0 18 <- [0xfea20000 - 0xfea3ffff] mem
ASSIGNED RESOURCES, bus 2
ASSIGNED RESOURCES, bus 0
done.
Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 cmd <- 07
PCI: 00:0d.0 cmd <- 83
PCI: 00:10.0 cmd <- 01
PCI: 00:10.1 cmd <- 01
PCI: 00:10.2 cmd <- 01
PCI: 00:10.3 cmd <- 02
PCI: 00:11.0 cmd <- 87
PCI: 00:11.1 cmd <- 07
PCI: 00:11.5 cmd <- 01
PCI: 00:12.0 cmd <- 83
PCI: 00:14.0 cmd <- 07
PCI: 02:04.0 cmd <- 03
PCI: 02:05.0 cmd <- 03
done.
Initializing PCI devices...
PCI devices initialized
totalram: 127M
Initializing CPU #0
===
[...]
===
Southbridge fixup
setting firewire
Assigning IRQ 10 to 0:d.0
  Readback = 10
setting usb
Assigning IRQ 11 to 0:10.0
  Readback = 11
Assigning IRQ 10 to 0:10.1
  Readback = 10
Assigning IRQ 12 to 0:10.2
  Readback = 12
Assigning IRQ 5 to 0:10.3
  Readback = 5
setting ethernet
Assigning IRQ 11 to 0:12.0
  Readback = 11
setting pci slot
setting vt8235 slot
Assigning IRQ 5 to 0:11.1
  Readback = 5
Assigning IRQ 12 to 0:11.5
  Readback = 12
Checking IRQ routing tables...
/home/niki/packages/freebios-20031024/src/arch/i386/lib/pirq_routing.c:    30:check_pirq_routing_table() - irq_routing_table lo
cated
 at: 0x00008a20
done.
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...failed
Wrote linuxbios table at: 00000500 - 00000640  checksum ed05
===

the system (booted with linuxbios+modified irq_tables.c) sayes:
===
PCI: Using configuration type 1
mtrr: v2.0 (20020519)
ACPI: Subsystem revision 20031002
ACPI: System description tables not found
    ACPI-0084: *** Error: acpi_load_tables: Could not get RSDP, AE_NOT_FOUND
    ACPI-0134: *** Error: acpi_load_tables: Could not load tables: AE_NOT_FOUND
ACPI: Unable to load the System Description Tables
ACPI: ACPI tables contain no PCI IRQ routing entries
PCI: Invalid ACPI-PCI IRQ routing table
PCI: Probing PCI hardware
PCI: Probing PCI hardware (bus 00)
[...cut...]
PCI: No IRQ known for interrupt pin A of device 0000:02:04.0. Please try using pci=biosirq.
PCI: No IRQ known for interrupt pin A of device 0000:02:05.0. Please try using pci=biosirq.
===

===
# cat /proc/interrupts 
           CPU0       
  0:     116849          XT-PIC  timer
  1:          8          XT-PIC  i8042
  2:          0          XT-PIC  cascade
  3:          0          XT-PIC  serial
  4:        257          XT-PIC  serial
  8:          1          XT-PIC  rtc
 11:          0          XT-PIC  eth2
 12:          0          XT-PIC  VIA8233
 14:         21          XT-PIC  ide0
 15:       1051          XT-PIC  ide1
NMI:          0 
ERR:          0
===

it seems that 02:04.0 and 02:05.0 are detected...
so what goes wrong?
there is no ``Assigning IRQ XX to ...'' for 02:04.0 and 02:05.0 in linuxbios...

it is strange to me that all this worked with a regular (singleport) intel
ethernet card!



when using the award bios the kernel sayes (regarding pci):
===
PCI: Using configuration type 1
mtrr: v2.0 (20020519)
ACPI: Subsystem revision 20031002
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Root Bridge [PCI0] (00:00)
PCI: Probing PCI hardware (bus 00)
ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 7 10 *11 12 14 15)
ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 10 11 *12 14 15)
ACPI: PCI Interrupt Link [LNKC] (IRQs 1 3 4 5 6 7 *10 11 12 14 15)
ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 7 10 11 12 14 15)
Linux Plug and Play Support v0.97 (c) Adam Belay
ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 12
ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 11
ACPI: PCI Interrupt Link [LNKC] enabled at IRQ 10
ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 5
PCI: Using ACPI for IRQ routing
PCI: if you experience problems, try using option 'pci=noacpi' or even 'acpi=off'
[...later...]
PCI: Via IRQ fixup for 0000:00:10.0, from 0 to 11
PCI: Via IRQ fixup for 0000:00:10.1, from 255 to 12
PCI: Via IRQ fixup for 0000:00:10.2, from 255 to 10
ACPI: Power Button (FF) [PWRF]
ACPI: Processor [CPU0] (supports C1 C2, 2 throttling states)
isapnp: Scanning for PnP cards...
isapnp: No Plug & Play device found
===

and
===
# cat /proc/interrupts 
           CPU0       
  0:     159023          XT-PIC  timer
  1:          8          XT-PIC  i8042
  2:          0          XT-PIC  cascade
  3:          0          XT-PIC  serial
  4:        270          XT-PIC  serial
  8:          1          XT-PIC  rtc
  9:          0          XT-PIC  acpi
 10:          6          XT-PIC  VIA8233, eth1
 11:          0          XT-PIC  eth2
 12:          6          XT-PIC  eth0
 14:         21          XT-PIC  ide0
 15:       1049          XT-PIC  ide1
NMI:          0 
ERR:          0
===

niki


From niki.waibel at newlogic.com  Thu Nov 27 10:38:00 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Thu Nov 27 10:38:00 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <200311271322.hARDMo84015599@enterprise2.newlogic.at>
Message-ID: <200311271614.hARGER84007125@enterprise2.newlogic.at>

i think i found the main problem:

award bios / dual ethernet nic:
===
# /sbin/lspci 
00:00.0 Host bridge: VIA Technologies, Inc.: Unknown device 3123
00:01.0 PCI bridge: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP]
00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80)
00:10.0 USB Controller: VIA Technologies, Inc. USB (rev 80)
00:10.1 USB Controller: VIA Technologies, Inc. USB (rev 80)
00:10.2 USB Controller: VIA Technologies, Inc. USB (rev 80)
00:10.3 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 82)
00:11.0 ISA bridge: VIA Technologies, Inc. VT8235 ISA Bridge
00:11.1 IDE interface: VIA Technologies, Inc. VT82C586/B/686A/B PIPC Bus Master IDE (rev 06)
00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233 AC97 Audio Controller (rev 50)
00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 74)
00:14.0 PCI bridge: Intel Corp. 21154 PCI-to-PCI Bridge
01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3122 (rev 03)
02:04.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 0d)
02:05.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 0d)
===

award bios / std ethernet nic:
===
# lspci
00:00.0 Host bridge: VIA Technologies, Inc.: Unknown device 3123
00:01.0 PCI bridge: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP]
00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80)
00:10.0 USB Controller: VIA Technologies, Inc. USB (rev 80)
00:10.1 USB Controller: VIA Technologies, Inc. USB (rev 80)
00:10.2 USB Controller: VIA Technologies, Inc. USB (rev 80)
00:10.3 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 82)
00:11.0 ISA bridge: VIA Technologies, Inc. VT8235 ISA Bridge
00:11.1 IDE interface: VIA Technologies, Inc. VT82C586/B/686A/B PIPC Bus Master IDE (rev 06)
00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233 AC97 Audio Controller (rev 50)
00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 74)
00:14.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 0c)
01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3122 (rev 03)
===

the dual eth controller seems to use bus #2 ??!!
the normal eth controller bus #0.

is that some sort of virtual bus?
the epia-m has only one pci bus... has it?

niki


From niki.waibel at newlogic.com  Thu Nov 27 11:31:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Thu Nov 27 11:31:01 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <200311271614.hARGER84007125@enterprise2.newlogic.at>
Message-ID: <200311271707.hARH7084014113@enterprise2.newlogic.at>

this is maybe interesting as well:
===
# cat /proc/iomem 
00000000-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000c7fff : Video ROM
000f0000-000fffff : System ROM
00100000-1dfeffff : System RAM
  00100000-00315318 : Kernel code
  00315319-0043debf : Kernel data
1dff0000-1dff2fff : ACPI Non-volatile Storage
1dff3000-1dffffff : ACPI Tables
d0000000-d7ffffff : 0000:00:00.0
d8000000-dbffffff : PCI Bus #01
  d8000000-dbffffff : 0000:01:00.0
dc000000-ddffffff : PCI Bus #01
  dc000000-dcffffff : 0000:01:00.0
de000000-de0fffff : PCI Bus #02
  de000000-de01ffff : 0000:02:04.0
    de000000-de01ffff : e100
  de020000-de03ffff : 0000:02:05.0
    de020000-de03ffff : e100
  de040000-de040fff : 0000:02:05.0
    de040000-de040fff : e100
  de041000-de041fff : 0000:02:04.0
    de041000-de041fff : e100
de100000-de1000ff : 0000:00:10.3
de101000-de1010ff : 0000:00:12.0
  de101000-de1010ff : via-rhine
de102000-de1027ff : 0000:00:0d.0
ffff0000-ffffffff : reserved
===
(award bios + dial nic)

maybe the dual nic has some extention rom code on it which is
executed from the award bios...
it should not be too difficult to jump to that code from linuxbios. is it?

niki



From jan at kneschke.de  Thu Nov 27 12:05:01 2003
From: jan at kneschke.de (Jan Kneschke)
Date: Thu Nov 27 12:05:01 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <200311271614.hARGER84007125@enterprise2.newlogic.at>
References: <200311271322.hARDMo84015599@enterprise2.newlogic.at> <200311271614.hARGER84007125@enterprise2.newlogic.at>
Message-ID: <20031127174118.GY27814@weigon.dyndns.org>

On Thu, Nov 27, 2003 at 05:14:27PM +0100, Niki Waibel wrote:
> i think i found the main problem:
> 
> award bios / dual ethernet nic:
> ===
> # /sbin/lspci 

> 00:14.0 PCI bridge: Intel Corp. 21154 PCI-to-PCI Bridge

> 02:04.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 0d)
> 02:05.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 0d)
> ===

> the dual eth controller seems to use bus #2 ??!!
> the normal eth controller bus #0.
> 
> is that some sort of virtual bus?
> the epia-m has only one pci bus... has it?

you see the pci-to-pci bridge ?

in general multi-port network-card have a pci-to-pci bridge and an interal
pci-bus for the different interfaces.

> niki

  Jan

-- 
http://jan.kneschke.de - localizer, modlogan, pxtools
mailto:jan at kneschke.de - Jan Kneschke


From thomas at wehrspann.de  Thu Nov 27 15:24:01 2003
From: thomas at wehrspann.de (thomas at wehrspann.de)
Date: Thu Nov 27 15:24:01 2003
Subject: automatic power on possible?
Message-ID: <200311272142.21841.thomas@wehrspann.de>

Most modern motherboards supports the timer based automatic power on
via BIOS settings. With linuxbios this is not(?) possible. There is a program
for linux, called nvram-wakeup, to set the wakeup time in nvram or rtc. But
especially for the K7SEM or EPIA boards a reboot is needed after it, so the
wakeup settings can take effect.
Does anyone know what the BIOS is doing what linuxbios does not?
Perhaps it can be done in a program?

Thanks


Thomas Wehrspann


From gizara at cox.net  Thu Nov 27 16:16:00 2003
From: gizara at cox.net (gizara)
Date: Thu Nov 27 16:16:00 2003
Subject: Linuxbios with Diskonchip?
References: <BAY2-F15662iwZZiYYH000145c5@hotmail.com>
Message-ID: <003e01c3b530$ff3d7020$6f566044@oc.cox.net>

If I remember correctly, Disk-on-Chip comprises NAND flash technology which
inherently cannot execute in place, strictly sequential (data) accesses...
So you would still need some sort of rudimentary boot flash(NOR) or other
ROM to execute code to first load the BIOS, then the kernal, into shadow,
then main (DRAM) memory locations, respectively.

In a system I'm architecting we're still going to use a 256Kx8 flash for
LinuxBIOS, from there use JFFS2 and associated utilities to get the kernal
and various applications and data from a bare NAND on board.

This link and its links go into much more detail than I can in this email
about issues you may face:

http://www.linux-mtd.infradead.org/tech/nand.html

Good Luck!


----- Original Message -----
From: "Devi Priya" <ijpriya at hotmail.com>
To: <linuxbios at clustermatic.org>
Sent: Wednesday, November 26, 2003 10:47 PM
Subject: Linuxbios with Diskonchip?


> Hi,
>
> I shall have my BIOS program, Linux kernel and filesystem in the same
> Diskonchip. I want to use linuxbios (for sc1200).  What is the physical
> memory mapping that should be done? SDRAM mapped to lower order address
and
> Diskonchip to the higher order address. Is it correct?
>
> _________________________________________________________________
> Enjoy shopping online? Get this e credit card.
> http://server1.msn.co.in/features/amex/ It cuts cost & adds value!
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From ebiederman at lnxi.com  Thu Nov 27 17:20:01 2003
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Nov 27 17:20:01 2003
Subject: Tyan S4880
In-Reply-To: <20031125095338.GA5805@suse.de>
References: <3174569B9743D511922F00A0C9431423039905AE@TYANWEB>
	<20031125095338.GA5805@suse.de>
Message-ID: <m3y8u1v2lx.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at suse.de> writes:

> * YhLu <YhLu at tyan.com> [031125 03:37]:
> > Stefan,
> > 
> > I'm porting Tyan S4880 now. I found that the following building err, do you
> > meet it in AMD board?
> 
> No, the AMD boards build fine for me. 
> gcc-3.3.1-29
> binutils-2.14.90.0.6-8
> 
> > Even I only enable the CPU0's memctrl in the auto.c
> 
> It seems the struct itself in auto.c is pretty uncritical for size.
> Other parts like the log level need a lot more tuning if you want the
> image to be as verbose as possible. 

I think that is more because changing the loglevel is something
we have real control over.  I think most of the bloat is in
auto.c but I have not gone back and looked for a while.

Before the memory controller setup was called in a loop it
made a real difference if you setup 1 memory controller or
2 because both calls were inlined.  With the loop the memory
controller code is only inlined once no matter how many memory
controllers you have.
 
> * Do you compile with romcc -O (not -O0 and not -O2)

Hmm.  -O2 should work and better than -O.  I know it was
broken for a while...

> guess the size issue should be mentioned in the docs. Everybody
> fiddling with LinuxBIOS on AMD64 _has_ seen it..

Yes.  And this is why I keep working on making inlining optional
in romcc.

Eric


From ijpriya at hotmail.com  Thu Nov 27 20:21:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Thu Nov 27 20:21:01 2003
Subject: Linuxbios with Diskonchip?
Message-ID: <BAY2-F1359LT6yeLnHT00016fd6@hotmail.com>

Hi,

      I am using Diskonchip millennium with boot capability. I just want to 
know if diskonchip is mapped to the high order physical address (at reset) 
and is any remapping is done later?


>From: "gizara" <gizara at cox.net>
>To: "Devi Priya" <ijpriya at hotmail.com>, <linuxbios at clustermatic.org>
>Subject: Re: Linuxbios with Diskonchip?
>Date: Thu, 27 Nov 2003 13:54:13 -0800
>
>
>If I remember correctly, Disk-on-Chip comprises NAND flash technology which
>inherently cannot execute in place, strictly sequential (data) accesses...
>So you would still need some sort of rudimentary boot flash(NOR) or other
>ROM to execute code to first load the BIOS, then the kernal, into shadow,
>then main (DRAM) memory locations, respectively.
>
>In a system I'm architecting we're still going to use a 256Kx8 flash for
>LinuxBIOS, from there use JFFS2 and associated utilities to get the kernal
>and various applications and data from a bare NAND on board.
>
>This link and its links go into much more detail than I can in this email
>about issues you may face:
>
>http://www.linux-mtd.infradead.org/tech/nand.html
>
>Good Luck!
>
>
>----- Original Message -----
>From: "Devi Priya" <ijpriya at hotmail.com>
>To: <linuxbios at clustermatic.org>
>Sent: Wednesday, November 26, 2003 10:47 PM
>Subject: Linuxbios with Diskonchip?
>
>
> > Hi,
> >
> > I shall have my BIOS program, Linux kernel and filesystem in the same
> > Diskonchip. I want to use linuxbios (for sc1200).  What is the physical
> > memory mapping that should be done? SDRAM mapped to lower order address
>and
> > Diskonchip to the higher order address. Is it correct?
> >
> > _________________________________________________________________
> > Enjoy shopping online? Get this e credit card.
> > http://server1.msn.co.in/features/amex/ It cuts cost & adds value!
> >
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios

_________________________________________________________________
Find your first love. Rekindle past joys! http://www.batchmates.com/msn.asp 
Get in touch with batchmates.



From niki.waibel at newlogic.com  Fri Nov 28 02:42:00 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Fri Nov 28 02:42:00 2003
Subject: Linuxbios with Diskonchip?
In-Reply-To: <003e01c3b530$ff3d7020$6f566044@oc.cox.net>
Message-ID: <200311280818.hAS8IV84001995@enterprise2.newlogic.at>

the doc millennium "maps" the first 2 pages of the NAND flash into its high and low address space.
it _can_ be used to boot/init memory/copy nand pages to ram/jmp to ram.
but -- you have to do all that within 512 bytes of code.

mem layout of the doc millennium (2001) is:
address
0x0000 512bytes boot code (first 2 pages copied during power on via a reset mechanism)
       512bytes boot code (mirror)
       512bytes boot code (mirror)
       512bytes boot code (mirror)
0x0800 512bytes flash area window
       512bytes flash area window (mirror)
       512bytes flash area window (mirror)
       512bytes flash area window (mirror)
0x1000 512bytes control registers -- not all 512bytes used
       512bytes control registers -- not all 512bytes used (mirror)
       512bytes control registers -- not all 512bytes used (mirror)
       512bytes control registers -- not all 512bytes used (mirror)
0x1800 512bytes boot code (first 2 pages copied during power on via a reset mechanism)
       512bytes boot code (mirror)
       512bytes boot code (mirror)
       512bytes boot code (mirror)

i'd like to get this working on a via epia-m motherboard once.
replacing the existing bios.

niki

On 27-Nov-2003 gizara wrote:
> 
> If I remember correctly, Disk-on-Chip comprises NAND flash technology which
> inherently cannot execute in place, strictly sequential (data) accesses...
> So you would still need some sort of rudimentary boot flash(NOR) or other
> ROM to execute code to first load the BIOS, then the kernal, into shadow,
> then main (DRAM) memory locations, respectively.
> 
> In a system I'm architecting we're still going to use a 256Kx8 flash for
> LinuxBIOS, from there use JFFS2 and associated utilities to get the kernal
> and various applications and data from a bare NAND on board.
> 
> This link and its links go into much more detail than I can in this email
> about issues you may face:
> 
> http://www.linux-mtd.infradead.org/tech/nand.html
> 
> Good Luck!
> 
> 
> ----- Original Message -----
> From: "Devi Priya" <ijpriya at hotmail.com>
> To: <linuxbios at clustermatic.org>
> Sent: Wednesday, November 26, 2003 10:47 PM
> Subject: Linuxbios with Diskonchip?
> 
> 
>> Hi,
>>
>> I shall have my BIOS program, Linux kernel and filesystem in the same
>> Diskonchip. I want to use linuxbios (for sc1200).  What is the physical
>> memory mapping that should be done? SDRAM mapped to lower order address
> and
>> Diskonchip to the higher order address. Is it correct?
>>
>> _________________________________________________________________
>> Enjoy shopping online? Get this e credit card.
>> http://server1.msn.co.in/features/amex/ It cuts cost & adds value!
>>
>> _______________________________________________
>> Linuxbios mailing list
>> Linuxbios at clustermatic.org
>> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios

-- 
niki w. waibel - system administrator @ newlogic technologies ag


From ijpriya at hotmail.com  Fri Nov 28 04:41:01 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Fri Nov 28 04:41:01 2003
Subject: ipl code for sc1200?
Message-ID: <BAY2-F912HGr7uFTjvY00017d72@hotmail.com>

Hi,
	I cannot find ipl.s code for sc1200 (nano mainboard). Which code should I 
use?

_________________________________________________________________
Find your first love. Rekindle past joys! http://www.batchmates.com/msn.asp 
Get in touch with batchmates.



From niki.waibel at newlogic.com  Fri Nov 28 06:10:01 2003
From: niki.waibel at newlogic.com (Niki Waibel)
Date: Fri Nov 28 06:10:01 2003
Subject: intel dual netwokcard problem on epia-m -- nearly fixed
In-Reply-To: <200311271707.hARH7084014113@enterprise2.newlogic.at>
Message-ID: <200311281146.hASBkN84029302@enterprise2.newlogic.at>

okay -- i got the dual card working -- somehow:
===
$ diff -u freebios-20031024.orig/src/mainboard/via/epia-m/mainboard.c freebios-20031024/src/mainboard/via/epia-m/mainboard.c
--- freebios-20031024.orig/src/mainboard/via/epia-m/mainboard.c 2003-07-25 05:20:20.000000000 +0200
+++ freebios-20031024/src/mainboard/via/epia-m/mainboard.c      2003-11-28 11:02:37.948735048 +0100
@@ -8,8 +8,10 @@
 static const unsigned char usbIrqs[4] = { 11, 10, 12, 5 };
 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
 static const unsigned char slotIrqs[4] = { 10, 12, 5, 11 };
+static const unsigned char dualenetaIrq[4] = { 12, 5, 11, 10 };
+static const unsigned char dualenetbIrq[4] = { 10, 12, 5, 11 };
 static const unsigned char firewireIrqs[4] = {10, 12, 5, 11 };
-static const unsigned char vt8235Irqs[4] = { 5,10, 12, 11 };
+static const unsigned char vt8235Irqs[4] = { 5, 10, 12, 11 };
 
 
 /*
@@ -57,6 +59,12 @@
        // vt8235 slot
        printk_info("setting vt8235 slot\n");
        pci_assign_irqs(0, 0x11, vt8235Irqs);
+
+       // dual eth card
+       printk_info("setting pci slot - pci-pci bridge - dual eth card (a)\n");
+       pci_assign_irqs(2, 0x4, dualenetaIrq);
+       printk_info("setting pci slot - pci-pci bridge - dual eth card (b)\n");
+       pci_assign_irqs(2, 0x5, dualenetbIrq);
 }
 
 
===

jan: thanks a lot for the tip with the bridge!!!

it seems that i have to play a little bit more with the interrupts.
the e100.o code in linux tells me ``Disabling IRQ #10'' and/or
``Disabling IRQ #12'' (depending on the values in dualenetaIrq[4] and
dualenetbIrq[4]) when bringing up the nics. and then one or both of the
nics dont work...

niki


From ijpriya at hotmail.com  Fri Nov 28 06:38:00 2003
From: ijpriya at hotmail.com (Devi Priya)
Date: Fri Nov 28 06:38:00 2003
Subject: Linuxbios with Diskonchip?
Message-ID: <BAY2-F81jp3b6uIU1Gj000180f8@hotmail.com>

Hi,
	Thanks for ur suggestion. I want to know to which CPU address does the DOC 
Millennium is mapped?


>From: Niki Waibel <niki.waibel at newlogic.com>
>Reply-To: Niki Waibel <niki.waibel at newlogic.com>
>To: Devi Priya <ijpriya at hotmail.com>
>CC: linuxbios at clustermatic.org, gizara <gizara at cox.net>
>Subject: Re: Linuxbios with Diskonchip?
>Date: Fri, 28 Nov 2003 09:18:31 +0100 (MET)
>
>the doc millennium "maps" the first 2 pages of the NAND flash into its high 
>and low address space.
>it _can_ be used to boot/init memory/copy nand pages to ram/jmp to ram.
>but -- you have to do all that within 512 bytes of code.
>
>mem layout of the doc millennium (2001) is:
>address
>0x0000 512bytes boot code (first 2 pages copied during power on via a reset 
>mechanism)
>        512bytes boot code (mirror)
>        512bytes boot code (mirror)
>        512bytes boot code (mirror)
>0x0800 512bytes flash area window
>        512bytes flash area window (mirror)
>        512bytes flash area window (mirror)
>        512bytes flash area window (mirror)
>0x1000 512bytes control registers -- not all 512bytes used
>        512bytes control registers -- not all 512bytes used (mirror)
>        512bytes control registers -- not all 512bytes used (mirror)
>        512bytes control registers -- not all 512bytes used (mirror)
>0x1800 512bytes boot code (first 2 pages copied during power on via a reset 
>mechanism)
>        512bytes boot code (mirror)
>        512bytes boot code (mirror)
>        512bytes boot code (mirror)
>
>i'd like to get this working on a via epia-m motherboard once.
>replacing the existing bios.
>
>niki
>
>On 27-Nov-2003 gizara wrote:
> >
> > If I remember correctly, Disk-on-Chip comprises NAND flash technology 
>which
> > inherently cannot execute in place, strictly sequential (data) 
>accesses...
> > So you would still need some sort of rudimentary boot flash(NOR) or 
>other
> > ROM to execute code to first load the BIOS, then the kernal, into 
>shadow,
> > then main (DRAM) memory locations, respectively.
> >
> > In a system I'm architecting we're still going to use a 256Kx8 flash for
> > LinuxBIOS, from there use JFFS2 and associated utilities to get the 
>kernal
> > and various applications and data from a bare NAND on board.
> >
> > This link and its links go into much more detail than I can in this 
>email
> > about issues you may face:
> >
> > http://www.linux-mtd.infradead.org/tech/nand.html
> >
> > Good Luck!
> >
> >
> > ----- Original Message -----
> > From: "Devi Priya" <ijpriya at hotmail.com>
> > To: <linuxbios at clustermatic.org>
> > Sent: Wednesday, November 26, 2003 10:47 PM
> > Subject: Linuxbios with Diskonchip?
> >
> >
> >> Hi,
> >>
> >> I shall have my BIOS program, Linux kernel and filesystem in the same
> >> Diskonchip. I want to use linuxbios (for sc1200).  What is the physical
> >> memory mapping that should be done? SDRAM mapped to lower order address
> > and
> >> Diskonchip to the higher order address. Is it correct?
> >>
> >> _________________________________________________________________
> >> Enjoy shopping online? Get this e credit card.
> >> http://server1.msn.co.in/features/amex/ It cuts cost & adds value!
> >>
> >> _______________________________________________
> >> Linuxbios mailing list
> >> Linuxbios at clustermatic.org
> >> http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
>
>--
>niki w. waibel - system administrator @ newlogic technologies ag

_________________________________________________________________
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http://www.msn.co.in/DigitalSelf/ Enter this cool contest.



From linuxbios at xdr.com  Sat Nov 29 13:02:01 2003
From: linuxbios at xdr.com (Dave Ashley)
Date: Sat Nov 29 13:02:01 2003
Subject: automatic power on possible?
Message-ID: <200311291839.hATIdOWN006185@xdr.com>

>Does anyone know what the BIOS is doing what linuxbios does not?

The southbridges of the via epia + epia-m have a feature that a specific
bit in the cmos ram will cause the motherboard to be always on. Even when off
it uses the ATX standby power to power a little portion of the southbridge
chip. For our purposes this was insufficient, we need the motherboard to be
*ON!!!* even in the event of cmos content corruption, failure of cmos battery.
So we had to devise a hardware based solution.

I think your thing is something else. The power on at a certain time works
by the machine not really being off, it is in a soft off state. So the range
of power off to full on would be
1)OFF, power supply is completely unplugged
2)Off, nothing functioning but the little bit of standby circuitry
3)Soft off, perhaps cpu is halted, as many things are shut down as possible
4)Fully on

Linuxbios has no presence except at state 2--anything else is beyond its scope.
Conceivably linuxbios could hit the bit to keep the power on all the time.

Note I am just giving my opinion, which is not official in any way.

-Dave



From rminnich at lanl.gov  Sat Nov 29 19:48:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Nov 29 19:48:01 2003
Subject: epia-m results of getpir [PMX:#]
In-Reply-To: <20031127143005.A23275@mail.cwlinux.com>
Message-ID: <Pine.LNX.4.44.0311291824250.17575-100000@maxroach.lanl.gov>

On Thu, 27 Nov 2003, Andrew Ip wrote:

> AFAIK, pirq table on EPIA doesn't work.  We fixed the irqs by writing irq#
> to devices.

so this is another case where the PIRQ tables from the standard bios are 
wrong?

ron



From rminnich at lanl.gov  Sat Nov 29 19:49:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Nov 29 19:49:00 2003
Subject: sc1200 with linuxbios possiblility?
In-Reply-To: <20031127071401.9250.qmail@web8201.mail.in.yahoo.com>
Message-ID: <Pine.LNX.4.44.0311291825150.17575-100000@maxroach.lanl.gov>

just make the linuxbios payload a linux kernel+initrd combination. We've 
been doing this for years. 

ron




From rminnich at lanl.gov  Sat Nov 29 19:50:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Nov 29 19:50:01 2003
Subject: intel dual netwokcard problem on epia-m
In-Reply-To: <200311271227.hARCRl84008740@enterprise2.newlogic.at>
Message-ID: <Pine.LNX.4.44.0311291826560.17575-100000@maxroach.lanl.gov>

I think somebody just plugged in a bad irq_tables.c 

So test that one you have, if it works, tell me and I'll put it into the 
tree.

ron



From rminnich at lanl.gov  Sat Nov 29 19:57:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Nov 29 19:57:00 2003
Subject: Linuxbios with Diskonchip?
In-Reply-To: <003e01c3b530$ff3d7020$6f566044@oc.cox.net>
Message-ID: <Pine.LNX.4.44.0311291831320.17575-100000@maxroach.lanl.gov>

On Thu, 27 Nov 2003, gizara wrote:

> 
> If I remember correctly, Disk-on-Chip comprises NAND flash technology which
> inherently cannot execute in place, strictly sequential (data) accesses...
> So you would still need some sort of rudimentary boot flash(NOR) or other
> ROM to execute code to first load the BIOS, then the kernal, into shadow,
> then main (DRAM) memory locations, respectively.

yes, and ollie lo did this three years ago on sis 630. see code, read 
HOWTO.

I am terse right now, can't type much due to stupid pinched nerve, so bear 
with me, but this was done and works fine. Ollie, can you fill in details?

ron



From rminnich at lanl.gov  Sat Nov 29 19:58:01 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Nov 29 19:58:01 2003
Subject: Linuxbios with Diskonchip?
In-Reply-To: <BAY2-F1359LT6yeLnHT00016fd6@hotmail.com>
Message-ID: <Pine.LNX.4.44.0311291834380.17575-100000@maxroach.lanl.gov>

On Fri, 28 Nov 2003, Devi Priya wrote:

> Hi,
> 
>       I am using Diskonchip millennium with boot capability. I just want to 
> know if diskonchip is mapped to the high order physical address (at reset) 
> and is any remapping is done later?

usually mapped at flash address, right? 0xf0000 and 0xfff00000

ron



From rminnich at lanl.gov  Sat Nov 29 19:59:00 2003
From: rminnich at lanl.gov (ron minnich)
Date: Sat Nov 29 19:59:00 2003
Subject: Linuxbios with Diskonchip?
In-Reply-To: <200311280818.hAS8IV84001995@enterprise2.newlogic.at>
Message-ID: <Pine.LNX.4.44.0311291835550.17575-100000@maxroach.lanl.gov>

On Fri, 28 Nov 2003, Niki Waibel wrote:

> 
> i'd like to get this working on a via epia-m motherboard once.
> replacing the existing bios.

good luck, it's a hard chipset to do startup in that little space.

ron



From donald.zoch at amd.com  Sat Nov 29 23:00:00 2003
From: donald.zoch at amd.com (Donald Zoch)
Date: Sat Nov 29 23:00:00 2003
Subject: arima hdama linuxbios
In-Reply-To: <Pine.LNX.4.44.0311261610470.21656-100000@maxroach.lanl.gov>
References: <20031126140928.B17280@lard.amd.com>
 <Pine.LNX.4.44.0311261610470.21656-100000@maxroach.lanl.gov>
Message-ID: <20031126180142.A3214@lard.amd.com>

I mean screen output.    Thanks for the info.  
I'll try the serial port next time I get the chance. 

On Wed, Nov 26, 2003 at 04:10:56PM -0700, ron minnich wrote:
> do you mean screen or serial output?
> 
> there's no vga yet.
> 
> ron
> 
Donald
----
Donald Zoch                         5900 E. Ben White Blvd. MS 625
Advanced Micro Devices              Austin, Tx  78741
MPD Unix Systems Administrator      Phone: (512) 602-7945
donald.zoch at amd.com                 Pager: (512) 604-5401



From svante.signell at telia.com  Sun Nov 30 18:14:01 2003
From: svante.signell at telia.com (Svante Signell)
Date: Sun Nov 30 18:14:01 2003
Subject: Level 2 cache activation code?
In-Reply-To: <1069797381.15097.72.camel@em2.my.own.domain>
References: <Pine.LNX.4.44.0311251406230.10874-100000@maxroach.lanl.gov>
	 <1069797381.15097.72.camel@em2.my.own.domain>
Message-ID: <1070234054.19232.32.camel@em2.my.own.domain>

I have now made a small kernel module based on l2_cache.c giving the
following output:

Nov 30 17:46:56 cl-dual kernel: Configuring L2 cache...CPU signature of
6b0 so no L2 cache configuration
Nov 30 17:46:56 cl-dual kernel: Enable Cache
Nov 30 17:46:56 cl-dual kernel: done.
Nov 30 17:46:56 cl-dual kernel:  cache_on  installed

No speed-up seen. Extremely slow as before. Any hints? mtrr is OK, I
believe. Is it the microcode??

The processor is an 1.3GHz Celeron Tualatin, with CPUID: 6b0. According
to the code in l2_cache.c newer CPUs than Coppermine (680) does not need
the L2 setup code. Is this the case?
if (signature < 0x630 || signature >= 0x680) {
  printk_debug("CPU signature of %x so no L2 cache configuration\n",
signature);
  goto done;

I few questions:
1. Does a kernel module have to be a standalone object without linking
stage?
2. How to add libraries to link with, if unresolved externals show up.
3. How to create a kernel module consisting of more than one object
file. Now I include the needed source files into the main one.
4. The cflags used are:
CFLAGS = -D__KERNEL__ -DMODULE -I ./include -I$/usr/src/linux/include -I
/usr/src/kernel-headers-2.4.22-1 -O2 -Wall -g
5. My module code looks like:
cat cache_on.c

#include <linux/module.h>
#include <linux/kernel.h>
(#include source files and other header files)

#define PFX " cache_on "

int init_module(void)
{
 p6_configure_l2_cache();
 printk(KERN_INFO PFX " installed \n");
 return 0;
}

void cleanup_module(void)
{
 printk(KERN_INFO PFX " removed\n");
}

On Tue, 2003-11-25 at 22:56, Svante Signell wrote:
> Ron and Takeshi,
> 
> Thanks for the tip. I'll try that next. Any pointers how to create a
> kernel module? So far I have only been writing code for user space.
> 
> On Tue, 2003-11-25 at 22:06, ron minnich wrote:
> > what I did to test this code was to build a kernel module for my linux, 
> > with this code inside, and insmod the kernel module.
> > 
> > ron
> > 
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios


From dpd at alphalink.com.au  Sun Nov 30 18:51:00 2003
From: dpd at alphalink.com.au (Denis Dowling)
Date: Sun Nov 30 18:51:00 2003
Subject: Level 2 cache activation code?
References: <Pine.LNX.4.44.0311251406230.10874-100000@maxroach.lanl.gov> <1069797381.15097.72.camel@em2.my.own.domain> <1070234054.19232.32.camel@em2.my.own.domain>
Message-ID: <00de01c3b79c$5afc6f20$0701000a@techmanager>

Hi Svante,

----- Original Message ----- 
From: "Svante Signell" <svante.signell at telia.com>
To: "ron minnich" <rminnich at lanl.gov>
Cc: "Takeshi Sone" <ts1 at tsn.or.jp>; <linuxbios at clustermatic.org>
Sent: Monday, December 01, 2003 10:14 AM
Subject: Re: Level 2 cache activation code?


>
> I have now made a small kernel module based on l2_cache.c giving the
> following output:
>
> Nov 30 17:46:56 cl-dual kernel: Configuring L2 cache...CPU signature of
> 6b0 so no L2 cache configuration
> Nov 30 17:46:56 cl-dual kernel: Enable Cache
> Nov 30 17:46:56 cl-dual kernel: done.
> Nov 30 17:46:56 cl-dual kernel:  cache_on  installed
>
> No speed-up seen. Extremely slow as before. Any hints? mtrr is OK, I
> believe. Is it the microcode??
>
> The processor is an 1.3GHz Celeron Tualatin, with CPUID: 6b0. According
> to the code in l2_cache.c newer CPUs than Coppermine (680) does not need
> the L2 setup code. Is this the case?

This was based on the assumption that all CPU from the coppermine forward
had the cache integrated onto the CPU die. Is this the case with your CPU.
Is it just a single large CPU on the slot1 pcb or does there look to be
cache chips mounted on the board as well?

> if (signature < 0x630 || signature >= 0x680) {
>   printk_debug("CPU signature of %x so no L2 cache configuration\n",
> signature);
>   goto done;

You could always just drop this test and see what happens later. If the CPU
does have external cache chips then this code might just work in
initiallising the cache.
>
> I few questions:
> 1. Does a kernel module have to be a standalone object without linking
> stage?

Yes just an object file compiled with the correct module flags.

> 2. How to add libraries to link with, if unresolved externals show up.

They should not. It is possible to add libraries but generally it is simpler
to keep all of the module code in the one file. Modules can reference other
modules if required. The depmod program will then load all required modules.

> 3. How to create a kernel module consisting of more than one object
> file. Now I include the needed source files into the main one.

Generally this is the easiest way to test this.

> 4. The cflags used are:
> CFLAGS = -D__KERNEL__ -DMODULE -I ./include -I$/usr/src/linux/include -I
> /usr/src/kernel-headers-2.4.22-1 -O2 -Wall -g

Have a look at a normal kernel compile and compare these arguments against
what is used for the other modules.

> 5. My module code looks like:
> cat cache_on.c
>
> #include <linux/module.h>
> #include <linux/kernel.h>
> (#include source files and other header files)
>
> #define PFX " cache_on "
>
> int init_module(void)
> {
>  p6_configure_l2_cache();
>  printk(KERN_INFO PFX " installed \n");
>  return 0;
> }
>
> void cleanup_module(void)
> {
>  printk(KERN_INFO PFX " removed\n");
> }

Looks fine. Turn on as much debugging in the l2_cache code as possible and
post to me and I will decode. Need to be able to see all of the printk_debug
messages.

Regards,
Denis