Level 2 cache activation code?
rminnich at lanl.gov
Thu Nov 6 08:40:01 CET 2003
On Thu, 6 Nov 2003, Svante Signell wrote:
> Sorry for taking up this thread again but now I have made a test of the
> l2_cache activation code and have some further questions.
you don't need this code any more. The last processor it mattered for is
long dead. I am not removing it but if you are having trouble then you
have a PII; do you?
> 4. You state that the L2 cache stuff is only needed for P2 CPUs, not for
> P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron
> 2 CPU (Tualatin), which is of P3 type. What if the BIOS does not
> recognise the CPU and disables the L2 cache? People claim that AMI
> BIOSes work this way. It the enabling code sufficient to make things
> 5. If the slowness is not due to a disabled L2 cache (how to test this
> properly btw?), can the problems be solved by tying with the mtrr or
> microcode update code?
use lmbench to scope out your caches.
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