Level 2 cache activation code?

Takeshi Sone ts1 at tsn.or.jp
Fri Nov 14 02:08:01 CET 2003


On Fri, Nov 14, 2003 at 08:26:55AM +0100, Svante Signell wrote:
> For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
> around 400ns independent of array size. The only thing changig is that
> the latency numbers increase to 440-460ns for large values of the
> stride. My interpretation is that not even the L1 cache is working
> properly. All other tests indicate a _very_ slow CPU, around 7MHz is
> measured by lmbench (BTW how good is this value?)  compared to the
> expected 1.3GHz. Two questions immediately arise.
> 
> 1. Is this slowness reasonable if _no- caches are working properly?
> 2. If there is a problem with the on-chip voltage regulator and the CPU
> clock speed is really 7MHz, as measured by lmbench, can the CPU operate
> properly at this low speed. I thought there was a _lower_ limit as well
> as an upper limit for the operating frequency?

What do these commands say?

    cat /proc/mtrr
    cat /proc/cpuinfo

-- 
Takeshi



More information about the coreboot mailing list