Level 2 cache activation code?
Svante Signell
svante.signell at telia.com
Fri Nov 14 16:12:00 CET 2003
On Fri, 2003-11-14 at 08:41, Takeshi Sone wrote:
> On Fri, Nov 14, 2003 at 08:26:55AM +0100, Svante Signell wrote:
> > For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
> > around 400ns independent of array size. The only thing changig is that
> > the latency numbers increase to 440-460ns for large values of the
> > stride. My interpretation is that not even the L1 cache is working
> > properly. All other tests indicate a _very_ slow CPU, around 7MHz is
> > measured by lmbench (BTW how good is this value?) compared to the
> > expected 1.3GHz. Two questions immediately arise.
> >
> > 1. Is this slowness reasonable if _no- caches are working properly?
> > 2. If there is a problem with the on-chip voltage regulator and the CPU
> > clock speed is really 7MHz, as measured by lmbench, can the CPU operate
> > properly at this low speed. I thought there was a _lower_ limit as well
> > as an upper limit for the operating frequency?
>
> What do these commands say?
>
> cat /proc/mtrr
> cat /proc/cpuinfo
Normal output: 1.4GHz Tualatin
cat/proc/mtrr:
reg00: base=0x00000000 ( 0MB), size= 256MB: write-back, count=1
reg01: base=0xe4000000 (3648MB), size= 8MB: write-combining, count=1
# Faulty system:
cat /proc/mtrr
cat: /proc/mtrr: No such file or directory
Faulty system:
$ cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 11
model name : Intel(R) Celeron(TM) CPU 1300MHz
stepping : 4
cpu MHz : 1340.197
cache size : 256 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 mmx fxsr sse
bogomips : 2641.10
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