Level 2 cache activation code?

[Svante Signell]

I did boot another kernel and for that kernel there was one entry for
mtrr, so this seems to work. However, now I have tried executing both
the mtrr and cache activation code, and when coming to any inline
assembly code the program exits with a segfault :( All commented out
calls have been tried one after the other by single-stepping with gdb. 

Below is the main progam I used:

#include <mem.h>
main()
{
  struct mem_range mem;
  int res = iopl(3);
  if(res) {error();exit(-1);}
  //  cache_enable();
  //  p6_configure_l2_cache();
  cache_on(mem);
}
 
On Sat, 2003-11-15 at 20:54, ron minnich wrote:
> On Sun, 16 Nov 2003, Takeshi Sone wrote:
> 
> > On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
> > > # Faulty system:
> > > cat /proc/mtrr
> > > cat: /proc/mtrr: No such file or directory
> > 
> > I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
> > (MTRR is the registers that tell CPU where to cache)
> 
> 
> no, even if bios does not set mtrr, those registers exist, and are 
> readable. Something weird is going on here!
> 
> ron
> is going on here. 
> 
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