About Hardreset on Opteron MB

[Stefan Reinauer]

* Eric W. Biederman <ebiederman at lnxi.com> [031119 00:16]:
> So it might make sense to set everything up in a very early pass before
> memory reset.  Reset the system, and then let the existing resets will
> not trigger.
> 
> Either that or Stefans delayed scheme.   At this point I am not certain
> which will be easier to maintain.  If we do implement the delayed reset
> I want to move the memory clear code up into the generic framework so we
> don't have to clear memory twice.  But if we can get the resets over with
> before we initialize memory we are in better shape.  That plus something
> like the kernels quirk interface to handle the various know bits of buggy
> hardware and we should be ok.

Would cache-as-ram be an alternative for AMD64 cpus to move the pretty
complex ht code to a point as early as possible? Romcc really does a
great job, but IIRC the current ht speed code is where it is now because
it is really hard to do before there is memory.

I also suspect AMD doing a better job in keeping cache as ram
initialization code the same over different cpu steppings than Intel
managed with their P-IV.

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development