Level 2 cache activation code?

Takeshi Sone ts1 at tsn.or.jp
Tue Nov 25 15:24:01 CET 2003


On Tue, Nov 25, 2003 at 08:34:22PM +0100, Svante Signell wrote:
> Do I need to use gcc-2.95.x instead of gcc-3.3.2 to make the inline
> assembly run OK? Or is there something about 16bit mode versus 32bit
> mode?

I bet it's not the compiler problem.
I guess it's a kernel-mode vs. user-mode problem.
I'm not very sure but some instructions like cache manupilation
need to be run in kernel-mode, even if IOPL=3.
If such instructions executed in user-mode, it results in segfault.
So you have to run your cache activation code in the kernel, either
put that code in the kernel itself or to make a kernel module to do it.

However, I don't know what exact code you need to enable the cache,
given that MTRR is working..

> On Sun, 2003-11-16 at 11:14, Svante Signell wrote:
> > I did boot another kernel and for that kernel there was one entry for
> > mtrr, so this seems to work. However, now I have tried executing both
> > the mtrr and cache activation code, and when coming to any inline
> > assembly code the program exits with a segfault :( All commented out
> > calls have been tried one after the other by single-stepping with gdb. 
> > 
> > Below is the main progam I used:
> > 
> > #include <mem.h>
> > main()
> > {
> >   struct mem_range mem;
> >   int res = iopl(3);
> >   if(res) {error();exit(-1);}
> >   //  cache_enable();
> >   //  p6_configure_l2_cache();
> >   cache_on(mem);
> > }
> >  
> > On Sat, 2003-11-15 at 20:54, ron minnich wrote:
> > > On Sun, 16 Nov 2003, Takeshi Sone wrote:
> > > 
> > > > On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
> > > > > # Faulty system:
> > > > > cat /proc/mtrr
> > > > > cat: /proc/mtrr: No such file or directory
> > > > 
> > > > I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
> > > > (MTRR is the registers that tell CPU where to cache)
-- 
Takeshi



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