AMD8151

[Stefan Reinauer]

* Eric W. Biederman <ebiederman at lnxi.com> [031020 20:23]:
> > my config.lb defines:
> > northbridge amd/amdk8 "mc0"
> >         southbridge amd/amd8151 "amd8151" link 0
> >         end
> >         southbridge amd/amd8111 "amd8111" link [1|2]
> >         end
> > end
> > 
> > What is the right way of describing how the 8111 is connected in the
> > config?
> 
> So far I pretend a hypertransport chain is just a bus so
> the amd 8111 hangs off of link 0 of mc0.
 
Ok. When LinuxBIOS is configured like this, I get a reboot somewhere in
PCI setup (see earlier logs)

> > If I set amd8111 link to 0 I get a reboot plus hang at
> > PCI: 03:00.2 [ffff/ffff] disabled
> 
> It might be an interesting test case not to disable anything,
> in the config file..
 
I'll try that right ahead. In the hdama config file, some "pci" tags
contain [on|off], others don't. Why?
 
> > amd8111_enable dev: PCI: 03:01.0 lpc_dev: PCI: 01:05.0 index: 9 reg:
> > fe9f -> fce
> 
> This bit looks decidedly weird. I would expect the 8111 lpc device to
> show up at 01:04.0.  And it shows up at 01:5 odd but ok.
> I guess bus 2 goes to the agp.  And then bus 3 would go to the
> pci buss hanging off the amd8111.  So 3:0.0 makes sense to
> be the pci device hanging off there.
> 
> The really weird part is that the disable is clearing multiple
> enable bits and that does not feel correct somehow.
 
 
> > Copying LinuxBIOS to ram.
> > Jumping to LinuxBIOS.
> 
> And this feels like memory corruption.  I wonder if I broke
> the unbuffered dimm case?
 
That might explain why I get weird read errors when plugging memory in
the 2nd dimm slot, no?
I'll test some registered dimms, too.
 
> > I also noticed that not all elements in the capability linked list
> > of the 8151 are HT capabilities. The first one on 8151 is an AGP
> > capability element. Maybe this explains why a different ordered probing
> > is needed, does LinuxBIOS correctly skip AGP capability blocks?

> It should ignore all but HT capabilities bugs are possible.
> 
> BTW I need to find a way to cleanly handle bugs in capabilities.

Currently this is the suggested (but afaik not supported) way.

cpu k8 "cpu0"
 register "up"   = "{ .chip = &amd8111, .ht_width=8, .ht_speed=200 }"
 register "down" = "{ .chip = &amd8151, .ht_width=16, .ht_speed=600 }"
end

If this is the preferred way, I'd move the register statements to
the nortbridge rather than the cpu. Otoh, they do belong to the device
they are attached to.
What about enhancing the "southbridge" statement? It contains "link 0"
already. It could also specify "speed 200 width 8" in addition to that.

generically supporting capabilities needs a defined set of capabilities
to support (PCI caps, HT caps, ...?)

  Stefan

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