[COMMIT] Infrastructure Updates 4
YhLu
YhLu at tyan.com
Wed Sep 3 12:19:00 CEST 2003
Eric,
For s2885
8151
| (link0)
CPU0 -- CPU1
| (link2)
8131
|
8111
So the Config.lb should include
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8151 "amd8151"
pci 5:0.0
pci 5:1.0
end
southbridge amd/amd8131 "amd8131"
pci 1:0.0
pci 1:0.1
pci 1:1.0
pci 1:1.1
southbridge amd/amd8111 "amd8111"
pci 1:0.0
pci 1:1.0
pci 1:1.1
pci 1:1.2
pci 1:1.3
pci 1:1.5
pci 1:1.6
end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
cpu k8 "cpu0"
register "up" = "{ .chip = &amd8151, .ht_width=16, .ht_speed=600 }"
register "down" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600
}"
end
cpu k8 "cpu1"
end
Is that right?
Regards
YH.
_
More information about the coreboot
mailing list