Using Cache As Ram for K8

[Tony Cheng]

It's great to hear that AMD CPU allow software to access Cache, it's
absolutely not allowed in the Intel CPU which I just finish working on.

I guess you must turned off cache completely and CPUs are not prefetching,
snooping and ete. before you use it as memory, right? I'm not that
knowledgable at this point with AMD Opteron. but this is pretty intrigueing.
I will try it someday, I hope AMD supports this type of use. In another
word, AMD will not scew up the cache data software saved at the background
and SW saving data to it doesn't impact CPU function.

I'm really try to ask you about another question, you have mentioned the AMD
Serenade Mainboard, Do you have the LinuxBIOS source code for this AMD
Serenade Mainboard? I couldn't find it in the Sorceforge CVS. (Only AMD Solo
and Quatet are available there)

I have a Tyan board, and Yh gave me some latest code which works great. But
Tyan doesn't have a HDT Header. AMD Serenade will be a good chioce for us to
try some our code and watch it using an American Arium.

Thanks

Tony

----- Original Message ----- 
From: "Li-Ta Lo" <ollie at lanl.gov>
To: "LinuxBIOS" <linuxbios at clustermatic.org>; "Eric Biederman"
<ebiederman at lnxi.com>; "YhLu" <YhLu at tyan.com>
Sent: Thursday, June 24, 2004 10:27 AM
Subject: Using Cache As Ram for K8


> Hello,
>
> I have successfully used the cache in the K8 processor as RAM on
> the AMD Serenade mainboard. The cache as ram is used as a tiny
> stack space for the code generated by GCC which replace the need
> for a register only C complier like ROMCC. Now the whole LinuxBIOS
> C code can be compiled by GCC.
>
> There are few problems remaining. The first thing is I can only
> use 7 cache lines of cache (448 bytes) reliably in the K8. The
> access to the 8th cache line is unstable and the access to the
> 9th cache line hangs the processor. The other problem is the
> optimize_connection() function for multi-processor configuration
> runs unstably under CAR. It does not overflow the stack, it's just
> plain unstable for some reason. So I can only configure the mainboard
> as Uniprocessor.
>
> Is there anyone has any idea about these problems ? If we can solve
> these two problems, Cache As Ram can be used routinly for K8 and
> probably we can try to extend it to some other processors.
>
> YHLu,
> Do you have any dual K8 EVB with HDT pin out and works "perfectly"
> under normal (ROMCC) LinuxBIOS ? The ROMCC LinuxBIOS deos not work
> for the AMD Serenade board 100% (I still have the phantom device s
> problem) and the s2885 board we have does not have the pin out.
>
> Eric,
> What is the "effective" or "equalvalent" stack size of ROMCC ?
> Is 448 bytes of stack adquant for ROMCC "linted" code in general ?
>
>
> Ollie
>
>
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