Merge/Cleanup status

Yinghai Lu yhlu at tyan.com
Mon Nov 1 17:38:00 CET 2004


Eric,

What the reasons that you set MTRRs for one CPU two times.?
amd_setup_mtrrs of amd_mtrr.c call x86_setup_mtrrs...

regards

Yinghai Lu

APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor AMD device f5a
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
Setting variable MTRR 2, base: 3072MB, range:  512MB, type WB
Setting variable MTRR 3, base: 3584MB, range:  256MB, type WB
Setting variable MTRR 4, base: 3840MB, range:  128MB, type WB
Setting variable MTRR 5, base: 4096MB, range: 4096MB, type WB
Setting variable MTRR 6, base: 8192MB, range: 8192MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled




More information about the coreboot mailing list