Eric W. Biederman ebiederman at
Mon Nov 29 15:32:00 CET 2004

YhLu <YhLu at> writes:

> Every pci_read_config and pci_write_config need to findout top parenent bus
> to get bus ops. (get_pbus).
> It looks weird....

Yes, it does look weird.  But it comes very close to modeling reality.
You have to find the top of the pci bus to perform reads and writes.
The apparent inefficiency does not thrill me but the tree is not
usually very deep so in practice get_pbus only needs to execute one
or two look iterations.

It allows any bus that has specific methods for pci read/write
to implement them, and any bus that does not need not care.

If I read the documentation correctly one of the powerpc northbridges
the cpc710 I think actually has 2 separate pci domains with a 
different base register to access each of the different pci domains.

So having pci access methods that vary by pci domain is a case that
needs to be handled, and this code allows it.  

In addition we need something similar to handle the extended pci
accesses which PCI express allows.  I still need to find out how
the hypertransport to PCI-Express bridges handle that case.  Do the
decode the reserved HT memory region that is just below 1TB or do
they do something else?


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