PCI IRQ tables
liutao at safe-mail.net
Mon Oct 18 22:51:00 CEST 2004
Thanks for your answer:)
But I'm still not very clear of the PCI interrupt
routing for legacy PIC mode on AMD64. For example in
s2885 mainboard the pirq table specifys the AMD8111
as the interrupt router (bus1 dev4 fn3), then how
does the interrupt from the PCIX devices on AMD8131
routed to CPU?
Or does the interrupt router in pirq table only
responses of legacy 32bitPCI/ISA devices, and Linux
handles all the AMD8131?
Another question is, if use IO-APIC, does linuxbios
specify the bus/devfn in mptable and let linux
do the real job of setting the IO-APIC registers?
>It's the same if you enable io apic.
>In the irq-table.
>Entry Bus 1 for 8111 and 8131
>Other 8131 bus may be discovered by Kernel.
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