Via EPIA-MII ROM speed?

talbotx at talbotx at
Fri Feb 11 07:57:01 CET 2005

Thank you for some real numbers.  Ok, a few note to add to your very good description of the issue at hand. I found that my hard drive has a spin up time of about 3~5 seconds so that’s out of the picture. Solved that issue by switching from a HDD to a Compact Flash (CF), no spin up, almost no seek time.  The board (Via EPIA-MII) has a built on CF slot.  Linux bios allowed me to boot from the CF.  Also there is one other number we need to look at.  How long does it take for FILO to load?  I have no clue on numbers for FILO.  The 2 step process LinuxBios à kernel (LBK), or the 3 set process, LinuxBios à FILO à kernel (LBFK).  In the LBFK process all the transaction are faster, but the second step my slow down the process long enough to make the LBK process faster. I am not very sure here and there are still just ideas and I need to do some real testing.  In the long run I may be forced to use LBFK as the smallest 2.6 kernel I have been able to compile comes in at 404k+linuxbios > ROM.  I think 512KB is the biggest ROM chip out there that will work with this board.

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> On Fri, 11 Feb 2005 08:32:43 -0800, Adam Talbot wrote: 
> > How fast is the ROM chip MB/s. In my case a SST 39SF020A 70-4C-NH. I was 
> > trying to figure out what would be faster... Linuxbios calling a 2.6 kernel 
> > off the hard drive, or loading my 2.6 kernel out of the rom file. I have the 
> > 512k rom chips, so I have room to add my kernel. If I put my kernel into 
> > the rom, can I just call it as a payload? 
> > -Adam 
> Your challenge won't be loading speed but rather getting a kernel in 512k. 
> That said my first guess is that in ROM is going to be much faster on 
> all but a few special cases but lets just do some math and see... 
> For loading from the BIOS chip you are talking ISA cycles. Which is 
> approx 1uS per cycle but you are only going to get 8 bits at a time 
> unless you happend to have a 16-Bit flash. 
> Lets neglect RAM speed since it should be the same in both cases. 
> The string copy functions of x86 assembly will let you set up a block 
> memory move with basiclly no overhead. So you should be able to load 
> the entire ROM into a block of RAM in 525 mS. 
> Reading from IDE will happen over the PCI bus which is much faster. I 
> don't really know what the actual cycle time of PCI is sine it varies 
> but the clock is 4 tims faster so lets assume we can get 4x the cycle 
> rate or 250 ns per cycle. Ide devices are 16 bit so we are going to 
> approx 8x the data rate. However, the HD involes a seek for every 
> 512 16 bit words. I don't think FILO takes advantage of the streaming 
> commands. So for every 1kb we are talking 128uS of data time and 10 
> to 12 ms avg seek. so 512 x 12.128 mS give you 6.2 seconds. 
> But thats a worst case number and neglects the cache of a modern HD. 
> If the HD is able to cache up the entire 512k so the seek times are 0 
> then the number would have a low of .128 mS * 512 = 65mS. That's 
> negelecting the overhead with issuing the read commands to the IDE 
> device so in reality its higher than that. 
> So the only answer is you have to test and see. Could be faster could 
> be slower. Also if you take in account harddisk spinup time from a 
> cold boot which is always going to be larger than .5s it in ROM will 
> be faster. But if you use something like a compact flash you don't 
> have the hd platter spinup time. Then its going to depend on the 
> device. 
> I'd be intersted in hearing about your results. 
> -- 
> Richard A. Smith 
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