From ramesh_bios at yahoo.com  Tue Mar  1 00:47:00 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Tue Mar  1 00:47:00 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: 6667
Message-ID: <20050301112223.19403.qmail@web30009.mail.mud.yahoo.com>

Good point. I did not know about ACPI. Ok, looking
through the source, I don't see ACPI in the gx1 code.
So I presume that this means that LinuxBIOS doesn't
provide ACPI support in the case of the Geode.

Would I be able to test if Linux 2.6.10 is able to
parse the normal BIOS' PIRQ table by booting linux
with acpi=off? If it does work at that point, then I
could assume that the area to be fixed would be the
PIRQ table generation in LinuxBIOS. If not, then it'd
be time to examine the kernel's pirq code.

I'm still somewhat confused though. At the point that
LB calls the kernel, shoudn't LB have used the IRQ
table values to set the PCI config space registers to
write IRQ values to the PCI config registers and such?
And if that were done, Linux would not need to parse a
PIRQ table, yes?

Thanks.


--- Stefan Reinauer <stepan at openbios.org> wrote:
> * ramesh bios <ramesh_bios at yahoo.com> [050301
> 08:19]:
> > That's odd. My understanding might be lacking. 
> > 
> > I think the PIRQ table parser in 2.6.10 seems to
> work
> > because it works when I use the normal BIOS. 
> 
> Sure normal BIOS does not provide ACPI instead? In
> such case, PIRQ stays
> mostly untouched.
> 
> Stefan
> 
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


		
__________________________________ 
Do you Yahoo!? 
Take Yahoo! Mail with you! Get it on your mobile phone. 
http://mobile.yahoo.com/maildemo 


From petekarl at student.chalmers.se  Tue Mar  1 01:09:00 2005
From: petekarl at student.chalmers.se (Peter Karlsson)
Date: Tue Mar  1 01:09:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
Message-ID: <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>

On Tue, 1 Mar 2005, Anton Borisov wrote:

> Payload is file that holds, for instance, LAN ROM, i.e. software 
>responsible for remoting loading from server. It's just an example. There 
>are FAQs (try to google) which explain much of your questions.

LinuxBIOS (initialises hardware) -> payload (etherboot,OpenBIOS, FILO 
etc.) (-> operating system)?

Ok, but that was just an example. Technical jargon explanation is still 
needed to get into linuxbios. For instance:
http://www.clustermatic.org/pipermail/linuxbios/2003-March/002240.html

This mail mentions SPD,VID,DID,I2C etc. Does everybody know what these 
mean? To get more people interested in linuxbios one has to lower the 
bars, and technical jargon is a major blocker (at least for me). And yes, 
I do know what i2c is, and I think I know what spd is (ram speed?) but vid 
& did does not ring a bell. For anyone not knowing what i2c is I'll 
recommend:
http://www.esacademy.com/faq/i2c/index.htm

Best regards

Peter K


From andreas at bawue.net  Tue Mar  1 01:20:01 2005
From: andreas at bawue.net (Andreas Thienemann)
Date: Tue Mar  1 01:20:01 2005
Subject: new free software foundation crusade: http://www.fsf.org/campaigns/free-bios.html
In-Reply-To: <20050301094558.zeurs4wccggwo8co@2pmtechnologies.com>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
 <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
 <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
 <Pine.LNX.4.58.0503010049250.3322@gate.bb.dicp.net>
 <Pine.LNX.4.58.0502281712350.18334@enigma.lanl.gov>
 <20050301094558.zeurs4wccggwo8co@2pmtechnologies.com>
Message-ID: <Pine.LNX.4.58.0503011250480.12790@gate.bb.dicp.net>

Hi Mark,

On Tue, 1 Mar 2005 mark.wilkinson at 2pmtech.com wrote:

> Andreas, which version of LB where you looking at ? People still seem to be
> getting on ok with V1 and the HOW-TO I wrote some time ago.
I tried the Linuxbios 1 version together with the howto.

> Which version of the EPIA are you using, is it the original EPIA or one
> of the other version (ie EPIA-M, EPIA-MII etc) ? If it's the EPIA, I may
> be able to help.
I tried the epia-pd.
According to the specs, the hardware itself is not that different from the 
M version. Seems not to be the case however.

bye,
 andreas


From mark.wilkinson at 2pmtech.com  Tue Mar  1 01:53:00 2005
From: mark.wilkinson at 2pmtech.com (mark.wilkinson at 2pmtech.com)
Date: Tue Mar  1 01:53:00 2005
Subject: new free software foundation crusade:
	http://www.fsf.org/campaigns/free-bios.html
In-Reply-To: <Pine.LNX.4.58.0503011250480.12790@gate.bb.dicp.net>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
	<Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
	<Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
	<Pine.LNX.4.58.0503010049250.3322@gate.bb.dicp.net>
	<Pine.LNX.4.58.0502281712350.18334@enigma.lanl.gov>
	<20050301094558.zeurs4wccggwo8co@2pmtechnologies.com>
	<Pine.LNX.4.58.0503011250480.12790@gate.bb.dicp.net>
Message-ID: <20050301122907.dhz10ccgk0cc404s@2pmtechnologies.com>

Hi Andreas

Quoting Andreas Thienemann <andreas at bawue.net>:

> Hi Mark,
>
> On Tue, 1 Mar 2005 mark.wilkinson at 2pmtech.com wrote:
>
>> Andreas, which version of LB where you looking at ? People still seem to be
>> getting on ok with V1 and the HOW-TO I wrote some time ago.
> I tried the Linuxbios 1 version together with the howto.
>
>> Which version of the EPIA are you using, is it the original EPIA or one
>> of the other version (ie EPIA-M, EPIA-MII etc) ? If it's the EPIA, I may
>> be able to help.
> I tried the epia-pd.

This could be the start of the problem, from what I remember, the versions of
the EPIA after the initial one where each different enough to cause problems,
such as a different north/south bridge requiring different configurations to
get the ram, serial, etc up and running.

The inital EPIA has a via VT8601 northbridge and a VT8231 southbridge.

Looking at VIA's website, everything after the EPIA, upto but not 
including the
new EPIA-SP have a CLE266 northbridge and a VT8235 southbridge. This 
would mean
that the code for the EPIA-M in LinuxBIOS should work for these motherboards.

The EPIA-SP is listed as having a CN400 northbridge and a VT8237 Southbrigde.

Unfortunately, I think the EPIA-M code is not working at the present, I don't
think it got updated after the major code changes a little while ago (Someone
please correct me if I'm wrong)

getting that code to compile would be your first step.

> According to the specs, the hardware itself is not that different from the
> M version. Seems not to be the case however.
>
> bye,
>  andreas

Regards
Mark Wilkinson.




From stepan at openbios.org  Tue Mar  1 01:57:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Tue Mar  1 01:57:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050301112223.19403.qmail@web30009.mail.mud.yahoo.com>
References: <20050301112223.19403.qmail@web30009.mail.mud.yahoo.com>
Message-ID: <20050301123159.GB27020@openbios.org>

* ramesh bios <ramesh_bios at yahoo.com> [050301 12:22]:
> Would I be able to test if Linux 2.6.10 is able to
> parse the normal BIOS' PIRQ table by booting linux
> with acpi=off? If it does work at that point, then I
> could assume that the area to be fixed would be the
> PIRQ table generation in LinuxBIOS. If not, then it'd
> be time to examine the kernel's pirq code.

Yes. Something along that line. For the one Geode system I had, I wrote
the interrupt configuration myself, avoiding to fiddle with kernel pirq
code (still needs a somewhat correct pirq table)
 
> I'm still somewhat confused though. At the point that
> LB calls the kernel, shoudn't LB have used the IRQ
> table values to set the PCI config space registers to
> write IRQ values to the PCI config registers and such?
> And if that were done, Linux would not need to parse a
> PIRQ table, yes?

LinuxBIOS does not do that, it provides the tables and requires the OS
to do so.




From smithbone at gmail.com  Tue Mar  1 04:32:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  1 04:32:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050301123159.GB27020@openbios.org>
References: <20050301112223.19403.qmail@web30009.mail.mud.yahoo.com>
	 <20050301123159.GB27020@openbios.org>
Message-ID: <8a0c367805030107075f5dbf28@mail.gmail.com>

> > And if that were done, Linux would not need to parse a
> > PIRQ table, yes?
> 
> LinuxBIOS does not do that, it provides the tables and requires the OS
> to do so.

I've found that Linux up to  2.6.9 (I haven't tested .10)  Dosen't do
this fully.  With my 440bx chipset there are config registers in the
northbridge that control which IRQ line each of the PCI PIRQ lines are
routed to.  Even with a proper PIRQ table these registers are not
setup and I get the same error reported.

I have code in my final_mainboard_fixup() that sets these registers
such that they match my table and then every thing works fine.

I suggest you diff the output of lspci -xxx for the northbridge
between linubios and factory bios and resolve all the differences with
the datasheet.

-- 
Richard A. Smith


From smithbone at gmail.com  Tue Mar  1 04:41:00 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  1 04:41:00 2005
Subject: new free software foundation crusade: http://www.fsf.org/campaigns/free-bios.html
In-Reply-To: <Pine.LNX.4.58.0502282209500.19122@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DC36@exchfive.olympus.f5net.com>
	 <Pine.LNX.4.58.0502282209500.19122@enigma.lanl.gov>
Message-ID: <8a0c3678050301071521aef753@mail.gmail.com>

> 
> I am hoping to get guys like Eric and Richard Smith to get accounts and
> add content!

I'm trying to but I can't seem to create an account.  I go to the
login or create page and I get login stuff but no option to create a
new account?

-- 
Richard A. Smith


From stuge-linuxbios at cdy.org  Tue Mar  1 04:43:01 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Tue Mar  1 04:43:01 2005
Subject: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.GSO.4.62.0503011030100.17857@bilbo.dd.chalmers.se>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com> <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu> <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <20050228233406.GA4506@foo.birdnet.se> <Pine.GSO.4.62.0503011030100.17857@bilbo.dd.chalmers.se>
Message-ID: <20050301151814.GD15145@foo.birdnet.se>

On Tue, Mar 01, 2005 at 10:36:35AM +0100, Peter Karlsson wrote:
> On Tue, 1 Mar 2005, Peter Stuge wrote:
> 
> >There are probably more sections that would be useful too.
> 
> Technical jargon? I'm still a bit confused about what payload is and 
> there's probably quite a few words/acronyms that are being used but
> it's hard to know exactly what they mean.

Right. These all go to "2.1. Basics and terms"..

I wrote a short summary which discusses payloads a little, perhaps it
can help clear things out;
http://www.clustermatic.org/pipermail/linuxbios/2005-January/010815.html

I'm going to add that to the wiki in a minute.


//Peter


From stuge-linuxbios at cdy.org  Tue Mar  1 05:05:01 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Tue Mar  1 05:05:01 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
Message-ID: <20050301154031.GE15145@foo.birdnet.se>

On Tue, Mar 01, 2005 at 12:44:23PM +0100, Peter Karlsson wrote:
> LinuxBIOS (initialises hardware) -> payload (etherboot,OpenBIOS,
> FILO etc.) (-> operating system)?

Exactly right. But with the right flash memory on the mainboard you
can use the operating system (Linux) as payload directly.


> Ok, but that was just an example. Technical jargon explanation is
> still needed to get into linuxbios. For instance:
> http://www.clustermatic.org/pipermail/linuxbios/2003-March/002240.html
> 
> This mail mentions SPD,VID,DID,I2C etc. Does everybody know what
> these mean? To get more people interested in linuxbios one has to
> lower the bars, and technical jargon is a major blocker (at least for
> me).

I'm not sure I agree that the bar must be lowered. Much of the
development going on in LinuxBIOS is _heavily_ technical and spans
across quite a few different architectures. It's not right or useful
to force developers to work and/or communicate below their
capabilities, and certainly not in an open source project. I would
hate it if someone tried to do that to me.

I do believe however, that all the technical prerequisite knowledge
should be listed, so that people can get up-to-speed on their own.
I'll try to work for this and I think that the wiki is a great forum.


> And yes, I do know what i2c is, and I think I know what spd is (ram
> speed?)

SPD is Serial Presence Detect, the name of an I2C bus between the
northbridge and all RAM modules. Each RAM module has an EEPROM with
more or less correct information about how memory initialization code
should set up the memory controller for correct size and optimal
performance. Quite frequently the information is busted. :(


> but vid & did does not ring a bell.

These are short for Vendor ID and Device ID. VID and DID (or PID,
Product ID) are id numbers assigned by organizations such as PCI-SIG
and USBIF to hardware manufacturers allowing software to identify
hardware in a reliable manner. The ids are stored inside the device,
whether it's PCI or USB. Also true for PCMCIA/CardBus.


//Peter


From rminnich at lanl.gov  Tue Mar  1 05:09:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 05:09:00 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050301071914.50670.qmail@web30008.mail.mud.yahoo.com>
References: <20050301071914.50670.qmail@web30008.mail.mud.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503010843160.20461@enigma.lanl.gov>


On Mon, 28 Feb 2005, ramesh bios wrote:

> That's odd. My understanding might be lacking. 
> 
> I think the PIRQ table parser in 2.6.10 seems to work
> because it works when I use the normal BIOS. 

no, it's messy. Some bioses set IRQ settings that don't agree with their 
own PIRQ tables. I've seen this in practice. So the fact that the normal 
BIOS has working IRQs means nothing. 

I'd like a URL for the Cox/Christer discussion :-)
ron


From rminnich at lanl.gov  Tue Mar  1 05:10:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 05:10:01 2005
Subject: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.GSO.4.62.0503011030100.17857@bilbo.dd.chalmers.se>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
 <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
 <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <20050228233406.GA4506@foo.birdnet.se>
 <Pine.GSO.4.62.0503011030100.17857@bilbo.dd.chalmers.se>
Message-ID: <Pine.LNX.4.58.0503010845090.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, Peter Karlsson wrote:

> On Tue, 1 Mar 2005, Peter Stuge wrote:
> 
> > There are probably more sections that would be useful too.
> 
> Technical jargon? I'm still a bit confused about what payload is and there's
> probably quite a few words/acronyms that are being used but it's hard to know
> exactly what they mean.
> 
> Best regards
> 

wiki contributors, here is a question; go for it!
ron


From rminnich at lanl.gov  Tue Mar  1 05:11:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 05:11:00 2005
Subject: new free software foundation crusade:	http://www.fsf.org/campaigns/free-bios.html
In-Reply-To: <20050301094558.zeurs4wccggwo8co@2pmtechnologies.com>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
 <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
 <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
 <Pine.LNX.4.58.0503010049250.3322@gate.bb.dicp.net>
 <Pine.LNX.4.58.0502281712350.18334@enigma.lanl.gov>
 <20050301094558.zeurs4wccggwo8co@2pmtechnologies.com>
Message-ID: <Pine.LNX.4.58.0503010845370.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005 mark.wilkinson at 2pmtech.com wrote:

> Andreas, which version of LB where you looking at ? People still seem to
> be getting on ok with V1 and the HOW-TO I wrote some time ago. Which
> version of the EPIA are you using, is it the original EPIA or one of the
> other version (ie EPIA-M, EPIA-MII etc) ? If it's the EPIA, I may be
> able to help.

V2 epia. V2 epia used to work, but does not currently. It locks up in ram 
init. 

My worry is that the code was fixed to use DRAM timings from SPD and the
infamous 8601 bugs have now caught up with us.

ron


From rminnich at lanl.gov  Tue Mar  1 05:12:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 05:12:01 2005
Subject: Porting Linuxbios to Via P4m266A
In-Reply-To: <Pine.GSO.4.62.0503011038200.17857@bilbo.dd.chalmers.se>
References: <E1D5zgk-0005b8-St@denali.ccs.neu.edu>
 <Pine.GSO.4.62.0503011038200.17857@bilbo.dd.chalmers.se>
Message-ID: <Pine.LNX.4.58.0503010846390.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, Peter Karlsson wrote:

> My current understanding of how linuxbios works is very limited but, is there
> an absolute requirement that this should occur over a serial port?

no. recall this is a just a hack to figure out what the bios is doing, not 
some permanent thing.

ron


From rminnich at lanl.gov  Tue Mar  1 05:16:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 05:16:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050301112223.19403.qmail@web30009.mail.mud.yahoo.com>
References: <20050301112223.19403.qmail@web30009.mail.mud.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503010849490.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, ramesh bios wrote:

> Would I be able to test if Linux 2.6.10 is able to
> parse the normal BIOS' PIRQ table by booting linux
> with acpi=off? 

no, the problem is that the BIOSes we have seen in some cases just assign 
a bunch of IRQs, and ignore their own tables. Hence, the problem gets 
harder.

> I'm still somewhat confused though. At the point that
> LB calls the kernel, shoudn't LB have used the IRQ
> table values to set the PCI config space registers to
> write IRQ values to the PCI config registers and such?

no, we have always let Linux do this because:
- for a given version of linux, you really don't know what tables it will 
   use, so it makes no sense to do a lot of work and then have linux 
   repeat it
- there are multiple options in some cases for which IRQ to use, and 
  again, you want to let the OS figure that out

ron


From rminnich at lanl.gov  Tue Mar  1 05:17:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 05:17:01 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
Message-ID: <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, Peter Karlsson wrote:

> To get more people interested in linuxbios one has to lower the bars, and
> technical jargon is a major blocker (at least for me). And yes, I do know what
> i2c is, and I think I know what spd is (ram speed?) but vid & did does not
> ring a bell. For anyone not knowing what i2c is I'll recommend:
> http://www.esacademy.com/faq/i2c/index.htm

so we need a glossary. Good point.

ron


From bchafy at ccs.neu.edu  Tue Mar  1 05:18:01 2005
From: bchafy at ccs.neu.edu (Bryan E. Chafy)
Date: Tue Mar  1 05:18:01 2005
Subject: Porting Linuxbios to Via P4m266A
In-Reply-To: <Pine.GSO.4.62.0503011038200.17857@bilbo.dd.chalmers.se> from "Peter Karlsson" at Mar 01, 2005 10:50:55 AM
Message-ID: <E1D69gi-0003nP-KQ@denali.ccs.neu.edu>

> My current understanding of how linuxbios works is very limited but, is 
> there an absolute requirement that this should occur over a serial port?
>

No,  however getting higher speed devices to work may require 
some amount of working memory, interrupts, etc 
(the parallel port might be ok however).
IMO, once memory is working (and interrupts enabled), much of
the hard work is done.


From rminnich at lanl.gov  Tue Mar  1 05:21:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 05:21:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <8a0c367805030107075f5dbf28@mail.gmail.com>
References: <20050301112223.19403.qmail@web30009.mail.mud.yahoo.com> 
 <20050301123159.GB27020@openbios.org> <8a0c367805030107075f5dbf28@mail.gmail.com>
Message-ID: <Pine.LNX.4.58.0503010855100.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, Richard Smith wrote:

> I've found that Linux up to 2.6.9 (I haven't tested .10)  Dosen't do
> this fully.  With my 440bx chipset there are config registers in the
> northbridge that control which IRQ line each of the PCI PIRQ lines are
> routed to.  Even with a proper PIRQ table these registers are not setup
> and I get the same error reported.

that's whacky. The old linux did fine with 440bx. I never had to do 
anything but set up PIRQ tables. 

> I suggest you diff the output of lspci -xxx for the northbridge between
> linubios and factory bios and resolve all the differences with the
> datasheet.

on the geode 2.4.18 always worked, and if I patched linux for later 
linuxes, that worked fine too. 

What a mess PIRQ got to be .... 

ron


From rminnich at lanl.gov  Tue Mar  1 05:47:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 05:47:01 2005
Subject: wiki.linuxbios.org
Message-ID: <Pine.LNX.4.58.0503010921500.20461@enigma.lanl.gov>

I have started to bring over content to the wiki. Those who have logins -- 
you can see my formatting is not that great in the FAQ, fixers welcome.

ron


From a.mimms at f5.com  Tue Mar  1 06:34:00 2005
From: a.mimms at f5.com (Alan Mimms)
Date: Tue Mar  1 06:34:00 2005
Subject: new free software foundation crusade: http://www.fsf.org/campaigns/free-bios.html
Message-ID: <7D7AEA925A7F724194B1521C75E622DC84DCA4@exchfive.olympus.f5net.com>

So would someone who DOES have an account please edit the login page to
put a mailto link there to allow users to at least know that the UI on
that page isn't as described in the error you get when you try to create
an account the way the page says to do so?  It's guaranteed to be an FAQ
which will bother everyone more than the time it would take to fix it on
the page.

Alan Mimms, Senior Architect
F5 Networks, Inc.  Spokane Development Center
Liberty Lake, Washington
v: 509-343-3524   f: 509-343-3501


-----Original Message-----
From: Ronald G. Minnich [mailto:rminnich at lanl.gov] 
Sent: Monday, February 28, 2005 9:13 PM
To: Alan Mimms
Cc: Andreas Thienemann; linuxbios at clustermatic.org
Subject: RE: new free software foundation crusade:
http://www.fsf.org/campaigns/free-bios.html



On Mon, 28 Feb 2005, Alan Mimms wrote:

> One problem tho: no form for creating usernames.  Was this
intentional?

yes. Creating users who can edit the pages is going to pass through
sysops 
so we don't have people randomly dropping in and trashing the pages.
Plan 
9 wiki had a terrible time with this until they locked things down.
Every 
once in a while all the Plan 9 wiki would end up with links to porn
sites. 

ron


From rminnich at lanl.gov  Tue Mar  1 06:37:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 06:37:00 2005
Subject: new free software foundation crusade: http://www.fsf.org/campaigns/free-bios.html
In-Reply-To: <7D7AEA925A7F724194B1521C75E622DC84DCA4@exchfive.olympus.f5net.com>
References: <7D7AEA925A7F724194B1521C75E622DC84DCA4@exchfive.olympus.f5net.com>
Message-ID: <Pine.LNX.4.58.0503011011170.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, Alan Mimms wrote:

> So would someone who DOES have an account please edit the login page to
> put a mailto link there to allow users to at least know that the UI on
> that page isn't as described in the error you get when you try to create
> an account the way the page says to do so?  It's guaranteed to be an FAQ
> which will bother everyone more than the time it would take to fix it on
> the page.
> 

Alan, you mean the thing on the upper right 'log in or create account'?

We'll get that done. 

Thanks for checking things out.

ron


From rminnich at lanl.gov  Tue Mar  1 06:50:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 06:50:00 2005
Subject: port guides
Message-ID: <Pine.LNX.4.58.0503011024310.20461@enigma.lanl.gov>

I've moved the three port guides over. Antony's is really good, but sadly 
is for v1. 

The EPIA one is good for V2.

ron


From smithbone at gmail.com  Tue Mar  1 06:52:00 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  1 06:52:00 2005
Subject: new free software foundation crusade: http://www.fsf.org/campaigns/free-bios.html
In-Reply-To: <Pine.LNX.4.58.0503011011170.20461@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DCA4@exchfive.olympus.f5net.com>
	 <Pine.LNX.4.58.0503011011170.20461@enigma.lanl.gov>
Message-ID: <8a0c3678050301092245e773@mail.gmail.com>

> > So would someone who DOES have an account please edit the login page to
> > put a mailto link there to allow users to at least know that the UI on
> > that page isn't as described in the error you get when you try to create
> > an account the way the page says to do so?  It's guaranteed to be an FAQ
> > which will bother everyone more than the time it would take to fix it on
> > the page.
> >

You might also note the the login is case sensitive.

-- 
Richard A. Smith


From ollie at lanl.gov  Tue Mar  1 06:55:01 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  1 06:55:01 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
	 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
	 <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov>
Message-ID: <1109698216.3049.4.camel@logarithm.lanl.gov>

On Tue, 2005-03-01 at 08:52, Ronald G. Minnich wrote:
> On Tue, 1 Mar 2005, Peter Karlsson wrote:
> 
> > To get more people interested in linuxbios one has to lower the bars, and
> > technical jargon is a major blocker (at least for me). And yes, I do know what
> > i2c is, and I think I know what spd is (ram speed?) but vid & did does not
> > ring a bell. For anyone not knowing what i2c is I'll recommend:
> > http://www.esacademy.com/faq/i2c/index.htm
> 
> so we need a glossary. Good point.
> 
> ron

Ron,

Probably we should seriously consider writing the "Users Manual" and
"Programmer's Manual" as I mentioned before?

Ollie




From rminnich at lanl.gov  Tue Mar  1 06:58:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 06:58:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <1109698216.3049.4.camel@logarithm.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> 
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> 
 <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov> <1109698216.3049.4.camel@logarithm.lanl.gov>
Message-ID: <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, Li-Ta Lo wrote:

> Probably we should seriously consider writing the "Users Manual" and
> "Programmer's Manual" as I mentioned before?

yes, it has to be done.

ron


From ollie at lanl.gov  Tue Mar  1 06:59:00 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  1 06:59:00 2005
Subject: new free software foundation
	crusade:http://www.fsf.org/campaigns/free-bios.html
In-Reply-To: <Pine.LNX.4.58.0502282227240.19122@enigma.lanl.gov>
References: <18c389818c3254.18c325418c3898@vsnl.net>
	 <Pine.LNX.4.58.0502282227240.19122@enigma.lanl.gov>
Message-ID: <1109698453.3049.7.camel@logarithm.lanl.gov>

On Mon, 2005-02-28 at 22:28, Ronald G. Minnich wrote:
> On Tue, 1 Mar 2005 sherlock at vsnl.com wrote:
> 
> > The names (type nos) of motherboards are very region dependent and
> > boards with same parts will have different nos depending on the region
> > and manufacturer. Why not add the chipset partnums to the motherboard
> > info on the Supported motherboard page. 
> 
> that actually doesn't help as much as you might think. I don't have a good 
> answer for this problem. But we can try to put the chipset names there. 
> 

Probably we should put a link to the vendor's web page for the
mainboard. If the vendor is doing something stupid with their
web page, we have no way to fix it.

Ollie

> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios



From ollie at lanl.gov  Tue Mar  1 06:59:03 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  1 06:59:03 2005
Subject: new free software foundation crusade:
	http://www.fsf.org/campaigns/free-bios.html
In-Reply-To: <8a0c3678050301092245e773@mail.gmail.com>
References: 	 <7D7AEA925A7F724194B1521C75E622DC84DCA4@exchfive.olympus.f5net.com>
	 <Pine.LNX.4.58.0503011011170.20461@enigma.lanl.gov>
	 <8a0c3678050301092245e773@mail.gmail.com>
Message-ID: <1109698485.3049.9.camel@logarithm.lanl.gov>

On Tue, 2005-03-01 at 10:22, Richard Smith wrote:
> > > So would someone who DOES have an account please edit the login page to
> > > put a mailto link there to allow users to at least know that the UI on
> > > that page isn't as described in the error you get when you try to create
> > > an account the way the page says to do so?  It's guaranteed to be an FAQ
> > > which will bother everyone more than the time it would take to fix it on
> > > the page.
> > >
> 
> You might also note the the login is case sensitive.

Do I have an account?

Ollie




From ollie at lanl.gov  Tue Mar  1 07:08:00 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  1 07:08:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
	 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
	 <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov>
	 <1109698216.3049.4.camel@logarithm.lanl.gov>
	 <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>
Message-ID: <1109699013.3049.22.camel@logarithm.lanl.gov>

On Tue, 2005-03-01 at 10:32, Ronald G. Minnich wrote:
> On Tue, 1 Mar 2005, Li-Ta Lo wrote:
> 
> > Probably we should seriously consider writing the "Users Manual" and
> > "Programmer's Manual" as I mentioned before?
> 
> yes, it has to be done.
> 
> ron

Ron,

Do I have to right to distribute my FREENIX '05 paper? If I can,
should I put it on the wiki?

Ollie




From rminnich at lanl.gov  Tue Mar  1 07:10:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 07:10:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <1109699013.3049.22.camel@logarithm.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> 
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> 
 <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov> 
 <1109698216.3049.4.camel@logarithm.lanl.gov>  <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>
 <1109699013.3049.22.camel@logarithm.lanl.gov>
Message-ID: <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, Li-Ta Lo wrote:

> Do I have to right to distribute my FREENIX '05 paper? If I can,
> should I put it on the wiki?

yes.

ron


From ollie at lanl.gov  Tue Mar  1 07:14:00 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  1 07:14:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
	 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
	 <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov>
	 <1109698216.3049.4.camel@logarithm.lanl.gov>
	 <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>
	 <1109699013.3049.22.camel@logarithm.lanl.gov>
	 <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov>
Message-ID: <1109699365.3049.26.camel@logarithm.lanl.gov>

On Tue, 2005-03-01 at 10:45, Ronald G. Minnich wrote:
> On Tue, 1 Mar 2005, Li-Ta Lo wrote:
> 
> > Do I have to right to distribute my FREENIX '05 paper? If I can,
> > should I put it on the wiki?
> 
> yes.
> 

even the copyright is assigned to USENIX.org?

Ollie
> ron



From rminnich at lanl.gov  Tue Mar  1 07:15:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 07:15:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <1109699365.3049.26.camel@logarithm.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> 
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> 
 <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov> 
 <1109698216.3049.4.camel@logarithm.lanl.gov>  <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>
  <1109699013.3049.22.camel@logarithm.lanl.gov>  <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov>
 <1109699365.3049.26.camel@logarithm.lanl.gov>
Message-ID: <Pine.LNX.4.58.0503011050190.20461@enigma.lanl.gov>


On Tue, 1 Mar 2005, Li-Ta Lo wrote:

> even the copyright is assigned to USENIX.org?

yes, AFAIK you can still post it. I post all my usenix pappers.

ron


From talbotx at comcast.net  Tue Mar  1 07:47:01 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Tue Mar  1 07:47:01 2005
Subject: Can any one ID this board?
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>  <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>  <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov>  <1109698216.3049.4.camel@logarithm.lanl.gov>  <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>  <1109699013.3049.22.camel@logarithm.lanl.gov>  <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov> <1109699365.3049.26.camel@logarithm.lanl.gov> <Pine.LNX.4.58.0503011050190.20461@enigma.lanl.gov>
Message-ID: <011901c51e8b$91816170$9901a8c0@newflame>

Well, I have been googling this board for the last 2 day's and have found
nothing.  Can any of your guys ID this board? Or perhaps point me in the
right direction.  I put the BIOS into my programer and grabed a copy of the
ROM, but that has given me no new information.  I am looking for the pin
outs, VGA, PS/2, network.  Any ideas?

http://www.etministries.com/webfolders/top.JPG
http://www.etministries.com/webfolders/bottom.JPG

-Adam




From rminnich at lanl.gov  Tue Mar  1 07:53:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 07:53:01 2005
Subject: Can any one ID this board?
In-Reply-To: <011901c51e8b$91816170$9901a8c0@newflame>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> 
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> 
 <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov> 
 <1109698216.3049.4.camel@logarithm.lanl.gov>  <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>
  <1109699013.3049.22.camel@logarithm.lanl.gov>  <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov>
 <1109699365.3049.26.camel@logarithm.lanl.gov> <Pine.LNX.4.58.0503011050190.20461@enigma.lanl.gov>
 <011901c51e8b$91816170$9901a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0503011127340.20461@enigma.lanl.gov>

don't know, but it sure looks like yer basic geode board to me.

ron



From lindahl at pathscale.com  Tue Mar  1 09:04:00 2005
From: lindahl at pathscale.com (Greg Lindahl)
Date: Tue Mar  1 09:04:00 2005
Subject: AMD Opteron D0 support
In-Reply-To: <2ea3fae10502231744dfa5c66@mail.gmail.com>
References: <2ea3fae10502231744dfa5c66@mail.gmail.com>
Message-ID: <20050301193843.GA1405@greglaptop.internal.keyresearch.com>

> Any one got D0 Opteron?

Actually it turns out that we have 6 of them -- what would you like to
know?

-- greg



From rminnich at lanl.gov  Tue Mar  1 11:39:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 11:39:00 2005
Subject: wiki.linuxbios.org
Message-ID: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>

This page is improving so quickly you almost need a video camera to watch 
it!

Thanks to all of you who have contributed today. It's just fantastic!

ron


From bari at onelabs.com  Tue Mar  1 12:03:00 2005
From: bari at onelabs.com (Bari Ari)
Date: Tue Mar  1 12:03:00 2005
Subject: wiki.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>
Message-ID: <4224EF75.6010801@onelabs.com>

What's the status on getting an account & password? Who do you have to know?

-Bari

Ronald G. Minnich wrote:

> This page is improving so quickly you almost need a video camera to watch 
> it!
> 
> Thanks to all of you who have contributed today. It's just fantastic!
> 
> ron
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
> 
> 
> 




From rminnich at lanl.gov  Tue Mar  1 12:11:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 12:11:00 2005
Subject: wiki.linuxbios.org
In-Reply-To: <4224EF75.6010801@onelabs.com>
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>
 <4224EF75.6010801@onelabs.com>
Message-ID: <Pine.LNX.4.58.0503011546190.20671@enigma.lanl.gov>


On Tue, 1 Mar 2005, Bari Ari wrote:

> What's the status on getting an account & password? Who do you have to know?
> 
> -Bari

me or stepan. You want one bari? 

ron
> 


From ollie at lanl.gov  Tue Mar  1 12:26:00 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  1 12:26:00 2005
Subject: wiki.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0503011546190.20671@enigma.lanl.gov>
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>
	 <4224EF75.6010801@onelabs.com>
	 <Pine.LNX.4.58.0503011546190.20671@enigma.lanl.gov>
Message-ID: <1109718097.3104.5.camel@logarithm.lanl.gov>

On Tue, 2005-03-01 at 15:46, Ronald G. Minnich wrote:
> On Tue, 1 Mar 2005, Bari Ari wrote:
> 
> > What's the status on getting an account & password? Who do you have to know?
> > 
> > -Bari
> 
> me or stepan. You want one bari? 
> 


Stephan,

How do I put a PDF file there? Or a hierachy of html files?

Ollie




From bgr at linespeed.net  Tue Mar  1 13:49:00 2005
From: bgr at linespeed.net (Brian G. Rhodes)
Date: Tue Mar  1 13:49:00 2005
Subject: VIA chips
Message-ID: <1109726228.32673.11.camel@manowar.linespeed.net>

Does anyone here happen to know if VIA works with smaller companies who
want to create reference designs using thier processors and bridge
chips?  Or only larger motherboard manufacturers.



From ramesh_bios at yahoo.com  Tue Mar  1 15:09:00 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Tue Mar  1 15:09:00 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: 6667
Message-ID: <20050302014353.89946.qmail@web30005.mail.mud.yahoo.com>

The URL for the Cox/Weinigel thread about PIRQ tables
on the geode gx1 is at:
http://lkml.org/lkml/2002/7/5/104

I'm doing a little bit more analysis of the problem
now. I've been looking at the following block of code
from 2.6.10's pci/irq.c. First of all, LB states this
during bootup:
---
Checking IRQ routing tables...
/bios/freebios/src/arch/i386/lib/pirq_routing.c:   
30:check_pirq_routing_table() - irq_routing_table
located at: 0x00008740
done.
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...failed
Wrote linuxbios table at: 00000500 - 00000664 
checksum f9fe
---
I'm not sure why the copy to 0xf0000 failed. That's
kinda odd but I'll live with it for now. Now, I put
some debug in the kernel code to see whether it found
the pirq table and I saw:

---
no pirq_table so calling pcibios_get_irq_routing_table
pirq_table=00000000
---

coming from pcibios_irq_init. So based on the code
appended below, I believe that the kernel isn't
finding the pirq table. And I think this is because
the kernel's pirq_find_routing_table function only
looks from __va(0xf0000) to __va(0x100000) whereas LB
puts it at 0000500. The second attempt that the kernel
makes to get the PIRQ table is with
pcibios_get_irq_routing_table and that fails too. I
need to look at that, but first I think I'll look into
why the copy to f0000 fails. In the meantime, any
advice?

---
static int __init pcibios_irq_init(void)
{
        DBG("PCI: IRQ init\n");

        if (pcibios_enable_irq || raw_pci_ops == NULL)
                return 0;

        dmi_check_system(pciirq_dmi_table);

        pirq_table = pirq_find_routing_table();

#ifdef CONFIG_PCI_BIOS
        if (!pirq_table && (pci_probe &
PCI_BIOS_IRQ_SCAN)) {
                printk(KERN_WARNING "no pirq_table so
calling pcibios_get\n");
                pirq_table =
pcibios_get_irq_routing_table();
                printk(KERN_WARNING
"pirq_table=%p\n",pirq_table);
        }
#endif
        if (pirq_table) {
                printk(KERN_WARNING "had
pirq_table\n");
                pirq_peer_trick();
                pirq_find_router(&pirq_router);
                if (pirq_table->exclusive_irqs) {
                        int i;
                        for (i=0; i<16; i++)
                                if
(!(pirq_table->exclusive_irqs & (1 << i)))
                                       
pirq_penalty[i] += 100;
                }
                /* If we're using the I/O APIC, avoid
using the PCI IRQ routing table */
                if (io_apic_assign_pci_irqs) {
                        printk(KERN_WARNING "using
io_apic to assign irqs\n");
                        pirq_table = NULL;
                }
        }

        pcibios_enable_irq = pirq_enable_irq;

        pcibios_fixup_irqs();
        return 0;
}
---




--- "Ronald G. Minnich" <rminnich at lanl.gov> wrote:
> 
> 
> On Tue, 1 Mar 2005, Richard Smith wrote:
> 
> > I've found that Linux up to 2.6.9 (I haven't
> tested .10)  Dosen't do
> > this fully.  With my 440bx chipset there are
> config registers in the
> > northbridge that control which IRQ line each of
> the PCI PIRQ lines are
> > routed to.  Even with a proper PIRQ table these
> registers are not setup
> > and I get the same error reported.
> 
> that's whacky. The old linux did fine with 440bx. I
> never had to do 
> anything but set up PIRQ tables. 
> 
> > I suggest you diff the output of lspci -xxx for
> the northbridge between
> > linubios and factory bios and resolve all the
> differences with the
> > datasheet.
> 
> on the geode 2.4.18 always worked, and if I patched
> linux for later 
> linuxes, that worked fine too. 
> 
> What a mess PIRQ got to be .... 
> 
> ron
> 

__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 


From talbotx at comcast.net  Tue Mar  1 15:53:01 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Tue Mar  1 15:53:01 2005
Subject: wiki.linuxbios.org update
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>
Message-ID: <015e01c51ecf$7dfa33e0$9901a8c0@newflame>

-Ron
Love the new page. As I do not have edit permissions, but would like to
help, here is the specs for the Via board's to put under your "(Unfinished
re-organization: Supported Motherboards)" section. You may need to do a
little formatting, but they should be for the most part, copy and paste.
Also more then willing to write the tutorial for the epia-mII, and the
sample configs.  If you would be so kind as to fix via south bridge stuff.
-Adam

    a.. Via EPIA
    b.. Spec: Via C3/EDEN CPU, up to 1GB PC133, LAN, IDE, Video
    c.. Chipset(s): PLE133,  VT8231
    d.. Location in source tree: /targets/via/epia
    e.. Status: Supported
      a.. Working perpherials: (???)
      b.. Known broken perpherials: (???)
      c.. Diffrences between revisions: (???)
        a.. (Working/known broken perpherials (per revision))
    f.. Sample configuration(s): (???)
    g.. Motherboard specific configuration items: (???)
    h.. Build tutorial:
    i..

    a.. Via EPIA-M
    a.. Spec: Via C3/EDEN CPU, up to 1GB DDR266, LAN, IDE, Video
    b.. Chipset(s): CLE266, VT8235
    c.. Location in source tree: /targets/via/epia-m
    d.. Status: Supported
      a.. Working perpherials: (???)
      b.. Known broken perpherials: (???)
      c.. Diffrences between revisions: (???)
        a.. (Working/known broken perpherials (per revision))
    e.. Sample configuration(s): (???)
    f.. Motherboard specific configuration items: (???)
    g.. Build tutorial:

    a.. Via EPIA-MII
    b.. Spec: Via C3/EDEN CPU, up to 1GB DDR266, LAN, IDE, PCMCIA, CF, Video
    c.. Chipset(s):CLE266, VT8235
    d.. Location in source tree: /targets/via/epia-mii
    e.. Status: Supported
      a.. Working perpherials: (PCMCIA, CF)
      b.. Known broken perpherials: (???)
      c.. Diffrences between revisions: (???)
        a.. (Working/known broken perpherials (per revision))
    f.. Sample configuration(s): (???)
    g.. Motherboard specific configuration items: (???)
    h.. Build tutorial:




From gnif at spacevs.com  Tue Mar  1 15:56:01 2005
From: gnif at spacevs.com (Geoffrey McRae)
Date: Tue Mar  1 15:56:01 2005
Subject: Can any one ID this board?
In-Reply-To: <Pine.LNX.4.58.0503011127340.20461@enigma.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> 
    <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> 
    <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov> 
    <1109698216.3049.4.camel@logarithm.lanl.gov> 
    <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov> 
    <1109699013.3049.22.camel@logarithm.lanl.gov> 
    <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov>
    <1109699365.3049.26.camel@logarithm.lanl.gov>
    <Pine.LNX.4.58.0503011050190.20461@enigma.lanl.gov>
    <011901c51e8b$91816170$9901a8c0@newflame>
    <Pine.LNX.4.58.0503011127340.20461@enigma.lanl.gov>
Message-ID: <38818.165.12.252.12.1109730651.squirrel@webmail.spacevs.com>

Does anybody know of a source for these in Australia, I would love to get
my hands on one or two to play with

Geoff

> don't know, but it sure looks like yer basic geode board to me.
>
> ron
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>




From talbotx at comcast.net  Tue Mar  1 15:57:00 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Tue Mar  1 15:57:00 2005
Subject: Can any one ID this board?
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>     <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>     <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov>     <1109698216.3049.4.camel@logarithm.lanl.gov>     <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>     <1109699013.3049.22.camel@logarithm.lanl.gov>     <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov>    <1109699365.3049.26.camel@logarithm.lanl.gov>    <Pine.LNX.4.58.0503011050190.20461@enigma.lanl.gov>    <011901c51e8b$91816170$9901a8c0@newflame>    <Pine.LNX.4.58.0503011127340.20461@enigma.lanl.gov> <38818.165.12.252.12.1109730651.squirrel@webmail.spacevs.com>
Message-ID: <016401c51ed0$177a5090$9901a8c0@newflame>

don't no of a source, or even who makes that board.

----- Original Message ----- 
From: "Geoffrey McRae" <gnif at spacevs.com>
To: "Ronald G. Minnich" <rminnich at lanl.gov>
Cc: "Adam Talbot" <talbotx at comcast.net>; <linuxbios at clustermatic.org>
Sent: Tuesday, March 01, 2005 6:30 PM
Subject: Re: Can any one ID this board?


> Does anybody know of a source for these in Australia, I would love to get
> my hands on one or two to play with
> 
> Geoff
> 
> > don't know, but it sure looks like yer basic geode board to me.
> >
> > ron
> >
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
> 
> 
> 



From jdarby at powercom.net  Tue Mar  1 15:58:00 2005
From: jdarby at powercom.net (Justin C. Darby)
Date: Tue Mar  1 15:58:00 2005
Subject: wiki.linuxbios.org update
In-Reply-To: <015e01c51ecf$7dfa33e0$9901a8c0@newflame>
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov> <015e01c51ecf$7dfa33e0$9901a8c0@newflame>
Message-ID: <42252671.40900@powercom.net>

This is beautiful. I'll add it right away.

Justin

Adam Talbot wrote:

>-Ron
>Love the new page. As I do not have edit permissions, but would like to
>help, here is the specs for the Via board's to put under your "(Unfinished
>re-organization: Supported Motherboards)" section. You may need to do a
>little formatting, but they should be for the most part, copy and paste.
>Also more then willing to write the tutorial for the epia-mII, and the
>sample configs.  If you would be so kind as to fix via south bridge stuff.
>-Adam
>
>    a.. Via EPIA
>    b.. Spec: Via C3/EDEN CPU, up to 1GB PC133, LAN, IDE, Video
>    c.. Chipset(s): PLE133,  VT8231
>    d.. Location in source tree: /targets/via/epia
>    e.. Status: Supported
>      a.. Working perpherials: (???)
>      b.. Known broken perpherials: (???)
>      c.. Diffrences between revisions: (???)
>        a.. (Working/known broken perpherials (per revision))
>    f.. Sample configuration(s): (???)
>    g.. Motherboard specific configuration items: (???)
>    h.. Build tutorial:
>    i..
>
>    a.. Via EPIA-M
>    a.. Spec: Via C3/EDEN CPU, up to 1GB DDR266, LAN, IDE, Video
>    b.. Chipset(s): CLE266, VT8235
>    c.. Location in source tree: /targets/via/epia-m
>    d.. Status: Supported
>      a.. Working perpherials: (???)
>      b.. Known broken perpherials: (???)
>      c.. Diffrences between revisions: (???)
>        a.. (Working/known broken perpherials (per revision))
>    e.. Sample configuration(s): (???)
>    f.. Motherboard specific configuration items: (???)
>    g.. Build tutorial:
>
>    a.. Via EPIA-MII
>    b.. Spec: Via C3/EDEN CPU, up to 1GB DDR266, LAN, IDE, PCMCIA, CF, Video
>    c.. Chipset(s):CLE266, VT8235
>    d.. Location in source tree: /targets/via/epia-mii
>    e.. Status: Supported
>      a.. Working perpherials: (PCMCIA, CF)
>      b.. Known broken perpherials: (???)
>      c.. Diffrences between revisions: (???)
>        a.. (Working/known broken perpherials (per revision))
>    f.. Sample configuration(s): (???)
>    g.. Motherboard specific configuration items: (???)
>    h.. Build tutorial:
>
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
>  
>



From talbotx at comcast.net  Tue Mar  1 15:59:00 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Tue Mar  1 15:59:00 2005
Subject: wiki.linuxbios.org update
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov> <015e01c51ecf$7dfa33e0$9901a8c0@newflame> <42252671.40900@powercom.net>
Message-ID: <016e01c51ed0$597b2280$9901a8c0@newflame>

Thank you Justin
-Adam
----- Original Message ----- 
From: "Justin C. Darby" <jdarby at powercom.net>
To: "Adam Talbot" <talbotx at comcast.net>
Cc: "Ronald G. Minnich" <rminnich at lanl.gov>; <linuxbios at clustermatic.org>
Sent: Tuesday, March 01, 2005 6:35 PM
Subject: Re: wiki.linuxbios.org update


> This is beautiful. I'll add it right away.
>
> Justin
>
> Adam Talbot wrote:
>
> >-Ron
> >Love the new page. As I do not have edit permissions, but would like to
> >help, here is the specs for the Via board's to put under your
"(Unfinished
> >re-organization: Supported Motherboards)" section. You may need to do a
> >little formatting, but they should be for the most part, copy and paste.
> >Also more then willing to write the tutorial for the epia-mII, and the
> >sample configs.  If you would be so kind as to fix via south bridge
stuff.
> >-Adam
> >
> >    a.. Via EPIA
> >    b.. Spec: Via C3/EDEN CPU, up to 1GB PC133, LAN, IDE, Video
> >    c.. Chipset(s): PLE133,  VT8231
> >    d.. Location in source tree: /targets/via/epia
> >    e.. Status: Supported
> >      a.. Working perpherials: (???)
> >      b.. Known broken perpherials: (???)
> >      c.. Diffrences between revisions: (???)
> >        a.. (Working/known broken perpherials (per revision))
> >    f.. Sample configuration(s): (???)
> >    g.. Motherboard specific configuration items: (???)
> >    h.. Build tutorial:
> >    i..
> >
> >    a.. Via EPIA-M
> >    a.. Spec: Via C3/EDEN CPU, up to 1GB DDR266, LAN, IDE, Video
> >    b.. Chipset(s): CLE266, VT8235
> >    c.. Location in source tree: /targets/via/epia-m
> >    d.. Status: Supported
> >      a.. Working perpherials: (???)
> >      b.. Known broken perpherials: (???)
> >      c.. Diffrences between revisions: (???)
> >        a.. (Working/known broken perpherials (per revision))
> >    e.. Sample configuration(s): (???)
> >    f.. Motherboard specific configuration items: (???)
> >    g.. Build tutorial:
> >
> >    a.. Via EPIA-MII
> >    b.. Spec: Via C3/EDEN CPU, up to 1GB DDR266, LAN, IDE, PCMCIA, CF,
Video
> >    c.. Chipset(s):CLE266, VT8235
> >    d.. Location in source tree: /targets/via/epia-mii
> >    e.. Status: Supported
> >      a.. Working perpherials: (PCMCIA, CF)
> >      b.. Known broken perpherials: (???)
> >      c.. Diffrences between revisions: (???)
> >        a.. (Working/known broken perpherials (per revision))
> >    f.. Sample configuration(s): (???)
> >    g.. Motherboard specific configuration items: (???)
> >    h.. Build tutorial:
> >
> >
> >_______________________________________________
> >Linuxbios mailing list
> >Linuxbios at clustermatic.org
> >http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
> >
>
>




From jdarby at powercom.net  Tue Mar  1 16:00:01 2005
From: jdarby at powercom.net (Justin C. Darby)
Date: Tue Mar  1 16:00:01 2005
Subject: wiki.linuxbios.org
In-Reply-To: <1109718097.3104.5.camel@logarithm.lanl.gov>
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>	 <4224EF75.6010801@onelabs.com>	 <Pine.LNX.4.58.0503011546190.20671@enigma.lanl.gov> <1109718097.3104.5.camel@logarithm.lanl.gov>
Message-ID: <422526E9.40201@powercom.net>

I will be establishing web storage space for files (originally for 
myself, but I can make it available to others). If you need space, I'm 
going to configure websites like:

http://linuxbios-wiki-resource.windex.org/<username>/

that are intended for use by wiki maintainers to publish binaries, PDF 
files, and the like.

It will likely only be available via SCP, so using 'scp' or FileZilla 
would be required.

If you want an account, please let me know your wiki userid (so I can 
keep track of who is who), and I'll shoot you back a password/login 
information. You of course will need to agree not to abuse my DS3 
connected personal machine for non-linuxbios related purpose. :)

If anyone wants to CNAME me a record off of linuxbios.org, I'll be happy 
to set it up to maintain consistancy. Maintaining FTP space is a lot of 
work, so I'll be happy to do it for anyone with edit access and provide 
access to anyone who wants it for mirrors. The machine already has some 
"general public" type user accounts and is without incident (so far).

Justin

Li-Ta Lo wrote:

>On Tue, 2005-03-01 at 15:46, Ronald G. Minnich wrote:
>  
>
>>On Tue, 1 Mar 2005, Bari Ari wrote:
>>
>>    
>>
>>>What's the status on getting an account & password? Who do you have to know?
>>>
>>>-Bari
>>>      
>>>
>>me or stepan. You want one bari? 
>>
>>    
>>
>
>
>Stephan,
>
>How do I put a PDF file there? Or a hierachy of html files?
>
>Ollie
>
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
>  
>



From gnif at spacevs.com  Tue Mar  1 16:04:00 2005
From: gnif at spacevs.com (Geoffrey McRae)
Date: Tue Mar  1 16:04:00 2005
Subject: Can any one ID this board?
In-Reply-To: <016401c51ed0$177a5090$9901a8c0@newflame>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>    
    <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>    
    <Pine.LNX.4.58.0503010851550.20461@enigma.lanl.gov>    
    <1109698216.3049.4.camel@logarithm.lanl.gov>    
    <Pine.LNX.4.58.0503011032350.20461@enigma.lanl.gov>    
    <1109699013.3049.22.camel@logarithm.lanl.gov>    
    <Pine.LNX.4.58.0503011045220.20461@enigma.lanl.gov>   
    <1109699365.3049.26.camel@logarithm.lanl.gov>   
    <Pine.LNX.4.58.0503011050190.20461@enigma.lanl.gov>   
    <011901c51e8b$91816170$9901a8c0@newflame>   
    <Pine.LNX.4.58.0503011127340.20461@enigma.lanl.gov>
    <38818.165.12.252.12.1109730651.squirrel@webmail.spacevs.com>
    <016401c51ed0$177a5090$9901a8c0@newflame>
Message-ID: <60036.165.12.252.12.1109731124.squirrel@webmail.spacevs.com>

I am not worried if its not "That" board, just any embedded board that
would be good for an experimenter like myself.

> don't no of a source, or even who makes that board.
>
> ----- Original Message -----
> From: "Geoffrey McRae" <gnif at spacevs.com>
> To: "Ronald G. Minnich" <rminnich at lanl.gov>
> Cc: "Adam Talbot" <talbotx at comcast.net>; <linuxbios at clustermatic.org>
> Sent: Tuesday, March 01, 2005 6:30 PM
> Subject: Re: Can any one ID this board?
>
>
>> Does anybody know of a source for these in Australia, I would love to
>> get
>> my hands on one or two to play with
>>
>> Geoff
>>
>> > don't know, but it sure looks like yer basic geode board to me.
>> >
>> > ron
>> >
>> > _______________________________________________
>> > Linuxbios mailing list
>> > Linuxbios at clustermatic.org
>> > http://www.clustermatic.org/mailman/listinfo/linuxbios
>> >
>>
>>
>>
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>




From ramesh_bios at yahoo.com  Tue Mar  1 16:06:01 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Tue Mar  1 16:06:01 2005
Subject: Can any one ID this board?
In-Reply-To: 6667
Message-ID: <20050302024057.27967.qmail@web30007.mail.mud.yahoo.com>

Hey Adam,

I think it's a typical geode gx1 board as well.

I'm no expert. But here are my guesses. VGA is
typically 16 pins. LPT is typically on a 26 pin
header. Serial ports typically on 10 pin headers.
Keyboard/Mouse typically on one 6 pin header. I think
I see parallel port at the horizontal 26 pin header at
the bottom right of your top pic. The horizontal
header at the top left looks like a 44 pin IDE header.
One thing that you could do is get the MAC address of
the ethernet and that might give you an idea of who
owns that block of MAC addresses. So long as it's not
RealTek, of course. I don't know what the long
vertical connector, my eyesight's failing me but it
looks like a 50 pin header in which case it'd be a
breakout connector of the kind that advantech uses. In
which case you'd have to find the datasheet.


--- Adam Talbot <talbotx at comcast.net> wrote:
> Well, I have been googling this board for the last 2
> day's and have found
> nothing.  Can any of your guys ID this board? Or
> perhaps point me in the
> right direction.  I put the BIOS into my programer
> and grabed a copy of the
> ROM, but that has given me no new information.  I am
> looking for the pin
> outs, VGA, PS/2, network.  Any ideas?
> 
> http://www.etministries.com/webfolders/top.JPG
> http://www.etministries.com/webfolders/bottom.JPG
> 
> -Adam
> 
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> 

__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 


From ramesh_bios at yahoo.com  Tue Mar  1 16:25:00 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Tue Mar  1 16:25:00 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050302014353.89946.qmail@web30005.mail.mud.yahoo.com>
Message-ID: <20050302030006.41016.qmail@web30002.mail.mud.yahoo.com>

Strike that. The issue is somewhere with
copy_pirq_routing_table. IE: why does the copy to
f0000 fail. I had assumed that the 500 address was an
alternate location that the table was copied to. So
now, I'm looking at that f000 failure.

--- ramesh bios <ramesh_bios at yahoo.com> wrote:

> The URL for the Cox/Weinigel thread about PIRQ
> tables
> on the geode gx1 is at:
> http://lkml.org/lkml/2002/7/5/104
> 
> I'm doing a little bit more analysis of the problem
> now. I've been looking at the following block of
> code
> from 2.6.10's pci/irq.c. First of all, LB states
> this
> during bootup:
> ---
> Checking IRQ routing tables...
> /bios/freebios/src/arch/i386/lib/pirq_routing.c:   
> 30:check_pirq_routing_table() - irq_routing_table
> located at: 0x00008740
> done.
> Copying IRQ routing tables to 0xf0000...done.
> Verifing priq routing tables copy at
> 0xf0000...failed
> Wrote linuxbios table at: 00000500 - 00000664 
> checksum f9fe
> ---
> I'm not sure why the copy to 0xf0000 failed. That's
> kinda odd but I'll live with it for now. Now, I put
> some debug in the kernel code to see whether it
> found
> the pirq table and I saw:
> 
> ---
> no pirq_table so calling
> pcibios_get_irq_routing_table
> pirq_table=00000000
> ---
> 
> coming from pcibios_irq_init. So based on the code
> appended below, I believe that the kernel isn't
> finding the pirq table. And I think this is because
> the kernel's pirq_find_routing_table function only
> looks from __va(0xf0000) to __va(0x100000) whereas
> LB
> puts it at 0000500. The second attempt that the
> kernel
> makes to get the PIRQ table is with
> pcibios_get_irq_routing_table and that fails too. I
> need to look at that, but first I think I'll look
> into
> why the copy to f0000 fails. In the meantime, any
> advice?
> 
> ---
> static int __init pcibios_irq_init(void)
> {
>         DBG("PCI: IRQ init\n");
> 
>         if (pcibios_enable_irq || raw_pci_ops ==
> NULL)
>                 return 0;
> 
>         dmi_check_system(pciirq_dmi_table);
> 
>         pirq_table = pirq_find_routing_table();
> 
> #ifdef CONFIG_PCI_BIOS
>         if (!pirq_table && (pci_probe &
> PCI_BIOS_IRQ_SCAN)) {
>                 printk(KERN_WARNING "no pirq_table
> so
> calling pcibios_get\n");
>                 pirq_table =
> pcibios_get_irq_routing_table();
>                 printk(KERN_WARNING
> "pirq_table=%p\n",pirq_table);
>         }
> #endif
>         if (pirq_table) {
>                 printk(KERN_WARNING "had
> pirq_table\n");
>                 pirq_peer_trick();
>                 pirq_find_router(&pirq_router);
>                 if (pirq_table->exclusive_irqs) {
>                         int i;
>                         for (i=0; i<16; i++)
>                                 if
> (!(pirq_table->exclusive_irqs & (1 << i)))
>                                        
> pirq_penalty[i] += 100;
>                 }
>                 /* If we're using the I/O APIC,
> avoid
> using the PCI IRQ routing table */
>                 if (io_apic_assign_pci_irqs) {
>                         printk(KERN_WARNING "using
> io_apic to assign irqs\n");
>                         pirq_table = NULL;
>                 }
>         }
> 
>         pcibios_enable_irq = pirq_enable_irq;
> 
>         pcibios_fixup_irqs();
>         return 0;
> }
> ---
> 
> 
> 
> 
> --- "Ronald G. Minnich" <rminnich at lanl.gov> wrote:
> > 
> > 
> > On Tue, 1 Mar 2005, Richard Smith wrote:
> > 
> > > I've found that Linux up to 2.6.9 (I haven't
> > tested .10)  Dosen't do
> > > this fully.  With my 440bx chipset there are
> > config registers in the
> > > northbridge that control which IRQ line each of
> > the PCI PIRQ lines are
> > > routed to.  Even with a proper PIRQ table these
> > registers are not setup
> > > and I get the same error reported.
> > 
> > that's whacky. The old linux did fine with 440bx.
> I
> > never had to do 
> > anything but set up PIRQ tables. 
> > 
> > > I suggest you diff the output of lspci -xxx for
> > the northbridge between
> > > linubios and factory bios and resolve all the
> > differences with the
> > > datasheet.
> > 
> > on the geode 2.4.18 always worked, and if I
> patched
> > linux for later 
> > linuxes, that worked fine too. 
> > 
> > What a mess PIRQ got to be .... 
> > 
> > ron
> > 
> 
> __________________________________________________
> Do You Yahoo!?
> Tired of spam?  Yahoo! Mail has the best spam
> protection around 
> http://mail.yahoo.com 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> 



		
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Yahoo! Sports - Sign up for Fantasy Baseball. 
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From rminnich at lanl.gov  Tue Mar  1 16:27:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 16:27:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050302014353.89946.qmail@web30005.mail.mud.yahoo.com>
References: <20050302014353.89946.qmail@web30005.mail.mud.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503012000120.21241@enigma.lanl.gov>


On Tue, 1 Mar 2005, ramesh bios wrote:

> ---
> Checking IRQ routing tables...
> /bios/freebios/src/arch/i386/lib/pirq_routing.c:   
> 30:check_pirq_routing_table() - irq_routing_table
> located at: 0x00008740
> done.
> Copying IRQ routing tables to 0xf0000...done.
> Verifing priq routing tables copy at 0xf0000...failed


!#@$!#@$!$@#!@

Can you make it so the payload is NOT compressed? 

ron


From rminnich at lanl.gov  Tue Mar  1 16:27:03 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 16:27:03 2005
Subject: wiki.linuxbios.org update
In-Reply-To: <016e01c51ed0$597b2280$9901a8c0@newflame>
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>
 <015e01c51ecf$7dfa33e0$9901a8c0@newflame> <42252671.40900@powercom.net>
 <016e01c51ed0$597b2280$9901a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0503012002080.21241@enigma.lanl.gov>

Yes, Justin Darby did a GREAT job of fixing up the FAQ, btw.

ron



From rminnich at lanl.gov  Tue Mar  1 16:29:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  1 16:29:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050302030006.41016.qmail@web30002.mail.mud.yahoo.com>
References: <20050302030006.41016.qmail@web30002.mail.mud.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503012003300.21241@enigma.lanl.gov>


On Tue, 1 Mar 2005, ramesh bios wrote:

> Strike that. The issue is somewhere with
> copy_pirq_routing_table. IE: why does the copy to
> f0000 fail. I had assumed that the 500 address was an
> alternate location that the table was copied to. So
> now, I'm looking at that f000 failure.


the copy to f0000 fails because shadow ram is not set up. 

You can fix this one of two ways. One is to figure out how to enable 
shadow ram. The second is to make the payload uncompressed. The copy will 
still fail but linux will find the PIRQ table anyway.

ron


From ramesh_bios at yahoo.com  Tue Mar  1 17:28:00 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Tue Mar  1 17:28:00 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: 6667
Message-ID: <20050302040242.67734.qmail@web30006.mail.mud.yahoo.com>

1. Shadow RAM

I guess I would need to find a way to tell the
northbridge to enable shadow RAM for some range around
f0000. I looked through the CS5530A datasheet and see
shadow registers but no mention of shadowing RAM. Nor
in the GX1 datasheet either. I'm looking for some
register in either the GX1 or the CS5530A that would
enable this. I am looking for some register that would
enable me to remap the C0000-F0000 address range to
somewhere in sdram. Is that the right thing to be
looking for?

2. Uncompressed payload
I'm not sure I understand what this means. Right now,
my payload is filo. In the build, I see:

dd conv=sync bs=196608 if=/bios/filo-0.4.2/filo.elf
of=payload.block
cat payload.block > romimage

Oh, I guess you must mean this stuff:

objcopy -O binary linuxbios_c linuxbios_payload.bin
./nrv2b e linuxbios_payload.bin
linuxbios_payload.nrv2b

So I guess there is some kind of compression going on
there. 

Which method would be the right thing to do? I'll look
at the shadow ram thing first then.

Thanks.


--- "Ronald G. Minnich" <rminnich at lanl.gov> wrote:
> 
> 
> On Tue, 1 Mar 2005, ramesh bios wrote:
> 
> > Strike that. The issue is somewhere with
> > copy_pirq_routing_table. IE: why does the copy to
> > f0000 fail. I had assumed that the 500 address was
> an
> > alternate location that the table was copied to.
> So
> > now, I'm looking at that f000 failure.
> 
> 
> the copy to f0000 fails because shadow ram is not
> set up. 
> 
> You can fix this one of two ways. One is to figure
> out how to enable 
> shadow ram. The second is to make the payload
> uncompressed. The copy will 
> still fail but linux will find the PIRQ table
> anyway.
> 
> ron
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


		
__________________________________ 
Do you Yahoo!? 
Yahoo! Mail - 250MB free storage. Do more. Manage less. 
http://info.mail.yahoo.com/mail_250


From sherlock at vsnl.com  Tue Mar  1 17:40:01 2005
From: sherlock at vsnl.com (sherlock at vsnl.com)
Date: Tue Mar  1 17:40:01 2005
Subject: new free software
 foundationcrusade:http://www.fsf.org/campaigns/free-bios.html
Message-ID: <19c916919c9213.19c921319c9169@vsnl.net>

On Tuesday 01 March 2005 23:04, Li-Ta Lo wrote:
> On Mon, 2005-02-28 at 22:28, Ronald G. Minnich wrote:
> > On Tue, 1 Mar 2005 sherlock at vsnl.com wrote:
> > > The names (type nos) of motherboards are very region dependent
> > > and boards with same parts will have different nos depending on

> > that actually doesn't help as much as you might think. I don't
> > have a good answer for this problem. But we can try to put the
> > chipset names there.
>
> Probably we should put a link to the vendor's web page for the
> mainboard. If the vendor is doing something stupid with their
> web page, we have no way to fix it.

Actually it will help. I have 2 kobian (P4M266a and P4M266v) boards 
using different sound chips and one with capability to boot from s
mart card (whatever that is). 
Inetrchanging the bios produced the additional boot capability. 
Everthing worked fine even under windose (which afaik uses the 
bios during runtime). Also buying boards might be a little easier.
And in any case it would not hurt. 

rgds
jtd



From sherlock at vsnl.com  Tue Mar  1 18:29:01 2005
From: sherlock at vsnl.com (sherlock at vsnl.com)
Date: Tue Mar  1 18:29:01 2005
Subject: Porting Linuxbios to Via P4m266A
Message-ID: <19d908119dbe65.19dbe6519d9081@vsnl.net>

Hi all,
Just recieved the spec sheet for ProSavageDDR P4M266 VT8751 P4 DDR 
SMA North Bridge.
Bad news is that I am not supposed to disclose it without permission 
(as per the Copyright notice). At this point I have recieved the 
manual without any NDA although the manual says "Confidential NDA 
Required".
I have written back asking for permission to disclose the contents 
without NDA. I have pointed out the benefits they are going to derive. 
Let's see how it goes.
I have a feeling that they may allow disclosure without NDA.

rgds
jtd



From stepan at openbios.org  Tue Mar  1 21:33:02 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Tue Mar  1 21:33:02 2005
Subject: Porting Linuxbios to Via P4m266A
In-Reply-To: <19d908119dbe65.19dbe6519d9081@vsnl.net>
References: <19d908119dbe65.19dbe6519d9081@vsnl.net>
Message-ID: <20050302080833.GD14054@openbios.org>

* sherlock at vsnl.com <sherlock at vsnl.com> [050302 06:03]:
> I have written back asking for permission to disclose the contents 
> without NDA. I have pointed out the benefits they are going to derive. 
> Let's see how it goes.
> I have a feeling that they may allow disclosure without NDA.

Many vendors accept releasing the code produced after reading such specs
while they don't allow the specs themselfes to be revealed.
Also, you can offer them to review the code before releasing it.

Stefan




From sherlock at vsnl.com  Tue Mar  1 22:01:01 2005
From: sherlock at vsnl.com (sherlock at vsnl.com)
Date: Tue Mar  1 22:01:01 2005
Subject: Porting Linuxbios to Via P4m266A
Message-ID: <1a321b71a33e68.1a33e681a321b7@vsnl.net>

On Wednesday 02 March 2005 13:38, Stefan Reinauer wrote:
> * sherlock at vsnl.com <sherlock at vsnl.com> [050302 06:03]:
> > I have written back asking for permission to disclose the
> > contents without NDA. I have pointed out the benefits they are
> > going to derive. Let's see how it goes.
> > I have a feeling that they may allow disclosure without NDA.
>
> Many vendors accept releasing the code produced after reading such
> specs while they don't allow the specs themselfes to be revealed.
> Also, you can offer them to review the code before releasing it.
>
> Stefan

Ok. As a fallback plan. If they do not permit spec release, I plan 
to wax eloquent to them if we succeed. May be they will get it.

rgds
jtd




From ian at abelon.com  Tue Mar  1 22:23:00 2005
From: ian at abelon.com (Ian Smith)
Date: Tue Mar  1 22:23:00 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050302040242.67734.qmail@web30006.mail.mud.yahoo.com>
References: <20050302040242.67734.qmail@web30006.mail.mud.yahoo.com>
Message-ID: <6.1.2.0.2.20050302085011.0530d340@mail.abelon.com>

Ramesh,

At 04:02 02/03/2005, ramesh bios wrote:
>1. Shadow RAM
>
>I guess I would need to find a way to tell the
>northbridge to enable shadow RAM for some range around
>f0000. I looked through the CS5530A datasheet and see
>shadow registers but no mention of shadowing RAM. Nor
>in the GX1 datasheet either. I'm looking for some
>register in either the GX1 or the CS5530A that would
>enable this. I am looking for some register that would
>enable me to remap the C0000-F0000 address range to
>somewhere in sdram. Is that the right thing to be
>looking for?

I think you may need to look at your settings for the BC_XMAP_2 and 
BC_XMAP_3 registers on the GX1 - these control read and write access to the 
BIOS shadow ram regions.

>2. Uncompressed payload
>I'm not sure I understand what this means. Right now,
>my payload is filo. In the build, I see:
>
>dd conv=sync bs=196608 if=/bios/filo-0.4.2/filo.elf
>of=payload.block
>cat payload.block > romimage
>
>Oh, I guess you must mean this stuff:
>
>objcopy -O binary linuxbios_c linuxbios_payload.bin
>./nrv2b e linuxbios_payload.bin
>linuxbios_payload.nrv2b
>
>So I guess there is some kind of compression going on
>there.

Not sure if you're using Linuxbios V1 or V2 but in V1 there is an option in 
your build config file to turn off compression - you probably need 
something like:

option CONFIG_COMPRESS=0

If it's V2 then no doubt there is an equivalent there too.

>Which method would be the right thing to do? I'll look
>at the shadow ram thing first then.
>
>Thanks.

Nope this helps

Ian

>--- "Ronald G. Minnich" <rminnich at lanl.gov> wrote:
> >
> >
> > On Tue, 1 Mar 2005, ramesh bios wrote:
> >
> > > Strike that. The issue is somewhere with
> > > copy_pirq_routing_table. IE: why does the copy to
> > > f0000 fail. I had assumed that the 500 address was
> > an
> > > alternate location that the table was copied to.
> > So
> > > now, I'm looking at that f000 failure.
> >
> >
> > the copy to f0000 fails because shadow ram is not
> > set up.
> >
> > You can fix this one of two ways. One is to figure
> > out how to enable
> > shadow ram. The second is to make the payload
> > uncompressed. The copy will
> > still fail but linux will find the PIRQ table
> > anyway.
> >
> > ron
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> >
>http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
>
>
>
>__________________________________
>Do you Yahoo!?
>Yahoo! Mail - 250MB free storage. Do more. Manage less.
>http://info.mail.yahoo.com/mail_250
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios



From cro_marmot at comcast.net  Tue Mar  1 22:28:00 2005
From: cro_marmot at comcast.net (David Hendricks)
Date: Tue Mar  1 22:28:00 2005
Subject: HP Pavillion ZV5000 (Laptop)
Message-ID: <20050302020327.0d97460d@sunder>

Here's the info on the ZV5000 I promised earlier (To Yhlu IIRC) in case
you're still interested in K8 laptops.

HP Pavillion ZV5000
0000:00:00.0 Host bridge: nVidia Corporation: Unknown device 00d1 (rev
a4)
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 0
	Region 0: Memory at e8000000 (32-bit, prefetchable)
	Capabilities: [44] #08 [0180]
	Capabilities: [c0] AGP version 2.0
		Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans-
64bit- FW+ AGP3- Rate=x1,x2,x4
		Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=x1

0000:00:01.0 ISA bridge: nVidia Corporation: Unknown device 00d0 (rev
a6)
	Subsystem: nVidia Corporation: Unknown device 0c80
	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 0

0000:00:01.1 SMBus: nVidia Corporation: Unknown device 00d4 (rev a4)
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Interrupt: pin A routed to IRQ 10
	Region 4: I/O ports at 2040 [size=64]
	Region 5: I/O ports at 2000 [size=64]
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:00:02.0 USB Controller: nVidia Corporation: Unknown device 00d7
(rev a5) (prog-if 10 [OHCI])
	Subsystem: nVidia Corporation: Unknown device 0c80
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Interrupt: pin A routed to IRQ 11
	Region 0: Memory at e0000000 (32-bit, non-prefetchable)
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:00:02.1 USB Controller: nVidia Corporation: Unknown device 00d7
(rev a5) (prog-if 10 [OHCI])
	Subsystem: nVidia Corporation: Unknown device 0c80
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Interrupt: pin B routed to IRQ 10
	Region 0: Memory at e0001000 (32-bit, non-prefetchable)
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:00:02.2 USB Controller: nVidia Corporation: Unknown device 00d8
(rev a2) (prog-if 20 [EHCI])
	Subsystem: nVidia Corporation: Unknown device 0c80
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Interrupt: pin C routed to IRQ 10
	Region 0: Memory at e0004000 (32-bit, non-prefetchable)
	Capabilities: [80] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:00:06.0 Multimedia audio controller: nVidia Corporation: Unknown
device 00da (rev a2)
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 0 (500ns min, 1250ns max)
	Interrupt: pin A routed to IRQ 11
	Region 0: I/O ports at 1400
	Region 1: I/O ports at 1c00 [size=128]
	Region 2: Memory at e0002000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:00:06.1 Modem: nVidia Corporation: Unknown device 00d9 (rev a2)
(prog-if 00 [Generic])
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Interrupt: pin B routed to IRQ 10
	Region 0: I/O ports at 1800
	Region 1: I/O ports at 1c80 [size=128]
	Region 2: Memory at e0003000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:00:08.0 IDE interface: nVidia Corporation: Unknown device 00d5 (rev
a5) (prog-if 8a [Master SecP PriP])
	Subsystem: nVidia Corporation: Unknown device 0c80
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Region 4: I/O ports at 2080 [size=16]
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:00:0a.0 PCI bridge: nVidia Corporation: Unknown device 00dd (rev
a2) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=128
	I/O behind bridge: 00003000-00007fff
	Memory behind bridge: e0100000-e17fffff
	Prefetchable memory behind bridge: fff00000-000fffff
	Expansion ROM at 00003000 [disabled] [size=20K]
	BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-

0000:00:0b.0 PCI bridge: nVidia Corporation: Unknown device 00d2 (rev
a4) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 16
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=10
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: e2000000-e2ffffff
	Prefetchable memory behind bridge: f0000000-f80fffff
	BridgeCtl: Parity+ SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B-

0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Capabilities: [80] #08 [2101]

0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-

0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-

0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-

0000:01:00.0 VGA compatible controller: nVidia Corporation NV17
[GeForce4 440 Go 64M] (rev a3) (prog-if 00 [VGA])
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (1250ns min, 250ns max)
	Interrupt: pin A routed to IRQ 11
	Region 0: Memory at e2000000 (32-bit, non-prefetchable)
	Region 1: Memory at f0000000 (32-bit, prefetchable) [size=128M]
	Region 2: Memory at f8000000 (32-bit, prefetchable) [size=512K]
	Capabilities: [60] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [44] AGP version 2.0
		Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA- ITACoh- GART64- HTrans-
64bit- FW+ AGP3- Rate=x1,x2,x4
		Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW-
Rate=<none>

0000:02:00.0 FireWire (IEEE 1394): Texas Instruments TSB43AB21
IEEE-1394a-2000 Controller (PHY/Link) (prog-if 10 [OHCI])
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (500ns min, 1000ns max), cache line size 10
	Interrupt: pin A routed to IRQ 11
	Region 0: Memory at e0108000 (32-bit, non-prefetchable)
	Region 1: Memory at e0100000 (32-bit, non-prefetchable) [size=16K]
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME+

0000:02:01.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 10
	Region 0: I/O ports at 7000
	Region 1: Memory at e0108800 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:02:02.0 Network controller: Broadcom Corporation BCM94306 802.11g
(rev 03)
	Subsystem: Hewlett-Packard Company: Unknown device 12f4
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
	Latency: 64
	Interrupt: pin A routed to IRQ 11
	Region 0: Memory at e0104000 (32-bit, non-prefetchable)

0000:02:04.0 CardBus bridge: Texas Instruments: Unknown device ac54 (rev
01)
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 168, cache line size 04
	Interrupt: pin A routed to IRQ 11
	Region 0: Memory at e0106000 (32-bit, non-prefetchable)
	Bus: primary=02, secondary=03, subordinate=06, sec-latency=176
	Memory window 0: e0200000-e03ff000 (prefetchable)
	Memory window 1: e0400000-e05ff000
	I/O window 0: 00004000-000040ff
	I/O window 1: 00004400-000044ff
	BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset+ 16bInt+ PostWrite+
	16-bit legacy interface ports at 0001

0000:02:04.1 CardBus bridge: Texas Instruments: Unknown device ac54 (rev
01)
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 168, cache line size 04
	Interrupt: pin B routed to IRQ 10
	Region 0: Memory at e0107000 (32-bit, non-prefetchable)
	Bus: primary=02, secondary=07, subordinate=0a, sec-latency=176
	Memory window 0: e1000000-e13ff000 (prefetchable)
	Memory window 1: e0c00000-e0fff000
	I/O window 0: 00006000-00006fff
	I/O window 1: 00005000-00005fff
	BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset+ 16bInt+ PostWrite+
	16-bit legacy interface ports at 0001

0000:02:04.2 System peripheral: Texas Instruments: Unknown device 8201
(rev 01)
	Subsystem: Hewlett-Packard Company: Unknown device 006d
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (1750ns min, 1000ns max), cache line size 10
	Region 0: I/O ports at 7400
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

0000:00:00.0 Host bridge: nVidia Corporation: Unknown device 00d1 (rev
a4)
00: de 10 d1 00 06 01 b0 00 a4 00 00 06 00 00 00 00
10: 08 00 00 e8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 08 c0 80 01 20 00 01 01 d0 00 00 00
50: 23 04 07 00 03 00 00 00 00 00 00 00 00 00 00 00
60: 32 31 03 00 66 45 04 00 66 06 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 13 66 66 00
80: 13 66 66 00 c8 00 00 00 70 00 00 00 07 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 02 00 20 00 17 02 00 1f 01 00 00 00 ff ff ff ff
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:01.0 ISA bridge: nVidia Corporation: Unknown device 00d0 (rev
a6)
00: de 10 d0 00 0f 00 a0 00 a6 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: de 10 80 0c 00 00 d0 fe fa 3e ff 00 fa 3e ff 00
50: fa 3e ff 00 7f b1 29 04 00 00 00 01 00 00 ff ff
60: 01 80 00 00 01 84 00 00 01 88 00 00 00 00 f9 ff
70: 10 00 ff ff 01 00 00 00 00 00 71 00 ab 0b 0b 00
80: 00 aa 00 00 ab 00 ab 00 b0 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 10 00 00 00 00 00 00 00 04 40 00 71 33 14 00
f0: 00 ff 5f bf 00 00 00 00 10 ff ff ff 00 00 30 07

0000:00:01.1 SMBus: nVidia Corporation: Unknown device 00d4 (rev a4)
00: de 10 d4 00 01 00 b0 00 a4 00 05 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 20 00 00 01 20 00 00 00 00 00 00 3c 10 6d 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01
40: 3c 10 6d 00 01 00 02 c0 00 00 00 00 00 00 00 00
50: 41 20 00 00 01 20 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:02.0 USB Controller: nVidia Corporation: Unknown device 00d7
(rev a5)
00: de 10 d7 00 07 00 b0 00 a5 10 03 0c 00 00 80 00
10: 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01
40: de 10 80 0c 01 00 02 fe 00 00 00 00 02 00 00 00
50: 00 00 00 00 1d 47 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 10 ff ff ff 04 14 30 07

0000:00:02.1 USB Controller: nVidia Corporation: Unknown device 00d7
(rev a5)
00: de 10 d7 00 07 00 b0 00 a5 10 03 0c 00 00 80 00
10: 00 10 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01
40: de 10 80 0c 01 00 02 fe 00 00 00 00 03 00 00 00
50: 00 00 00 00 1d 47 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 10 ff ff ff 04 14 30 07

0000:00:02.2 USB Controller: nVidia Corporation: Unknown device 00d8
(rev a2)
00: de 10 d8 00 06 00 b0 00 a2 20 03 0c 00 00 80 00
10: 00 40 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 03 03 01
40: de 10 80 0c 0a 80 80 20 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 20 20 01 00 00 60 98 01 c3 13 00 00 00 00 00 00
70: 00 00 00 04 00 10 30 80 89 3d 84 22 e7 25 04 80
80: 01 00 02 fe 00 00 00 00 00 00 00 00 15 16 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 00 00 00 00 00 08 e0 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 10 ff ff ff 00 00 30 07

0000:00:06.0 Multimedia audio controller: nVidia Corporation: Unknown
device 00da (rev a2)
00: de 10 da 00 07 00 b0 00 a2 00 01 04 00 00 80 00
10: 01 14 00 00 01 1c 00 00 00 20 00 e0 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 02 05
40: 3c 10 6d 00 01 00 02 06 00 00 00 00 06 01 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 10 ff ff ff 00 00 30 07

0000:00:06.1 Modem: nVidia Corporation: Unknown device 00d9 (rev a2)
00: de 10 d9 00 03 00 b0 00 a2 00 03 07 00 00 80 00
10: 01 18 00 00 81 1c 00 00 00 30 00 e0 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 02 05
40: 3c 10 6d 00 01 00 02 80 00 00 00 00 07 01 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 10 ff ff ff 00 00 30 07

0000:00:08.0 IDE interface: nVidia Corporation: Unknown device 00d5 (rev
a5)
00: de 10 d5 00 05 00 b0 00 a5 8a 01 01 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 81 20 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01
40: de 10 80 0c 01 00 02 00 00 00 00 00 00 09 00 00
50: 03 f0 00 00 00 00 00 00 a8 20 a8 20 22 00 20 20
60: 00 03 00 c6 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 88 1c 1e 00 00 02 2c 00 f0 2f 1e
90: 00 00 18 34 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 12 ff ff ff 08 11 30 07

0000:00:0a.0 PCI bridge: nVidia Corporation: Unknown device 00dd (rev
a2)
00: de 10 dd 00 07 01 a0 00 a2 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 80 30 70 80 a2
20: 10 e0 70 e1 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 02
40: 00 00 03 00 01 00 02 00 01 00 00 00 00 00 04 00
50: 00 00 fe 1f 00 00 00 00 ff 1f 00 00 03 00 80 00
60: 00 00 80 00 00 00 00 00 00 00 00 00 03 00 90 00
70: 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:0b.0 PCI bridge: nVidia Corporation: Unknown device 00d2 (rev
a4)
00: de 10 d2 00 07 01 20 02 a4 00 04 06 00 10 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 0a f0 00 20 22
20: 00 e2 f0 e2 00 f0 00 f8 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 0f 00
40: 01 00 00 00 00 00 f0 1f 20 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 10 ff ff ff ff ff ff ff ff
60: ff 40 ff 40 00 00 00 20 00 00 00 20 ff ff ff ff
70: ff ff ff ff 00 00 00 00 00 00 00 00 ff ff ff ff
80: ff ff ff ff 00 80 00 00 ea 01 00 00 ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: 17 02 00 1f 00 00 00 00 0c 00 00 00 00 00 00 00
b0: 04 07 00 00 00 00 00 00 01 00 00 00 00 00 00 00
c0: 00 00 00 00 20 00 00 00 00 00 30 07 00 00 30 07
d0: 00 00 00 00 00 00 00 00 08 00 00 e8 ff ff ff 07
e0: 00 00 50 02 00 00 51 02 00 00 50 02 00 00 51 02
f0: 00 00 50 02 00 00 51 02 00 00 50 02 00 00 51 02

0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
60: 00 00 00 00 e4 00 00 00 0f cc 00 0f 4c 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 08 00 01 21 20 00 11 10 22 04 75 80 02 00 00 00
90: 56 04 51 02 00 00 ff 00 07 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 03 00 00 00 00 00 1f 00 00 00 20 00 01 00 00 00
50: 00 00 20 00 02 00 00 00 00 00 20 00 03 00 00 00
60: 00 00 20 00 04 00 00 00 00 00 20 00 05 00 00 00
70: 00 00 20 00 06 00 00 00 00 00 20 00 07 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 03 0a 00 00 00 0b 00 00 03 00 20 00 00 0b fe 00
c0: 00 00 00 00 00 00 00 00 13 10 00 00 00 f0 0f 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 00 00 00 01 04 00 00 01 08 00 00 01 0c 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 f2 e0 01 00 f2 e0 01 00 f2 e0 01 00 f2 e0 01
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 22 00 00 00 00 00 00 00 35 33 72 13 30 0a 00 00
90: 00 8c 0c 08 06 08 5b 0e 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 5a 62 bc 5f 21 00 00 00 ef 5f 02 9b 6a 39 ef 85
c0: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 68 82 04 2a 24 10 80 0a 80 8a 00 c2 60 24 80 80
e0: 14 8b 60 84 34 08 42 0b a3 79 08 f0 20 01 00 1d
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
50: 48 08 00 00 00 00 00 00 00 00 00 00 c0 86 1a fd
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00
80: 61 63 07 63 13 41 13 61 00 00 00 00 00 00 00 00
90: 05 00 00 00 74 00 00 00 00 50 02 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 30 00 00 80 57 1c 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 01 07 0d 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 20 08 50 00 08 01 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:01:00.0 VGA compatible controller: nVidia Corporation NV17
[GeForce4 440 Go 64M] (rev a3)
00: de 10 79 01 07 00 b0 02 a3 00 00 03 00 40 00 00
10: 00 00 00 e2 08 00 00 f0 08 00 00 f8 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 05 01
40: 3c 10 6d 00 02 00 20 00 17 00 00 1f 00 00 00 00
50: 01 00 00 00 01 00 00 00 ce d6 23 00 0f 00 00 00
60: 01 44 02 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:02:00.0 FireWire (IEEE 1394): Texas Instruments TSB43AB21
IEEE-1394a-2000 Controller (PHY/Link)
00: 4c 10 26 80 16 01 10 02 00 10 00 0c 10 40 00 00
10: 00 80 10 e0 00 00 10 e0 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 02 04
40: 00 00 00 00 01 00 02 7e 00 80 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00
f0: 00 00 00 00 00 10 00 00 3c 10 6d 00 00 00 00 00

0000:02:01.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)
00: ec 10 39 81 07 01 90 02 10 00 00 02 00 40 00 00
10: 01 70 00 00 00 88 10 e0 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:02:02.0 Network controller: Broadcom Corporation BCM94306 802.11g
(rev 03)
00: e4 14 20 43 06 01 00 00 03 00 80 02 00 40 00 00
10: 00 40 10 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 f4 12
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00
40: 01 00 c2 07 00 40 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 10 00 18 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:02:04.0 CardBus bridge: Texas Instruments: Unknown device ac54 (rev
01)
00: 4c 10 54 ac 07 00 10 02 01 00 07 06 04 a8 82 00
10: 00 60 10 e0 a0 00 00 02 02 03 06 b0 00 00 20 e0
20: 00 f0 3f e0 00 00 40 e0 00 f0 5f e0 00 40 00 00
30: fc 40 00 00 00 44 00 00 fc 44 00 00 0b 01 c0 05
40: 3c 10 6d 00 01 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 61 f0 44 08 19 00 00 10 07 00 03 00 22 1d 11 01
90: c0 22 64 60 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 00 12 fe 00 00 c0 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:02:04.1 CardBus bridge: Texas Instruments: Unknown device ac54 (rev
01)
00: 4c 10 54 ac 07 00 10 02 01 00 07 06 04 a8 82 00
10: 00 70 10 e0 a0 00 00 02 02 07 0a b0 00 00 00 e1
20: 00 f0 3f e1 00 00 c0 e0 00 f0 ff e0 00 60 00 00
30: fc 6f 00 00 00 50 00 00 fc 5f 00 00 0a 02 c0 05
40: 3c 10 6d 00 01 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 61 f1 44 08 19 00 00 10 07 00 03 00 22 1d 11 01
90: c0 22 64 60 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 00 12 fe 00 00 c0 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:02:04.2 System peripheral: Texas Instruments: Unknown device 8201
(rev 01)
00: 4c 10 01 82 07 01 10 02 01 00 80 08 10 40 00 00
10: 01 74 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 07 04
40: 00 00 00 00 01 00 02 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 02 00 00 00 fc 00 01 00 0a 00 0f 00 10 30 d3 1f


From m303 at luusa.org  Tue Mar  1 23:48:00 2005
From: m303 at luusa.org (Martin Ley)
Date: Tue Mar  1 23:48:00 2005
Subject: wiki.linuxbios.org
In-Reply-To: <422526E9.40201@powercom.net>
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov>
	 <4224EF75.6010801@onelabs.com>
	 <Pine.LNX.4.58.0503011546190.20671@enigma.lanl.gov>
	 <1109718097.3104.5.camel@logarithm.lanl.gov>  <422526E9.40201@powercom.net>
Message-ID: <1109759442.2747.12.camel@black>

Hi all,

I am reading the linuxbios list for about 4 month, looking forward to
use linuxbios on my Epia M10000. I am not sure, if I build everything
allright. Maybe with the complete update of the website, there could be
ready-made ROM images available to download. I want to boot from hda,
which is a CF card.

The next thing is, how do I get the ROM image to the flash? The flash is
a SST39SF020A. The best solution would be that I use a second flash to
play with linuxbios, but I can't find a distributor in germany willing
to sell small quantities. 
My colleage has a programmer, which supports that flash. The idea is,
that he saves the standard BIOS and writes linuxbios to it. In case the
linuxbios image does not work, the original BIOS could be rewritten to
it. Would that work?

Thank you in advance for your help.

Regards
Martin

Am Dienstag, den 01.03.2005, 20:37 -0600 schrieb Justin C. Darby:
> I will be establishing web storage space for files (originally for 
> myself, but I can make it available to others). If you need space, I'm 
> going to configure websites like:
> 
> http://linuxbios-wiki-resource.windex.org/<username>/
> 
> that are intended for use by wiki maintainers to publish binaries, PDF 
> files, and the like.
> 

> Justin




From stepan at openbios.org  Wed Mar  2 00:44:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed Mar  2 00:44:00 2005
Subject: wiki.linuxbios.org
In-Reply-To: <1109759442.2747.12.camel@black>
References: <Pine.LNX.4.58.0503011509060.20671@enigma.lanl.gov> <4224EF75.6010801@onelabs.com> <Pine.LNX.4.58.0503011546190.20671@enigma.lanl.gov> <1109718097.3104.5.camel@logarithm.lanl.gov> <422526E9.40201@powercom.net> <1109759442.2747.12.camel@black>
Message-ID: <20050302111909.GA21545@openbios.org>

* Martin Ley <m303 at luusa.org> [050302 11:30]:
> The next thing is, how do I get the ROM image to the flash? The flash is
> a SST39SF020A. The best solution would be that I use a second flash to
> play with linuxbios, but I can't find a distributor in germany willing
> to sell small quantities. 

You might try Conrad or any other electronics shop. Be sure to purchase
a chip of the same family (39xx0y0)

http://wiki.linuxbios.org/index.php/FAQ#How_do_I_.28re-.29flash_the_BIOS.3F

> My colleage has a programmer, which supports that flash. The idea is,
> that he saves the standard BIOS and writes linuxbios to it. In case the
> linuxbios image does not work, the original BIOS could be rewritten to
> it. Would that work?

Yes. This will work, I did such a lot of times. With the flash_rom
utility mentioned in the FAQ you can also easily create a rom backup
file of your original bios. (Be sure to copy it to another machine or
floppy before erasing the flash chip though ;)

Stefan



From ourlinuxid at yahoo.co.in  Wed Mar  2 00:47:00 2005
From: ourlinuxid at yahoo.co.in (Ramesh Chhaba)
Date: Wed Mar  2 00:47:00 2005
Subject: error in making bios
Message-ID: <20050302111951.7955.qmail@web8402.mail.in.yahoo.com>

Hi All ,

I was just trying to make a linuxBIOS for epic.
at last step it gives error .

././buildrom linuxbios.strip linuxbios.rom
../../../../../lnxieepro100.ebi 0x10000 0x20000
../../../../../lnxieepro100.ebi: No such file or
directory
make[1]: *** [linuxbios.rom] Error 2
make[1]: Leaving directory
`/usr/downloads/freebios-20041019-1200/freebios2/targets/via/epia/epia/normal'
make: *** [normal/linuxbios.rom] Error 1
[root at Linux3 epia]#


Can anybody tell how this error can be removed

Thanks 
Ramesh

________________________________________________________________________
Yahoo! India Matrimony: Find your life partner online
Go to: http://yahoo.shaadi.com/india-matrimony


From stepan at openbios.org  Wed Mar  2 01:02:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed Mar  2 01:02:01 2005
Subject: error in making bios
In-Reply-To: <20050302111951.7955.qmail@web8402.mail.in.yahoo.com>
References: <20050302111951.7955.qmail@web8402.mail.in.yahoo.com>
Message-ID: <20050302113735.GA22296@openbios.org>

* Ramesh Chhaba <ourlinuxid at yahoo.co.in> [050302 12:19]:
> I was just trying to make a linuxBIOS for epic.
> at last step it gives error .
> 
> ././buildrom linuxbios.strip linuxbios.rom
> ../../../../../lnxieepro100.ebi 0x10000 0x20000
> ../../../../../lnxieepro100.ebi: No such file or directory
> 
> Can anybody tell how this error can be removed
 
Yes, fix the path to the payload in
freebios2/targets/via/epia/Config.lb

You might want to use a different payload. Have a look at:
    http://wiki.linuxbios.org/index.php/Payloads

Stefan


From petekarl at student.chalmers.se  Wed Mar  2 01:15:00 2005
From: petekarl at student.chalmers.se (Peter Karlsson)
Date: Wed Mar  2 01:15:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <20050301154031.GE15145@foo.birdnet.se>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
 <20050301154031.GE15145@foo.birdnet.se>
Message-ID: <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>

On Tue, 1 Mar 2005, Peter Stuge wrote:

> Exactly right. But with the right flash memory on the mainboard you
> can use the operating system (Linux) as payload directly.

Ok, thanks. I've seen this discussed on this list; dependent on size of 
flash mem.

> I'm not sure I agree that the bar must be lowered. Much of the
> development going on in LinuxBIOS is _heavily_ technical and spans
> across quite a few different architectures. It's not right or useful
> to force developers to work and/or communicate below their
> capabilities, and certainly not in an open source project. I would
> hate it if someone tried to do that to me.

I really don't want to force anyone to do anything they don't want to do. 
My request/suggestion/whatever was merely what someone else suggested 
("programmer's manual" etc.), not dumb-down the project as a whole, or 
"forcing" developers to hand-hold "newbies" like me... I apologise, if it 
came across like that. Maybe it's my english (it's not my native 
language).

> I do believe however, that all the technical prerequisite knowledge
> should be listed, so that people can get up-to-speed on their own.
> I'll try to work for this and I think that the wiki is a great forum.

That's a great idea. And I also think the wiki is a great thing to have. 
:-)

> SPD is Serial Presence Detect, the name of an I2C bus between the
> northbridge and all RAM modules. Each RAM module has an EEPROM with
> more or less correct information about how memory initialization code
> should set up the memory controller for correct size and optimal
> performance. Quite frequently the information is busted. :(

<snip>

> These are short for Vendor ID and Device ID. VID and DID (or PID,
> Product ID) are id numbers assigned by organizations such as PCI-SIG
> and USBIF to hardware manufacturers allowing software to identify
> hardware in a reliable manner. The ids are stored inside the device,
> whether it's PCI or USB. Also true for PCMCIA/CardBus.

Ok, thanks again for educating me!

Best regards

Peter K


From petekarl at student.chalmers.se  Wed Mar  2 01:56:01 2005
From: petekarl at student.chalmers.se (Peter Karlsson)
Date: Wed Mar  2 01:56:01 2005
Subject: Porting Linuxbios to Via P4m266A
In-Reply-To: <Pine.LNX.4.58.0503010846390.20461@enigma.lanl.gov>
References: <E1D5zgk-0005b8-St@denali.ccs.neu.edu>
 <Pine.GSO.4.62.0503011038200.17857@bilbo.dd.chalmers.se>
 <Pine.LNX.4.58.0503010846390.20461@enigma.lanl.gov>
Message-ID: <Pine.GSO.4.62.0503021321460.10589@bilbo.dd.chalmers.se>

On Tue, 1 Mar 2005, Ronald G. Minnich wrote:

> no. recall this is a just a hack to figure out what the bios is doing, not
> some permanent thing.

Ok, it's just that I have an intel m/b (i875-based) and from what I've 
gathered there's no support for any newer intel chips than the 440xX, so a 
hack like that would perhaps enable me to experiment (me play to ;-). Of 
course I need to get a hold of a bios-saviour kit first since this is my 
only 'puter (currently)...

Best regards

Peter K


From stepan at openbios.org  Wed Mar  2 02:15:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed Mar  2 02:15:00 2005
Subject: Porting Linuxbios to Via P4m266A
In-Reply-To: <Pine.GSO.4.62.0503021321460.10589@bilbo.dd.chalmers.se>
References: <E1D5zgk-0005b8-St@denali.ccs.neu.edu> <Pine.GSO.4.62.0503011038200.17857@bilbo.dd.chalmers.se> <Pine.LNX.4.58.0503010846390.20461@enigma.lanl.gov> <Pine.GSO.4.62.0503021321460.10589@bilbo.dd.chalmers.se>
Message-ID: <20050302125047.GA25347@openbios.org>

* Peter Karlsson <petekarl at student.chalmers.se> [050302 13:31]:
> Ok, it's just that I have an intel m/b (i875-based) and from what I've 
> gathered there's no support for any newer intel chips than the 440xX, so a 
> hack like that would perhaps enable me to experiment (me play to ;-). Of 
> course I need to get a hold of a bios-saviour kit first since this is my 
> only 'puter (currently)...

A good way for the adventurous is to boot the machine, swap the chip
while it is running, flash the new chip, and reboot. This way you only
need a decent chip claw for not even 10 bucks.

Yes, you do risk wasting your motherboard theoretically, and no, it
never happened to me in the last 5 ys

Stefan




From rminnich at lanl.gov  Wed Mar  2 04:03:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 04:03:00 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050302040242.67734.qmail@web30006.mail.mud.yahoo.com>
References: <20050302040242.67734.qmail@web30006.mail.mud.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503020737590.22678@enigma.lanl.gov>

you should try to get shadow ram working. 

ron



From rminnich at lanl.gov  Wed Mar  2 04:15:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 04:15:01 2005
Subject: Porting Linuxbios to Via P4m266A
In-Reply-To: <19d908119dbe65.19dbe6519d9081@vsnl.net>
References: <19d908119dbe65.19dbe6519d9081@vsnl.net>
Message-ID: <Pine.LNX.4.58.0503020750170.22678@enigma.lanl.gov>


On Wed, 2 Mar 2005 sherlock at vsnl.com wrote:

> I have written back asking for permission to disclose the contents
> without NDA. I have pointed out the benefits they are going to derive.  
> Let's see how it goes. I have a feeling that they may allow disclosure
> without NDA.

another option is to ask for permission to release code but not release 
the material. VIA has done that for me in the past. 

ron


From rminnich at lanl.gov  Wed Mar  2 04:29:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 04:29:01 2005
Subject: error in making bios
In-Reply-To: <20050302111951.7955.qmail@web8402.mail.in.yahoo.com>
References: <20050302111951.7955.qmail@web8402.mail.in.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503020803510.22810@enigma.lanl.gov>


On Wed, 2 Mar 2005, Ramesh Chhaba wrote:

> Hi All ,
> 
> I was just trying to make a linuxBIOS for epic.
> at last step it gives error .
> 
> ././buildrom linuxbios.strip linuxbios.rom
> ../../../../../lnxieepro100.ebi 0x10000 0x20000
> ../../../../../lnxieepro100.ebi: No such file or
> directory

it needs that file. So you need to provide that file or make your own 
Config file with a different file.

ron


From rminnich at lanl.gov  Wed Mar  2 04:30:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 04:30:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
 <20050301154031.GE15145@foo.birdnet.se> <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
Message-ID: <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>


On Wed, 2 Mar 2005, Peter Karlsson wrote:

> Ok, thanks again for educating me!

so, peter, you want to accumulate the Glossary for us :-)

ron


From jdarby at powercom.net  Wed Mar  2 04:41:01 2005
From: jdarby at powercom.net (Justin C. Darby)
Date: Wed Mar  2 04:41:01 2005
Subject: [wiki] v2 PC-Chips support
Message-ID: <4225D8B5.1020405@powercom.net>

Hi all,

I seem to remember LinuxBIOS having a few PC-Chips motherboards 
supported, but there is currently no mention of it on the page.

Is this not in v2?

Are any of the supported PC-Chips motherboards still in production or 
use that should be in the documentation?

Thanks,
Justin



From rminnich at lanl.gov  Wed Mar  2 04:48:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 04:48:00 2005
Subject: [wiki] v2 PC-Chips support
In-Reply-To: <4225D8B5.1020405@powercom.net>
References: <4225D8B5.1020405@powercom.net>
Message-ID: <Pine.LNX.4.58.0503020823240.22810@enigma.lanl.gov>


On Wed, 2 Mar 2005, Justin C. Darby wrote:

> I seem to remember LinuxBIOS having a few PC-Chips motherboards supported, but
> there is currently no mention of it on the page.
> 
> Is this not in v2?

It is not in v2. 

> Are any of the supported PC-Chips motherboards still in production or
> use that should be in the documentation?

Not sure.

ron


From smithbone at gmail.com  Wed Mar  2 04:54:00 2005
From: smithbone at gmail.com (Richard Smith)
Date: Wed Mar  2 04:54:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
	 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
	 <20050301154031.GE15145@foo.birdnet.se>
	 <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
	 <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
Message-ID: <8a0c367805030207282d68053b@mail.gmail.com>

On Wed, 2 Mar 2005 08:05:06 -0700 (MST), Ronald G. Minnich
<rminnich at lanl.gov> wrote:
> 
> 
> On Wed, 2 Mar 2005, Peter Karlsson wrote:
> 
> > Ok, thanks again for educating me!
> 
> so, peter, you want to accumulate the Glossary for us :-)

A tehnical glossary would be nice but  one thing we _really_ need is a
listing of all config options and what they do.  This was (and still
is) one of the largest hurdles for me.  And its one of the things that
Google won't find much on.

I compiled part of a list for V1 and its in my FAQ I put out but V2 is
all new to me.

-- 
Richard A. Smith


From jdarby at powercom.net  Wed Mar  2 04:59:00 2005
From: jdarby at powercom.net (Justin C. Darby)
Date: Wed Mar  2 04:59:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <8a0c367805030207282d68053b@mail.gmail.com>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>	 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>	 <20050301154031.GE15145@foo.birdnet.se>	 <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>	 <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov> <8a0c367805030207282d68053b@mail.gmail.com>
Message-ID: <4225DD05.8070400@powercom.net>

Richard Smith wrote:

>A tehnical glossary would be nice but  one thing we _really_ need is a
>listing of all config options and what they do.  This was (and still
>is) one of the largest hurdles for me.  And its one of the things that
>Google won't find much on.
>
>I compiled part of a list for V1 and its in my FAQ I put out but V2 is
>all new to me.
>
>  
>
If someone can point me in the right direction (in the source, I'd 
guess) to find all of the configuration options without descriptions I 
can setup a page dedicated to explaining them one at a time.

Justin



From stepan at openbios.org  Wed Mar  2 05:05:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed Mar  2 05:05:01 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <8a0c367805030207282d68053b@mail.gmail.com>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> <20050301154031.GE15145@foo.birdnet.se> <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se> <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov> <8a0c367805030207282d68053b@mail.gmail.com>
Message-ID: <20050302154020.GA581@openbios.org>

* Richard Smith <smithbone at gmail.com> [050302 16:28]:
> A tehnical glossary would be nice but  one thing we _really_ need is a
> listing of all config options and what they do.  This was (and still
> is) one of the largest hurdles for me.  And its one of the things that
> Google won't find much on.

Should this be generated automatically out of Options.lb? There is a lot
of description in that file already.




From stepan at openbios.org  Wed Mar  2 05:06:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed Mar  2 05:06:01 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <4225DD05.8070400@powercom.net>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> <20050301154031.GE15145@foo.birdnet.se> <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se> <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov> <8a0c367805030207282d68053b@mail.gmail.com> <4225DD05.8070400@powercom.net>
Message-ID: <20050302154116.GB581@openbios.org>

* Justin C. Darby <jdarby at powercom.net> [050302 16:34]:
> If someone can point me in the right direction (in the source, I'd 
> guess) to find all of the configuration options without descriptions I 
> can setup a page dedicated to explaining them one at a time.
 
freebios2/src/config/Options.lb




From smithbone at gmail.com  Wed Mar  2 05:20:00 2005
From: smithbone at gmail.com (Richard Smith)
Date: Wed Mar  2 05:20:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <20050302154020.GA581@openbios.org>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
	 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
	 <20050301154031.GE15145@foo.birdnet.se>
	 <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
	 <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
	 <8a0c367805030207282d68053b@mail.gmail.com>
	 <20050302154020.GA581@openbios.org>
Message-ID: <8a0c3678050302075519758f44@mail.gmail.com>

> > listing of all config options and what they do.  This was (and still
> > is) one of the largest hurdles for me.  And its one of the things that
> > Google won't find much on.
> 
> Should this be generated automatically out of Options.lb? There is a lot
> of description in that file already.

Thats a good idea.  What about adding a "description" section where
this info is filled out.  Then the config tool would generate some
sort of  text file in the target directory describing all the options
that are set.  You could perhaps add some dependency info in there as
well.

-- 
Richard A. Smith


From smithbone at gmail.com  Wed Mar  2 05:25:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Wed Mar  2 05:25:01 2005
Subject: FAQ question fixup
In-Reply-To: <4225DD05.8070400@powercom.net>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
	 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
	 <20050301154031.GE15145@foo.birdnet.se>
	 <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
	 <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
	 <8a0c367805030207282d68053b@mail.gmail.com>
	 <4225DD05.8070400@powercom.net>
Message-ID: <8a0c367805030208007492c87e@mail.gmail.com>

I've been adding selected info from my V1 FAQ up into the wiki.  The
following is some info I compiled up on V1 start up.

If someone(s) would update this for V2 and post it t the wiki I think
it would be very useful.


================================
Help!  I'm a newbie and I'm completely lost in the code.

   There seem to be two main parts to linuxbios. The first is 
   arch/{arch}/config/ctr0.base which does the very low level initialization, 
   like turning on memory, etc. The second is arch/{arch}/lib/c_start.S which 
   does whatever else is necessary to call the C function hardwaremain(). 
   hardwaremain() then does whatever else is necessary to load linux.
     
   c_start.S is linked with linuxbios.a, a library containing generic support 
   routines (those found in the lib directory) and anything specified using the 
   'object'  directive in a Config file (and other stuff). The resultant 
   'executable' is called linuxbios_c. The loader script used to link 
   linuxbios_c is config/linuxbios_c.ld, and is configured to be
loaded relative
   to _RAMBASE.
     
   crt0.base is not linked against anything. Any additional assembly routines 
   you need must be specified using the 'mainboardinit' directive in a Config 
   file. This causes the specified assembly file to be added to 
   "crt0_includes.h" which is in turn included at the start of crt0.base (or at 
   the end in the case of the ppc version). The loader script used to link 
   crt0.base is in arch/{arch}/config/ldscript.base. The resultant 'executable' 
   is called linuxbios and will be loaded at _ROMBASE. The tricky thing is that 
   this loader script will also load the linuxbios_c 'executable' at a location 
   called _payload in this file. The main task of crt0.base is then to 
   initialize enough hardware so that this payload can be copied from rom into 
   ram (which may also involve uncompressing code). Then control is transferred 
   to _start, which is the first location in linuxbios_c.
     
   To get an idea of how crt0.base works, look at the following files. This is 
   the order of execution specified by the configuration file for sis735.
     
     cpu/i386/entry16.inc
     cpu/i386/entry32.inc
     superio/sis/950/setup_serial.inc
     pc80/serial.inc
     arch/i386/lib/console.inc
     cpu/k7/earlymtrr.inc
     northsouthbridge/sis/735/raminit.inc
     arch/i386/config/crt0.base
     
   Next look at c_start.S which will show you what happens once control is 
   transferred to _start. Finally, look at
arch/{arch}/lib/hardwaremain.c to see
   what other stuff is done to get linux loaded.
     
   Most other files are specific to particular hardware, so it can be pretty 
   confusing to just browse the tree.



-- 
Richard A. Smith


From stepan at openbios.org  Wed Mar  2 05:29:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed Mar  2 05:29:01 2005
Subject: FAQ question fixup
In-Reply-To: <8a0c367805030208007492c87e@mail.gmail.com>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> <20050301154031.GE15145@foo.birdnet.se> <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se> <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov> <8a0c367805030207282d68053b@mail.gmail.com> <4225DD05.8070400@powercom.net> <8a0c367805030208007492c87e@mail.gmail.com>
Message-ID: <20050302160404.GA1662@openbios.org>

* Richard Smith <smithbone at gmail.com> [050302 17:00]:
> I've been adding selected info from my V1 FAQ up into the wiki.  The
> following is some info I compiled up on V1 start up.
> 
> If someone(s) would update this for V2 and post it t the wiki I think
> it would be very useful.

I have an old writeup on this for v2 at home. I'll try to find it
(printout) I think this should even go to an extra page.


> ================================
> Help!  I'm a newbie and I'm completely lost in the code.
> 
>    There seem to be two main parts to linuxbios. The first is 
>    arch/{arch}/config/ctr0.base which does the very low level initialization, 
>    like turning on memory, etc. The second is arch/{arch}/lib/c_start.S which 
>    does whatever else is necessary to call the C function hardwaremain(). 
>    hardwaremain() then does whatever else is necessary to load linux.
>      
>    c_start.S is linked with linuxbios.a, a library containing generic support 
>    routines (those found in the lib directory) and anything specified using the 
>    'object'  directive in a Config file (and other stuff). The resultant 
>    'executable' is called linuxbios_c. The loader script used to link 
>    linuxbios_c is config/linuxbios_c.ld, and is configured to be
> loaded relative
>    to _RAMBASE.
>      
>    crt0.base is not linked against anything. Any additional assembly routines 
>    you need must be specified using the 'mainboardinit' directive in a Config 
>    file. This causes the specified assembly file to be added to 
>    "crt0_includes.h" which is in turn included at the start of crt0.base (or at 
>    the end in the case of the ppc version). The loader script used to link 
>    crt0.base is in arch/{arch}/config/ldscript.base. The resultant 'executable' 
>    is called linuxbios and will be loaded at _ROMBASE. The tricky thing is that 
>    this loader script will also load the linuxbios_c 'executable' at a location 
>    called _payload in this file. The main task of crt0.base is then to 
>    initialize enough hardware so that this payload can be copied from rom into 
>    ram (which may also involve uncompressing code). Then control is transferred 
>    to _start, which is the first location in linuxbios_c.
>      
>    To get an idea of how crt0.base works, look at the following files. This is 
>    the order of execution specified by the configuration file for sis735.
>      
>      cpu/i386/entry16.inc
>      cpu/i386/entry32.inc
>      superio/sis/950/setup_serial.inc
>      pc80/serial.inc
>      arch/i386/lib/console.inc
>      cpu/k7/earlymtrr.inc
>      northsouthbridge/sis/735/raminit.inc
>      arch/i386/config/crt0.base
>      
>    Next look at c_start.S which will show you what happens once control is 
>    transferred to _start. Finally, look at
> arch/{arch}/lib/hardwaremain.c to see
>    what other stuff is done to get linux loaded.
>      
>    Most other files are specific to particular hardware, so it can be pretty 
>    confusing to just browse the tree.
> 
> 
> 
> -- 
> Richard A. Smith
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


From rminnich at lanl.gov  Wed Mar  2 05:56:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 05:56:01 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <4225DD05.8070400@powercom.net>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> 
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> 
 <20050301154031.GE15145@foo.birdnet.se>  <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
  <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
 <8a0c367805030207282d68053b@mail.gmail.com> <4225DD05.8070400@powercom.net>
Message-ID: <Pine.LNX.4.58.0503020931030.22960@enigma.lanl.gov>


On Wed, 2 Mar 2005, Justin C. Darby wrote:

> If someone can point me in the right direction (in the source, I'd guess) to
> find all of the configuration options without descriptions I can setup a page
> dedicated to explaining them one at a time.
> 


src/config/Options.lb


What's nice is the format greg watson worked up is amenable to processing 
to produce html. I think this ought to be easy to autmoate.

ron


From jrollins at ligo.mit.edu  Wed Mar  2 05:59:00 2005
From: jrollins at ligo.mit.edu (Jamie Rollins)
Date: Wed Mar  2 05:59:00 2005
Subject: documentation page on wiki
Message-ID: <Pine.GSO.4.56.0503021120460.5481@ligo.mit.edu>

So I'm trying to put together a Documentation page on the new site.
However, since I don't actually know how to do any of this stuff myself
(which is why I'm very excited about the new page), I'm just culling
documentation from where ever I can find it.  The only "official" things
I'm finding right now are the old how-to's and the LinuxBIOS Configuration
Tool paper from Ron Minnich in Jan 2001 that I pulled from the V1 CVS
repository.  There's also a very nice article that I found from Linux
Magazine that is better than most other things that I've read about
getting started:

http://www.linuxbios.org/papers/linux-magazine/LinuxBIOS.pdf

Does any one have any idea whether or not we can re-print this article, or
at least link to it from the page?

Also, I'm making a call for all documentation input.  I think that the
page should be organized with a general documentation applicable to all
systems, and then how-to's for specific motherboards (which can be linked
to from the Supported Motherboards page).

jamie.





From rminnich at lanl.gov  Wed Mar  2 06:01:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 06:01:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <8a0c3678050302075519758f44@mail.gmail.com>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> 
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> 
 <20050301154031.GE15145@foo.birdnet.se>  <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
  <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov> 
 <8a0c367805030207282d68053b@mail.gmail.com>  <20050302154020.GA581@openbios.org>
 <8a0c3678050302075519758f44@mail.gmail.com>
Message-ID: <Pine.LNX.4.58.0503020935560.22960@enigma.lanl.gov>


On Wed, 2 Mar 2005, Richard Smith wrote:

> Thats a good idea.  What about adding a "description" section where
> this info is filled out.  Then the config tool would generate some
> sort of  text file in the target directory describing all the options
> that are set.  

Makefile.settings

ron


From jdarby at powercom.net  Wed Mar  2 06:02:01 2005
From: jdarby at powercom.net (Justin C. Darby)
Date: Wed Mar  2 06:02:01 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.LNX.4.58.0503020931030.22960@enigma.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>  <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>  <20050301154031.GE15145@foo.birdnet.se>  <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>  <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov> <8a0c367805030207282d68053b@mail.gmail.com> <4225DD05.8070400@powercom.net> <Pine.LNX.4.58.0503020931030.22960@enigma.lanl.gov>
Message-ID: <4225EB9E.20406@powercom.net>

Ronald G. Minnich wrote:

> src/config/Options.lb
>
>
>What's nice is the format greg watson worked up is amenable to processing 
>to produce html. I think this ought to be easy to autmoate.
>
>ron
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
>  
>
I will get out my web programming hat to see if I can get that automated 
after I run out of other things to do. :)

Justin



From yinghailu at gmail.com  Wed Mar  2 08:00:00 2005
From: yinghailu at gmail.com (yhlu)
Date: Wed Mar  2 08:00:00 2005
Subject: HP Pavillion ZV5000 (Laptop)
In-Reply-To: <20050302020327.0d97460d@sunder>
References: <20050302020327.0d97460d@sunder>
Message-ID: <2ea3fae1050302103575a6d31e@mail.gmail.com>

Cool.

Anyone has ASUS z80k or Z81k, that one has 5 USB port.

YH


On Wed, 2 Mar 2005 02:03:27 -0700, David Hendricks
<cro_marmot at comcast.net> wrote:
> Here's the info on the ZV5000 I promised earlier (To Yhlu IIRC) in case
> you're still interested in K8 laptops.
> 
> HP Pavillion ZV5000
> 0000:00:00.0 Host bridge: nVidia Corporation: Unknown device 00d1 (rev
> a4)
>        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR+ FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 0
>        Region 0: Memory at e8000000 (32-bit, prefetchable)
>        Capabilities: [44] #08 [0180]
>        Capabilities: [c0] AGP version 2.0
>                Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans-
> 64bit- FW+ AGP3- Rate=x1,x2,x4
>                Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=x1
> 
> 0000:00:01.0 ISA bridge: nVidia Corporation: Unknown device 00d0 (rev
> a6)
>        Subsystem: nVidia Corporation: Unknown device 0c80
>        Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 0
> 
> 0000:00:01.1 SMBus: nVidia Corporation: Unknown device 00d4 (rev a4)
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Interrupt: pin A routed to IRQ 10
>        Region 4: I/O ports at 2040 [size=64]
>        Region 5: I/O ports at 2000 [size=64]
>        Capabilities: [44] Power Management version 2
>                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot+,D3cold+)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:00:02.0 USB Controller: nVidia Corporation: Unknown device 00d7
> (rev a5) (prog-if 10 [OHCI])
>        Subsystem: nVidia Corporation: Unknown device 0c80
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 0 (750ns min, 250ns max)
>        Interrupt: pin A routed to IRQ 11
>        Region 0: Memory at e0000000 (32-bit, non-prefetchable)
>        Capabilities: [44] Power Management version 2
>                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
> PME(D0+,D1+,D2+,D3hot+,D3cold+)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:00:02.1 USB Controller: nVidia Corporation: Unknown device 00d7
> (rev a5) (prog-if 10 [OHCI])
>        Subsystem: nVidia Corporation: Unknown device 0c80
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 0 (750ns min, 250ns max)
>        Interrupt: pin B routed to IRQ 10
>        Region 0: Memory at e0001000 (32-bit, non-prefetchable)
>        Capabilities: [44] Power Management version 2
>                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
> PME(D0+,D1+,D2+,D3hot+,D3cold+)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:00:02.2 USB Controller: nVidia Corporation: Unknown device 00d8
> (rev a2) (prog-if 20 [EHCI])
>        Subsystem: nVidia Corporation: Unknown device 0c80
>        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 0 (750ns min, 250ns max)
>        Interrupt: pin C routed to IRQ 10
>        Region 0: Memory at e0004000 (32-bit, non-prefetchable)
>        Capabilities: [80] Power Management version 2
>                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
> PME(D0+,D1+,D2+,D3hot+,D3cold+)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:00:06.0 Multimedia audio controller: nVidia Corporation: Unknown
> device 00da (rev a2)
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 0 (500ns min, 1250ns max)
>        Interrupt: pin A routed to IRQ 11
>        Region 0: I/O ports at 1400
>        Region 1: I/O ports at 1c00 [size=128]
>        Region 2: Memory at e0002000 (32-bit, non-prefetchable) [size=4K]
>        Capabilities: [44] Power Management version 2
>                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot-,D3cold-)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:00:06.1 Modem: nVidia Corporation: Unknown device 00d9 (rev a2)
> (prog-if 00 [Generic])
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Interrupt: pin B routed to IRQ 10
>        Region 0: I/O ports at 1800
>        Region 1: I/O ports at 1c80 [size=128]
>        Region 2: Memory at e0003000 (32-bit, non-prefetchable) [size=4K]
>        Capabilities: [44] Power Management version 2
>                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot-,D3cold+)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:00:08.0 IDE interface: nVidia Corporation: Unknown device 00d5 (rev
> a5) (prog-if 8a [Master SecP PriP])
>        Subsystem: nVidia Corporation: Unknown device 0c80
>        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 0 (750ns min, 250ns max)
>        Region 4: I/O ports at 2080 [size=16]
>        Capabilities: [44] Power Management version 2
>                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot-,D3cold-)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:00:0a.0 PCI bridge: nVidia Corporation: Unknown device 00dd (rev
> a2) (prog-if 00 [Normal decode])
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR+ FastB2B-
>        Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 0
>        Bus: primary=00, secondary=02, subordinate=02, sec-latency=128
>        I/O behind bridge: 00003000-00007fff
>        Memory behind bridge: e0100000-e17fffff
>        Prefetchable memory behind bridge: fff00000-000fffff
>        Expansion ROM at 00003000 [disabled] [size=20K]
>        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
> 
> 0000:00:0b.0 PCI bridge: nVidia Corporation: Unknown device 00d2 (rev
> a4) (prog-if 00 [Normal decode])
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR+ FastB2B-
>        Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR-
>        Latency: 16
>        Bus: primary=00, secondary=01, subordinate=01, sec-latency=10
>        I/O behind bridge: 0000f000-00000fff
>        Memory behind bridge: e2000000-e2ffffff
>        Prefetchable memory behind bridge: f0000000-f80fffff
>        BridgeCtl: Parity+ SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B-
> 
> 0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
>        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Capabilities: [80] #08 [2101]
> 
> 0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
>        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
> 
> 0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
>        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
> 
> 0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
>        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
> 
> 0000:01:00.0 VGA compatible controller: nVidia Corporation NV17
> [GeForce4 440 Go 64M] (rev a3) (prog-if 00 [VGA])
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR-
>        Latency: 64 (1250ns min, 250ns max)
>        Interrupt: pin A routed to IRQ 11
>        Region 0: Memory at e2000000 (32-bit, non-prefetchable)
>        Region 1: Memory at f0000000 (32-bit, prefetchable) [size=128M]
>        Region 2: Memory at f8000000 (32-bit, prefetchable) [size=512K]
>        Capabilities: [60] Power Management version 2
>                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot-,D3cold-)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
>        Capabilities: [44] AGP version 2.0
>                Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA- ITACoh- GART64- HTrans-
> 64bit- FW+ AGP3- Rate=x1,x2,x4
>                Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW-
> Rate=<none>
> 
> 0000:02:00.0 FireWire (IEEE 1394): Texas Instruments TSB43AB21
> IEEE-1394a-2000 Controller (PHY/Link) (prog-if 10 [OHCI])
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
> Stepping- SERR+ FastB2B-
>        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR-
>        Latency: 64 (500ns min, 1000ns max), cache line size 10
>        Interrupt: pin A routed to IRQ 11
>        Region 0: Memory at e0108000 (32-bit, non-prefetchable)
>        Region 1: Memory at e0100000 (32-bit, non-prefetchable) [size=16K]
>        Capabilities: [44] Power Management version 2
>                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
> PME(D0+,D1+,D2+,D3hot+,D3cold-)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME+
> 
> 0000:02:01.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
> RTL-8139/8139C/8139C+ (rev 10)
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR+ FastB2B-
>        Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR-
>        Latency: 64 (8000ns min, 16000ns max)
>        Interrupt: pin A routed to IRQ 10
>        Region 0: I/O ports at 7000
>        Region 1: Memory at e0108800 (32-bit, non-prefetchable) [size=256]
>        Capabilities: [50] Power Management version 2
>                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
> PME(D0-,D1+,D2+,D3hot+,D3cold+)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:02:02.0 Network controller: Broadcom Corporation BCM94306 802.11g
> (rev 03)
>        Subsystem: Hewlett-Packard Company: Unknown device 12f4
>        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR+ FastB2B-
>        Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort- >SERR- <PERR-
>        Latency: 64
>        Interrupt: pin A routed to IRQ 11
>        Region 0: Memory at e0104000 (32-bit, non-prefetchable)
> 
> 0000:02:04.0 CardBus bridge: Texas Instruments: Unknown device ac54 (rev
> 01)
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR-
>        Latency: 168, cache line size 04
>        Interrupt: pin A routed to IRQ 11
>        Region 0: Memory at e0106000 (32-bit, non-prefetchable)
>        Bus: primary=02, secondary=03, subordinate=06, sec-latency=176
>        Memory window 0: e0200000-e03ff000 (prefetchable)
>        Memory window 1: e0400000-e05ff000
>        I/O window 0: 00004000-000040ff
>        I/O window 1: 00004400-000044ff
>        BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset+ 16bInt+ PostWrite+
>        16-bit legacy interface ports at 0001
> 
> 0000:02:04.1 CardBus bridge: Texas Instruments: Unknown device ac54 (rev
> 01)
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B-
>        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR-
>        Latency: 168, cache line size 04
>        Interrupt: pin B routed to IRQ 10
>        Region 0: Memory at e0107000 (32-bit, non-prefetchable)
>        Bus: primary=02, secondary=07, subordinate=0a, sec-latency=176
>        Memory window 0: e1000000-e13ff000 (prefetchable)
>        Memory window 1: e0c00000-e0fff000
>        I/O window 0: 00006000-00006fff
>        I/O window 1: 00005000-00005fff
>        BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset+ 16bInt+ PostWrite+
>        16-bit legacy interface ports at 0001
> 
> 0000:02:04.2 System peripheral: Texas Instruments: Unknown device 8201
> (rev 01)
>        Subsystem: Hewlett-Packard Company: Unknown device 006d
>        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR+ FastB2B-
>        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR-
>        Latency: 64 (1750ns min, 1000ns max), cache line size 10
>        Region 0: I/O ports at 7400
>        Capabilities: [44] Power Management version 2
>                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot-,D3cold-)
>                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> 
> 0000:00:00.0 Host bridge: nVidia Corporation: Unknown device 00d1 (rev
> a4)
> 00: de 10 d1 00 06 01 b0 00 a4 00 00 06 00 00 00 00
> 10: 08 00 00 e8 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 00 00
> 40: 00 00 00 00 08 c0 80 01 20 00 01 01 d0 00 00 00
> 50: 23 04 07 00 03 00 00 00 00 00 00 00 00 00 00 00
> 60: 32 31 03 00 66 45 04 00 66 06 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 13 66 66 00
> 80: 13 66 66 00 c8 00 00 00 70 00 00 00 07 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 02 00 20 00 17 02 00 1f 01 00 00 00 ff ff ff ff
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:00:01.0 ISA bridge: nVidia Corporation: Unknown device 00d0 (rev
> a6)
> 00: de 10 d0 00 0f 00 a0 00 a6 00 01 06 00 00 80 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 40: de 10 80 0c 00 00 d0 fe fa 3e ff 00 fa 3e ff 00
> 50: fa 3e ff 00 7f b1 29 04 00 00 00 01 00 00 ff ff
> 60: 01 80 00 00 01 84 00 00 01 88 00 00 00 00 f9 ff
> 70: 10 00 ff ff 01 00 00 00 00 00 71 00 ab 0b 0b 00
> 80: 00 aa 00 00 ab 00 ab 00 b0 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 10 00 00 00 00 00 00 00 04 40 00 71 33 14 00
> f0: 00 ff 5f bf 00 00 00 00 10 ff ff ff 00 00 30 07
> 
> 0000:00:01.1 SMBus: nVidia Corporation: Unknown device 00d4 (rev a4)
> 00: de 10 d4 00 01 00 b0 00 a4 00 05 0c 00 00 80 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 41 20 00 00 01 20 00 00 00 00 00 00 3c 10 6d 00
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01
> 40: 3c 10 6d 00 01 00 02 c0 00 00 00 00 00 00 00 00
> 50: 41 20 00 00 01 20 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:00:02.0 USB Controller: nVidia Corporation: Unknown device 00d7
> (rev a5)
> 00: de 10 d7 00 07 00 b0 00 a5 10 03 0c 00 00 80 00
> 10: 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01
> 40: de 10 80 0c 01 00 02 fe 00 00 00 00 02 00 00 00
> 50: 00 00 00 00 1d 47 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 10 ff ff ff 04 14 30 07
> 
> 0000:00:02.1 USB Controller: nVidia Corporation: Unknown device 00d7
> (rev a5)
> 00: de 10 d7 00 07 00 b0 00 a5 10 03 0c 00 00 80 00
> 10: 00 10 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01
> 40: de 10 80 0c 01 00 02 fe 00 00 00 00 03 00 00 00
> 50: 00 00 00 00 1d 47 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 10 ff ff ff 04 14 30 07
> 
> 0000:00:02.2 USB Controller: nVidia Corporation: Unknown device 00d8
> (rev a2)
> 00: de 10 d8 00 06 00 b0 00 a2 20 03 0c 00 00 80 00
> 10: 00 40 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
> 30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 03 03 01
> 40: de 10 80 0c 0a 80 80 20 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 20 20 01 00 00 60 98 01 c3 13 00 00 00 00 00 00
> 70: 00 00 00 04 00 10 30 80 89 3d 84 22 e7 25 04 80
> 80: 01 00 02 fe 00 00 00 00 00 00 00 00 15 16 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 01 00 00 00 00 00 08 e0 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 10 ff ff ff 00 00 30 07
> 
> 0000:00:06.0 Multimedia audio controller: nVidia Corporation: Unknown
> device 00da (rev a2)
> 00: de 10 da 00 07 00 b0 00 a2 00 01 04 00 00 80 00
> 10: 01 14 00 00 01 1c 00 00 00 20 00 e0 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 02 05
> 40: 3c 10 6d 00 01 00 02 06 00 00 00 00 06 01 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 10 ff ff ff 00 00 30 07
> 
> 0000:00:06.1 Modem: nVidia Corporation: Unknown device 00d9 (rev a2)
> 00: de 10 d9 00 03 00 b0 00 a2 00 03 07 00 00 80 00
> 10: 01 18 00 00 81 1c 00 00 00 30 00 e0 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 02 05
> 40: 3c 10 6d 00 01 00 02 80 00 00 00 00 07 01 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 10 ff ff ff 00 00 30 07
> 
> 0000:00:08.0 IDE interface: nVidia Corporation: Unknown device 00d5 (rev
> a5)
> 00: de 10 d5 00 05 00 b0 00 a5 8a 01 01 00 00 00 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 81 20 00 00 00 00 00 00 00 00 00 00 de 10 80 0c
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01
> 40: de 10 80 0c 01 00 02 00 00 00 00 00 00 09 00 00
> 50: 03 f0 00 00 00 00 00 00 a8 20 a8 20 22 00 20 20
> 60: 00 03 00 c6 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 88 1c 1e 00 00 02 2c 00 f0 2f 1e
> 90: 00 00 18 34 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 12 ff ff ff 08 11 30 07
> 
> 0000:00:0a.0 PCI bridge: nVidia Corporation: Unknown device 00dd (rev
> a2)
> 00: de 10 dd 00 07 01 a0 00 a2 00 04 06 00 00 01 00
> 10: 00 00 00 00 00 00 00 00 00 02 02 80 30 70 80 a2
> 20: 10 e0 70 e1 f0 ff 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 02
> 40: 00 00 03 00 01 00 02 00 01 00 00 00 00 00 04 00
> 50: 00 00 fe 1f 00 00 00 00 ff 1f 00 00 03 00 80 00
> 60: 00 00 80 00 00 00 00 00 00 00 00 00 03 00 90 00
> 70: 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:00:0b.0 PCI bridge: nVidia Corporation: Unknown device 00d2 (rev
> a4)
> 00: de 10 d2 00 07 01 20 02 a4 00 04 06 00 10 01 00
> 10: 00 00 00 00 00 00 00 00 00 01 01 0a f0 00 20 22
> 20: 00 e2 f0 e2 00 f0 00 f8 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 0f 00
> 40: 01 00 00 00 00 00 f0 1f 20 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 10 ff ff ff ff ff ff ff ff
> 60: ff 40 ff 40 00 00 00 20 00 00 00 20 ff ff ff ff
> 70: ff ff ff ff 00 00 00 00 00 00 00 00 ff ff ff ff
> 80: ff ff ff ff 00 80 00 00 ea 01 00 00 ff ff ff ff
> 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> a0: 17 02 00 1f 00 00 00 00 0c 00 00 00 00 00 00 00
> b0: 04 07 00 00 00 00 00 00 01 00 00 00 00 00 00 00
> c0: 00 00 00 00 20 00 00 00 00 00 30 07 00 00 30 07
> d0: 00 00 00 00 00 00 00 00 08 00 00 e8 ff ff ff 07
> e0: 00 00 50 02 00 00 51 02 00 00 50 02 00 00 51 02
> f0: 00 00 50 02 00 00 51 02 00 00 50 02 00 00 51 02
> 
> 0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
> 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
> 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
> 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
> 60: 00 00 00 00 e4 00 00 00 0f cc 00 0f 4c 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 08 00 01 21 20 00 11 10 22 04 75 80 02 00 00 00
> 90: 56 04 51 02 00 00 ff 00 07 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
> 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 40: 03 00 00 00 00 00 1f 00 00 00 20 00 01 00 00 00
> 50: 00 00 20 00 02 00 00 00 00 00 20 00 03 00 00 00
> 60: 00 00 20 00 04 00 00 00 00 00 20 00 05 00 00 00
> 70: 00 00 20 00 06 00 00 00 00 00 20 00 07 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 03 0a 00 00 00 0b 00 00 03 00 20 00 00 0b fe 00
> c0: 00 00 00 00 00 00 00 00 13 10 00 00 00 f0 0f 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
> 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 40: 01 00 00 00 01 04 00 00 01 08 00 00 01 0c 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 f2 e0 01 00 f2 e0 01 00 f2 e0 01 00 f2 e0 01
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 22 00 00 00 00 00 00 00 35 33 72 13 30 0a 00 00
> 90: 00 8c 0c 08 06 08 5b 0e 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 5a 62 bc 5f 21 00 00 00 ef 5f 02 9b 6a 39 ef 85
> c0: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 68 82 04 2a 24 10 80 0a 80 8a 00 c2 60 24 80 80
> e0: 14 8b 60 84 34 08 42 0b a3 79 08 f0 20 01 00 1d
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
> 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 40: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
> 50: 48 08 00 00 00 00 00 00 00 00 00 00 c0 86 1a fd
> 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00
> 80: 61 63 07 63 13 41 13 61 00 00 00 00 00 00 00 00
> 90: 05 00 00 00 74 00 00 00 00 50 02 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 30 00 00 80 57 1c 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 01 07 0d 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 20 08 50 00 08 01 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:01:00.0 VGA compatible controller: nVidia Corporation NV17
> [GeForce4 440 Go 64M] (rev a3)
> 00: de 10 79 01 07 00 b0 02 a3 00 00 03 00 40 00 00
> 10: 00 00 00 e2 08 00 00 f0 08 00 00 f8 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
> 30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 05 01
> 40: 3c 10 6d 00 02 00 20 00 17 00 00 1f 00 00 00 00
> 50: 01 00 00 00 01 00 00 00 ce d6 23 00 0f 00 00 00
> 60: 01 44 02 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:02:00.0 FireWire (IEEE 1394): Texas Instruments TSB43AB21
> IEEE-1394a-2000 Controller (PHY/Link)
> 00: 4c 10 26 80 16 01 10 02 00 10 00 0c 10 40 00 00
> 10: 00 80 10 e0 00 00 10 e0 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 02 04
> 40: 00 00 00 00 01 00 02 7e 00 80 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00
> f0: 00 00 00 00 00 10 00 00 3c 10 6d 00 00 00 00 00
> 
> 0000:02:01.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
> RTL-8139/8139C/8139C+ (rev 10)
> 00: ec 10 39 81 07 01 90 02 10 00 00 02 00 40 00 00
> 10: 01 70 00 00 00 88 10 e0 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
> 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 20 40
> 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:02:02.0 Network controller: Broadcom Corporation BCM94306 802.11g
> (rev 03)
> 00: e4 14 20 43 06 01 00 00 03 00 80 02 00 40 00 00
> 10: 00 40 10 e0 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 f4 12
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00
> 40: 01 00 c2 07 00 40 00 00 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 10 00 18 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:02:04.0 CardBus bridge: Texas Instruments: Unknown device ac54 (rev
> 01)
> 00: 4c 10 54 ac 07 00 10 02 01 00 07 06 04 a8 82 00
> 10: 00 60 10 e0 a0 00 00 02 02 03 06 b0 00 00 20 e0
> 20: 00 f0 3f e0 00 00 40 e0 00 f0 5f e0 00 40 00 00
> 30: fc 40 00 00 00 44 00 00 fc 44 00 00 0b 01 c0 05
> 40: 3c 10 6d 00 01 00 00 00 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 61 f0 44 08 19 00 00 10 07 00 03 00 22 1d 11 01
> 90: c0 22 64 60 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 01 00 12 fe 00 00 c0 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:02:04.1 CardBus bridge: Texas Instruments: Unknown device ac54 (rev
> 01)
> 00: 4c 10 54 ac 07 00 10 02 01 00 07 06 04 a8 82 00
> 10: 00 70 10 e0 a0 00 00 02 02 07 0a b0 00 00 00 e1
> 20: 00 f0 3f e1 00 00 c0 e0 00 f0 ff e0 00 60 00 00
> 30: fc 6f 00 00 00 50 00 00 fc 5f 00 00 0a 02 c0 05
> 40: 3c 10 6d 00 01 00 00 00 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 61 f1 44 08 19 00 00 10 07 00 03 00 22 1d 11 01
> 90: c0 22 64 60 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 01 00 12 fe 00 00 c0 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> 0000:02:04.2 System peripheral: Texas Instruments: Unknown device 8201
> (rev 01)
> 00: 4c 10 01 82 07 01 10 02 01 00 80 08 10 40 00 00
> 10: 01 74 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 6d 00
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 07 04
> 40: 00 00 00 00 01 00 02 00 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 02 00 00 00 fc 00 01 00 0a 00 0f 00 10 30 d3 1f
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From Stephen.Kimball at bench.com  Wed Mar  2 08:10:00 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed Mar  2 08:10:00 2005
Subject: FILO dependencies
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40B9C@nh-ex01.nh.bench.com>

I'm using FILO with nVidia reference board with a CK804. I've got LinuxBIOS to load FILO and FILO sees the IDE controller but not the drive.  I thought FILO was device independent, but could the IDE controllers on the CK804 require FILO changes?
Thanks.

Steve

----------------------- serial output -----------------------------------
Press <Enter> for default boot, or <Esc> for boot prompt...
boot: hdc1:/boot/vmlinuz-2.6.9-1.667smp initrd=hdc1:/boot/initrd-2.6.9-1.667smp.img
 root=LABEL=/1 console=tty0 console=ttyS0,115200 desktop splash=silent showopts
malloc_diag: alloc: 624 bytes (5 blocks), free: 15752 bytes (1 blocks)
malloc_diag: alloc: 640 bytes (6 blocks), free: 15736 bytes (1 blocks)
file_open: dev=hdc1, path=/boot/vmlinuz-2.6.9-1.667smp
find_ide_controller: found PCI IDE controller 10de:0053 prog_if=0x8a
find_ide_controller: secodary channel: compatibility mode
find_ide_controller: cmd_base=0x170 ctrl_base=0x374
Detected floating bus
No drive detected on IDE channel 1
devopen: failed to open ide
malloc_diag: alloc: 624 bytes (5 blocks), free: 15752 bytes (1 blocks)
malloc_diag: alloc: 456 bytes (4 blocks), free: 15920 bytes (1 blocks)
boot: hdc1:/boot/vmlinuz-2.6.9-1.667smp initrd=hdc1:/boot/initrd-2.6.9-1.667smp.img
 root=LABEL=/1 console=tty0 console=ttyS0,115200 desktop splash=silent showopts
malloc_diag: alloc: 624 bytes (5 blocks), free: 15752 bytes (1 blocks)
malloc_diag: alloc: 640 bytes (6 blocks), free: 15736 bytes (1 blocks)
file_open: dev=hdc1, path=/boot/vmlinuz-2.6.9-1.667smp
Drive 2 does not exist
devopen: failed to open ide
malloc_diag: alloc: 624 bytes (5 blocks), free: 15752 bytes (1 blocks)
malloc_diag: alloc: 456 bytes (4 blocks), free: 15920 bytes (1 blocks)
boot: hdc1:/boot/vmlinuz-2.6.9-1.667smp initrd=hdc1:/boot/initrd-2.6.9-1.667smp.img
 root=LABEL=/1 console=tty0 console=ttyS0,115200 desktop splash=silent showopts


From rminnich at lanl.gov  Wed Mar  2 08:23:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 08:23:01 2005
Subject: FILO dependencies
In-Reply-To: <9B124F08B3EFDA4F8813B05102DC719503A40B9C@nh-ex01.nh.bench.com>
References: <9B124F08B3EFDA4F8813B05102DC719503A40B9C@nh-ex01.nh.bench.com>
Message-ID: <Pine.LNX.4.58.0503021158170.23155@enigma.lanl.gov>


On Wed, 2 Mar 2005 Stephen.Kimball at bench.com wrote:

> 
> I'm using FILO with nVidia reference board with a CK804. I've got
> LinuxBIOS to load FILO and FILO sees the IDE controller but not the
> drive.  I thought FILO was device independent, but could the IDE
> controllers on the CK804 require FILO changes?

Wow, you've taken this far. 

Not sure yet. I need  a board, so guess we'll order some.
ron


From stepan at openbios.org  Wed Mar  2 08:31:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed Mar  2 08:31:00 2005
Subject: FILO dependencies
In-Reply-To: <9B124F08B3EFDA4F8813B05102DC719503A40B9C@nh-ex01.nh.bench.com>
References: <9B124F08B3EFDA4F8813B05102DC719503A40B9C@nh-ex01.nh.bench.com>
Message-ID: <20050302190640.GA8517@openbios.org>

* Stephen.Kimball at bench.com <Stephen.Kimball at bench.com> [050302 19:40]:
> 
> I'm using FILO with nVidia reference board with a CK804. I've got
> LinuxBIOS to load FILO and FILO sees the IDE controller but not the
> drive.  I thought FILO was device independent, but could the IDE
> controllers on the CK804 require FILO changes?  Thanks.

You should be using 0.4.2 and be sure to set
PCI_BRUTE_SCAN = 1

You probably end up with filo not looking at anything but bus 0.
Common problem on amd64 boards.

Stefan




From yinghailu at gmail.com  Wed Mar  2 08:59:00 2005
From: yinghailu at gmail.com (yhlu)
Date: Wed Mar  2 08:59:00 2005
Subject: FILO dependencies
In-Reply-To: <20050302190640.GA8517@openbios.org>
References: <9B124F08B3EFDA4F8813B05102DC719503A40B9C@nh-ex01.nh.bench.com>
	 <20050302190640.GA8517@openbios.org>
Message-ID: <2ea3fae1050302113453120634@mail.gmail.com>

Why not try Etherboot at first? That would be easier.


On Wed, 2 Mar 2005 20:06:40 +0100, Stefan Reinauer <stepan at openbios.org> wrote:
> * Stephen.Kimball at bench.com <Stephen.Kimball at bench.com> [050302 19:40]:
> >
> > I'm using FILO with nVidia reference board with a CK804. I've got
> > LinuxBIOS to load FILO and FILO sees the IDE controller but not the
> > drive.  I thought FILO was device independent, but could the IDE
> > controllers on the CK804 require FILO changes?  Thanks.
> 
> You should be using 0.4.2 and be sure to set
> PCI_BRUTE_SCAN = 1
> 
> You probably end up with filo not looking at anything but bus 0.
> Common problem on amd64 boards.
> 
> Stefan
> 
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From ollie at lanl.gov  Wed Mar  2 09:28:00 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Wed Mar  2 09:28:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <20050302154116.GB581@openbios.org>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
	 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
	 <20050301154031.GE15145@foo.birdnet.se>
	 <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
	 <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
	 <8a0c367805030207282d68053b@mail.gmail.com> <4225DD05.8070400@powercom.net>
	 <20050302154116.GB581@openbios.org>
Message-ID: <1109793794.4024.12.camel@logarithm.lanl.gov>

On Wed, 2005-03-02 at 08:41, Stefan Reinauer wrote:
> * Justin C. Darby <jdarby at powercom.net> [050302 16:34]:
> > If someone can point me in the right direction (in the source, I'd 
> > guess) to find all of the configuration options without descriptions I 
> > can setup a page dedicated to explaining them one at a time.
>  
> freebios2/src/config/Options.lb
> 
> 


I think another problem of the config tool is the syntax and
semantics of the configure language. Most people have problem
understand the keywords used in the language (device, chip,
pci_domain). And the language is not context free neither
(links <-> number of instances of a device listed). We really
need a good documentation on the config tool.

BTW, the config.g is really diffcult to understand too.

Ollie
 



From rminnich at lanl.gov  Wed Mar  2 10:04:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 10:04:01 2005
Subject: FILO dependencies
In-Reply-To: <2ea3fae1050302113453120634@mail.gmail.com>
References: <9B124F08B3EFDA4F8813B05102DC719503A40B9C@nh-ex01.nh.bench.com>
  <20050302190640.GA8517@openbios.org> <2ea3fae1050302113453120634@mail.gmail.com>
Message-ID: <Pine.LNX.4.58.0503021339190.23623@enigma.lanl.gov>


On Wed, 2 Mar 2005, yhlu wrote:

> Why not try Etherboot at first? That would be easier.

we've never found it to be easier, but that is a point of disagreement 
between several places :-)

ron


From Stephen.Kimball at bench.com  Wed Mar  2 11:07:00 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed Mar  2 11:07:00 2005
Subject: FILO dependencies
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40B9E@nh-ex01.nh.bench.com>

I'm using FILO 0.4.2 and have PCI_BRUTE_SCAN=1.  
I found it to be too brute, so I changed it to only scan buses 0,1,2. No need to scan 256 buses.

FILO finds the IDE controller, but the IDE_BASE0 and IDE_BASE1 in FILO's ide.c point to the wrong place.  These are PCI addresses?  Does FILO assume 8111's PCI addresses for it's IDE?

Steve

-----Original Message-----
From: Stefan Reinauer [mailto:stepan at openbios.org] 
Sent: Wednesday, March 02, 2005 2:07 PM
To: Kimball, Stephen
Cc: linuxbios at clustermatic.org
Subject: Re: FILO dependencies

* Stephen.Kimball at bench.com <Stephen.Kimball at bench.com> [050302 19:40]:
> 
> I'm using FILO with nVidia reference board with a CK804. I've got
> LinuxBIOS to load FILO and FILO sees the IDE controller but not the
> drive.  I thought FILO was device independent, but could the IDE
> controllers on the CK804 require FILO changes?  Thanks.

You should be using 0.4.2 and be sure to set
PCI_BRUTE_SCAN = 1

You probably end up with filo not looking at anything but bus 0.
Common problem on amd64 boards.

Stefan




From stepan at openbios.org  Wed Mar  2 11:27:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed Mar  2 11:27:00 2005
Subject: FAQ question fixup
In-Reply-To: <20050302160404.GA1662@openbios.org>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru> <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se> <20050301154031.GE15145@foo.birdnet.se> <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se> <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov> <8a0c367805030207282d68053b@mail.gmail.com> <4225DD05.8070400@powercom.net> <8a0c367805030208007492c87e@mail.gmail.com> <20050302160404.GA1662@openbios.org>
Message-ID: <20050302220218.GA14162@openbios.org>

* Stefan Reinauer <stepan at openbios.org> [050302 17:04]:
> * Richard Smith <smithbone at gmail.com> [050302 17:00]:
> > I've been adding selected info from my V1 FAQ up into the wiki.  The
> > following is some info I compiled up on V1 start up.
> > 
> > If someone(s) would update this for V2 and post it t the wiki I think
> > it would be very useful.

Something along this line. I wrote it about a year ago and never really
used it since so it might be wrong here and there.

--> wiki?

Stefan

-----------------------------------------------------------------------

reset16.[inc|lds]
-----------------
 Description:
  * code placed at reset vector (0xfffffff0)
  * jump to _start in entry16.inc
  * jump to protected_start in entry32.inc (what is this good for??)

 Comments:
  reset16.lds supports ROMBASEs smaller than 0xffff0000. reset16.inc does
  not. Do we ever need anything else on x86 based systems? If not, I
  suggest to drop the conditionals.
  It seems to me that the second jump is later done by entry16.inc, and
  the reset vector is never reached. Is it used by something else?

entry16.[inc|lds]
-----------------
 Description:
  * linker script provides 16bit versions of the addresses (?)
  * switch to protected mode.
  * jump to __protected_start in entry32.inc
 
 Comments:
  Can someone enlighten me on the restriction comments here? given that 
  we are always on a standard x86 system, we are always above
  0xffff0000?

entry32.[inc|lds]
-----------------
 Description:
  * linker script is a noop.
  * sets up all segment registers to the same value. (ROM_CODE_SEG)
  * falls through to bist32.inc

 Comments:
  there's two entry points here, protected_start and __protected_start.
  Are they both needed? protected_start seems to do the same thing as
  the end of entry16.inc.
  The comment states that we do something with memory here. It seems
  this is wrong, since we are far before enabling memory.

bist32.inc
----------
 Description:
  * Checks EAX for BIST failures.
  * if everything is ok, falls through (skipping next 
    files that put code in different sections: reset16.inc,
    cpu_reset.inc, id.inc) On K8 this goes to early_mtrr.inc

early_mtrr.inc
--------------
 Description:
  * set up variable and fixed mtrrs.
  * set up XIP

 Comments:
  Will this hurt C-A-R? Can we somehow derive the XIP addresses from the
  information that we know, making XIP more solid?

failover.c
----------
 Description:
  * romcc generated code
  * if normal boot, we jump into normal image.
  * if cpu reset, we jump into __cpu_reset, which jumps into 
    __main (Where is this one? crt0.base? auto.inc?)
  * if we're running on the second CPU, we jump into normal/fallback
    image (???)
  * if no problems appeared, jump into normal image
  * otherwise fall through (to auto.c ??)

 Comments:
  What's HAVE_REGPARM_SUPPORT? There's a lot of conditions in this file.
  I did not follow all the branches yet. Maybe someone can explain more?
  it seems that __cpu_reset jumps into __main - does this mean the dram
  init survives a cpu reset?


> -------------- part 1: creating init code -----------------------------
>  1) compile romcc
>  2) create option table
>  3) process and compile romcc based code
>  4) create crt0.o from romcc based code
> 
> -------------- part 2: creating payload -------------------------------
>  5) compile all drivers
>  6) compile all objects
>  7) compile static device tree
>  8) link objects and static tree --> linuxbios.a
>  9) create linuxbios_c from start.o, drivers and linuxbios.a
>  a) create linuxbios_payload from linuxbios_c (with or w/o nrv2b)
> 
> -------------- part 3: final image ------------------------------------
>  b) create "linuxbios" from crt0.o (including linuxbios_payload via
>     linker script arch/i386/config/ldscript.lb)
>  c) create romimage linuxbios.rom from "linuxbios" with buildrom






From ramesh_bios at yahoo.com  Wed Mar  2 15:35:01 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Wed Mar  2 15:35:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: 6667
Message-ID: <20050303021017.20231.qmail@web30005.mail.mud.yahoo.com>

Hi, 

Thanks for the hint. I see the BC_XMAP registers
touched in nsc/gx1/gx_setup.inc. 

        .long   BC_XMAP_1, 0x60
        .long   BC_XMAP_2, 0
        .long   BC_XMAP_3, 0

And from the gx1 spec:

---
GX_BASE+800Ch-800Fh BC_XMAP_3 Register (R/W) Default
Value = 00000000h
19:16 F0 F0 Region: Region control field for address
range F0000h to F3FFFh.

Bit Position: Function
3 PCI Accessible: The PCI slave can access this memory
if this bit is set high and if the appropriate Read or
Write Enable
bit is also set high.
2 Cache Enable1: Caching this region of memory is
inhibited if this bit is cleared.
1 Write Enable1: Write operations to this region of
memory are allowed if this bit is set high. If this
bit is cleared, then write
operations in this region are directed to the PCI
master.
0 Read Enable: Read operations to this region of
memory are allowed if this bit is set high. If this
bit is cleared then read
operations in this region are directed to the PCI
master.
---

So 3 looks like the right value to set to enable read
and write. So at first I tried with 0x33333333 just to
see what would happen if I made all those regions
read/write. (I'm still not sure how the gx1 processor
knows what part of SDRAM those regions are mapped to.)
In any case, that results in a hang immediately after
boot. You see just: "LinuxBIOS starting..." Meaning,
you don't see even raminit occur. Then I tried just
0x00030000 and that had the same effect. I then tried
moving the 3 across one by one to see if any would
avoid the hang. But nope, a 3 in any of those nibbles
causes the hang. I then tried to set write only, that
is, a value of 0x2. That does boot. But then one can't
readback the table.

So, I'm stuck. I think I need to figure out how and
where we tell the gx1 what address range maps to the
SDRAM.

--- Ian Smith <ian at abelon.com> wrote:
> Ramesh,
> 
> At 04:02 02/03/2005, ramesh bios wrote:
> >1. Shadow RAM
> >
> >I guess I would need to find a way to tell the
> >northbridge to enable shadow RAM for some range
> around
> >f0000. I looked through the CS5530A datasheet and
> see
> >shadow registers but no mention of shadowing RAM.
> Nor
> >in the GX1 datasheet either. I'm looking for some
> >register in either the GX1 or the CS5530A that
> would
> >enable this. I am looking for some register that
> would
> >enable me to remap the C0000-F0000 address range to
> >somewhere in sdram. Is that the right thing to be
> >looking for?
> 
> I think you may need to look at your settings for
> the BC_XMAP_2 and 
> BC_XMAP_3 registers on the GX1 - these control read
> and write access to the 
> BIOS shadow ram regions.
> 
> >2. Uncompressed payload
> >I'm not sure I understand what this means. Right
> now,
> >my payload is filo. In the build, I see:
> >
> >dd conv=sync bs=196608 if=/bios/filo-0.4.2/filo.elf
> >of=payload.block
> >cat payload.block > romimage
> >
> >Oh, I guess you must mean this stuff:
> >
> >objcopy -O binary linuxbios_c linuxbios_payload.bin
> >./nrv2b e linuxbios_payload.bin
> >linuxbios_payload.nrv2b
> >
> >So I guess there is some kind of compression going
> on
> >there.
> 
> Not sure if you're using Linuxbios V1 or V2 but in
> V1 there is an option in 
> your build config file to turn off compression - you
> probably need 
> something like:
> 
> option CONFIG_COMPRESS=0
> 
> If it's V2 then no doubt there is an equivalent
> there too.
> 
> >Which method would be the right thing to do? I'll
> look
> >at the shadow ram thing first then.
> >
> >Thanks.
> 
> Nope this helps
> 
> Ian
> 
> >--- "Ronald G. Minnich" <rminnich at lanl.gov> wrote:
> > >
> > >
> > > On Tue, 1 Mar 2005, ramesh bios wrote:
> > >
> > > > Strike that. The issue is somewhere with
> > > > copy_pirq_routing_table. IE: why does the copy
> to
> > > > f0000 fail. I had assumed that the 500 address
> was
> > > an
> > > > alternate location that the table was copied
> to.
> > > So
> > > > now, I'm looking at that f000 failure.
> > >
> > >
> > > the copy to f0000 fails because shadow ram is
> not
> > > set up.
> > >
> > > You can fix this one of two ways. One is to
> figure
> > > out how to enable
> > > shadow ram. The second is to make the payload
> > > uncompressed. The copy will
> > > still fail but linux will find the PIRQ table
> > > anyway.
> > >
> > > ron
> > > _______________________________________________
> > > Linuxbios mailing list
> > > Linuxbios at clustermatic.org
> > >
>
>http://www.clustermatic.org/mailman/listinfo/linuxbios
> > >
> >
> >
> >
> >__________________________________
> >Do you Yahoo!?
> >Yahoo! Mail - 250MB free storage. Do more. Manage
> less.
> >http://info.mail.yahoo.com/mail_250
> >_______________________________________________
> >Linuxbios mailing list
> >Linuxbios at clustermatic.org
>
>http://www.clustermatic.org/mailman/listinfo/linuxbios
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


	
		
__________________________________ 
Celebrate Yahoo!'s 10th Birthday! 
Yahoo! Netrospective: 100 Moments of the Web 
http://birthday.yahoo.com/netrospective/


From rminnich at lanl.gov  Wed Mar  2 16:48:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed Mar  2 16:48:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050303021017.20231.qmail@web30005.mail.mud.yahoo.com>
References: <20050303021017.20231.qmail@web30005.mail.mud.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503022021440.24264@enigma.lanl.gov>

for shadow ram, you need to enable writes to go to ram. Later on, when you 
are done with a region, you need to enable reads. 

So the way you do this: figure out which one is for 0xf0000. Enable writes 
(2). At the end of the process, you need to set (3) for the area. 


And, somebody will have to explain how this fits in with the new stuff, as 
I have not looked at shadow ram setup at all in V2!

ron


From ramesh_bios at yahoo.com  Thu Mar  3 04:16:01 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Thu Mar  3 04:16:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: 6667
Message-ID: <20050303145107.9439.qmail@web30007.mail.mud.yahoo.com>

Ok, so I think this means I should:
1. Enable writes for F0000h thru F3FFFh (in
gx_setup.inc) using BC_XMAP_3
2. Copy the pirq table to F0000  as in
pirq_routing.c:copy_pirq_routing_table
3. Enable read and writes for F0000h thru F3FFFh in
pirq_routing.c:verify_copy_pirq_routing_table using
BC_XMAP_3 

I'll give this a shot when I get some time and see how
it goes.  

Thanks.

--- "Ronald G. Minnich" <rminnich at lanl.gov> wrote:
> 
> for shadow ram, you need to enable writes to go to
> ram. Later on, when you 
> are done with a region, you need to enable reads. 
> 
> So the way you do this: figure out which one is for
> 0xf0000. Enable writes 
> (2). At the end of the process, you need to set (3)
> for the area. 
> 
> 
> And, somebody will have to explain how this fits in
> with the new stuff, as 
> I have not looked at shadow ram setup at all in V2!
> 
> ron
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


	
		
__________________________________ 
Celebrate Yahoo!'s 10th Birthday! 
Yahoo! Netrospective: 100 Moments of the Web 
http://birthday.yahoo.com/netrospective/


From Stephen.Kimball at bench.com  Thu Mar  3 05:30:01 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Thu Mar  3 05:30:01 2005
Subject: FILO dependencies
Message-ID: <9B124F08B3EFDA4F8813B05102DC7195029059D1@nh-ex01.nh.bench.com>

Thanks for the suggestions.
FILO is fine. It work best when the CK804's 
IDE configuration registers are setup correctly.

Steve 

-----Original Message-----
From: Ronald G. Minnich [mailto:rminnich at lanl.gov] 
Sent: Wednesday, March 02, 2005 1:59 PM
To: Kimball, Stephen
Cc: linuxbios at clustermatic.org
Subject: Re: FILO dependencies



On Wed, 2 Mar 2005 Stephen.Kimball at bench.com wrote:

> 
> I'm using FILO with nVidia reference board with a CK804. I've got
> LinuxBIOS to load FILO and FILO sees the IDE controller but not the
> drive.  I thought FILO was device independent, but could the IDE
> controllers on the CK804 require FILO changes?

Wow, you've taken this far. 

Not sure yet. I need  a board, so guess we'll order some.
ron


From petekarl at student.chalmers.se  Thu Mar  3 07:23:00 2005
From: petekarl at student.chalmers.se (Peter Karlsson)
Date: Thu Mar  3 07:23:00 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
 <20050301154031.GE15145@foo.birdnet.se> <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
 <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
Message-ID: <Pine.GSO.4.62.0503031655060.3327@bilbo.dd.chalmers.se>

On Wed, 2 Mar 2005, Ronald G. Minnich wrote:

> so, peter, you want to accumulate the Glossary for us :-)

Sure. It's the least I could do. What would be required of me? I just 
downloaded a snapshot (the last time I tried cvs it didn't work), so I'll 
have a look at the code (I'm not good at C or x86 asm though).

A small start might be:
------------------------------------------
I2C - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient 
inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for 
more info.

Code examples(?): ...
------------------------------------------
VID - Vendor ID, a way of identifying the hardware manufacturer. See 
'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and 
'http://pciids.sourceforge.net/' for more info.

A way of obtaining info for your hardware is through the 'lspci' command. 
Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for 
more verbose output.
------------------------------------------
DID - Device ID, a way of identifying the hardware in question. See above 
for more info.
------------------------------------------

Is this too "dumbed-down"? I would like some connection with examples, 
hence the stub in the I2C section. Any 
suggestions/improvements/critique/comments welcome.

And as someone else mentioned that explanation of config options is 
needed; why not use doxygen (or similar tool), which seems a really easy 
way to document the code and outputs, text, html, LaTeX etc.?

Best regards

Peter K


From rminnich at lanl.gov  Thu Mar  3 08:06:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu Mar  3 08:06:01 2005
Subject: Fw: Re: Documentation [was: new FSF campaign ..]
In-Reply-To: <Pine.GSO.4.62.0503031655060.3327@bilbo.dd.chalmers.se>
References: <20050301140629.4b44b208.a.borisov@tesv.tmb.ru>
 <Pine.GSO.4.62.0503011231040.21405@bilbo.dd.chalmers.se>
 <20050301154031.GE15145@foo.birdnet.se> <Pine.GSO.4.62.0503021235320.10589@bilbo.dd.chalmers.se>
 <Pine.LNX.4.58.0503020804440.22810@enigma.lanl.gov>
 <Pine.GSO.4.62.0503031655060.3327@bilbo.dd.chalmers.se>
Message-ID: <Pine.LNX.4.58.0503031140290.26025@enigma.lanl.gov>


On Thu, 3 Mar 2005, Peter Karlsson wrote:

> ------------------------------------------
> I2C - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient
> inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for more
> info.

this is fine.

> And as someone else mentioned that explanation of config options is
> needed; why not use doxygen (or similar tool), which seems a really easy
> way to document the code and outputs, text, html, LaTeX etc.?

Actually, when you build a target, you can then type
make documentation

and should get docs for that board.

ron


From YhLu at tyan.com  Thu Mar  3 09:13:01 2005
From: YhLu at tyan.com (YhLu)
Date: Thu Mar  3 09:13:01 2005
Subject: ABout use LinuxBIOS with Tyan MB
Message-ID: <3174569B9743D511922F00A0C943142308A05756@TYANWEB>

All,

Please email me if you are using LinuxBIOS with Tyan MB esp in production.
Please include MB and usage...
I want to some data to let my company to spend more effect to support
LinuxBIOS and Opensource project.

Regards

YH


From stepan at openbios.org  Thu Mar  3 10:11:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu Mar  3 10:11:01 2005
Subject: Want to stay up to date?
Message-ID: <20050303204641.GA24520@openbios.org>

Hi,

for all those of you using an RSS news reader (like KNewsTicker), you
can get informed about changes of the LinuxBIOS wiki with the following
rss feeds:

Recently changed pages:
http://wiki.linuxbios.org/index.php?title=Special:Recentchanges&feed=rss

New pages:
http://wiki.linuxbios.org/index.php?title=Special:Newpages&feed=rss

I have not succeeded yet putting the News page into an RSS stream yet

Stefan



From YhLu at tyan.com  Thu Mar  3 10:52:00 2005
From: YhLu at tyan.com (YhLu)
Date: Thu Mar  3 10:52:00 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
Message-ID: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>

Anyone tried LinuxBIOS with freeBSD?

regards

YH


From ollie at lanl.gov  Thu Mar  3 11:35:00 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Thu Mar  3 11:35:00 2005
Subject: Want to stay up to date?
In-Reply-To: <20050303204641.GA24520@openbios.org>
References: <20050303204641.GA24520@openbios.org>
Message-ID: <1109887858.13000.5.camel@exponential.lanl.gov>

On Thu, 2005-03-03 at 13:46, Stefan Reinauer wrote:
> Hi,
> 
> for all those of you using an RSS news reader (like KNewsTicker), you
> can get informed about changes of the LinuxBIOS wiki with the following
> rss feeds:
> 
> Recently changed pages:
> http://wiki.linuxbios.org/index.php?title=Special:Recentchanges&feed=rss
> 
> New pages:
> http://wiki.linuxbios.org/index.php?title=Special:Newpages&feed=rss
> 
> I have not succeeded yet putting the News page into an RSS stream yet
> 
> Stefan


Server down?

Server error!
The server encountered an internal error and was unable to complete your
request. Either the server is overloaded or there was an error in a CGI
script. 

If you think this is a server error, please contact the webmaster.


Error 500
wiki.linuxbios.org
Thu Mar 3 23:10:29 2005
Apache/2.0.52 (Linux/SUSE)


Ollie




From stepan at openbios.org  Thu Mar  3 11:53:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu Mar  3 11:53:01 2005
Subject: Want to stay up to date?
In-Reply-To: <1109887858.13000.5.camel@exponential.lanl.gov>
References: <20050303204641.GA24520@openbios.org> <1109887858.13000.5.camel@exponential.lanl.gov>
Message-ID: <20050303222856.GA26953@openbios.org>

* Li-Ta Lo <ollie at lanl.gov> [050303 23:10]:
> 
> Server down?
> 
> Server error!
> The server encountered an internal error and was unable to complete your
> request. Either the server is overloaded or there was an error in a CGI
> script. 
> 
> If you think this is a server error, please contact the webmaster.
 
Big sorry! I'm currently reconfiguring things to make life easier (Nicer
URLs, better nav menu etc) but I broke something temporarily. It should
work again now

Stefan

 


From ramesh_bios at yahoo.com  Thu Mar  3 17:37:01 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Thu Mar  3 17:37:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: 6667
Message-ID: <20050304041256.96418.qmail@web30002.mail.mud.yahoo.com>

Ok, so I tried this specific sequence and it failed.

making region read/write
done making region read/write
Verifing priq routing tables copy at 0xf0000...failed,
f0000=b0 while 87c0=24

Could it be that f0000 is mapped to the flash? I'm
trying to figure out whether that is technically
possible for a gx1? Could the hardware somehow have a
control that maps the 2Mbit flash to that block?

Thanks.

--- ramesh bios <ramesh_bios at yahoo.com> wrote:
> Ok, so I think this means I should:
> 1. Enable writes for F0000h thru F3FFFh (in
> gx_setup.inc) using BC_XMAP_3
> 2. Copy the pirq table to F0000  as in
> pirq_routing.c:copy_pirq_routing_table
> 3. Enable read and writes for F0000h thru F3FFFh in
> pirq_routing.c:verify_copy_pirq_routing_table using
> BC_XMAP_3 
> 
> I'll give this a shot when I get some time and see
> how
> it goes.  
> 
> Thanks.
> 
> --- "Ronald G. Minnich" <rminnich at lanl.gov> wrote:
> > 
> > for shadow ram, you need to enable writes to go to
> > ram. Later on, when you 
> > are done with a region, you need to enable reads. 
> > 
> > So the way you do this: figure out which one is
> for
> > 0xf0000. Enable writes 
> > (2). At the end of the process, you need to set
> (3)
> > for the area. 
> > 
> > 
> > And, somebody will have to explain how this fits
> in
> > with the new stuff, as 
> > I have not looked at shadow ram setup at all in
> V2!
> > 
> > ron
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> >
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> > 
> 
> 
> 	
> 		
> __________________________________ 
> Celebrate Yahoo!'s 10th Birthday! 
> Yahoo! Netrospective: 100 Moments of the Web 
> http://birthday.yahoo.com/netrospective/
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> 

__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 


From ebiederman at lnxi.com  Thu Mar  3 18:27:01 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Thu Mar  3 18:27:01 2005
Subject: Version Control
In-Reply-To: <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
	<Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
	<Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
	<1109611840.16514.10.camel@localhost>
	<Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov>
Message-ID: <m3psygdmvr.fsf_-_@maxwell.lnxi.com>

"Ronald G. Minnich" <rminnich at lanl.gov> writes:

> On Mon, 28 Feb 2005, Josh England wrote:
> 
> > The offer still stands to host SVN for the freebios trees as well as
> > host linuxbios.org, plan9.net, etc....I think the server is close to
> > being ready.  We'll have to figure out how to best transfer the CVS
> > history over to SVN -- I've heard the tools for that are not the best.
> 
> good stuff. I think linuxbios.org web pages will be somewhere but SVN 
> would be nice on the sandia.org host.

For the web pages I don't care.  But for the sources I SVN does not solve
one of our major problems:  Multiple repositories.

Because of the NDA issues inherent in doing LinuxBIOS support before
a chipset is released, and because of forks needed to ensure quality
board ports that vendors can support I don't see multiple repositories
going away.

So arch aka tla appears to be the sane way to go.  It can act as
a shared repository with multiple commiters.  It also handles forks
well.  Arch among other things is drop dead simple to setup.  Pretty
much you need an ssh account that you can place all of your developers
public keys in .ssh/authorized_keys.  From there all of the logic
happens remotely with sftp.  Stefan can probably testify to that a
little more than I can.

I am in the process of prototyping it internally to verify that
everything works properly.  I have already converted my internal
linuxbios tree with 903 changesets.  And have just started doing
a little bit of development on it.  So far all of the important
cases involving multiple branches and multiple repositories
seem to work and are relatively easy to handle.

The big plus of something like this is it will be a lot less work
for me to push my changes to the public tree so everyone will get
them sooner.

The latest version of cscvs is not perfect but it does do an adequate
job of converting a cvs repository into an arch repository.  You just
have to be very patient with it :)  It took about 8 hours to convert
my internal tree.

Ron does this sound like something you would be willing to look at?

Eric


From stepan at openbios.org  Thu Mar  3 21:48:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu Mar  3 21:48:00 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050304041256.96418.qmail@web30002.mail.mud.yahoo.com>
References: <20050304041256.96418.qmail@web30002.mail.mud.yahoo.com>
Message-ID: <20050304082317.GA13306@openbios.org>

* ramesh bios <ramesh_bios at yahoo.com> [050304 05:12]:
> Ok, so I tried this specific sequence and it failed.
> 
> making region read/write
> done making region read/write
> Verifing priq routing tables copy at 0xf0000...failed,
> f0000=b0 while 87c0=24
> 
> Could it be that f0000 is mapped to the flash? I'm
> trying to figure out whether that is technically
> possible for a gx1? Could the hardware somehow have a
> control that maps the 2Mbit flash to that block?

In /dev/bios I've been using the following code to switch between the
ram image and the rom image. I don't have the specs at hand, but you
should look into the specs of device 0x1078:0x0100

static void cs5530_activate(void)
{
        /* Save modified registers for later reset */
        pci_dummy[0]=pci_read(CURRENT,0x52);

        /* enable rom write access */
        pci_write(CURRENT, 0x52, pci_dummy[0]|0x06);

}

static void cs5530_deactivate(void)
{
        pci_write(CURRENT, 0x52, pci_dummy[0]);
}





From stepan at openbios.org  Fri Mar  4 00:42:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Fri Mar  4 00:42:01 2005
Subject: Version Control
In-Reply-To: <m3psygdmvr.fsf_-_@maxwell.lnxi.com>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com> <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu> <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost> <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com>
Message-ID: <20050304111716.GA27004@openbios.org>

* Eric W. Biederman <ebiederman at lnxi.com> [050304 06:02]:
> For the web pages I don't care.  But for the sources I SVN does not solve
> one of our major problems:  Multiple repositories.
 
With the Wiki the web page issue has solved. 

> So arch aka tla appears to be the sane way to go.  It can act as
> a shared repository with multiple commiters.  It also handles forks
> well.  Arch among other things is drop dead simple to setup.  Pretty
> much you need an ssh account that you can place all of your developers
> public keys in .ssh/authorized_keys.  From there all of the logic
> happens remotely with sftp.  Stefan can probably testify to that a
> little more than I can.

Either the authorized_key or a gate keeper can be used.

> I am in the process of prototyping it internally to verify that
> everything works properly.  I have already converted my internal
> linuxbios tree with 903 changesets.  And have just started doing
> a little bit of development on it.  So far all of the important
> cases involving multiple branches and multiple repositories
> seem to work and are relatively easy to handle.

after solving the usual python issues I have cscvs working nicely here
as well. I am in the progress of setting up a tla version of the
repository that is publicly available on openbios.org. It will also be
fed into the repository browser viewarch 

Which one are you using? I have:
hun at n-dimensional.de--2005-public/cscvs--hun--1.2

> Ron does this sound like something you would be willing to look at?

Let the public import finish and then have a look at the repository on
openbios.org. There you can play and find out if you like it.

Stefan




From markuswolters at gmx.de  Fri Mar  4 03:22:01 2005
From: markuswolters at gmx.de (Markus Wolters)
Date: Fri Mar  4 03:22:01 2005
Subject: linuxbios on k7sem with 2.6.x kernel?
Message-ID: <200503040821.j248L3L07925@nwn.definitive.org>

Hallo,

 

I have an old k7sem board and I want to try Linuxbios (v1 or v2) on it. Now
before I kill my board, I have a 

few questions, maybe somebody could answer them to me and give me a helping
hand?

 

Is it possible to use a 2.6 kernel?

Is it possible to use the original bios chip?

And how do I configure and build it with these options, if it is possible?

 

Regards Markus

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From rminnich at lanl.gov  Fri Mar  4 05:36:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri Mar  4 05:36:01 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
Message-ID: <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>


On Thu, 3 Mar 2005, YhLu wrote:

> Anyone tried LinuxBIOS with freeBSD?
> 

I talked to freebsd guys about it. Freebsd makes BIOS calls, so that would 
need to be fixed.

ron


From smithbone at gmail.com  Fri Mar  4 05:46:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Fri Mar  4 05:46:01 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
Message-ID: <8a0c3678050304082037f8dceb@mail.gmail.com>

> > Anyone tried LinuxBIOS with freeBSD?
> >
> 
> I talked to freebsd guys about it. Freebsd makes BIOS calls, so that would
> need to be fixed.

That or see if it works with ADLO.

-- 
Richard A. Smith


From smithbone at gmail.com  Fri Mar  4 05:46:12 2005
From: smithbone at gmail.com (Richard Smith)
Date: Fri Mar  4 05:46:12 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
Message-ID: <8a0c3678050304082037f8dceb@mail.gmail.com>

> > Anyone tried LinuxBIOS with freeBSD?
> >
> 
> I talked to freebsd guys about it. Freebsd makes BIOS calls, so that would
> need to be fixed.

That or see if it works with ADLO.

-- 
Richard A. Smith


From rminnich at lanl.gov  Fri Mar  4 06:02:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri Mar  4 06:02:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <20050304041256.96418.qmail@web30002.mail.mud.yahoo.com>
References: <20050304041256.96418.qmail@web30002.mail.mud.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503040937080.28450@enigma.lanl.gov>


On Thu, 3 Mar 2005, ramesh bios wrote:

> Ok, so I tried this specific sequence and it failed.
> 
> making region read/write

nope. you need to make it write-only, 



> Verifing priq routing tables copy at 0xf0000...failed,

then copy

The make it read-write.

> Could it be that f0000 is mapped to the flash? 

yes, it's supposed to be!


ron


From rminnich at lanl.gov  Fri Mar  4 06:03:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri Mar  4 06:03:01 2005
Subject: Version Control
In-Reply-To: <m3psygdmvr.fsf_-_@maxwell.lnxi.com>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
 <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
 <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost>
 <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>


On Thu, 3 Mar 2005, Eric W. Biederman wrote:

> Ron does this sound like something you would be willing to look at?

by all means!

ron


From rminnich at lanl.gov  Fri Mar  4 06:13:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri Mar  4 06:13:01 2005
Subject: linuxbios on k7sem with 2.6.x kernel?
In-Reply-To: <200503040821.j248L3L07925@nwn.definitive.org>
References: <200503040821.j248L3L07925@nwn.definitive.org>
Message-ID: <Pine.LNX.4.58.0503040947580.28557@enigma.lanl.gov>


On Fri, 4 Mar 2005, Markus Wolters wrote:

> Is it possible to use a 2.6 kernel?

yes

> Is it possible to use the original bios chip?

DON'T DO THAT. if you don't have a backup chip, don't try it.

ron


From rminnich at lanl.gov  Fri Mar  4 06:26:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri Mar  4 06:26:01 2005
Subject: Geode GX1 and IRQ tables
In-Reply-To: <Pine.LNX.4.58.0503040937080.28450@enigma.lanl.gov>
References: <20050304041256.96418.qmail@web30002.mail.mud.yahoo.com>
 <Pine.LNX.4.58.0503040937080.28450@enigma.lanl.gov>
Message-ID: <Pine.LNX.4.58.0503041000500.28557@enigma.lanl.gov>


On Fri, 4 Mar 2005, Ronald G. Minnich wrote:

> 
> 
> On Thu, 3 Mar 2005, ramesh bios wrote:
> 
> > Ok, so I tried this specific sequence and it failed.
> > 
> > making region read/write
> 
> nope. you need to make it write-only, 

arg, I'm not thinking, we are running out of high memory and then RAM. 

So making it read/write should have worked. Blash.

Dump the memory at 0xf0000 BEFORE and AFTER you copy the PIRQ.

ron


From stepan at openbios.org  Fri Mar  4 07:13:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Fri Mar  4 07:13:01 2005
Subject: Version Control
In-Reply-To: <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com> <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu> <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost> <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com> <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
Message-ID: <20050304174830.GA11943@openbios.org>

* Ronald G. Minnich <rminnich at lanl.gov> [050304 17:39]:
> On Thu, 3 Mar 2005, Eric W. Biederman wrote:
> 
> > Ron does this sound like something you would be willing to look at?
> 
> by all means!
 
The repository is there now.

Note: The caches have not been built on the server, so viewarch is
reaaaally slow. This will change soon.

freebios2:
http://www.openbios.org/cgi-bin/viewarch.cgi/stepan at openbios.org--devel/freebios--devel--2.0

freebios:
http://www.openbios.org/cgi-bin/viewarch.cgi/stepan at openbios.org--devel/freebios--devel--1.0






From jdarby at powercom.net  Fri Mar  4 07:42:00 2005
From: jdarby at powercom.net (Justin C. Darby)
Date: Fri Mar  4 07:42:00 2005
Subject: First cluster project
Message-ID: <42879.216.114.15.78.1109960271.squirrel@www.windex.org>

Hi folks,

I'm just posting the first message of what I hope is a few updates to
getting my current work project on-line. Some of you know me from the wiki
(which I've been busy working on the outline of this project for and have
neglected working on the last couple of days).

After getting some very appreicated advice from Yhlu, I'm going to be
installing LinuxBIOS on a three machines as part of a ColdFusion web
server cluster in the very near future. I do not beleive the board we're
going to be using is in the tree yet (but I am assured it will be soon).

The board we're going to use is the Tyan Thunder K8WE (S2895) with the
Ultra 320 SCSI controller. It's going to boot from IDE-CF, and the OS
install will exist on the SCSI disks. All 3 machines will have BIOS
Saviors installed on them (to make emergency repairs easier on my not so
technically inclined coworkers).

I'm going to document (hopefully) the entire process of getting the system
running to the wiki, and if I can get good information from Yhlu and the
rest of you, that will include building everything from source. The plan
right now is to use LinuxBIOS + Etherboot to boot off of the IDE CF card,
since booting from SCSI is more problematic (from what I hear). The
systems will be using ATI Raedon chipset PCI express cards.

This isin't a high capacity cluster in the sense most of you use, but it
is a situation where we need every second to count as this is the first
project we are going to be striving for 99.999 on internally.

Other things we're using and I'm going to be documenting (but not likely
in the wiki for LinuxBIOS).. these may be of interest to some folks here:

* Lustre (If I can get a good dialogue with the ClusterFS folks started..
still waiting to hear from them. I need to mirror two hard disks over
1000mbit tcp/ip for redundancy.)
* Debian/AMD-64 hosting a chrooted CentOS/i386 enviroment to run
ColdFusion (ColdFusion requires RHEL/SUSE server.. we're going to give it
a shot on CentOS because of the absuredly high cost of RHEL/SUSE server in
our enviroment and the fact we can't run a native AMD64 built of it with
ColdFusion anyway).
* A custom loadbalancer module with keepalive for Apache I've written that
I am still trying to get approval for releasing to the public (it's not
quite done yet, anyhow -- only supports GET and POST, not HEAD, and POST
support hasn't been well tested).
* A custom configuration module for Apache that's still experimental on my
part that allows virtualhost definitions to reside on a MySQL (or SQL Lite
to remove the dependancy on MySQL only) server (if I can get this to work,
I will also be pushing to release this to the public).
* A set of patches to ProFTPD to allow authentication over MySQL (these
will likely be contributed back to the ProFTPD development team).

Anyhow, I'll provide more information to anyone who wants it. The idea
isin't 100% intact, yet, we're still hammering out final details.

Justin



From bari at onelabs.com  Fri Mar  4 09:38:01 2005
From: bari at onelabs.com (Bari Ari)
Date: Fri Mar  4 09:38:01 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <8a0c3678050304082037f8dceb@mail.gmail.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov> <8a0c3678050304082037f8dceb@mail.gmail.com>
Message-ID: <4228C1F3.6@onelabs.com>

Richard Smith wrote:

>>>Anyone tried LinuxBIOS with freeBSD?
>>>
>>
>>I talked to freebsd guys about it. Freebsd makes BIOS calls, so that would
>>need to be fixed.
> 
> 
> That or see if it works with ADLO.
> 
Since it's FreeBSD vs Win, it should be easier to make ADLO work if it 
doesn't work right out of the box.

-Bari


From yinghailu at gmail.com  Fri Mar  4 10:50:01 2005
From: yinghailu at gmail.com (yhlu)
Date: Fri Mar  4 10:50:01 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <4228C1F3.6@onelabs.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
Message-ID: <2ea3fae10503041324369dedc1@mail.gmail.com>

where is the ADLO latest code and doc?

YH


On Fri, 04 Mar 2005 14:15:47 -0600, Bari Ari <bari at onelabs.com> wrote:
> Richard Smith wrote:
> 
> >>>Anyone tried LinuxBIOS with freeBSD?
> >>>
> >>
> >>I talked to freebsd guys about it. Freebsd makes BIOS calls, so that would
> >>need to be fixed.
> >
> >
> > That or see if it works with ADLO.
> >
> Since it's FreeBSD vs Win, it should be easier to make ADLO work if it
> doesn't work right out of the box.
> 
> -Bari
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From yinghailu at gmail.com  Fri Mar  4 10:53:03 2005
From: yinghailu at gmail.com (yhlu)
Date: Fri Mar  4 10:53:03 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <4228C1F3.6@onelabs.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
Message-ID: <2ea3fae10503041324369dedc1@mail.gmail.com>

where is the ADLO latest code and doc?

YH


On Fri, 04 Mar 2005 14:15:47 -0600, Bari Ari <bari at onelabs.com> wrote:
> Richard Smith wrote:
> 
> >>>Anyone tried LinuxBIOS with freeBSD?
> >>>
> >>
> >>I talked to freebsd guys about it. Freebsd makes BIOS calls, so that would
> >>need to be fixed.
> >
> >
> > That or see if it works with ADLO.
> >
> Since it's FreeBSD vs Win, it should be easier to make ADLO work if it
> doesn't work right out of the box.
> 
> -Bari
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From bari at onelabs.com  Fri Mar  4 10:59:00 2005
From: bari at onelabs.com (Bari Ari)
Date: Fri Mar  4 10:59:00 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <2ea3fae10503041324369dedc1@mail.gmail.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com> <2ea3fae10503041324369dedc1@mail.gmail.com>
Message-ID: <4228D51B.4090500@onelabs.com>

http://wiki.linuxbios.org/ADLO

-Bari

yhlu wrote:

> where is the ADLO latest code and doc?
> 
> YH
> 



From jrollins at ligo.mit.edu  Fri Mar  4 11:25:00 2005
From: jrollins at ligo.mit.edu (Jamie Rollins)
Date: Fri Mar  4 11:25:00 2005
Subject: ASUS and linuxbios
In-Reply-To: <4228C1F3.6@onelabs.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB> 
 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov> <8a0c3678050304082037f8dceb@mail.gmail.com>
 <4228C1F3.6@onelabs.com>
Message-ID: <Pine.GSO.4.56.0503041654410.259@ligo.mit.edu>

What is the current assesment of linuxbios support with ASUS motherboards?
I'm looking specifically at the K8V-X, but I'm curious about support for
ASUS boards in general.  The K8V-X uses the VIA K8T800 chipset, which
seems to be fairly common.  Is anyone working on this?  Is ASUS amiable to
linuxbios?  What's the word on the street?

Jamie Rollins.


From smithbone at gmail.com  Fri Mar  4 11:37:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Fri Mar  4 11:37:01 2005
Subject: ASUS and linuxbios
In-Reply-To: <Pine.GSO.4.56.0503041654410.259@ligo.mit.edu>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
	 <Pine.GSO.4.56.0503041654410.259@ligo.mit.edu>
Message-ID: <8a0c36780503041412442e157@mail.gmail.com>

> ASUS boards in general.  The K8V-X uses the VIA K8T800 chipset, which
> seems to be fairly common.  Is anyone working on this?  Is ASUS amiable to
> linuxbios?  What's the word on the street?

Not really.  A lot of the ASUS boards worked with so far have special
things done to the SMbus and thus the SPD can't be read with knowing
what bits in the northbridge to tweak.

-- 
Richard A. Smith


From smithbone at gmail.com  Fri Mar  4 11:45:00 2005
From: smithbone at gmail.com (Richard Smith)
Date: Fri Mar  4 11:45:00 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <4228D51B.4090500@onelabs.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
	 <2ea3fae10503041324369dedc1@mail.gmail.com>
	 <4228D51B.4090500@onelabs.com>
Message-ID: <8a0c367805030414206b349033@mail.gmail.com>

On Fri, 04 Mar 2005 15:37:31 -0600, Bari Ari <bari at onelabs.com> wrote:

> http://wiki.linuxbios.org/ADLO
> 

That info is all from my V1 stuff  and ADLO is not in V2 yet.  However
its just a elf payload just like anything else so it will load fine. 
It won't run until you get the shadowing right.

I don't remember what the final result of our V2 shadowing discussion
was.  I seem to remember that we thought we could do an elf location
trick that might make the mainboard specific shadowing in ADLO
unnecessary.

-- 
Richard A. Smith


From smithbone at gmail.com  Fri Mar  4 11:48:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Fri Mar  4 11:48:01 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <4228D51B.4090500@onelabs.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
	 <2ea3fae10503041324369dedc1@mail.gmail.com>
	 <4228D51B.4090500@onelabs.com>
Message-ID: <8a0c367805030414206b349033@mail.gmail.com>

On Fri, 04 Mar 2005 15:37:31 -0600, Bari Ari <bari at onelabs.com> wrote:

> http://wiki.linuxbios.org/ADLO
> 

That info is all from my V1 stuff  and ADLO is not in V2 yet.  However
its just a elf payload just like anything else so it will load fine. 
It won't run until you get the shadowing right.

I don't remember what the final result of our V2 shadowing discussion
was.  I seem to remember that we thought we could do an elf location
trick that might make the mainboard specific shadowing in ADLO
unnecessary.

-- 
Richard A. Smith


From ebiederman at lnxi.com  Sat Mar  5 23:31:00 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sat Mar  5 23:31:00 2005
Subject: Version Control
In-Reply-To: <20050304174830.GA11943@openbios.org>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
	<Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
	<Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
	<1109611840.16514.10.camel@localhost>
	<Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov>
	<m3psygdmvr.fsf_-_@maxwell.lnxi.com>
	<Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
	<20050304174830.GA11943@openbios.org>
Message-ID: <m36505gka9.fsf@maxwell.lnxi.com>

Stefan Reinauer <stepan at openbios.org> writes:

> * Ronald G. Minnich <rminnich at lanl.gov> [050304 17:39]:
> > On Thu, 3 Mar 2005, Eric W. Biederman wrote:
> > 
> > > Ron does this sound like something you would be willing to look at?
> > 
> > by all means!
>  
> The repository is there now.
> 
> Note: The caches have not been built on the server, so viewarch is
> reaaaally slow. This will change soon.
> 
> freebios2:
> http://www.openbios.org/cgi-bin/viewarch.cgi/stepan at openbios.org--devel/freebios--devel--2.0
> 
> 
> freebios:
> http://www.openbios.org/cgi-bin/viewarch.cgi/stepan at openbios.org--devel/freebios--devel--1.0

Stefan I have not looked at it yet but could you look at signing your tree.
That is something we need for a public tree.

Eric





From rminnich at lanl.gov  Sun Mar  6 15:31:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Sun Mar  6 15:31:01 2005
Subject: ASUS and linuxbios
In-Reply-To: <Pine.GSO.4.56.0503041654410.259@ligo.mit.edu>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB> 
 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov> <8a0c3678050304082037f8dceb@mail.gmail.com>
 <4228C1F3.6@onelabs.com> <Pine.GSO.4.56.0503041654410.259@ligo.mit.edu>
Message-ID: <Pine.LNX.4.58.0503061906290.2187@enigma.lanl.gov>

I was talking to ASUS at one point but the conversation faltered. I can 
try again. Pick a mobo you really want to see it done for.

ron



From gnif at spacevs.com  Sun Mar  6 19:07:01 2005
From: gnif at spacevs.com (Geoffrey McRae)
Date: Sun Mar  6 19:07:01 2005
Subject: ASUS and linuxbios
In-Reply-To: <Pine.LNX.4.58.0503061906290.2187@enigma.lanl.gov>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB> 
    <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
    <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
    <Pine.GSO.4.56.0503041654410.259@ligo.mit.edu>
    <Pine.LNX.4.58.0503061906290.2187@enigma.lanl.gov>
Message-ID: <48158.165.12.252.12.1110174163.squirrel@webmail.spacevs.com>

I would like the:
  Asus K8N-E Delux Please
I have a lan cafe with 40 of these machines in it, would be nice to be
running linuxbios in them so I can run a cluster after hours ;D (That is
if they could still boot windows 2000)

> I was talking to ASUS at one point but the conversation faltered. I can
> try again. Pick a mobo you really want to see it done for.
>
> ron
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>




From jsteve17 at yahoo.com  Mon Mar  7 00:29:02 2005
From: jsteve17 at yahoo.com (Jeff Stevens)
Date: Mon Mar  7 00:29:02 2005
Subject: Compilation Problem (overlaping sections)
Message-ID: <20050307110546.10628.qmail@web41403.mail.yahoo.com>

I am trying to compile LinuxBios for a custom
quad-opteron system.  I copied from the amd quartet to
create my build environment.  The Quartet seems to
compile correct, but mine errors out.  Here is a
screen dump:

objcopy -O binary linuxbios_ram linuxbios_ram.bin
./nrv2b e linuxbios_ram.bin linuxbios_ram.nrv2b
input/output = 84556/28434 = 2.974
cp linuxbios_ram.nrv2b linuxbios_ram.rom
gcc -m32 -nostdlib -nostartfiles -static -o linuxbios
-T ldscript.ld crt0.o
/usr/bin/ld: section .reset [fffdfff0 -> fffdffff]
overlaps section .rom [fffd6f16 -> fffe119f]
/usr/bin/ld: section .id [fffdffd7 -> fffdffef]
overlaps section .rom [fffd6f16 -> fffe119f]
collect2: ld returned 1 exit status
make[1]: *** [linuxbios] Error 1
make[1]: Leaving directory
`/usr/src/freebios_030205/freebios2/targets/cwcec/vortex/vortex/normal'
make: *** [normal/linuxbios.rom] Error 1


Please help!

Thanks in advance,
   Jeff Stevens


	
		
__________________________________ 
Celebrate Yahoo!'s 10th Birthday! 
Yahoo! Netrospective: 100 Moments of the Web 
http://birthday.yahoo.com/netrospective/


From jsteve17 at yahoo.com  Mon Mar  7 02:48:00 2005
From: jsteve17 at yahoo.com (Jeff Stevens)
Date: Mon Mar  7 02:48:00 2005
Subject: Compilation Problem (overlaping sections)
In-Reply-To: 6667
Message-ID: <20050307132444.2799.qmail@web41410.mail.yahoo.com>

I'm sorry, I was wrong.  The AMD Quartet doesn't seem
to compile either.  I get the same error!


--- Jeff Stevens <jsteve17 at yahoo.com> wrote:
> I am trying to compile LinuxBios for a custom
> quad-opteron system.  I copied from the amd quartet
> to
> create my build environment.  The Quartet seems to
> compile correct, but mine errors out.  Here is a
> screen dump:
> 
> objcopy -O binary linuxbios_ram linuxbios_ram.bin
> ./nrv2b e linuxbios_ram.bin linuxbios_ram.nrv2b
> input/output = 84556/28434 = 2.974
> cp linuxbios_ram.nrv2b linuxbios_ram.rom
> gcc -m32 -nostdlib -nostartfiles -static -o
> linuxbios
> -T ldscript.ld crt0.o
> /usr/bin/ld: section .reset [fffdfff0 -> fffdffff]
> overlaps section .rom [fffd6f16 -> fffe119f]
> /usr/bin/ld: section .id [fffdffd7 -> fffdffef]
> overlaps section .rom [fffd6f16 -> fffe119f]
> collect2: ld returned 1 exit status
> make[1]: *** [linuxbios] Error 1
> make[1]: Leaving directory
>
`/usr/src/freebios_030205/freebios2/targets/cwcec/vortex/vortex/normal'
> make: *** [normal/linuxbios.rom] Error 1
> 
> 
> Please help!
> 
> Thanks in advance,
>    Jeff Stevens
> 
> 
> 	
> 		
> __________________________________ 
> Celebrate Yahoo!'s 10th Birthday! 
> Yahoo! Netrospective: 100 Moments of the Web 
> http://birthday.yahoo.com/netrospective/
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


	
		
__________________________________ 
Celebrate Yahoo!'s 10th Birthday! 
Yahoo! Netrospective: 100 Moments of the Web 
http://birthday.yahoo.com/netrospective/


From rminnich at lanl.gov  Mon Mar  7 05:30:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon Mar  7 05:30:01 2005
Subject: Compilation Problem (overlaping sections)
In-Reply-To: <20050307132444.2799.qmail@web41410.mail.yahoo.com>
References: <20050307132444.2799.qmail@web41410.mail.yahoo.com>
Message-ID: <Pine.LNX.4.58.0503070906140.3728@enigma.lanl.gov>


On Mon, 7 Mar 2005, Jeff Stevens wrote:

> I'm sorry, I was wrong.  The AMD Quartet doesn't seem
> to compile either.  I get the same error!

sigh, things are growing bigger. 

anybody want to fix this one?

ron


From yinghailu at gmail.com  Mon Mar  7 08:03:00 2005
From: yinghailu at gmail.com (yhlu)
Date: Mon Mar  7 08:03:00 2005
Subject: Compilation Problem (overlaping sections)
In-Reply-To: <Pine.LNX.4.58.0503070906140.3728@enigma.lanl.gov>
References: <20050307132444.2799.qmail@web41410.mail.yahoo.com>
	 <Pine.LNX.4.58.0503070906140.3728@enigma.lanl.gov>
Message-ID: <2ea3fae1050307103921cf1a75@mail.gmail.com>

How about Tyan s4882 in your compile environment? It should be OK.

Please try to set LOG_LEVEL in your MB Config to 7.

YH


On Mon, 7 Mar 2005 09:06:42 -0700 (MST), Ronald G. Minnich
<rminnich at lanl.gov> wrote:
> 
> 
> On Mon, 7 Mar 2005, Jeff Stevens wrote:
> 
> > I'm sorry, I was wrong.  The AMD Quartet doesn't seem
> > to compile either.  I get the same error!
> 
> sigh, things are growing bigger.
> 
> anybody want to fix this one?
> 
> ron
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From yinghailu at gmail.com  Mon Mar  7 08:09:00 2005
From: yinghailu at gmail.com (yhlu)
Date: Mon Mar  7 08:09:00 2005
Subject: ASUS and linuxbios
In-Reply-To: <48158.165.12.252.12.1110174163.squirrel@webmail.spacevs.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
	 <Pine.GSO.4.56.0503041654410.259@ligo.mit.edu>
	 <Pine.LNX.4.58.0503061906290.2187@enigma.lanl.gov>
	 <48158.165.12.252.12.1110174163.squirrel@webmail.spacevs.com>
Message-ID: <2ea3fae1050307104210c3831@mail.gmail.com>

depends if you can get enough Info about MB and chipset.

Anyway SB is easier than NB....

YH


On Mon, 7 Mar 2005 16:42:43 +1100 (EST), Geoffrey McRae
<gnif at spacevs.com> wrote:
> I would like the:
>  Asus K8N-E Delux Please
> I have a lan cafe with 40 of these machines in it, would be nice to be
> running linuxbios in them so I can run a cluster after hours ;D (That is
> if they could still boot windows 2000)
> 
> > I was talking to ASUS at one point but the conversation faltered. I can
> > try again. Pick a mobo you really want to see it done for.
> >
> > ron
> >
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> > http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From dbudko at vmware.com  Mon Mar  7 10:53:01 2005
From: dbudko at vmware.com (Dmitriy Budko)
Date: Mon Mar  7 10:53:01 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
Message-ID: <5A253C86762DE142943F5A47AD31DBB934CB4A@PA-ECLUSTER4.vmware.com>

Does anybody needs LinuxBIOS for VMware virtual machines?
If you want it please describe why do you want it.

Thanks,

Dmitriy Budko,	
the maintainer of VMware's BIOS and chipset



From rminnich at lanl.gov  Mon Mar  7 13:01:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon Mar  7 13:01:00 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <5A253C86762DE142943F5A47AD31DBB934CB4A@PA-ECLUSTER4.vmware.com>
References: <5A253C86762DE142943F5A47AD31DBB934CB4A@PA-ECLUSTER4.vmware.com>
Message-ID: <Pine.LNX.4.58.0503071637120.4804@enigma.lanl.gov>


On Mon, 7 Mar 2005, Dmitriy Budko wrote:

> Does anybody needs LinuxBIOS for VMware virtual machines?
> If you want it please describe why do you want it.

it would sure make it easier to do full-up sims of linuxbios-equipped 
systems.

ron


From stepan at openbios.org  Mon Mar  7 13:33:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Mon Mar  7 13:33:00 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <5A253C86762DE142943F5A47AD31DBB934CB4A@PA-ECLUSTER4.vmware.com>
References: <5A253C86762DE142943F5A47AD31DBB934CB4A@PA-ECLUSTER4.vmware.com>
Message-ID: <20050308000902.GA2921@openbios.org>

* Dmitriy Budko <dbudko at vmware.com> [050307 22:28]:
> Does anybody needs LinuxBIOS for VMware virtual machines?
> If you want it please describe why do you want it.

This sounds very interesting. Having a possibility to test 
LinuxBIOS+payload in vmware would allow easy and comfortable 
payload development in projects such as OpenBIOS, filo or etherboot.

   Stefan



From thomas at wehrspann.de  Mon Mar  7 13:38:00 2005
From: thomas at wehrspann.de (Thomas Wehrspann)
Date: Mon Mar  7 13:38:00 2005
Subject: linuxbios on k7sem with 2.6.x kernel?
In-Reply-To: <200503040821.j248L3L07925@nwn.definitive.org>
References: <200503040821.j248L3L07925@nwn.definitive.org>
Message-ID: <200503080113.10216.thomas@wehrspann.de>

On Friday 04 March 2005 14:57, Markus Wolters wrote:
> Hallo,
> 
>  
> 
> I have an old k7sem board and I want to try Linuxbios (v1 or v2) on it. Now
> before I kill my board, I have a 
> 
I have the same board. Works well with LinuxBIOS v1. 
AFAIK there is currently no v2 support for SiS boards like the K7SEM.

> few questions, maybe somebody could answer them to me and give me a helping
> hand?
> 
>  
> 
> Is it possible to use a 2.6 kernel?
> 
Yes, works here.
The kernel patches with v1 are only for 2.4 kernels. They are not neccessary, 
but perhaps useful, so i ported them to 2.6 a while ago. See here
http://www.clustermatic.org/pipermail/linuxbios/2004-July/008446.html

> Is it possible to use the original bios chip?
> 
Try to get a DiskOnChip Millenium (NOT a DoC 2000). Although they are not 
produced anymore ;-(
Does anyone know if the DoC Millenium Plus (has a  boot capability) is also 
sufficient?

> And how do I configure and build it with these options, if it is possible?
> 
There is a K7SEM HOWTO in the sources.

The last time i checked the CVS, it was broken for K7SEM. Try this patch for a 
workaround
http://www.clustermatic.org/pipermail/linuxbios/2003-August/004354.html


Thomas


From dbudko at vmware.com  Mon Mar  7 17:22:00 2005
From: dbudko at vmware.com (Dmitriy Budko)
Date: Mon Mar  7 17:22:00 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
Message-ID: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>

> From: Ronald G. Minnich
> On Mon, 7 Mar 2005, Dmitriy Budko wrote:
> 
> > Does anybody needs LinuxBIOS for VMware virtual machines?
> > If you want it please describe why do you want it.
> 
> it would sure make it easier to do full-up sims of linuxbios-equipped 
> systems.

So, you don't need it for "production" systems, only for development, 
do you?

How difficult is it to port Intel 440BX chipset support from
V1 to V2?

It seems to me that supporting a new SIO chips (the emulated 
NS PC97338/PC87338) should be easy.


Dmitriy Budko, VMware


From nathanael at gnat.ca  Mon Mar  7 17:25:47 2005
From: nathanael at gnat.ca (Nathanael D. Noblet)
Date: Mon Mar  7 17:25:47 2005
Subject: error snapshots download.
Message-ID: <1110254313.5896.2.camel@platinum.gnat.ca>

So I downloaded the cvs snapshot referenced from the new wiki. It seems
to be a copy of the repository, and not a checkout.(files are .v ) with
all sorts of version information.

Just a FYI.

-- 
Nathanael D. Noblet <nathanael at gnat.ca>
Gnat Solutions



From ebiederman at lnxi.com  Mon Mar  7 17:58:01 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Mar  7 17:58:01 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <8a0c367805030414206b349033@mail.gmail.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	<Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	<8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
	<2ea3fae10503041324369dedc1@mail.gmail.com>
	<4228D51B.4090500@onelabs.com>
	<8a0c367805030414206b349033@mail.gmail.com>
Message-ID: <m3k6oiycv8.fsf@maxwell.lnxi.com>

Richard Smith <smithbone at gmail.com> writes:

> On Fri, 04 Mar 2005 15:37:31 -0600, Bari Ari <bari at onelabs.com> wrote:
> 
> > http://wiki.linuxbios.org/ADLO
> > 
> 
> That info is all from my V1 stuff  and ADLO is not in V2 yet.  However
> its just a elf payload just like anything else so it will load fine. 
> It won't run until you get the shadowing right.
> 
> I don't remember what the final result of our V2 shadowing discussion
> was.  I seem to remember that we thought we could do an elf location
> trick that might make the mainboard specific shadowing in ADLO
> unnecessary.

Right.  We should simply need to enable the shadow memory in V2.
ADLO can take it from there.  We can reexamine if we ever find
memory that has a problem being read-write.

It is weird that ADLO loads in one place and runs in another but
that is largely a non-issue.  We need the a loader that runs
in protected mode.  So whatever I was thinking with ELF tricks
is something we can ignore.

Eric





From ebiederman at lnxi.com  Mon Mar  7 18:08:01 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Mar  7 18:08:01 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
References: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
Message-ID: <m3acpevja9.fsf@maxwell.lnxi.com>

"Dmitriy Budko" <dbudko at vmware.com> writes:

> > From: Ronald G. Minnich
> > On Mon, 7 Mar 2005, Dmitriy Budko wrote:
> > 
> > > Does anybody needs LinuxBIOS for VMware virtual machines?
> > > If you want it please describe why do you want it.
> > 
> > it would sure make it easier to do full-up sims of linuxbios-equipped 
> > systems.
> 
> So, you don't need it for "production" systems, only for development, 
> do you?
> 
> How difficult is it to port Intel 440BX chipset support from
> V1 to V2?

Not terribly hard.  It is more of a time/desire thing.  Does vmware
accurately simulate what is required to bring memory up or do we
get to short cut that.  If the latter the porting could be done
very quickly.  Memory initialization is generally the hard part,
of a LinuxBIOS port and would likely be trivial under vmware :)

> It seems to me that supporting a new SIO chips (the emulated 
> NS PC97338/PC87338) should be easy.

Right it should not be a problem there.

The case that was discussed recently with vmware was to do things
the other way around.  The observation was made that for server
clusters dedicated to running vmware, running LinuxBIOS underneath
could help boot time and cluster management.

Eric


From smithbone at gmail.com  Mon Mar  7 18:29:00 2005
From: smithbone at gmail.com (Richard Smith)
Date: Mon Mar  7 18:29:00 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <m3acpevja9.fsf@maxwell.lnxi.com>
References: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
	 <m3acpevja9.fsf@maxwell.lnxi.com>
Message-ID: <8a0c3678050307210562081588@mail.gmail.com>

> > How difficult is it to port Intel 440BX chipset support from
> > V1 to V2?
> 
> Not terribly hard.  It is more of a time/desire thing.  Does vmware
> accurately simulate what is required to bring memory up or do we

Yep. not to bad.  I've got the beginnings of the port already done.  I
got hung up on getting my dump_spd routine to return somthing else
besides zero.  Its really wierd.  I can actually see the data on the
SMbus happening but I don't ever seem to get a result back.

Like Eric says if you don't have to to the RAM init then it will
probally move really quickly.

I haven't had chance to work on it for a while.  If your are
interested I can whip up a patch vs current cvs and send it to you. 
It's not in the V2 tree.


-- 
Richard A. Smith


From ebiederman at lnxi.com  Mon Mar  7 20:59:01 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Mar  7 20:59:01 2005
Subject: First cluster project
In-Reply-To: <42879.216.114.15.78.1109960271.squirrel@www.windex.org>
References: <42879.216.114.15.78.1109960271.squirrel@www.windex.org>
Message-ID: <m3fyz6k2so.fsf@maxwell.lnxi.com>

"Justin C. Darby" <jdarby at powercom.net> writes:

> * Lustre (If I can get a good dialogue with the ClusterFS folks started..
> still waiting to hear from them. I need to mirror two hard disks over
> 1000mbit tcp/ip for redundancy.)

For the small scale you are looking at,  I recommend you look at
nbd and the linux md layer, or possibly drbd.  I don't believe Lustre
does redundancy in software yet.  If you need an active/active
configuration things are harder.  nfs from the primary to the secondary
would be my first guess there.

Eric


From ebiederman at lnxi.com  Mon Mar  7 23:01:00 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Mon Mar  7 23:01:00 2005
Subject: Version Control
In-Reply-To: <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
	<Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
	<Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
	<1109611840.16514.10.camel@localhost>
	<Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov>
	<m3psygdmvr.fsf_-_@maxwell.lnxi.com>
	<Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
Message-ID: <m33bv6cwc4.fsf@maxwell.lnxi.com>

"Ronald G. Minnich" <rminnich at lanl.gov> writes:

> On Thu, 3 Mar 2005, Eric W. Biederman wrote:
> 
> > Ron does this sound like something you would be willing to look at?
> 
> by all means!

I'm in the prep stages of merging my tree with Stefan's.  This
first merge is going to be as bad anything I have done before but
after that things should be much easier.

I have managed to check Stefan's pgp signatures on his tree and
everything looks good there :)

The next piece to investigate is how we plan on publishing and
committing changes.  The bread and butter of a version control
system.  Ron are you far enough along in playing with arch
that you are ready for that piece of the conversation?

Eric


From stepan at openbios.org  Tue Mar  8 00:02:01 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Tue Mar  8 00:02:01 2005
Subject: Version Control
In-Reply-To: <m33bv6cwc4.fsf@maxwell.lnxi.com>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com> <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu> <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost> <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com> <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov> <m33bv6cwc4.fsf@maxwell.lnxi.com>
Message-ID: <20050308103820.GB3068@openbios.org>

* Eric W. Biederman <ebiederman at lnxi.com> [050308 10:37]:
> The next piece to investigate is how we plan on publishing and
> committing changes.  The bread and butter of a version control
> system.  Ron are you far enough along in playing with arch
> that you are ready for that piece of the conversation?
 
http://www.openbios.org/experience/gnuarch.html and 
http://www.openbios.org/cgi-bin/viewarch.cgi/stepan at openbios.org--devel/

will likely help a bit. Got to add a commit section (which is fairly
easy, doing "tla commit" and maybe some hints for branching and merging.)

We could either use pqm or add ssh keys for each commiter. How many are
there currently?

Stefan



From spirit at reactor.ru  Tue Mar  8 00:22:00 2005
From: spirit at reactor.ru (Alexander Amelkin)
Date: Tue Mar  8 00:22:00 2005
Subject: Build error on the EPIA-M
In-Reply-To: <8a0c367805022714441ac61185@mail.gmail.com>
References: <20050224003326.74249.qmail@web81504.mail.yahoo.com>
 <Pine.LNX.4.58.0502232034570.3731@enigma.lanl.gov>
 <032401c51a2f$2117f350$9901a8c0@newflame>
 <Pine.LNX.4.58.0502240803000.5105@enigma.lanl.gov>
 <036901c51a97$090b8160$9901a8c0@newflame>
 <Pine.LNX.4.58.0502241037111.5365@enigma.lanl.gov>
 <002101c51c84$81219650$9901a8c0@newflame>
 <Pine.BSF.4.62.0502270833470.63359@www.missl.cs.umd.edu>
 <001101c51cec$57762fb0$9901a8c0@newflame>
 <Pine.BSF.4.62.0502271328230.63359@www.missl.cs.umd.edu>
 <8a0c367805022714441ac61185@mail.gmail.com>
Message-ID: <1641756931.20050308135810@amelkin.msk.ru>

Hi!

Richard Smith:

RS> I don't think in-kernel will be enough.  pcmica services depend on the
RS> card manager deamon to detect device insertions and register the
RS> device.  cardmgr is user space.

No, you're a bit wrong. PCMCIA services do not _depend_ on cardmgr.
They may take advantage of it, but do not depend on it. The only case
when you need cardmgr is for removable (not potentially, but actually)
devices. If you place your CF card into EPIA MII once and for all, you
can easily load all your pcmcia drivers manually (or put them
in-kernel) and have a working PCMCIA IDE.


-- 
? ?????????,
 Alexander                          mailto:spirit at reactor.ru



From rminnich at lanl.gov  Tue Mar  8 03:38:00 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  8 03:38:00 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
References: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
Message-ID: <Pine.LNX.4.58.0503080714170.6480@enigma.lanl.gov>


On Mon, 7 Mar 2005, Dmitriy Budko wrote:

> So, you don't need it for "production" systems, only for development, 
> do you?

I would say so. 

> How difficult is it to port Intel 440BX chipset support from
> V1 to V2?

easy. Been done. Ask Richard Smith.

> It seems to me that supporting a new SIO chips (the emulated 
> NS PC97338/PC87338) should be easy.

yes.


ron


From rminnich at lanl.gov  Tue Mar  8 03:47:03 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  8 03:47:03 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <8a0c3678050307210562081588@mail.gmail.com>
References: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
  <m3acpevja9.fsf@maxwell.lnxi.com> <8a0c3678050307210562081588@mail.gmail.com>
Message-ID: <Pine.LNX.4.58.0503080715430.6480@enigma.lanl.gov>


On Mon, 7 Mar 2005, Richard Smith wrote:

> Yep. not to bad.  I've got the beginnings of the port already done.  I
> got hung up on getting my dump_spd routine to return somthing else
> besides zero.  Its really wierd.  I can actually see the data on the
> SMbus happening but I don't ever seem to get a result back.

ah, richard, it just occurred to me. A lot of the spd code starts the op, 
and waits for the 'active' bit to go to 0 in the status. If the CPU is too 
fast, it will sample the 'active' bit before the smbus hardware starts to 
do anything. Then you read back bad data. 

As I found on some chipsets, the CPU can be too fast, and it should:
1. start op
2. wait for 'smbus active' indicator to go to 1
3. wait for 'smbus active' indicator to go to 0

is this by any chance your problem?

ron


From rminnich at lanl.gov  Tue Mar  8 03:49:09 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  8 03:49:09 2005
Subject: Version Control
In-Reply-To: <m33bv6cwc4.fsf@maxwell.lnxi.com>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
 <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
 <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost>
 <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com>
 <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov> <m33bv6cwc4.fsf@maxwell.lnxi.com>
Message-ID: <Pine.LNX.4.58.0503080721380.6480@enigma.lanl.gov>


On Tue, 8 Mar 2005, Eric W. Biederman wrote:

> The next piece to investigate is how we plan on publishing and
> committing changes.  The bread and butter of a version control system.  
> Ron are you far enough along in playing with arch that you are ready for
> that piece of the conversation?

nope. Have not had time to look as I have been sick. Fooey. 

The only issue I worry about is making sure that vendors have One Place To 
Go for as they do know (i.e. sourceforge.net). It seems to me that 
openbios.org could be that place. Sound ok?

ron


From rminnich at lanl.gov  Tue Mar  8 03:51:13 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue Mar  8 03:51:13 2005
Subject: Version Control
In-Reply-To: <20050308103820.GB3068@openbios.org>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
 <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
 <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost>
 <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com>
 <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov> <m33bv6cwc4.fsf@maxwell.lnxi.com>
 <20050308103820.GB3068@openbios.org>
Message-ID: <Pine.LNX.4.58.0503080723360.6480@enigma.lanl.gov>


On Tue, 8 Mar 2005, Stefan Reinauer wrote:

> We could either use pqm or add ssh keys for each commiter. How many are
> there currently?

I think maybe 8 or so active.

ron


From smithbone at gmail.com  Tue Mar  8 04:04:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  8 04:04:01 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <Pine.LNX.4.58.0503080715430.6480@enigma.lanl.gov>
References: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
	 <m3acpevja9.fsf@maxwell.lnxi.com>
	 <8a0c3678050307210562081588@mail.gmail.com>
	 <Pine.LNX.4.58.0503080715430.6480@enigma.lanl.gov>
Message-ID: <8a0c367805030806405265797@mail.gmail.com>

> As I found on some chipsets, the CPU can be too fast, and it should:
> 1. start op
> 2. wait for 'smbus active' indicator to go to 1
> 3. wait for 'smbus active' indicator to go to 0
> 
> is this by any chance your problem?

The code is basiclly a port of the working V1 assembly code converted
to C.  I seem to remember that the V1 code did exactly what you are
talking about.  Perhaps I goofed up a flag polarity or some other core
piece of info while doing it.

I'll whip up a patch today when I get to work and post it up for
anyone interested to look at.  Perhaps a fresh set of eyes will catch
the issue.

I'll need a place to upload to.  Or I guess you can commit to CVS.
Didn't someone mention that they were going to provide space for stuff
like this?

-- 
Richard A. Smith


From smithbone at gmail.com  Tue Mar  8 04:07:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  8 04:07:01 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <Pine.LNX.4.58.0503080714170.6480@enigma.lanl.gov>
References: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
	 <Pine.LNX.4.58.0503080714170.6480@enigma.lanl.gov>
Message-ID: <8a0c367805030806412b48166c@mail.gmail.com>

> > How difficult is it to port Intel 440BX chipset support from
> > V1 to V2?
> 
> easy. Been done. Ask Richard Smith.
> 

Been working on it.  Not even close to done.

-- 
Richard A. Smith


From smithbone at gmail.com  Tue Mar  8 04:10:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  8 04:10:01 2005
Subject: Build error on the EPIA-M
In-Reply-To: <1641756931.20050308135810@amelkin.msk.ru>
References: <20050224003326.74249.qmail@web81504.mail.yahoo.com>
	 <Pine.LNX.4.58.0502240803000.5105@enigma.lanl.gov>
	 <036901c51a97$090b8160$9901a8c0@newflame>
	 <Pine.LNX.4.58.0502241037111.5365@enigma.lanl.gov>
	 <002101c51c84$81219650$9901a8c0@newflame>
	 <Pine.BSF.4.62.0502270833470.63359@www.missl.cs.umd.edu>
	 <001101c51cec$57762fb0$9901a8c0@newflame>
	 <Pine.BSF.4.62.0502271328230.63359@www.missl.cs.umd.edu>
	 <8a0c367805022714441ac61185@mail.gmail.com>
	 <1641756931.20050308135810@amelkin.msk.ru>
Message-ID: <8a0c3678050308064638804bea@mail.gmail.com>

> RS> I don't think in-kernel will be enough.  pcmica services depend on the
> RS> card manager deamon to detect device insertions and register the
> RS> device.  cardmgr is user space.
> 
> No, you're a bit wrong. PCMCIA services do not _depend_ on cardmgr.
> They may take advantage of it, but do not depend on it. The only case
> when you need cardmgr is for removable (not potentially, but actually)
> devices. If you place your CF card into EPIA MII once and for all, you
> can easily load all your pcmcia drivers manually (or put them
> in-kernel) and have a working PCMCIA IDE.

I did a test where I did exactly that. And the IDE device did not
appear until I ran cardmgr  even though both the card bridge driver
and ide-cs were compiled in.

I'm guessing thought that cardmgr just knows the right /proc/ things
to tickle to make the IDE device appear.  Do you happen to know what
those are?

-- 
Richard A. Smith


From jsteve17 at yahoo.com  Tue Mar  8 04:21:01 2005
From: jsteve17 at yahoo.com (Jeff Stevens)
Date: Tue Mar  8 04:21:01 2005
Subject: Compilation Problem (overlaping sections)
In-Reply-To: 6667
Message-ID: <20050308145755.76496.qmail@web41410.mail.yahoo.com>

Yes, the Tyan s4882 seems to compile fine.  I actually
had my LOG_LEVEL set to 6 already, but I tried 7 and
down to 5, and that didn't help.  I also tried
changing the LOG_LEVEL in the amd quartet, compiled
it, and it didn't work either.

Thanks,
  Jeff Stevens

--- yhlu <yinghailu at gmail.com> wrote:
> How about Tyan s4882 in your compile environment? It
> should be OK.
> 
> Please try to set LOG_LEVEL in your MB Config to 7.
> 
> YH
> 
> 
> On Mon, 7 Mar 2005 09:06:42 -0700 (MST), Ronald G.
> Minnich
> <rminnich at lanl.gov> wrote:
> > 
> > 
> > On Mon, 7 Mar 2005, Jeff Stevens wrote:
> > 
> > > I'm sorry, I was wrong.  The AMD Quartet doesn't
> seem
> > > to compile either.  I get the same error!
> > 
> > sigh, things are growing bigger.
> > 
> > anybody want to fix this one?
> > 
> > ron
> > _______________________________________________
> > Linuxbios mailing list
> > Linuxbios at clustermatic.org
> >
>
http://www.clustermatic.org/mailman/listinfo/linuxbios
> >
> 


	
		
__________________________________ 
Celebrate Yahoo!'s 10th Birthday! 
Yahoo! Netrospective: 100 Moments of the Web 
http://birthday.yahoo.com/netrospective/


From Stephen.Kimball at bench.com  Tue Mar  8 04:55:01 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Tue Mar  8 04:55:01 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40BB6@nh-ex01.nh.bench.com>

If you haven't already tried... maybe a few out's to port 0x80 to slow things down.

Steve

-----Original Message-----
From: Richard Smith [mailto:smithbone at gmail.com] 
Sent: Tuesday, March 08, 2005 9:40 AM
To: Ronald G. Minnich
Cc: Dmitriy Budko; Eric W. Biederman; linuxbios at clustermatic.org
Subject: Re: Does anybody needs LinuxBIOS for VMware virtual machines?

> As I found on some chipsets, the CPU can be too fast, and it should:
> 1. start op
> 2. wait for 'smbus active' indicator to go to 1
> 3. wait for 'smbus active' indicator to go to 0
> 
> is this by any chance your problem?

The code is basiclly a port of the working V1 assembly code converted
to C.  I seem to remember that the V1 code did exactly what you are
talking about.  Perhaps I goofed up a flag polarity or some other core
piece of info while doing it.

I'll whip up a patch today when I get to work and post it up for
anyone interested to look at.  Perhaps a fresh set of eyes will catch
the issue.

I'll need a place to upload to.  Or I guess you can commit to CVS.
Didn't someone mention that they were going to provide space for stuff
like this?

-- 
Richard A. Smith
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


From smithbone at gmail.com  Tue Mar  8 05:05:01 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  8 05:05:01 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <9B124F08B3EFDA4F8813B05102DC719503A40BB6@nh-ex01.nh.bench.com>
References: <9B124F08B3EFDA4F8813B05102DC719503A40BB6@nh-ex01.nh.bench.com>
Message-ID: <8a0c367805030807416cf98d27@mail.gmail.com>

On Tue, 8 Mar 2005 10:31:41 -0500, Stephen.Kimball at bench.com
<Stephen.Kimball at bench.com> wrote:
> If you haven't already tried... maybe a few out's to port 0x80 to slow things down.

Thats a pretty quick and easy test.  I'll do that in a bit and see what happens.

-- 
Richard A. Smith


From smithbone at gmail.com  Tue Mar  8 12:24:00 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  8 12:24:00 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <8a0c367805030807416cf98d27@mail.gmail.com>
References: <9B124F08B3EFDA4F8813B05102DC719503A40BB6@nh-ex01.nh.bench.com>
	 <8a0c367805030807416cf98d27@mail.gmail.com>
Message-ID: <8a0c36780503080916476cd56f@mail.gmail.com>

> <Stephen.Kimball at bench.com> wrote:
> > If you haven't already tried... maybe a few out's to port 0x80 to slow things down.
> 
> Thats a pretty quick and easy test.  I'll do that in a bit and see what happens.

No change.  I still get all 0xff's (not all zeros like I said earlier)  

I think I'm a victim of my own cleverness.  Digging back into the code
I now rember that my port is _not_ just a port of the V1 assembly. 
Its a total rewrite.

My port is heavly based on the AMD solo board.  Thats the mainboard
that had a superIO closest to mine and out of all the boards I looked
at the AMD north and southbridge code was the cleanist and easiest to
follow.  So I basically took the smbus code from the amd8111 and
changed the register defines and bit flags to match the i440bx.

Well at least thats the theory.  Obviously I got something wrong.  The
structure for the sm_bus read already has a delay function in it.  It
was only one out(80,80) I bumped it up to 6 but no change.

I suspect that one of my flags is just incorrect.  What needs to
happen is lots of debug prints to watch the status register and verify
that a single read really does the right thing.

I was kinda hopeing it would just "work".  Sigh.  

I can't really mess with it again till this weekend but if someone
else wants the code let me know.

-- 
Richard A. Smith


From yinghailu at gmail.com  Tue Mar  8 12:54:00 2005
From: yinghailu at gmail.com (yhlu)
Date: Tue Mar  8 12:54:00 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <m3k6oiycv8.fsf@maxwell.lnxi.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
	 <2ea3fae10503041324369dedc1@mail.gmail.com>
	 <4228D51B.4090500@onelabs.com>
	 <8a0c367805030414206b349033@mail.gmail.com>
	 <m3k6oiycv8.fsf@maxwell.lnxi.com>
Message-ID: <2ea3fae105030809536638fa24@mail.gmail.com>

So need to make shadowing work in V2 before make ADLO working...?

which region?

YH



On 07 Mar 2005 21:34:35 -0700, Eric W. Biederman <ebiederman at lnxi.com> wrote:
> Richard Smith <smithbone at gmail.com> writes:
> 
> > On Fri, 04 Mar 2005 15:37:31 -0600, Bari Ari <bari at onelabs.com> wrote:
> >
> > > http://wiki.linuxbios.org/ADLO
> > >
> >
> > That info is all from my V1 stuff  and ADLO is not in V2 yet.  However
> > its just a elf payload just like anything else so it will load fine.
> > It won't run until you get the shadowing right.
> >
> > I don't remember what the final result of our V2 shadowing discussion
> > was.  I seem to remember that we thought we could do an elf location
> > trick that might make the mainboard specific shadowing in ADLO
> > unnecessary.
> 
> Right.  We should simply need to enable the shadow memory in V2.
> ADLO can take it from there.  We can reexamine if we ever find
> memory that has a problem being read-write.
> 
> It is weird that ADLO loads in one place and runs in another but
> that is largely a non-issue.  We need the a loader that runs
> in protected mode.  So whatever I was thinking with ELF tricks
> is something we can ignore.
> 
> Eric
> 
>


From yinghailu at gmail.com  Tue Mar  8 12:59:00 2005
From: yinghailu at gmail.com (yhlu)
Date: Tue Mar  8 12:59:00 2005
Subject: Compilation Problem (overlaping sections)
In-Reply-To: <20050308145755.76496.qmail@web41410.mail.yahoo.com>
References: <20050308145755.76496.qmail@web41410.mail.yahoo.com>
Message-ID: <2ea3fae105030809543801ff1c@mail.gmail.com>

So get start from s4882 or wait someone have time to fix amd quartet.

YH


On Tue, 8 Mar 2005 06:57:55 -0800 (PST), Jeff Stevens
<jsteve17 at yahoo.com> wrote:
> Yes, the Tyan s4882 seems to compile fine.  I actually
> had my LOG_LEVEL set to 6 already, but I tried 7 and
> down to 5, and that didn't help.  I also tried
> changing the LOG_LEVEL in the amd quartet, compiled
> it, and it didn't work either.
> 
> Thanks,
>  Jeff Stevens
> 
> --- yhlu <yinghailu at gmail.com> wrote:
> > How about Tyan s4882 in your compile environment? It
> > should be OK.
> >
> > Please try to set LOG_LEVEL in your MB Config to 7.
> >
> > YH
> >
> >
> > On Mon, 7 Mar 2005 09:06:42 -0700 (MST), Ronald G.
> > Minnich
> > <rminnich at lanl.gov> wrote:
> > >
> > >
> > > On Mon, 7 Mar 2005, Jeff Stevens wrote:
> > >
> > > > I'm sorry, I was wrong.  The AMD Quartet doesn't
> > seem
> > > > to compile either.  I get the same error!
> > >
> > > sigh, things are growing bigger.
> > >
> > > anybody want to fix this one?
> > >
> > > ron
> > > _______________________________________________
> > > Linuxbios mailing list
> > > Linuxbios at clustermatic.org
> > >
> >
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> > >
> >
> 
> __________________________________
> Celebrate Yahoo!'s 10th Birthday!
> Yahoo! Netrospective: 100 Moments of the Web
> http://birthday.yahoo.com/netrospective/
>


From yinghailu at gmail.com  Tue Mar  8 13:01:06 2005
From: yinghailu at gmail.com (yhlu)
Date: Tue Mar  8 13:01:06 2005
Subject: error snapshots download.
In-Reply-To: <1110254313.5896.2.camel@platinum.gnat.ca>
References: <1110254313.5896.2.camel@platinum.gnat.ca>
Message-ID: <2ea3fae105030809555a8fe41a@mail.gmail.com>

Then you need to set up one CVS server local to use it...


On Mon, 07 Mar 2005 19:58:33 -0800, Nathanael D. Noblet
<nathanael at gnat.ca> wrote:
> So I downloaded the cvs snapshot referenced from the new wiki. It seems
> to be a copy of the repository, and not a checkout.(files are .v ) with
> all sorts of version information.
> 
> Just a FYI.
> 
> --
> Nathanael D. Noblet <nathanael at gnat.ca>
> Gnat Solutions
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From yinghailu at gmail.com  Tue Mar  8 13:03:10 2005
From: yinghailu at gmail.com (yhlu)
Date: Tue Mar  8 13:03:10 2005
Subject: Version Control
In-Reply-To: <Pine.LNX.4.58.0503080723360.6480@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
	 <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
	 <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
	 <1109611840.16514.10.camel@localhost>
	 <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov>
	 <m3psygdmvr.fsf_-_@maxwell.lnxi.com>
	 <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
	 <m33bv6cwc4.fsf@maxwell.lnxi.com> <20050308103820.GB3068@openbios.org>
	 <Pine.LNX.4.58.0503080723360.6480@enigma.lanl.gov>
Message-ID: <2ea3fae10503080956207fc975@mail.gmail.com>

Can we put the server in US instead of EU?

YH


On Tue, 8 Mar 2005 07:23:50 -0700 (MST), Ronald G. Minnich
<rminnich at lanl.gov> wrote:
> 
> 
> On Tue, 8 Mar 2005, Stefan Reinauer wrote:
> 
> > We could either use pqm or add ssh keys for each commiter. How many are
> > there currently?
> 
> I think maybe 8 or so active.
> 
> ron
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>


From smithbone at gmail.com  Tue Mar  8 13:06:03 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue Mar  8 13:06:03 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <2ea3fae105030809536638fa24@mail.gmail.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	 <Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	 <8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
	 <2ea3fae10503041324369dedc1@mail.gmail.com>
	 <4228D51B.4090500@onelabs.com>
	 <8a0c367805030414206b349033@mail.gmail.com>
	 <m3k6oiycv8.fsf@maxwell.lnxi.com>
	 <2ea3fae105030809536638fa24@mail.gmail.com>
Message-ID: <8a0c3678050308100237c09b93@mail.gmail.com>

On Tue, 8 Mar 2005 09:53:03 -0800, yhlu <yinghailu at gmail.com> wrote:
> So need to make shadowing work in V2 before make ADLO working...?
> 
> which region?
> 

0xf0000 - 0xfffff and 0xc0000- 0xcffff.  Look at util/ADLO/loader.s 
That shows you the ranges.

-- 
Richard A. Smith


From ollie at lanl.gov  Tue Mar  8 13:29:01 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  8 13:29:01 2005
Subject: Does anybody needs LinuxBIOS for VMware virtual machines?
In-Reply-To: <8a0c3678050307210562081588@mail.gmail.com>
References: <5A253C86762DE142943F5A47AD31DBB934CB4F@PA-ECLUSTER4.vmware.com>
	 <m3acpevja9.fsf@maxwell.lnxi.com>
	 <8a0c3678050307210562081588@mail.gmail.com>
Message-ID: <1110306520.3952.3.camel@exponential.lanl.gov>

On Mon, 2005-03-07 at 22:05, Richard Smith wrote:
> > > How difficult is it to port Intel 440BX chipset support from
> > > V1 to V2?
> > 
> > Not terribly hard.  It is more of a time/desire thing.  Does vmware
> > accurately simulate what is required to bring memory up or do we
> 
> Yep. not to bad.  I've got the beginnings of the port already done.  I
> got hung up on getting my dump_spd routine to return somthing else
> besides zero.  Its really wierd.  I can actually see the data on the
> SMbus happening but I don't ever seem to get a result back.
> 


There are two user space program you can try first in the V1 tree.
One is the util/scanspd, the other is util/sis/spd_dump.

Ollie




From ollie at lanl.gov  Tue Mar  8 13:33:31 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  8 13:33:31 2005
Subject: linuxbios on k7sem with 2.6.x kernel?
In-Reply-To: <200503080113.10216.thomas@wehrspann.de>
References: <200503040821.j248L3L07925@nwn.definitive.org>
	 <200503080113.10216.thomas@wehrspann.de>
Message-ID: <1110306670.3952.6.camel@exponential.lanl.gov>

On Mon, 2005-03-07 at 17:13, Thomas Wehrspann wrote:
> > Is it possible to use the original bios chip?
> > 
> Try to get a DiskOnChip Millenium (NOT a DoC 2000). Although they are not 
> produced anymore ;-(
> Does anyone know if the DoC Millenium Plus (has a  boot capability) is also 
> sufficient?

The problem is that the M Plus had different programming sequence. The 
IPL.S and others does not work on it without modification.

Ollie




From stepan at openbios.org  Tue Mar  8 13:35:36 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Tue Mar  8 13:35:36 2005
Subject: Version Control
In-Reply-To: <2ea3fae10503080956207fc975@mail.gmail.com>
References: <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu> <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost> <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com> <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov> <m33bv6cwc4.fsf@maxwell.lnxi.com> <20050308103820.GB3068@openbios.org> <Pine.LNX.4.58.0503080723360.6480@enigma.lanl.gov> <2ea3fae10503080956207fc975@mail.gmail.com>
Message-ID: <20050308183132.GA2434@openbios.org>

* yhlu <yinghailu at gmail.com> [050308 18:56]:
> Can we put the server in US instead of EU?
> 
> YH

The machine is hanging off the second hop from the Frankfurt backbone
over to the US, 7 hops from tyan.com... This should be a _lot_ faster
than sourceforge.net

Have you had throughput/latency problems?

Stefan



From ebiederman at lnxi.com  Tue Mar  8 14:08:00 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Mar  8 14:08:00 2005
Subject: Anyone tried LinuxBIOS with freeBSD?
In-Reply-To: <8a0c3678050308100237c09b93@mail.gmail.com>
References: <3174569B9743D511922F00A0C943142308A05766@TYANWEB>
	<Pine.LNX.4.58.0503040911410.28450@enigma.lanl.gov>
	<8a0c3678050304082037f8dceb@mail.gmail.com> <4228C1F3.6@onelabs.com>
	<2ea3fae10503041324369dedc1@mail.gmail.com>
	<4228D51B.4090500@onelabs.com>
	<8a0c367805030414206b349033@mail.gmail.com>
	<m3k6oiycv8.fsf@maxwell.lnxi.com>
	<2ea3fae105030809536638fa24@mail.gmail.com>
	<8a0c3678050308100237c09b93@mail.gmail.com>
Message-ID: <m3u0nmt0rr.fsf@maxwell.lnxi.com>

Richard Smith <smithbone at gmail.com> writes:

> On Tue, 8 Mar 2005 09:53:03 -0800, yhlu <yinghailu at gmail.com> wrote:
> > So need to make shadowing work in V2 before make ADLO working...?
> > 
> > which region?
> > 
> 
> 0xf0000 - 0xfffff and 0xc0000- 0xcffff.  Look at util/ADLO/loader.s 
> That shows you the ranges.

In general simply making 0xc0000 - 0xfffff memory is a good target
and I think v2 does that by default.

Eric


From ollie at lanl.gov  Tue Mar  8 14:14:00 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue Mar  8 14:14:00 2005
Subject: Version Control
In-Reply-To: <20050304174830.GA11943@openbios.org>
References: 	 <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
	 <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
	 <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
	 <1109611840.16514.10.camel@localhost>
	 <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov>
	 <m3psygdmvr.fsf_-_@maxwell.lnxi.com>
	 <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
	 <20050304174830.GA11943@openbios.org>
Message-ID: <1110309230.3952.9.camel@exponential.lanl.gov>

On Fri, 2005-03-04 at 10:48, Stefan Reinauer wrote:
> * Ronald G. Minnich <rminnich at lanl.gov> [050304 17:39]:
> > On Thu, 3 Mar 2005, Eric W. Biederman wrote:
> > 
> > > Ron does this sound like something you would be willing to look at?
> > 
> > by all means!
>  
> The repository is there now.
> 
> Note: The caches have not been built on the server, so viewarch is
> reaaaally slow. This will change soon.
> 
> freebios2:
> http://www.openbios.org/cgi-bin/viewarch.cgi/stepan at openbios.org--devel/freebios--devel--2.0
> 
> freebios:
> http://www.openbios.org/cgi-bin/viewarch.cgi/stepan at openbios.org--devel/freebios--devel--1.0
> 
> 

what is the tla command for

cvs -d:xxx login
cvs -d:xxx co freebios2

Ollie




From ebiederman at lnxi.com  Tue Mar  8 14:21:01 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Mar  8 14:21:01 2005
Subject: Version Control
In-Reply-To: <1110309230.3952.9.camel@exponential.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
	<Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
	<Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
	<1109611840.16514.10.camel@localhost>
	<Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov>
	<m3psygdmvr.fsf_-_@maxwell.lnxi.com>
	<Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
	<20050304174830.GA11943@openbios.org>
	<1110309230.3952.9.camel@exponential.lanl.gov>
Message-ID: <m3u0nmlzbe.fsf@maxwell.lnxi.com>

Li-Ta Lo <ollie at lanl.gov> writes:

> what is the tla command for
> 
> cvs -d:xxx login
> cvs -d:xxx co freebios2

tla register-archive ftp://ftp.openbios.org/pub/arch/stepan at openbios.org--devel
tla get -A stepan at openbios.org--devel  freebios--devel--2.0

For more information look at:
http://www.openbios.org/experience/gnuarch.html
http://wiki.gnuarch.org/

Eric


From ebiederman at lnxi.com  Tue Mar  8 14:36:00 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Tue Mar  8 14:36:00 2005
Subject: Version Control
In-Reply-To: <Pine.LNX.4.58.0503080721380.6480@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com>
	<Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu>
	<Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov>
	<1109611840.16514.10.camel@localhost>
	<Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov>
	<m3psygdmvr.fsf_-_@maxwell.lnxi.com>
	<Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov>
	<m33bv6cwc4.fsf@maxwell.lnxi.com>
	<Pine.LNX.4.58.0503080721380.6480@enigma.lanl.gov>
Message-ID: <m3oedulyn4.fsf@maxwell.lnxi.com>

"Ronald G. Minnich" <rminnich at lanl.gov> writes:

> On Tue, 8 Mar 2005, Eric W. Biederman wrote:
> 
> > The next piece to investigate is how we plan on publishing and
> > committing changes.  The bread and butter of a version control system.  
> > Ron are you far enough along in playing with arch that you are ready for
> > that piece of the conversation?
> 
> nope. Have not had time to look as I have been sick. Fooey. 
> 
> The only issue I worry about is making sure that vendors have One Place To 
> Go for as they do know (i.e. sourceforge.net). It seems to me that 
> openbios.org could be that place. Sound ok?

Generally.  And certainly it should be the tree we work against.
However one of very nice things about arch is that any with
a file sever can trivially setup a mirror.

But I do agree we do a blessed repository that holds the mainline development.

Eric


From stepan at openbios.org  Tue Mar  8 14:39:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Tue Mar  8 14:39:00 2005
Subject: Version Control
In-Reply-To: <1110309230.3952.9.camel@exponential.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com> <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu> <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost> <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com> <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov> <20050304174830.GA11943@openbios.org> <1110309230.3952.9.camel@exponential.lanl.gov>
Message-ID: <20050308193835.GA8822@openbios.org>

* Li-Ta Lo <ollie at lanl.gov> [050308 20:13]:
> stepan at openbios.org--devel/freebios--devel--2.0
> 
> what is the tla command for
> 
> cvs -d:xxx login
> cvs -d:xxx co freebios2
 
You would do:

* once (preperation to use arch in general and on the openbios.org repos):

  # make TLA know about you 
  tla my-id "Li-Ta Lo <ollie at lanl.gov>" 

  # make TLA know about where to find the code
  tla register-archive ftp://ftp.openbios.org/pub/arch/stepan at openbios.org--devel

  # register key
  wget  http://www.openbios.org/~stepan/gpg/openbios-arch.pub
  gpg --import openbios-arch.pub
  

* then everytime you do a fresh checkout:

  tla get stepan at openbios.org--devel/freebios--devel--2.0 freebios2

  will fetch the tree calling the target directory freebios2

Stefan





From stepan at openbios.org  Tue Mar  8 14:42:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Tue Mar  8 14:42:00 2005
Subject: Version Control
In-Reply-To: <m3u0nmlzbe.fsf@maxwell.lnxi.com>
References: <7D7AEA925A7F724194B1521C75E622DC84DB32@exchfive.olympus.f5net.com> <Pine.GSO.4.56.0502281203500.13663@ligo.mit.edu> <Pine.LNX.4.58.0502281011400.17588@enigma.lanl.gov> <1109611840.16514.10.camel@localhost> <Pine.LNX.4.58.0502281047550.17588@enigma.lanl.gov> <m3psygdmvr.fsf_-_@maxwell.lnxi.com> <Pine.LNX.4.58.0503040938540.28450@enigma.lanl.gov> <20050304174830.GA11943@openbios.org> <1110309230.3952.9.camel@exponential.lanl.gov> <m3u0nmlzbe.fsf@maxwell.lnxi.com>
Message-ID: <20050308193958.GB8822@openbios.org>

* Eric W. Biederman <ebiederman at lnxi.com> [050308 20:20]:
> For more information look at:
> http://www.openbios.org/experience/gnuarch.html
> http://wiki.gnuarch.org/
 
Especially this part of the wiki is probably interesting:
http://wiki.gnuarch.org/moin.cgi/Learning_20Arch_20commands_20for_20CVS_20users

Stefan




From mikey at wirelabs.net  Tue Mar  8 15:41:01 2005
From: mikey at wirelabs.net (Michal Szwaczko)
Date: Tue Mar  8 15:41:01 2005
Subject: Asus TX97-E
Message-ID: <20050308204020.GA23008@matrix>

Hello,

I'm tracking the list, CVS, listening to some really kind folks at 
Freenode's #openbios (Stepan et al) for some time now, but still did't 
find a working Asus TX97 configuration. To the point: 

I have an Asus TX97-_E_ which seems to be really diferent from the one that is
claimed supported in the v1 tree (tx97-le) The difference - from what I can 
gather not being a hw level programmer - is the cache chips and superIO.
I tried many many config options but still, no serial output, the board is 
just plain dead after flashing. Has anyone tried/succeeded in getting 
this board to work? Or can anyone point my mistakes if it should be working
and isn't because I might be making some fundamental errors? 

The cache chips are two of tmtech t35l6432a-60 
The IO chip is: Winbond w83877af 

The config I use is here: 
<URL:http://m.wirelabs.net/mb-config> 

And a little modified (for a different superio)tx97le/Config: 
<URL:http://m.wirelabs.net/Config>

The image builds ok, but I am not sure if it is even workable at minimum 
with those options on that motherboard.
There was a discussion some time ago on this list about similar problem, but 
I don't think I could track down any voice from the developers about this.

Can anyone shed some light on this matter? Point me to any direction?
Thanks

-- 
[ .O. | Micha? 'Mikey' Szwaczko  | GPG Key#:0x653CBD53 ]
[ ..O | Developer/Troubleshooter | GNU Generation Now! ]
[ OOO | There's no spoon.                              ]


From rminnich at lanl.gov  Mon Mar 14 16:50:16 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon, 14 Mar 2005 08:50:16 -0700 (MST)
Subject: [LinuxBIOS] cutting over
Message-ID: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>

linuxbios at openbios.org is the new mailing list. I will shut the old one 
down in a day or two. Hope you call get this.

ron



From talbotx at comcast.net  Mon Mar 14 17:18:05 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Mon, 14 Mar 2005 08:18:05 -0800
Subject: [LinuxBIOS] Status on the EPIA-MII
References: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>
Message-ID: <005501c528b1$6aa72af0$9901a8c0@newflame>

-Ron
What is the status on the EPIA-MII, is the south bridge fixed?
-Adam




From tyson at irobot.com  Mon Mar 14 17:20:18 2005
From: tyson at irobot.com (Tyson Sawyer)
Date: Mon, 14 Mar 2005 11:20:18 -0500
Subject: [LinuxBIOS] cutting over
In-Reply-To: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>
References: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>
Message-ID: <4235B9C2.7010506@irobot.com>

Ronald G. Minnich wrote:
> linuxbios at openbios.org is the new mailing list. I will shut the old one 
> down in a day or two. Hope you call get this.

Do we need to move ourselves over or will the existing list of 
subscribers be moved?

Thanks!
Ty

-- 
Tyson D Sawyer                     iRobot Corporation
Lead Systems Engineer              Government & Industrial Robotics
tsawyer at irobot.com                 Robots for the Real World
781-345-0200 ext 3329              http://www.irobot.com



From sxpert at esitcom.org  Mon Mar 14 17:32:42 2005
From: sxpert at esitcom.org (Amaury Jacquot)
Date: Mon, 14 Mar 2005 17:32:42 +0100
Subject: [LinuxBIOS] about the epia M10000
Message-ID: <4235BCAA.7030806@esitcom.org>

hey guys.
I am running a raid5 array out of an epia M10000, netbooted via the 
official bios' PXE.
I have a problem, in that I have to power cycle the thing to get the PXE 
thing to boot. if I use the "reboot" command, the PXE fails with

Exiting PXE boot rom

or something similar.
would replacing the original bios with LinuxBios solve my problem ?



From rminnich at lanl.gov  Mon Mar 14 17:59:24 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon, 14 Mar 2005 09:59:24 -0700 (MST)
Subject: [LinuxBIOS] Re: Status on the EPIA-MII
In-Reply-To: <005501c528b1$6aa72af0$9901a8c0@newflame>
References: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>
	<005501c528b1$6aa72af0$9901a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0503140958590.22781@enigma.lanl.gov>



On Mon, 14 Mar 2005, Adam Talbot wrote:

> What is the status on the EPIA-MII, is the south bridge fixed?

no, still busted. Actually EPIA is busted too. 

Somebody really busted that south code :-)
ron



From rminnich at lanl.gov  Mon Mar 14 17:59:55 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon, 14 Mar 2005 09:59:55 -0700 (MST)
Subject: [LinuxBIOS] cutting over
In-Reply-To: <4235B9C2.7010506@irobot.com>
References: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>
	<4235B9C2.7010506@irobot.com>
Message-ID: <Pine.LNX.4.58.0503140959320.22781@enigma.lanl.gov>



On Mon, 14 Mar 2005, Tyson Sawyer wrote:

> Do we need to move ourselves over or will the existing list of subscribers be
> moved?

gets moved automagically, (i.e. stefan) but you should be getting dup mail 
emails from linuxbios at openbios.org

ron



From rodmur at maybe.org  Mon Mar 14 19:15:00 2005
From: rodmur at maybe.org (Dale Harris)
Date: Mon, 14 Mar 2005 10:15:00 -0800
Subject: [LinuxBIOS] Linux vs. Open?
Message-ID: <20050314181500.GP3035@maybe.org>

So this is likely a dumb question.  But what is the difference between
LinuxBIOS and OpenBIOS?  


Dale Harris




From stepan at openbios.org  Mon Mar 14 23:39:34 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Mon, 14 Mar 2005 23:39:34 +0100
Subject: [LinuxBIOS] cutting over
In-Reply-To: <Pine.LNX.4.58.0503140959320.22781@enigma.lanl.gov>
References: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>
	<4235B9C2.7010506@irobot.com>
	<Pine.LNX.4.58.0503140959320.22781@enigma.lanl.gov>
Message-ID: <20050314223934.GB13056@openbios.org>

* Ronald G. Minnich <rminnich at lanl.gov> [050314 17:59]:
> 
> 
> On Mon, 14 Mar 2005, Tyson Sawyer wrote:
> 
> > Do we need to move ourselves over or will the existing list of subscribers be
> > moved?
> 
> gets moved automagically, (i.e. stefan) but you should be getting dup mail 
> emails from linuxbios at openbios.org
 
All people have been moved over to the new list, except those that were
excessively bouncing or those that have subscibed in the last 2 days.

Sorry for the inconvenience caused by the move.

   Stefan



From nathanael at gnat.ca  Mon Mar 14 23:44:26 2005
From: nathanael at gnat.ca (Nathanael Noblet)
Date: Mon, 14 Mar 2005 14:44:26 -0800
Subject: [LinuxBIOS] Linux vs. Open?
In-Reply-To: <20050314181500.GP3035@maybe.org>
References: <20050314181500.GP3035@maybe.org>
Message-ID: <2d16126568092d2bd953a0d97d2fd073@gnat.ca>


On Mar 14, 2005, at 10:15 AM, Dale Harris wrote:

> So this is likely a dumb question.  But what is the difference between
> LinuxBIOS and OpenBIOS?

As far as my very limited knowledge goes, LinuxBIOS isn't a BIOS 
persay. It will initialize your hardware to a state that it can load a 
bootloader of sometype (or even just a program like memtest). When you 
are creating a linuxbios for a board/system. You will determine what 
payload(s) you want it to have. These payloads can be filo, etherboot a 
linux kernel, or ALDO or OpenBIOS.

OpenBIOS as far as I understand, is attempting to create a BIOS 
replica/replacement, and as such could be a payload to LinuxBIOS.

You might also want to check out the new site 
http://wiki.linuxbios.org/ which will probably have more definitive 
answers to your question.
-- 
Nathanael D. Noblet
Gnat Solutions
204 - 131 Gorge Road E
Victoria, BC V9A 1L1

T 250.385.4613
C 250.893.4613
http://www.gnat.ca/




From jjengla at sandia.gov  Sat Mar 12 11:19:51 2005
From: jjengla at sandia.gov (Josh England)
Date: Sat, 12 Mar 2005 02:19:51 -0800
Subject: [LinuxBIOS] cutting over
In-Reply-To: <20050314223934.GB13056@openbios.org>
References: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>
	<4235B9C2.7010506@irobot.com>
	<Pine.LNX.4.58.0503140959320.22781@enigma.lanl.gov>
	<20050314223934.GB13056@openbios.org>
Message-ID: <1110622791.9006.17.camel@localhost>

Is the new list going to be archived/searchable?  Where is the web page
for it?

-JE

On Mon, 2005-03-14 at 23:39 +0100, Stefan Reinauer wrote:
> * Ronald G. Minnich <rminnich at lanl.gov> [050314 17:59]:
> > 
> > 
> > On Mon, 14 Mar 2005, Tyson Sawyer wrote:
> > 
> > > Do we need to move ourselves over or will the existing list of subscribers be
> > > moved?
> > 
> > gets moved automagically, (i.e. stefan) but you should be getting dup mail 
> > emails from linuxbios at openbios.org
>  
> All people have been moved over to the new list, except those that were
> excessively bouncing or those that have subscibed in the last 2 days.
> 
> Sorry for the inconvenience caused by the move.
> 
>    Stefan
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 





From stuge-linuxbios at cdy.org  Tue Mar 15 02:34:17 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Tue, 15 Mar 2005 02:34:17 +0100
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <2d16126568092d2bd953a0d97d2fd073@gnat.ca>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
Message-ID: <20050315013417.GA22655@foo.birdnet.se>

On Mon, Mar 14, 2005 at 02:44:26PM -0800, Nathanael Noblet wrote:
> On Mar 14, 2005, at 10:15 AM, Dale Harris wrote:
> 
> >So this is likely a dumb question.  But what is the difference
> >between LinuxBIOS and OpenBIOS?

[..]

> You might also want to check out the new site 
> http://wiki.linuxbios.org/ which will probably have more definitive
> answers to your question.

This inspired me to touch up the general description of LinuxBIOS in
the FAQ, to include mention of OpenBIOS and freebios. I realized that
there's some disparity in the term LinuxBIOS, in what it covers.

It's good to use LinuxBIOS for the completed product, including
payload and all. It looks good, feels good and is practical.

I would like to have a name for the part that isn't the payload.
Suggestions? I've called it "the initialization part|code" but I
don't like that too much.


//Peter



From bari at onelabs.com  Tue Mar 15 03:38:00 2005
From: bari at onelabs.com (Bari Ari)
Date: Mon, 14 Mar 2005 20:38:00 -0600
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <20050315013417.GA22655@foo.birdnet.se>
References: <20050314181500.GP3035@maybe.org>	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
Message-ID: <42364A88.4090904@onelabs.com>

Peter Stuge wrote:

> I would like to have a name for the part that isn't the payload.
> Suggestions? I've called it "the initialization part|code" but I
> don't like that too much.

How about Pre Payload Environment - PPE? Since PXE is already taken.

-Bari



From nathanael at gnat.ca  Tue Mar 15 04:00:06 2005
From: nathanael at gnat.ca (Nathanael Noblet)
Date: Mon, 14 Mar 2005 19:00:06 -0800
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <42364A88.4090904@onelabs.com>
References: <20050314181500.GP3035@maybe.org>	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
Message-ID: <c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>


On Mar 14, 2005, at 6:38 PM, Bari Ari wrote:

> Peter Stuge wrote:
>
>> I would like to have a name for the part that isn't the payload.
>> Suggestions? I've called it "the initialization part|code" but I
>> don't like that too much.
>
> How about Pre Payload Environment - PPE? Since PXE is already taken.

BSI
Basic System Initialization

[B]MHI
[Basic] Memory Hardware Initialization

HD[E|P]
Hardware Discovery [Environment | Phase]

;)
-- 
Nathanael D. Noblet
Gnat Solutions
204 - 131 Gorge Road E
Victoria, BC V9A 1L1

T 250.385.4613
C 250.893.4613
http://www.gnat.ca/




From cro_marmot at comcast.net  Tue Mar 15 07:21:32 2005
From: cro_marmot at comcast.net (David Hendricks)
Date: Mon, 14 Mar 2005 23:21:32 -0700
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
Message-ID: <20050314232132.3366b7b4@sunder>

HASH - Hardware And SHit

"LinuxBIOS begins in the HASH stage where it initializes the memory
controller and CPU, scans system busses, etc. before booting a payload."
We could call the bootloader stage BASH, external ROMs (SCSI, VGA) RASH,
and any other software SASH. The -ASH ending is incredibly versatile.

Or if you prefer names without profanity:
HIC: Hardware initialization code
HEC: Hardware enabling code
MIR: Mainboard Initialization Routines
MIS: Mainboard Initialization Stuff
NAB: Not A Bootloader
NAP: Not A Payload

I'm still not entirely clear on why a new acronym is necessary, though.
Perhaps we should try to clear up the definition of the word "payload"
more than using another acronym to describe what is meant by the word
"BIOS" since BIOS is already sort of a generic term for a wad of
hardware initialization routines. Then we can explain why "Linux" is in
the name of the project. Or perhaps the solution would be to change the
name of the project back to FreeBIOS. If not that, we can call it
Minnich's BIOS (Since it rhymes with LinuxBIOS) and pray that nobody
calls it MinixBIOS :)

On Mon, 14 Mar 2005 19:00:06 -0800
Nathanael Noblet <nathanael at gnat.ca> wrote:

> 
> On Mar 14, 2005, at 6:38 PM, Bari Ari wrote:
> 
> > Peter Stuge wrote:
> >
> >> I would like to have a name for the part that isn't the payload.
> >> Suggestions? I've called it "the initialization part|code" but I
> >> don't like that too much.
> >
> > How about Pre Payload Environment - PPE? Since PXE is already taken.
> 
> BSI
> Basic System Initialization
> 
> [B]MHI
> [Basic] Memory Hardware Initialization
> 
> HD[E|P]
> Hardware Discovery [Environment | Phase]
> 
> ;)
> -- 
> Nathanael D. Noblet
> Gnat Solutions
> 204 - 131 Gorge Road E
> Victoria, BC V9A 1L1
> 
> T 250.385.4613
> C 250.893.4613
> http://www.gnat.ca/
> 
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios



From stuge-linuxbios at cdy.org  Tue Mar 15 10:57:56 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Tue, 15 Mar 2005 10:57:56 +0100
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <20050314232132.3366b7b4@sunder>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
Message-ID: <20050315095755.GA11300@foo.birdnet.se>

On Mon, Mar 14, 2005 at 11:21:32PM -0700, David Hendricks wrote:

[..lots of good acronym ideas..]

> I'm still not entirely clear on why a new acronym is necessary,

I was looking more for an official term, not neccessarily an acronym.


> Perhaps we should try to clear up the definition of the word
> "payload" more than using another acronym to describe what is meant
> by the word "BIOS" since BIOS is already sort of a generic term for
> a wad of hardware initialization routines.

"BIOS" is quickly getting obsolete.. Plus LinuxBIOS as of now doesn't
do much in the traditional BIOS sense; there are no callbacks, by
design. It's a mainboard firmware rather than a BIOS. That's actually
pretty good, "mainboard firmware" - but then I'm back at the original
problem; what to call the non-payload part. Core? Hardware init?


> Then we can explain why "Linux" is in the name of the project. Or
> perhaps the solution would be to change the name of the project
> back to FreeBIOS. If not that, we can call it Minnich's BIOS (Since
> it rhymes with LinuxBIOS) and pray that nobody calls it MinixBIOS
> :)

:) The name LinuxBIOS has catched on however, I recall Ron wrote that
it catched on even among vendors, and changing it without a really
good reason would just hurt in that case.

Terribly sorry if anyone thinks I'm splitting hairs. I just want to
see what ideas are out there on this.


//Peter



From stuge-linuxbios at cdy.org  Tue Mar 15 11:02:24 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Tue, 15 Mar 2005 11:02:24 +0100
Subject: [LinuxBIOS] Re: Flash package images [was: ELAN SC520]
In-Reply-To: <20050314234742.669e22f8@sunder>
References: <20050222155811.GA10110@openbios.org>
	<1109088774.11584.5.camel@localhost.localdomain>
	<20050309221109.GB7425@openbios.org>
	<1110453405.7972.39.camel@localhost.localdomain>
	<Pine.LNX.4.58.0503100838070.12217@enigma.lanl.gov>
	<42307428.6080008@lnxi.com> <20050310183809.GC23375@foo.birdnet.se>
	<Pine.LNX.4.58.0503101355590.12976@enigma.lanl.gov>
	<20050311082403.GE5020@foo.birdnet.se>
	<20050314234742.669e22f8@sunder>
Message-ID: <20050315100224.GB11300@foo.birdnet.se>

On Mon, Mar 14, 2005 at 11:47:42PM -0700, David Hendricks wrote:
> Is there a way to save those images of the flash chips somewhere on
> openbios.org? The images are a great idea, but I'm not sure if
> hotlinking to other sites is a good idea. I suppose if someone
> bitches or they take the image down, the wiki can be changed easily
> as well.

Right.

There are ways to upload to the wiki, but that naturally requires
proper copyright things. I found it easier just to link to some good
images that I found through google images.

If only I could find my digital camera I'd be happy to take some
pictures and donate them to the wiki, but it's been missing for a
while. :( Anyone else with loose flash parts, please beat me to it.
If you don't have wiki write access, just send me the images and I'll
upload them.


//Peter



From smithbone at gmail.com  Tue Mar 15 14:18:33 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 15 Mar 2005 07:18:33 -0600
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <20050315095755.GA11300@foo.birdnet.se>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se> <42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
Message-ID: <8a0c3678050315051826e5d9ea@mail.gmail.com>

> pretty good, "mainboard firmware" - but then I'm back at the original
> problem; what to call the non-payload part. Core? Hardware init?

What about init phase?  The whole pre-payload is basically just a
per-subsystem init procedure.  Be it CPU, memory, pci cards, or
whatever.

> Terribly sorry if anyone thinks I'm splitting hairs. I just want to
> see what ideas are out there on this.

I doubt anyone thinks that.  I'm sure that most of us are just happy
that someone _is_ thinking about these kind of things and actually
doing something.  This is exactly the type of info that a newbe needs.
 Attention to this type of stuff is what sets a good "Project" apart
from just a pile of code.

-- 
Richard A. Smith



From jrollins at ligo.mit.edu  Tue Mar 15 14:30:17 2005
From: jrollins at ligo.mit.edu (Jamie Rollins)
Date: Tue, 15 Mar 2005 08:30:17 -0500 (EST)
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <8a0c3678050315051826e5d9ea@mail.gmail.com>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se> <42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<8a0c3678050315051826e5d9ea@mail.gmail.com>
Message-ID: <Pine.GSO.4.56.0503150818270.2062@ligo.mit.edu>

And I personally don't see the problem with looking ahead to an acronym
either, for what it's worth.  Most concepts end up being abbreviated
anyway.

jamie.



On Tue, 15 Mar 2005, Richard Smith wrote:

> > pretty good, "mainboard firmware" - but then I'm back at the original
> > problem; what to call the non-payload part. Core? Hardware init?
>
> What about init phase?  The whole pre-payload is basically just a
> per-subsystem init procedure.  Be it CPU, memory, pci cards, or
> whatever.
>
> > Terribly sorry if anyone thinks I'm splitting hairs. I just want to
> > see what ideas are out there on this.
>
> I doubt anyone thinks that.  I'm sure that most of us are just happy
> that someone _is_ thinking about these kind of things and actually
> doing something.  This is exactly the type of info that a newbe needs.
>  Attention to this type of stuff is what sets a good "Project" apart
> from just a pile of code.
>
> --
> Richard A. Smith
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From chromi at chromatix.demon.co.uk  Tue Mar 15 16:00:06 2005
From: chromi at chromatix.demon.co.uk (Jonathan Morton)
Date: Tue, 15 Mar 2005 15:00:06 +0000
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <Pine.GSO.4.56.0503150818270.2062@ligo.mit.edu>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<8a0c3678050315051826e5d9ea@mail.gmail.com>
	<Pine.GSO.4.56.0503150818270.2062@ligo.mit.edu>
Message-ID: <343de22b6836cfff83b855fc7069c995@chromatix.demon.co.uk>

>>> pretty good, "mainboard firmware" - but then I'm back at the original
>>> problem; what to call the non-payload part. Core? Hardware init?
>>
>> What about init phase?  The whole pre-payload is basically just a
>> per-subsystem init procedure.  Be it CPU, memory, pci cards, or
>> whatever.

If I understand right, the "bootstrap" section (presently called 
LinuxBIOS) is essentially a stripped-down Linux kernel with some rather 
more in-depth device initialisation capabilities.  Such a configuration 
does make sense, and would allow very flexible boot device support.

If this is true, then as a kernel it *does* have callbacks, and can 
justifiably be termed a BIOS in the strict sense of the word, even if 
it doesn't provide the legacy "IBM compatible" calls to run M$-DOS 
directly.  Thus the name "LinuxBIOS" should probably stick.

Since I'm not heavily involved with the project, I might have got these 
details very wrong.  Please don't shoot me too much.

The combination of LinuxBIOS with a trivial "chainloader" payload for 
booting a sophisticated OS directly, should probably stay as LinuxBIOS. 
  As for the combination of LinuxBIOS with an OpenFirmware-like payload, 
I think it could be called LinuxFirmware.

The latter could be an extremely powerful system configuration tool.  
Certainly overclockers would love it, with a (relatively) universal 
interface to and support for their favourite tweaks.  Sysadmins would 
like it too, if it contained sophisticated diagnostic routines 
(Memtest86 and 'badblocks' in firmware?) etc.

Eventually, even Intel will have to admit it's time to ditch the old, 
frequently buggy and restrictive AMI and Award BIOS structures.  
Goodness, BIOSes of both kinds have caused havoc when faced with a HD 
slightly larger than was expected at the time of manufacture, multiple 
times in recent history.  The onus has largely been on the HD 
manufacturers to work around the BIOS bugs.  That's just wrong.

--------------------------------------------------------------
from:     Jonathan "Chromatix" Morton
mail:     chromi at chromatix.demon.co.uk
website:  http://www.chromatix.uklinux.net/
tagline:  The key to knowledge is not to rely on people to teach you it.




From rminnich at lanl.gov  Tue Mar 15 16:46:13 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 15 Mar 2005 08:46:13 -0700 (MST)
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <343de22b6836cfff83b855fc7069c995@chromatix.demon.co.uk>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se> <42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<8a0c3678050315051826e5d9ea@mail.gmail.com>
	<Pine.GSO.4.56.0503150818270.2062@ligo.mit.edu>
	<343de22b6836cfff83b855fc7069c995@chromatix.demon.co.uk>
Message-ID: <Pine.LNX.4.58.0503150844040.25502@enigma.lanl.gov>



On Tue, 15 Mar 2005, Jonathan Morton wrote:

> If I understand right, the "bootstrap" section (presently called
> LinuxBIOS) is essentially a stripped-down Linux kernel with some rather
> more in-depth device initialisation capabilities.  Such a configuration
> does make sense, and would allow very flexible boot device support.

such was the plan. 

But the small flash size problem changed the plan

> If this is true, then as a kernel it *does* have callbacks, and can
> justifiably be termed a BIOS in the strict sense of the word, even if it
> doesn't provide the legacy "IBM compatible" calls to run M$-DOS
> directly. Thus the name "LinuxBIOS" should probably stick.

yeah. I still think long term I want linux in there. The Intel EFI guys 
beat up on me a lot about this -- "LinuxBIOS has no API". 

My response was, "of course it does -- it's called the linux system call 
layer". 

But it's harder to make that case when there's no linux in there ...

> Eventually, even Intel will have to admit it's time to ditch the old,
> frequently buggy and restrictive AMI and Award BIOS structures.  
> Goodness, BIOSes of both kinds have caused havoc when faced with a HD
> slightly larger than was expected at the time of manufacture, multiple
> times in recent history.  The onus has largely been on the HD
> manufacturers to work around the BIOS bugs.  That's just wrong.

Intel has admitted that, long ago; it's just that their solution is 
utterly proprietary, which runs against the grain. At least my grain.

ron



From smithbone at gmail.com  Tue Mar 15 17:43:56 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 15 Mar 2005 10:43:56 -0600
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <Pine.LNX.4.58.0503150844040.25502@enigma.lanl.gov>
References: <20050314181500.GP3035@maybe.org>
	<20050315013417.GA22655@foo.birdnet.se> <42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<8a0c3678050315051826e5d9ea@mail.gmail.com>
	<Pine.GSO.4.56.0503150818270.2062@ligo.mit.edu>
	<343de22b6836cfff83b855fc7069c995@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0503150844040.25502@enigma.lanl.gov>
Message-ID: <8a0c36780503150843e293c52@mail.gmail.com>

> yeah. I still think long term I want linux in there. The Intel EFI guys
> beat up on me a lot about this -- "LinuxBIOS has no API".
 
What do the EFI guys need and API for? 

-- 
Richard A. Smith



From rminnich at lanl.gov  Tue Mar 15 20:14:34 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 15 Mar 2005 12:14:34 -0700 (MST)
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <8a0c36780503150843e293c52@mail.gmail.com>
References: <20050314181500.GP3035@maybe.org>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<8a0c3678050315051826e5d9ea@mail.gmail.com>
	<Pine.GSO.4.56.0503150818270.2062@ligo.mit.edu>
	<343de22b6836cfff83b855fc7069c995@chromatix.demon.co.uk> 
	<Pine.LNX.4.58.0503150844040.25502@enigma.lanl.gov>
	<8a0c36780503150843e293c52@mail.gmail.com>
Message-ID: <Pine.LNX.4.58.0503151213500.25874@enigma.lanl.gov>



On Tue, 15 Mar 2005, Richard Smith wrote:
> What do the EFI guys need and API for? 


oh, goodness, that's the whole point of EFI. It has a very complex API, 
including timers, file systems, network protocols, and on and on. It's 
quite incredible.

ron



From bari at onelabs.com  Wed Mar 16 02:29:01 2005
From: bari at onelabs.com (Bari Ari)
Date: Tue, 15 Mar 2005 19:29:01 -0600
Subject: [LinuxBIOS] Tyan K7M (S2498) for AMD
	=?windows-1252?q?Geode=99_NX_CPU?=
Message-ID: <42378BDD.1030901@onelabs.com>

Tyan has two new Geode boards that use the VIA KN400A, VT8237 SB 
chipset, Winbond W83697HF LPC I/O chip and Realtek ALC655 AC'97 codec. 
One version even offers Gb ethernet. Any news on LinuxBIOS support or 
help with support for it?

http://www.tyan.com/products/html/tomcatk7m_spec.html

-Bari



From YhLu at tyan.com  Wed Mar 16 02:45:07 2005
From: YhLu at tyan.com (YhLu)
Date: Tue, 15 Mar 2005 17:45:07 -0800
Subject: [LinuxBIOS] RE: Tyan K7M (S2498) for AMD Geode? NX CPU
Message-ID: <3174569B9743D511922F00A0C943142308A06062@TYANWEB>

I will get one to play. 

> -----Original Message-----
> From: Bari Ari [mailto:bari at onelabs.com] 
> Sent: Tuesday, March 15, 2005 5:29 PM
> To: linuxbios at openbios.org
> Cc: YhLu
> Subject: Tyan K7M (S2498) for AMD Geode? NX CPU
> 
> Tyan has two new Geode boards that use the VIA KN400A, VT8237 
> SB chipset, Winbond W83697HF LPC I/O chip and Realtek ALC655 
> AC'97 codec. 
> One version even offers Gb ethernet. Any news on LinuxBIOS 
> support or help with support for it?
> 
> http://www.tyan.com/products/html/tomcatk7m_spec.html
> 
> -Bari
> 



From kevin at koconnor.net  Wed Mar 16 13:41:25 2005
From: kevin at koconnor.net (Kevin O'Connor)
Date: Wed, 16 Mar 2005 07:41:25 -0500
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <20050315095755.GA11300@foo.birdnet.se>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
Message-ID: <20050316124125.GA17668@double.lan>

On Tue, Mar 15, 2005 at 10:57:56AM +0100, Peter Stuge wrote:
> "BIOS" is quickly getting obsolete.. Plus LinuxBIOS as of now doesn't
> do much in the traditional BIOS sense; there are no callbacks, by
> design. It's a mainboard firmware rather than a BIOS. That's actually
> pretty good, "mainboard firmware" - but then I'm back at the original
> problem; what to call the non-payload part. Core? Hardware init?

I think the term "BIOS" means different things to different people.  Some
think of it as the POST stage - which is what LinuxBIOS replaces.  Others
would associate it with the old DOS callbacks (as you did).  And yet others
think of the menu screen in a COTS BIOS where boot options can be set.

> > Then we can explain why "Linux" is in the name of the project. Or
> > perhaps the solution would be to change the name of the project
> > back to FreeBIOS. If not that, we can call it Minnich's BIOS (Since
> > it rhymes with LinuxBIOS) and pray that nobody calls it MinixBIOS
> > :)
> 
> :) The name LinuxBIOS has catched on however, I recall Ron wrote that
> it catched on even among vendors, and changing it without a really
> good reason would just hurt in that case.

I wonder if the pain of changing names would be worth preventing the
perpetual misunderstanding that the current name creates.  LinuxBIOS right
now has nothing to do with Linux.  The misconception that Linux is in the
firmware or that the firmware was derived from Linux comes up frequently.
(See one of the replies in this thread..)

Interestingly, Linux is a trademarked term.  If a manufacture ever started
shipping LinuxBIOS, they'd need to put the little blurb about "Linux is a
trademark owned by Linus Torvalds" in their promotional material -- even
though Linus and Linux have nothing to do with the product.

Also, if LinuxBIOS+ADLO ever matures, one could get in the very awkward
position of trying to explain to end users that they're really running
Windows and not Linux.  :-)

-Kevin



From chromi at chromatix.demon.co.uk  Wed Mar 16 14:00:52 2005
From: chromi at chromatix.demon.co.uk (Jonathan Morton)
Date: Wed, 16 Mar 2005 13:00:52 +0000
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <20050316124125.GA17668@double.lan>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<20050316124125.GA17668@double.lan>
Message-ID: <4ddc9802a5613720bcc82049f5792dca@chromatix.demon.co.uk>

>> The name LinuxBIOS has catched on however, I recall Ron wrote that
>> it catched on even among vendors, and changing it without a really
>> good reason would just hurt in that case.
>
> I wonder if the pain of changing names would be worth preventing the
> perpetual misunderstanding that the current name creates.  LinuxBIOS 
> right
> now has nothing to do with Linux.  The misconception that Linux is in 
> the
> firmware or that the firmware was derived from Linux comes up 
> frequently.
> (See one of the replies in this thread..)

Yeah, point taken.  Instead, how about OpenStrap for the bootstrap 
section?  This could go with BeltStrap as the variant with OpenFirmware 
included.  The latter has some subliminal connotations of 
performance...

--------------------------------------------------------------
from:     Jonathan "Chromatix" Morton
mail:     chromi at chromatix.demon.co.uk
website:  http://www.chromatix.uklinux.net/
tagline:  The key to knowledge is not to rely on people to teach you it.




From rminnich at lanl.gov  Wed Mar 16 17:44:36 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed, 16 Mar 2005 09:44:36 -0700 (MST)
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <4ddc9802a5613720bcc82049f5792dca@chromatix.demon.co.uk>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se> <42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<20050316124125.GA17668@double.lan>
	<4ddc9802a5613720bcc82049f5792dca@chromatix.demon.co.uk>
Message-ID: <Pine.LNX.4.58.0503160944090.28289@enigma.lanl.gov>



On Wed, 16 Mar 2005, Jonathan Morton wrote:
> Yeah, point taken.  Instead, how about OpenStrap for the bootstrap section?

yuck. :=)

THe problem is this: linuxbios is a very catchy name, rolls off the 
tongue. 

I've not found a better name.

ron



From rminnich at lanl.gov  Wed Mar 16 17:45:19 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed, 16 Mar 2005 09:45:19 -0700 (MST)
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <20050316124125.GA17668@double.lan>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se> <42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<20050316124125.GA17668@double.lan>
Message-ID: <Pine.LNX.4.58.0503160945020.28289@enigma.lanl.gov>



On Wed, 16 Mar 2005, Kevin O'Connor wrote:

> Also, if LinuxBIOS+ADLO ever matures, one could get in the very awkward
> position of trying to explain to end users that they're really running
> Windows and not Linux.  :-)

but what do we call it if we ever meet the end goal: linux is the bios. 

ron



From ollie at lanl.gov  Wed Mar 16 22:51:31 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Wed, 16 Mar 2005 14:51:31 -0700
Subject: [LinuxBIOS] CVS or TLA
Message-ID: <1111008754.3821.0.camel@logarithm.lanl.gov>

Stephan,

What is the current status of the revision control system?
Are we going to use the tla now?

Ollie





From stepan at openbios.org  Wed Mar 16 22:57:27 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed, 16 Mar 2005 22:57:27 +0100
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <Pine.LNX.4.58.0503150844040.25502@enigma.lanl.gov>
References: <2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<8a0c3678050315051826e5d9ea@mail.gmail.com>
	<Pine.GSO.4.56.0503150818270.2062@ligo.mit.edu>
	<343de22b6836cfff83b855fc7069c995@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0503150844040.25502@enigma.lanl.gov>
Message-ID: <20050316215727.GA25597@openbios.org>

* Ronald G. Minnich <rminnich at lanl.gov> [050315 16:46]:
> yeah. I still think long term I want linux in there. The Intel EFI guys 
> beat up on me a lot about this -- "LinuxBIOS has no API". 
> 
> My response was, "of course it does -- it's called the linux system call 
> layer". 
> 
> But it's harder to make that case when there's no linux in there ...

OpenBIOS is such an API. And it is an API created after an industry
proven standard, not some proprietary monopoly game punching IEEE1275
with a big "NIH" ;-)

Well, if it only were complete...

Stefan




From stepan at openbios.org  Thu Mar 17 01:18:21 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu, 17 Mar 2005 01:18:21 +0100
Subject: [LinuxBIOS] CVS or TLA
In-Reply-To: <1111008754.3821.0.camel@logarithm.lanl.gov>
References: <1111008754.3821.0.camel@logarithm.lanl.gov>
Message-ID: <20050317001821.GD6422@openbios.org>

* Li-Ta Lo <ollie at lanl.gov> [050316 22:51]:
> Stephan,
> 
> What is the current status of the revision control system?
> Are we going to use the tla now?
 
After quite some delay, commits to the gnu arch repository work now as
well.

The Download page in Wiki has some information on public downloading of
the archive. We should add the developers information to a seperate page
once everything has settled

 http://wiki.linuxbios.org/index.php/Download_freebios_v2

Stefan




From stuge-linuxbios at cdy.org  Thu Mar 17 06:06:01 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 17 Mar 2005 06:06:01 +0100
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <8a0c3678050315051826e5d9ea@mail.gmail.com>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<8a0c3678050315051826e5d9ea@mail.gmail.com>
Message-ID: <20050317050601.GA23408@foo.birdnet.se>

On Tue, Mar 15, 2005 at 07:18:33AM -0600, Richard Smith wrote:
> > pretty good, "mainboard firmware" - but then I'm back at the
> > original problem; what to call the non-payload part. Core?
> > Hardware init?
> 
> What about init phase?  The whole pre-payload is basically just a
> per-subsystem init procedure.  Be it CPU, memory, pci cards, or
> whatever.

I like that! Although a small alarm goes off in the back of my head
since Linux and init are already pretty close to each other, at least
in my memory bank. But perhaps hwinit or hardware init? Oh, that's
the second time I come up with that.. :) "Hardware initialization
phase" or hwinit for short, sounds good?


> > Terribly sorry if anyone thinks I'm splitting hairs. I just want
> > to see what ideas are out there on this.
> 
> I doubt anyone thinks that.  I'm sure that most of us are just
> happy that someone _is_ thinking about these kind of things and
> actually doing something.  This is exactly the type of info that a
> newbe needs.  Attention to this type of stuff is what sets a good
> "Project" apart from just a pile of code.

Thanks! That's very encouraging. :) I wish I had time and hardware
to contribute to the code as well, but I don't mind working on
"softer" matters.


//Peter



From ourlinuxid at yahoo.co.in  Thu Mar 17 06:28:16 2005
From: ourlinuxid at yahoo.co.in (Ramesh Chhaba)
Date: Thu, 17 Mar 2005 05:28:16 +0000 (GMT)
Subject: [LinuxBIOS] STPC support
Message-ID: <20050317052816.76110.qmail@web8401.mail.in.yahoo.com>

Hi All ,
 I want to use linuxbios for STPC Atlas .
 
Weather it is supported or what I have to do to use linux bios for STPC Atlas.
 
Thank You
 
Ramesh Chander

Yahoo! India Matrimony: Find your life partneronline.
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From stuge-linuxbios at cdy.org  Thu Mar 17 07:08:11 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 17 Mar 2005 07:08:11 +0100
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <20050316124125.GA17668@double.lan>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<20050316124125.GA17668@double.lan>
Message-ID: <20050317060811.GD23408@foo.birdnet.se>

On Wed, Mar 16, 2005 at 07:41:25AM -0500, Kevin O'Connor wrote:
> On Tue, Mar 15, 2005 at 10:57:56AM +0100, Peter Stuge wrote:
> > "BIOS" is quickly getting obsolete.. Plus LinuxBIOS as of now doesn't
> > do much in the traditional BIOS sense; there are no callbacks, by
> > design. It's a mainboard firmware rather than a BIOS. That's actually
> > pretty good, "mainboard firmware" - but then I'm back at the original
> > problem; what to call the non-payload part. Core? Hardware init?
> 
> I think the term "BIOS" means different things to different people. 
> Some think of it as the POST stage - which is what LinuxBIOS
> replaces.  Others would associate it with the old DOS callbacks (as
> you did).  And yet others think of the menu screen in a COTS BIOS
> where boot options can be set.

Right. Are there more fundamental blocks in a classic BIOS that I
can't think of?

- Hardware init controlled by battery-backed NVRAM
LinuxBIOS does this but it is instead controlled by compile-time
options. What is the desired development of this part?

- Boot process controlled by NVRAM
LinuxBIOS does this too, by loading a payload, and this is also
controlled by compile-time options. What is the desired development
of this part?

- Legacy services, and the only way BIOS is visible after OS loads
LinuxBIOS does not, and should not, ever, do this. Right?


I'm not saying a LinuxBIOS firmware image cannot have callbacks, but
they probably shouldn't be to this project, but rather, as Ron says,
to the Linux kernel itself. I keep making this distinctions since we
will not start developing the kernel "inside" LinuxBIOS, but a
firmware image will instead be a marriage between LinuxBIOS parts and
kernel parts.


> I wonder if the pain of changing names would be worth preventing the
> perpetual misunderstanding that the current name creates.

Right. Perhaps it will.

> LinuxBIOS right now has nothing to do with Linux.  The misconception
> that Linux is in the firmware or that the firmware was derived from
> Linux comes up frequently.
> (See one of the replies in this thread..)

Right.


> Interestingly, Linux is a trademarked term.  If a manufacture ever
> started shipping LinuxBIOS, they'd need to put the little blurb
> about "Linux is a trademark owned by Linus Torvalds" in their
> promotional material -- even though Linus and Linux have nothing to
> do with the product.

This is also a reason to change the name. And a pretty good one IMHO.


> Also, if LinuxBIOS+ADLO ever matures, one could get in the very
> awkward position of trying to explain to end users that they're
> really running Windows and not Linux.  :-)

Yup.


//Peter



From stuge-linuxbios at cdy.org  Thu Mar 17 07:09:25 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 17 Mar 2005 07:09:25 +0100
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <Pine.LNX.4.58.0503160945020.28289@enigma.lanl.gov>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<20050316124125.GA17668@double.lan>
	<Pine.LNX.4.58.0503160945020.28289@enigma.lanl.gov>
Message-ID: <20050317060925.GE23408@foo.birdnet.se>

On Wed, Mar 16, 2005 at 09:45:19AM -0700, Ronald G. Minnich wrote:
> On Wed, 16 Mar 2005, Kevin O'Connor wrote:
> 
> > Also, if LinuxBIOS+ADLO ever matures, one could get in the very
> > awkward position of trying to explain to end users that they're
> > really running Windows and not Linux.  :-)
> 
> but what do we call it if we ever meet the end goal: linux is the bios.

Ron, I think you just said it! (Well, wrote it.)

LitheBIOS


//Peter



From stuge-linuxbios at cdy.org  Thu Mar 17 07:18:14 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 17 Mar 2005 07:18:14 +0100
Subject: [LinuxBIOS] Names names.. [was: Linux vs. Open?]
In-Reply-To: <343de22b6836cfff83b855fc7069c995@chromatix.demon.co.uk>
References: <20050314181500.GP3035@maybe.org>
	<2d16126568092d2bd953a0d97d2fd073@gnat.ca>
	<20050315013417.GA22655@foo.birdnet.se>
	<42364A88.4090904@onelabs.com>
	<c7f7f8951d8c17bf1a1e3fddfb570106@gnat.ca>
	<20050314232132.3366b7b4@sunder>
	<20050315095755.GA11300@foo.birdnet.se>
	<8a0c3678050315051826e5d9ea@mail.gmail.com>
	<Pine.GSO.4.56.0503150818270.2062@ligo.mit.edu>
	<343de22b6836cfff83b855fc7069c995@chromatix.demon.co.uk>
Message-ID: <20050317061814.GF23408@foo.birdnet.se>

On Tue, Mar 15, 2005 at 03:00:06PM +0000, Jonathan Morton wrote:
> >>>pretty good, "mainboard firmware" - but then I'm back at the original
> >>>problem; what to call the non-payload part. Core? Hardware init?
> >>
> >>What about init phase?  The whole pre-payload is basically just a
> >>per-subsystem init procedure.  Be it CPU, memory, pci cards, or
> >>whatever.
> 
> If I understand right, the "bootstrap" section (presently called
> LinuxBIOS) is essentially a stripped-down Linux kernel with some
> rather more in-depth device initialisation capabilities.  Such a
> configuration does make sense, and would allow very flexible boot
> device support.

Unfortunately not, as Ron said.

To further explain, a LinuxBIOS firmware image file (.bin, to be
flashed into a flash ROM) currently has a couple of logical parts:

* RAM initialization
* Hardware initialization of remaining things on the mainboard far
enough for a Linux kernel to be able to find, further init and use.
* Payload

The first two are developed in the freebios/freebios2 source tree
that recently moved from SourceForge to OpenBIOS.org. The payload can
come from a number of different places; it can be a Linux kernel, but
can also be FILO, (loads a supposed OS kernel from a filesystem on a
mass-storage device) Etherboot, (loads a supposed OS kernel from the
network, but also includes a version of FILO) ADLO, (legacy
compatibility layer that can be used to start up Windows 2000 and
other products) memtest86 (tests RAM) and probably lots of other
programs that I can't remember.


> If this is true, then as a kernel it *does* have callbacks, and can
> justifiably be termed a BIOS in the strict sense of the word, even
> if it doesn't provide the legacy "IBM compatible" calls to run
> M$-DOS directly.  Thus the name "LinuxBIOS" should probably stick.

With Linux as the payload, yes, definately. I do imagine other uses
for it, although that is the primary goal.


//Peter



From stepan at openbios.org  Thu Mar 17 10:13:05 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu, 17 Mar 2005 10:13:05 +0100
Subject: [LinuxBIOS] cutting over
In-Reply-To: <1110622791.9006.17.camel@localhost>
References: <Pine.LNX.4.58.0503140849420.22631@enigma.lanl.gov>
	<4235B9C2.7010506@irobot.com>
	<Pine.LNX.4.58.0503140959320.22781@enigma.lanl.gov>
	<20050314223934.GB13056@openbios.org>
	<1110622791.9006.17.camel@localhost>
Message-ID: <20050317091305.GB31596@openbios.org>

* Josh England <jjengla at sandia.gov> [050312 11:19]:
> Is the new list going to be archived/searchable?  Where is the web page
> for it?

http://www.openbios.org/pipermail/linuxbios/ 
 
Some mails might have slipped through but it should be working now,
including all the mails from the old archive


Stefan



From ollie at lanl.gov  Thu Mar 17 19:11:33 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Thu, 17 Mar 2005 11:11:33 -0700
Subject: [LinuxBIOS] CVS or TLA
In-Reply-To: <20050317001821.GD6422@openbios.org>
References: <1111008754.3821.0.camel@logarithm.lanl.gov>
	<20050317001821.GD6422@openbios.org>
Message-ID: <1111083093.4277.3.camel@logarithm.lanl.gov>

On Wed, 2005-03-16 at 17:18, Stefan Reinauer wrote:
> * Li-Ta Lo <ollie at lanl.gov> [050316 22:51]:
> > Stephan,
> > 
> > What is the current status of the revision control system?
> > Are we going to use the tla now?
>  
> After quite some delay, commits to the gnu arch repository work now as
> well.
> 
> The Download page in Wiki has some information on public downloading of
> the archive. We should add the developers information to a seperate page
> once everything has settled
> 
>  http://wiki.linuxbios.org/index.php/Download_freebios_v2
> 
> Stefan
> 

How updated is you tla archive? I think there are changes on the CVS.

BTW, do I have to send you my gpg key to get commit privilege? Or ssh
key is enough.

Ollie




From stepan at openbios.org  Thu Mar 17 19:21:24 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu, 17 Mar 2005 19:21:24 +0100
Subject: [LinuxBIOS] CVS or TLA
In-Reply-To: <1111083093.4277.3.camel@logarithm.lanl.gov>
References: <1111008754.3821.0.camel@logarithm.lanl.gov>
	<20050317001821.GD6422@openbios.org>
	<1111083093.4277.3.camel@logarithm.lanl.gov>
Message-ID: <20050317182124.GA13698@openbios.org>

* Li-Ta Lo <ollie at lanl.gov> [050317 19:11]:
> 
> How updated is you tla archive? I think there are changes on the CVS.
 
The latest commit was your x86emu fixes on 2005-03-10

http://www.openbios.org/cgi-bin/viewarch.cgi/linuxbios at linuxbios.org--devel/freebios--import--2.0
(rather slow due to about 1000 changesets. i am discussing this issue
with the author of viewarch.)

> BTW, do I have to send you my gpg key to get commit privilege? Or ssh
> key is enough.
 
It is enough to use ssh. THOUGH: It is highly recommended that you sign
the commits so that the origin can be verified. (ie otherwise I could
in theory fake a commit done by you)  

Stefan




From rminnich at lanl.gov  Thu Mar 17 22:35:31 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 17 Mar 2005 14:35:31 -0700 (MST)
Subject: [LinuxBIOS] CVS or TLA
In-Reply-To: <20050317182124.GA13698@openbios.org>
References: <1111008754.3821.0.camel@logarithm.lanl.gov>
	<20050317001821.GD6422@openbios.org>
	<1111083093.4277.3.camel@logarithm.lanl.gov>
	<20050317182124.GA13698@openbios.org>
Message-ID: <Pine.LNX.4.58.0503171435001.32005@enigma.lanl.gov>



On Thu, 17 Mar 2005, Stefan Reinauer wrote:

> It is enough to use ssh. THOUGH: It is highly recommended that you sign
> the commits so that the origin can be verified. (ie otherwise I could in
> theory fake a commit done by you)

to make sure I understand: if I have a gpgkey, then the commit process 
will automagically ensure that it is signed, which is not the case for 
sshkey?

ron



From ebiederman at lnxi.com  Thu Mar 17 23:08:12 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: 17 Mar 2005 15:08:12 -0700
Subject: [LinuxBIOS] CVS or TLA
In-Reply-To: <Pine.LNX.4.58.0503171435001.32005@enigma.lanl.gov>
References: <1111008754.3821.0.camel@logarithm.lanl.gov>
	<20050317001821.GD6422@openbios.org>
	<1111083093.4277.3.camel@logarithm.lanl.gov>
	<20050317182124.GA13698@openbios.org>
	<Pine.LNX.4.58.0503171435001.32005@enigma.lanl.gov>
Message-ID: <m3d5tyudrn.fsf@maxwell.lnxi.com>

"Ronald G. Minnich" <rminnich at lanl.gov> writes:

> On Thu, 17 Mar 2005, Stefan Reinauer wrote:
> 
> > It is enough to use ssh. THOUGH: It is highly recommended that you sign
> > the commits so that the origin can be verified. (ie otherwise I could in
> > theory fake a commit done by you)
> 
> to make sure I understand: if I have a gpgkey, then the commit process 
> will automagically ensure that it is signed, which is not the case for 
> sshkey?

These issues are orthogonal.

The ssh key provides write access to the repository through sftp.
By chance this is the easiest way to implement a shared archive.

The gpg key (which is mandatory on a signed arch archive like 
linuxbios at linuxbios.org--devel) allows people to check to see if it
was really you who committed the change.

So you just need the ssh key to talk to Stefan box at openbios.org

Eric



From stuge-linuxbios at cdy.org  Thu Mar 17 23:12:38 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 17 Mar 2005 23:12:38 +0100
Subject: [LinuxBIOS] Re: Does a System BIOS do some kind of initialization
	on a Ethernet card?
In-Reply-To: <BAY102-F36EA4C8E9C900F5D6EB86BBA490@phx.gbl>
References: <BAY102-F36EA4C8E9C900F5D6EB86BBA490@phx.gbl>
Message-ID: <20050317221238.GG30465@foo.birdnet.se>

This is completely off-topic for the LinuxBIOS mailing list.


On Thu, Mar 17, 2005 at 09:54:18AM -0600, DongWook Kim wrote:
> I have a problem with activating the ethernet in my embedded linux.
> I am using realtek 8100c(It is one of the realteck's 8139 compatible NIC).
> 
> Our company designed a board and a some kind of system BIOS for our board.
> And after I installed a linux on the board with the BIOS and upload the 
> firmware of the realtek 8100c into its rom.

The only ROM I see close to the 8100C is the EEPROM that contains
configuration and MAC address. This should only have to be written
to once.


[..]
> 
> Does my System BIOS need some kind of initialization on the
> realteck 8100c?

Besides normal PCI init required for all PCI devices I very much doubt
that. But speak with your hardware department and your supplier. And
check out the chip data sheet.


//Peter



From liutao1980 at gmail.com  Fri Mar 18 10:30:14 2005
From: liutao1980 at gmail.com (Tao Liu)
Date: Fri, 18 Mar 2005 17:30:14 +0800
Subject: [LinuxBIOS] [PATCH] amd8111_nic init
Message-ID: <8eca059b05031801302e0f89df@mail.gmail.com>

Hello,

This patch handles the phy reset pin's polarity. AMD8111's PHY_RESET pin
is active high by default, but some PHY requires active low reset signal.
On mainboards which use 8111's PHY_RESET pin to reset PHY the bios
must select the correct PHY_RST_POL for 8111, otherwise the PHY chip
would always be held in reset state and can't be accessed by software.

I sent a similar patch several months ago but no response on this list,
would someone who has cvs commit right check and apply it?

-- 
Tao


diff -Naur freebios2-20050305-0000/src/include/device/pci_ids.h
freebios2-20050305-0000-lt/src/include/device/pci_ids.h
--- freebios2-20050305-0000/src/include/device/pci_ids.h	2004-12-11
04:50:43.000000000 +0800
+++ freebios2-20050305-0000-lt/src/include/device/pci_ids.h	2005-03-07
15:43:04.000000000 +0800
@@ -418,6 +418,7 @@
 #define PCI_DEVICE_ID_AMD_8111_SMB      0x746a
 #define PCI_DEVICE_ID_AMD_8111_ACPI     0x746b
 
+#define PCI_DEVICE_ID_AMD_8111_NIC	0x7462
 #define PCI_DEVICE_ID_AMD_8111_USB2     0x7463
 #define PCI_DEVICE_ID_AMD_8131_PCIX	0x7450
 #define PCI_DEVICE_ID_AMD_8131_IOAPIC   0x7451
diff -Naur freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c
freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/amd8111_nic.c
--- freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c	2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/amd8111_nic.c	2005-03-18
16:17:04.000000000 +0800
@@ -8,18 +8,82 @@
 #include <device/pci_ops.h>
 #include "amd8111.h"
 
+#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val))
 
+#define CMD3		0x54
+
+typedef enum {
+	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
+	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
+	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
+	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
+}VAL_BITS;
+
+typedef enum {
+	/* VAL3 */
+	ASF_INIT_DONE_ALIAS	= (1 << 29),
+	/* VAL2 */
+	JUMBO			= (1 << 21),
+	VSIZE			= (1 << 20),	
+	VLONLY			= (1 << 19),
+	VL_TAG_DEL		= (1 << 18),	
+	/* VAL1 */
+	EN_PMGR			= (1 << 14),			
+	INTLEVEL		= (1 << 13),
+	FORCE_FULL_DUPLEX	= (1 << 12),	
+	FORCE_LINK_STATUS	= (1 << 11),	
+	APEP			= (1 << 10),	
+	MPPLBA			= (1 << 9),	
+	/* VAL0 */
+	RESET_PHY_PULSE		= (1 << 2),	
+	RESET_PHY		= (1 << 1),	
+	PHY_RST_POL		= (1 << 0),	
+}CMD3_BITS;
+
+static void nic_init(struct device *dev)
+{
+	struct southbridge_amd_amd8111_config *conf;
+	struct resource *resource;
+	void *mmio;
+
+	conf = dev->chip_info;
+	resource = find_resource(dev, PCI_BASE_ADDRESS_0);
+	mmio = (void *)resource->base;
+
+	/* Hard Reset PHY */
+	printk_debug("Reseting PHY... ");
+	if (conf->phy_lowreset) {
+		writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3);
+	} else {
+		writel(VAL0 | RESET_PHY, mmio + CMD3);
+	}
+	mdelay(15);
+	writel(RESET_PHY, mmio + CMD3);
+	printk_debug("Done\n");
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0xc8,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+	
 static struct device_operations nic_ops  = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.enable           = amd8111_enable,
-	.init             = 0,
+	.init		  = nic_init,
 	.scan_bus         = 0,
+	.enable		  = amd8111_enable,
+	.ops_pci	  = &lops_pci,
 };
 
 static struct pci_driver nic_driver __pci_driver = {
 	.ops    = &nic_ops,
 	.vendor = PCI_VENDOR_ID_AMD,
-	.device = 0x7462,
+	.device = PCI_DEVICE_ID_AMD_8111_NIC,
 };
diff -Naur freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h
freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/chip.h
--- freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h	2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/chip.h	2005-03-07
16:12:27.000000000 +0800
@@ -5,6 +5,7 @@
 {
 	unsigned int ide0_enable : 1;
 	unsigned int ide1_enable : 1;
+	unsigned int phy_lowreset : 1;
 };
 
 struct chip_operations;



From ebiederman at lnxi.com  Fri Mar 18 11:18:46 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: 18 Mar 2005 03:18:46 -0700
Subject: [LinuxBIOS] [PATCH] amd8111_nic init
In-Reply-To: <8eca059b05031801302e0f89df@mail.gmail.com>
References: <8eca059b05031801302e0f89df@mail.gmail.com>
Message-ID: <m31xadtfy1.fsf@maxwell.lnxi.com>

Tao Liu <liutao1980 at gmail.com> writes:

> Hello,
> 
> This patch handles the phy reset pin's polarity. AMD8111's PHY_RESET pin
> is active high by default, but some PHY requires active low reset signal.
> On mainboards which use 8111's PHY_RESET pin to reset PHY the bios
> must select the correct PHY_RST_POL for 8111, otherwise the PHY chip
> would always be held in reset state and can't be accessed by software.
> 
> I sent a similar patch several months ago but no response on this list,
> would someone who has cvs commit right check and apply it?

Thanks, committed.

Eric



From stepan at openbios.org  Fri Mar 18 11:41:37 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Fri, 18 Mar 2005 11:41:37 +0100
Subject: [LinuxBIOS] CVS or TLA
In-Reply-To: <Pine.LNX.4.58.0503171435001.32005@enigma.lanl.gov>
References: <1111008754.3821.0.camel@logarithm.lanl.gov>
	<20050317001821.GD6422@openbios.org>
	<1111083093.4277.3.camel@logarithm.lanl.gov>
	<20050317182124.GA13698@openbios.org>
	<Pine.LNX.4.58.0503171435001.32005@enigma.lanl.gov>
Message-ID: <20050318104136.GF23583@openbios.org>

* Ronald G. Minnich <rminnich at lanl.gov> [050317 22:35]:
> > It is enough to use ssh. THOUGH: It is highly recommended that you sign
> > the commits so that the origin can be verified. (ie otherwise I could in
> > theory fake a commit done by you)
> 
> to make sure I understand: if I have a gpgkey, then the commit process 
> will automagically ensure that it is signed, which is not the case for 
> sshkey?

You have to do the following:
  $ mkdir -p ~/.arch-params/signing
  $ echo "gpg --clearsign" > ~/.arch-params/signing/\=default
  $ echo "gpg --verify-files -" > ~/.arch-params/signing/\=default.check


* gpg is only there to proof integrity of the checkins
* ssh only gives you access to the machine

Stefan




From jsteve17 at yahoo.com  Fri Mar 18 15:27:33 2005
From: jsteve17 at yahoo.com (Jeff Stevens)
Date: Fri, 18 Mar 2005 06:27:33 -0800 (PST)
Subject: [LinuxBIOS] Problems Setting The Opteron Address Map (resourcemap.c)
Message-ID: <20050318142733.30900.qmail@web41405.mail.yahoo.com>

I am trying to understand the Opteron Address Map, and
am having some problems.  I'm pretty sure I understand
everything but the PCI I/O section, but I have few
questions about the other sections also.  If there is
a good document to help one setup the address map,
other than the "AMD BIOS and Kernel Developer's
Guide", please let me know.

I have a Quad-Opteron system, with an AMD 8131 and AMD
8111 hanging off of CPU 0, and another AMD 8131
hanging off of CPU 1.  Each CPU has 4 DIMM slots for
DDR memory.

1. Does the DRAM map section pertain to the DDR SDRAM,
or is there an ability on the Opteron (as on some
other PPC processors I have dealt with) to hang
standard DRAM off of the local bus of the processor? 
If this is for DDR SDRAM, if I leave them all
disabled, do these get configured later when the BIOS
reads the SPD PROM for the DDR?  Or do I have to
configure a Window for each processor's maximum
allowable DDR SDRAM?

2. It seems that the Memory Mapped I/O section is
mainly to map the AMD 8111 and 8131s IO-APIC address
ranges (which seem to be 64KB in size).  Is this
correct, and is there anything else that should go
there (maybe PCI space)?

3. The PCI I/O section is my main problem.  I haven't
dealt with PCI too much in depth.  I don't understand
how it uses only 13 bits for the PCI I/O Base and
Limit addresses?  I thought that you need a 32-bit
address?  Please help me understand exactly what the
I/O base address is!  The only examples in the
LinuxBIOS tree have the AMD 8111 & 8131s hanging off
of one CPU, and therefor just steer all of the address
range to that HT link.

Thanks you in advance!

Jeff Stevens



		
__________________________________ 
Do you Yahoo!? 
Yahoo! Small Business - Try our new resources site!
http://smallbusiness.yahoo.com/resources/ 



From stepan at openbios.org  Fri Mar 18 15:54:41 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Fri, 18 Mar 2005 15:54:41 +0100
Subject: [LinuxBIOS] Problems Setting The Opteron Address Map
	(resourcemap.c)
In-Reply-To: <20050318142733.30900.qmail@web41405.mail.yahoo.com>
References: <20050318142733.30900.qmail@web41405.mail.yahoo.com>
Message-ID: <20050318145441.GA3112@openbios.org>

* Jeff Stevens <jsteve17 at yahoo.com> [050318 15:27]:
> If there is
> a good document to help one setup the address map,
> other than the "AMD BIOS and Kernel Developer's
> Guide", please let me know.

I'm afraid there is not.
 
> 1. Does the DRAM map section pertain to the DDR SDRAM,
> or is there an ability on the Opteron (as on some
> other PPC processors I have dealt with) to hang
> standard DRAM off of the local bus of the processor? 
> If this is for DDR SDRAM, if I leave them all
> disabled, do these get configured later when the BIOS
> reads the SPD PROM for the DDR?  Or do I have to
> configure a Window for each processor's maximum
> allowable DDR SDRAM?

They are supposed to be filled out by the SPDROM setup 
code of LinuxBIOS. Leave them untouched.
 
> 2. It seems that the Memory Mapped I/O section is
> mainly to map the AMD 8111 and 8131s IO-APIC address
> ranges (which seem to be 64KB in size).  Is this
> correct, and is there anything else that should go
> there (maybe PCI space)?
 
AFAIK this should stay untouched as well to be set up 
by LinuxBIOS.

> 3. The PCI I/O section is my main problem.  I haven't
> dealt with PCI too much in depth.  I don't understand
> how it uses only 13 bits for the PCI I/O Base and
> Limit addresses?  I thought that you need a 32-bit
> address?  

It is the upper bit range, so you automatically set these 
given a certain alignment.

> I/O base address is!  The only examples in the
> LinuxBIOS tree have the AMD 8111 & 8131s hanging off
> of one CPU, and therefor just steer all of the address
> range to that HT link.

No, have a look at the island/aruma board. It has 8131 
hanging off every single CPU.

Stefan




From Stephen.Kimball at bench.com  Fri Mar 18 22:01:23 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Fri, 18 Mar 2005 16:01:23 -0500
Subject: [LinuxBIOS] multiple devices in mainboard Config.lb
Message-ID: <9B124F08B3EFDA4F8813B05102DC719502905A24@nh-ex01.nh.bench.com>

I'm trying to write the mainboard Config.lb file to support a CK804 and an IO4 on one Opteron.  

I can write a mainboard Config.lb file that will boot the system from an IDE device, but that's only because new device table entries are created for the IDE device.  So I'm not using the static on_mainboard=1 entries.

I can write a Config.lb file to use the CK804, but incoherent.c bumps up the device numbers and northbridge.c moves the device to bus 1.  Then I get the PCI bus configured like this

Bus# 00, Dev# 18, Func# 0  --->  Vendor ID = 1022   Device ID = 1100
Bus# 00, Dev# 18, Func# 1  --->  Vendor ID = 1022   Device ID = 1101
Bus# 00, Dev# 18, Func# 2  --->  Vendor ID = 1022   Device ID = 1102
Bus# 00, Dev# 18, Func# 3  --->  Vendor ID = 1022   Device ID = 1103
Bus# 00, Dev# 19, Func# 0  --->  Vendor ID = 1022   Device ID = 1100
Bus# 00, Dev# 19, Func# 1  --->  Vendor ID = 1022   Device ID = 1101
Bus# 00, Dev# 19, Func# 2  --->  Vendor ID = 1022   Device ID = 1102
Bus# 00, Dev# 19, Func# 3  --->  Vendor ID = 1022   Device ID = 1103
Bus# 01, Dev# 01, Func# 0  --->  Vendor ID = 10DE   Device ID = 005E
Bus# 01, Dev# 02, Func# 0  --->  Vendor ID = 10DE   Device ID = 0051
Bus# 01, Dev# 02, Func# 1  --->  Vendor ID = 10DE   Device ID = 0052
Bus# 01, Dev# 02, Func# 2  --->  Vendor ID = 10DE   Device ID = 005F
Bus# 01, Dev# 03, Func# 0  --->  Vendor ID = 10DE   Device ID = 005A
Bus# 01, Dev# 03, Func# 1  --->  Vendor ID = 10DE   Device ID = 005B
Bus# 01, Dev# 05, Func# 0  --->  Vendor ID = 10DE   Device ID = 0059
Bus# 01, Dev# 05, Func# 1  --->  Vendor ID = 10DE   Device ID = 0058
Bus# 01, Dev# 07, Func# 0  --->  Vendor ID = 10DE   Device ID = 0053
Bus# 01, Dev# 08, Func# 0  --->  Vendor ID = 10DE   Device ID = 0054
Bus# 01, Dev# 09, Func# 0  --->  Vendor ID = 10DE   Device ID = 0055
Bus# 01, Dev# 0A, Func# 0  --->  Vendor ID = 10DE   Device ID = 005C
Bus# 01, Dev# 0B, Func# 0  --->  Vendor ID = 10DE   Device ID = 0056
Bus# 01, Dev# 0C, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 01, Dev# 0D, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 01, Dev# 0E, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 01, Dev# 0F, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 03, Dev# 01, Func# 0  --->  Vendor ID = 10DE   Device ID = 005E
Bus# 03, Dev# 02, Func# 0  --->  Vendor ID = 10DE   Device ID = 00D3
Bus# 03, Dev# 02, Func# 1  --->  Vendor ID = 10DE   Device ID = 0052
Bus# 03, Dev# 02, Func# 2  --->  Vendor ID = 10DE   Device ID = 005F
Bus# 03, Dev# 08, Func# 0  --->  Vendor ID = 10DE   Device ID = 0054
Bus# 03, Dev# 09, Func# 0  --->  Vendor ID = 10DE   Device ID = 0055
Bus# 03, Dev# 0B, Func# 0  --->  Vendor ID = 10DE   Device ID = 0056
Bus# 03, Dev# 0C, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 03, Dev# 0D, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 03, Dev# 0E, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 03, Dev# 0F, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D


If I add "device pci_domain" statements before the devices, I get this
                                                                                                                                                             
Bus# 00, Dev# 18, Func# 0  --->  Vendor ID = 1022   Device ID = 1100
Bus# 00, Dev# 18, Func# 1  --->  Vendor ID = 1022   Device ID = 1101
Bus# 00, Dev# 18, Func# 2  --->  Vendor ID = 1022   Device ID = 1102
Bus# 00, Dev# 18, Func# 3  --->  Vendor ID = 1022   Device ID = 1103
Bus# 00, Dev# 19, Func# 0  --->  Vendor ID = 1022   Device ID = 1100
Bus# 00, Dev# 19, Func# 1  --->  Vendor ID = 1022   Device ID = 1101
Bus# 00, Dev# 19, Func# 2  --->  Vendor ID = 1022   Device ID = 1102
Bus# 00, Dev# 19, Func# 3  --->  Vendor ID = 1022   Device ID = 1103
Bus# 01, Dev# 00, Func# 0  --->  Vendor ID = 10DE   Device ID = 005E
Bus# 01, Dev# 01, Func# 0  --->  Vendor ID = 10DE   Device ID = 0051
Bus# 01, Dev# 01, Func# 1  --->  Vendor ID = 10DE   Device ID = 0052
Bus# 01, Dev# 01, Func# 2  --->  Vendor ID = 10DE   Device ID = 005F
Bus# 01, Dev# 02, Func# 0  --->  Vendor ID = 10DE   Device ID = 005A
Bus# 01, Dev# 02, Func# 1  --->  Vendor ID = 10DE   Device ID = 005B
Bus# 01, Dev# 04, Func# 0  --->  Vendor ID = 10DE   Device ID = 0059
Bus# 01, Dev# 04, Func# 1  --->  Vendor ID = 10DE   Device ID = 0058
Bus# 01, Dev# 06, Func# 0  --->  Vendor ID = 10DE   Device ID = 0053
Bus# 01, Dev# 07, Func# 0  --->  Vendor ID = 10DE   Device ID = 0054
Bus# 01, Dev# 08, Func# 0  --->  Vendor ID = 10DE   Device ID = 0055
Bus# 01, Dev# 09, Func# 0  --->  Vendor ID = 10DE   Device ID = 005C
Bus# 01, Dev# 0A, Func# 0  --->  Vendor ID = 10DE   Device ID = 0056
Bus# 01, Dev# 0B, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 01, Dev# 0C, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 01, Dev# 0D, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 01, Dev# 0E, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 02, Dev# 00, Func# 0  --->  Vendor ID = 10DE   Device ID = 005E
Bus# 02, Dev# 01, Func# 0  --->  Vendor ID = 10DE   Device ID = 00D3
Bus# 02, Dev# 01, Func# 1  --->  Vendor ID = 10DE   Device ID = 0052
Bus# 02, Dev# 01, Func# 2  --->  Vendor ID = 10DE   Device ID = 005F
Bus# 02, Dev# 07, Func# 0  --->  Vendor ID = 10DE   Device ID = 0054
Bus# 02, Dev# 08, Func# 0  --->  Vendor ID = 10DE   Device ID = 0055
Bus# 02, Dev# 0A, Func# 0  --->  Vendor ID = 10DE   Device ID = 0056
Bus# 02, Dev# 0B, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 02, Dev# 0C, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 02, Dev# 0D, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
Bus# 02, Dev# 0E, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
                                                                                                                                                             
So why does incoherent.c need to bump up the device numbers when the devices are on different busses?  There should be no device number conflicts?  No matter what I do, LinuxBIOS always creates new device table entries, because my Config.lb file has the devices on the wrong bus - 0.  The config file doesn't specify a device's bus and it doesn't assume a bus from the domain statement.  How is this suppose to work?

Attached is my Config.lb file.

Thanks for the help.

Steve Kimball     
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From yinghailu at gmail.com  Fri Mar 18 23:27:49 2005
From: yinghailu at gmail.com (yhlu)
Date: Fri, 18 Mar 2005 14:27:49 -0800
Subject: [LinuxBIOS] multiple devices in mainboard Config.lb
In-Reply-To: <9B124F08B3EFDA4F8813B05102DC719502905A24@nh-ex01.nh.bench.com>
References: <9B124F08B3EFDA4F8813B05102DC719502905A24@nh-ex01.nh.bench.com>
Message-ID: <2ea3fae105031814277e7c995@mail.gmail.com>

the first one is right.

bus 2 is leave for bus under your master ck804 pci bus behind pci bridge 1:a.0

YH


On Fri, 18 Mar 2005 16:01:23 -0500, Stephen.Kimball at bench.com
<Stephen.Kimball at bench.com> wrote:
> I'm trying to write the mainboard Config.lb file to support a CK804 and an IO4 on one Opteron.
> 
> I can write a mainboard Config.lb file that will boot the system from an IDE device, but that's only because new device table entries are created for the IDE device.  So I'm not using the static on_mainboard=1 entries.
> 
> I can write a Config.lb file to use the CK804, but incoherent.c bumps up the device numbers and northbridge.c moves the device to bus 1.  Then I get the PCI bus configured like this
> 
> Bus# 00, Dev# 18, Func# 0  --->  Vendor ID = 1022   Device ID = 1100
> Bus# 00, Dev# 18, Func# 1  --->  Vendor ID = 1022   Device ID = 1101
> Bus# 00, Dev# 18, Func# 2  --->  Vendor ID = 1022   Device ID = 1102
> Bus# 00, Dev# 18, Func# 3  --->  Vendor ID = 1022   Device ID = 1103
> Bus# 00, Dev# 19, Func# 0  --->  Vendor ID = 1022   Device ID = 1100
> Bus# 00, Dev# 19, Func# 1  --->  Vendor ID = 1022   Device ID = 1101
> Bus# 00, Dev# 19, Func# 2  --->  Vendor ID = 1022   Device ID = 1102
> Bus# 00, Dev# 19, Func# 3  --->  Vendor ID = 1022   Device ID = 1103
> Bus# 01, Dev# 01, Func# 0  --->  Vendor ID = 10DE   Device ID = 005E
> Bus# 01, Dev# 02, Func# 0  --->  Vendor ID = 10DE   Device ID = 0051
> Bus# 01, Dev# 02, Func# 1  --->  Vendor ID = 10DE   Device ID = 0052
> Bus# 01, Dev# 02, Func# 2  --->  Vendor ID = 10DE   Device ID = 005F
> Bus# 01, Dev# 03, Func# 0  --->  Vendor ID = 10DE   Device ID = 005A
> Bus# 01, Dev# 03, Func# 1  --->  Vendor ID = 10DE   Device ID = 005B
> Bus# 01, Dev# 05, Func# 0  --->  Vendor ID = 10DE   Device ID = 0059
> Bus# 01, Dev# 05, Func# 1  --->  Vendor ID = 10DE   Device ID = 0058
> Bus# 01, Dev# 07, Func# 0  --->  Vendor ID = 10DE   Device ID = 0053
> Bus# 01, Dev# 08, Func# 0  --->  Vendor ID = 10DE   Device ID = 0054
> Bus# 01, Dev# 09, Func# 0  --->  Vendor ID = 10DE   Device ID = 0055
> Bus# 01, Dev# 0A, Func# 0  --->  Vendor ID = 10DE   Device ID = 005C
> Bus# 01, Dev# 0B, Func# 0  --->  Vendor ID = 10DE   Device ID = 0056
> Bus# 01, Dev# 0C, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 01, Dev# 0D, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 01, Dev# 0E, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 01, Dev# 0F, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 03, Dev# 01, Func# 0  --->  Vendor ID = 10DE   Device ID = 005E
> Bus# 03, Dev# 02, Func# 0  --->  Vendor ID = 10DE   Device ID = 00D3
> Bus# 03, Dev# 02, Func# 1  --->  Vendor ID = 10DE   Device ID = 0052
> Bus# 03, Dev# 02, Func# 2  --->  Vendor ID = 10DE   Device ID = 005F
> Bus# 03, Dev# 08, Func# 0  --->  Vendor ID = 10DE   Device ID = 0054
> Bus# 03, Dev# 09, Func# 0  --->  Vendor ID = 10DE   Device ID = 0055
> Bus# 03, Dev# 0B, Func# 0  --->  Vendor ID = 10DE   Device ID = 0056
> Bus# 03, Dev# 0C, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 03, Dev# 0D, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 03, Dev# 0E, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 03, Dev# 0F, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> 
> If I add "device pci_domain" statements before the devices, I get this
> 
> Bus# 00, Dev# 18, Func# 0  --->  Vendor ID = 1022   Device ID = 1100
> Bus# 00, Dev# 18, Func# 1  --->  Vendor ID = 1022   Device ID = 1101
> Bus# 00, Dev# 18, Func# 2  --->  Vendor ID = 1022   Device ID = 1102
> Bus# 00, Dev# 18, Func# 3  --->  Vendor ID = 1022   Device ID = 1103
> Bus# 00, Dev# 19, Func# 0  --->  Vendor ID = 1022   Device ID = 1100
> Bus# 00, Dev# 19, Func# 1  --->  Vendor ID = 1022   Device ID = 1101
> Bus# 00, Dev# 19, Func# 2  --->  Vendor ID = 1022   Device ID = 1102
> Bus# 00, Dev# 19, Func# 3  --->  Vendor ID = 1022   Device ID = 1103
> Bus# 01, Dev# 00, Func# 0  --->  Vendor ID = 10DE   Device ID = 005E
> Bus# 01, Dev# 01, Func# 0  --->  Vendor ID = 10DE   Device ID = 0051
> Bus# 01, Dev# 01, Func# 1  --->  Vendor ID = 10DE   Device ID = 0052
> Bus# 01, Dev# 01, Func# 2  --->  Vendor ID = 10DE   Device ID = 005F
> Bus# 01, Dev# 02, Func# 0  --->  Vendor ID = 10DE   Device ID = 005A
> Bus# 01, Dev# 02, Func# 1  --->  Vendor ID = 10DE   Device ID = 005B
> Bus# 01, Dev# 04, Func# 0  --->  Vendor ID = 10DE   Device ID = 0059
> Bus# 01, Dev# 04, Func# 1  --->  Vendor ID = 10DE   Device ID = 0058
> Bus# 01, Dev# 06, Func# 0  --->  Vendor ID = 10DE   Device ID = 0053
> Bus# 01, Dev# 07, Func# 0  --->  Vendor ID = 10DE   Device ID = 0054
> Bus# 01, Dev# 08, Func# 0  --->  Vendor ID = 10DE   Device ID = 0055
> Bus# 01, Dev# 09, Func# 0  --->  Vendor ID = 10DE   Device ID = 005C
> Bus# 01, Dev# 0A, Func# 0  --->  Vendor ID = 10DE   Device ID = 0056
> Bus# 01, Dev# 0B, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 01, Dev# 0C, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 01, Dev# 0D, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 01, Dev# 0E, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 02, Dev# 00, Func# 0  --->  Vendor ID = 10DE   Device ID = 005E
> Bus# 02, Dev# 01, Func# 0  --->  Vendor ID = 10DE   Device ID = 00D3
> Bus# 02, Dev# 01, Func# 1  --->  Vendor ID = 10DE   Device ID = 0052
> Bus# 02, Dev# 01, Func# 2  --->  Vendor ID = 10DE   Device ID = 005F
> Bus# 02, Dev# 07, Func# 0  --->  Vendor ID = 10DE   Device ID = 0054
> Bus# 02, Dev# 08, Func# 0  --->  Vendor ID = 10DE   Device ID = 0055
> Bus# 02, Dev# 0A, Func# 0  --->  Vendor ID = 10DE   Device ID = 0056
> Bus# 02, Dev# 0B, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 02, Dev# 0C, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 02, Dev# 0D, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> Bus# 02, Dev# 0E, Func# 0  --->  Vendor ID = 10DE   Device ID = 005D
> 
> So why does incoherent.c need to bump up the device numbers when the devices are on different busses?  There should be no device number conflicts?  No matter what I do, LinuxBIOS always creates new device table entries, because my Config.lb file has the devices on the wrong bus - 0.  The config file doesn't specify a device's bus and it doesn't assume a bus from the domain statement.  How is this suppose to work?
> 
> Attached is my Config.lb file.
> 
> Thanks for the help.
> 
> Steve Kimball
> 
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 
> 
>



From florian-zeitz at lycos.de  Sun Mar 20 14:50:06 2005
From: florian-zeitz at lycos.de (Florian Zeitz)
Date: Sun, 20 Mar 2005 14:50:06 +0100
Subject: [LinuxBIOS] Re: "Options.lb 2 XML" the 2nd
In-Reply-To: <20050319195414.GA26244@openbios.org>
References: <4234596E.6050506@lycos.de> <20050319195414.GA26244@openbios.org>
Message-ID: <423D7F8E.9020007@lycos.de>

Stefan Reinauer wrote:

> Ok, I checked the script into the arch repository now, utils/optionlist.
>
>I changed the xsl sheet slightly so it works with my version of xsltproc
>and saxon. Which xsl processor are you using?
>
>Thanks for your work
>
>Stefan
>
>  
>
To be honest I tried so many different xsl processors that I really 
can't remember what I finally used.
I think it was a good idea to make it XSLT 1.0 (again (I had it written 
in XSLT 1.0 first, too) as it seems a lot more processors can handle it. 
You might want to completely remove the xsl:choose stuff (so basically 
what is commented right now) it was a hack to get the xml (the 
unprocessed of course) to show correctly in firefox and is specific to 
XSLT 2.0 anyway because it uses xhtml as method.



From markuswolters at gmx.de  Sun Mar 20 18:05:16 2005
From: markuswolters at gmx.de (Markus Wolters)
Date: Sun, 20 Mar 2005 18:05:16 +0100
Subject: [LinuxBIOS] How to flash the bios?
Message-ID: <mailman.41.1355070981.16123.coreboot@coreboot.org>

Hello,

 

I have compiled and build freebios and everything went ok. The romimage is
at /usr/src/freebios/build.

My mainboard is a K7SEM. When I do flash_rom, this error message appears :

 

2f is 0xfd

EEPROM not found

 

I'm not sure what I'm doing wrong. How do I have to flash the image?

 

Thanks

 

Markus

 

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From slavik914 at mrbrklyn.com  Sun Mar 20 20:39:00 2005
From: slavik914 at mrbrklyn.com (Steve Milo)
Date: Sun, 20 Mar 2005 14:39:00 -0500 (EST)
Subject: [LinuxBIOS] Re: "Options.lb 2 XML" the 2nd
In-Reply-To: <423D7F8E.9020007@lycos.de>
Message-ID: <Pine.LNX.4.44.0503201436320.25058-100000@www2.mrbrklyn.com>

Pardon me but, am I to understand that XML is implemented in a firmware
environment?!

Steve M

On Sun, 20 Mar 2005, Florian Zeitz wrote:

> Stefan Reinauer wrote:
>
> > Ok, I checked the script into the arch repository now, utils/optionlist.
> >
> >I changed the xsl sheet slightly so it works with my version of xsltproc
> >and saxon. Which xsl processor are you using?
> >
> >Thanks for your work
> >
> >Stefan
> >
> >
> >
> To be honest I tried so many different xsl processors that I really
> can't remember what I finally used.
> I think it was a good idea to make it XSLT 1.0 (again (I had it written
> in XSLT 1.0 first, too) as it seems a lot more processors can handle it.
> You might want to completely remove the xsl:choose stuff (so basically
> what is commented right now) it was a hack to get the xml (the
> unprocessed of course) to show correctly in firefox and is specific to
> XSLT 2.0 anyway because it uses xhtml as method.
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>




From stepan at openbios.org  Mon Mar 21 00:39:06 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Mon, 21 Mar 2005 00:39:06 +0100
Subject: [LinuxBIOS] Re: "Options.lb 2 XML" the 2nd
In-Reply-To: <Pine.LNX.4.44.0503201436320.25058-100000@www2.mrbrklyn.com>
References: <423D7F8E.9020007@lycos.de>
	<Pine.LNX.4.44.0503201436320.25058-100000@www2.mrbrklyn.com>
Message-ID: <20050320233906.GA13093@openbios.org>

* Steve Milo <slavik914 at mrbrklyn.com> [050320 20:39]:
> Pardon me but, am I to understand that XML is implemented in a firmware
> environment?!
 
for the purpose of automatically creating up to date documentation from
the code, yes indeed. There is no xml involved on the firmware level
itself.

Stefan
 



From markuswolters at gmx.de  Mon Mar 21 09:04:48 2005
From: markuswolters at gmx.de (Markus Wolters)
Date: Mon, 21 Mar 2005 09:04:48 +0100
Subject: [LinuxBIOS] RE: How to flash the bios?
In-Reply-To: <20050320202709.35965f02@sunder>
Message-ID: <mailman.42.1355070981.16123.coreboot@coreboot.org>


> Once you have identified the part, let us know what it is exactly and if
> we don't already have support for it in the flash_rom utility, we might
> be able to add support for it.

It's the original bios chip. 
It is labelled:
PMC Flash
MFCN5
0231
Pm29F002T-90PC




From Stephen.Kimball at bench.com  Mon Mar 21 14:04:34 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Mon, 21 Mar 2005 08:04:34 -0500
Subject: [LinuxBIOS] multiple devices in mainboard Config.lb
Message-ID: <9B124F08B3EFDA4F8813B05102DC719502905A25@nh-ex01.nh.bench.com>

OK, that makes sense.  So how do I specify bus 1 and 3 in the Config file?

Steve

-----Original Message-----
From: yhlu [mailto:yinghailu at gmail.com] 
Sent: Friday, March 18, 2005 5:28 PM
To: Kimball, Stephen
Cc: linuxbios at openbios.org
Subject: Re: [LinuxBIOS] multiple devices in mainboard Config.lb

the first one is right.

bus 2 is leave for bus under your master ck804 pci bus behind pci bridge 1:a.0

YH



From rminnich at lanl.gov  Mon Mar 21 15:06:20 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon, 21 Mar 2005 07:06:20 -0700 (MST)
Subject: [LinuxBIOS] RE: How to flash the bios?
In-Reply-To: <200503210806.j2L86ba1020089@proofpoint2.lanl.gov>
References: <200503210806.j2L86ba1020089@proofpoint2.lanl.gov>
Message-ID: <Pine.LNX.4.58.0503210705560.9600@enigma.lanl.gov>



On Mon, 21 Mar 2005, Markus Wolters wrote:

> Pm29F002T-90PC

I think that should have worked. I suggest you try the flash_rom from 
freeebios2 -- it has more parts supported.

ron



From Stephen.Kimball at bench.com  Mon Mar 21 18:34:23 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Mon, 21 Mar 2005 12:34:23 -0500
Subject: [LinuxBIOS] multiple devices in mainboard Config.lb
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40BD1@nh-ex01.nh.bench.com>

YH,
I found that moving my changes to the latest LinuxBIOS source makes a difference.  Now the device tree entries magically are put on a more correct bus.  But LinuxBIOS uses different busses depending on how I number the devices.  If I number the PCI devices to power up defaults, then the device table uses bus 1 for the first CK804 and 3 for the second.  If I number them with the bumped up device numbers given by incoherent.c then it uses busses 1 and 2. I would assume that the Config.lb file would use the device's power up default values?  

I'm dumping the device tree in device.c after "Devices initialized" with

printk_info("Dev tree...\n");
for(dev = all_devices; dev; dev = dev->next) {
       bus = dev->bus;
       printk_info("%s bus %d link %d ", dev_path(dev), bus->secondary, bus->link);
       printk_info(" sibling %s ", dev_path(dev->sibling));
       printk_info(" next %s\n", dev_path(dev->next));
       printk_info(" vendor %x ", dev->vendor);
       printk_info(" on_mainboard %x ", dev->on_mainboard);
       printk_info(" enabled %x ", dev->enabled);
       printk_info(" have_resources %x ", dev->have_resources);
       printk_info(" initialized %x\n", dev->initialized);
}
printk_info("End of tree\n");

Thanks.

Steve  

-----Original Message-----
From: Kimball, Stephen 
Sent: Monday, March 21, 2005 8:05 AM
To: yinghailu at gmail.com
Cc: linuxbios at openbios.org
Subject: RE: [LinuxBIOS] multiple devices in mainboard Config.lb

OK, that makes sense.  So how do I specify bus 1 and 3 in the Config file?

Steve

-----Original Message-----
From: yhlu [mailto:yinghailu at gmail.com] 
Sent: Friday, March 18, 2005 5:28 PM
To: Kimball, Stephen
Cc: linuxbios at openbios.org
Subject: Re: [LinuxBIOS] multiple devices in mainboard Config.lb

the first one is right.

bus 2 is leave for bus under your master ck804 pci bus behind pci bridge 1:a.0

YH

_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios



From ourlinuxid at yahoo.co.in  Tue Mar 22 07:12:46 2005
From: ourlinuxid at yahoo.co.in (Ramesh Chhaba)
Date: Tue, 22 Mar 2005 06:12:46 +0000 (GMT)
Subject: [LinuxBIOS] Help regarding compiling and building bios
Message-ID: <20050322061246.83549.qmail@web8408.mail.in.yahoo.com>

Hi All ,
 
   I am a newbie in the fiels of LinuxBios, I want to make linuxbios for the 
STPC Atlas , I know it is not supported in the freebios2
but it is supprted in the freebios (1).
Bit I have found making of first version is diffrent from that of
freebios2 .
I want to use Etherboot as payload for this bios.
Somebody plz do this favour for me that tell me exact steps
1. Downloading freebios version 1 (Usually when i download it misses some files)
2. Compiling etherboot as payload.
3. Compiling and building freeebios
It is very odd ,i am not knowing anything :(( 
But I have been caught in few errors during compiling 
and dont know exavt steps
I want final output as a rom image that i can burn into BIOS chip.
Thanks in advance
Ramesh Chander
   
 

Yahoo! India Matrimony: Find your life partneronline.
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From smithbone at gmail.com  Tue Mar 22 16:38:49 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 22 Mar 2005 09:38:49 -0600
Subject: [LinuxBIOS] Help regarding compiling and building bios
In-Reply-To: <20050322061246.83549.qmail@web8408.mail.in.yahoo.com>
References: <20050322061246.83549.qmail@web8408.mail.in.yahoo.com>
Message-ID: <8a0c36780503220738670a13fd@mail.gmail.com>

>    I am a newbie in the fiels of LinuxBios, I want to make linuxbios for the
> STPC Atlas , I know it is not supported in the freebios2
> but it is supprted in the freebios (1). 

I don't think the Atlas is supported.  Whats in V1 is the consumer2
product.  Offhand I don't remember the difference between the 2.

> Bit I have found making of first version is diffrent from that of
> freebios2 . 
> I want to use Etherboot as payload for this bios. 
> Somebody plz do this favour for me that tell me exact steps 
> 1. Downloading freebios version 1 (Usually when i download it misses some
> files) 

Which files?

> 2. Compiling etherboot as payload. 

I've attached a FAQ I did a long time ago.  It has some stuff on
etherboot wich may be useful.  Its almost 2 years old though so use it
more as a guideline rather than an absolute reference.

> 3. Compiling and building freeebios 

1) Create a build directory somewhere outside the linubios tree.  Lets
use lb_atlas for example.

In lb_atlas create a config file: atlas.config.  In this file you need
at minimum

target         src
mainboard  stpc/consumer2

payload <path_to_etherboot_image>

There are probally lots of other options you may need to include.  You
will have to look at the source code to figure out what they need to
be.

Then run the following:

python /path/to/freebios/util/config/NLBConfig.py
/path/to/lb_atlas/atlas.config /path/to/freebios

This will create a lb_atlas/src directory with all the source for a
consumer setup.

Then you cd to src and type make.

> I want final output as a rom image that i can burn into BIOS chip. 

The final output will be called romimage

-- 
Richard A. Smith



From ourlinuxid at yahoo.co.in  Wed Mar 23 06:25:55 2005
From: ourlinuxid at yahoo.co.in (Ramesh Chhaba)
Date: Wed, 23 Mar 2005 05:25:55 +0000 (GMT)
Subject: [LinuxBIOS] Help regarding compiling and building bios
In-Reply-To: <8a0c36780503220738670a13fd@mail.gmail.com>
Message-ID: <20050323052555.18693.qmail@web8406.mail.in.yahoo.com>

Hi 
Thanks for ur support .
Somehow I am able to get full source code
yes u r right , Atlas is not supported ,
But i think I can manage to convert Elite/Consumer  to Atlas which is supported.
 

>I've attached a FAQ I did a long time ago. It has some stuff on
>etherboot wich may be useful. Its almost 2 years old though so use it
 
U might have forgot to attach that file   :(( ,
I have made a BOOTROM for NIC card can it be attached as payload by converting it in to ELF image
 or I have to make any other special motherboard specific image.
???
 
 
>There are probally lots of other options you may need to include. You
>will have to look at the source code to figure out what they need to
>be.
 
Is there any guideline  from where to find thwe other suitable option.
 
Plz provide me help regarding these topics
Ramesh Chander


 


Richard Smith <smithbone at gmail.com> wrote:
> I am a newbie in the fiels of LinuxBios, I want to make linuxbios for the
> STPC Atlas , I know it is not supported in the freebios2
> but it is supprted in the freebios (1). 

I don't think the Atlas is supported. Whats in V1 is the consumer2
product. Offhand I don't remember the difference between the 2.

> Bit I have found making of first version is diffrent from that of
> freebios2 . 
> I want to use Etherboot as payload for this bios. 
> Somebody plz do this favour for me that tell me exact steps 
> 1. Downloading freebios version 1 (Usually when i download it misses some
> files) 

Which files?

> 2. Compiling etherboot as payload. 

I've attached a FAQ I did a long time ago. It has some stuff on
etherboot wich may be useful. Its almost 2 years old though so use it
more as a guideline rather than an absolute reference.

> 3. Compiling and building freeebios 

1) Create a build directory somewhere outside the linubios tree. Lets
use lb_atlas for example.

In lb_atlas create a config file: atlas.config. In this file you need
at minimum

target src
mainboard stpc/consumer2

payload 


There are probally lots of other options you may need to include. You
will have to look at the source code to figure out what they need to
be.

Then run the following:

python /path/to/freebios/util/config/NLBConfig.py
/path/to/lb_atlas/atlas.config /path/to/freebios

This will create a lb_atlas/src directory with all the source for a
consumer setup.

Then you cd to src and type make.

> I want final output as a rom image that i can burn into BIOS chip. 

The final output will be called romimage

-- 
Richard A. Smith

Yahoo! India Matrimony: Find your life partneronline.
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From smithbone at gmail.com  Wed Mar 23 15:58:12 2005
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 23 Mar 2005 08:58:12 -0600
Subject: [LinuxBIOS] Help regarding compiling and building bios
In-Reply-To: <20050323052555.18693.qmail@web8406.mail.in.yahoo.com>
References: <8a0c36780503220738670a13fd@mail.gmail.com>
	<20050323052555.18693.qmail@web8406.mail.in.yahoo.com>
Message-ID: <8a0c367805032306581ae49aee@mail.gmail.com>

On Wed, 23 Mar 2005 05:25:55 +0000 (GMT), Ramesh Chhaba
<ourlinuxid at yahoo.co.in> wrote:

> >I've attached a FAQ I did a long time ago. It has some stuff on
> >etherboot wich may be useful. Its almost 2 years old though so use it 
>   
> U might have forgot to attach that file   :(( , 

oops sorry.  Here it is. 

> I have made a BOOTROM for NIC card can it be attached as payload by
> converting it in to ELF image 
>  or I have to make any other special motherboard specific image. 

Did you re-compile or get one of the pre-built ones? I seem to
remember you have to recompile with some special options set.

> >There are probally lots of other options you may need to include. You
> >will have to look at the source code to figure out what they need to
> >be. 
>   
> Is there any guideline  from where to find thwe other suitable option. 

Nope the only real reference is the source code.

-- 
Richard A. Smith
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From stuge-linuxbios at cdy.org  Thu Mar 24 16:04:10 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 24 Mar 2005 16:04:10 +0100
Subject: [LinuxBIOS] Re: Notebook 340s2 (sis630) 256k Flash
In-Reply-To: <8a0c367805032406553e8696d3@mail.gmail.com>
References: <42408A19.4080007@1en.de>
	<8a0c36780503221317f6614e6@mail.gmail.com>
	<4240A642.3050003@1en.de> <4241F9D4.1010509@1en.de>
	<4241FBA9.3050705@onelabs.com>
	<Pine.LNX.4.61.0503241103030.10117@labor.neusy>
	<8a0c367805032406553e8696d3@mail.gmail.com>
Message-ID: <20050324150410.GC9588@foo.birdnet.se>

On Thu, Mar 24, 2005 at 08:55:57AM -0600, Richard Smith wrote:
> It means that the 87570 may have control of the write enable line
> on the flash.  If its not asserted no writes to the flash will be
> possible unless you pull the chip.

I got the impression that he tested the first flash with an external
programmer, although it would certainly be nice to add support for
the system to flash_rom.


//Peter



From stuge-linuxbios at cdy.org  Thu Mar 24 16:13:13 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 24 Mar 2005 16:13:13 +0100
Subject: [LinuxBIOS] Re: .bin final size [was: Error in compiling STPC
	Consumer]
In-Reply-To: <Pine.LNX.4.58.0503240800580.17754@enigma.lanl.gov>
References: <8a0c36780503230709586f04be@mail.gmail.com>
	<20050324055417.18547.qmail@web8410.mail.in.yahoo.com>
	<8a0c367805032400153fc815bb@mail.gmail.com>
	<Pine.LNX.4.58.0503240800580.17754@enigma.lanl.gov>
Message-ID: <20050324151313.GD9588@foo.birdnet.se>

(Is @clustermatic.org still working?)

On Thu, Mar 24, 2005 at 08:01:09AM -0700, Ronald G. Minnich wrote:
> On Thu, 24 Mar 2005, Richard Smith wrote:
> > On Thu, 24 Mar 2005 05:54:17 +0000 (GMT), Ramesh Chhaba 
> > <ourlinuxid at yahoo.co.in> wrote:
> > > But I want to make my romimage within 256KB 
> > >   
> > > So what options I acn change to do that 
> > > currently my image is 356 (approx) KB 
> > 
> > PAY_LOAD_SIZE is not a maximum size.  its the blocksize option
> > thats used in the 'dd' statemnet that copies the payload into a
> > file.  So 64k is the minimum it will be but it could be 128k,
> > 192k, 256k, etc.
> > 
> > Make your ROM_SIZE be the size you want the image - payload size.
> > You can see all the magic for this in the makefile that the
> > config tool generates.  I remember I had to tweak with my numbers
> > till I got to to come out the right size.
> 
> this is a clear FAQ entry.

I wish I understood it better, I guess I should take a look at the
Makefile..


//Peter



From rminnich at lanl.gov  Thu Mar 24 16:50:38 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 24 Mar 2005 08:50:38 -0700 (MST)
Subject: [LinuxBIOS] Re: .bin final size [was: Error in compiling STPC
	Consumer]
In-Reply-To: <20050324151313.GD9588@foo.birdnet.se>
References: <8a0c36780503230709586f04be@mail.gmail.com>
	<20050324055417.18547.qmail@web8410.mail.in.yahoo.com>
	<8a0c367805032400153fc815bb@mail.gmail.com>
	<Pine.LNX.4.58.0503240800580.17754@enigma.lanl.gov>
	<20050324151313.GD9588@foo.birdnet.se>
Message-ID: <Pine.LNX.4.58.0503240850260.17754@enigma.lanl.gov>



On Thu, 24 Mar 2005, Peter Stuge wrote:

> (Is @clustermatic.org still working?)

it is *supposed* to be dead.

ron



From smithbone at gmail.com  Thu Mar 24 17:11:52 2005
From: smithbone at gmail.com (Richard Smith)
Date: Thu, 24 Mar 2005 10:11:52 -0600
Subject: [LinuxBIOS] Re: .bin final size [was: Error in compiling STPC
	Consumer]
In-Reply-To: <Pine.LNX.4.58.0503240850260.17754@enigma.lanl.gov>
References: <8a0c36780503230709586f04be@mail.gmail.com>
	<20050324055417.18547.qmail@web8410.mail.in.yahoo.com>
	<8a0c367805032400153fc815bb@mail.gmail.com>
	<Pine.LNX.4.58.0503240800580.17754@enigma.lanl.gov>
	<20050324151313.GD9588@foo.birdnet.se>
	<Pine.LNX.4.58.0503240850260.17754@enigma.lanl.gov>
Message-ID: <8a0c367805032408115bd91114@mail.gmail.com>

> 
> it is *supposed* to be dead.

I didn't realize we had fully cut over yet.  Should I be changing  all
the responses to openbios.org as they come in or will there be some
sort of forward?

-- 
Richard A. Smith



From rminnich at lanl.gov  Thu Mar 24 17:15:34 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 24 Mar 2005 09:15:34 -0700 (MST)
Subject: [LinuxBIOS] Re: .bin final size [was: Error in compiling STPC
	Consumer]
In-Reply-To: <8a0c367805032408115bd91114@mail.gmail.com>
References: <8a0c36780503230709586f04be@mail.gmail.com> 
	<20050324055417.18547.qmail@web8410.mail.in.yahoo.com> 
	<8a0c367805032400153fc815bb@mail.gmail.com>
	<Pine.LNX.4.58.0503240800580.17754@enigma.lanl.gov>
	<20050324151313.GD9588@foo.birdnet.se>
	<Pine.LNX.4.58.0503240850260.17754@enigma.lanl.gov>
	<8a0c367805032408115bd91114@mail.gmail.com>
Message-ID: <Pine.LNX.4.58.0503240915200.17754@enigma.lanl.gov>



On Thu, 24 Mar 2005, Richard Smith wrote:

> I didn't realize we had fully cut over yet.  Should I be changing  all
> the responses to openbios.org as they come in or will there be some
> sort of forward?

try to change response and see how it works.

ron




From rminnich at lanl.gov  Thu Mar 24 17:16:42 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 24 Mar 2005 09:16:42 -0700 (MST)
Subject: [LinuxBIOS] cutting over
Message-ID: <Pine.LNX.4.58.0503240916310.17754@enigma.lanl.gov>


I'm now cut over :-)

ron



From rminnich at lanl.gov  Fri Mar 25 22:20:13 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 25 Mar 2005 14:20:13 -0700 (MST)
Subject: [LinuxBIOS] testing
Message-ID: <Pine.LNX.4.58.0503251420100.20558@enigma.lanl.gov>


ron



From jonsmirl at gmail.com  Sat Mar 26 20:36:22 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Sat, 26 Mar 2005 14:36:22 -0500
Subject: [LinuxBIOS] New version of ROM posting app
Message-ID: <9e4733910503261136395beac2@mail.gmail.com>

I put two new posting apps, a vm86 version and emu86 version out on:
bk://mesa3d.bkbits.net/rom

Get klibc from:
http://kernel.org/pub/linux/libs/klibc/

Install it somewhere and build it. You need to make a link to the
kernel source in the top level klibc directory. In this directory make
a link from the klibc-xxx directory to klibc.

Both projects will then build.
v86bios uses vm86 to run the rom
post uses emu86

Use an environment variable to pick the card to be acted on:
export DEVPATH=/bus/pci/devices/0000:01:00.0

vm86 is 20K non-debug
emu86 is 40K non-debug

Currently they don't use Ben's VGA arbiter which isn't ready yet. When
finished these app will automatically be triggered on driver load as
part of the hotplug process.

The source to vm86 is from the linux BIOS project where is has been
worked on to make it substantially smaller. I like to keep everyone on
the same source code base if possible.

Once we get these cleaned up and working I'm hoping to get them added
to the klibc project. Once in klibc, klibc is schedule to go into the
kernel sooner or later.

They are both partially working but fail part way through the posting
process. I've been playing with them a couple of days and I can't
figure out why they are failing. They are both failing for different
reasons. Can anyone help?

-- 
Jon Smirl
jonsmirl at gmail.com



From hansolofalcon at worldnet.att.net  Sun Mar 27 03:03:40 2005
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Sat, 26 Mar 2005 20:03:40 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <9e4733910503261136395beac2@mail.gmail.com>
Message-ID: <001601c53268$d4c07f20$6401a8c0@who5>

Hello from Gregg C Levine
While I appreciate the offer of the application, as I am eager to test
nearly everything new for the primary Linux BIOS project, I have one
or two questions.

Question One, Is this the same emu86, that is a project on BerliOS?
It's at http://emu86.berlios.de Also where is this vm86 available?

Question Two, I have bitkeeper installed, and it can reach itself,
that is the company's site. But how can I retrieve the code stored at
bk://mesa3d.bkbits.net/rom? I try feeding the string to bk command,
and I get an odd command back.

Has anyone on the list used bitkeeper before, other then yourself? I
am afraid I am more use to CVS, then BK.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi

> -----Original Message-----
> From: linuxbios-bounces at openbios.org
[mailto:linuxbios-bounces at openbios.org]
> On Behalf Of Jon Smirl
> Sent: Saturday, March 26, 2005 2:36 PM
> To: Jesse Barnes; Kendall Bennett; Benjamin Herrenschmidt;
> linuxbios at openbios.org
> Subject: [LinuxBIOS] New version of ROM posting app
> 
> I put two new posting apps, a vm86 version and emu86 version out on:
> bk://mesa3d.bkbits.net/rom
> 
> Get klibc from:
> http://kernel.org/pub/linux/libs/klibc/
> 
> Install it somewhere and build it. You need to make a link to the
> kernel source in the top level klibc directory. In this directory
make
> a link from the klibc-xxx directory to klibc.
> 
> Both projects will then build.
> v86bios uses vm86 to run the rom
> post uses emu86
> 
> Use an environment variable to pick the card to be acted on:
> export DEVPATH=/bus/pci/devices/0000:01:00.0
> 
> vm86 is 20K non-debug
> emu86 is 40K non-debug
> 
> Currently they don't use Ben's VGA arbiter which isn't ready yet.
When
> finished these app will automatically be triggered on driver load as
> part of the hotplug process.
> 
> The source to vm86 is from the linux BIOS project where is has been
> worked on to make it substantially smaller. I like to keep everyone
on
> the same source code base if possible.
> 
> Once we get these cleaned up and working I'm hoping to get them
added
> to the klibc project. Once in klibc, klibc is schedule to go into
the
> kernel sooner or later.
> 
> They are both partially working but fail part way through the
posting
> process. I've been playing with them a couple of days and I can't
> figure out why they are failing. They are both failing for different
> reasons. Can anyone help?
> 
> --
> Jon Smirl
> jonsmirl at gmail.com
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios




From jonsmirl at gmail.com  Sun Mar 27 03:16:18 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Sat, 26 Mar 2005 20:16:18 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <001601c53268$d4c07f20$6401a8c0@who5>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<001601c53268$d4c07f20$6401a8c0@who5>
Message-ID: <9e473391050326171619388d84@mail.gmail.com>

On Sat, 26 Mar 2005 20:03:40 -0500, Gregg C Levine
<hansolofalcon at worldnet.att.net> wrote:
> Hello from Gregg C Levine
> While I appreciate the offer of the application, as I am eager to test
> nearly everything new for the primary Linux BIOS project, I have one
> or two questions.
> 
> Question One, Is this the same emu86, that is a project on BerliOS?
> It's at http://emu86.berlios.de Also where is this vm86 available?

It is the emu86 that is contained in the linusbios project.
linuxbios/src/devices/emulator

There are about 100 variations on emu86 floating around.

> Question Two, I have bitkeeper installed, and it can reach itself,
> that is the company's site. But how can I retrieve the code stored at
> bk://mesa3d.bkbits.net/rom? I try feeding the string to bk command,
> and I get an odd command back.

 bk clone bk://mesa3d.bkbits.net/rom target_dir

> Has anyone on the list used bitkeeper before, other then yourself? I
> am afraid I am more use to CVS, then BK.

The Linux kernel is developed using bitkeeper.  Instead of copying
kernel images from kernel.org you can use this to keep up to date with
the latest changes.

bk clone  bk://linux.bkbits.net/linux-2.5 target_dir

After you have the initial tree down, to get updates
cd target_dir
bk pull

You can get bitkeeper here:
http://www.bitkeeper.com/Products.BK_Pro.Downloads.html
It is a free download.

-- 
Jon Smirl
jonsmirl at gmail.com



From ollie at lanl.gov  Sun Mar 27 08:15:08 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Sat, 26 Mar 2005 23:15:08 -0700
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <9e4733910503261136395beac2@mail.gmail.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
Message-ID: <1111904108.5983.5.camel@logarithm.lanl.gov>

On Sat, 2005-03-26 at 14:36 -0500, Jon Smirl wrote:
> Currently they don't use Ben's VGA arbiter which isn't ready yet. When
> finished these app will automatically be triggered on driver load as
> part of the hotplug process.
>
> The source to vm86 is from the linux BIOS project where is has been
> worked on to make it substantially smaller. I like to keep everyone on
> the same source code base if possible.
> 
> Once we get these cleaned up and working I'm hoping to get them added
> to the klibc project. Once in klibc, klibc is schedule to go into the
> kernel sooner or later.
> 
> They are both partially working but fail part way through the posting
> process. I've been playing with them a couple of days and I can't
> figure out why they are failing. They are both failing for different
> reasons. Can anyone help?
> 


Which version of x86emu are you using? The larger one from XF86 or the 
reduced version from Paulo?

I didn't follow the discussion on LKML about integrating the emulator,
what was the conclusion. Got O.K. from Linus?

-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From oxygene at studentenbude.ath.cx  Sun Mar 27 08:44:46 2005
From: oxygene at studentenbude.ath.cx (Patrick Mauritz)
Date: Sun, 27 Mar 2005 08:44:46 +0200
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <9e473391050326171619388d84@mail.gmail.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<001601c53268$d4c07f20$6401a8c0@who5>
	<9e473391050326171619388d84@mail.gmail.com>
Message-ID: <1111905886.763.5.camel@divert.streichelzoo>

Am Samstag, den 26.03.2005, 20:16 -0500 schrieb Jon Smirl:
> You can get bitkeeper here:
> http://www.bitkeeper.com/Products.BK_Pro.Downloads.html
> It is a free download.
free as in "you may download it, but never ever mess with us, compete
with us - while we define what our competition is, or even think about
complaining about problems (or mcvoy might send some nastygrams your way
- at least that part of the deal is not a legal issue)"

a client-only bk tool, which might just be enough under a different
license (BSD-L iirc, though they were talking/joking about a "no whining
license") was released about a week ago at
http://www.bitkeeper.com/press/2005-03-17.html


patrick mauritz





From jonsmirl at gmail.com  Sun Mar 27 09:15:04 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Sun, 27 Mar 2005 02:15:04 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1111904108.5983.5.camel@logarithm.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
Message-ID: <9e47339105032623152c5bc006@mail.gmail.com>

On Sat, 26 Mar 2005 23:15:08 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> On Sat, 2005-03-26 at 14:36 -0500, Jon Smirl wrote:
> > Currently they don't use Ben's VGA arbiter which isn't ready yet. When
> > finished these app will automatically be triggered on driver load as
> > part of the hotplug process.
> >
> > The source to vm86 is from the linux BIOS project where is has been
> > worked on to make it substantially smaller. I like to keep everyone on
> > the same source code base if possible.
> >
> > Once we get these cleaned up and working I'm hoping to get them added
> > to the klibc project. Once in klibc, klibc is schedule to go into the
> > kernel sooner or later.
> >
> > They are both partially working but fail part way through the posting
> > process. I've been playing with them a couple of days and I can't
> > figure out why they are failing. They are both failing for different
> > reasons. Can anyone help?
> >
> 
> Which version of x86emu are you using? The larger one from XF86 or the
> reduced version from Paulo?

The one from linux BIOS cvs:
linuxbios/src/devices/emulator/x86emu

> 
> I didn't follow the discussion on LKML about integrating the emulator,
> what was the conclusion. Got O.K. from Linus?

The emulator is going to run in user space. When the driver loads it
uses a hotplug event to trigger the posting app.

Linux is being changed currently to support early user space. Early
user space is active as soon as it is feasible. It runs things from
initramfs. The video driver and the reset program will be on the
initramfs. When the hardware is detected the driver will be loaded.
The driver will then trigger hotplug which will cause the reset. This
will occur as early in the boot process as possible. Much earlier than
current user space.

Klibc is the C library for initramfs. The plan is to integrate it into
the kernel tree even though it runs in user space. The reset app would
then go into that part of the tree.

Many other parts of the kernel are being moved to this model where
large piece of the driver run in user space. Another example is iSCSI
support.

Note that the reset program needs to run on a recent kernel. Check
/sys/bus/pci/devices/0000:01:00.0/rom and make sure it is there. If
not you need a more recent kernel.

> 
> --
> Li-Ta Lo <ollie at lanl.gov>
> Los Alamos National Lab
> 
> 


-- 
Jon Smirl
jonsmirl at gmail.com



From ebiederman at lnxi.com  Sun Mar 27 17:11:39 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: 27 Mar 2005 08:11:39 -0700
Subject: [LinuxBIOS] Happy Easter
Message-ID: <m37jjt3yz8.fsf@maxwell.lnxi.com>




From jonsmirl at gmail.com  Sun Mar 27 18:28:46 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Sun, 27 Mar 2005 11:28:46 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1111905886.763.5.camel@divert.streichelzoo>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<001601c53268$d4c07f20$6401a8c0@who5>
	<9e473391050326171619388d84@mail.gmail.com>
	<1111905886.763.5.camel@divert.streichelzoo>
Message-ID: <9e473391050327082821dbf68d@mail.gmail.com>

On Sun, 27 Mar 2005 08:44:46 +0200, Patrick Mauritz
<oxygene at studentenbude.ath.cx> wrote:
> Am Samstag, den 26.03.2005, 20:16 -0500 schrieb Jon Smirl:
> > You can get bitkeeper here:
> > http://www.bitkeeper.com/Products.BK_Pro.Downloads.html
> > It is a free download.
> free as in "you may download it, but never ever mess with us, compete
> with us - while we define what our competition is, or even think about
> complaining about problems (or mcvoy might send some nastygrams your way
> - at least that part of the deal is not a legal issue)"
> 
> a client-only bk tool, which might just be enough under a different
> license (BSD-L iirc, though they were talking/joking about a "no whining
> license") was released about a week ago at
> http://www.bitkeeper.com/press/2005-03-17.html

If bitkeeper is really a problem send me an email and I will send you
a tar ball.

-- 
Jon Smirl
jonsmirl at gmail.com



From hansolofalcon at worldnet.att.net  Sun Mar 27 19:58:44 2005
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Sun, 27 Mar 2005 12:58:44 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <9e473391050326171619388d84@mail.gmail.com>
Message-ID: <001201c532f6$a1802280$6401a8c0@who5>

Hello from Gregg C Levine
First off all, thank you for the BK advice. That was what I was
missing. I actually didn't think that the clone command applied to
everything that BK is used for, just for themselves. (Don't ask why!)

However, the next question is which version of the library are you
using? I chose the most recent, and before that: I chose version 0.198
as well, but it is failing with the included headers from the Linux
kernel, I'll post a copy of the script blurb here:
strip --strip-all -R .comment -R .note shared/ipconfig
ar cru libipconfig.a main.o netdev.o packet.o bootp_proto.o
dhcp_proto.o
make[1]: Leaving directory `/usr/src/klibc-0.198/ipconfig'
make[1]: Entering directory `/usr/src/klibc-0.198/nfsmount'
gcc -Wp,-MD,./.main.o.d -mregparm=3 -DREGPARM=3 -march=i386 -Os -g
-falign-functions=0 -falign-jumps=0 -falign-loops=0  -nostdinc
-iwithprefix include -D__KLIBC__ -DBITSIZE=32 -I../include/arch/i386
-I../include/bits32 -I../include -I../linux/include
-I../linux/include2 -I../linux/include -Wstrict-prototypes -Wall -I.
-c -o main.o main.c
In file included from main.c:16:
../linux/include/linux/nfs_mount.h:26: error: field `old_root' has
incomplete type
../linux/include/linux/nfs_mount.h:40: error: field `root' has
incomplete type
make[1]: *** [main.o] Error 1
make[1]: Leaving directory `/usr/src/klibc-0.198/nfsmount'
make: *** [all] Error 2

Ironically the release before that one, 0.190 gets through everything,
but crashes to a halt inside the ash directory. And 0.181 builds the
library, but complains about some trivial data, or a trivial error.

Whereas the currently stable release 1.0 gets all of the way through
building stuff until it reaches this point:
cp -f shared/ipconfig shared.g
strip --strip-all -R .comment -R .note shared/ipconfig
ar cru libipconfig.a main.o netdev.o packet.o bootp_proto.o
dhcp_proto.o
make[1]: Leaving directory `/usr/src/klibc-1.0/ipconfig'
make[1]: Entering directory `/usr/src/klibc-1.0/nfsmount'
gcc -Wp,-MD,./.main.o.d -march=i386 -Os -g -fomit-frame-pointer
-falign-functions=0 -falign-jumps=0 -falign-loops=0 -m32 -nostdinc
-iwithprefix include -D__KLIBC__ -I../include/arch/i386
-I../include/bits32 -I../include -I../linux/include
-I../linux/include2 -I../linux/include -mregparm=3 -D_REGPARM=3
-Wstrict-prototypes -Wall -I. -c -o main.o main.c
In file included from main.c:16:
../linux/include/linux/nfs_mount.h:26: error: field `old_root' has
incomplete type
../linux/include/linux/nfs_mount.h:40: error: field `root' has
incomplete type
make[1]: *** [main.o] Error 1
make[1]: Leaving directory `/usr/src/klibc-1.0/nfsmount'
make: *** [all] Error 2

-----
All of this is being built using the tools with Slackware-10.1, binary
utilities are at 2..19 and the gcc release version 3.3.4. Also the
kernel is at 2.4.29.

If you would like to know why I chose the Slackware distribution, it's
because I have found that one to be relatively easy to use for setting
up new systems, including work stations, and servers. 

What is strange is why the two versions have the exactly the same
errors. Do you think I should send those two complaints to the list
which covers the activities of the library?
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi

> -----Original Message-----
> From: Jon Smirl [mailto:jonsmirl at gmail.com]
> Sent: Saturday, March 26, 2005 8:16 PM
> To: Gregg C Levine
> Cc: linuxbios at openbios.org
> Subject: Re: [LinuxBIOS] New version of ROM posting app
> 
> On Sat, 26 Mar 2005 20:03:40 -0500, Gregg C Levine
> <hansolofalcon at worldnet.att.net> wrote:
> > Hello from Gregg C Levine
> > While I appreciate the offer of the application, as I am eager to
test
> > nearly everything new for the primary Linux BIOS project, I have
one
> > or two questions.
> >
> > Question One, Is this the same emu86, that is a project on
BerliOS?
> > It's at http://emu86.berlios.de Also where is this vm86 available?
> 
> It is the emu86 that is contained in the linusbios project.
> linuxbios/src/devices/emulator
> 
> There are about 100 variations on emu86 floating around.
> 
> > Question Two, I have bitkeeper installed, and it can reach itself,
> > that is the company's site. But how can I retrieve the code stored
at
> > bk://mesa3d.bkbits.net/rom? I try feeding the string to bk
command,
> > and I get an odd command back.
> 
>  bk clone bk://mesa3d.bkbits.net/rom target_dir
> 
> > Has anyone on the list used bitkeeper before, other then yourself?
I
> > am afraid I am more use to CVS, then BK.
> 
> The Linux kernel is developed using bitkeeper.  Instead of copying
> kernel images from kernel.org you can use this to keep up to date
with
> the latest changes.
> 
> bk clone  bk://linux.bkbits.net/linux-2.5 target_dir
> 
> After you have the initial tree down, to get updates
> cd target_dir
> bk pull
> 
> You can get bitkeeper here:
> http://www.bitkeeper.com/Products.BK_Pro.Downloads.html
> It is a free download.
> 
> --
> Jon Smirl
> jonsmirl at gmail.com




From jonsmirl at gmail.com  Sun Mar 27 20:24:58 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Sun, 27 Mar 2005 13:24:58 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <001201c532f6$a1802280$6401a8c0@who5>
References: <9e473391050326171619388d84@mail.gmail.com>
	<001201c532f6$a1802280$6401a8c0@who5>
Message-ID: <9e47339105032710241ba9aef9@mail.gmail.com>

On Sun, 27 Mar 2005 12:58:44 -0500, Gregg C Levine > All of this is
being built using the tools with Slackware-10.1, binary
> utilities are at 2..19 and the gcc release version 3.3.4. Also the
> kernel is at 2.4.29.

klibc and the rom reset program are both targeted at the 2.6 kernel.
The rom program requires a recent 2.6 kernel to work.

I'm not sure if klib supports the 2.4 kernel. klib is very closely
tied to the kernel source.

2.4 is in maintenance mode. All new development is being done on 2.6.

I don't use slackware but one most distributions you can do:
bk clone bk://linux.bkbits.net/linux-2.5 target_dir
set up your config
make
make installl

Then when you boot you can choose what kernel to use.

-- 
Jon Smirl
jonsmirl at gmail.com



From jonsmirl at gmail.com  Sun Mar 27 21:13:29 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Sun, 27 Mar 2005 14:13:29 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <001201c532f6$a1802280$6401a8c0@who5>
References: <9e473391050326171619388d84@mail.gmail.com>
	<001201c532f6$a1802280$6401a8c0@who5>
Message-ID: <9e473391050327111352500c34@mail.gmail.com>

Also, I know the reset program doesn't work. I need some help figuring
out why it doesn't work.  It is failing on all the video cards I have.

After about the fifth INT 1A it exits and doesn't complete the reset.

-- 
Jon Smirl
jonsmirl at gmail.com



From jonsmirl at gmail.com  Sun Mar 27 21:16:18 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Sun, 27 Mar 2005 14:16:18 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <001201c532f6$a1802280$6401a8c0@who5>
References: <9e473391050326171619388d84@mail.gmail.com>
	<001201c532f6$a1802280$6401a8c0@who5>
Message-ID: <9e47339105032711166fba7fb2@mail.gmail.com>

Also, I know the reset program doesn't work. I need some help figuring
out why it doesn't work.  It is failing on all the video cards I have.

After about the fifth INT 1A it exits and doesn't complete the reset.

There are three primary applications for the program:
1) using an x86 board in a non-x86 machine
2) display wall systems where the host machine may have 16 video boards in it.
3) Multihead X using multiple cards

-- 
Jon Smirl
jonsmirl at gmail.com



From jonsmirl at gmail.com  Mon Mar 28 04:00:06 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Sun, 27 Mar 2005 21:00:06 -0500
Subject: [LinuxBIOS] Re: New version of ROM posting app
In-Reply-To: <9e4733910503261136395beac2@mail.gmail.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
Message-ID: <9e473391050327180052a647f6@mail.gmail.com>

On Sat, 26 Mar 2005 14:36:22 -0500, Jon Smirl <jonsmirl at gmail.com> wrote:
> I put two new posting apps, a vm86 version and emu86 version out on:
> bk://mesa3d.bkbits.net/rom

Still doesn't work but I am making progress. I had forgotten that my
user space program needs to route VGA until the kernel support is
there. I've added VGA routing support temporarily.

-- 
Jon Smirl
jonsmirl at gmail.com



From ollie at lanl.gov  Mon Mar 28 20:05:08 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Mon, 28 Mar 2005 11:05:08 -0700
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <9e47339105032623152c5bc006@mail.gmail.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
Message-ID: <1112033108.3612.9.camel@exponential.lanl.gov>

On Sun, 2005-03-27 at 02:15 -0500, Jon Smirl wrote:
> On Sat, 26 Mar 2005 23:15:08 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> > On Sat, 2005-03-26 at 14:36 -0500, Jon Smirl wrote:
> > > Currently they don't use Ben's VGA arbiter which isn't ready yet. When
> > > finished these app will automatically be triggered on driver load as
> > > part of the hotplug process.
> > >
> > > The source to vm86 is from the linux BIOS project where is has been
> > > worked on to make it substantially smaller. I like to keep everyone on
> > > the same source code base if possible.
> > >
> > > Once we get these cleaned up and working I'm hoping to get them added
> > > to the klibc project. Once in klibc, klibc is schedule to go into the
> > > kernel sooner or later.
> > >
> > > They are both partially working but fail part way through the posting
> > > process. I've been playing with them a couple of days and I can't
> > > figure out why they are failing. They are both failing for different
> > > reasons. Can anyone help?
> > >
> > 
> > Which version of x86emu are you using? The larger one from XF86 or the
> > reduced version from Paulo?
> 
> The one from linux BIOS cvs:
> linuxbios/src/devices/emulator/x86emu
> 

Actually, the code on the LinuxBIOS cvs may be the reduced version by 
Paulo, depending on when you check it out. Paulo's version has some
bug such that it may fail to init the hardware. I did commited some
fix to the CVS I got from him. But there are some fixed not commited
dur to the CVS -> TLA transition.

> > 
> > I didn't follow the discussion on LKML about integrating the emulator,
> > what was the conclusion. Got O.K. from Linus?
> 
> The emulator is going to run in user space. When the driver loads it
> uses a hotplug event to trigger the posting app.
> 
> Linux is being changed currently to support early user space. Early
> user space is active as soon as it is feasible. It runs things from
> initramfs. The video driver and the reset program will be on the
> initramfs. When the hardware is detected the driver will be loaded.
> The driver will then trigger hotplug which will cause the reset. This
> will occur as early in the boot process as possible. Much earlier than
> current user space.
> 
> Klibc is the C library for initramfs. The plan is to integrate it into
> the kernel tree even though it runs in user space. The reset app would
> then go into that part of the tree.
> 
> Many other parts of the kernel are being moved to this model where
> large piece of the driver run in user space. Another example is iSCSI
> support.
> 
> Note that the reset program needs to run on a recent kernel. Check
> /sys/bus/pci/devices/0000:01:00.0/rom and make sure it is there. If
> not you need a more recent kernel.
> 

How recent should that be? 2.6.11?

Did you try to link the emulator with GLIBC than klibc? Do they have the
same behavior?

Ollie
 




From jonsmirl at gmail.com  Mon Mar 28 20:11:05 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Mon, 28 Mar 2005 13:11:05 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1112033108.3612.9.camel@exponential.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
Message-ID: <9e4733910503281011c2773bd@mail.gmail.com>

On Mon, 28 Mar 2005 11:05:08 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> > > Which version of x86emu are you using? The larger one from XF86 or the
> > > reduced version from Paulo?
> >
> > The one from linux BIOS cvs:
> > linuxbios/src/devices/emulator/x86emu
> >
> 
> Actually, the code on the LinuxBIOS cvs may be the reduced version by
> Paulo, depending on when you check it out. Paulo's version has some
> bug such that it may fail to init the hardware. I did commited some
> fix to the CVS I got from him. But there are some fixed not commited
> dur to the CVS -> TLA transition.

What I used is in the current CVS repository:
:pserver:anonymous at cvs.sourceforge.net:/cvsroot/freebios

> >
> > Note that the reset program needs to run on a recent kernel. Check
> > /sys/bus/pci/devices/0000:01:00.0/rom and make sure it is there. If
> > not you need a more recent kernel.
> >
> 
> How recent should that be? 2.6.11?

2.6.11 is fine. I think it went in around 2.6.9.

> Did you try to link the emulator with GLIBC than klibc? Do they have the
> same behavior?

I haven't tried the emulator with glibc vs klibc. But I have tried
several other programs against both without problem. Problems with
klibc are usually in the form of not being able to compile against it.
Actual bugs in the code are pretty rare now.

> 
> Ollie
> 
> 


-- 
Jon Smirl
jonsmirl at gmail.com



From pmarques at grupopie.com  Mon Mar 28 20:44:55 2005
From: pmarques at grupopie.com (Paulo Marques)
Date: Mon, 28 Mar 2005 19:44:55 +0100
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <9e4733910503281011c2773bd@mail.gmail.com>
References: <9e4733910503261136395beac2@mail.gmail.com>	
	<1111904108.5983.5.camel@logarithm.lanl.gov>	
	<9e47339105032623152c5bc006@mail.gmail.com>	
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
Message-ID: <424850A7.8030506@grupopie.com>

Jon Smirl wrote:
> On Mon, 28 Mar 2005 11:05:08 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> 
>>>>Which version of x86emu are you using? The larger one from XF86 or the
>>>>reduced version from Paulo?
>>>
>>>The one from linux BIOS cvs:
>>>linuxbios/src/devices/emulator/x86emu
>>>
>>
>>Actually, the code on the LinuxBIOS cvs may be the reduced version by
>>Paulo, depending on when you check it out. Paulo's version has some
>>bug such that it may fail to init the hardware. I did commited some
>>fix to the CVS I got from him. But there are some fixed not commited
>>dur to the CVS -> TLA transition.
> 
> 
> What I used is in the current CVS repository:
> :pserver:anonymous at cvs.sourceforge.net:/cvsroot/freebios

I just went there to check out the versions.

The version in "freebios" is the large version whereas the version in 
"freebios2" is the reduced version.

The large version still has the "#define xorl(a,b)   ((a) && !(b)) || 
(!(a) && (b))" bug in line 100 in ops2.c. This macro needs an extra 
parenthesis to avoid priority issues.

The reduced version, on top of this bug, still has the XCHG AX,BX bug. 
To fix it manually, edit line 2230 in ops.c and change:

         M.x86.R_EAX = *reg16;

to

         M.x86.R_AX = *reg16;

This bug cleared the top 16 bits of EAX when doing a XCHG AX,BX 
instruction. In the BIOS Ollie tested with, this produced a division by 
zero later in the code.

It also has the "write destination on CMP" bug.

I can send a proper patch against this version to fix all this, but if 
the version in the arch repository is already updated, then there is no 
need for it.

-- 
Paulo Marques
Software Development Department - Grupo PIE, S.A.
Phone: +351 252 290600, Fax: +351 252 290601
Web: www.grupopie.com

All that is necessary for the triumph of evil is that good men do nothing.
Edmund Burke (1729 - 1797)



From jonsmirl at gmail.com  Mon Mar 28 23:49:58 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Mon, 28 Mar 2005 16:49:58 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1112033108.3612.9.camel@exponential.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
Message-ID: <9e473391050328134920cc6886@mail.gmail.com>

On Mon, 28 Mar 2005 11:05:08 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:

I get the same result from all three test versions you sent.

running file ../bios.fil
No size specified. defaulting to 32k
No base specified. defaulting to 0xc0000
No initial code segment specified. defaulting to 0xc000
No initial instruction pointer specified. defaulting to 0x0003
updating int vector 0x1a
updating int vector 0x1a
updating int vector 0x1a
int1a vector at 0
eax=0x9 ecx=0xde01 eflags=0x44
updating int vector 0x0
c000:00a3: 63 ILLEGAL X86 OPCODE!
halt_sys: file ops.c, line 93
halted

Here is a trace from an old vm86 program that works:
Maybe INT15 isn't hooked up in yours?

PCI says configuration type 1
PCI probing configuration type 1

Probing for devices on PCI bus 0:
bus: 0 card: 0 func 0 reg0: 0x25788086 bc 0x6, sub 0x0, if 0x0, hdr 0x0
bus: 0 card: 1 func 0 reg0: 0x25798086 bc 0x6, sub 0x4, if 0x0, hdr 0x1
Pci-Pci Bridge found; primary: 0x0 secondary: 0x1
bus: 0 card: 29 func 0 reg0: 0x24d28086 bc 0xc, sub 0x3, if 0x0, hdr 0x80
bus: 0 card: 29 func 1 reg0: 0x24d48086 bc 0xc, sub 0x3, if 0x0, hdr 0x0
bus: 0 card: 29 func 2 reg0: 0x24d78086 bc 0xc, sub 0x3, if 0x0, hdr 0x0
bus: 0 card: 29 func 3 reg0: 0x24de8086 bc 0xc, sub 0x3, if 0x0, hdr 0x0
bus: 0 card: 30 func 0 reg0: 0x244e8086 bc 0x6, sub 0x4, if 0x0, hdr 0x1
Pci-Pci Bridge found; primary: 0x0 secondary: 0x2
bus: 0 card: 31 func 0 reg0: 0x24d08086 bc 0x6, sub 0x1, if 0x0, hdr 0x80
bus: 0 card: 31 func 1 reg0: 0x24db8086 bc 0x1, sub 0x1, if 0x8a, hdr 0x0
bus: 0 card: 31 func 2 reg0: 0x24d18086 bc 0x1, sub 0x1, if 0x8f, hdr 0x0
bus: 0 card: 31 func 3 reg0: 0x24d38086 bc 0xc, sub 0x5, if 0x0, hdr 0x0

Probing for devices on PCI bus 1:
bus: 1 card: 0 func 0 reg0: 0x49661002 bc 0x3, sub 0x0, if 0x0, hdr 0x80
Display found
bus: 1 card: 0 func 1 reg0: 0x496e1002 bc 0x3, sub 0x80, if 0x0, hdr 0x0
Display found

Probing for devices on PCI bus 2:
bus: 2 card: 0 func 0 reg0: 0x165314e4 bc 0x2, sub 0x0, if 0x0, hdr 0x0
bus: 2 card: 2 func 0 reg0: 0x8019104c bc 0xc, sub 0x0, if 0x10, hdr 0x0
bus: 2 card: 3 func 0 reg0: 0x50441002 bc 0x3, sub 0x0, if 0x0, hdr 0x0
Display found
bus: 2 card: 12 func 0 reg0: 0x100e8086 bc 0x2, sub 0x0, if 0x0, hdr 0x0
Max buses in system: 3
Min PCI mem address: 0x20020200
writing: 0x80000 to 0x8000083c
writing: 0x2b00083 to 0x80010004
writing: 0xfea00001 to 0x80010030
ax: 0x100
RomBase: 0xfea00000
writing: 0xfea00001 to 0x80010030
data segment in BIOS: 0x164, type: 0x0 BIOS length: 0xd000
writing: 0xfea00000 to 0x80010030
int 0x1a received: ax:0xb109
int 0x1a: ax=0xb109 bx=0x100 cx=0x0 dx=0x0 di=0x14
Slot=0x80010000
reading: 0xde01 from 0x80010014
ax=0x9 cx=0xde01 flags=0xb0246
int 0x15 received: ax:0x4e08
int 0x42 received: ax:0x7
int 0x42: ax:0x7 bx:0x200 cx:0x0 dx:0x3c2
int 0x6d received: ax:0x3
calling card BIOS at: 0xc000:1ea0
int 0x6d received: ax:0x3
calling card BIOS at: 0xc000:1ea0
int 0x6d received: ax:0x1301
calling card BIOS at: 0xc000:1ea0
int 0x1a received: ax:0xb102
int 0x1a: ax=0xb102 bx=0x7 cx=0x691 dx=0x1106 di=0x6b60
ax=0x8602 bx=0x7 flags=0x30047
int 0x1a received: ax:0xb102
int 0x1a: ax=0xb102 bx=0x7 cx=0x305 dx=0x1106 di=0x6b60
ax=0x8602 bx=0x7 flags=0x30247
int 0x1a received: ax:0xb109
int 0x1a: ax=0xb109 bx=0x0 cx=0x0 dx=0x0 di=0x0
Slot=0x80010000
ax=0x8709 cx=0x0 flags=0x30247
writing: 0x80000 to 0x8000083c
writing: 0x2b00087 to 0x80010104
writing: 0x1 to 0x80010130
ax: 0x101
writing: 0xffffffff to 0x80010130
reading: 0x0 from 0x80010130
bios size: 0x0
writing: 0x0 to 0x80010130
biosSize: 0x0
reading: 0xf4000008 from 0x80010010
writing: 0xffffffff to 0x80010010
reading: 0xfc000008 from 0x80010010
writing: 0xf4000008 to 0x80010010
size: 0x4000000
RomBase: 0xf4000000
writing: 0xf4000001 to 0x80010130
writing: 0x0 to 0x80010130
int 0x42 received: ax:0x7
int 0x42: ax:0x7 bx:0x7be cx:0x900 dx:0x3c2
int 0x6d received: ax:0x3
calling card BIOS at: 0xc000:13a6
int 0x6d received: ax:0x1301
calling card BIOS at: 0xc000:13a6
writing: 0xa0000 to 0x8000f03c
writing: 0x2900083 to 0x80021804
writing: 0xfe800001 to 0x80021830
ax: 0x218
RomBase: 0xfe800000
writing: 0xfe800001 to 0x80021830
data segment in BIOS: 0x16c, type: 0x0 BIOS length: 0xc000
writing: 0xfe800000 to 0x80021830
int 0x1a received: ax:0xb109
int 0x1a: ax=0xb109 bx=0x218 cx=0x0 dx=0x0 di=0x14
Slot=0x80021800
reading: 0xce01 from 0x80021814
ax=0x9 cx=0xce01 flags=0xb0246
int 0x42 received: ax:0x7
int 0x42: ax:0x7 bx:0x990 cx:0x200 dx:0x3c2
int 0x6d received: ax:0x3
calling card BIOS at: 0xc000:13a6
int 0x10 received: ax:0x4f02
int 0x10: ax:0x4f02 bx:0x100 cx:0x205 dx:0xce12
calling card BIOS at: 0xc000:13a6
int 0x10 received: ax:0x3
int 0x10: ax:0x3 bx:0x8d18 cx:0x3c00000 dx:0xce59
calling card BIOS at: 0xc000:13a6
int 0x6d received: ax:0x1301
calling card BIOS at: 0xc000:13a6
writing: 0xa0000 to 0x8000f03c
writing: 0x0 to 0x8000083c
writing: 0x2b00080 to 0x80010004
writing: 0xfea00000 to 0x80010030
writing: 0x2b00087 to 0x80010104
writing: 0x0 to 0x80010130
writing: 0x2900083 to 0x80021804
writing: 0xfe800000 to 0x80021830

-- 
Jon Smirl
jonsmirl at gmail.com



From jonsmirl at gmail.com  Tue Mar 29 00:04:09 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Mon, 28 Mar 2005 17:04:09 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1112033108.3612.9.camel@exponential.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
Message-ID: <9e47339105032814046f46a09@mail.gmail.com>

On Mon, 28 Mar 2005 11:05:08 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:

I get the same result from all three test versions you sent.

running file ../bios.fil
No size specified. defaulting to 32k
No base specified. defaulting to 0xc0000
No initial code segment specified. defaulting to 0xc000
No initial instruction pointer specified. defaulting to 0x0003
updating int vector 0x1a
updating int vector 0x1a
updating int vector 0x1a
int1a vector at 0
eax=0x9 ecx=0xde01 eflags=0x44
updating int vector 0x0
c000:00a3: 63 ILLEGAL X86 OPCODE!
halt_sys: file ops.c, line 93
halted

Here is a trace from an old vm86 program that works:
Maybe INT15 isn't hooked up in yours?

PCI says configuration type 1
PCI probing configuration type 1

Probing for devices on PCI bus 0:
bus: 0 card: 0 func 0 reg0: 0x25788086 bc 0x6, sub 0x0, if 0x0, hdr 0x0
bus: 0 card: 1 func 0 reg0: 0x25798086 bc 0x6, sub 0x4, if 0x0, hdr 0x1
Pci-Pci Bridge found; primary: 0x0 secondary: 0x1
bus: 0 card: 29 func 0 reg0: 0x24d28086 bc 0xc, sub 0x3, if 0x0, hdr 0x80
bus: 0 card: 29 func 1 reg0: 0x24d48086 bc 0xc, sub 0x3, if 0x0, hdr 0x0
bus: 0 card: 29 func 2 reg0: 0x24d78086 bc 0xc, sub 0x3, if 0x0, hdr 0x0
bus: 0 card: 29 func 3 reg0: 0x24de8086 bc 0xc, sub 0x3, if 0x0, hdr 0x0
bus: 0 card: 30 func 0 reg0: 0x244e8086 bc 0x6, sub 0x4, if 0x0, hdr 0x1
Pci-Pci Bridge found; primary: 0x0 secondary: 0x2
bus: 0 card: 31 func 0 reg0: 0x24d08086 bc 0x6, sub 0x1, if 0x0, hdr 0x80
bus: 0 card: 31 func 1 reg0: 0x24db8086 bc 0x1, sub 0x1, if 0x8a, hdr 0x0
bus: 0 card: 31 func 2 reg0: 0x24d18086 bc 0x1, sub 0x1, if 0x8f, hdr 0x0
bus: 0 card: 31 func 3 reg0: 0x24d38086 bc 0xc, sub 0x5, if 0x0, hdr 0x0

Probing for devices on PCI bus 1:
bus: 1 card: 0 func 0 reg0: 0x49661002 bc 0x3, sub 0x0, if 0x0, hdr 0x80
Display found
bus: 1 card: 0 func 1 reg0: 0x496e1002 bc 0x3, sub 0x80, if 0x0, hdr 0x0
Display found

Probing for devices on PCI bus 2:
bus: 2 card: 0 func 0 reg0: 0x165314e4 bc 0x2, sub 0x0, if 0x0, hdr 0x0
bus: 2 card: 2 func 0 reg0: 0x8019104c bc 0xc, sub 0x0, if 0x10, hdr 0x0
bus: 2 card: 3 func 0 reg0: 0x50441002 bc 0x3, sub 0x0, if 0x0, hdr 0x0
Display found
bus: 2 card: 12 func 0 reg0: 0x100e8086 bc 0x2, sub 0x0, if 0x0, hdr 0x0
Max buses in system: 3
Min PCI mem address: 0x20020200
writing: 0x80000 to 0x8000083c
writing: 0x2b00083 to 0x80010004
writing: 0xfea00001 to 0x80010030
ax: 0x100
RomBase: 0xfea00000
writing: 0xfea00001 to 0x80010030
data segment in BIOS: 0x164, type: 0x0 BIOS length: 0xd000
writing: 0xfea00000 to 0x80010030
int 0x1a received: ax:0xb109
int 0x1a: ax=0xb109 bx=0x100 cx=0x0 dx=0x0 di=0x14
Slot=0x80010000
reading: 0xde01 from 0x80010014
ax=0x9 cx=0xde01 flags=0xb0246
int 0x15 received: ax:0x4e08
int 0x42 received: ax:0x7
int 0x42: ax:0x7 bx:0x200 cx:0x0 dx:0x3c2
int 0x6d received: ax:0x3
calling card BIOS at: 0xc000:1ea0
int 0x6d received: ax:0x3
calling card BIOS at: 0xc000:1ea0
int 0x6d received: ax:0x1301
calling card BIOS at: 0xc000:1ea0
int 0x1a received: ax:0xb102
int 0x1a: ax=0xb102 bx=0x7 cx=0x691 dx=0x1106 di=0x6b60
ax=0x8602 bx=0x7 flags=0x30047
int 0x1a received: ax:0xb102
int 0x1a: ax=0xb102 bx=0x7 cx=0x305 dx=0x1106 di=0x6b60
ax=0x8602 bx=0x7 flags=0x30247
int 0x1a received: ax:0xb109
int 0x1a: ax=0xb109 bx=0x0 cx=0x0 dx=0x0 di=0x0
Slot=0x80010000
ax=0x8709 cx=0x0 flags=0x30247
writing: 0x80000 to 0x8000083c
writing: 0x2b00087 to 0x80010104
writing: 0x1 to 0x80010130
ax: 0x101
writing: 0xffffffff to 0x80010130
reading: 0x0 from 0x80010130
bios size: 0x0
writing: 0x0 to 0x80010130
biosSize: 0x0
reading: 0xf4000008 from 0x80010010
writing: 0xffffffff to 0x80010010
reading: 0xfc000008 from 0x80010010
writing: 0xf4000008 to 0x80010010
size: 0x4000000
RomBase: 0xf4000000
writing: 0xf4000001 to 0x80010130
writing: 0x0 to 0x80010130
int 0x42 received: ax:0x7
int 0x42: ax:0x7 bx:0x7be cx:0x900 dx:0x3c2
int 0x6d received: ax:0x3
calling card BIOS at: 0xc000:13a6
int 0x6d received: ax:0x1301
calling card BIOS at: 0xc000:13a6
writing: 0xa0000 to 0x8000f03c
writing: 0x2900083 to 0x80021804
writing: 0xfe800001 to 0x80021830
ax: 0x218
RomBase: 0xfe800000
writing: 0xfe800001 to 0x80021830
data segment in BIOS: 0x16c, type: 0x0 BIOS length: 0xc000
writing: 0xfe800000 to 0x80021830
int 0x1a received: ax:0xb109
int 0x1a: ax=0xb109 bx=0x218 cx=0x0 dx=0x0 di=0x14
Slot=0x80021800
reading: 0xce01 from 0x80021814
ax=0x9 cx=0xce01 flags=0xb0246
int 0x42 received: ax:0x7
int 0x42: ax:0x7 bx:0x990 cx:0x200 dx:0x3c2
int 0x6d received: ax:0x3
calling card BIOS at: 0xc000:13a6
int 0x10 received: ax:0x4f02
int 0x10: ax:0x4f02 bx:0x100 cx:0x205 dx:0xce12
calling card BIOS at: 0xc000:13a6
int 0x10 received: ax:0x3
int 0x10: ax:0x3 bx:0x8d18 cx:0x3c00000 dx:0xce59
calling card BIOS at: 0xc000:13a6
int 0x6d received: ax:0x1301
calling card BIOS at: 0xc000:13a6
writing: 0xa0000 to 0x8000f03c
writing: 0x0 to 0x8000083c
writing: 0x2b00080 to 0x80010004
writing: 0xfea00000 to 0x80010030
writing: 0x2b00087 to 0x80010104
writing: 0x0 to 0x80010130
writing: 0x2900083 to 0x80021804
writing: 0xfe800000 to 0x80021830

-- 
Jon Smirl
jonsmirl at gmail.com



From ollie at lanl.gov  Tue Mar 29 00:28:20 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Mon, 28 Mar 2005 15:28:20 -0700
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <424850A7.8030506@grupopie.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
Message-ID: <1112048900.7035.3.camel@exponential.lanl.gov>

On Mon, 2005-03-28 at 19:44 +0100, Paulo Marques wrote:
> Jon Smirl wrote:
> > On Mon, 28 Mar 2005 11:05:08 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> > 
> >>>>Which version of x86emu are you using? The larger one from XF86 or the
> >>>>reduced version from Paulo?
> >>>
> >>>The one from linux BIOS cvs:
> >>>linuxbios/src/devices/emulator/x86emu
> >>>
> >>
> >>Actually, the code on the LinuxBIOS cvs may be the reduced version by
> >>Paulo, depending on when you check it out. Paulo's version has some
> >>bug such that it may fail to init the hardware. I did commited some
> >>fix to the CVS I got from him. But there are some fixed not commited
> >>dur to the CVS -> TLA transition.
> > 
> > 
> > What I used is in the current CVS repository:
> > :pserver:anonymous at cvs.sourceforge.net:/cvsroot/freebios
> 
> I just went there to check out the versions.
> 

Can you go to 

http://www.openbios.org/cgi-bin/viewarch.cgi

to check the version in the TLA ?

-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From jonsmirl at gmail.com  Tue Mar 29 00:57:27 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Mon, 28 Mar 2005 17:57:27 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1112048900.7035.3.camel@exponential.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
Message-ID: <9e47339105032814577e5c2800@mail.gmail.com>

On Mon, 28 Mar 2005 15:28:20 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> Can you go to
> 
> http://www.openbios.org/cgi-bin/viewarch.cgi
> 
> to check the version in the TLA ?
> 

Different output but same failure. This looks like a problem with the
BIOS emulation not with the emu86.

-- 
Jon Smirl
jonsmirl at gmail.com

running file ../bios.fil
No size specified. defaulting to 32k
No base specified. defaulting to 0xc0000
No initial code segment specified. defaulting to 0xc000
No initial instruction pointer specified. defaulting to 0x0003
updating int vector 0x1a
updating int vector 0x1a
updating int vector 0x1a
int1a vector at 0
eax=0x9 ecx=0xde01 eflags=0x44
outw(0xc000, 0xde14)
outw(0x0100, 0xde16)
outl(0x80010000, 0x0cf8)
inl(0x0cfc) = 0x49661002
outl(0x80010014, 0x0cf8)
inl(0x0cfc) = 0x0000de01
outl(0x5133a3b0, 0xde30)
inl(0xde30) = 0x5133a3b0
outl(0x5133a3b0, 0xde30)
outl(0x000000ec, 0xde00)
outl(0x00004443, 0xde04)
outl(0x0000023c, 0xde00)
outl(0x00000000, 0xde04)
outl(0x00000420, 0xde00)
outl(0x807f0000, 0xde04)
outl(0x04000200, 0xde50)
inl(0xde50) = 0x04000200
outl(0x04000200, 0xde50)
outl(0xff604102, 0xde58)
inl(0xde58) = 0xff604102
outl(0xff604102, 0xde58)
outl(0x00000168, 0xde00)
inl(0xde04) = 0x6006b516
outl(0x6006b516, 0xde04)
outl(0x00000020, 0xde00)
outl(0x00000000, 0xde04)
outl(0x00000024, 0xde00)
outl(0x00000000, 0xde04)
outl(0x00000188, 0xde00)
inl(0xde04) = 0x0001c000
outl(0x0001c000, 0xde04)
outl(0x00000d00, 0xde00)
inl(0xde04) = 0x5b300600
outl(0x5b300600, 0xde04)
outl(0x00000d04, 0xde00)
inl(0xde04) = 0x00000806
outl(0x00000806, 0xde04)
outl(0x00000284, 0xde00)
outl(0x08000008, 0xde04)
outl(0x00000174, 0xde00)
outl(0x001e0000, 0xde04)
outl(0x00000130, 0xde00)
outl(0x70000000, 0xde04)
outl(0x00000178, 0xde00)
outl(0x0f0fc221, 0xde04)
outl(0x0000017c, 0xde00)
outl(0x0aa40aa4, 0xde04)
outl(0x000001f8, 0xde00)
outl(0x0000010a, 0xde04)
outl(0x000001fc, 0xde00)
outl(0x00f460d6, 0xde04)
outl(0x000001f8, 0xde00)
outl(0x0000010b, 0xde04)
outl(0x000001fc, 0xde00)
outl(0xf52fd005, 0xde04)
outl(0x000001f8, 0xde00)
outl(0x0000010d, 0xde04)
outl(0x000001fc, 0xde00)
outl(0xf52fd005, 0xde04)
outl(0x000001f8, 0xde00)
outl(0x0000010f, 0xde04)
outl(0x000001fc, 0xde00)
outl(0x00009249, 0xde04)
outl(0x000001f8, 0xde00)
outl(0x0000010c, 0xde04)
outl(0x000001fc, 0xde00)
outl(0x161555ff, 0xde04)
outl(0x000001f8, 0xde00)
outl(0x0000010e, 0xde04)
outl(0x000001fc, 0xde00)
outl(0x161555ff, 0xde04)
outl(0x00000188, 0xde00)
outl(0x00000000, 0xde04)
outl(0x000001f8, 0xde00)
outl(0x00000000, 0xde04)
outl(0x00000d00, 0xde00)
inl(0xde04) = 0x5b300600
outl(0x5b300600, 0xde04)
outb(0x00, 0xde08)
outb(0x05, 0x03c2)
inb(0x03da) = 0x01
inb(0x03ba) = 0xff
outb(0x00, 0x03c0)
outw(0x2001, 0x03c4)
updating int vector 0x0
c000:00a3: 63 ILLEGAL X86 OPCODE!
halt_sys: file ops.c, line 93
halted



From ollie at lanl.gov  Tue Mar 29 01:14:54 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Mon, 28 Mar 2005 16:14:54 -0700
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <9e47339105032814577e5c2800@mail.gmail.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
	<9e47339105032814577e5c2800@mail.gmail.com>
Message-ID: <1112051694.7035.6.camel@exponential.lanl.gov>

On Mon, 2005-03-28 at 17:57 -0500, Jon Smirl wrote:
> On Mon, 28 Mar 2005 15:28:20 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> > Can you go to
> > 
> > http://www.openbios.org/cgi-bin/viewarch.cgi
> > 
> > to check the version in the TLA ?
> > 
> 
> Different output but same failure. This looks like a problem with the
> BIOS emulation not with the emu86.
> 

Paulo,

Can you send him (and me) your most updated version?
The message

	updating int vector 0x0
	c000:00a3: 63 ILLEGAL X86 OPCODE!
	halt_sys: file ops.c, line 93

means the emulator is have a NULL pointer reference.

BTW, what vga cards are you using?

-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From jonsmirl at gmail.com  Tue Mar 29 01:29:57 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Mon, 28 Mar 2005 18:29:57 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1112051694.7035.6.camel@exponential.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
	<9e47339105032814577e5c2800@mail.gmail.com>
	<1112051694.7035.6.camel@exponential.lanl.gov>
Message-ID: <9e47339105032815293607782a@mail.gmail.com>

On Mon, 28 Mar 2005 16:14:54 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> On Mon, 2005-03-28 at 17:57 -0500, Jon Smirl wrote:
> > On Mon, 28 Mar 2005 15:28:20 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> > > Can you go to
> > >
> > > http://www.openbios.org/cgi-bin/viewarch.cgi
> > >
> > > to check the version in the TLA ?
> > >
> >
> > Different output but same failure. This looks like a problem with the
> > BIOS emulation not with the emu86.
> >
> 
> Paulo,
> 
> Can you send him (and me) your most updated version?
> The message
> 
>         updating int vector 0x0
>         c000:00a3: 63 ILLEGAL X86 OPCODE!
>         halt_sys: file ops.c, line 93
> 
> means the emulator is have a NULL pointer reference.
> 
> BTW, what vga cards are you using?

ATI Radeon 9000
ATI Rage128
S3 based one

They are all failing.

> --
> Li-Ta Lo <ollie at lanl.gov>
> Los Alamos National Lab
> 
> 


-- 
Jon Smirl
jonsmirl at gmail.com



From ollie at lanl.gov  Tue Mar 29 01:39:24 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Mon, 28 Mar 2005 16:39:24 -0700
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <9e47339105032815293607782a@mail.gmail.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
	<9e47339105032814577e5c2800@mail.gmail.com>
	<1112051694.7035.6.camel@exponential.lanl.gov>
	<9e47339105032815293607782a@mail.gmail.com>
Message-ID: <1112053164.7035.11.camel@exponential.lanl.gov>

On Mon, 2005-03-28 at 18:29 -0500, Jon Smirl wrote:
> On Mon, 28 Mar 2005 16:14:54 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> > On Mon, 2005-03-28 at 17:57 -0500, Jon Smirl wrote:
> > > On Mon, 28 Mar 2005 15:28:20 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> > > > Can you go to
> > > >
> > > > http://www.openbios.org/cgi-bin/viewarch.cgi
> > > >
> > > > to check the version in the TLA ?
> > > >
> > >
> > > Different output but same failure. This looks like a problem with the
> > > BIOS emulation not with the emu86.
> > >
> > 
> > Paulo,
> > 
> > Can you send him (and me) your most updated version?
> > The message
> > 
> >         updating int vector 0x0
> >         c000:00a3: 63 ILLEGAL X86 OPCODE!
> >         halt_sys: file ops.c, line 93
> > 
> > means the emulator is have a NULL pointer reference.
> > 
> > BTW, what vga cards are you using?
> 
> ATI Radeon 9000
> ATI Rage128
> S3 based one
> 

I always had problem with those old S3 cards. Can you try some recent 
Nvidia cards?

-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From jonsmirl at gmail.com  Tue Mar 29 03:05:17 2005
From: jonsmirl at gmail.com (Jon Smirl)
Date: Mon, 28 Mar 2005 20:05:17 -0500
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1112051694.7035.6.camel@exponential.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
	<9e47339105032814577e5c2800@mail.gmail.com>
	<1112051694.7035.6.camel@exponential.lanl.gov>
Message-ID: <9e4733910503281705733fb308@mail.gmail.com>

On Mon, 28 Mar 2005 16:14:54 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> On Mon, 2005-03-28 at 17:57 -0500, Jon Smirl wrote:
> > On Mon, 28 Mar 2005 15:28:20 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
> > > Can you go to
> > >
> > > http://www.openbios.org/cgi-bin/viewarch.cgi
> > >
> > > to check the version in the TLA ?
> > >
> >
> > Different output but same failure. This looks like a problem with the
> > BIOS emulation not with the emu86.
> >
> 
> Paulo,
> 
> Can you send him (and me) your most updated version?
> The message
> 
>         updating int vector 0x0
>         c000:00a3: 63 ILLEGAL X86 OPCODE!
>         halt_sys: file ops.c, line 93
> 
> means the emulator is have a NULL pointer reference.
> 
> BTW, what vga cards are you using?

ATI Radeon 9000
ATI Rage128
S3 based one

They are all failing.

> --
> Li-Ta Lo <ollie at lanl.gov>
> Los Alamos National Lab
> 
> 


-- 
Jon Smirl
jonsmirl at gmail.com



From yinghailu at gmail.com  Tue Mar 29 05:13:20 2005
From: yinghailu at gmail.com (yhlu)
Date: Mon, 28 Mar 2005 19:13:20 -0800
Subject: [LinuxBIOS] Any MB with smsc DME1737?
Message-ID: <2ea3fae10503281913329b50ff@mail.gmail.com>

I hope someone can test my code about that.

YH



From kevin at koconnor.net  Tue Mar 29 05:57:50 2005
From: kevin at koconnor.net (Kevin O'Connor)
Date: Mon, 28 Mar 2005 22:57:50 -0500
Subject: [LinuxBIOS] Re: Error in compiling STPC Consumer
In-Reply-To: <m3sm2l6nv9.fsf@maxwell.lnxi.com>
References: <8a0c36780503230709586f04be@mail.gmail.com>
	<20050324055417.18547.qmail@web8410.mail.in.yahoo.com>
	<8a0c367805032407117f7f5d5e@mail.gmail.com>
	<m3sm2l6nv9.fsf@maxwell.lnxi.com>
Message-ID: <20050329035750.GA14309@double.lan>

On Thu, Mar 24, 2005 at 08:54:18AM -0700, Eric W. Biederman wrote:
> All you have to do is not tell romcc it has mmx or sse registers.  
> For a modern memory controller that gets awfully tight but for a
> simpler memory controller it should be doable, to make everything
> fit.  I almost had the Opteron memory controller working in just 8
> registers.

Just out of curiosity, would getting romcc to work in 64bit mode be
worthwhile?  It would give the compiler access to eight additional 64
bit registers..

-Kevin



From ebiederman at lnxi.com  Tue Mar 29 06:44:21 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: 28 Mar 2005 21:44:21 -0700
Subject: [LinuxBIOS] Re: Error in compiling STPC Consumer
In-Reply-To: <20050329035750.GA14309@double.lan>
References: <8a0c36780503230709586f04be@mail.gmail.com>
	<20050324055417.18547.qmail@web8410.mail.in.yahoo.com>
	<8a0c367805032407117f7f5d5e@mail.gmail.com>
	<m3sm2l6nv9.fsf@maxwell.lnxi.com> <20050329035750.GA14309@double.lan>
Message-ID: <m3vf7bkqmy.fsf@maxwell.lnxi.com>

Kevin O'Connor <kevin at koconnor.net> writes:

> On Thu, Mar 24, 2005 at 08:54:18AM -0700, Eric W. Biederman wrote:
> > All you have to do is not tell romcc it has mmx or sse registers.  
> > For a modern memory controller that gets awfully tight but for a
> > simpler memory controller it should be doable, to make everything
> > fit.  I almost had the Opteron memory controller working in just 8
> > registers.
> 
> Just out of curiosity, would getting romcc to work in 64bit mode be
> worthwhile?  It would give the compiler access to eight additional 64
> bit registers..

Potentially the down side is that we are going to loose at
least 4KiB of the ROM for page tables.   The benefit
is 8 additional general purpose registers and 8 more sse registers.

The code is designed to be portable so it shouldn't be too
hard to do a 64bit port.  So have fun if you want to try it.

The biggest potential benefit on the romcc side is being able to avoid
inlining some procedure calls but that is a much harder problem.

Eric



From liutao1980 at gmail.com  Tue Mar 29 09:26:39 2005
From: liutao1980 at gmail.com (Tao Liu)
Date: Tue, 29 Mar 2005 15:26:39 +0800
Subject: [LinuxBIOS] [PATCH] amd8131 print secondary bus mode/frequency
Message-ID: <8eca059b050328232649fc9d9b@mail.gmail.com>

Hello,

this patch prints the secondary bus mode/frequency during amd8131 init process,
maybe this can help users to configure PCI-X mode/frequency jumpers.

--- freebios2-20050305-0000-orig/src/southbridge/amd/amd8131/amd8131_bridge.c	2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000/src/southbridge/amd/amd8131/amd8131_bridge.c	2005-03-29
10:18:19.000000000 +0800
@@ -76,6 +76,28 @@
 		dword |= (1<<1);
 		pci_write_config32(dev, 0xc8, dword);
 	}
+
+	/* Print Secondary Bus frequency */
+	dword = pci_read_config32(dev, 0xa0);
+	dword = ((dword >> 22) & 0x7);
+	printk_debug("Secondary bus mode: ");
+	switch (dword) {
+	case 0:
+		printk_debug("Conventional PCI\n");
+		break;
+	case 1:
+		printk_debug("66MHz PCI-X\n");
+		break;
+	case 2:
+		printk_debug("100MHz PCI-X\n");
+		break;
+	case 3:
+		printk_debug("133MHz PCI-X\n");
+		break;
+	default:
+		printk_debug("Unknown\n");
+		break;
+	}
 	
 	return;
 }

-- 
Liu Tao



From stuge-linuxbios at cdy.org  Tue Mar 29 11:38:49 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Tue, 29 Mar 2005 11:38:49 +0200
Subject: [LinuxBIOS] Re: NSC sc1100 port
In-Reply-To: <4248EB47.3060908@setabox.com>
References: <4248EB47.3060908@setabox.com>
Message-ID: <20050329093849.GC18355@foo.birdnet.se>

On Tue, Mar 29, 2005 at 01:44:39PM +0800, William J Beksi wrote:
> Has anyone ported or working on porting the National Semicondutor
> sc1100 cpu?

There has been work made in the freebios tree (often called v1) to
support scx200s, check out the nano mainboard, but I'm not sure what
the differences between x200 and x100 are.


//Peter



From ramesh_bios at yahoo.com  Tue Mar 29 12:10:19 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Tue, 29 Mar 2005 02:10:19 -0800 (PST)
Subject: [LinuxBIOS] Offtopic: Datasheet for VIA VT8237 southbridge and
	CLE266 northbridge
Message-ID: <20050329101019.54694.qmail@web30005.mail.mud.yahoo.com>

Hi guys,

I've been googling for the VIA VT8237 southbridge and
the CLE266 datasheets. No luck so far. About to mail
their support email address. Hopefully I'll get
register specs rather than a marketing brochure.
Anyone happen to have this info and/or suggestions on
how to get it quickly? Please feel free to mail me
privately.

Thanks.



		
__________________________________ 
Do you Yahoo!? 
Yahoo! Small Business - Try our new resources site!
http://smallbusiness.yahoo.com/resources/ 



From pmarques at grupopie.com  Tue Mar 29 13:33:21 2005
From: pmarques at grupopie.com (Paulo Marques)
Date: Tue, 29 Mar 2005 12:33:21 +0100
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1112048900.7035.3.camel@exponential.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>	
	<1111904108.5983.5.camel@logarithm.lanl.gov>	
	<9e47339105032623152c5bc006@mail.gmail.com>	
	<1112033108.3612.9.camel@exponential.lanl.gov>	
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
Message-ID: <42493D01.3020108@grupopie.com>

Li-Ta Lo wrote:
> On Mon, 2005-03-28 at 19:44 +0100, Paulo Marques wrote:
> 
>>Jon Smirl wrote:
>>
>>>On Mon, 28 Mar 2005 11:05:08 -0700, Li-Ta Lo <ollie at lanl.gov> wrote:
>>>
>>>
>>>>>>Which version of x86emu are you using? The larger one from XF86 or the
>>>>>>reduced version from Paulo?
>>>>>
>>>>>The one from linux BIOS cvs:
>>>>>linuxbios/src/devices/emulator/x86emu
>>>>>
>>>>
>>>>Actually, the code on the LinuxBIOS cvs may be the reduced version by
>>>>Paulo, depending on when you check it out. Paulo's version has some
>>>>bug such that it may fail to init the hardware. I did commited some
>>>>fix to the CVS I got from him. But there are some fixed not commited
>>>>dur to the CVS -> TLA transition.
>>>
>>>
>>>What I used is in the current CVS repository:
>>>:pserver:anonymous at cvs.sourceforge.net:/cvsroot/freebios
>>
>>I just went there to check out the versions.
>>
> 
> 
> Can you go to 
> 
> http://www.openbios.org/cgi-bin/viewarch.cgi
> 
> to check the version in the TLA ?

The version there is the large version and it still has the "#define 
xorl" bug in ops2.c...

-- 
Paulo Marques
Software Development Department - Grupo PIE, S.A.
Phone: +351 252 290600, Fax: +351 252 290601
Web: www.grupopie.com

All that is necessary for the triumph of evil is that good men do nothing.
Edmund Burke (1729 - 1797)



From pmarques at grupopie.com  Tue Mar 29 14:27:04 2005
From: pmarques at grupopie.com (Paulo Marques)
Date: Tue, 29 Mar 2005 13:27:04 +0100
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <1112048900.7035.3.camel@exponential.lanl.gov>
References: <9e4733910503261136395beac2@mail.gmail.com>	
	<1111904108.5983.5.camel@logarithm.lanl.gov>	
	<9e47339105032623152c5bc006@mail.gmail.com>	
	<1112033108.3612.9.camel@exponential.lanl.gov>	
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
Message-ID: <42494998.7050005@grupopie.com>

Li-Ta Lo wrote:
>[...]
>>>
>>>What I used is in the current CVS repository:
>>>:pserver:anonymous at cvs.sourceforge.net:/cvsroot/freebios
>>
>>I just went there to check out the versions.
>>
> 
> 
> Can you go to 
> 
> http://www.openbios.org/cgi-bin/viewarch.cgi
> 
> to check the version in the TLA ?

Oops, if I go to:

freebios->devel->2.0->patch-13 -> util/vgabios/x86emu/src/x86emu

the version there is the reduced one, but still has the nasty "XCHG 
AX,BX" bug (and the "destination written on CMP" bug too).

Ollie, can you explain to Jon how to make the kind of logs you produced 
to test the reduced version? If he could send me a log of the problem it 
would be much easier to try to track it down.

Anyway, attached is my latest source (only the .c files). These can be 
replaced over a reduced version. I think that only ops.c, ops2.c and 
prim_ops.c have differences from any other reduced version out there.

I believe there is still a lot of room for code size reduction in there, 
but we must agree on two issues before I start improving on the code again:

  - where is the "official" repository?

  - does the reduced version behave like the large version, and if this 
is the case, can we make the reduced version the current official one?

A few more logs from different boards to test with the log tester might 
help us settle this last question. Having more logs will also help me 
develop more on the emulator and be able to test against known working 
versions to make sure there are no regressions.

As for the repository, I really don't care where it is, as long there is 
one official one instead of 3 or 4 like we have now. Even more, if you 
think is ok for me to hack on the emulator and then just send the new 
version to the linuxbios mailing list and to Kendall, so that whoever 
wants it might update their repositories, that is fine by me, also.

-- 
Paulo Marques
Software Development Department - Grupo PIE, S.A.
Phone: +351 252 290600, Fax: +351 252 290601
Web: www.grupopie.com

All that is necessary for the triumph of evil is that good men do nothing.
Edmund Burke (1729 - 1797)
-------------- next part --------------
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From stepan at openbios.org  Tue Mar 29 14:29:00 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Tue, 29 Mar 2005 14:29:00 +0200
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <42493D01.3020108@grupopie.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
	<42493D01.3020108@grupopie.com>
Message-ID: <20050329122900.GA14291@openbios.org>

* Paulo Marques <pmarques at grupopie.com> [050329 13:33]:
> >to check the version in the TLA ?
> 
> The version there is the large version and it still has the "#define 
> xorl" bug in ops2.c...

There's the other one in the
linuxbios at linuxbios.org--devel/freebios--devel--2.0 tree, not sure if
that is what Ollie meant.




From smithbone at gmail.com  Tue Mar 29 15:33:17 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 29 Mar 2005 07:33:17 -0600
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <42494998.7050005@grupopie.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
	<42494998.7050005@grupopie.com>
Message-ID: <8a0c36780503290533273aec22@mail.gmail.com>

> but we must agree on two issues before I start improving on the code again:
> 
>   - where is the "official" repository?
> 

linubios just cut over from sourceforge CVS to TLA on openbios.org. 
CVS is deprecated should now be read only.  So the "official" tree is
whats in TLA.

http://wiki.linuxbios.org/index.php/Download_freebios_v2

Has all the details.  Note if you find any details that are incorrect
let us know as we are still getting the transfer fully worked out.

-- 
Richard A. Smith



From bari at onelabs.com  Tue Mar 29 16:45:02 2005
From: bari at onelabs.com (Bari Ari)
Date: Tue, 29 Mar 2005 08:45:02 -0600
Subject: [LinuxBIOS] Offtopic: Datasheet for VIA VT8237 southbridge and
	CLE266 northbridge
In-Reply-To: <20050329101019.54694.qmail@web30005.mail.mud.yahoo.com>
References: <20050329101019.54694.qmail@web30005.mail.mud.yahoo.com>
Message-ID: <424969EE.4010705@onelabs.com>

ramesh bios wrote:
> Hi guys,
> 
> I've been googling for the VIA VT8237 southbridge and
> the CLE266 datasheets. No luck so far. About to mail
> their support email address. Hopefully I'll get
> register specs rather than a marketing brochure.
> Anyone happen to have this info and/or suggestions on
> how to get it quickly? Please feel free to mail me
> privately.

Contact VIA sales, convince VIA that it's worth their time and effort to 
support you, sign their NDA and then receive their datasheets.

-Bari



From smithbone at gmail.com  Tue Mar 29 17:32:42 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 29 Mar 2005 09:32:42 -0600
Subject: [LinuxBIOS] New version of ROM posting app
In-Reply-To: <42496543.2030600@grupopie.com>
References: <9e4733910503261136395beac2@mail.gmail.com>
	<1111904108.5983.5.camel@logarithm.lanl.gov>
	<9e47339105032623152c5bc006@mail.gmail.com>
	<1112033108.3612.9.camel@exponential.lanl.gov>
	<9e4733910503281011c2773bd@mail.gmail.com>
	<424850A7.8030506@grupopie.com>
	<1112048900.7035.3.camel@exponential.lanl.gov>
	<42494998.7050005@grupopie.com>
	<8a0c36780503290533273aec22@mail.gmail.com>
	<42496543.2030600@grupopie.com>
Message-ID: <8a0c36780503290732790ce4c0@mail.gmail.com>

> 
> I'm assuming then that the linuxbios->freebios->devel-2.0 is the most up
> to date, and that I should use that one as the official one.
> 
> Is this correct?

Yes. freebios--devel--2.0 freebios2 is where your tree should come from.

It may not necessarly be the most up to date.  But its headed that
way.  One of the reasons to move to tla was because every one has
thier own tree and tla makes syncing and managing those individual
trees easier.  There are one or 2 tree syncs in progress.  I don't
think any of them affect the emulator itself just how it may be
called.

Its the official tree now and if you fix that one then everyone else
can diff and come into line.

-- 
Richard A. Smith



From rminnich at lanl.gov  Tue Mar 29 18:42:38 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 29 Mar 2005 09:42:38 -0700 (MST)
Subject: [LinuxBIOS] Re: NSC sc1100 port
In-Reply-To: <424984FC.2050501@onelabs.com>
References: <4248EB47.3060908@setabox.com>
	<Pine.LNX.4.58.0503290845340.31904@enigma.lanl.gov>
	<424984FC.2050501@onelabs.com>
Message-ID: <Pine.LNX.4.58.0503290942160.31904@enigma.lanl.gov>





On Tue, 29 Mar 2005, Bari Ari wrote:

> It's a Geode (x86).

right, I forgot. 

moving this reply to new mailing list, hope you get it.

ron



From talbotx at comcast.net  Tue Mar 29 21:57:36 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Tue, 29 Mar 2005 11:57:36 -0800
Subject: [LinuxBIOS] Status on the Via EPIA MII boards?
References: <4248EB47.3060908@setabox.com><Pine.LNX.4.58.0503290845340.31904@enigma.lanl.gov><424984FC.2050501@onelabs.com>
	<Pine.LNX.4.58.0503290942160.31904@enigma.lanl.gov>
Message-ID: <001e01c53499$8e5bf900$c501a8c0@newflame>

-Ron
What is the status of the MII board, is the south bridge running?
-Adam




From stuge-linuxbios at cdy.org  Tue Mar 29 22:57:58 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Tue, 29 Mar 2005 22:57:58 +0200
Subject: [LinuxBIOS] Re: NSC sc1100 port
In-Reply-To: <424984FC.2050501@onelabs.com>
References: <4248EB47.3060908@setabox.com>
	<Pine.LNX.4.58.0503290845340.31904@enigma.lanl.gov>
	<424984FC.2050501@onelabs.com>
Message-ID: <20050329205758.GD7659@foo.birdnet.se>

On Tue, Mar 29, 2005 at 10:40:28AM -0600, Bari Ari wrote:
> http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_10524,00.html

Looks like a smaller sibling of the SCx200s. Might work with little
to no modification of the nano code in v1.


//Peter



From rminnich at lanl.gov  Tue Mar 29 23:20:40 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 29 Mar 2005 14:20:40 -0700 (MST)
Subject: [LinuxBIOS] Re: Status on the Via EPIA MII boards?
In-Reply-To: <001e01c53499$8e5bf900$c501a8c0@newflame>
References: <4248EB47.3060908@setabox.com><Pine.LNX.4.58.0503290845340.31904@enigma.lanl.gov><424984FC.2050501@onelabs.com>
	<Pine.LNX.4.58.0503290942160.31904@enigma.lanl.gov>
	<001e01c53499$8e5bf900$c501a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0503291420170.31904@enigma.lanl.gov>



On Tue, 29 Mar 2005, Adam Talbot wrote:

> -Ron
> What is the status of the MII board, is the south bridge running?

working on the last problem on plain epia first, south came up but no 
enet.

ron



From bari at onelabs.com  Tue Mar 29 23:22:50 2005
From: bari at onelabs.com (Bari Ari)
Date: Tue, 29 Mar 2005 15:22:50 -0600
Subject: [LinuxBIOS] Re: NSC sc1100 port
In-Reply-To: <20050329205758.GD7659@foo.birdnet.se>
References: <4248EB47.3060908@setabox.com>	<Pine.LNX.4.58.0503290845340.31904@enigma.lanl.gov>	<424984FC.2050501@onelabs.com>
	<20050329205758.GD7659@foo.birdnet.se>
Message-ID: <4249C72A.902@onelabs.com>

Peter Stuge wrote:


> Looks like a smaller sibling of the SCx200s. Might work with little
> to no modification of the nano code in v1.

The SC1100 is for designs that don't need graphics. The rest is the same 
as the SCx200's.

-Bari



From jwalsh at bigpond.net.au  Wed Mar 30 07:29:06 2005
From: jwalsh at bigpond.net.au (Justin Walsh)
Date: Tue, 29 Mar 2005 21:29:06 -0800
Subject: [LinuxBIOS] Bios "Bible"?
Message-ID: <001501c534e9$6452cee0$0300a8c0@nsw.bigpond.net.au>


Or what is the definitive Blue Book on:
1. Bios in General?
3. Bios in particular?
3. How does one switch a 686 or 786 from native into real mode? i.e. 286
emulation?
Thanks
JW

http://en.wikipedia.org/wiki/BIOS
Google Search on Bios:
http://www.google.com.au/search?hl=en&q=Bios&btnG=Google+Search&meta=




From stuge-linuxbios at cdy.org  Wed Mar 30 01:25:42 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Wed, 30 Mar 2005 01:25:42 +0200
Subject: [LinuxBIOS] Bios "Bible"?
In-Reply-To: <001501c534e9$6452cee0$0300a8c0@nsw.bigpond.net.au>
References: <001501c534e9$6452cee0$0300a8c0@nsw.bigpond.net.au>
Message-ID: <20050329232542.GB28709@foo.birdnet.se>

On Tue, Mar 29, 2005 at 09:29:06PM -0800, Justin Walsh wrote:
> 
> Or what is the definitive Blue Book on:
> 1. Bios in General?
> 3. Bios in particular?

I'm not sure there is one. Traditionally BIOS code seem to have been
a secret well-kept by mainboard/BIOS companies.


> 3. How does one switch a 686 or 786 from native into real mode?
> i.e. 286 emulation?

x86 CPUs start up in a backwards-compatible 8086 real mode. Protected
mode is entered by setting bit 0 in the cr0 register, but first some
descriptor tables need to be set up. Switching back and forth
basically is a matter of flipping the PE bit.


//Peter



From aphthong at sizzard.com  Wed Mar 30 01:36:43 2005
From: aphthong at sizzard.com (aphthong at sizzard.com)
Date: Tue, 29 Mar 2005 15:36:43 -0800
Subject: [LinuxBIOS] Bios "Bible"?
In-Reply-To: <001501c534e9$6452cee0$0300a8c0@nsw.bigpond.net.au>
References: <001501c534e9$6452cee0$0300a8c0@nsw.bigpond.net.au>
Message-ID: <6.2.0.14.2.20050329153610.0471eb50@mail.sizzard.com>

Your best bet it "The Undocumented PC" by Frank van Gilluwre.

Jordan

At 09:29 PM 3/29/2005, Justin Walsh wrote:

>Or what is the definitive Blue Book on:
>1. Bios in General?
>3. Bios in particular?
>3. How does one switch a 686 or 786 from native into real mode? i.e. 286
>emulation?
>Thanks
>JW
>
>http://en.wikipedia.org/wiki/BIOS
>Google Search on Bios:
>http://www.google.com.au/search?hl=en&q=Bios&btnG=Google+Search&meta=
>
>
>_______________________________________________
>LinuxBIOS mailing list
>LinuxBIOS at openbios.org
>http://www.openbios.org/mailman/listinfo/linuxbios




From ramesh_bios at yahoo.com  Wed Mar 30 05:28:00 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Tue, 29 Mar 2005 19:28:00 -0800 (PST)
Subject: [LinuxBIOS] RTC on geode gx1
Message-ID: <20050330032800.71775.qmail@web30009.mail.mud.yahoo.com>

I'm using the freebios v1 tree on a geode
gx1/cs5530a/w83977 with 2.6.11. I noticed that there
appears to be problem with writing to the RTC using
hwclock. I seem to be able to use hwclock to set the
time but not the date. That is:

# date
Wed Mar 30 09:16:11 IST 2005
# hwclock
Mon Jan 10 08:56:16 2005  0.000000 seconds
# hwclock -w
# hwclock
Tue Jan 11 09:16:21 2005  0.000000 seconds

I noticed that the date went to Jan 11 while the time
was updated correctly. When I switch back to the
vendor BIOS, this issue goes away. I'm not yet sure
what to suspect. I'll go look at the kernel's rtc code
for writing to the CMOS since it would appear that it
can set the time but not the date for some reason. If
anyone has any suggestions, please let me know.

Thanks.

__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 



From stepan at openbios.org  Wed Mar 30 09:25:58 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed, 30 Mar 2005 09:25:58 +0200
Subject: [LinuxBIOS] Re: Amlcode structure generation
In-Reply-To: <9B124F08B3EFDA4F8813B05102DC719502109CAE@nh-ex01.bench.com>
References: <9B124F08B3EFDA4F8813B05102DC719502109CAE@nh-ex01.bench.com>
Message-ID: <20050330072558.GA4764@openbios.org>

* Peter.VanEchaute at bench.com <Peter.VanEchaute at bench.com> [050329 23:20]:
> I am not a guru on the topic of ACIP or APIC.? I am attempting to make a stab
> at it and had a question about the file
> 
> src/mainboard/island/aruma/dsdt.c
> 
> My question is how was it created?

Using iasl, intel's aml compiler. 

Stefan





From ourlinuxid at yahoo.co.in  Wed Mar 30 14:38:19 2005
From: ourlinuxid at yahoo.co.in (Ramesh Chhaba)
Date: Wed, 30 Mar 2005 13:38:19 +0100 (BST)
Subject: [LinuxBIOS] logic error in rom image geomatry
Message-ID: <20050330123819.17866.qmail@web8408.mail.in.yahoo.com>


Hi All ,

I am trying to understand the boot sequence of PC BIOS

I have got an rough idea it is as follows

 1. system power up and fetch up first from ffffff0 addr. 
 2. there  is a near jump to code  to get system in to flat or protected mode
 3. then we can jump to further secod stage bootloader after neccessary HW init.

 Plz  Somebody correct it and explain it in detail .
  
Second thing  
 My BIOS image is ok abt 10 KB (suppose)
 and i have chip of 256KB So my image is like this


      -------------------------  lower most address(00000)
  Second stage bootloader :  


     
 Protected mode init code :

 


  Basic HW init Code      : 


              ..ffff0      jmp instruction to Basic HW init code( at bottom )                           
                          --------------------------- uppermost address(ffff...)

(Fig is reversed as per normal figures in books for memory )


                      
And I want to know where to place this small code in BIG chip


         ---------------------Chip start  addr
                        
                         where to place my code in it ??? 

                                                   
               

 


   ----------------------chip end  addr

 

I think start and end of both will be in same direction  so it may be like this

  --------------------------lowest address for chip
   (free space with ff ff)

     -------------------------  lower most address(00000)
  Second stage bootloader :  


     
 Protected mode init code :

 


  Basic HW init Code      : 


  ..ffff0      jmp instruction to Basic HW init code( at bottom )                           

        --------------------------- uppermost address(ffff...) both for chip and code 
     
     

Plz comment  and correct above information .   

Thank you 

Ramesh Chander


Yahoo! India Matrimony: Find your life partneronline.
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From smithbone at gmail.com  Wed Mar 30 15:16:04 2005
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 30 Mar 2005 07:16:04 -0600
Subject: [LinuxBIOS] logic error in rom image geomatry
In-Reply-To: <20050330123819.17866.qmail@web8408.mail.in.yahoo.com>
References: <20050330123819.17866.qmail@web8408.mail.in.yahoo.com>
Message-ID: <8a0c36780503300516165c53a7@mail.gmail.com>

> Second thing  
>  My BIOS image is ok abt 10 KB (suppose)
>  and i have chip of 256KB So my image is like this 
>                       
> And I want to know where to place this small code in BIG chip 
> 

LInuxbios has to be located so that the reset vector code is at the
right location.  The PC reset vector is 0xfffffff0.  So the linuxbios
image has to occupy the very top of your  rom chip.

So if your flash is 256Kb = 262144 bytes.
your lb size 10kb = 10240 bytes

Offset in flash chip to start programming = flash size - linubbios size 
= 262144 - 10240 = 251904

So as you can see you need to know the _exact_ size of your image file
even if you are only 1 byte off it still won't work.

Basically you have to make sure that the last 16 bytes of the
linuxbios image match the last 16 bytes of your flash chip.  
Everything else in the linuxbios image should be relative.

-- 
Richard A. Smith



From stuge-linuxbios at cdy.org  Wed Mar 30 21:41:58 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Wed, 30 Mar 2005 21:41:58 +0200
Subject: [LinuxBIOS] RTC on geode gx1
In-Reply-To: <20050330032800.71775.qmail@web30009.mail.mud.yahoo.com>
References: <20050330032800.71775.qmail@web30009.mail.mud.yahoo.com>
Message-ID: <20050330194158.GB19445@foo.birdnet.se>

On Tue, Mar 29, 2005 at 07:28:00PM -0800, ramesh bios wrote:
> I'm using the freebios v1 tree on a geode
> gx1/cs5530a/w83977 with 2.6.11. I noticed that there
> appears to be problem with writing to the RTC using
> hwclock. I seem to be able to use hwclock to set the
> time but not the date. That is:

There are a few bits in the 5530 at page 107 in the data sheet
regarding the RTC, but I doubt the RTC would be reachable at all if
they weren't ok.

I just went over the RTC part of the W83977F data sheet too and it
seems to have a couple of control bits that may have to be tweaked
to get proper operation. I don't remember if anyone else has had
similar problems with that superio.

Besides timing, the only other explanation I can think of is that
since time is stored in RTC registers 00h, 02h and 04h, date of month
in 07h and month/year in 08h-09h, if address bit 3 wasn't connected
properly then the date registers would be unreachable, but then you
should see some connection between time and date, so lack of proper
initialization or possibly a timing issue is my guess..


//Peter



From YhLu at tyan.com  Thu Mar 31 01:08:52 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 30 Mar 2005 15:08:52 -0800
Subject: [LinuxBIOS] Re: Error in compiling STPC Consumer
Message-ID: <3174569B9743D511922F00A0C943142309348CEB@TYANWEB>

Eric,

the code in raminit.c is_opteron will treat my athlon 64 (939) as Opteron
too.

YH

static int is_opteron(const struct mem_controller *ctrl)
{
        /* Test to see if I am an Opteron.  
         * FIXME Testing dual channel capability is correct for now
         * but a beter test is probably required.
         */
#warning "FIXME implement a better test for opterons"
        uint32_t nbcap;
        nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
        return !!(nbcap & NBCAP_128Bit);
}




From ramesh_bios at yahoo.com  Thu Mar 31 04:25:54 2005
From: ramesh_bios at yahoo.com (ramesh bios)
Date: Wed, 30 Mar 2005 18:25:54 -0800 (PST)
Subject: [LinuxBIOS] RTC on geode gx1
In-Reply-To: 6667
Message-ID: <20050331022554.71778.qmail@web30002.mail.mud.yahoo.com>

I noticed that, unlike, some of the other
northbridge/southbridge code, the cs5530 code doesn't
do an rtc_init(0). I added that and that now allows me
to set the date. But... I still have weirdness going
on:

RTC Init
RTC: Checksum invalid zeroing cmos
Invalid CMOS LB checksum

So now I'm in the process of reading the rtc_init
code, looking at the board (I know now that my
w83977AF is connected to a 32.768kHz oscillator) and
then figuring out what all the settings mean. That is,
stuff like below. I'm not sure whether the defaults
are good for any board or if they need to be
customized. I guess I'll be finding this out
iteratively.

/* control registers - Moto names
 */
#define RTC_REG_A               10
#define RTC_REG_B               11
#define RTC_REG_C               12
#define RTC_REG_D               13

#define RTC_FREQ_SELECT RTC_REG_A
#define RTC_CONTROL     RTC_REG_B
#define RTC_CONTROL_DEFAULT (RTC_24H)
#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ |
RTC_RATE_1024HZ)



--- Peter Stuge <stuge-linuxbios at cdy.org> wrote:
> On Tue, Mar 29, 2005 at 07:28:00PM -0800, ramesh
> bios wrote:
> > I'm using the freebios v1 tree on a geode
> > gx1/cs5530a/w83977 with 2.6.11. I noticed that
> there
> > appears to be problem with writing to the RTC
> using
> > hwclock. I seem to be able to use hwclock to set
> the
> > time but not the date. That is:
> 
> There are a few bits in the 5530 at page 107 in the
> data sheet
> regarding the RTC, but I doubt the RTC would be
> reachable at all if
> they weren't ok.
> 
> I just went over the RTC part of the W83977F data
> sheet too and it
> seems to have a couple of control bits that may have
> to be tweaked
> to get proper operation. I don't remember if anyone
> else has had
> similar problems with that superio.
> 
> Besides timing, the only other explanation I can
> think of is that
> since time is stored in RTC registers 00h, 02h and
> 04h, date of month
> in 07h and month/year in 08h-09h, if address bit 3
> wasn't connected
> properly then the date registers would be
> unreachable, but then you
> should see some connection between time and date, so
> lack of proper
> initialization or possibly a timing issue is my
> guess..
> 
> 
> //Peter
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 


		
__________________________________ 
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From YhLu at tyan.com  Thu Mar 31 05:03:22 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 30 Mar 2005 19:03:22 -0800
Subject: [LinuxBIOS] Athlon64 939
Message-ID: <3174569B9743D511922F00A0C943142309348D35@TYANWEB>

The Athlon 64 939 support dual channel.

but in the test in s2865 with d0 Athlon64 939 in LinuxBIOS, it only work
with one DIMM in socket 1.

weird....

the same code with Opteron d0 ....

YH

> -----Original Message-----
> From: YhLu 
> Sent: Wednesday, March 30, 2005 3:09 PM
> To: ebiederman at lnxi.com; Kevin O'Connor
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] Re: Error in compiling STPC Consumer
> 
> Eric,
> 
> the code in raminit.c is_opteron will treat my athlon 64 
> (939) as Opteron too.
> 
> YH
> 
> static int is_opteron(const struct mem_controller *ctrl) {
>         /* Test to see if I am an Opteron.  
>          * FIXME Testing dual channel capability is correct for now
>          * but a beter test is probably required.
>          */
> #warning "FIXME implement a better test for opterons"
>         uint32_t nbcap;
>         nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
>         return !!(nbcap & NBCAP_128Bit); }
> 
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From tony_cheng at pcmagic.net  Thu Mar 31 05:36:23 2005
From: tony_cheng at pcmagic.net (Tony Cheng)
Date: Wed, 30 Mar 2005 19:36:23 -0800
Subject: [LinuxBIOS] Mount linux elf image for netboot as loop device
Message-ID: <01fc01c535a2$cfb050e0$919814ac@trans.corp>


I used mkelfImage to combined Linux Kernel 2.4.20 and initrd into elf image for netboot. then I try to use "mount -o loop my_elfImage" to mount this image as a loop device. I get a error message like this:

#mount: you must specify the filesystem type

I have specified the my_elfImage in /etc/fstab as this: (I add a line in fstab because mount ask me to do that)

/root/loop/my_elfImage     /root/loop/tl           auto    noauto,owner,kudzu 0 0

I changed the file type from auto to ext3 and etc. but nothing work for me. 

Could anybody kindly help me on this? 

Thanks

tony
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From nathanael at gnat.ca  Thu Mar 31 05:44:18 2005
From: nathanael at gnat.ca (Nathanael Noblet)
Date: Wed, 30 Mar 2005 19:44:18 -0800
Subject: [LinuxBIOS] Mount linux elf image for netboot as loop device
In-Reply-To: <01fc01c535a2$cfb050e0$919814ac@trans.corp>
References: <01fc01c535a2$cfb050e0$919814ac@trans.corp>
Message-ID: <56bd62b916377fb95572145d6833a3bb@gnat.ca>


On Mar 30, 2005, at 7:36 PM, Tony Cheng wrote:

> ?
> I used mkelfImage to combined Linux Kernel 2.4.20 and initrd into elf 
> image for netboot. then I try to use "mount -o loop my_elfImage" to 
> mount this image?as a loop device. I get a error message like this:

mkelfimage doesn't make a filesystem as far as I know, and only puts 
the kernel into a format that the linuxbios expects to find so it can 
load it into ram and jump to it. What you are asking to do is about as 
the same as mounting a compiled program as a filesystem. You can't do 
'mount -o loop /bin/bash /mnt/loop' anymore then you can mount the 
kernel file.

-- 
Nathanael D. Noblet
Gnat Solutions
204 - 131 Gorge Road E
Victoria, BC V9A 1L1

T 250.385.4613
C 250.893.4613
http://www.gnat.ca/




From liutao1980 at gmail.com  Thu Mar 31 08:30:06 2005
From: liutao1980 at gmail.com (Tao Liu)
Date: Thu, 31 Mar 2005 14:30:06 +0800
Subject: [LinuxBIOS] [PATCH] small fixes
Message-ID: <8eca059b05033022304a8eb64@mail.gmail.com>

Hello,

this patch fixes two small program errors, one is loop condition always true,
the other is return 1 in void type function.


--- freebios2-20050305-0000-orig/src/drivers/generic/debug/debug_dev.c	2004-12-11
04:50:42.000000000 +0800
+++ freebios2-20050305-0000/src/drivers/generic/debug/debug_dev.c	2005-03-31
13:54:00.000000000 +0800
@@ -35,9 +35,10 @@
 static void print_pci_regs_all(void)
 {
         struct device *dev;
-	unsigned char bus, device, function;
+	unsigned int bus;
+	unsigned char device, function;
 
-	for(bus=0; bus<=256; bus++) {
+	for(bus=0; bus<=0xff; bus++) {
 		for(device=0; device<=0x1f; device++) {
 			for (function=0; function<=7; function++){
 				unsigned devfn;
--- freebios2-20050305-0000-orig/src/devices/emulator/biosemu.c	2005-01-20
07:19:26.000000000 +0800
+++ freebios2-20050305-0000/src/devices/emulator/biosemu.c	2005-03-31
13:24:26.000000000 +0800
@@ -122,7 +122,8 @@ void do_int(int num)
 	case 0x6D:
 		if (getIntVect(num) == 0x0000) {
 			printk_debug("un-inited int vector\n");
-			return 1;
+			//return 1;
+			ret = 1;
 		}
 		if (getIntVect(num) == 0xFF065) {
 			//ret = int42_handler();

-- 
Liu Tao



From liutao1980 at gmail.com  Thu Mar 31 09:19:56 2005
From: liutao1980 at gmail.com (Tao Liu)
Date: Thu, 31 Mar 2005 15:19:56 +0800
Subject: [LinuxBIOS] [PATCH 1/2] src/config/Options.lb: Add OEM ROM section
	definitions
Message-ID: <8eca059b0503302319785e078f@mail.gmail.com>

Hello,

this patch adds following options, for the use of OEM ROM section,
eg: onboard PCI device's BIOS in boot ROM or MAC address saved in boot ROM

ROM_TOTAL_SIZE: the total size of boot ROM
ROM_OEM_SIZE: the size of boot ROM used by OEM_ROM section
ROM_SIZE: the size of boot ROM used by LinuxBIOS
ROM_OEM_START: OEM_ROM start address

OEM ROM exists in the low address end of boot ROM, so
default ROM_OEM_SIZE = 0
default ROM_SIZE = ROM_TOTAL_SIZE - ROM_OEM_SIZE
default ROM_OEM_START = 0xffffffff - ROM_TOTAL_SIZE + 1

OEM devices should know the offset of their data in OEM ROM,
so they can visit their data at address (ROM_OEM_START + oem_my_data_offset)

to use OEM ROM, one should define ROM_TOTAL_SIZE and ROM_OEM_SIZE
in mainboard's Options.lb file. 

this patch won't break mainboards which defines ROM_SIZE and don't mentions
ROM_TOTAL_SIZE and ROM_OEM_SIZE.



--- freebios2-20050305-0000-orig/src/config/Options.lb	2005-01-15
05:54:16.000000000 +0800
+++ freebios2-20050305-0000/src/config/Options.lb	2005-03-30
20:49:16.000000000 +0800
@@ -190,11 +190,29 @@
 	export used
 	comment "Default fallback image size"
 end
-define ROM_SIZE
+define ROM_TOTAL_SIZE
 	default none
 	format "0x%x"
 	export used
-	comment "Size of your ROM"
+	comment "Size of your boot ROM"
+end
+define ROM_OEM_SIZE
+	default 0
+	format "0x%x"
+	export used
+	comment "Size of your ROM used by OEM vendors"
+end
+define ROM_OEM_START
+	default {0xffffffff - ROM_TOTAL_SIZE + 1}
+	format "0x%x"
+	export used
+	comment "OEM ROM start location"
+end
+define ROM_SIZE
+	default {ROM_TOTAL_SIZE - ROM_OEM_SIZE}
+	format "0x%x"
+	export used
+	comment "Size of your ROM used by LinuxBIOS"
 end
 define ROM_IMAGE_SIZE
 	default 65535

-- 
Liu Tao



From liutao1980 at gmail.com  Thu Mar 31 09:29:08 2005
From: liutao1980 at gmail.com (Tao Liu)
Date: Thu, 31 Mar 2005 15:29:08 +0800
Subject: [LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC address in linuxbios
Message-ID: <8eca059b050330232948f5be4b@mail.gmail.com>

Hello,

this patch sets 8111NIC's mac. The 48-bit mac address is saved in OEM ROM,
in nic_init() the driver gets the mac address through register oem_mac_offset,
and copy it to 8111NIC's PADR register.


diff -Nur freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c
freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c
--- freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c	2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c	2005-03-31
12:50:56.000000000 +0800
@@ -6,20 +6,99 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <delay.h>
 #include "amd8111.h"
 
+#undef writel
+#undef writeb
+#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val))
+#define writeb(val,addr) (*(volatile uint8_t *)(addr) = (val))
 
+#define CMD3		0x54
+#define PADR		0x160
+
+typedef enum {
+	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
+	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
+	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
+	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
+}VAL_BITS;
+
+typedef enum {
+	/* VAL3 */
+	ASF_INIT_DONE_ALIAS	= (1 << 29),
+	/* VAL2 */
+	JUMBO			= (1 << 21),
+	VSIZE			= (1 << 20),	
+	VLONLY			= (1 << 19),
+	VL_TAG_DEL		= (1 << 18),	
+	/* VAL1 */
+	EN_PMGR			= (1 << 14),			
+	INTLEVEL		= (1 << 13),
+	FORCE_FULL_DUPLEX	= (1 << 12),	
+	FORCE_LINK_STATUS	= (1 << 11),	
+	APEP			= (1 << 10),	
+	MPPLBA			= (1 << 9),	
+	/* VAL0 */
+	RESET_PHY_PULSE		= (1 << 2),	
+	RESET_PHY		= (1 << 1),	
+	PHY_RST_POL		= (1 << 0),	
+}CMD3_BITS;
+
+static void nic_init(struct device *dev)
+{
+	struct southbridge_amd_amd8111_config *conf;
+	struct resource *resource;
+	void *mmio;
+	unsigned char *oem_mac_addr;
+	int i;
+
+	conf = dev->chip_info;
+	resource = find_resource(dev, PCI_BASE_ADDRESS_0);
+	mmio = (void *)(unsigned long)resource->base;
+
+	/* Hard Reset PHY */
+	printk_debug("Reseting PHY... ");
+	if (conf->phy_lowreset) {
+		writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3);
+	} else {
+		writel(VAL0 | RESET_PHY, mmio + CMD3);
+	}
+	mdelay(15);
+	writel(RESET_PHY, mmio + CMD3);
+	printk_debug("Done\n");
+
+	/* Set MAC address */
+	printk_debug("Mac Addr ");
+	oem_mac_addr = (unsigned char *)(ROM_OEM_START + conf->oem_mac_offset);
+	for (i = 0; i < 6; i++) {
+		printk_debug("%02X%c", oem_mac_addr[i], i == 5 ? '\n' : ':');
+		writeb(oem_mac_addr[i], mmio + PADR + i);
+	}
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0xc8,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+	
 static struct device_operations nic_ops  = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.enable           = amd8111_enable,
-	.init             = 0,
+	.init		  = nic_init,
 	.scan_bus         = 0,
+	.enable		  = amd8111_enable,
+	.ops_pci	  = &lops_pci,
 };
 
 static struct pci_driver nic_driver __pci_driver = {
 	.ops    = &nic_ops,
 	.vendor = PCI_VENDOR_ID_AMD,
-	.device = 0x7462,
+	.device = PCI_DEVICE_ID_AMD_8111_NIC,
 };
diff -Nur freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h
freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h
--- freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h	2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h	2005-03-31
12:49:32.000000000 +0800
@@ -5,6 +5,8 @@
 {
 	unsigned int ide0_enable : 1;
 	unsigned int ide1_enable : 1;
+	unsigned int phy_lowreset : 1;
+	unsigned long oem_mac_offset;
 };
 
 struct chip_operations;


-- 
Liu Tao



From ebiederman at lnxi.com  Thu Mar 31 12:00:54 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: 31 Mar 2005 03:00:54 -0700
Subject: [LinuxBIOS] Re: Athlon64 939
In-Reply-To: <3174569B9743D511922F00A0C943142309348D35@TYANWEB>
References: <3174569B9743D511922F00A0C943142309348D35@TYANWEB>
Message-ID: <m3ll84i17t.fsf@maxwell.lnxi.com>

YhLu <YhLu at tyan.com> writes:

> The Athlon 64 939 support dual channel.
> 
> but in the test in s2865 with d0 Athlon64 939 in LinuxBIOS, it only work
> with one DIMM in socket 1.
> 
> weird....
> 
> the same code with Opteron d0 ....

I seem to recall that unbuffered DIMMS have some pretty hefty restrictions,
on what works and what doesn't.  One DIMM per channel may be correct.

If these are registered DIMMS this appears to be a deeper issue.  You might
want to try running the memory as PC2700, to see if that gets you farther.

> > -----Original Message-----
> > From: YhLu 
> > Sent: Wednesday, March 30, 2005 3:09 PM
> > To: ebiederman at lnxi.com; Kevin O'Connor
> > Cc: linuxbios at openbios.org
> > Subject: RE: [LinuxBIOS] Re: Error in compiling STPC Consumer
> > 
> > Eric,
> > 
> > the code in raminit.c is_opteron will treat my athlon 64 
> > (939) as Opteron too.

Reflecting on this.  It looks like the test needs to be against
the brand-id field of cpuid.

Eric




From ourlinuxid at yahoo.co.in  Thu Mar 31 13:34:07 2005
From: ourlinuxid at yahoo.co.in (Ramesh Chhaba)
Date: Thu, 31 Mar 2005 12:34:07 +0100 (BST)
Subject: [LinuxBIOS] Simulator to test BIOS 
Message-ID: <20050331113407.45242.qmail@web8406.mail.in.yahoo.com>

Hi all ,
 
I want any simulator that i can use as virtual machine to test my romimage without burning it in to actual chip.
 
I there is any  such software or alternative .
 
Thank you
 
Ramesh Chander

Yahoo! India Matrimony: Find your life partneronline.
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From ourlinuxid at yahoo.co.in  Thu Mar 31 13:34:21 2005
From: ourlinuxid at yahoo.co.in (Ramesh Chhaba)
Date: Thu, 31 Mar 2005 12:34:21 +0100 (BST)
Subject: [LinuxBIOS] Simulator to test BIOS 
Message-ID: <20050331113421.49388.qmail@web8405.mail.in.yahoo.com>

Hi all ,
 
I want any simulator that i can use as virtual machine to test my romimage without burning it in to actual chip.
 
I there is any  such software or alternative .
 
Thank you
 
Ramesh Chander


Yahoo! India Matrimony: Find your life partneronline.
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From stepan at openbios.org  Thu Mar 31 14:38:36 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu, 31 Mar 2005 14:38:36 +0200
Subject: [LinuxBIOS] Simulator to test BIOS
In-Reply-To: <20050331113421.49388.qmail@web8405.mail.in.yahoo.com>
References: <20050331113421.49388.qmail@web8405.mail.in.yahoo.com>
Message-ID: <20050331123835.GA10359@openbios.org>

* Ramesh Chhaba <ourlinuxid at yahoo.co.in> [050331 13:34]:
> Hi all ,
>  
> I want any simulator that i can use as virtual machine to test my romimage
> without burning it in to actual chip.
>  
> I there is any  such software or alternative .
>  
> Thank you

Go have a look at http://www.promice.com/

You will find out that you can pull the chip a couple of times before
these devices are charged off.

Stefan





From smithbone at gmail.com  Thu Mar 31 14:50:26 2005
From: smithbone at gmail.com (Richard Smith)
Date: Thu, 31 Mar 2005 06:50:26 -0600
Subject: [LinuxBIOS] Simulator to test BIOS
In-Reply-To: <20050331113407.45242.qmail@web8406.mail.in.yahoo.com>
References: <20050331113407.45242.qmail@web8406.mail.in.yahoo.com>
Message-ID: <8a0c3678050331045054b2ae2c@mail.gmail.com>

>   
> I want any simulator that i can use as virtual machine to test my romimage
> without burning it in to actual chip. 
>   
> I there is any  such software or alternative . 

Not really.  Doing this is very difficult.  Since to have an emulator
up and running you already have chips that have been initialized and
in a lot of cases you can't tell if your code really did what it was
suppoed to do.

You might want to look at bochs or vmware both of those packages can
be fed a bios image.   But I don't think they will be that useful for
the chip init phase of things.

Burning flashes is just one of the things you have to accept in the
BIOS developement world.
A good ROM emulator helps a _lot_ but only if you have a board that
has a replaceable flash.

-- 
Richard A. Smith



From okajima at digitalinfra.co.jp  Thu Mar 31 19:08:31 2005
From: okajima at digitalinfra.co.jp (Jun OKAJIMA)
Date: Fri, 01 Apr 2005 02:08:31 +0900
Subject: [LinuxBIOS] USB 2.0 booting
Message-ID: <200503311708.AA00042@bbb-jz5c7z9hn9y.digitalinfra.co.jp>



Hello Linux BIOS developers.

As far as I understand, current Linux BIOS does not boot from USB memory
stick if it is USB 2.0, Right?. But, I also understand that EHCI (= USB 2.0)
can also work as UHCI/OHCI( = USB1.1).
Then, if I use a M/B which has EHCI and put USB 2.0 stick to it,
and  put Linux kernel supports EHCI driver there.
And if I boot it with Etherboot/FILO with USB 1.1 support in this case,
can it boot as USB 1.1? and can I switch USB mode to 2.0 after booting?

What I want to do is like this.

1. Boot linux kernel by Etherboot/FILO/USB1.1 from USB stick.
2. Reading Linux kernel itself is slow.
   But after that, it works with 2.0 performance?.

                --- Okajima, Jun. Tokyo, Japan.




From yinghailu at gmail.com  Thu Mar 31 19:30:57 2005
From: yinghailu at gmail.com (yhlu)
Date: Thu, 31 Mar 2005 09:30:57 -0800
Subject: [LinuxBIOS] Re: Athlon64 939
In-Reply-To: <m3ll84i17t.fsf@maxwell.lnxi.com>
References: <3174569B9743D511922F00A0C943142309348D35@TYANWEB>
	<m3ll84i17t.fsf@maxwell.lnxi.com>
Message-ID: <2ea3fae1050331093057b74c6c@mail.gmail.com>

> > >
> > > the code in raminit.c is_opteron will treat my athlon 64
> > > (939) as Opteron too.
> 
> Reflecting on this.  It looks like the test needs to be against
> the brand-id field of cpuid.
> 
even brand-id is the same. I guess We need another MARCO in auto.c....

YH



From yinghailu at gmail.com  Thu Mar 31 19:35:33 2005
From: yinghailu at gmail.com (yhlu)
Date: Thu, 31 Mar 2005 09:35:33 -0800
Subject: [LinuxBIOS] USB 2.0 booting
In-Reply-To: <200503311708.AA00042@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
References: <200503311708.AA00042@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
Message-ID: <2ea3fae10503310935d630893@mail.gmail.com>

It should work as USB 1.1.

I was planning to add USB 2 support FILO in Etherboot.

But in long term FILO and Etherboot will gone, the tiny kernel in
Flash with LinuxBIOS will do everything. The kenel may include every
device that you want.

please look at 
http://www.selenic.com/tiny/

YH




On Fri, 01 Apr 2005 02:08:31 +0900, Jun OKAJIMA
<okajima at digitalinfra.co.jp> wrote:
> 
> 
> Hello Linux BIOS developers.
> 
> As far as I understand, current Linux BIOS does not boot from USB memory
> stick if it is USB 2.0, Right?. But, I also understand that EHCI (= USB 2.0)
> can also work as UHCI/OHCI( = USB1.1).
> Then, if I use a M/B which has EHCI and put USB 2.0 stick to it,
> and  put Linux kernel supports EHCI driver there.
> And if I boot it with Etherboot/FILO with USB 1.1 support in this case,
> can it boot as USB 1.1? and can I switch USB mode to 2.0 after booting?
> 
> What I want to do is like this.
> 
> 1. Boot linux kernel by Etherboot/FILO/USB1.1 from USB stick.
> 2. Reading Linux kernel itself is slow.
>   But after that, it works with 2.0 performance?.
> 
>                --- Okajima, Jun. Tokyo, Japan.
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From yinghailu at gmail.com  Thu Mar 31 19:37:48 2005
From: yinghailu at gmail.com (yhlu)
Date: Thu, 31 Mar 2005 09:37:48 -0800
Subject: [LinuxBIOS] [PATCH 1/2] src/config/Options.lb: Add OEM ROM
	section definitions
In-Reply-To: <8eca059b0503302319785e078f@mail.gmail.com>
References: <8eca059b0503302319785e078f@mail.gmail.com>
Message-ID: <2ea3fae105033109373d319d80@mail.gmail.com>

don't need.

for evey device that need FW or option you can add fw_rom=.... or
rom_address= in Config.lb of src/mainboard.

Also just change ROM_IMAGE_SIZE in section in target Config.lb


On Thu, 31 Mar 2005 15:19:56 +0800, Tao Liu <liutao1980 at gmail.com> wrote:
> Hello,
> 
> this patch adds following options, for the use of OEM ROM section,
> eg: onboard PCI device's BIOS in boot ROM or MAC address saved in boot ROM
> 
> ROM_TOTAL_SIZE: the total size of boot ROM
> ROM_OEM_SIZE: the size of boot ROM used by OEM_ROM section
> ROM_SIZE: the size of boot ROM used by LinuxBIOS
> ROM_OEM_START: OEM_ROM start address
> 
> OEM ROM exists in the low address end of boot ROM, so
> default ROM_OEM_SIZE = 0
> default ROM_SIZE = ROM_TOTAL_SIZE - ROM_OEM_SIZE
> default ROM_OEM_START = 0xffffffff - ROM_TOTAL_SIZE + 1
> 
> OEM devices should know the offset of their data in OEM ROM,
> so they can visit their data at address (ROM_OEM_START + oem_my_data_offset)
> 
> to use OEM ROM, one should define ROM_TOTAL_SIZE and ROM_OEM_SIZE
> in mainboard's Options.lb file.
> 
> this patch won't break mainboards which defines ROM_SIZE and don't mentions
> ROM_TOTAL_SIZE and ROM_OEM_SIZE.
> 
> --- freebios2-20050305-0000-orig/src/config/Options.lb  2005-01-15
> 05:54:16.000000000 +0800
> +++ freebios2-20050305-0000/src/config/Options.lb       2005-03-30
> 20:49:16.000000000 +0800
> @@ -190,11 +190,29 @@
>        export used
>        comment "Default fallback image size"
> end
> -define ROM_SIZE
> +define ROM_TOTAL_SIZE
>        default none
>        format "0x%x"
>        export used
> -       comment "Size of your ROM"
> +       comment "Size of your boot ROM"
> +end
> +define ROM_OEM_SIZE
> +       default 0
> +       format "0x%x"
> +       export used
> +       comment "Size of your ROM used by OEM vendors"
> +end
> +define ROM_OEM_START
> +       default {0xffffffff - ROM_TOTAL_SIZE + 1}
> +       format "0x%x"
> +       export used
> +       comment "OEM ROM start location"
> +end
> +define ROM_SIZE
> +       default {ROM_TOTAL_SIZE - ROM_OEM_SIZE}
> +       format "0x%x"
> +       export used
> +       comment "Size of your ROM used by LinuxBIOS"
> end
> define ROM_IMAGE_SIZE
>        default 65535
> 
> --
> Liu Tao
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From yinghailu at gmail.com  Thu Mar 31 19:40:53 2005
From: yinghailu at gmail.com (yhlu)
Date: Thu, 31 Mar 2005 09:40:53 -0800
Subject: [LinuxBIOS] [PATCH] small fixes
In-Reply-To: <8eca059b05033022304a8eb64@mail.gmail.com>
References: <8eca059b05033022304a8eb64@mail.gmail.com>
Message-ID: <2ea3fae1050331094070af6f56@mail.gmail.com>

you need to use tla to get latest source code.

YH


On Thu, 31 Mar 2005 14:30:06 +0800, Tao Liu <liutao1980 at gmail.com> wrote:
> Hello,
> 
> this patch fixes two small program errors, one is loop condition always true,
> the other is return 1 in void type function.
> 
> --- freebios2-20050305-0000-orig/src/drivers/generic/debug/debug_dev.c  2004-12-11
> 04:50:42.000000000 +0800
> +++ freebios2-20050305-0000/src/drivers/generic/debug/debug_dev.c       2005-03-31
> 13:54:00.000000000 +0800
> @@ -35,9 +35,10 @@
> static void print_pci_regs_all(void)
> {
>         struct device *dev;
> -       unsigned char bus, device, function;
> +       unsigned int bus;
> +       unsigned char device, function;
> 
> -       for(bus=0; bus<=256; bus++) {
> +       for(bus=0; bus<=0xff; bus++) {
>                for(device=0; device<=0x1f; device++) {
>                        for (function=0; function<=7; function++){
>                                unsigned devfn;
> --- freebios2-20050305-0000-orig/src/devices/emulator/biosemu.c 2005-01-20
> 07:19:26.000000000 +0800
> +++ freebios2-20050305-0000/src/devices/emulator/biosemu.c      2005-03-31
> 13:24:26.000000000 +0800
> @@ -122,7 +122,8 @@ void do_int(int num)
>        case 0x6D:
>                if (getIntVect(num) == 0x0000) {
>                        printk_debug("un-inited int vector\n");
> -                       return 1;
> +                       //return 1;
> +                       ret = 1;
>                }
>                if (getIntVect(num) == 0xFF065) {
>                        //ret = int42_handler();
> 
> --
> Liu Tao
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From ollie at lanl.gov  Thu Mar 31 21:10:38 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Thu, 31 Mar 2005 12:10:38 -0700
Subject: [LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC address in linuxbios
In-Reply-To: <8eca059b050330232948f5be4b@mail.gmail.com>
References: <8eca059b050330232948f5be4b@mail.gmail.com>
Message-ID: <1112296238.7035.33.camel@exponential.lanl.gov>

On Thu, 2005-03-31 at 15:29 +0800, Tao Liu wrote:
> Hello,
> 
> this patch sets 8111NIC's mac. The 48-bit mac address is saved in OEM ROM,
> in nic_init() the driver gets the mac address through register oem_mac_offset,
> and copy it to 8111NIC's PADR register.
> 
> 

Is it store is it own serial EEPROM or in the same ROM as BIOS? If it 
is  stored in it won EEPROM, this code sould be in the kernel driver 
than BIOS.

Ollie


> diff -Nur freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c
> freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c
> --- freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c	2004-10-21
> 18:44:04.000000000 +0800
> +++ freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c	2005-03-31
> 12:50:56.000000000 +0800
> @@ -6,20 +6,99 @@
>  #include <device/pci.h>
>  #include <device/pci_ids.h>
>  #include <device/pci_ops.h>
> +#include <delay.h>
>  #include "amd8111.h"
>  
> +#undef writel
> +#undef writeb
> +#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val))
> +#define writeb(val,addr) (*(volatile uint8_t *)(addr) = (val))
>  
> +#define CMD3		0x54
> +#define PADR		0x160
> +
> +typedef enum {
> +	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
> +	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
> +	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
> +	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
> +}VAL_BITS;
> +
> +typedef enum {
> +	/* VAL3 */
> +	ASF_INIT_DONE_ALIAS	= (1 << 29),
> +	/* VAL2 */
> +	JUMBO			= (1 << 21),
> +	VSIZE			= (1 << 20),	
> +	VLONLY			= (1 << 19),
> +	VL_TAG_DEL		= (1 << 18),	
> +	/* VAL1 */
> +	EN_PMGR			= (1 << 14),			
> +	INTLEVEL		= (1 << 13),
> +	FORCE_FULL_DUPLEX	= (1 << 12),	
> +	FORCE_LINK_STATUS	= (1 << 11),	
> +	APEP			= (1 << 10),	
> +	MPPLBA			= (1 << 9),	
> +	/* VAL0 */
> +	RESET_PHY_PULSE		= (1 << 2),	
> +	RESET_PHY		= (1 << 1),	
> +	PHY_RST_POL		= (1 << 0),	
> +}CMD3_BITS;
> +
> +static void nic_init(struct device *dev)
> +{
> +	struct southbridge_amd_amd8111_config *conf;
> +	struct resource *resource;
> +	void *mmio;
> +	unsigned char *oem_mac_addr;
> +	int i;
> +
> +	conf = dev->chip_info;
> +	resource = find_resource(dev, PCI_BASE_ADDRESS_0);
> +	mmio = (void *)(unsigned long)resource->base;
> +
> +	/* Hard Reset PHY */
> +	printk_debug("Reseting PHY... ");
> +	if (conf->phy_lowreset) {
> +		writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3);
> +	} else {
> +		writel(VAL0 | RESET_PHY, mmio + CMD3);
> +	}
> +	mdelay(15);
> +	writel(RESET_PHY, mmio + CMD3);
> +	printk_debug("Done\n");
> +
> +	/* Set MAC address */
> +	printk_debug("Mac Addr ");
> +	oem_mac_addr = (unsigned char *)(ROM_OEM_START + conf->oem_mac_offset);
> +	for (i = 0; i < 6; i++) {
> +		printk_debug("%02X%c", oem_mac_addr[i], i == 5 ? '\n' : ':');
> +		writeb(oem_mac_addr[i], mmio + PADR + i);
> +	}
> +}
> +
> +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
> +{
> +	pci_write_config32(dev, 0xc8,
> +		((device & 0xffff) << 16) | (vendor & 0xffff));
> +}
> +
> +static struct pci_operations lops_pci = {
> +	.set_subsystem = lpci_set_subsystem,
> +};
> +	
>  static struct device_operations nic_ops  = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
> -	.enable           = amd8111_enable,
> -	.init             = 0,
> +	.init		  = nic_init,
>  	.scan_bus         = 0,
> +	.enable		  = amd8111_enable,
> +	.ops_pci	  = &lops_pci,
>  };
>  
>  static struct pci_driver nic_driver __pci_driver = {
>  	.ops    = &nic_ops,
>  	.vendor = PCI_VENDOR_ID_AMD,
> -	.device = 0x7462,
> +	.device = PCI_DEVICE_ID_AMD_8111_NIC,
>  };
> diff -Nur freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h
> freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h
> --- freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h	2004-10-21
> 18:44:04.000000000 +0800
> +++ freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h	2005-03-31
> 12:49:32.000000000 +0800
> @@ -5,6 +5,8 @@
>  {
>  	unsigned int ide0_enable : 1;
>  	unsigned int ide1_enable : 1;
> +	unsigned int phy_lowreset : 1;
> +	unsigned long oem_mac_offset;
>  };
>  
>  struct chip_operations;
> 
> 
-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From tony_cheng at pcmagic.net  Thu Mar 31 21:24:39 2005
From: tony_cheng at pcmagic.net (Tony Cheng)
Date: Thu, 31 Mar 2005 11:24:39 -0800
Subject: [LinuxBIOS] Mount linux elf image for netboot as loop device
References: <01fc01c535a2$cfb050e0$919814ac@trans.corp>
	<56bd62b916377fb95572145d6833a3bb@gnat.ca>
Message-ID: <020601c53627$48a64d90$919814ac@trans.corp>

The mkelfImage would package initrd with the kernal. does the mount it as a
loop device would allow user to take look what's in there?

If mount as loop device would not work, do you think there is a way to look
what's in the elf image after it has been made?

Thanks

Tony


----- Original Message ----- 
From: "Nathanael Noblet" <nathanael at gnat.ca>
To: "Tony Cheng" <tony_cheng at pcmagic.net>
Cc: <linuxbios at openbios.org>
Sent: Wednesday, March 30, 2005 7:44 PM
Subject: Re: [LinuxBIOS] Mount linux elf image for netboot as loop device



On Mar 30, 2005, at 7:36 PM, Tony Cheng wrote:

>
> I used mkelfImage to combined Linux Kernel 2.4.20 and initrd into elf
> image for netboot. then I try to use "mount -o loop my_elfImage" to
> mount this image as a loop device. I get a error message like this:

mkelfimage doesn't make a filesystem as far as I know, and only puts
the kernel into a format that the linuxbios expects to find so it can
load it into ram and jump to it. What you are asking to do is about as
the same as mounting a compiled program as a filesystem. You can't do
'mount -o loop /bin/bash /mnt/loop' anymore then you can mount the
kernel file.

-- 
Nathanael D. Noblet
Gnat Solutions
204 - 131 Gorge Road E
Victoria, BC V9A 1L1

T 250.385.4613
C 250.893.4613
http://www.gnat.ca/







From YhLu at tyan.com  Thu Mar 31 22:04:30 2005
From: YhLu at tyan.com (YhLu)
Date: Thu, 31 Mar 2005 12:04:30 -0800
Subject: [LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC address in linux bios
Message-ID: <3174569B9743D511922F00A0C943142309348DB5@TYANWEB>

Should be in BIOS.because different MB use different MAC assigned in
Factory.

But in MB design, it should use another SEEPROM to store that. So the BIOS
or NIC get it.

YH 

> -----Original Message-----
> From: Li-Ta Lo [mailto:ollie at lanl.gov] 
> Sent: Thursday, March 31, 2005 11:11 AM
> To: Tao Liu
> Cc: LinuxBIOS
> Subject: Re: [LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC 
> address in linuxbios
> 
> On Thu, 2005-03-31 at 15:29 +0800, Tao Liu wrote:
> > Hello,
> > 
> > this patch sets 8111NIC's mac. The 48-bit mac address is 
> saved in OEM 
> > ROM, in nic_init() the driver gets the mac address through register 
> > oem_mac_offset, and copy it to 8111NIC's PADR register.
> > 
> > 
> 
> Is it store is it own serial EEPROM or in the same ROM as 
> BIOS? If it is  stored in it won EEPROM, this code sould be 
> in the kernel driver than BIOS.
> 
> Ollie
> 
> 
> > diff -Nur 
> > 
> freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c
> > freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c
> > --- 
> freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd81
> 11_nic.c	2004-10-21
> > 18:44:04.000000000 +0800
> > +++ 
> freebios2-20050305-0000/src/southbridge/amd/amd8111/amd811
> 1_nic.c	2005-03-31
> > 12:50:56.000000000 +0800
> > @@ -6,20 +6,99 @@
> >  #include <device/pci.h>
> >  #include <device/pci_ids.h>
> >  #include <device/pci_ops.h>
> > +#include <delay.h>
> >  #include "amd8111.h"
> >  
> > +#undef writel
> > +#undef writeb
> > +#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val)) 
> > +#define writeb(val,addr) (*(volatile uint8_t *)(addr) = (val))
> >  
> > +#define CMD3		0x54
> > +#define PADR		0x160
> > +
> > +typedef enum {
> > +	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
> > +	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
> > +	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
> > +	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
> > +}VAL_BITS;
> > +
> > +typedef enum {
> > +	/* VAL3 */
> > +	ASF_INIT_DONE_ALIAS	= (1 << 29),
> > +	/* VAL2 */
> > +	JUMBO			= (1 << 21),
> > +	VSIZE			= (1 << 20),	
> > +	VLONLY			= (1 << 19),
> > +	VL_TAG_DEL		= (1 << 18),	
> > +	/* VAL1 */
> > +	EN_PMGR			= (1 << 14),			
> > +	INTLEVEL		= (1 << 13),
> > +	FORCE_FULL_DUPLEX	= (1 << 12),	
> > +	FORCE_LINK_STATUS	= (1 << 11),	
> > +	APEP			= (1 << 10),	
> > +	MPPLBA			= (1 << 9),	
> > +	/* VAL0 */
> > +	RESET_PHY_PULSE		= (1 << 2),	
> > +	RESET_PHY		= (1 << 1),	
> > +	PHY_RST_POL		= (1 << 0),	
> > +}CMD3_BITS;
> > +
> > +static void nic_init(struct device *dev) {
> > +	struct southbridge_amd_amd8111_config *conf;
> > +	struct resource *resource;
> > +	void *mmio;
> > +	unsigned char *oem_mac_addr;
> > +	int i;
> > +
> > +	conf = dev->chip_info;
> > +	resource = find_resource(dev, PCI_BASE_ADDRESS_0);
> > +	mmio = (void *)(unsigned long)resource->base;
> > +
> > +	/* Hard Reset PHY */
> > +	printk_debug("Reseting PHY... ");
> > +	if (conf->phy_lowreset) {
> > +		writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3);
> > +	} else {
> > +		writel(VAL0 | RESET_PHY, mmio + CMD3);
> > +	}
> > +	mdelay(15);
> > +	writel(RESET_PHY, mmio + CMD3);
> > +	printk_debug("Done\n");
> > +
> > +	/* Set MAC address */
> > +	printk_debug("Mac Addr ");
> > +	oem_mac_addr = (unsigned char *)(ROM_OEM_START + 
> conf->oem_mac_offset);
> > +	for (i = 0; i < 6; i++) {
> > +		printk_debug("%02X%c", oem_mac_addr[i], i == 5 
> ? '\n' : ':');
> > +		writeb(oem_mac_addr[i], mmio + PADR + i);
> > +	}
> > +}
> > +
> > +static void lpci_set_subsystem(device_t dev, unsigned vendor, 
> > +unsigned device) {
> > +	pci_write_config32(dev, 0xc8,
> > +		((device & 0xffff) << 16) | (vendor & 0xffff)); }
> > +
> > +static struct pci_operations lops_pci = {
> > +	.set_subsystem = lpci_set_subsystem, };
> > +	
> >  static struct device_operations nic_ops  = {
> >  	.read_resources   = pci_dev_read_resources,
> >  	.set_resources    = pci_dev_set_resources,
> >  	.enable_resources = pci_dev_enable_resources,
> > -	.enable           = amd8111_enable,
> > -	.init             = 0,
> > +	.init		  = nic_init,
> >  	.scan_bus         = 0,
> > +	.enable		  = amd8111_enable,
> > +	.ops_pci	  = &lops_pci,
> >  };
> >  
> >  static struct pci_driver nic_driver __pci_driver = {
> >  	.ops    = &nic_ops,
> >  	.vendor = PCI_VENDOR_ID_AMD,
> > -	.device = 0x7462,
> > +	.device = PCI_DEVICE_ID_AMD_8111_NIC,
> >  };
> > diff -Nur 
> > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h
> > freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h
> > --- 
> freebios2-20050305-0000-orig/src/southbridge/amd/amd8111
> /chip.h	2004-10-21
> > 18:44:04.000000000 +0800
> > +++ 
> freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h	
> 2005-03-31
> > 12:49:32.000000000 +0800
> > @@ -5,6 +5,8 @@
> >  {
> >  	unsigned int ide0_enable : 1;
> >  	unsigned int ide1_enable : 1;
> > +	unsigned int phy_lowreset : 1;
> > +	unsigned long oem_mac_offset;
> >  };
> >  
> >  struct chip_operations;
> > 
> > 
> --
> Li-Ta Lo <ollie at lanl.gov>
> Los Alamos National Lab
> 
> 
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