From okajima at digitalinfra.co.jp  Sun May  1 02:44:24 2005
From: okajima at digitalinfra.co.jp (Jun OKAJIMA)
Date: Sun, 01 May 2005 09:44:24 +0900
Subject: [LinuxBIOS] VIA EPIA build
Message-ID: <200505010044.AA00098@bbb-jz5c7z9hn9y.digitalinfra.co.jp>


It would be sure that many guys in this list have succeeded to
build a rom image for VIA EPIA series with both freebios1 and 2.
How you did it?  And what is the difference with my case?

                          --- Okajima.

----------------

Hello Linux BIOS developers.

I have tried to run linuxbios on VIA EPIA-C800 M/B, but failed. I tried
both freebios1 and 2 src trees, but both failed, Sigh. Anyone can help me ?

Source trees:
  freebios-20041019-1200.tar.bz2 
  freebios2-20050305-0000.tar.bz2
     from http://snapshots.linuxbios.org/
in both case, I uses filo/usb from Etherboot 5.4.0 as a payload.


FreeBIOS1:
  I tried with both util/config/epia.conf and epia800.conf, but both failed.
  epia.conf does not run. it shows weird and buggy chars. must be runaway.
  epia800.conf runs. but does not load a payload. just ended up with
  "bad gzip magic numbers" after had execed pc80/ide_* stuff.
  I looked up why epia.conf does not run and found the difference between both
  configurations. it would need these lines to be added, but why?
option BOOT_IDE=1
option IDE_BOOT_DRIVE=0
option ONE_TRACK=63

FreeBIOS2:
  Just did not work. it seems not to work totally, because even VGA sync
  signal does not comes. BTW, how to enable VGA debugging output?
  

                 --- Okajima, Jun. Tokyo, Japan.



From hamish at prodigi.ch  Sun May  1 14:42:04 2005
From: hamish at prodigi.ch (Hamish Guthrie)
Date: Sun, 1 May 2005 14:42:04 +0200
Subject: [LinuxBIOS] Committed GX1 code to V2 tree
Message-ID: <LDEKLCIFJMAFIOPNLICOKEBJEPAA.hamish@prodigi.ch>

I have just finished committing my GX1 code to the V2 tree.

There is still some work to be done (enabling shadow, and a few other odds
and ends). I have tested this with etherboot only, so I have no idea what
FILO will do - maybe someone would like to play with that!

I also added my test target mainboard - this is an eaglelion 5bcm board, and
is in src/mainboard as well as target.

The Eaglelion board I have is a generic PC-style motherboard with the GX1
and cs5530 companion chip on it, as well as an NSC pc97317 super-io. It has
no ethernet controller on-board, but I used a PCI ethernet card plugged into
one of the 2 PCI slots it has.

The SDRAM detection code in this version is robust and detects all the DIMMS
I have been able to throw at it correctly.
--
No virus found in this outgoing message.
Checked by AVG Anti-Virus.
Version: 7.0.308 / Virus Database: 266.11.0 - Release Date: 29.04.2005




From miernik at ffii.org  Mon May  2 10:17:40 2005
From: miernik at ffii.org (Miernik)
Date: Mon, 2 May 2005 10:17:40 +0200
Subject: [LinuxBIOS] Re: recommended motherboard
References: <20050501142532.GA6140@www.wegener-net.de>
	<Pine.LNX.4.58.0505010940530.28790@enigma.lanl.gov>
Message-ID: <20050502081740.E0B.9.NOFFLE@localhost.localdomain.local>

Ronald G. Minnich <rminnich at lanl.gov> wrote:
> tyan right now does a great job of supporting linuxbios, I would look
> at their opteron mobos.

And where is a good place to buy them, if I am in Europe?
Can I just go to a computer shop and say "give me a Tyan motherboard
with Linuxbios"?

What was this about Tyan announcing having Linuxbios for all new
mainboards? Do I remember correctly?

Which is the cheapest Tyan mainboard which runs Linuxbios?

-- 
Miernik             _________________________  xmpp:miernik at amessage.info
___________________/_______________________/      mailto:miernik at ffii.org
                       Save Europe from Software Patents
                http://www.gnu.org/philosophy/savingeurope.html




From sxpert at esitcom.org  Mon May  2 11:11:56 2005
From: sxpert at esitcom.org (Amaury Jacquot)
Date: Mon, 02 May 2005 11:11:56 +0200
Subject: [LinuxBIOS] Re: recommended motherboard
In-Reply-To: <20050502081740.E0B.9.NOFFLE@localhost.localdomain.local>
References: <20050501142532.GA6140@www.wegener-net.de>	<Pine.LNX.4.58.0505010940530.28790@enigma.lanl.gov>
	<20050502081740.E0B.9.NOFFLE@localhost.localdomain.local>
Message-ID: <4275EEDC.3010008@esitcom.org>

Miernik wrote:
> Ronald G. Minnich <rminnich at lanl.gov> wrote:
> 
>>tyan right now does a great job of supporting linuxbios, I would look
>>at their opteron mobos.
> 
> 
> And where is a good place to buy them, if I am in Europe?
> Can I just go to a computer shop and say "give me a Tyan motherboard
> with Linuxbios"?
> 
> What was this about Tyan announcing having Linuxbios for all new
> mainboards? Do I remember correctly?
> 
> Which is the cheapest Tyan mainboard which runs Linuxbios?
> 

check here :
http://www.rue-hardware.com/prix/comparer/101/Cartes-meres/?i1=3&f1=&i2=4&f2=648&i3=5&i4=18&f4=&mq=143&pxmin=0&pxmax=0&od=nom&show=0&nbf=4

my preference would go for a K8W ...



From rminnich at lanl.gov  Mon May  2 16:23:23 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon, 2 May 2005 08:23:23 -0600 (MDT)
Subject: [LinuxBIOS] Re: recommended motherboard
In-Reply-To: <20050502081740.E0B.9.NOFFLE@localhost.localdomain.local>
References: <20050501142532.GA6140@www.wegener-net.de>
	<Pine.LNX.4.58.0505010940530.28790@enigma.lanl.gov>
	<20050502081740.E0B.9.NOFFLE@localhost.localdomain.local>
Message-ID: <Pine.LNX.4.58.0505020823150.31295@enigma.lanl.gov>


talk to charlie ding, cding at tyan.com

ron



From stepan at openbios.org  Mon May  2 16:28:34 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Mon, 2 May 2005 16:28:34 +0200
Subject: [LinuxBIOS] Opteron memclk speed/loading fix
In-Reply-To: <8eca059b050430020113eaa087@mail.gmail.com>
References: <8eca059b050430020113eaa087@mail.gmail.com>
Message-ID: <20050502142834.GA3794@openbios.org>

* Tao Liu <liutao1980 at gmail.com> [050430 11:01]:
> Hello,
> 
> the following patch fixes memclk selection on different loadings for opteron,
> it is useful if you have more than 4dimms for one opteron cpu. 
 
Was someone able to test this on a couple of systems? Should it be
commited to the repository?

Stefan



From YhLu at tyan.com  Mon May  2 19:35:35 2005
From: YhLu at tyan.com (YhLu)
Date: Mon, 2 May 2005 10:35:35 -0700 
Subject: [LinuxBIOS] Opteron memclk speed/loading fix
Message-ID: <3174569B9743D511922F00A0C943142309B07BC8@TYANWEB>

memory speed downgrade is only need if you have 
8 dimm 4g installed with 400Mhz, and it should be set to 266Mhz..... 
8 dimm 2g installed with 400Mhz, and it should be set to 333Mhz..... 

Do we have such MB to be supportd except 4 rank dimm?

YH

> -----Original Message-----
> From: Stefan Reinauer [mailto:stepan at openbios.org] 
> Sent: Monday, May 02, 2005 7:29 AM
> To: Tao Liu
> Cc: LinuxBIOS
> Subject: Re: [LinuxBIOS] Opteron memclk speed/loading fix
> 
> * Tao Liu <liutao1980 at gmail.com> [050430 11:01]:
> > Hello,
> > 
> > the following patch fixes memclk selection on different 
> loadings for 
> > opteron, it is useful if you have more than 4dimms for one 
> opteron cpu.
>  
> Was someone able to test this on a couple of systems? Should 
> it be commited to the repository?
> 
> Stefan
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From okajima at digitalinfra.co.jp  Mon May  2 22:03:14 2005
From: okajima at digitalinfra.co.jp (Jun OKAJIMA)
Date: Tue, 03 May 2005 05:03:14 +0900
Subject: [LinuxBIOS] VIA EPIA build
Message-ID: <200505022003.AA00099@bbb-jz5c7z9hn9y.digitalinfra.co.jp>



Dont you have any suggestion?


---------------

It would be sure that many guys in this list have succeeded to
build a rom image for VIA EPIA series with both freebios1 and 2.
How you did it?  And what is the difference with my case?

                          --- Okajima.

----------------

Hello Linux BIOS developers.

I have tried to run linuxbios on VIA EPIA-C800 M/B, but failed. I tried
both freebios1 and 2 src trees, but both failed, Sigh. Anyone can help me ?

Source trees:
  freebios-20041019-1200.tar.bz2 
  freebios2-20050305-0000.tar.bz2
     from http://snapshots.linuxbios.org/
in both case, I uses filo/usb from Etherboot 5.4.0 as a payload.


FreeBIOS1:
  I tried with both util/config/epia.conf and epia800.conf, but both failed.
  epia.conf does not run. it shows weird and buggy chars. must be runaway.
  epia800.conf runs. but does not load a payload. just ended up with
  "bad gzip magic numbers" after had execed pc80/ide_* stuff.
  I looked up why epia.conf does not run and found the difference between both
  configurations. it would need these lines to be added, but why?
option BOOT_IDE=1
option IDE_BOOT_DRIVE=0
option ONE_TRACK=63

FreeBIOS2:
  Just did not work. it seems not to work totally, because even VGA sync
  signal does not comes. BTW, how to enable VGA debugging output?
  

                 --- Okajima, Jun. Tokyo, Japan.



From stuge-linuxbios at cdy.org  Mon May  2 22:17:50 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Mon, 2 May 2005 22:17:50 +0200
Subject: [LinuxBIOS] VIA EPIA build
In-Reply-To: <200505022003.AA00099@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
References: <200505022003.AA00099@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
Message-ID: <20050502201750.GA30998@foo.birdnet.se>

On Tue, May 03, 2005 at 05:03:14AM +0900, Jun OKAJIMA wrote:
> FreeBIOS1:
>   I tried with both util/config/epia.conf and epia800.conf, but
> both failed.
>   epia.conf does not run. it shows weird and buggy chars. must be
> runaway.

I don't think so. Try changing the serial port speed in the terminal
program, first try half the speed and if that doesn't work try
experimenting. I seem to recall that the EPIA builds had a problem
with serial port init and that made the port run at 57600 instead of
115200.


>   epia800.conf runs. but does not load a payload. just ended up with
>   "bad gzip magic numbers" after had execed pc80/ide_* stuff.

Same for all payloads? I guess there's a problem with RAM then.


> FreeBIOS2:
>   Just did not work. it seems not to work totally, because even VGA
> sync signal does not comes. BTW, how to enable VGA debugging output?

Initializing VGA is very complex and the code for bringing VGA up in
LinuxBIOS has not been around for too long. I suggest you experiment
further with the v2 code, v1 is no longer developed and unsupported,
and stick to the serial console.


//Peter



From rminnich at lanl.gov  Mon May  2 23:02:26 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon, 2 May 2005 15:02:26 -0600 (MDT)
Subject: [LinuxBIOS] VIA EPIA build
In-Reply-To: <200505022003.AA00099@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
References: <200505022003.AA00099@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
Message-ID: <Pine.LNX.4.58.0505021502090.31295@enigma.lanl.gov>



On Tue, 3 May 2005, Jun OKAJIMA wrote:

> 
> 
> Dont you have any suggestion?

you will have to give us a few more days, we have a new guy doing EPIA and 
I think he will make it go.

ron



From stepan at openbios.org  Tue May  3 13:59:32 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Tue, 3 May 2005 13:59:32 +0200
Subject: [LinuxBIOS] Re: Compiling Digitallogic/adl855pc
In-Reply-To: <20050429215837.GB12494@openbios.org>
References: <3174569B9743D511922F00A0C943142309B07A16@TYANWEB>
	<8a0c367805042814191ca1095d@mail.gmail.com>
	<Pine.LNX.4.58.0504281534370.20199@enigma.lanl.gov>
	<20050429215837.GB12494@openbios.org>
Message-ID: <20050503115932.GA781@openbios.org>

* Stefan Reinauer <stepan at openbios.org> [050429 23:58]:
> * Ronald G. Minnich <rminnich at lanl.gov> [050428 23:34]:
> > > Also wasn't there some sort of autobuild thing that was setup to check
> > > for compile regressions in the tree?  Is that still active?
> > 
> > stepan had that going, don't know status.
> 
> It's still running on the obsolete cvs tree. I'm going to switch it asap
 
http://snapshots.linuxbios.org/ is up and running with the tla tree and
now provides a link to the autobuild log of each release.

Stefan





From lje at kontron.dk  Wed May  4 12:41:40 2005
From: lje at kontron.dk (Lasse Jensen)
Date: Wed, 4 May 2005 12:41:40 +0200 
Subject: [LinuxBIOS] Re: Compiling Digitallogic/adl855pc
Message-ID: <E3AA489882EF484F9BD56AFD9B4227DE19B4C5@INSIDE01>

Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64)
  Creating config file... ok
  Creating builddir...ok
  Compiling image ..ok.

Hmmm its NOT amd64 here, its Pentium-M. but the problem is that I still cant
build it :(

What distubution and/or addons do you use to compile this:
freebios--devel--2.0--patch-29.tar.bz2

Im have tried on 3 versions not, and it would still not compile...
any ideas? How does the autobuild work?

/Lasse

-----Original Message-----
From: Stefan Reinauer [mailto:stepan at openbios.org] 
Sent: 3. maj 2005 14:00
To: Ronald G. Minnich
Cc: linuxbios at openbios.org
Subject: Re: [LinuxBIOS] Re: Compiling Digitallogic/adl855pc

* Stefan Reinauer <stepan at openbios.org> [050429 23:58]:
> * Ronald G. Minnich <rminnich at lanl.gov> [050428 23:34]:
> > > Also wasn't there some sort of autobuild thing that was setup to check
> > > for compile regressions in the tree?  Is that still active?
> > 
> > stepan had that going, don't know status.
> 
> It's still running on the obsolete cvs tree. I'm going to switch it asap
 
http://snapshots.linuxbios.org/ is up and running with the tla tree and
now provides a link to the autobuild log of each release.

Stefan



_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios
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From stepan at openbios.org  Wed May  4 13:22:15 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Wed, 4 May 2005 13:22:15 +0200
Subject: [LinuxBIOS] Re: Compiling Digitallogic/adl855pc
In-Reply-To: <E3AA489882EF484F9BD56AFD9B4227DE19B4C5@INSIDE01>
References: <E3AA489882EF484F9BD56AFD9B4227DE19B4C5@INSIDE01>
Message-ID: <20050504112215.GA29048@openbios.org>

* Lasse Jensen <lje at kontron.dk> [050504 12:41]:
> What distubution and/or addons do you use to compile this:
> freebios--devel--2.0--patch-29.tar.bz2

SUSE 9.2
$ rpm -q binutils gcc python
binutils-2.15.91.0.2-7
gcc-3.3.4-11
python-2.3.4-3.2

> Im have tried on 3 versions not, and it would still not compile...
> any ideas? How does the autobuild work?

it's the script in utils/abuild





From liutao1980 at gmail.com  Fri May  6 13:35:39 2005
From: liutao1980 at gmail.com (Tao Liu)
Date: Fri, 6 May 2005 19:35:39 +0800
Subject: [LinuxBIOS] Opteron memclk speed/loading fix
In-Reply-To: <3174569B9743D511922F00A0C943142309B07BC8@TYANWEB>
References: <3174569B9743D511922F00A0C943142309B07BC8@TYANWEB>
Message-ID: <8eca059b05050604356b6b653@mail.gmail.com>

Hello,

we are building an 1 cpu 8 dimm board and experienced this problem,
and accroding to amd's amd64 bios developers' guide memory speed
downgrade should also be applyed to the following 4dimm configurations:

(1)  4 dimm with more than 2 double-rank dimms, downgrade to 333MHz
(2)  more than 1 double-rank dimm for single channel, downgrade to 333MHz

Tao

On 5/3/05, YhLu <YhLu at tyan.com> wrote:
> memory speed downgrade is only need if you have
> 8 dimm 4g installed with 400Mhz, and it should be set to 266Mhz.....
> 8 dimm 2g installed with 400Mhz, and it should be set to 333Mhz.....
> 
> Do we have such MB to be supportd except 4 rank dimm?
> 
> YH



From ebiederman at lnxi.com  Fri May  6 16:55:20 2005
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: 06 May 2005 08:55:20 -0600
Subject: [LinuxBIOS] Opteron memclk speed/loading fix
In-Reply-To: <8eca059b05050604356b6b653@mail.gmail.com>
References: <3174569B9743D511922F00A0C943142309B07BC8@TYANWEB>
	<8eca059b05050604356b6b653@mail.gmail.com>
Message-ID: <m3psw4l7zb.fsf@maxwell.lnxi.com>

Tao Liu <liutao1980 at gmail.com> writes:

> Hello,
> 
> we are building an 1 cpu 8 dimm board and experienced this problem,
> and accroding to amd's amd64 bios developers' guide memory speed
> downgrade should also be applyed to the following 4dimm configurations:
> 
> (1)  4 dimm with more than 2 double-rank dimms, downgrade to 333MHz
> (2)  more than 1 double-rank dimm for single channel, downgrade to 333MHz

In principle I agree with this.  However those are guidelines and it
stated that the actual details may very per motherboard.

So for merging I would request we have a generic function that
performs this logic,  and have the generic call in raminit.c
make a motherboard specific call.  By default that motherboard
specific call would simply call the default generic method,
but a motherboard that has better memory stability could override
this.

Eric



From YhLu at tyan.com  Fri May  6 19:04:47 2005
From: YhLu at tyan.com (YhLu)
Date: Fri, 6 May 2005 10:04:47 -0700 
Subject: [LinuxBIOS] Opteron memclk speed/loading fix
Message-ID: <3174569B9743D511922F00A0C943142309B08014@TYANWEB>

That's right.

Some MB can work with 4G 4 ranks DIMM in 400Mhz in 4 slots. 

YH

> -----Original Message-----
> From: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
> Sent: Friday, May 06, 2005 7:55 AM
> To: Tao Liu
> Cc: YhLu; LinuxBIOS
> Subject: Re: [LinuxBIOS] Opteron memclk speed/loading fix
> 
> Tao Liu <liutao1980 at gmail.com> writes:
> 
> > Hello,
> > 
> > we are building an 1 cpu 8 dimm board and experienced this problem, 
> > and accroding to amd's amd64 bios developers' guide memory speed 
> > downgrade should also be applyed to the following 4dimm 
> configurations:
> > 
> > (1)  4 dimm with more than 2 double-rank dimms, downgrade to 333MHz
> > (2)  more than 1 double-rank dimm for single channel, downgrade to 
> > 333MHz
> 
> In principle I agree with this.  However those are guidelines 
> and it stated that the actual details may very per motherboard.
> 
> So for merging I would request we have a generic function 
> that performs this logic,  and have the generic call in 
> raminit.c make a motherboard specific call.  By default that 
> motherboard specific call would simply call the default 
> generic method, but a motherboard that has better memory 
> stability could override this.
> 
> Eric
> 



From bari at onelabs.com  Sat May  7 00:18:00 2005
From: bari at onelabs.com (Bari Ari)
Date: Fri, 06 May 2005 17:18:00 -0500
Subject: [LinuxBIOS] ISA, PCI and Mini-PCI POST Cards
Message-ID: <427BED18.9020909@onelabs.com>

Here's an inexpensive source for POST Cards:

  http://www.elstonsystems.com/prod/pc_analyzer.html
  http://shopv2.elstonsystems.com/product_info.php/products_id/57

The supplier ships real fast, they work great and they are very low 
cost. The ISA/PCI version is only $18 US, and the Mini-PCI version is 
$30 US.

-Bari



From svante.signell at telia.com  Sun May  8 23:34:51 2005
From: svante.signell at telia.com (Svante Signell)
Date: Sun, 08 May 2005 23:34:51 +0200
Subject: [LinuxBIOS] RE: DiskOnChip and PLCC32 packages
In-Reply-To: <Pine.LNX.4.58.0504271111190.17519@enigma.lanl.gov>
References: <LDEKLCIFJMAFIOPNLICOGEIKEOAA.hamish@prodigi.ch>
	<1114605748.14393.30.camel@circle.hypercube>
	<Pine.LNX.4.58.0504271111190.17519@enigma.lanl.gov>
Message-ID: <1115588091.5063.4.camel@em2.my.own.domain>

On Wed, 2005-04-27 at 11:11 -0600, Ronald G. Minnich wrote:
> 
> On Wed, 27 Apr 2005, Seb James wrote:
> 
> > Great. Would LILO also function as a payload for LinuxBIOS?
> 
> no. LILO makes bios calls. Sorry :-(
> 
> Use FILO!
What about grub legacy and grub 2?



From talbotx at comcast.net  Mon May  9 22:03:46 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Mon, 9 May 2005 13:03:46 -0700
Subject: [LinuxBIOS] Re: Build error on the EPIA-M
References: <200505091403.AA00104@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
Message-ID: <007501c554d2$35a888b0$c501a8c0@newflame>

-Okajima
I have see not played with the fast boot stuff from VIA.

I had that error before.  It is because of a rebuilding of Linux BIOS's 
config structure.  Go look at the configs for the Tyan boards, most of those 
are up to date.  As of last week the EPIA-MII is still broken.  The 
southbridge is not working, yet.  I hope to see a few in the next few days.

USB and CF are the same speed. Keep in mind that USB has more over head. 
They are both based of the same technology.  The current fastest Flash chips 
on the market are moving at 20MB/sec.  I have see these in both USB and CF. 
I have an Sandisk Extream III 1GB CF that moves at 20MB/sec.

I have my 1GB CF pluged into my EPIA-MII throught the IDE bus. I use that 
for about half of my linux system and my hibernation file.  I like the speed 
it gives.  The CF also does not have a spin up time.  If I/we can get 
Linuxbios working... The system will be powered up and done with linux bios 
befor the disk will be done spining up, CF does not have this issue.
Hope this help
-Adam Talbot

----- Original Message ----- 
From: "Jun OKAJIMA" <okajima at digitalinfra.co.jp>
To: <talbotx at comcast.net>
Sent: Monday, May 09, 2005 7:03 AM
Subject: Build error on the EPIA-M


>
>
> BTW, you have interest in a fast booting? Me too.
> I tried fastboot util from VIA on EPIA-MII, but it does not work.
> You have succeeded to run it?
>
> One impression about your discussion on the ML is,
> Why you stick to CF card? USB 2.0 memory is generally cheaper,
> and sometimes faster. My USB memory can be read at about 20MB/sec.
> Or if you have trouble on driver stuff, use DOM (disk on module).
>
>                         ---- Okajima.
>
> ----------------
>
> Hello.
>
> I have gotten same problem. I hope you give me any advice
> if you already have solved it.
>
>                    ---- Okajima, Jun. Tokyo, Japan.
>
>
> From Linux BIOS ML.
> ------------
> build_dir=via/epia-m/epia-m
> Trying to find one of TARGET on line 4:
>>  loadoptions
>>  ^
> List of nearby tokens:
> ===> ERROR: Could not parse file
> via/epia-m/Config.lb:0
> 





From liutao1980 at gmail.com  Tue May 10 11:56:18 2005
From: liutao1980 at gmail.com (Tao Liu)
Date: Tue, 10 May 2005 17:56:18 +0800
Subject: [LinuxBIOS] Opteron memclk speed/loading fix
In-Reply-To: <m3psw4l7zb.fsf@maxwell.lnxi.com>
References: <3174569B9743D511922F00A0C943142309B07BC8@TYANWEB>
	<8eca059b05050604356b6b653@mail.gmail.com>
	<m3psw4l7zb.fsf@maxwell.lnxi.com>
Message-ID: <8eca059b050510025622e38d42@mail.gmail.com>

On 06 May 2005 08:55:20 -0600, Eric W. Biederman <ebiederman at lnxi.com> wrote:
> In principle I agree with this.  However those are guidelines and it
> stated that the actual details may very per motherboard.
> 
> So for merging I would request we have a generic function that
> performs this logic,  and have the generic call in raminit.c
> make a motherboard specific call.  By default that motherboard
> specific call would simply call the default generic method,
> but a motherboard that has better memory stability could override
> this.
> 
> Eric

I think we can create a mem speed table for each mem controller,
the table has 5 columns:
    dimms,  how many dimms max for this configuration  
    1rank,  how many 1rank dimms max for this configuration
    2rank,  ....
    4rank,  ....
    speed,  the max speed for this configuration

so for a normal mainboard the table should be:
dimms,  1rank,  2rank,  4rank,  speed
8,  8,  8,  8,  333
4,  4,  4,  4,  333
4,  4,  2,  0,  400
4,  4,  0,  2,  400
0,  0,  0,  0,  0  (the end)

and for a mainboard can work with 4 4rank dimms the table maybe:
dimms,  1rank,  2rank,  4rank,  speed
8,  8,  8,  8,  333
4,  4,  4,  4,  400 
0,  0,  0,  0,  0  (the end)

in raminit.c we analyse this table and get the max speed for each
mem controller of this mainboard. for single channel case we divide
the first four column values by 2 and get the correct configuration.
I don't know whether there are 3rank dimms, if yes maybe we should
have the 3rank column.

Tao



From liutao1980 at gmail.com  Wed May 11 11:11:22 2005
From: liutao1980 at gmail.com (Tao Liu)
Date: Wed, 11 May 2005 17:11:22 +0800
Subject: [LinuxBIOS] Opteron memclk speed/loading fix
In-Reply-To: <8eca059b050510025622e38d42@mail.gmail.com>
References: <3174569B9743D511922F00A0C943142309B07BC8@TYANWEB>
	<8eca059b05050604356b6b653@mail.gmail.com>
	<m3psw4l7zb.fsf@maxwell.lnxi.com>
	<8eca059b050510025622e38d42@mail.gmail.com>
Message-ID: <8eca059b0505110211362c09c3@mail.gmail.com>

Hello,

attached is the patch which implements the mem speed table,
mainboards describe it's mem speed ability in mem_controller structure
as the following example:

	static const struct mem_controller cpu[] = {
		{
			.node_id = 0,
			.f0 = PCI_DEV(0, 0x18, 0),
			.f1 = PCI_DEV(0, 0x18, 1),
			.f2 = PCI_DEV(0, 0x18, 2),
			.f3 = PCI_DEV(0, 0x18, 3),
			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, (0xa<<3)|4, (0xa<<3)|6 },
			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, (0xa<<3)|5, (0xa<<3)|7 },
			.memclk_conf = {
				{4, 4, 2, 0, 0, 200},	/* 200M for:  4x1rank,  2x1rank + 2x2rank, etc */
				{4, 4, 0, 2, 0, 200},
				{4, 4, 0, 0, 2, 200},
				{8, 8, 8, 8, 8, 166},	/* 166M for other case */
				{0, 0, 0, 0, 0, 0},	/* the end */
			}
		},
	};

Tao
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From miernik at ffii.org  Wed May 11 12:13:09 2005
From: miernik at ffii.org (Miernik)
Date: Wed, 11 May 2005 12:13:09 +0200
Subject: [LinuxBIOS] Re: recommended motherboard
References: <20050501142532.GA6140@www.wegener-net.de>
	<Pine.LNX.4.58.0505010940530.28790@enigma.lanl.gov>
	<20050502081740.E0B.9.NOFFLE@localhost.localdomain.local>
	<Pine.LNX.4.58.0505020823150.31295@enigma.lanl.gov>
Message-ID: <20050511101309.E4F.4.NOFFLE@localhost.localdomain.local>

Ronald G. Minnich <rminnich at lanl.gov> wrote:
> 
> talk to charlie ding, cding at tyan.com

I mailed him Tue, 3 May 2005 10:42:45 +0200 but still no answer. 

-- 
Miernik             _________________________  xmpp:miernik at amessage.info
___________________/_______________________/      mailto:miernik at ffii.org
Protect Europe from a legal disaster. Petition against software patents
http://www.noepatents.org/index_html?LANG=en




From yinghailu at gmail.com  Wed May 11 18:47:33 2005
From: yinghailu at gmail.com (yhlu)
Date: Wed, 11 May 2005 09:47:33 -0700
Subject: [LinuxBIOS] Re: recommended motherboard
In-Reply-To: <20050511101309.E4F.4.NOFFLE@localhost.localdomain.local>
References: <20050501142532.GA6140@www.wegener-net.de>
	<Pine.LNX.4.58.0505010940530.28790@enigma.lanl.gov>
	<20050502081740.E0B.9.NOFFLE@localhost.localdomain.local>
	<Pine.LNX.4.58.0505020823150.31295@enigma.lanl.gov>
	<20050511101309.E4F.4.NOFFLE@localhost.localdomain.local>
Message-ID: <2ea3fae105051109477030b3b5@mail.gmail.com>

I will let him talk to you today.

YH

On 5/11/05, Miernik <miernik at ffii.org> wrote:
> Ronald G. Minnich <rminnich at lanl.gov> wrote:
> >
> > talk to charlie ding, cding at tyan.com
> 
> I mailed him Tue, 3 May 2005 10:42:45 +0200 but still no answer.
> 
> --
> Miernik             _________________________  xmpp:miernik at amessage.info
> ___________________/_______________________/      mailto:miernik at ffii.org
> Protect Europe from a legal disaster. Petition against software patents
> http://www.noepatents.org/index_html?LANG=en
> 
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From YhLu at tyan.com  Wed May 11 20:21:03 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 11 May 2005 11:21:03 -0700
Subject: [LinuxBIOS] About Nvidia chipset support
Message-ID: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>

All,

Finally I get the approval for releasing Nvidia chipset support for Ck804. I
hope end user to press nvidia to release more info to make sata and on die
lan work.

The problem my code is messed up dual core support etc. I need some time to
split them up.

I will commit soon about
Nvidia CK804 support
smbus bus number support (to handle multi sumbus and mux)
superio smsc 47 support
Tyan S2895/S2891/S2892 support
flash_rom Ck804 support

maybe two months later after AMD issue auth letter or put dual core on
public

AMD D0/E0 Opteron new mem mapping support
AMD E Opteron dual core support
AMD E Opteron mem hole support
AMD K8 Four Ranks DIMM support

Regards

YH



From Stephen.Kimball at bench.com  Wed May 11 21:22:30 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed, 11 May 2005 15:22:30 -0400
Subject: [LinuxBIOS] About Nvidia chipset support
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C38@nh-ex01.bench.com>

We are working with nVidia to get approval to release Ck804 support, too.
We have SATA working.  Which peripherals do you have working?

Steve

-----Original Message-----
From: linuxbios-bounces at openbios.org [mailto:linuxbios-bounces at openbios.org] On Behalf Of YhLu
Sent: Wednesday, May 11, 2005 2:21 PM
To: Ronald G. Minnich; ebiederman at lnxi.com; Stefan Reinauer; Li-Ta Lo
Cc: linuxbios at openbios.org
Subject: [LinuxBIOS] About Nvidia chipset support

All,

Finally I get the approval for releasing Nvidia chipset support for Ck804. I
hope end user to press nvidia to release more info to make sata and on die
lan work.

The problem my code is messed up dual core support etc. I need some time to
split them up.

I will commit soon about
Nvidia CK804 support
smbus bus number support (to handle multi sumbus and mux)
superio smsc 47 support
Tyan S2895/S2891/S2892 support
flash_rom Ck804 support

maybe two months later after AMD issue auth letter or put dual core on
public

AMD D0/E0 Opteron new mem mapping support
AMD E Opteron dual core support
AMD E Opteron mem hole support
AMD K8 Four Ranks DIMM support

Regards

YH

_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios



From YhLu at tyan.com  Wed May 11 22:14:34 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 11 May 2005 13:14:34 -0700
Subject: [LinuxBIOS] About Nvidia chipset support
Message-ID: <3174569B9743D511922F00A0C943142309F809B6@TYANWEB>

except sata and ondie lan.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 11, 2005 12:23 PM
> To: YhLu; rminnich at lanl.gov
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] About Nvidia chipset support
> 
> We are working with nVidia to get approval to release Ck804 
> support, too.
> We have SATA working.  Which peripherals do you have working?
> 
> Steve
> 
> -----Original Message-----
> From: linuxbios-bounces at openbios.org 
> [mailto:linuxbios-bounces at openbios.org] On Behalf Of YhLu
> Sent: Wednesday, May 11, 2005 2:21 PM
> To: Ronald G. Minnich; ebiederman at lnxi.com; Stefan Reinauer; Li-Ta Lo
> Cc: linuxbios at openbios.org
> Subject: [LinuxBIOS] About Nvidia chipset support
> 
> All,
> 
> Finally I get the approval for releasing Nvidia chipset 
> support for Ck804. I hope end user to press nvidia to release 
> more info to make sata and on die lan work.
> 
> The problem my code is messed up dual core support etc. I 
> need some time to split them up.
> 
> I will commit soon about
> Nvidia CK804 support
> smbus bus number support (to handle multi sumbus and mux) 
> superio smsc 47 support Tyan S2895/S2891/S2892 support 
> flash_rom Ck804 support
> 
> maybe two months later after AMD issue auth letter or put 
> dual core on public
> 
> AMD D0/E0 Opteron new mem mapping support AMD E Opteron dual 
> core support AMD E Opteron mem hole support AMD K8 Four Ranks 
> DIMM support
> 
> Regards
> 
> YH
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From YhLu at tyan.com  Wed May 11 22:36:26 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 11 May 2005 13:36:26 -0700
Subject: [LinuxBIOS] About Nvidia chipset support
Message-ID: <3174569B9743D511922F00A0C943142309F809BC@TYANWEB>

commited. 

> -----Original Message-----
> From: YhLu 
> Sent: Wednesday, May 11, 2005 11:21 AM
> To: Ronald G. Minnich; ebiederman at lnxi.com; Stefan Reinauer; Li-Ta Lo
> Cc: linuxbios at openbios.org
> Subject: [LinuxBIOS] About Nvidia chipset support
> 
> All,
> 
> Finally I get the approval for releasing Nvidia chipset 
> support for Ck804. I hope end user to press nvidia to release 
> more info to make sata and on die lan work.
> 
> The problem my code is messed up dual core support etc. I 
> need some time to split them up.
> 
> I will commit soon about
> Nvidia CK804 support
> smbus bus number support (to handle multi sumbus and mux) 
> superio smsc 47 support Tyan S2895/S2891/S2892 support 
> flash_rom Ck804 support
> 
> maybe two months later after AMD issue auth letter or put 
> dual core on public
> 
> AMD D0/E0 Opteron new mem mapping support AMD E Opteron dual 
> core support AMD E Opteron mem hole support AMD K8 Four Ranks 
> DIMM support
> 
> Regards
> 
> YH
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From rminnich at lanl.gov  Wed May 11 23:09:16 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed, 11 May 2005 15:09:16 -0600 (MDT)
Subject: [LinuxBIOS] Re: About Nvidia chipset support
In-Reply-To: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
Message-ID: <Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>

great news!

thanks
ron




From talbotx at comcast.net  Thu May 12 02:17:43 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Wed, 11 May 2005 17:17:43 -0700
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
	<Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>
Message-ID: <002501c55688$04acc660$c501a8c0@newflame>

Any one have the current status of the EPIA-M/MII?
-Adam Talbot




From beneo at comcast.net  Thu May 12 03:56:48 2005
From: beneo at comcast.net (beneo)
Date: Wed, 11 May 2005 18:56:48 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
Message-ID: <00e901c55695$dbda7490$131814ac@trans.corp>


I'm playing with the AMD seranede board. The flash_and_burn utility can not program linuxBIOS to the flash. but I can read the linuxbios and save to a file correctly.

If I boot from AMI BIOS, using same utility, I can program a linuxBIOS into the flash. That made me believe some setting by linuxBIOS on the AMD Ref board is not right. I just don't know what.

I used gdb to trace the code, Flash_and_burn utility enables flash by program two AMD Southbridge 8111 registers, One for enable 4MB window to flash (DevB, 0x43), one for enable write to the flash (DevB, 0x40). I checked the AMD datasheet, it seems all it need. But if I boot with LinuxBIOS, the flash erase command has no effect. with AMI BIOS, I can sucessfully erase a sector. 

could anybody give me some pointer on what to check? 

I should add, the linuxBIOS only reports 2GB memory when I really have 4GB in the system. I don't know if this have something to do with my issue.

Thanks 

Beneo
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From YhLu at tyan.com  Thu May 12 04:27:17 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 11 May 2005 19:27:17 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
Message-ID: <3174569B9743D511922F00A0C943142309F80A63@TYANWEB>

what is EEPROM in your BIOS socket?
 
How do you install your DIMM? 4x1G in CPU0?
 
What is your cpu version?
 
YH


  _____  

From: beneo [mailto:beneo at comcast.net] 
Sent: Wednesday, May 11, 2005 6:57 PM
To: linuxbios at openbios.org
Subject: [LinuxBIOS] flash issue with AMD Ref board


 
I'm playing with the AMD seranede board. The flash_and_burn utility can not
program linuxBIOS to the flash. but I can read the linuxbios and save to a
file correctly.
 
If I boot from AMI BIOS, using same utility, I can program a linuxBIOS into
the flash. That made me believe some setting by linuxBIOS on the AMD Ref
board is not right. I just don't know what.
 
I used gdb to trace the code, Flash_and_burn utility enables flash by
program two AMD Southbridge 8111 registers, One for enable 4MB window to
flash (DevB, 0x43), one for enable write to the flash (DevB, 0x40). I
checked the AMD datasheet, it seems all it need. But if I boot with
LinuxBIOS, the flash erase command has no effect. with AMI BIOS, I can
sucessfully erase a sector. 
 
could anybody give me some pointer on what to check? 
 
I should add, the linuxBIOS only reports 2GB memory when I really have 4GB
in the system. I don't know if this have something to do with my issue.
 
Thanks 
 
Beneo
 

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From beneo at comcast.net  Thu May 12 04:14:02 2005
From: beneo at comcast.net (beneo)
Date: Wed, 11 May 2005 19:14:02 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
References: <3174569B9743D511922F00A0C943142309F80A63@TYANWEB>
Message-ID: <010701c55698$449e2600$131814ac@trans.corp>

EEPROM is SST 48LF004.

I install 2GB to CPU0 and 2GB to CPU1. I use 512MB DIMM, 4 DIMM per CPU, so total should be 4GB. But linux command cat /proc/meminfo report one 2 GB when using LinuxBIOS.

I have two opteron CPU, I'm not sure the version though.

thanks

beneo

  ----- Original Message ----- 
  From: YhLu 
  To: beneo ; linuxbios at openbios.org 
  Sent: Wednesday, May 11, 2005 7:27 PM
  Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


  what is EEPROM in your BIOS socket?

  How do you install your DIMM? 4x1G in CPU0?

  What is your cpu version?

  YH



----------------------------------------------------------------------------
    From: beneo [mailto:beneo at comcast.net] 
    Sent: Wednesday, May 11, 2005 6:57 PM
    To: linuxbios at openbios.org
    Subject: [LinuxBIOS] flash issue with AMD Ref board



    I'm playing with the AMD seranede board. The flash_and_burn utility can not program linuxBIOS to the flash. but I can read the linuxbios and save to a file correctly.

    If I boot from AMI BIOS, using same utility, I can program a linuxBIOS into the flash. That made me believe some setting by linuxBIOS on the AMD Ref board is not right. I just don't know what.

    I used gdb to trace the code, Flash_and_burn utility enables flash by program two AMD Southbridge 8111 registers, One for enable 4MB window to flash (DevB, 0x43), one for enable write to the flash (DevB, 0x40). I checked the AMD datasheet, it seems all it need. But if I boot with LinuxBIOS, the flash erase command has no effect. with AMI BIOS, I can sucessfully erase a sector. 

    could anybody give me some pointer on what to check? 

    I should add, the linuxBIOS only reports 2GB memory when I really have 4GB in the system. I don't know if this have something to do with my issue.

    Thanks 

    Beneo



------------------------------------------------------------------------------


  _______________________________________________
  LinuxBIOS mailing list
  LinuxBIOS at openbios.org
  http://www.openbios.org/mailman/listinfo/linuxbios
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From beneo at comcast.net  Thu May 12 04:20:20 2005
From: beneo at comcast.net (beneo)
Date: Wed, 11 May 2005 19:20:20 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
References: <3174569B9743D511922F00A0C943142309F80A63@TYANWEB>
	<010701c55698$449e2600$131814ac@trans.corp>
Message-ID: <012501c55699$25d8d700$131814ac@trans.corp>

YhLu,

EEPOM should be SST 49LF004, sorry. 

I also get the CPU version, it's a print out from cat /proc/cpuinfo. Total two CPU, I put the the second CPU here. 

processor       : 1
vendor_id       : AuthenticAMD
cpu family      : 15
model           : 5
model name      : 02/05
stepping        : 8
cpu MHz         : 1395.089
cache size      : 1024 KB
physical id     : 0
siblings        : 1
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall mmxext l
m 3dnowext 3dnow
bogomips        : 2785.28

Thanks 

Beneo

  ----- Original Message ----- 
  From: beneo 
  To: YhLu ; linuxbios at openbios.org 
  Sent: Wednesday, May 11, 2005 7:14 PM
  Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


  EEPROM is SST 48LF004.

  I install 2GB to CPU0 and 2GB to CPU1. I use 512MB DIMM, 4 DIMM per CPU, so total should be 4GB. But linux command cat /proc/meminfo report one 2 GB when using LinuxBIOS.

  I have two opteron CPU, I'm not sure the version though.

  thanks

  beneo

    ----- Original Message ----- 
    From: YhLu 
    To: beneo ; linuxbios at openbios.org 
    Sent: Wednesday, May 11, 2005 7:27 PM
    Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


    what is EEPROM in your BIOS socket?

    How do you install your DIMM? 4x1G in CPU0?

    What is your cpu version?

    YH



--------------------------------------------------------------------------
      From: beneo [mailto:beneo at comcast.net] 
      Sent: Wednesday, May 11, 2005 6:57 PM
      To: linuxbios at openbios.org
      Subject: [LinuxBIOS] flash issue with AMD Ref board



      I'm playing with the AMD seranede board. The flash_and_burn utility can not program linuxBIOS to the flash. but I can read the linuxbios and save to a file correctly.

      If I boot from AMI BIOS, using same utility, I can program a linuxBIOS into the flash. That made me believe some setting by linuxBIOS on the AMD Ref board is not right. I just don't know what.

      I used gdb to trace the code, Flash_and_burn utility enables flash by program two AMD Southbridge 8111 registers, One for enable 4MB window to flash (DevB, 0x43), one for enable write to the flash (DevB, 0x40). I checked the AMD datasheet, it seems all it need. But if I boot with LinuxBIOS, the flash erase command has no effect. with AMI BIOS, I can sucessfully erase a sector. 

      could anybody give me some pointer on what to check? 

      I should add, the linuxBIOS only reports 2GB memory when I really have 4GB in the system. I don't know if this have something to do with my issue.

      Thanks 

      Beneo



----------------------------------------------------------------------------


    _______________________________________________
    LinuxBIOS mailing list
    LinuxBIOS at openbios.org
    http://www.openbios.org/mailman/listinfo/linuxbios


------------------------------------------------------------------------------


  _______________________________________________
  LinuxBIOS mailing list
  LinuxBIOS at openbios.org
  http://www.openbios.org/mailman/listinfo/linuxbios
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From sxpert at esitcom.org  Thu May 12 16:27:56 2005
From: sxpert at esitcom.org (Amaury Jacquot)
Date: Thu, 12 May 2005 16:27:56 +0200
Subject: [LinuxBIOS] Flashing DELL bioses
Message-ID: <428367EC.8030102@esitcom.org>

kernel module to flash bios on dell servers & client systems (mebbe
laptops too ?)

http://www.ussg.iu.edu/hypermail/linux/kernel/0505.1/0557.html



From rminnich at lanl.gov  Thu May 12 16:35:19 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 12 May 2005 08:35:19 -0600 (MDT)
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
In-Reply-To: <002501c55688$04acc660$c501a8c0@newflame>
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
	<Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>
	<002501c55688$04acc660$c501a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>



On Wed, 11 May 2005, Adam Talbot wrote:

> Any one have the current status of the EPIA-M/MII?

we're building linuxbios here on the EPIA. EPIA-M, well, that is next. 

We're at the point of making sure linux boots fine, and having fun with 
bproc (partly learning curve issues with a new guy, or so I hope ...)

so, we hope to have good news soon. Hamish has done a godo job on geode 
and has ideas on how to improve Epia, so I'm counting on him :-)

ron



From rminnich at lanl.gov  Thu May 12 16:37:13 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 12 May 2005 08:37:13 -0600 (MDT)
Subject: [LinuxBIOS] flash issue with AMD Ref board
In-Reply-To: <00e901c55695$dbda7490$131814ac@trans.corp>
References: <00e901c55695$dbda7490$131814ac@trans.corp>
Message-ID: <Pine.LNX.4.58.0505120837010.4227@enigma.lanl.gov>

possibly amd has additional flash enable hardware. Since this is a ref 
board, is it still sold?

ron




From okajima at digitalinfra.co.jp  Thu May 12 16:47:19 2005
From: okajima at digitalinfra.co.jp (Jun OKAJIMA)
Date: Thu, 12 May 2005 23:47:19 +0900
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
In-Reply-To: <Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
References: <Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
Message-ID: <200505121447.AA00109@bbb-jz5c7z9hn9y.digitalinfra.co.jp>


Hello Mr. Ronald G. Minnch,
and thanks Mr. Adam Talbot for a private mail.

Probably you should have understood already, I also have been
awaiting for coming of the release. TIA, Ron!.


                 --- Okajima, Jun. Tokyo, Japan.


>
>
>On Wed, 11 May 2005, Adam Talbot wrote:
>
>> Any one have the current status of the EPIA-M/MII?
>
>we're building linuxbios here on the EPIA. EPIA-M, well, that is next. 
>
>We're at the point of making sure linux boots fine, and having fun with 
>bproc (partly learning curve issues with a new guy, or so I hope ...)
>
>so, we hope to have good news soon. Hamish has done a godo job on geode 
>and has ideas on how to improve Epia, so I'm counting on him :-)
>
>ron
>
>_______________________________________________
>LinuxBIOS mailing list
>LinuxBIOS at openbios.org
>http://www.openbios.org/mailman/listinfo/linuxbios
>



From rminnich at lanl.gov  Thu May 12 16:51:58 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 12 May 2005 08:51:58 -0600 (MDT)
Subject: [LinuxBIOS] flash issue with AMD Ref board
In-Reply-To: <012501c55699$25d8d700$131814ac@trans.corp>
References: <3174569B9743D511922F00A0C943142309F80A63@TYANWEB>
	<010701c55698$449e2600$131814ac@trans.corp>
	<012501c55699$25d8d700$131814ac@trans.corp>
Message-ID: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov>

the flash problem: this sounds more to me like an enable line that has 
been added for FLASHWR. 

Beneo, do you have a scope? it is often useful to put a scope on the WR 
line and see if it is toggling. 

ron




From rminnich at lanl.gov  Thu May 12 17:08:13 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 12 May 2005 09:08:13 -0600 (MDT)
Subject: [LinuxBIOS] Flashing DELL bioses
In-Reply-To: <428367EC.8030102@esitcom.org>
References: <428367EC.8030102@esitcom.org>
Message-ID: <Pine.LNX.4.58.0505120908040.4227@enigma.lanl.gov>

it's so gross. the bios does the updating of itself. 

bleah.

ron




From YhLu at tyan.com  Thu May 12 18:53:58 2005
From: YhLu at tyan.com (YhLu)
Date: Thu, 12 May 2005 09:53:58 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
Message-ID: <3174569B9743D511922F00A0C943142309F80AA9@TYANWEB>

SST49LF004 or SST49LF040 ?
 
YH


  _____  

From: beneo [mailto:beneo at comcast.net] 
Sent: Wednesday, May 11, 2005 7:20 PM
To: beneo; YhLu; linuxbios at openbios.org
Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


YhLu,
 
EEPOM should be SST 49LF004, sorry. 
 
I also get the CPU version, it's a print out from cat /proc/cpuinfo. Total
two CPU, I put the the second CPU here. 
 
processor       : 1
vendor_id       : AuthenticAMD
cpu family      : 15
model           : 5
model name      : 02/05
stepping        : 8
cpu MHz         : 1395.089
cache size      : 1024 KB
physical id     : 0
siblings        : 1
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 syscall mmxext l
m 3dnowext 3dnow
bogomips        : 2785.28
 
Thanks 
 
Beneo
 

----- Original Message ----- 
From: beneo <mailto:beneo at comcast.net>  
To: YhLu <mailto:YhLu at tyan.com>  ; linuxbios at openbios.org
<mailto:linuxbios at openbios.org>  
Sent: Wednesday, May 11, 2005 7:14 PM
Subject: Re: [LinuxBIOS] flash issue with AMD Ref board

EEPROM is SST 48LF004.
 
I install 2GB to CPU0 and 2GB to CPU1. I use 512MB DIMM, 4 DIMM per CPU, so
total should be 4GB. But linux command cat /proc/meminfo report one 2 GB
when using LinuxBIOS.
 
I have two opteron CPU, I'm not sure the version though.
 
thanks
 
beneo
 

----- Original Message ----- 
From: YhLu <mailto:YhLu at tyan.com>  
To: beneo <mailto:beneo at comcast.net>  ; linuxbios at openbios.org
<mailto:linuxbios at openbios.org>  
Sent: Wednesday, May 11, 2005 7:27 PM
Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


what is EEPROM in your BIOS socket?
 
How do you install your DIMM? 4x1G in CPU0?
 
What is your cpu version?
 
YH


  _____  

From: beneo [mailto:beneo at comcast.net] 
Sent: Wednesday, May 11, 2005 6:57 PM
To: linuxbios at openbios.org <mailto:linuxbios at openbios.org> 
Subject: [LinuxBIOS] flash issue with AMD Ref board


 
I'm playing with the AMD seranede board. The flash_and_burn utility can not
program linuxBIOS to the flash. but I can read the linuxbios and save to a
file correctly.
 
If I boot from AMI BIOS, using same utility, I can program a linuxBIOS into
the flash. That made me believe some setting by linuxBIOS on the AMD Ref
board is not right. I just don't know what.
 
I used gdb to trace the code, Flash_and_burn utility enables flash by
program two AMD Southbridge 8111 registers, One for enable 4MB window to
flash (DevB, 0x43), one for enable write to the flash (DevB, 0x40). I
checked the AMD datasheet, it seems all it need. But if I boot with
LinuxBIOS, the flash erase command has no effect. with AMI BIOS, I can
sucessfully erase a sector. 
 
could anybody give me some pointer on what to check? 
 
I should add, the linuxBIOS only reports 2GB memory when I really have 4GB
in the system. I don't know if this have something to do with my issue.
 
Thanks 
 
Beneo
 



  _____  




_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios



  _____  




_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios

-------------- next part --------------
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From hamish at prodigi.ch  Thu May 12 19:08:54 2005
From: hamish at prodigi.ch (Hamish Guthrie)
Date: Thu, 12 May 2005 19:08:54 +0200
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
In-Reply-To: <Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
Message-ID: <LDEKLCIFJMAFIOPNLICOAELKFAAA.hamish@prodigi.ch>

Ron,

I am progressing on the Geode, quite well in fact, even if I say so myself!
It may be a while before I get solidly into the Epia-M though, so all I
would like to suggest is that if there is anyone else holding back because
they think I may be doing something on the Epia-M - please do not - I have
had a look, but not started anything meaningful yet, though once I have the
Geode licked, I will be moving onto the Epia and Epia-M full-time, and all
of the niceties of the chipsets!

Hamish

> -----Original Message-----
> From: linuxbios-bounces at openbios.org
> [mailto:linuxbios-bounces at openbios.org]On Behalf Of Ronald G. Minnich
> Sent: Donnerstag, 12. Mai 2005 16:35
> To: Adam Talbot
> Cc: linuxbios at openbios.org
> Subject: Re: [LinuxBIOS] Current status of the the EPIA-M/MII
>
>
>
>
> On Wed, 11 May 2005, Adam Talbot wrote:
>
> > Any one have the current status of the EPIA-M/MII?
>
> we're building linuxbios here on the EPIA. EPIA-M, well, that is next.
>
> We're at the point of making sure linux boots fine, and having fun with
> bproc (partly learning curve issues with a new guy, or so I hope ...)
>
> so, we hope to have good news soon. Hamish has done a godo job on geode
> and has ideas on how to improve Epia, so I'm counting on him :-)
>
> ron
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>
> --
> No virus found in this incoming message.
> Checked by AVG Anti-Virus.
> Version: 7.0.308 / Virus Database: 266.11.8 - Release Date: 10.05.2005
>
--
No virus found in this outgoing message.
Checked by AVG Anti-Virus.
Version: 7.0.308 / Virus Database: 266.11.8 - Release Date: 10.05.2005




From beneo at comcast.net  Thu May 12 19:46:02 2005
From: beneo at comcast.net (beneo)
Date: Thu, 12 May 2005 10:46:02 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
References: <3174569B9743D511922F00A0C943142309F80AA9@TYANWEB>
Message-ID: <014601c5571a$76f8f300$131814ac@trans.corp>

It's SST 49LF004. It the replacement for SST49LF040. They use same argorithm to flash. I looked the flash_and_burn utility. That's the case there too. 

beneo.

  ----- Original Message ----- 
  From: YhLu 
  To: beneo ; linuxbios at openbios.org 
  Sent: Thursday, May 12, 2005 9:53 AM
  Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


  SST49LF004 or SST49LF040 ?

  YH



----------------------------------------------------------------------------
    From: beneo [mailto:beneo at comcast.net] 
    Sent: Wednesday, May 11, 2005 7:20 PM
    To: beneo; YhLu; linuxbios at openbios.org
    Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


    YhLu,

    EEPOM should be SST 49LF004, sorry. 

    I also get the CPU version, it's a print out from cat /proc/cpuinfo. Total two CPU, I put the the second CPU here. 

    processor       : 1
    vendor_id       : AuthenticAMD
    cpu family      : 15
    model           : 5
    model name      : 02/05
    stepping        : 8
    cpu MHz         : 1395.089
    cache size      : 1024 KB
    physical id     : 0
    siblings        : 1
    fdiv_bug        : no
    hlt_bug         : no
    f00f_bug        : no
    coma_bug        : no
    fpu             : yes
    fpu_exception   : yes
    cpuid level     : 1
    wp              : yes
    flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall mmxext l
    m 3dnowext 3dnow
    bogomips        : 2785.28

    Thanks 

    Beneo

      ----- Original Message ----- 
      From: beneo 
      To: YhLu ; linuxbios at openbios.org 
      Sent: Wednesday, May 11, 2005 7:14 PM
      Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


      EEPROM is SST 48LF004.

      I install 2GB to CPU0 and 2GB to CPU1. I use 512MB DIMM, 4 DIMM per CPU, so total should be 4GB. But linux command cat /proc/meminfo report one 2 GB when using LinuxBIOS.

      I have two opteron CPU, I'm not sure the version though.

      thanks

      beneo

        ----- Original Message ----- 
        From: YhLu 
        To: beneo ; linuxbios at openbios.org 
        Sent: Wednesday, May 11, 2005 7:27 PM
        Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


        what is EEPROM in your BIOS socket?

        How do you install your DIMM? 4x1G in CPU0?

        What is your cpu version?

        YH



----------------------------------------------------------------------
          From: beneo [mailto:beneo at comcast.net] 
          Sent: Wednesday, May 11, 2005 6:57 PM
          To: linuxbios at openbios.org
          Subject: [LinuxBIOS] flash issue with AMD Ref board



          I'm playing with the AMD seranede board. The flash_and_burn utility can not program linuxBIOS to the flash. but I can read the linuxbios and save to a file correctly.

          If I boot from AMI BIOS, using same utility, I can program a linuxBIOS into the flash. That made me believe some setting by linuxBIOS on the AMD Ref board is not right. I just don't know what.

          I used gdb to trace the code, Flash_and_burn utility enables flash by program two AMD Southbridge 8111 registers, One for enable 4MB window to flash (DevB, 0x43), one for enable write to the flash (DevB, 0x40). I checked the AMD datasheet, it seems all it need. But if I boot with LinuxBIOS, the flash erase command has no effect. with AMI BIOS, I can sucessfully erase a sector. 

          could anybody give me some pointer on what to check? 

          I should add, the linuxBIOS only reports 2GB memory when I really have 4GB in the system. I don't know if this have something to do with my issue.

          Thanks 

          Beneo



------------------------------------------------------------------------


        _______________________________________________
        LinuxBIOS mailing list
        LinuxBIOS at openbios.org
        http://www.openbios.org/mailman/listinfo/linuxbios


--------------------------------------------------------------------------


      _______________________________________________
      LinuxBIOS mailing list
      LinuxBIOS at openbios.org
      http://www.openbios.org/mailman/listinfo/linuxbios


------------------------------------------------------------------------------


  _______________________________________________
  LinuxBIOS mailing list
  LinuxBIOS at openbios.org
  http://www.openbios.org/mailman/listinfo/linuxbios
-------------- next part --------------
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From YhLu at tyan.com  Thu May 12 20:17:31 2005
From: YhLu at tyan.com (YhLu)
Date: Thu, 12 May 2005 11:17:31 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
Message-ID: <3174569B9743D511922F00A0C943142309F80AE9@TYANWEB>

004 only can be use in intel platform. FW hub interface...
 
040 can be used in AMD platform. LPC interface...
 
PMC 004 support two interface...
 
YH


  _____  

From: beneo [mailto:beneo at comcast.net] 
Sent: Thursday, May 12, 2005 10:46 AM
To: YhLu; linuxbios at openbios.org
Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


It's SST 49LF004. It the replacement for SST49LF040. They use same argorithm
to flash. I looked the flash_and_burn utility. That's the case there too. 
 
beneo.
 

----- Original Message ----- 
From: YhLu <mailto:YhLu at tyan.com>  
To: beneo <mailto:beneo at comcast.net>  ; linuxbios at openbios.org
<mailto:linuxbios at openbios.org>  
Sent: Thursday, May 12, 2005 9:53 AM
Subject: RE: [LinuxBIOS] flash issue with AMD Ref board

SST49LF004 or SST49LF040 ?
 
YH


  _____  

From: beneo [mailto:beneo at comcast.net] 
Sent: Wednesday, May 11, 2005 7:20 PM
To: beneo; YhLu; linuxbios at openbios.org <mailto:linuxbios at openbios.org> 
Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


YhLu,
 
EEPOM should be SST 49LF004, sorry. 
 
I also get the CPU version, it's a print out from cat /proc/cpuinfo. Total
two CPU, I put the the second CPU here. 
 
processor       : 1
vendor_id       : AuthenticAMD
cpu family      : 15
model           : 5
model name      : 02/05
stepping        : 8
cpu MHz         : 1395.089
cache size      : 1024 KB
physical id     : 0
siblings        : 1
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 syscall mmxext l
m 3dnowext 3dnow
bogomips        : 2785.28
 
Thanks 
 
Beneo
 

----- Original Message ----- 
From: beneo <mailto:beneo at comcast.net>  
To: YhLu <mailto:YhLu at tyan.com>  ; linuxbios at openbios.org
<mailto:linuxbios at openbios.org>  
Sent: Wednesday, May 11, 2005 7:14 PM
Subject: Re: [LinuxBIOS] flash issue with AMD Ref board

EEPROM is SST 48LF004.
 
I install 2GB to CPU0 and 2GB to CPU1. I use 512MB DIMM, 4 DIMM per CPU, so
total should be 4GB. But linux command cat /proc/meminfo report one 2 GB
when using LinuxBIOS.
 
I have two opteron CPU, I'm not sure the version though.
 
thanks
 
beneo
 

----- Original Message ----- 
From: YhLu <mailto:YhLu at tyan.com>  
To: beneo <mailto:beneo at comcast.net>  ; linuxbios at openbios.org
<mailto:linuxbios at openbios.org>  
Sent: Wednesday, May 11, 2005 7:27 PM
Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


what is EEPROM in your BIOS socket?
 
How do you install your DIMM? 4x1G in CPU0?
 
What is your cpu version?
 
YH


  _____  

From: beneo [mailto:beneo at comcast.net] 
Sent: Wednesday, May 11, 2005 6:57 PM
To: linuxbios at openbios.org <mailto:linuxbios at openbios.org> 
Subject: [LinuxBIOS] flash issue with AMD Ref board


 
I'm playing with the AMD seranede board. The flash_and_burn utility can not
program linuxBIOS to the flash. but I can read the linuxbios and save to a
file correctly.
 
If I boot from AMI BIOS, using same utility, I can program a linuxBIOS into
the flash. That made me believe some setting by linuxBIOS on the AMD Ref
board is not right. I just don't know what.
 
I used gdb to trace the code, Flash_and_burn utility enables flash by
program two AMD Southbridge 8111 registers, One for enable 4MB window to
flash (DevB, 0x43), one for enable write to the flash (DevB, 0x40). I
checked the AMD datasheet, it seems all it need. But if I boot with
LinuxBIOS, the flash erase command has no effect. with AMI BIOS, I can
sucessfully erase a sector. 
 
could anybody give me some pointer on what to check? 
 
I should add, the linuxBIOS only reports 2GB memory when I really have 4GB
in the system. I don't know if this have something to do with my issue.
 
Thanks 
 
Beneo
 



  _____  




_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios



  _____  




_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios



  _____  




_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios

-------------- next part --------------
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From beneo at comcast.net  Thu May 12 19:56:54 2005
From: beneo at comcast.net (beneo)
Date: Thu, 12 May 2005 10:56:54 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
References: <3174569B9743D511922F00A0C943142309F80A63@TYANWEB><010701c55698$449e2600$131814ac@trans.corp><012501c55699$25d8d700$131814ac@trans.corp>
	<Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov>
Message-ID: <014f01c5571b$fdca3c30$131814ac@trans.corp>


Ron,

I was also thinking if the AMD senanade board has some special hardware to
protect eeprom write. but after I tried to boot with AMI BIOS into Linux and
use same flash_and_burn utility to flash LinuxBIOS into the EEPROM
sucessufully, I started to be convienced there are some setup issue within
LinuxBIOS caused this.

I spent sometime to check 8111 southbridge, but I couldn't find anything
there.

Is that possible some setting in the Opteron that prevent write access to
the EEPROM address be passed down southbridge?  I'm not farmilar with the
Opteron NB and CPU, if you guys can give me some pointers, that would help
me a lot.

I don't have a scope now, I will see if I can get one.

Thanks

beneo

----- Original Message ----- 
From: "Ronald G. Minnich" <rminnich at lanl.gov>
To: "beneo" <beneo at comcast.net>
Cc: <linuxbios at openbios.org>; "YhLu" <YhLu at tyan.com>
Sent: Thursday, May 12, 2005 7:51 AM
Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


> the flash problem: this sounds more to me like an enable line that has
> been added for FLASHWR.
>
> Beneo, do you have a scope? it is often useful to put a scope on the WR
> line and see if it is toggling.
>
> ron
>
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios




From YhLu at tyan.com  Thu May 12 20:20:41 2005
From: YhLu at tyan.com (YhLu)
Date: Thu, 12 May 2005 11:20:41 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
Message-ID: <3174569B9743D511922F00A0C943142309F80AED@TYANWEB>

some GPIO need to be enabled. I guess.

You need to check the schematic in AMD NDA web site to find out which GPIO
control that.

YH 

> -----Original Message-----
> From: beneo [mailto:beneo at comcast.net] 
> Sent: Thursday, May 12, 2005 10:57 AM
> To: Ronald G. Minnich
> Cc: linuxbios at openbios.org; YhLu
> Subject: Re: [LinuxBIOS] flash issue with AMD Ref board
> 
> 
> Ron,
> 
> I was also thinking if the AMD senanade board has some 
> special hardware to protect eeprom write. but after I tried 
> to boot with AMI BIOS into Linux and use same flash_and_burn 
> utility to flash LinuxBIOS into the EEPROM sucessufully, I 
> started to be convienced there are some setup issue within 
> LinuxBIOS caused this.
> 
> I spent sometime to check 8111 southbridge, but I couldn't 
> find anything there.
> 
> Is that possible some setting in the Opteron that prevent 
> write access to the EEPROM address be passed down 
> southbridge?  I'm not farmilar with the Opteron NB and CPU, 
> if you guys can give me some pointers, that would help me a lot.
> 
> I don't have a scope now, I will see if I can get one.
> 
> Thanks
> 
> beneo
> 
> ----- Original Message -----
> From: "Ronald G. Minnich" <rminnich at lanl.gov>
> To: "beneo" <beneo at comcast.net>
> Cc: <linuxbios at openbios.org>; "YhLu" <YhLu at tyan.com>
> Sent: Thursday, May 12, 2005 7:51 AM
> Subject: Re: [LinuxBIOS] flash issue with AMD Ref board
> 
> 
> > the flash problem: this sounds more to me like an enable 
> line that has
> > been added for FLASHWR.
> >
> > Beneo, do you have a scope? it is often useful to put a 
> scope on the WR
> > line and see if it is toggling.
> >
> > ron
> >
> >
> > _______________________________________________
> > LinuxBIOS mailing list
> > LinuxBIOS at openbios.org
> > http://www.openbios.org/mailman/listinfo/linuxbios
> 



From toto_lebolo at yahoo.com  Thu May 12 20:02:59 2005
From: toto_lebolo at yahoo.com (Toto Lebolo)
Date: Thu, 12 May 2005 11:02:59 -0700 (PDT)
Subject: [LinuxBIOS] makefile for Windows
Message-ID: <20050512180259.90592.qmail@web60922.mail.yahoo.com>

I am trying to rebuild linux BIOS. I have installed the Windows version of the compilers.
Does the makefile run in windows? or just in Linux?
 
toto

		
---------------------------------
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From beneo at comcast.net  Thu May 12 20:11:06 2005
From: beneo at comcast.net (beneo)
Date: Thu, 12 May 2005 11:11:06 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
References: <3174569B9743D511922F00A0C943142309F80AE9@TYANWEB>
Message-ID: <016e01c5571d$f75afa90$131814ac@trans.corp>

I can boot with 004 parts though. 

When I get the board, The AMI BIOS does in the 040 part. I may did a sucessful flash on 040 part. I will check and report back. 

beneo

  ----- Original Message ----- 
  From: YhLu 
  To: beneo ; linuxbios at openbios.org 
  Sent: Thursday, May 12, 2005 11:17 AM
  Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


  004 only can be use in intel platform. FW hub interface...

  040 can be used in AMD platform. LPC interface...

  PMC 004 support two interface...

  YH



----------------------------------------------------------------------------
    From: beneo [mailto:beneo at comcast.net] 
    Sent: Thursday, May 12, 2005 10:46 AM
    To: YhLu; linuxbios at openbios.org
    Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


    It's SST 49LF004. It the replacement for SST49LF040. They use same argorithm to flash. I looked the flash_and_burn utility. That's the case there too. 

    beneo.

      ----- Original Message ----- 
      From: YhLu 
      To: beneo ; linuxbios at openbios.org 
      Sent: Thursday, May 12, 2005 9:53 AM
      Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


      SST49LF004 or SST49LF040 ?

      YH



------------------------------------------------------------------------
        From: beneo [mailto:beneo at comcast.net] 
        Sent: Wednesday, May 11, 2005 7:20 PM
        To: beneo; YhLu; linuxbios at openbios.org
        Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


        YhLu,

        EEPOM should be SST 49LF004, sorry. 

        I also get the CPU version, it's a print out from cat /proc/cpuinfo. Total two CPU, I put the the second CPU here. 

        processor       : 1
        vendor_id       : AuthenticAMD
        cpu family      : 15
        model           : 5
        model name      : 02/05
        stepping        : 8
        cpu MHz         : 1395.089
        cache size      : 1024 KB
        physical id     : 0
        siblings        : 1
        fdiv_bug        : no
        hlt_bug         : no
        f00f_bug        : no
        coma_bug        : no
        fpu             : yes
        fpu_exception   : yes
        cpuid level     : 1
        wp              : yes
        flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall mmxext l
        m 3dnowext 3dnow
        bogomips        : 2785.28

        Thanks 

        Beneo

          ----- Original Message ----- 
          From: beneo 
          To: YhLu ; linuxbios at openbios.org 
          Sent: Wednesday, May 11, 2005 7:14 PM
          Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


          EEPROM is SST 48LF004.

          I install 2GB to CPU0 and 2GB to CPU1. I use 512MB DIMM, 4 DIMM per CPU, so total should be 4GB. But linux command cat /proc/meminfo report one 2 GB when using LinuxBIOS.

          I have two opteron CPU, I'm not sure the version though.

          thanks

          beneo

            ----- Original Message ----- 
            From: YhLu 
            To: beneo ; linuxbios at openbios.org 
            Sent: Wednesday, May 11, 2005 7:27 PM
            Subject: RE: [LinuxBIOS] flash issue with AMD Ref board


            what is EEPROM in your BIOS socket?

            How do you install your DIMM? 4x1G in CPU0?

            What is your cpu version?

            YH



------------------------------------------------------------------
              From: beneo [mailto:beneo at comcast.net] 
              Sent: Wednesday, May 11, 2005 6:57 PM
              To: linuxbios at openbios.org
              Subject: [LinuxBIOS] flash issue with AMD Ref board



              I'm playing with the AMD seranede board. The flash_and_burn utility can not program linuxBIOS to the flash. but I can read the linuxbios and save to a file correctly.

              If I boot from AMI BIOS, using same utility, I can program a linuxBIOS into the flash. That made me believe some setting by linuxBIOS on the AMD Ref board is not right. I just don't know what.

              I used gdb to trace the code, Flash_and_burn utility enables flash by program two AMD Southbridge 8111 registers, One for enable 4MB window to flash (DevB, 0x43), one for enable write to the flash (DevB, 0x40). I checked the AMD datasheet, it seems all it need. But if I boot with LinuxBIOS, the flash erase command has no effect. with AMI BIOS, I can sucessfully erase a sector. 

              could anybody give me some pointer on what to check? 

              I should add, the linuxBIOS only reports 2GB memory when I really have 4GB in the system. I don't know if this have something to do with my issue.

              Thanks 

              Beneo



--------------------------------------------------------------------


            _______________________________________________
            LinuxBIOS mailing list
            LinuxBIOS at openbios.org
            http://www.openbios.org/mailman/listinfo/linuxbios


----------------------------------------------------------------------


          _______________________________________________
          LinuxBIOS mailing list
          LinuxBIOS at openbios.org
          http://www.openbios.org/mailman/listinfo/linuxbios


--------------------------------------------------------------------------


      _______________________________________________
      LinuxBIOS mailing list
      LinuxBIOS at openbios.org
      http://www.openbios.org/mailman/listinfo/linuxbios


------------------------------------------------------------------------------


  _______________________________________________
  LinuxBIOS mailing list
  LinuxBIOS at openbios.org
  http://www.openbios.org/mailman/listinfo/linuxbios
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From talbotx at comcast.net  Thu May 12 20:17:49 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Thu, 12 May 2005 11:17:49 -0700
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
	<Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>
	<002501c55688$04acc660$c501a8c0@newflame>
	<Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
Message-ID: <004501c5571e$e7c10830$c501a8c0@newflame>

-Ron
That is great news.  I can easily rebuild the configs for the EPIA-MII and 
hopefully add VGAbios.  Please let me know when you have uploaded the new 
tree.
-Adam

----- Original Message ----- 
From: "Ronald G. Minnich" <rminnich at lanl.gov>
To: "Adam Talbot" <talbotx at comcast.net>
Cc: <linuxbios at openbios.org>
Sent: Thursday, May 12, 2005 7:35 AM
Subject: Re: [LinuxBIOS] Current status of the the EPIA-M/MII


>
>
> On Wed, 11 May 2005, Adam Talbot wrote:
>
>> Any one have the current status of the EPIA-M/MII?
>
> we're building linuxbios here on the EPIA. EPIA-M, well, that is next.
>
> We're at the point of making sure linux boots fine, and having fun with
> bproc (partly learning curve issues with a new guy, or so I hope ...)
>
> so, we hope to have good news soon. Hamish has done a godo job on geode
> and has ideas on how to improve Epia, so I'm counting on him :-)
>
> ron
> 





From stepan at openbios.org  Thu May 12 21:49:58 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu, 12 May 2005 21:49:58 +0200
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: <20050512180259.90592.qmail@web60922.mail.yahoo.com>
References: <20050512180259.90592.qmail@web60922.mail.yahoo.com>
Message-ID: <20050512194958.GA21138@openbios.org>

* Toto Lebolo <toto_lebolo at yahoo.com> [050512 20:02]:
> I am trying to rebuild linux BIOS. I have installed the Windows version of the
> compilers.
> Does the makefile run in windows? or just in Linux?

Find out and tell us, please!

You'll also need python installed.

Stefan






From stepan at openbios.org  Thu May 12 22:02:06 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu, 12 May 2005 22:02:06 +0200
Subject: [LinuxBIOS] flash issue with AMD Ref board
In-Reply-To: <014f01c5571b$fdca3c30$131814ac@trans.corp>
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov>
	<014f01c5571b$fdca3c30$131814ac@trans.corp>
Message-ID: <20050512200206.GB21138@openbios.org>

* beneo <beneo at comcast.net> [050512 19:56]:
> I spent sometime to check 8111 southbridge, but I couldn't find anything
> there.
 
It would not be part of the southbridge itself, but for example
connected to the smbus.
It might also very well be that AMIBIOS sets the switch correctly, which
is why flashing works in Linux with AB. but not with LB.

> Is that possible some setting in the Opteron that prevent write access to
> the EEPROM address be passed down southbridge? I'm not farmilar with the
> Opteron NB and CPU, if you guys can give me some pointers, that would help
> me a lot.

Not in the Opteron/NB itself, but it could very well be something
mainboard specifi, but it could very well be something mainboard
specific..

Stefan




From toto_lebolo at yahoo.com  Thu May 12 23:48:12 2005
From: toto_lebolo at yahoo.com (Toto Lebolo)
Date: Thu, 12 May 2005 14:48:12 -0700 (PDT)
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: 6667
Message-ID: <20050512214812.92018.qmail@web60918.mail.yahoo.com>

Apparently it does not run.
I started modifying the commands in the makefile, and started compiling rombios.c
I am getting this error:
rombios.c:2662:1: pasting "(" and ""ata_cmd_data_in : read error\n"" does not give a valid preprocessing token
 
the source line is:
    BX_DEBUG_ATA("ata_cmd_data_in : read error\n");

Do you think it is due to the environment?
MiKL

Stefan Reinauer <stepan at openbios.org> wrote:
* Toto Lebolo [050512 20:02]:
> I am trying to rebuild linux BIOS. I have installed the Windows version of the
> compilers.
> Does the makefile run in windows? or just in Linux?

Find out and tell us, please!

You'll also need python installed.

Stefan




		
---------------------------------
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 Take Yahoo! Mail with you! Check email on your mobile phone.
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From hansolofalcon at worldnet.att.net  Fri May 13 00:10:55 2005
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Thu, 12 May 2005 18:10:55 -0400
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: <20050512214812.92018.qmail@web60918.mail.yahoo.com>
Message-ID: <008f01c5573f$7a8945e0$6401a8c0@who5>

Hello from Gregg C Levine
Are you using the Cygwin stuff for your work? For reasons that I've
never bothered to investigate, the people behind the entire Cygwin
collection of GNU utilities use the bleeding edge of the source code
that makes up the regular GNU collection.

For example, try your make file under Linux, and report back your
results. I suspect your seeing the effects of the maintainers of GCC
to perfect their compiler even further. 

However this is good news that at least something happens.

And Stefan the next time your visiting NYC, and the US, the drinks are
on me. I would not of thought of suggesting it.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi
-----Original Message-----
From: linuxbios-bounces at openbios.org
[mailto:linuxbios-bounces at openbios.org] On Behalf Of Toto Lebolo
Sent: Thursday, May 12, 2005 5:48 PM
To: Stefan Reinauer
Cc: linuxbios at openbios.org
Subject: Re: [LinuxBIOS] makefile for Windows

Apparently it does not run.
I started modifying the commands in the makefile, and started
compiling rombios.c
I am getting this error:
rombios.c:2662:1: pasting "(" and ""ata_cmd_data_in : read error\n""
does not give a valid preprocessing token
?
the source line is:
??? BX_DEBUG_ATA("ata_cmd_data_in : read error\n");
Do you think it is due to the environment?
MiKL

Stefan Reinauer <stepan at openbios.org> wrote:
* Toto Lebolo [050512 20:02]:
> I am trying to rebuild linux BIOS. I have installed the Windows
version of the
> compilers.
> Does the makefile run in windows? or just in Linux?

Find out and tell us, please!

You'll also need python installed.

Stefan



Yahoo! Mail Mobile
Take Yahoo! Mail with you! Check email on your mobile phone.





From beneo at comcast.net  Fri May 13 01:21:53 2005
From: beneo at comcast.net (beneo)
Date: Thu, 12 May 2005 16:21:53 -0700
Subject: [LinuxBIOS] flash issue with AMD Ref board
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov><014f01c5571b$fdca3c30$131814ac@trans.corp>
	<20050512200206.GB21138@openbios.org>
Message-ID: <017901c55749$61be55a0$131814ac@trans.corp>

Thanks for all the help and ideas. YhLu, you are good. 040 works, but 004
doesn't. 040 has LPC interface, 004 has FWH interface.

thanks

beneo

----- Original Message ----- 
From: "Stefan Reinauer" <stepan at openbios.org>
To: "beneo" <beneo at comcast.net>
Cc: <linuxbios at openbios.org>; "YhLu" <YhLu at tyan.com>
Sent: Thursday, May 12, 2005 1:02 PM
Subject: Re: [LinuxBIOS] flash issue with AMD Ref board


> * beneo <beneo at comcast.net> [050512 19:56]:
> > I spent sometime to check 8111 southbridge, but I couldn't find anything
> > there.
>
> It would not be part of the southbridge itself, but for example
> connected to the smbus.
> It might also very well be that AMIBIOS sets the switch correctly, which
> is why flashing works in Linux with AB. but not with LB.
>
> > Is that possible some setting in the Opteron that prevent write access
to
> > the EEPROM address be passed down southbridge? I'm not farmilar with the
> > Opteron NB and CPU, if you guys can give me some pointers, that would
help
> > me a lot.
>
> Not in the Opteron/NB itself, but it could very well be something
> mainboard specifi, but it could very well be something mainboard
> specific..
>
> Stefan
>
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios




From rminnich at lanl.gov  Fri May 13 01:42:03 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 12 May 2005 17:42:03 -0600 (MDT)
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
In-Reply-To: <004501c5571e$e7c10830$c501a8c0@newflame>
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
	<Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>
	<002501c55688$04acc660$c501a8c0@newflame>
	<Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
	<004501c5571e$e7c10830$c501a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0505121741500.4227@enigma.lanl.gov>

go ahead and try the new tree. Josiah England here is testing EPIA and it 
seems to be working fine.

ron




From rminnich at lanl.gov  Fri May 13 01:55:20 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 12 May 2005 17:55:20 -0600 (MDT)
Subject: [LinuxBIOS] flash issue with AMD Ref board
In-Reply-To: <20050512200206.GB21138@openbios.org>
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov>
	<014f01c5571b$fdca3c30$131814ac@trans.corp>
	<20050512200206.GB21138@openbios.org>
Message-ID: <Pine.LNX.4.58.0505121754400.4227@enigma.lanl.gov>



On Thu, 12 May 2005, Stefan Reinauer wrote:

> It might also very well be that AMIBIOS sets the switch correctly, which
> is why flashing works in Linux with AB. but not with LB.

I am basically certain that this is a GPIO enabling flash write problem. 

Simple test: under fuctory bios, dump the state of the GPIO lines. Then do 
same under linuxbios. Look for differences. This is how I find this sort 
of problem.

ron



From talbotx at comcast.net  Fri May 13 04:59:30 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Thu, 12 May 2005 19:59:30 -0700
Subject: [LinuxBIOS] buildtarget error
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov><014f01c5571b$fdca3c30$131814ac@trans.corp><20050512200206.GB21138@openbios.org>
	<Pine.LNX.4.58.0505121754400.4227@enigma.lanl.gov>
Message-ID: <008001c55767$c8c32f50$c501a8c0@newflame>

OK, so I am feeling about as bright as a door nob.
Working on the EPIA-MII, and I cant get it to "buildtarget".
The problem is there is only 29 lines in my Config.lb. So I am not sure 
where the error is coming from.
Any ideas?

# ./buildtarget via/epia-mii
build_dir=via/epia-mii/epia-mii
./buildtarget: line 46: [: via/epia-mii/epia-mii: binary operator expected
#

-Adam Talbot 





From talbotx at comcast.net  Fri May 13 05:42:03 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Thu, 12 May 2005 20:42:03 -0700
Subject: [LinuxBIOS] buildtarget error
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov><014f01c5571b$fdca3c30$131814ac@trans.corp><20050512200206.GB21138@openbios.org><Pine.LNX.4.58.0505121754400.4227@enigma.lanl.gov>
	<008001c55767$c8c32f50$c501a8c0@newflame>
Message-ID: <008f01c5576d$babac020$c501a8c0@newflame>

Well, i got past that error...
But the epia-m still does not compile, same error on the south bridge, any 
ideas?
-Adam
----- Original Message ----- 
From: "Adam Talbot" <talbotx at comcast.net>
To: "Ronald G. Minnich" <rminnich at lanl.gov>
Cc: <linuxbios at openbios.org>
Sent: Thursday, May 12, 2005 7:59 PM
Subject: [LinuxBIOS] buildtarget error


> OK, so I am feeling about as bright as a door nob.
> Working on the EPIA-MII, and I cant get it to "buildtarget".
> The problem is there is only 29 lines in my Config.lb. So I am not sure 
> where the error is coming from.
> Any ideas?
>
> # ./buildtarget via/epia-mii
> build_dir=via/epia-mii/epia-mii
> ./buildtarget: line 46: [: via/epia-mii/epia-mii: binary operator expected
> #
>
> -Adam Talbot
>
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 





From hamish at prodigi.ch  Fri May 13 06:33:14 2005
From: hamish at prodigi.ch (Hamish Guthrie)
Date: Fri, 13 May 2005 06:33:14 +0200
Subject: [LinuxBIOS] buildtarget error
In-Reply-To: <008f01c5576d$babac020$c501a8c0@newflame>
Message-ID: <LDEKLCIFJMAFIOPNLICOIEMHFAAA.hamish@prodigi.ch>

Adam,

I had a brief look at the epia-m code a few weeks ago and found the same
issues with the buildtarget and compile issues all over the place. The tree
that is there is very broken, and it took me a while just to get it to
compile. I found a number of run-time issues, then I fried my test board! I
am awaiting a replacement.

Hamish

> -----Original Message-----
> From: linuxbios-bounces at openbios.org
> [mailto:linuxbios-bounces at openbios.org]On Behalf Of Adam Talbot
> Sent: Freitag, 13. Mai 2005 05:42
> To: Adam Talbot
> Cc: linuxbios at openbios.org
> Subject: Re: [LinuxBIOS] buildtarget error
>
>
> Well, i got past that error...
> But the epia-m still does not compile, same error on the south
> bridge, any
> ideas?
> -Adam
> ----- Original Message -----
> From: "Adam Talbot" <talbotx at comcast.net>
> To: "Ronald G. Minnich" <rminnich at lanl.gov>
> Cc: <linuxbios at openbios.org>
> Sent: Thursday, May 12, 2005 7:59 PM
> Subject: [LinuxBIOS] buildtarget error
>
>
> > OK, so I am feeling about as bright as a door nob.
> > Working on the EPIA-MII, and I cant get it to "buildtarget".
> > The problem is there is only 29 lines in my Config.lb. So I am not sure
> > where the error is coming from.
> > Any ideas?
> >
> > # ./buildtarget via/epia-mii
> > build_dir=via/epia-mii/epia-mii
> > ./buildtarget: line 46: [: via/epia-mii/epia-mii: binary
> operator expected
> > #
> >
> > -Adam Talbot
> >
> >
> > _______________________________________________
> > LinuxBIOS mailing list
> > LinuxBIOS at openbios.org
> > http://www.openbios.org/mailman/listinfo/linuxbios
> >
>
>
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>
> --
> No virus found in this incoming message.
> Checked by AVG Anti-Virus.
> Version: 7.0.308 / Virus Database: 266.11.8 - Release Date: 10.05.2005
>
--
No virus found in this outgoing message.
Checked by AVG Anti-Virus.
Version: 7.0.308 / Virus Database: 266.11.8 - Release Date: 10.05.2005




From rminnich at lanl.gov  Fri May 13 16:58:20 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 13 May 2005 08:58:20 -0600 (MDT)
Subject: [LinuxBIOS] Re: buildtarget error
In-Reply-To: <008001c55767$c8c32f50$c501a8c0@newflame>
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov><014f01c5571b$fdca3c30$131814ac@trans.corp><20050512200206.GB21138@openbios.org>
	<Pine.LNX.4.58.0505121754400.4227@enigma.lanl.gov>
	<008001c55767$c8c32f50$c501a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0505130857510.7051@enigma.lanl.gov>



On Thu, 12 May 2005, Adam Talbot wrote:

> build_dir=via/epia-mii/epia-mii
> ./buildtarget: line 46: [: via/epia-mii/epia-mii: binary operator expected

what distro? 

can you send output of sh -x ./buildtarget 

ron



From talbotx at comcast.net  Fri May 13 17:06:00 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Fri, 13 May 2005 08:06:00 -0700
Subject: [LinuxBIOS] Re: buildtarget error
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov><014f01c5571b$fdca3c30$131814ac@trans.corp><20050512200206.GB21138@openbios.org>
	<Pine.LNX.4.58.0505121754400.4227@enigma.lanl.gov>
	<008001c55767$c8c32f50$c501a8c0@newflame>
	<Pine.LNX.4.58.0505130857510.7051@enigma.lanl.gov>
Message-ID: <00b401c557cd$466ae550$c501a8c0@newflame>

-Ron
Got it fixed...  But I looks like the south bridge is still messed up on the 
EPIA-M/MII
-Adam
gentoo linux

----- Original Message ----- 
From: "Ronald G. Minnich" <rminnich at lanl.gov>
To: "Adam Talbot" <talbotx at comcast.net>
Cc: <linuxbios at openbios.org>
Sent: Friday, May 13, 2005 7:58 AM
Subject: Re: buildtarget error


>
>
> On Thu, 12 May 2005, Adam Talbot wrote:
>
>> build_dir=via/epia-mii/epia-mii
>> ./buildtarget: line 46: [: via/epia-mii/epia-mii: binary operator 
>> expected
>
> what distro?
>
> can you send output of sh -x ./buildtarget
>
> ron
> 





From rminnich at lanl.gov  Fri May 13 18:12:39 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 13 May 2005 10:12:39 -0600 (MDT)
Subject: [LinuxBIOS] buildtarget error
In-Reply-To: <008f01c5576d$babac020$c501a8c0@newflame>
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov><014f01c5571b$fdca3c30$131814ac@trans.corp><20050512200206.GB21138@openbios.org><Pine.LNX.4.58.0505121754400.4227@enigma.lanl.gov>
	<008001c55767$c8c32f50$c501a8c0@newflame>
	<008f01c5576d$babac020$c501a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0505131012270.7051@enigma.lanl.gov>



On Thu, 12 May 2005, Adam Talbot wrote:

> Well, i got past that error...

tell me more. How did you get past it?

ron



From rminnich at lanl.gov  Fri May 13 18:19:48 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 13 May 2005 10:19:48 -0600 (MDT)
Subject: [LinuxBIOS] Re: buildtarget error
In-Reply-To: <00b401c557cd$466ae550$c501a8c0@newflame>
References: <Pine.LNX.4.58.0505120851200.4227@enigma.lanl.gov><014f01c5571b$fdca3c30$131814ac@trans.corp><20050512200206.GB21138@openbios.org>
	<Pine.LNX.4.58.0505121754400.4227@enigma.lanl.gov>
	<008001c55767$c8c32f50$c501a8c0@newflame>
	<Pine.LNX.4.58.0505130857510.7051@enigma.lanl.gov>
	<00b401c557cd$466ae550$c501a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0505131019390.7051@enigma.lanl.gov>



On Fri, 13 May 2005, Adam Talbot wrote:

> Got it fixed...  But I looks like the south bridge is still messed up on the
> EPIA-M/MII

what was the fix? what are the problems?

ron
> 



From lists at endian.se  Fri May 13 22:02:56 2005
From: lists at endian.se (Kjell Svensson)
Date: Fri, 13 May 2005 22:02:56 +0200
Subject: [LinuxBIOS] smartcore-p5 fails to elfboot both FILO and etherboot
Message-ID: <16e61cd9bc033edc7ff0889f006d8ccb@endian.se>

Hi LinuxBIOS list subscribers,

I've been struggling for a couple of days now trying to get LinuxBIOS 
working on a DigitalLogic SmartCore-P5 166MHz PC/104 card.
I am using the v1 tree, since the v1 tree contained smartcore support, 
but the v2 tree does not.
I had no problems building and flashing the LinuxBIOS, and it starts up 
just fine and ends up in elfboot as expected. Elfboot reports to find 
my payload, loads it, and attempts to start executing it. At that 
point, nothing more happens. Due to the limited "debugability" at this 
point, it's hard to say exactly what has happened, but a serial output 
character I have put early in the FILO startup code is not showing up 
so I guess the FILO code is never reached at all(?)
I have verified that the filo elf image I'm trying to load is OK by 
loading it from GRUB (it worked OK).

I have searched both the archives and other parts of the Internet for 
some hints about this, but the only interesting thing I was able to 
find was a FAQ in the FILO tree saying there was a bug in some 
linuxbios/elfboot checksum calculation routine that would cause FILO to 
crash. According to that FAQ, using the latest linuxbios patches should 
fix this problem. But I couldn't find any patches newer than the v1 
stable tree, so I assumed this was old info(?)...

Does this sound familiar to anyone? Any suggestions would be highly 
appreciated.
The v2 tree contains support for another DigitalLogic card that I'm not 
familiar with. Would there be any chance that config would work on my 
SmartCore-P5 card?

Cheers,
/Kjell





From YhLu at tyan.com  Fri May 13 22:54:19 2005
From: YhLu at tyan.com (YhLu)
Date: Fri, 13 May 2005 13:54:19 -0700
Subject: [LinuxBIOS] About Nvidia chipset support
Message-ID: <3174569B9743D511922F00A0C943142309F80C89@TYANWEB>

Just commit some lines to  ondie Lan work now.

YH

> -----Original Message-----
> From: YhLu 
> Sent: Wednesday, May 11, 2005 1:36 PM
> To: YhLu; Ronald G. Minnich; ebiederman at lnxi.com; Stefan 
> Reinauer; Li-Ta Lo
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] About Nvidia chipset support
> 
> commited. 
> 
> > -----Original Message-----
> > From: YhLu
> > Sent: Wednesday, May 11, 2005 11:21 AM
> > To: Ronald G. Minnich; ebiederman at lnxi.com; Stefan 
> Reinauer; Li-Ta Lo
> > Cc: linuxbios at openbios.org
> > Subject: [LinuxBIOS] About Nvidia chipset support
> > 
> > All,
> > 
> > Finally I get the approval for releasing Nvidia chipset support for 
> > Ck804. I hope end user to press nvidia to release more info to make 
> > sata and on die lan work.
> > 
> > The problem my code is messed up dual core support etc. I need some 
> > time to split them up.
> > 
> > I will commit soon about
> > Nvidia CK804 support
> > smbus bus number support (to handle multi sumbus and mux) 
> superio smsc 
> > 47 support Tyan S2895/S2891/S2892 support flash_rom Ck804 support
> > 
> > maybe two months later after AMD issue auth letter or put 
> dual core on 
> > public
> > 
> > AMD D0/E0 Opteron new mem mapping support AMD E Opteron dual core 
> > support AMD E Opteron mem hole support AMD K8 Four Ranks 
> DIMM support
> > 
> > Regards
> > 
> > YH
> > 
> > _______________________________________________
> > LinuxBIOS mailing list
> > LinuxBIOS at openbios.org
> > http://www.openbios.org/mailman/listinfo/linuxbios
> > 
> 



From rminnich at lanl.gov  Fri May 13 23:05:28 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 13 May 2005 15:05:28 -0600 (MDT)
Subject: [LinuxBIOS] smartcore-p5 fails to elfboot both FILO and etherboot
In-Reply-To: <16e61cd9bc033edc7ff0889f006d8ccb@endian.se>
References: <16e61cd9bc033edc7ff0889f006d8ccb@endian.se>
Message-ID: <Pine.LNX.4.58.0505131504270.7051@enigma.lanl.gov>

the existing digitallogic support in v2 is not going to work on your card. 

So your payload is FILO? And filo won't come up. 

Are you on serial port console? You didn't try to set filo up for console 
did you? What baud rate? 

ron




From lists at endian.se  Sat May 14 09:51:21 2005
From: lists at endian.se (Kjell Svensson)
Date: Sat, 14 May 2005 09:51:21 +0200
Subject: [LinuxBIOS] smartcore-p5 fails to elfboot both FILO and etherboot
In-Reply-To: <Pine.LNX.4.58.0505131504270.7051@enigma.lanl.gov>
References: <16e61cd9bc033edc7ff0889f006d8ccb@endian.se>
	<Pine.LNX.4.58.0505131504270.7051@enigma.lanl.gov>
Message-ID: <c5e1e75139a3927ea753311b03bb39bd@endian.se>

I was almost sure the DL support in v2 wouldn't with my card, so I 
didn't try that. :-)
Is there any reason the smartcore:s weren't migrated to v2? Any 
interest in me giving it a shot after getting it to work with v1?

Yep, my intended payload is FILO, but I have also tried Etherboot with 
the same result.
I'm trying to load Linux from an ext2 fs residing on the IDE compact 
flash slot in the card. The Linux system is already working well, the 
BIOS work is an attempt to speed up the boot process.
The flash is 256kB, so there's no chance to squeeze the kernel into it, 
and my understanding from the documentation is that FILO should then be 
the way to go. Right?
Since I wanted to avoid possibly screwing up my original BIOS, I have 
burned the romimage into another flash chip with a standalone flash 
programmer in the lab. We didn't have any 256kB flashes in stock, so 
I've been using 128kB and 512kB flashes instead and adjusted the 
PAYLOAD_SIZE accordingly. The result is the same regardless whether I'm 
using 128kB or 512kB flashes - FILO won't come up, but since I haven't 
actually been able to try the original 256kB size I was thinking maybe 
there's something more to adjust than the PAYLOAD_SIZE to compensate 
for another flash size?
I have enabled extensive debugging (level 9), and read the outputs 
carefully (sorry, can't attach the output today since that's on another 
machine in the lab) but I cnnot find anything suspicious there.

Yes, I'm on a serial console. In fact, my DL board is the variant that 
is even not populated with the VGA chipset (optional). Unless the FILO 
config options are very unclear - No, I have disabled console and 
enabled serial at 115200. I have tried the built FILO image by loading 
it from GRUB, and my FILO image then worked fine at the serial link.

The note in the FILO FAQ about a checksum error in LinuxBIOS causing a 
crash, is that something that sounds familiar?

Cheers,
/Kjell



On 13 maj 2005, at 23:05, Ronald G. Minnich wrote:

> the existing digitallogic support in v2 is not going to work on your 
> card.
>
> So your payload is FILO? And filo won't come up.
>
> Are you on serial port console? You didn't try to set filo up for 
> console
> did you? What baud rate?
>
> ron
>
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios




From okajima at digitalinfra.co.jp  Sun May 15 08:59:38 2005
From: okajima at digitalinfra.co.jp (Jun OKAJIMA)
Date: Sun, 15 May 2005 15:59:38 +0900
Subject: [LinuxBIOS] EPIA result
Message-ID: <200505150659.AA00113@bbb-jz5c7z9hn9y.digitalinfra.co.jp>




Here is my result of current LinuxBIOS. And still does not work.
Do you have any advice? Especially, lx1 / epia would run with very little
effort, I suppose. What I have missed?

BTW, I even have not got EPIA-M with VIA fast boot util running.
Why? any advice? I used a single-bank 128 MB DDR-266 DDR RAM
which the doc assigns and tried both BIOS_R and BIOS_D,
but even debug messages from a serial port do not come.

                      --- Okajima, Jun.

Source:
  freebios--devel--2.0--patch-30.tar.bz2
  freebios--devel--1.0--base-0.tar.bz2
Payload:
  filo.elf with USB from Etherboot-5.4.0
M/B:
  EPIA C800 with 128M SDRAM on slot0 and 512M SDRAM on slot1.
  EPIA MII 12000 with 128M single bank DDR.
both are confirmed to work in Linux and Windows.
mems are checked with memtest86 and no problem.

result:
lx1 / epia   -> can not load a payload. maybe I missed something?
lx1 / epiam  -> can not recognize SDRAM.
lx2 / epia   -> stuck with MTTR stuff.
lx2 / epiam  -> can not build.
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From okajima at digitalinfra.co.jp  Sun May 15 09:37:55 2005
From: okajima at digitalinfra.co.jp (Jun OKAJIMA)
Date: Sun, 15 May 2005 16:37:55 +0900
Subject: [LinuxBIOS] EPIA result
In-Reply-To: <200505150659.AA00113@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
References: <200505150659.AA00113@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
Message-ID: <200505150737.AA00114@bbb-jz5c7z9hn9y.digitalinfra.co.jp>


>
>lx1 / epia   -> can not load a payload. maybe I missed something?
>lx1 / epiam  -> can not recognize SDRAM.
>lx2 / epia   -> stuck with MTTR stuff.
>lx2 / epiam  -> can not build.
>

it is reverse. missed. the right result is,

lx1 / epia   -> can not load a payload. maybe I missed something?
lx1 / epiam  -> stuck with MTTR stuff. and said 96MB mem but I put 128MB DDR.
lx2 / epia   -> can not recognize SDRAM.
lx2 / epiam  -> can not build.




From okajima at digitalinfra.co.jp  Sun May 15 13:56:31 2005
From: okajima at digitalinfra.co.jp (Jun OKAJIMA)
Date: Sun, 15 May 2005 20:56:31 +0900
Subject: [LinuxBIOS] EPIA result
In-Reply-To: <200505150659.AA00113@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
References: <200505150659.AA00113@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
Message-ID: <200505151156.AA00116@bbb-jz5c7z9hn9y.digitalinfra.co.jp>


>
>lx1 / epia   -> can not load a payload. maybe I missed something?
>lx1 / epiam  -> can not recognize SDRAM.
>lx2 / epia   -> stuck with MTTR stuff.
>lx2 / epiam  -> can not build.
>

sorry it is reverse. the right result is this.
anyway, can you give me any suggestion?

lx1 / epia   -> can not load a payload. maybe I missed something?
lx1 / epiam  -> stuck with MTTR stuff. and said 96MB mem but I put 128MB DDR.
lx2 / epia   -> can not recognize SDRAM.
lx2 / epiam  -> can not build.




From joncsorenson at yahoo.com  Sun May 15 23:24:16 2005
From: joncsorenson at yahoo.com (Jon Sorenson)
Date: Sun, 15 May 2005 14:24:16 -0700 (PDT)
Subject: [LinuxBIOS] EPIA-M
Message-ID: <20050515212416.59489.qmail@web51506.mail.yahoo.com>

What is the ETA for EPIA-M to build correctly? 

thanks!

-Jon



From rminnich at lanl.gov  Mon May 16 06:07:47 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Sun, 15 May 2005 22:07:47 -0600 (MDT)
Subject: [LinuxBIOS] EPIA result
In-Reply-To: <200505150659.AA00113@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
References: <200505150659.AA00113@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
Message-ID: <Pine.LNX.4.58.0505152207330.13884@enigma.lanl.gov>

sorry, can you send the output to me directly, uncompressed, as your 
attachment got stripped.

ron




From rminnich at lanl.gov  Mon May 16 06:08:44 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Sun, 15 May 2005 22:08:44 -0600 (MDT)
Subject: [LinuxBIOS] EPIA result
In-Reply-To: <200505150737.AA00114@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
References: <200505150659.AA00113@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
	<200505150737.AA00114@bbb-jz5c7z9hn9y.digitalinfra.co.jp>
Message-ID: <Pine.LNX.4.58.0505152208130.13884@enigma.lanl.gov>


Don't put any more time into LX1.


On Sun, 15 May 2005, Jun OKAJIMA wrote:

> lx2 / epia   -> can not recognize SDRAM.

hmm, it boots here, tell me more about sdram you are using.


> lx2 / epiam  -> can not build.

yep, we need help. 

ron



From rminnich at lanl.gov  Mon May 16 06:13:22 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Sun, 15 May 2005 22:13:22 -0600 (MDT)
Subject: [LinuxBIOS] EPIA-M
In-Reply-To: <20050515212416.59489.qmail@web51506.mail.yahoo.com>
References: <20050515212416.59489.qmail@web51506.mail.yahoo.com>
Message-ID: <Pine.LNX.4.58.0505152213010.13884@enigma.lanl.gov>



On Sun, 15 May 2005, Jon Sorenson wrote:

> What is the ETA for EPIA-M to build correctly? 

well, josiah england is finishing up work on epia, then we move to -m. 

ron



From ollie at lanl.gov  Mon May 16 17:08:03 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Mon, 16 May 2005 09:08:03 -0600
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
In-Reply-To: <Pine.LNX.4.58.0505121741500.4227@enigma.lanl.gov>
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
	<Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>
	<002501c55688$04acc660$c501a8c0@newflame>
	<Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
	<004501c5571e$e7c10830$c501a8c0@newflame>
	<Pine.LNX.4.58.0505121741500.4227@enigma.lanl.gov>
Message-ID: <1116256083.5283.53.camel@exponential.lanl.gov>

On Thu, 2005-05-12 at 17:42 -0600, Ronald G. Minnich wrote:
> go ahead and try the new tree. Josiah England here is testing EPIA and it 
> seems to be working fine.
> 
> ron
> 


did Josiah commit anything? Probably he is using the same local version
as on my HD.

-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From okajima at digitalinfra.co.jp  Mon May 16 17:54:19 2005
From: okajima at digitalinfra.co.jp (Jun OKAJIMA)
Date: Tue, 17 May 2005 00:54:19 +0900
Subject: [LinuxBIOS] EPIA result
In-Reply-To: <Pine.LNX.4.58.0505152208130.13884@enigma.lanl.gov>
References: <Pine.LNX.4.58.0505152208130.13884@enigma.lanl.gov>
Message-ID: <200505161554.AA00120@bbb-jz5c7z9hn9y.digitalinfra.co.jp>


>
>Don't put any more time into LX1.
>

Yeah, but lx1 for epia seems very near to run.
and I know any software development is difficult to meet deadline.
so I am afraid that I can run lx2 very soon, despite of your effort.
for lx1, probably just filo/payload problem is left.
hope give me some advices.

>
>On Sun, 15 May 2005, Jun OKAJIMA wrote:
>
>> lx2 / epia   -> can not recognize SDRAM.
>
>hmm, it boots here, tell me more about sdram you are using.
>

128M -> single side PC100 CL2. 256Mbits chip * 4.
512M -> dual side PC133. CL is unknown. 256Mbit * 8 * dual side.
the 512M one is a little bit mysterious. it is recognized 256M single side
by the genie BIOS. But, this kind of problem ("memory picky problem?")
happens often on VIA epia M/B.
Anyway, I can use these two SDRAM for 384MB memory with the genie BIOS.
and confirmed memtest86 passed.


                    --- Okajima.


>
>> lx2 / epiam  -> can not build.
>
>yep, we need help. 
>
>ron
>



From beneo at comcast.net  Tue May 17 18:51:44 2005
From: beneo at comcast.net (beneo)
Date: Tue, 17 May 2005 09:51:44 -0700
Subject: [LinuxBIOS] Does LinuxBIOS will support new AMD CPU
Message-ID: <01a201c55b00$b5f8db80$131814ac@trans.corp>

I just hear AMD is having next generation CPU come out, the code name is santa rosa, It will replace Opteron CPU and have DDR2 support and etc. Does linux bios would support this?

beneo.
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From josiah at lanl.gov  Tue May 17 19:06:12 2005
From: josiah at lanl.gov (Josiah England)
Date: Tue, 17 May 2005 11:06:12 -0600
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
In-Reply-To: <1116256083.5283.53.camel@exponential.lanl.gov>
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
	<Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>
	<002501c55688$04acc660$c501a8c0@newflame>
	<Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
	<004501c5571e$e7c10830$c501a8c0@newflame>
	<Pine.LNX.4.58.0505121741500.4227@enigma.lanl.gov>
	<1116256083.5283.53.camel@exponential.lanl.gov>
Message-ID: <1116349572.30649.7.camel@plipper.ccstar>

On Mon, 2005-05-16 at 09:08 -0600, Li-Ta Lo wrote:
> On Thu, 2005-05-12 at 17:42 -0600, Ronald G. Minnich wrote:
> > go ahead and try the new tree. Josiah England here is testing EPIA and it 
> > seems to be working fine.
> > 
> > ron
> > 
> 
> 
> did Josiah commit anything? Probably he is using the same local version
> as on my HD.

Yes, I'm still the local version you sent me.




From rminnich at lanl.gov  Tue May 17 19:26:59 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 11:26:59 -0600 (MDT)
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
In-Reply-To: <1116349572.30649.7.camel@plipper.ccstar>
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
	<Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>
	<002501c55688$04acc660$c501a8c0@newflame>
	<Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
	<004501c5571e$e7c10830$c501a8c0@newflame>
	<Pine.LNX.4.58.0505121741500.4227@enigma.lanl.gov>
	<1116256083.5283.53.camel@exponential.lanl.gov>
	<1116349572.30649.7.camel@plipper.ccstar>
Message-ID: <Pine.LNX.4.58.0505171126480.18949@enigma.lanl.gov>

we need to get your stuff in, josiah; can you work with ollie on that?

ron




From ollie at lanl.gov  Tue May 17 19:41:34 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue, 17 May 2005 11:41:34 -0600
Subject: [LinuxBIOS] Current status of the the EPIA-M/MII
In-Reply-To: <Pine.LNX.4.58.0505171126480.18949@enigma.lanl.gov>
References: <3174569B9743D511922F00A0C943142309F80990@TYANWEB>
	<Pine.LNX.4.58.0505111509130.1422@enigma.lanl.gov>
	<002501c55688$04acc660$c501a8c0@newflame>
	<Pine.LNX.4.58.0505120833120.4227@enigma.lanl.gov>
	<004501c5571e$e7c10830$c501a8c0@newflame>
	<Pine.LNX.4.58.0505121741500.4227@enigma.lanl.gov>
	<1116256083.5283.53.camel@exponential.lanl.gov>
	<1116349572.30649.7.camel@plipper.ccstar>
	<Pine.LNX.4.58.0505171126480.18949@enigma.lanl.gov>
Message-ID: <1116351694.5208.17.camel@exponential.lanl.gov>

On Tue, 2005-05-17 at 11:26 -0600, Ronald G. Minnich wrote:
> we need to get your stuff in, josiah; can you work with ollie on that?
> 
> ron
> 

Can we put him on the list of commiter?
-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From YhLu at tyan.com  Tue May 17 20:22:17 2005
From: YhLu at tyan.com (YhLu)
Date: Tue, 17 May 2005 11:22:17 -0700
Subject: [LinuxBIOS] Does LinuxBIOS will support new AMD CPU
Message-ID: <3174569B9743D511922F00A0C9431423022C2A5C@TYANWEB>

K9?
 
I can not find the doc in NDA section....
 
Quad core?
 
I guess current only tie-1 can have some sample....
 
YH


  _____  

From: beneo [mailto:beneo at comcast.net] 
Sent: Tuesday, May 17, 2005 9:52 AM
To: linuxbios at openbios.org
Subject: [LinuxBIOS] Does LinuxBIOS will support new AMD CPU


I just hear AMD is having next generation CPU come out, the code name is
santa rosa, It will replace Opteron CPU and have DDR2 support and etc. Does
linux bios would support this?
 
beneo.

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From Stephen.Kimball at bench.com  Tue May 17 21:17:43 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Tue, 17 May 2005 15:17:43 -0400
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C45@nh-ex01.bench.com>

 

I'd like to suggest that the romstrap files be moved from southbridge to mainboard, because the files are board specific with a default MAC address.  Also the ck804_nic.c files needs a mainboard specific get_mac_address() that resides in mainboard.

 

Steve

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From rminnich at lanl.gov  Tue May 17 21:46:51 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 13:46:51 -0600 (MDT)
Subject: [LinuxBIOS] CK804 suggestions
In-Reply-To: <9B124F08B3EFDA4F8813B05102DC719503A40C45@nh-ex01.bench.com>
References: <9B124F08B3EFDA4F8813B05102DC719503A40C45@nh-ex01.bench.com>
Message-ID: <Pine.LNX.4.58.0505171346410.18949@enigma.lanl.gov>



On Tue, 17 May 2005 Stephen.Kimball at bench.com wrote:

> I'd like to suggest that the romstrap files be moved from southbridge to
> mainboard, because the files are board specific with a default MAC
> address.  Also the ck804_nic.c files needs a mainboard specific
> get_mac_address() that resides in mainboard.

YhLu, can you fix this? it's a good point.

ron



From lists at endian.se  Tue May 17 22:30:30 2005
From: lists at endian.se (Kjell Svensson)
Date: Tue, 17 May 2005 22:30:30 +0200
Subject: [LinuxBIOS] still no luck on smartcore-p5
Message-ID: <56ce23fbc454b4afca705f058d43d46c@endian.se>

Hi list,

I reported about a week ago that I could not get a DigitalLogic  
smartcore-p5 PC/104 card to run neither FILO nor Etherboot using  
LinuxBIOS v1. Since then, I have kept trying to get it to work, but  
still no luck - I'm stuck exactly at the same point as a week ago:  
LinuxBIOS seems to startup fine, bit no message ever comes out from  
FILO :-(

So here's another try to get some hints from the list.
- Has anybody reported the smartcore-p5 support in v1 to actually work?
- I have attached the config files for LinuxBIOS and FILO below, as  
well as the LinuxBIOS serial console output with extensive debugging  
output enabled. Can anyone experienced in reading these see anything  
unusual here?
- Any suggestions how I should proceed?

I'd really appreciate some help here, since without it I'll probably  
have to give up using the LinuxBIOS at this point.

Cheers, /Kjell



LinuxBIOS config:
----------------
# Sample config file for Intel 430TX chipset on the Smartcore P5

# This will make a target directory of ./smartcore-p5
target smartcore-p5

# ASUS CUA  main board
mainboard digitallogic/smartcore-p5

# option HAVE_PIRQ_TABLE=1

# Enable Serial Console for debugging
option SERIAL_CONSOLE=1
option SERIAL_POST=1
option NO_KEYBOARD=1

#option INBUF_COPY=1

option DEBUG=1
option DEFAULT_CONSOLE_LOGLEVEL=9
option MAXIMUM_CONSOLE_LOGLEVEL=10

# MEMORY TESTING USING MEMTEST
# option RAMTEST=1

option USE_GENERIC_ROM=1
# option ROM_SIZE=131072
# option ROM_SIZE=524288
option ROM_SIZE=262144

# option STD_FLASH=1
# option PAYLOAD_SIZE=65536
# option PAYLOAD_SIZE=458752

option PAYLOAD_SIZE=196608


option CONFIG_COMPRESS=1


option USE_ELF_BOOT=1

payload ../filo.elf
# payload ../eepro100.elf



FILO Config:
------------
# !!! NOTE !!!
# Do NOT add spaces or comments at the end of option lines.
# It confuses some versions of make.

# Image filename for automatic boot and optional command line parameter
AUTOBOOT_FILE = "hdc1:/bzImage root=/dev/hdc2 rw console=tty0  
console=ttyS0,115200"

# Time in second before booting AUTOBOOT_FILE
AUTOBOOT_DELAY = 5

# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus
IDE_DISK = 1

# VGA text console
#VGA_CONSOLE = 0
#PC_KEYBOARD = 0

# Serial console
SERIAL_CONSOLE = 1
SERIAL_IOBASE = 0x3f8
SERIAL_SPEED = 115200

# Filesystems
FSYS_EXT2FS = 1
#FSYS_FAT = 0
#FSYS_JFS = 0
#FSYS_MINIX = 0
#FSYS_REISERFS = 0
#FSYS_XFS = 0
#FSYS_ISO9660 = 0

# Support for boot disk image in bootable CD-ROM (El Torito)
#ELTORITO = 0

# PCI support
SUPPORT_PCI = 1

# Enable this if not all PCI buses are scanned (you can see it with  
DEBUG_PCI)
# K8-based boards may need it
#PCI_BRUTE_SCAN = 1

# Sound support (needs SUPPORT_PCI)
#SUPPORT_SOUND = 1

# Sound drivers
#VIA_SOUND = 1

# Debugging
DEBUG_ALL = 1
#DEBUG_ELFBOOT = 1
#DEBUG_ELFNOTE = 1
#DEBUG_LINUXBIOS = 1
#DEBUG_MALLOC = 1
#DEBUG_MULTIBOOT = 1
#DEBUG_SEGMENT = 1
#DEBUG_SYS_INFO = 1
#DEBUG_TIMER = 1
#DEBUG_BLOCKDEV = 1
#DEBUG_PCI = 1
#DEBUG_VIA_SOUND = 1
#DEBUG_LINUXLOAD = 1
#DEBUG_IDE = 1
#DEBUG_ELTORITO = 1

# i386 options

# Loader for standard Linux kernel image, a.k.a. /vmlinuz
LINUX_LOADER = 1

# Boot FILO from Multiboot loader (eg. GRUB)
MULTIBOOT_IMAGE = 1

# Use PCI Configuration Mechanism #1 (most boards)
PCI_CONFIG_1 = 1


LinuxBIOS serial console output (extensive debugging enabled):
---------------------------------------------------------------


LinuxBIOS-1.0.0 Mon May 16 14:25:45 CEST 2005 starting...
Ram1
After 0x0000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x54...
After 0x00...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x4000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x0000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x54...
After 0x00...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x4000000 nop...
First DRAM setup done
Ram2
Ram3
Ram Enable 1
Ram Enable 2
Ram Enable 3
Ram Enable 4
Ram Enable 5
Ram4
Ram5
Ram6
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
POST: 0x39
LinuxBIOS-1.0.0 Mon May 16 14:25:45 CEST 2005 booting...
POST: 0x40
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f
Scanning PCI bus...PCI: pci_scan_bus for bus 0
POST: 0x24
Read config dword bus 0,devfn 0x0,reg 0x0,val 0x71008086,res 0x0
Read config byte bus 0,devfn 0x0,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x0,reg 0x8,val 0x6000001,res 0x0
malloc Enter, size 204, free_mem_ptr 0001100c
malloc 0x0001100c
Read config byte bus 0,devfn 0x0,reg 0x4,val 0x6,res 0x0
Write config byte bus 0, devfn 0x0, reg 0x4, val 0x6
Read config byte bus 0,devfn 0x0,reg 0x4,val 0x6,res 0x0
Write config byte bus 0, devfn 0x0, reg 0x4, val 0x6
PCI: 00:00.0 [8086/7100]
Read config dword bus 0,devfn 0x8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x8, bad id 0xffffffff
Read config dword bus 0,devfn 0x10,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x10, bad id 0xffffffff
Read config dword bus 0,devfn 0x18,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x18, bad id 0xffffffff
Read config dword bus 0,devfn 0x20,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x20, bad id 0xffffffff
Read config dword bus 0,devfn 0x28,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x28, bad id 0xffffffff
Read config dword bus 0,devfn 0x30,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x30, bad id 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x0,val 0x71108086,res 0x0
Read config byte bus 0,devfn 0x38,reg 0xe,val 0x80,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x8,val 0x6010002,res 0x0
malloc Enter, size 204, free_mem_ptr 000110d8
malloc 0x000110d8
Read config byte bus 0,devfn 0x38,reg 0x4,val 0x7,res 0x0
Write config byte bus 0, devfn 0x38, reg 0x4, val 0x7
Read config byte bus 0,devfn 0x38,reg 0x4,val 0x7,res 0x0
Write config byte bus 0, devfn 0x38, reg 0x4, val 0x7
PCI: 00:07.0 [8086/7110]
Read config dword bus 0,devfn 0x39,reg 0x0,val 0x71118086,res 0x0
Read config byte bus 0,devfn 0x39,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x39,reg 0x8,val 0x1018001,res 0x0
malloc Enter, size 204, free_mem_ptr 000111a4
malloc 0x000111a4
Read config byte bus 0,devfn 0x39,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x39, reg 0x4, val 0x4
Read config byte bus 0,devfn 0x39,reg 0x4,val 0x4,res 0x0
Write config byte bus 0, devfn 0x39, reg 0x4, val 0x0
PCI: 00:07.1 [8086/7111]
Read config dword bus 0,devfn 0x3a,reg 0x0,val 0x71128086,res 0x0
Read config byte bus 0,devfn 0x3a,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3a,reg 0x8,val 0xc030001,res 0x0
malloc Enter, size 204, free_mem_ptr 00011270
malloc 0x00011270
Read config byte bus 0,devfn 0x3a,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x3a, reg 0x4, val 0x4
Read config byte bus 0,devfn 0x3a,reg 0x4,val 0x4,res 0x0
Write config byte bus 0, devfn 0x3a, reg 0x4, val 0x0
PCI: 00:07.2 [8086/7112]
Read config dword bus 0,devfn 0x3b,reg 0x0,val 0x71138086,res 0x0
Read config byte bus 0,devfn 0x3b,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x8,val 0x6800002,res 0x0
malloc Enter, size 204, free_mem_ptr 0001133c
malloc 0x0001133c
Read config byte bus 0,devfn 0x3b,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x3b, reg 0x4, val 0x4
Read config byte bus 0,devfn 0x3b,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x3b, reg 0x4, val 0x0
PCI: 00:07.3 [8086/7113]
Read config dword bus 0,devfn 0x3c,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x3c, bad id 0xffffffff
Read config dword bus 0,devfn 0x3d,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x3d, bad id 0xffffffff
Read config dword bus 0,devfn 0x3e,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x3e, bad id 0xffffffff
Read config dword bus 0,devfn 0x3f,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x3f, bad id 0xffffffff
Read config dword bus 0,devfn 0x40,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x40, bad id 0xffffffff
Read config dword bus 0,devfn 0x48,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x48, bad id 0xffffffff
Read config dword bus 0,devfn 0x50,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x50, bad id 0xffffffff
Read config dword bus 0,devfn 0x58,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x58, bad id 0xffffffff
Read config dword bus 0,devfn 0x60,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x60, bad id 0xffffffff
Read config dword bus 0,devfn 0x68,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x68, bad id 0xffffffff
Read config dword bus 0,devfn 0x70,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x70, bad id 0xffffffff
Read config dword bus 0,devfn 0x78,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x78, bad id 0xffffffff
Read config dword bus 0,devfn 0x80,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x80, bad id 0xffffffff
Read config dword bus 0,devfn 0x88,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x88, bad id 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x0,val 0x12098086,res 0x0
Read config byte bus 0,devfn 0x90,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x90,reg 0x8,val 0x2000010,res 0x0
malloc Enter, size 204, free_mem_ptr 00011408
malloc 0x00011408
Read config byte bus 0,devfn 0x90,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x90, reg 0x4, val 0x4
Read config byte bus 0,devfn 0x90,reg 0x4,val 0x4,res 0x0
Write config byte bus 0, devfn 0x90, reg 0x4, val 0x0
PCI: 00:12.0 [8086/1209]
Read config dword bus 0,devfn 0x98,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x98, bad id 0xffffffff
Read config dword bus 0,devfn 0xa0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xa0, bad id 0xffffffff
Read config dword bus 0,devfn 0xa8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xa8, bad id 0xffffffff
Read config dword bus 0,devfn 0xb0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xb0, bad id 0xffffffff
Read config dword bus 0,devfn 0xb8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xb8, bad id 0xffffffff
Read config dword bus 0,devfn 0xc0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xc0, bad id 0xffffffff
Read config dword bus 0,devfn 0xc8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xc8, bad id 0xffffffff
Read config dword bus 0,devfn 0xd0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xd0, bad id 0xffffffff
Read config dword bus 0,devfn 0xd8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xd8, bad id 0xffffffff
Read config dword bus 0,devfn 0xe0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xe0, bad id 0xffffffff
Read config dword bus 0,devfn 0xe8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xe8, bad id 0xffffffff
Read config dword bus 0,devfn 0xf0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xf0, bad id 0xffffffff
Read config dword bus 0,devfn 0xf8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xf8, bad id 0xffffffff
POST: 0x25
PCI: pci_scan_bus returning with max=00
POST: 0x55
done
POST: 0x66
Allocating PCI resources...
PCI: 00:00.0 compute_allocate_io: base: 00000400 size: 00000000 align:  
0 gran: 0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x39,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x20,val 0x1,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x20,val 0xfff1,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x20,val 0x1,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x20, val 0x1
Read config dword bus 0,devfn 0x39,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3a,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x20,val 0x1,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x20,val 0xffe1,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x20,val 0x1,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x20, val 0x1
Read config dword bus 0,devfn 0x3a,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x90,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x10,val 0xfffff000,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x14,val 0x1,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x14,val 0xffffffc1,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x14,val 0x1,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x14, val 0x1
Read config dword bus 0,devfn 0x90,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x18,val 0xfffe0000,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x30,val 0x0,res 0x0
PCI: 00:12.0 14 *  [0x00000400 - 0x0000043f] io
PCI: 00:07.2 20 *  [0x00000440 - 0x0000045f] io
PCI: 00:07.1 20 *  [0x00000460 - 0x0000046f] io
PCI: 00:00.0 compute_allocate_io: base: 00000470 size: 00000070 align:  
6 gran: 0 done
PCI: 00:00.0 compute_allocate_mem: base: 00000000 size: 00000000 align:  
0 gran: 0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x30,val 0x0,res 0x0
PCI: 00:12.0 18 *  [0x00000000 - 0x0001ffff] mem
PCI: 00:12.0 10 *  [0x00020000 - 0x00020fff] mem
PCI: 00:00.0 compute_allocate_mem: base: 00021000 size: 00021000 align:  
17 gran: 0 done
PCI: 00:00.0 compute_allocate_io: base: 00001000 size: 00000070 align:  
6 gran: 0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x30,val 0x0,res 0x0
PCI: 00:12.0 14 *  [0x00001000 - 0x0000103f] io
PCI: 00:07.2 20 *  [0x00001040 - 0x0000105f] io
PCI: 00:07.1 20 *  [0x00001060 - 0x0000106f] io
PCI: 00:00.0 compute_allocate_io: base: 00001070 size: 00000070 align:  
6 gran: 0 done
PCI: 00:00.0 compute_allocate_mem: base: febc0000 size: 00021000 align:  
17 gran: 0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x30,val 0x0,res 0x0
PCI: 00:12.0 18 *  [0xfebc0000 - 0xfebdffff] mem
PCI: 00:12.0 10 *  [0xfebe0000 - 0xfebe0fff] mem
PCI: 00:00.0 compute_allocate_mem: base: febe1000 size: 00021000 align:  
17 gran: 0 done
ASSIGN RESOURCES, bus 0
Write config byte bus 0, devfn 0x0, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x0,reg 0x3d,val 0x0,res 0x0
Write config byte bus 0, devfn 0x0, reg 0xc, val 0x10
Write config byte bus 0, devfn 0x38, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x38,reg 0x3d,val 0x0,res 0x0
Write config byte bus 0, devfn 0x38, reg 0xc, val 0x10
Write config dword bus 0, devfn 0x39, reg 0x20, val 0x1061
PCI: 00:07.1 20 <- [0x00001060 - 0x0000106f] io
Write config byte bus 0, devfn 0x39, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x39,reg 0x3d,val 0x0,res 0x0
Write config byte bus 0, devfn 0x39, reg 0xc, val 0x10
Write config dword bus 0, devfn 0x3a, reg 0x20, val 0x1041
PCI: 00:07.2 20 <- [0x00001040 - 0x0000105f] io
Write config byte bus 0, devfn 0x3a, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x3a,reg 0x3d,val 0x4,res 0x0
Write config byte bus 0, devfn 0x3a, reg 0x3c, val 0x0
Write config byte bus 0, devfn 0x3a, reg 0xc, val 0x10
Write config byte bus 0, devfn 0x3b, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x3b,reg 0x3d,val 0x0,res 0x0
Write config byte bus 0, devfn 0x3b, reg 0xc, val 0x10
Write config dword bus 0, devfn 0x90, reg 0x10, val 0xfebe0000
PCI: 00:12.0 10 <- [0xfebe0000 - 0xfebe0fff] mem
Write config dword bus 0, devfn 0x90, reg 0x14, val 0x1001
PCI: 00:12.0 14 <- [0x00001000 - 0x0000103f] io
Write config dword bus 0, devfn 0x90, reg 0x18, val 0xfebc0000
PCI: 00:12.0 18 <- [0xfebc0000 - 0xfebdffff] mem
Write config byte bus 0, devfn 0x90, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x90,reg 0x3d,val 0x1,res 0x0
Write config byte bus 0, devfn 0x90, reg 0x3c, val 0x0
Write config byte bus 0, devfn 0x90, reg 0xc, val 0x10
ASSIGNED RESOURCES, bus 0
Read config dword bus 0,devfn 0x0,reg 0x8,val 0x6000001,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x8,val 0x6010002,res 0x0
Read config dword bus 0,devfn 0x39,reg 0x8,val 0x1018001,res 0x0
Read config dword bus 0,devfn 0x3a,reg 0x8,val 0xc030001,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x8,val 0x6800002,res 0x0
Read config dword bus 0,devfn 0x90,reg 0x8,val 0x2000010,res 0x0
done.
POST: 0x88
Enabling PCI resourcess...Read config word bus 0,devfn 0x0,reg 0x4,val  
0x6,res 0x0
PCI: 00:00.0 cmd <- 06
Write config word bus 0, devfn 0x0, reg 0x4, val 0x6
Read config word bus 0,devfn 0x38,reg 0x4,val 0x7,res 0x0
PCI: 00:07.0 cmd <- 07
Write config word bus 0, devfn 0x38, reg 0x4, val 0x7
Read config word bus 0,devfn 0x39,reg 0x4,val 0x0,res 0x0
PCI: 00:07.1 cmd <- 01
Write config word bus 0, devfn 0x39, reg 0x4, val 0x1
Read config word bus 0,devfn 0x3a,reg 0x4,val 0x0,res 0x0
PCI: 00:07.2 cmd <- 01
Write config word bus 0, devfn 0x3a, reg 0x4, val 0x1
Read config word bus 0,devfn 0x3b,reg 0x4,val 0x0,res 0x0
PCI: 00:07.3 cmd <- 00
Write config word bus 0, devfn 0x3b, reg 0x4, val 0x0
Read config word bus 0,devfn 0x90,reg 0x4,val 0x0,res 0x0
PCI: 00:12.0 cmd <- 03
Write config word bus 0, devfn 0x90, reg 0x4, val 0x3
done.
Initializing PCI devices...
PCI devices initialized
POST: 0x89
Read config byte bus 0,devfn 0x0,reg 0x65,val 0x20,res 0x0
POST: 0x70
totalram: 128M
Initializing CPU #0
POST: 0x60
Enabling cache...POST: 0x6a
done.

Max cpuid index    : 1
Vendor ID          : GenuineIntel
Processor Type     : 0x00
Processor Family   : 0x05
Processor Model    : 0x08
Processor Mask     : 0x00
Processor Stepping : 0x01
Feature flags      : 0x008001bf

POST: 0x92
done.
POST: 0x9b
CPU #0 Initialized
BOOT CPU is 0
intel_mainboard_fixup()
Write config byte bus 0, devfn 0x0, reg 0x3c, val 0x15
Testing SMI
Read config dword bus 0,devfn 0x3b,reg 0x58,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x58, val 0x2000000
SMI disabled
POST: 0x75
POST: 0x77
POST: 0x91
POST: 0x92
Enabling extended BIOS access
Enabling Full ISA Mode
Read config byte bus 0,devfn 0x38,reg 0xb0,val 0x0,res 0x0
Write config byte bus 0, devfn 0x38, reg 0xb0, val 0x1
Enabling IRQ8
Read config byte bus 0,devfn 0x38,reg 0xb1,val 0x0,res 0x0
Write config byte bus 0, devfn 0x38, reg 0xb1, val 0x40
Enabling Mouse IRQ12 on piix4e
Write config word bus 0, devfn 0x38, reg 0x4e, val 0x3f1
done.
POST: 0x91
POST: 0x95
POST: 0xec
POST: 0x9a
Checking IRQ routing tables...
/home/ks/proj/p513_Tiburtius/fastboot/freebios-1.0/src/arch/i386/lib/ 
pirq_routing.c:    30:check_pirq_routing_table() - irq_routing_table  
located at: 0x000087c0
done.
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...failed
POST: 0x96
Wrote linuxbios table at: 00000500 - 00000684  checksum 2e6b

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

POST: 0xf8
     37:init_bytes() - zkernel_start:0xfffc0000  zkernel_mask:0x0000007f
Found ELF candiate at offset 0
header_offset is 0
Try to load at offset 0x0
malloc Enter, size 32, free_mem_ptr 000114d4
malloc 0x000114d4
New segment addr 0x100000 size 0x22300 offset 0xa0 filesize 0x8368
(cleaned up) New segment addr 0x100000 size 0x22300 offset 0xa0  
filesize 0x8368
lb: [0x0000000000004000, 0x000000000005100c)
malloc Enter, size 32, free_mem_ptr 000114f4
malloc 0x000114f4
New segment addr 0x122300 size 0x48 offset 0x8420 filesize 0x48
(cleaned up) New segment addr 0x122300 size 0x48 offset 0x8420 filesize  
0x48
lb: [0x0000000000004000, 0x000000000005100c)
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000022300  
filesz: 0x0000000000008368
[ 0x0000000000100000, 0000000000108368, 0x0000000000122300) <-  
00000000000000a0
Clearing Segment: addr: 0x0000000000108368 memsz: 0x0000000000019f98
Loading Segment: addr: 0x0000000000122300 memsz: 0x0000000000000048  
filesz: 0x0000000000000048
[ 0x0000000000122300, 0000000000122348, 0x0000000000122348) <-  
0000000000008420
Loaded segments
verified segments
closed down stream
Jumping to boot code at 0x104e24
POST: 0xfe
entry    = 0x00104e24
lb_start = 0x00004000
lb_size  = 0x0004d00c
adjust   = 0x07faeff4
buffer   = 0x07f65fe8
      elf_boot_notes = 0x0000ae80
adjusted_boot_notes = 0x07fb9e74




From YhLu at tyan.com  Tue May 17 23:36:42 2005
From: YhLu at tyan.com (YhLu)
Date: Tue, 17 May 2005 14:36:42 -0700
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <3174569B9743D511922F00A0C9431423022C2A60@TYANWEB>

don't need, 
1. good hw design should use one serial EEPROM to store MAC address, So when
flash the BIOS, the EEPROM is still there.
	in ck804_nic.c will read MAC from serial EEPROM in SMBUS (bus num
and device num is set in Mainboard Config.lb), at first.
2. even for bad design, you can keep your own romstrap.inc/lds in your
mainboard dir, and modify Config.lb to point corrent file.
	In such case, you need special flash util to keep your MAC address
or read the MAC address at first, and then set it back....

YH 

> -----Original Message-----
> From: Ronald G. Minnich [mailto:rminnich at lanl.gov] 
> Sent: Tuesday, May 17, 2005 12:47 PM
> To: Stephen.Kimball at bench.com
> Cc: YhLu; linuxbios at openbios.org
> Subject: Re: [LinuxBIOS] CK804 suggestions
> 
> 
> 
> On Tue, 17 May 2005 Stephen.Kimball at bench.com wrote:
> 
> > I'd like to suggest that the romstrap files be moved from 
> southbridge 
> > to mainboard, because the files are board specific with a 
> default MAC 
> > address.  Also the ck804_nic.c files needs a mainboard specific
> > get_mac_address() that resides in mainboard.
> 
> YhLu, can you fix this? it's a good point.
> 
> ron
> 



From Stephen.Kimball at bench.com  Tue May 17 23:59:53 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Tue, 17 May 2005 17:59:53 -0400
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C46@nh-ex01.bench.com>

Your approach only allows the MAC address to be in the EEPROM or the romstrap.  Every motherboard would have to put the EEPROM in exactly the same place for this to be a general solution.  Not likely.  
Neither place is a general solution.   
Getting the MAC address is board specific and belongs in mainboard.

Steve

-----Original Message-----
From: YhLu [mailto:YhLu at tyan.com] 
Sent: Tuesday, May 17, 2005 5:37 PM
To: Ronald G. Minnich; Kimball, Stephen
Cc: YhLu at tyan.com; linuxbios at openbios.org
Subject: RE: [LinuxBIOS] CK804 suggestions

don't need, 
1. good hw design should use one serial EEPROM to store MAC address, So when
flash the BIOS, the EEPROM is still there.
	in ck804_nic.c will read MAC from serial EEPROM in SMBUS (bus num
and device num is set in Mainboard Config.lb), at first.
2. even for bad design, you can keep your own romstrap.inc/lds in your
mainboard dir, and modify Config.lb to point corrent file.
	In such case, you need special flash util to keep your MAC address
or read the MAC address at first, and then set it back....

YH 

> -----Original Message-----
> From: Ronald G. Minnich [mailto:rminnich at lanl.gov] 
> Sent: Tuesday, May 17, 2005 12:47 PM
> To: Stephen.Kimball at bench.com
> Cc: YhLu; linuxbios at openbios.org
> Subject: Re: [LinuxBIOS] CK804 suggestions
> 
> 
> 
> On Tue, 17 May 2005 Stephen.Kimball at bench.com wrote:
> 
> > I'd like to suggest that the romstrap files be moved from 
> southbridge 
> > to mainboard, because the files are board specific with a 
> default MAC 
> > address.  Also the ck804_nic.c files needs a mainboard specific
> > get_mac_address() that resides in mainboard.
> 
> YhLu, can you fix this? it's a good point.
> 
> ron
> 



From rminnich at lanl.gov  Wed May 18 00:02:24 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 16:02:24 -0600 (MDT)
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <56ce23fbc454b4afca705f058d43d46c@endian.se>
References: <56ce23fbc454b4afca705f058d43d46c@endian.se>
Message-ID: <Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>



On Tue, 17 May 2005, Kjell Svensson wrote:

> - Has anybody reported the smartcore-p5 support in v1 to actually work?

I had a whole stack of them working years ago. They really ought to work.

I think it's a filo problem, could you try booting memtest86 instead?

ron



From rminnich at lanl.gov  Wed May 18 00:04:25 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 16:04:25 -0600 (MDT)
Subject: [LinuxBIOS] CK804 suggestions
In-Reply-To: <3174569B9743D511922F00A0C9431423022C2A60@TYANWEB>
References: <3174569B9743D511922F00A0C9431423022C2A60@TYANWEB>
Message-ID: <Pine.LNX.4.58.0505171603270.18949@enigma.lanl.gov>



On Tue, 17 May 2005, YhLu wrote:

> don't need, 
> 1. good hw design should use one serial EEPROM to store MAC address, So when
> flash the BIOS, the EEPROM is still there.

yes, but there were some sis-630 based cards several years ago that stored 
MAC in FLASH and CMOS. 

SO to upgrade FLASH:
- make sure address is in cmos
- write flash
- write MAC back to flash. 


There are some stupid designs out there. 

ron



From rminnich at lanl.gov  Wed May 18 00:06:18 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 16:06:18 -0600 (MDT)
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
References: <56ce23fbc454b4afca705f058d43d46c@endian.se>
	<Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
Message-ID: <Pine.LNX.4.58.0505171605570.18949@enigma.lanl.gov>



On Tue, 17 May 2005, Ronald G. Minnich wrote:

> 
> 
> On Tue, 17 May 2005, Kjell Svensson wrote:
> 
> > - Has anybody reported the smartcore-p5 support in v1 to actually work?
> 
> I had a whole stack of them working years ago. They really ought to work.

hey, I could try to see if mine still boots and, if so, send you the flash 
image ...

it's old.

ron



From YhLu at tyan.com  Wed May 18 00:35:59 2005
From: YhLu at tyan.com (YhLu)
Date: Tue, 17 May 2005 15:35:59 -0700
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <3174569B9743D511922F00A0C943142309F80ED8@TYANWEB>

In CMOS? unbelievable. 
Factory personal and service guys will keep kicking the design engineer and
blaming their design.

YH

> -----Original Message-----
> From: Ronald G. Minnich [mailto:rminnich at lanl.gov] 
> Sent: Tuesday, May 17, 2005 3:04 PM
> To: YhLu
> Cc: Stephen.Kimball at bench.com; linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] CK804 suggestions
> 
> 
> 
> On Tue, 17 May 2005, YhLu wrote:
> 
> > don't need,
> > 1. good hw design should use one serial EEPROM to store MAC 
> address, 
> > So when flash the BIOS, the EEPROM is still there.
> 
> yes, but there were some sis-630 based cards several years 
> ago that stored MAC in FLASH and CMOS. 
> 
> SO to upgrade FLASH:
> - make sure address is in cmos
> - write flash
> - write MAC back to flash. 
> 
> 
> There are some stupid designs out there. 
> 
> ron
> 



From toto_lebolo at yahoo.com  Wed May 18 00:20:25 2005
From: toto_lebolo at yahoo.com (Toto Lebolo)
Date: Tue, 17 May 2005 15:20:25 -0700 (PDT)
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: 6667
Message-ID: <20050517222025.20306.qmail@web60924.mail.yahoo.com>

I am getting now an error with bcc. 
 
bcc -o rombios.s -C-c -D__i86__ -0 -S _rombios_.c
Unable to execute bcc-cc1.exe
 
I don't know why I am getting this error the file is in the path.
MiKL~

Gregg C Levine <hansolofalcon at worldnet.att.net> wrote:
Hello from Gregg C Levine
Are you using the Cygwin stuff for your work? For reasons that I've
never bothered to investigate, the people behind the entire Cygwin
collection of GNU utilities use the bleeding edge of the source code
that makes up the regular GNU collection.

For example, try your make file under Linux, and report back your
results. I suspect your seeing the effects of the maintainers of GCC
to perfect their compiler even further. 

However this is good news that at least something happens.

And Stefan the next time your visiting NYC, and the US, the drinks are
on me. I would not of thought of suggesting it.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."  Obi-Wan Kenobi
-----Original Message-----
From: linuxbios-bounces at openbios.org
[mailto:linuxbios-bounces at openbios.org] On Behalf Of Toto Lebolo
Sent: Thursday, May 12, 2005 5:48 PM
To: Stefan Reinauer
Cc: linuxbios at openbios.org
Subject: Re: [LinuxBIOS] makefile for Windows

Apparently it does not run.
I started modifying the commands in the makefile, and started
compiling rombios.c
I am getting this error:
rombios.c:2662:1: pasting "(" and ""ata_cmd_data_in : read error\n""
does not give a valid preprocessing token
 
the source line is:
    BX_DEBUG_ATA("ata_cmd_data_in : read error\n");
Do you think it is due to the environment?
MiKL

Stefan Reinauer wrote:
* Toto Lebolo [050512 20:02]:
> I am trying to rebuild linux BIOS. I have installed the Windows
version of the
> compilers.
> Does the makefile run in windows? or just in Linux?

Find out and tell us, please!

You'll also need python installed.

Stefan



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From YhLu at tyan.com  Wed May 18 00:42:32 2005
From: YhLu at tyan.com (YhLu)
Date: Tue, 17 May 2005 15:42:32 -0700
Subject: [LinuxBIOS] www.linuxbios.org
Message-ID: <3174569B9743D511922F00A0C943142309F80EDD@TYANWEB>

someone report to me that www.linuxbios.org is down.

You'd better to direct them to wiki.linuxbios.org in the page.

YH



From YhLu at tyan.com  Wed May 18 00:43:01 2005
From: YhLu at tyan.com (YhLu)
Date: Tue, 17 May 2005 15:43:01 -0700
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <3174569B9743D511922F00A0C943142309F80EDE@TYANWEB>

what is your HW design about that?

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Tuesday, May 17, 2005 3:00 PM
> To: YhLu; rminnich at lanl.gov
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] CK804 suggestions
> 
> Your approach only allows the MAC address to be in the EEPROM 
> or the romstrap.  Every motherboard would have to put the 
> EEPROM in exactly the same place for this to be a general 
> solution.  Not likely.  
> Neither place is a general solution.   
> Getting the MAC address is board specific and belongs in mainboard.
> 
> Steve
> 
> -----Original Message-----
> From: YhLu [mailto:YhLu at tyan.com]
> Sent: Tuesday, May 17, 2005 5:37 PM
> To: Ronald G. Minnich; Kimball, Stephen
> Cc: YhLu at tyan.com; linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] CK804 suggestions
> 
> don't need,
> 1. good hw design should use one serial EEPROM to store MAC 
> address, So when flash the BIOS, the EEPROM is still there.
> 	in ck804_nic.c will read MAC from serial EEPROM in 
> SMBUS (bus num and device num is set in Mainboard Config.lb), 
> at first.
> 2. even for bad design, you can keep your own 
> romstrap.inc/lds in your mainboard dir, and modify Config.lb 
> to point corrent file.
> 	In such case, you need special flash util to keep your 
> MAC address or read the MAC address at first, and then set it back....
> 
> YH 
> 
> > -----Original Message-----
> > From: Ronald G. Minnich [mailto:rminnich at lanl.gov]
> > Sent: Tuesday, May 17, 2005 12:47 PM
> > To: Stephen.Kimball at bench.com
> > Cc: YhLu; linuxbios at openbios.org
> > Subject: Re: [LinuxBIOS] CK804 suggestions
> > 
> > 
> > 
> > On Tue, 17 May 2005 Stephen.Kimball at bench.com wrote:
> > 
> > > I'd like to suggest that the romstrap files be moved from
> > southbridge
> > > to mainboard, because the files are board specific with a
> > default MAC
> > > address.  Also the ck804_nic.c files needs a mainboard specific
> > > get_mac_address() that resides in mainboard.
> > 
> > YhLu, can you fix this? it's a good point.
> > 
> > ron
> > 
> 



From rminnich at lanl.gov  Wed May 18 00:50:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 16:50:01 -0600 (MDT)
Subject: [LinuxBIOS] CK804 suggestions
In-Reply-To: <3174569B9743D511922F00A0C943142309F80ED8@TYANWEB>
References: <3174569B9743D511922F00A0C943142309F80ED8@TYANWEB>
Message-ID: <Pine.LNX.4.58.0505171649260.18949@enigma.lanl.gov>



On Tue, 17 May 2005, YhLu wrote:

> In CMOS? unbelievable. 

yeah, I had a node once with a mac of 00:00:00:00:00:00. I kid you not. 
Worked fine.

The manufacturer did this to save the cost of an SEEPROM.

ron



From rminnich at lanl.gov  Wed May 18 00:50:48 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 16:50:48 -0600 (MDT)
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: <20050517222025.20306.qmail@web60924.mail.yahoo.com>
References: <20050517222025.20306.qmail@web60924.mail.yahoo.com>
Message-ID: <Pine.LNX.4.58.0505171650430.18949@enigma.lanl.gov>

uh, bcc?

why bcc?

ron




From smithbone at gmail.com  Wed May 18 00:56:41 2005
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 17 May 2005 17:56:41 -0500
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: <Pine.LNX.4.58.0505171650430.18949@enigma.lanl.gov>
References: <20050517222025.20306.qmail@web60924.mail.yahoo.com>
	<Pine.LNX.4.58.0505171650430.18949@enigma.lanl.gov>
Message-ID: <8a0c367805051715565039cf2d@mail.gmail.com>

On 5/17/05, Ronald G. Minnich <rminnich at lanl.gov> wrote:
> uh, bcc?
> 
> why bcc?
> 

ADLO needs it to compile bochs bios.  Are you trying to compile ADLO?

-- 
Richard A. Smith



From rminnich at lanl.gov  Wed May 18 01:09:24 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 17:09:24 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
Message-ID: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>


let's see if it works in 24 hours.

ron



From toto_lebolo at yahoo.com  Wed May 18 01:35:19 2005
From: toto_lebolo at yahoo.com (Toto Lebolo)
Date: Tue, 17 May 2005 16:35:19 -0700 (PDT)
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: 6667
Message-ID: <20050517233519.33272.qmail@web60924.mail.yahoo.com>

Yes I am trying to compile ADLO.
MiKL~

Richard Smith <smithbone at gmail.com> wrote:
On 5/17/05, Ronald G. Minnich wrote:
> uh, bcc?
> 
> why bcc?
> 

ADLO needs it to compile bochs bios. Are you trying to compile ADLO?

-- 
Richard A. Smith

		
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From chromi at chromatix.demon.co.uk  Wed May 18 02:34:42 2005
From: chromi at chromatix.demon.co.uk (Jonathan Morton)
Date: Wed, 18 May 2005 01:34:42 +0100
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
Message-ID: <9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>

> let's see if it works in 24 hours.

Trying it right now, from a clean DNS server, I get "This page 
intentionally left blank".

--------------------------------------------------------------
from:     Jonathan "Chromatix" Morton
mail:     chromi at chromatix.demon.co.uk
website:  http://www.chromatix.uklinux.net/
tagline:  The key to knowledge is not to rely on people to teach you it.




From rminnich at lanl.gov  Wed May 18 04:52:12 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Tue, 17 May 2005 20:52:12 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
Message-ID: <Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>

yeah, easydns is not being my friend today.

ron




From lists at endian.se  Wed May 18 07:20:01 2005
From: lists at endian.se (Kjell Svensson)
Date: Wed, 18 May 2005 07:20:01 +0200
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
References: <56ce23fbc454b4afca705f058d43d46c@endian.se>
	<Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
Message-ID: <76fbb2a418e7ae79792542582c344597@endian.se>

Thats good to know, I have really doubted this branch to be known to 
work at all.

I'm using FILO 0.4.2, don't think I've done any unusual config or so 
there. Is there something special with FILO that could go wrong?
I have missed memtest86. I suppose it's in the LinuxBIOS tree? I'll 
give it a try when I'm back with this tomorrow.

Thanks for your advice!
/Kjell


On 18 maj 2005, at 00:02, Ronald G. Minnich wrote:

>
>
> On Tue, 17 May 2005, Kjell Svensson wrote:
>
>> - Has anybody reported the smartcore-p5 support in v1 to actually 
>> work?
>
> I had a whole stack of them working years ago. They really ought to 
> work.
>
> I think it's a filo problem, could you try booting memtest86 instead?
>
> ron
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios




From lists at endian.se  Wed May 18 07:20:41 2005
From: lists at endian.se (Kjell Svensson)
Date: Wed, 18 May 2005 07:20:41 +0200
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <Pine.LNX.4.58.0505171605570.18949@enigma.lanl.gov>
References: <56ce23fbc454b4afca705f058d43d46c@endian.se>
	<Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
	<Pine.LNX.4.58.0505171605570.18949@enigma.lanl.gov>
Message-ID: <3cc9bb94ebb91f3693e5986cfdc31b2e@endian.se>

I'd really appreciate that! :-)

Thanks,
/Kjell


On 18 maj 2005, at 00:06, Ronald G. Minnich wrote:

>
>
> On Tue, 17 May 2005, Ronald G. Minnich wrote:
>
>>
>>
>> On Tue, 17 May 2005, Kjell Svensson wrote:
>>
>>> - Has anybody reported the smartcore-p5 support in v1 to actually 
>>> work?
>>
>> I had a whole stack of them working years ago. They really ought to 
>> work.
>
> hey, I could try to see if mine still boots and, if so, send you the 
> flash
> image ...
>
> it's old.
>
> ron
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios




From Peter.VanEchaute at bench.com  Wed May 18 14:08:59 2005
From: Peter.VanEchaute at bench.com (Peter.VanEchaute at bench.com)
Date: Wed, 18 May 2005 08:08:59 -0400
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <9B124F08B3EFDA4F8813B05102DC719502109CCF@nh-ex01.bench.com>

I too have done a few boards where the MAC address has been stored in the flash device.  The idea was to save on cost, the same as yours Ron.  This matter of board design is exactly that, board specific.  The CK804 has a specific place in flash that the MAC(s) should be placed anyways, in the ROMSTRAP+0x30.  I noticed you knew that YH.  As the CK804 area is chipset specific, it shouldn't be board specific.  So what I did is placed a define for your TYAN board, at least until you take your stuff out.  In the code, it reads the ROMSTRAP offset + 0x30.  Each MAC address is an +0x8 from there if you have more than one.  This is exactly how the CK804 BIOS Porting guides state to do it.  Now do you have to listen to me or the guide, no.  It's just my $0.02.

On a side note YH, you have a bug in the ck804_nic.c.  I hope it's OK to point this out.  But the MAC address is supposed to be placed into the Memmory Mapped IO (MMIO) area at offset 0xA8, and not in the device configuration space...

My recommendation...
        // set that into NIC MMIO
        write32(mac_l, base + 0xA8);
        write32(mac_h, base + 0xAC);

your code...
        // set that into NIC
        pci_write_config32(dev, 0xa8, mac_l);
        pci_write_config32(dev, 0xac, mac_h);




Here is the code I recommend(or at least something close to it)...


#include <console/console.h>
#include <device/device.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "ck804.h"

#define MAC_DBG      1
#define TYANs2895    0



uint8_t read8(unsigned long addr)
{
        return *((volatile uint8_t *)(addr));
}

uint16_t read16(unsigned long addr)
{
        return *((volatile uint16_t *)(addr));
}

uint32_t read32(unsigned long addr)
{
        return *((volatile uint32_t *)(addr));
}

void write8(unsigned long addr, uint8_t value)
{
        *((volatile uint8_t *)(addr)) = value;
}

void write16(unsigned long addr, uint16_t value)
{
        *((volatile uint16_t *)(addr)) = value;
}

void write32(unsigned long addr, uint32_t value)
{
        *((volatile uint32_t *)(addr)) = value;
}



static void nic_init(struct device *dev)
{
        uint32_t dword, old;
        uint32_t mac_h, mac_l;
        static uint32_t nic_index = 0;
        unsigned long mac_pos;
        uint32_t base;
        struct resource *res;
#define NvRegPhyInterface  0xC0
#define PHY_RGMII          0x10000000

        res = find_resource(dev, 0x10);
        base = res->base;
        write32(base + NvRegPhyInterface, PHY_RGMII);

        old = dword = pci_read_config32(dev, 0x30);
        dword &= ~(0xf);
        dword |= 0xf;
        if(old != dword) {
                pci_write_config32(dev, 0x30 , dword);
        }

#if TYAN
        int eeprom_valid = 0;
        struct southbridge_nvidia_ck804_config *conf;

        conf = dev->chip_info;
       
        if(conf->mac_eeprom_smbus != 0) { 
//      read MAC address from EEPROM at first
                struct device *dev_eeprom;
                dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);

                if(dev_eeprom) {
                //      if that is valid we will use that
                        unsigned char dat[6];
                        int status;
                        int i;
                        for(i=0;i<6;i++) {
                                status = smbus_read_byte(dev_eeprom, i);
                                if(status < 0) break;
                                dat[i] = status & 0xff;
                        }
                        if(status >= 0) {
                                mac_l = 0;
                                for(i=3;i>=0;i--) {
                                        mac_l <<= 8;
                                        mac_l += dat[i];
                                }
                                if(mac_l != 0xffffffff) {
                                        mac_l += nic_index;
                                        mac_h = 0;
                                        for(i=5;i>=4;i--) {
                                                mac_h <<= 8;
                                                mac_h += dat[i];
                                        }
                                        eeprom_valid = 1;       
                                }
                        }
                }
        }
//      if that is invalid we will read that from romstrap
        if(!eeprom_valid) {
                mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
                mac_l = read32(mac_pos) + nic_index;
                mac_h = read32(mac_pos + 4);
        }
#else
        // read directly from rom_strap
        mac_pos = read8(0xffffffe0); // refer to romstrap.inc
        mac_pos |= (read8(0xffffffe1)<<8);
        mac_pos |= (read8(0xffffffe2)<<16);
        mac_pos |= (read8(0xffffffe3)<<24);

        mac_pos += 0x30;
        for ( dword = nic_index ; dword > 0 ; dword-- )
        {
                mac_pos += 8;
        }

        mac_l = read32(mac_pos);
        mac_h = read32(mac_pos + 4);
#endif

        // set that into NIC MMIO
        write32(mac_l, base + 0xA8);
        write32(mac_h, base + 0xAC);

#if MAC_DBG
        printk_info("MAC:\tMAC Address is: %02x:%02x:%02x:%02x:%02x:%02x\n",
                        read8(base + 0xAD), read8(base + 0xAC),
                        read8(base + 0xAB), read8(base + 0xAA),
                        read8(base + 0xA9), read8(base + 0xA8));
#endif

        nic_index++;

#if CONFIG_PCI_ROM_RUN == 1
        pci_dev_init(dev);// it will init option rom
#endif

}



static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
        pci_write_config32(dev, 0x40,
                ((device & 0xffff) << 16) | (vendor & 0xffff));
}

static struct pci_operations lops_pci = {
        .set_subsystem = lpci_set_subsystem,
};

static struct device_operations nic_ops  = {
        .read_resources   = pci_dev_read_resources,
        .set_resources    = pci_dev_set_resources,
        .enable_resources = pci_dev_enable_resources,
        .init             = nic_init,
        .scan_bus         = 0,
//      .enable           = ck804_enable,
        .ops_pci          = &lops_pci,
};
static struct pci_driver nic_driver __pci_driver = {
        .ops    = &nic_ops,
        .vendor = PCI_VENDOR_ID_NVIDIA,
        .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC,
};
static struct pci_driver nic_bridge_driver __pci_driver = {
        .ops    = &nic_ops,
        .vendor = PCI_VENDOR_ID_NVIDIA,
        .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE,
};








From Stephen.Kimball at bench.com  Wed May 18 14:27:16 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed, 18 May 2005 08:27:16 -0400
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C47@nh-ex01.bench.com>

We are a contract manufacturer and don't have a design yet.
We are working with the nVidia CK804 Customer Reference Board.
They read the MAC address from the ROMSTRAP table.
It works, but it's not a good design.

Steve

-----Original Message-----
From: YhLu [mailto:YhLu at tyan.com] 
Sent: Tuesday, May 17, 2005 6:43 PM
To: Kimball, Stephen; rminnich at lanl.gov
Cc: linuxbios at openbios.org
Subject: RE: [LinuxBIOS] CK804 suggestions

what is your HW design about that?

YH 

 



From adam at cfar.umd.edu  Wed May 18 17:41:15 2005
From: adam at cfar.umd.edu (Adam Sulmicki)
Date: Wed, 18 May 2005 11:41:15 -0400 (EDT)
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: <20050517233519.33272.qmail@web60924.mail.yahoo.com>
References: <20050517233519.33272.qmail@web60924.mail.yahoo.com>
Message-ID: <Pine.BSF.4.62.0505181139010.74384@www.missl.cs.umd.edu>


>> uh, bcc?
>> why bcc?
> ADLO needs it to compile bochs bios. Are you trying to compile ADLO?
> Yes I am trying to compile ADLO.

note that ADLO uses "Bruce's C compiler" not "Borland's c compiler". (it 
is part of dev86 package, it seem still come with suse, but not anymore 
with fedora redhat core).

-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers



From yinghailu at gmail.com  Wed May 18 18:26:35 2005
From: yinghailu at gmail.com (yhlu)
Date: Wed, 18 May 2005 09:26:35 -0700
Subject: [LinuxBIOS] CK804 suggestions
In-Reply-To: <9B124F08B3EFDA4F8813B05102DC719502109CCF@nh-ex01.bench.com>
References: <9B124F08B3EFDA4F8813B05102DC719502109CCF@nh-ex01.bench.com>
Message-ID: <2ea3fae105051809265c1dac00@mail.gmail.com>

Peter,

1. About MAC set, that is according to Nvidia DOC, I guess MMIO is
some better thatn PCI config. the reason is BIOS set that in PCI
Config, and NIC controller will fill that into MMIO. The side effects
is if the CK804 DEV start from 0, it works well. but if it is from 1,
the NIC may fail to get MAC from the PCI Config.... timing...?
I will try MMIO to see if it can use dev num from 1.
2. You don't like SEEPROM? the code should try the SMBUS at first, and
if you do not set that (SMBUS num in Config.lb), it will be skipped.
3. readl.... has been defined in arch/io.h

YH



From Peter.VanEchaute at bench.com  Wed May 18 19:16:16 2005
From: Peter.VanEchaute at bench.com (Peter.VanEchaute at bench.com)
Date: Wed, 18 May 2005 13:16:16 -0400
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <9B124F08B3EFDA4F8813B05102DC719502109CD0@nh-ex01.bench.com>

1.  I didn't see that 0xA8 in the device config space was for the MAC address.  It doesn't show it in the register spec I received.  I'll give it a try when I get a chance.  I only saw that offset 0xA8 in the MMIO space was for it.

2.  Taking a closer look at it, I do like it.  Maybe just change the if(!eeprom_valid) part to read from the ROMSTRAP the way I had it.  The reason I like my way of reading the ROMSTRAPs MAC is because you have it at a fixed address.  But the ROMSTRAP could actually be used to setup lots and lots of device registers, if chosen to do so.  Thus pushing that address lower.

        // read directly from rom_strap
        mac_pos = read8(0xffffffe0); // refer to romstrap.inc 
        mac_pos |= (read8(0xffffffe1)<<8);
        mac_pos |= (read8(0xffffffe2)<<16);
        mac_pos |= (read8(0xffffffe3)<<24);

        mac_pos += 0x30;
        for ( dword = nic_index ; dword > 0 ; dword-- )
        {
                mac_pos += 8;
        }

        mac_l = read32(mac_pos);
        mac_h = read32(mac_pos + 4);

Sorry I didn't look at it more closely.

3.  yeah, I saw that.  I was just using something familiar.  Thanks.




From yinghailu at gmail.com  Wed May 18 19:24:00 2005
From: yinghailu at gmail.com (yhlu)
Date: Wed, 18 May 2005 10:24:00 -0700
Subject: [LinuxBIOS] CK804 suggestions
In-Reply-To: <9B124F08B3EFDA4F8813B05102DC719502109CD0@nh-ex01.bench.com>
References: <9B124F08B3EFDA4F8813B05102DC719502109CD0@nh-ex01.bench.com>
Message-ID: <2ea3fae1050518102428c5082b@mail.gmail.com>

1. In NV NDA doc.
2. That is trick, in romstrap.inc, rspointers must be 0xffffffe0, So
just put MAC below that in 16bytes, and it can be fixed. actually it
is not some kind of part romstrap, just want to make it in fixed
positon. Fixed position is better than floating..., it may make your
flash util more easier to find it.

YH

        .long 0x81543266                        // 30h, MAC address
low 4 byte ---> keep it in 0xffffffd0
        .long 0x000000E0                        // 34h, MAC address high 4 byte

        .long 0x002309CE                        // 38h, UUID low 4 byte
        .long 0x00E08100                        // 3Ch, UUID high 4 byte

rspointers:
        .long rstables                          // It will be 0xffffffe0
        .long rstables
        .long rstables
        .long rstables

        .globl __romstrap_end



From Stephen.Kimball at bench.com  Wed May 18 20:15:08 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed, 18 May 2005 14:15:08 -0400
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <9B124F08B3EFDA4F8813B05102DC719502905B04@nh-ex01.bench.com>

OK, so why not use a label to get the MAC address at 0xffffffd0?

Steve

-----Original Message-----
From: linuxbios-bounces at openbios.org [mailto:linuxbios-bounces at openbios.org] On Behalf Of yhlu
Sent: Wednesday, May 18, 2005 1:24 PM
To: Van Echaute, Peter
Cc: linuxbios at openbios.org
Subject: Re: [LinuxBIOS] CK804 suggestions

1. In NV NDA doc.
2. That is trick, in romstrap.inc, rspointers must be 0xffffffe0, So
just put MAC below that in 16bytes, and it can be fixed. actually it
is not some kind of part romstrap, just want to make it in fixed
positon. Fixed position is better than floating..., it may make your
flash util more easier to find it.

YH

        .long 0x81543266                        // 30h, MAC address
low 4 byte ---> keep it in 0xffffffd0
        .long 0x000000E0                        // 34h, MAC address high 4 byte

        .long 0x002309CE                        // 38h, UUID low 4 byte
        .long 0x00E08100                        // 3Ch, UUID high 4 byte

rspointers:
        .long rstables                          // It will be 0xffffffe0
        .long rstables
        .long rstables
        .long rstables

        .globl __romstrap_end

_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios



From YhLu at tyan.com  Wed May 18 20:40:14 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 18 May 2005 11:40:14 -0700
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <3174569B9743D511922F00A0C943142309F80FBC@TYANWEB>

don't need. Also if do that, the linker will complain the overlapping.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 18, 2005 11:15 AM
> To: yinghailu at gmail.com; Peter.VanEchaute at bench.com
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] CK804 suggestions
> 
> OK, so why not use a label to get the MAC address at 0xffffffd0?
> 
> Steve
> 
> -----Original Message-----
> From: linuxbios-bounces at openbios.org 
> [mailto:linuxbios-bounces at openbios.org] On Behalf Of yhlu
> Sent: Wednesday, May 18, 2005 1:24 PM
> To: Van Echaute, Peter
> Cc: linuxbios at openbios.org
> Subject: Re: [LinuxBIOS] CK804 suggestions
> 
> 1. In NV NDA doc.
> 2. That is trick, in romstrap.inc, rspointers must be 
> 0xffffffe0, So just put MAC below that in 16bytes, and it can 
> be fixed. actually it is not some kind of part romstrap, just 
> want to make it in fixed positon. Fixed position is better 
> than floating..., it may make your flash util more easier to find it.
> 
> YH
> 
>         .long 0x81543266                        // 30h, MAC address
> low 4 byte ---> keep it in 0xffffffd0
>         .long 0x000000E0                        // 34h, MAC 
> address high 4 byte
> 
>         .long 0x002309CE                        // 38h, UUID 
> low 4 byte
>         .long 0x00E08100                        // 3Ch, UUID 
> high 4 byte
> 
> rspointers:
>         .long rstables                          // It will be 
> 0xffffffe0
>         .long rstables
>         .long rstables
>         .long rstables
> 
>         .globl __romstrap_end
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From hansolofalcon at worldnet.att.net  Wed May 18 21:17:06 2005
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Wed, 18 May 2005 15:17:06 -0400
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: <Pine.BSF.4.62.0505181139010.74384@www.missl.cs.umd.edu>
Message-ID: <013c01c55bde$35c509a0$6401a8c0@who5>

Hello from Gregg C Levine
Indeed it does. 
Over on the BOCHS list a few years earlier, about the same time the
ADLO project surfaced, one of the people there had created a patched
version to accommodate the peculiarities of the X86 processors from
Intel properly in their simulations. It had to do with the handling of
the MSR registers that Intel created for specific granularity within
the machine memory map. 

But that's my understanding of things. I don't quite recall how it was
originally created, let alone how the decision to do this was reached.

Most users of the BOCHS kit don't need to build their own BIOS images,
so there was no real reason to promote this issue.
-------------------
Gregg C Levine hansolofalcon at worldnet.att.net
------------------------------------------------------------
"The Force will be with you...Always." Obi-Wan Kenobi
"Use the Force, Luke."? Obi-Wan Kenobi

> -----Original Message-----
> From: linuxbios-bounces at openbios.org
[mailto:linuxbios-bounces at openbios.org]
> On Behalf Of Adam Sulmicki
> Sent: Wednesday, May 18, 2005 11:41 AM
> To: Toto Lebolo
> Cc: linuxbios at openbios.org; Gregg C Levine
> Subject: Re: [LinuxBIOS] makefile for Windows
> 
> 
> >> uh, bcc?
> >> why bcc?
> > ADLO needs it to compile bochs bios. Are you trying to compile
ADLO?
> > Yes I am trying to compile ADLO.
> 
> note that ADLO uses "Bruce's C compiler" not "Borland's c compiler".
(it
> is part of dev86 package, it seem still come with suse, but not
anymore
> with fedora redhat core).
> 
> --
> Adam Sulmicki
> http://www.eax.com 	The Supreme Headquarters of the 32 bit
registers
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios





From YhLu at tyan.com  Wed May 18 21:42:31 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 18 May 2005 12:42:31 -0700
Subject: [LinuxBIOS] Next step with LinuxBIOS
Message-ID: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>

with Linuxtiny,  I enable the 
1. serial console
2. tcp/ip
3. smp ( i need apic...)
4. usb storage
5. lsi scsi disk
6. ide

the kernel get 682k.

actually space for normal payloads is 1024-128-90=806k.

how about the next step?
another small program to provide 
1. menu support
2. flash
3. cmos setting
4. boot from Net.. (copy to ramdisk and kexec)
5. boot from disk...(kexec...)

the small program in ramdisk or initramfs...?

Please comment

YH



From Stephen.Kimball at bench.com  Wed May 18 21:43:05 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed, 18 May 2005 15:43:05 -0400
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C49@nh-ex01.bench.com>

I get "undefined reference to `mac_address'". The romstrap.inc is included in mainboard's Config.lb, but it's not linked with ck804_nic.o.
So you need to use a hardcoded address.

Steve

-----Original Message-----
From: YhLu [mailto:YhLu at tyan.com] 
Sent: Wednesday, May 18, 2005 2:40 PM
To: Kimball, Stephen; yinghailu at gmail.com; Van Echaute, Peter
Cc: linuxbios at openbios.org
Subject: RE: [LinuxBIOS] CK804 suggestions

don't need. Also if do that, the linker will complain the overlapping.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 18, 2005 11:15 AM
> To: yinghailu at gmail.com; Peter.VanEchaute at bench.com
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] CK804 suggestions
> 
> OK, so why not use a label to get the MAC address at 0xffffffd0?
> 
> Steve
> 
> -----Original Message-----
> From: linuxbios-bounces at openbios.org 
> [mailto:linuxbios-bounces at openbios.org] On Behalf Of yhlu
> Sent: Wednesday, May 18, 2005 1:24 PM
> To: Van Echaute, Peter
> Cc: linuxbios at openbios.org
> Subject: Re: [LinuxBIOS] CK804 suggestions
> 
> 1. In NV NDA doc.
> 2. That is trick, in romstrap.inc, rspointers must be 
> 0xffffffe0, So just put MAC below that in 16bytes, and it can 
> be fixed. actually it is not some kind of part romstrap, just 
> want to make it in fixed positon. Fixed position is better 
> than floating..., it may make your flash util more easier to find it.
> 
> YH
> 
>         .long 0x81543266                        // 30h, MAC address
> low 4 byte ---> keep it in 0xffffffd0
>         .long 0x000000E0                        // 34h, MAC 
> address high 4 byte
> 
>         .long 0x002309CE                        // 38h, UUID 
> low 4 byte
>         .long 0x00E08100                        // 3Ch, UUID 
> high 4 byte
> 
> rspointers:
>         .long rstables                          // It will be 
> 0xffffffe0
>         .long rstables
>         .long rstables
>         .long rstables
> 
>         .globl __romstrap_end
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From YhLu at tyan.com  Wed May 18 22:08:23 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 18 May 2005 13:08:23 -0700
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <3174569B9743D511922F00A0C943142309F80FE7@TYANWEB>

send out the Config.lb 

You need to have romstrap.inc and romstrap.lds in your MB dir.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 18, 2005 12:43 PM
> To: YhLu; yinghailu at gmail.com
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] CK804 suggestions
> 
> I get "undefined reference to `mac_address'". The 
> romstrap.inc is included in mainboard's Config.lb, but it's 
> not linked with ck804_nic.o.
> So you need to use a hardcoded address.
> 
> Steve



From Stephen.Kimball at bench.com  Wed May 18 22:02:13 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed, 18 May 2005 16:02:13 -0400
Subject: [LinuxBIOS] CK804 suggestions
Message-ID: <9B124F08B3EFDA4F8813B05102DC719502905B07@nh-ex01.bench.com>

I agree with you... I can't use a label in the romstrap file.

-----Original Message-----
From: YhLu [mailto:YhLu at tyan.com] 
Sent: Wednesday, May 18, 2005 4:08 PM
To: Kimball, Stephen; yinghailu at gmail.com
Cc: linuxbios at openbios.org
Subject: RE: [LinuxBIOS] CK804 suggestions

send out the Config.lb 

You need to have romstrap.inc and romstrap.lds in your MB dir.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 18, 2005 12:43 PM
> To: YhLu; yinghailu at gmail.com
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] CK804 suggestions
> 
> I get "undefined reference to `mac_address'". The 
> romstrap.inc is included in mainboard's Config.lb, but it's 
> not linked with ck804_nic.o.
> So you need to use a hardcoded address.
> 
> Steve



From YhLu at tyan.com  Wed May 18 23:05:21 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 18 May 2005 14:05:21 -0700
Subject: [LinuxBIOS] RE: Next step with LinuxBIOS
Message-ID: <3174569B9743D511922F00A0C943142309F80FF6@TYANWEB>

Good. spare 40k. I can put IB driver in it now.

YH

 

> -----Original Message-----
> From: Diego Calleja [mailto:diegocg at gmail.com] 
> Sent: Wednesday, May 18, 2005 1:21 PM
> To: YhLu
> Cc: rminnich at lanl.gov; ebiederman at lnxi.com; 
> stepan at openbios.org; ollie at lanl.gov; linuxbios at openbios.org; 
> linux-tiny at selenic.com; linux-kernel at vger.kernel.org
> Subject: Re: Next step with LinuxBIOS
> 
> El Wed, 18 May 2005 12:42:31 -0700,
> YhLu <YhLu at tyan.com> escribi?:
> 
> > 3. smp ( i need apic...)
> 
> Why? Can't you use "Local APIC support on uniprocessors" 
> (CONFIG_X86_UP_APIC)?
> 



From toto_lebolo at yahoo.com  Thu May 19 00:24:26 2005
From: toto_lebolo at yahoo.com (Toto Lebolo)
Date: Wed, 18 May 2005 15:24:26 -0700 (PDT)
Subject: [LinuxBIOS] makefile for Windows
In-Reply-To: 6667
Message-ID: <20050518222427.28484.qmail@web60911.mail.yahoo.com>

I am actually using Bruce's C compiler. But the DOS version. got it from
http://www.cix.co.uk/~mayday/dev86/Dev86dos-0.16.2.zip
 
I tried also to go back to the earlier ver 14. It is not compiling. I guess because I am the only one in the entire world using this in DOS/windows. The issue is environmental ==> the compiler cannot open a file or does not find the path etc.
 
I am going to give up here I think.
Thanks anyway.
mikl


Adam Sulmicki <adam at cfar.umd.edu> wrote:

>> uh, bcc?
>> why bcc?
> ADLO needs it to compile bochs bios. Are you trying to compile ADLO?
> Yes I am trying to compile ADLO.

note that ADLO uses "Bruce's C compiler" not "Borland's c compiler". (it 
is part of dev86 package, it seem still come with suse, but not anymore 
with fedora redhat core).

-- 
Adam Sulmicki
http://www.eax.com The Supreme Headquarters of the 32 bit registers

		
---------------------------------
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 Get on-the-go sports scores, stock quotes, news & more. Check it out!
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From bari at onelabs.com  Thu May 19 03:15:26 2005
From: bari at onelabs.com (Bari Ari)
Date: Wed, 18 May 2005 20:15:26 -0500
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
Message-ID: <428BE8AE.7000703@onelabs.com>

Is the wiki link gone?  http://wiki.linuxbios.org

-Bari



From diegocg at gmail.com  Wed May 18 22:20:44 2005
From: diegocg at gmail.com (Diego Calleja)
Date: Wed, 18 May 2005 22:20:44 +0200
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>
References: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>
Message-ID: <20050518222044.2135e923.diegocg@gmail.com>

El Wed, 18 May 2005 12:42:31 -0700,
YhLu <YhLu at tyan.com> escribi?:

> 3. smp ( i need apic...)

Why? Can't you use "Local APIC support on uniprocessors" (CONFIG_X86_UP_APIC)?



From stepan at openbios.org  Thu May 19 13:48:21 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu, 19 May 2005 13:48:21 +0200
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <428BE8AE.7000703@onelabs.com>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
	<428BE8AE.7000703@onelabs.com>
Message-ID: <20050519114821.GA9539@openbios.org>

* Bari Ari <bari at onelabs.com> [050519 03:15]:
> Is the wiki link gone?  http://wiki.linuxbios.org

yes. and so is snapshots.linuxbios.org

Ron, the DNS for linuxbios.org does not seem to be 80.190.231.112.

Stefan

 
 



From rminnich at lanl.gov  Thu May 19 16:36:40 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 08:36:40 -0600 (MDT)
Subject: [LinuxBIOS] www.linuxbios.org is back
Message-ID: <Pine.LNX.4.58.0505190836320.24293@enigma.lanl.gov>

and at the rightplace.

ron



From rminnich at lanl.gov  Thu May 19 16:43:01 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 08:43:01 -0600 (MDT)
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <76fbb2a418e7ae79792542582c344597@endian.se>
References: <56ce23fbc454b4afca705f058d43d46c@endian.se>
	<Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
	<76fbb2a418e7ae79792542582c344597@endian.se>
Message-ID: <Pine.LNX.4.58.0505190842520.24293@enigma.lanl.gov>

google memtest86 or I can try to find my working binary. 

ron




From rminnich at lanl.gov  Thu May 19 16:54:18 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 08:54:18 -0600 (MDT)
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>
References: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>
Message-ID: <Pine.LNX.4.58.0505190852360.24293@enigma.lanl.gov>

YES, please send me your kernel config and I'd like to try this. The 
single biggest complaint we get on linubios is
- no command interface
- can't load a system from cdrom
- can't boot from arbitrary disk
- no command interface
- no command interface
- no command interface
- no command interface
- no command interface
- no command interface
- "we hate etherboot"
- "FILO does not do enough"
- "we want Open Firmware"

Oh, wait, that's more than one, but you get my drift. Please send config 
file!

I'd really like to get a kernel in there and start resolving these issues. 

ron





From rminnich at lanl.gov  Thu May 19 16:55:43 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 08:55:43 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <428BE8AE.7000703@onelabs.com>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
	<428BE8AE.7000703@onelabs.com>
Message-ID: <Pine.LNX.4.58.0505190855320.24293@enigma.lanl.gov>

it's all working again as of today. 

it took easydns a while to get this done correctly.

ron




From rminnich at lanl.gov  Thu May 19 16:56:39 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 08:56:39 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <20050519114821.GA9539@openbios.org>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
	<428BE8AE.7000703@onelabs.com> <20050519114821.GA9539@openbios.org>
Message-ID: <Pine.LNX.4.58.0505190856030.24293@enigma.lanl.gov>



On Thu, 19 May 2005, Stefan Reinauer wrote:

> yes. and so is snapshots.linuxbios.org
> 
> Ron, the DNS for linuxbios.org does not seem to be 80.190.231.112.

no, I wanted to just let easydns be the dns. I will now fix all the 
entries you want, should they all just be CNAMEs for linuxbios.org as the 
www and wiki are now?

ron



From bari at onelabs.com  Thu May 19 17:05:15 2005
From: bari at onelabs.com (Bari Ari)
Date: Thu, 19 May 2005 10:05:15 -0500
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <20050519114821.GA9539@openbios.org>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
	<428BE8AE.7000703@onelabs.com> <20050519114821.GA9539@openbios.org>
Message-ID: <428CAB2B.7040406@onelabs.com>

Stefan Reinauer wrote:
> * Bari Ari <bari at onelabs.com> [050519 03:15]:
> 
>>Is the wiki link gone?  http://wiki.linuxbios.org
> 
> 
> yes. and so is snapshots.linuxbios.org
> 
> Ron, the DNS for linuxbios.org does not seem to be 80.190.231.112.

Will  http://cvs.sourceforge.net/cvstarballs/freebios-cvsroot.tar.bz2 
be taken down for good as well?

-Bari



From stepan at openbios.org  Thu May 19 17:07:49 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Thu, 19 May 2005 17:07:49 +0200
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0505190856030.24293@enigma.lanl.gov>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
	<428BE8AE.7000703@onelabs.com> <20050519114821.GA9539@openbios.org>
	<Pine.LNX.4.58.0505190856030.24293@enigma.lanl.gov>
Message-ID: <20050519150749.GA15618@openbios.org>

* Ronald G. Minnich <rminnich at lanl.gov> [050519 16:56]:
> 
> 
> On Thu, 19 May 2005, Stefan Reinauer wrote:
> 
> > yes. and so is snapshots.linuxbios.org
> > 
> > Ron, the DNS for linuxbios.org does not seem to be 80.190.231.112.
> 
> no, I wanted to just let easydns be the dns. I will now fix all the 
> entries you want, should they all just be CNAMEs for linuxbios.org as the 
> www and wiki are now?
 
yes, that's perfect.




From tyson at irobot.com  Thu May 19 17:16:26 2005
From: tyson at irobot.com (Tyson Sawyer)
Date: Thu, 19 May 2005 11:16:26 -0400
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <Pine.LNX.4.58.0505190852360.24293@enigma.lanl.gov>
References: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>
	<Pine.LNX.4.58.0505190852360.24293@enigma.lanl.gov>
Message-ID: <428CADCA.5000302@irobot.com>

Ronald G. Minnich wrote:
> YES, please send me your kernel config and I'd like to try this. The 
> single biggest complaint we get on linubios is
> - no command interface
> - can't load a system from cdrom
> - can't boot from arbitrary disk
> - no command interface
> - no command interface
> - no command interface
> - no command interface
> - no command interface
> - no command interface
> - "we hate etherboot"
> - "FILO does not do enough"
> - "we want Open Firmware"
> 
> Oh, wait, that's more than one, but you get my drift. Please send config 
> file!
> 
> I'd really like to get a kernel in there and start resolving these issues. 

I put a command line interface on Linuxbios v1 a LOOOONG time ago and we 
are still using it.

...but at least at the time you weren't interested in the patches. ;-)

We use it to select a kernel image in the ROM, the kernel command line 
options and optionally select a initrd image from ROM.   ...we have lots 
of ROM. ;-)

Cheers!
Ty

-- 
Tyson D Sawyer                     iRobot Corporation
Lead Systems Engineer              Government & Industrial Robotics
tsawyer at irobot.com                 Robots for the Real World
781-345-0200 ext 3329              http://www.irobot.com



From rminnich at lanl.gov  Thu May 19 17:26:05 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 09:26:05 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <428CAB2B.7040406@onelabs.com>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
	<428BE8AE.7000703@onelabs.com>
	<20050519114821.GA9539@openbios.org> <428CAB2B.7040406@onelabs.com>
Message-ID: <Pine.LNX.4.58.0505190925230.24293@enigma.lanl.gov>



On Thu, 19 May 2005, Bari Ari wrote:

> Will http://cvs.sourceforge.net/cvstarballs/freebios-cvsroot.tar.bz2 be
> taken down for good as well?

I sure hope so, or is that still needed.

ron



From rminnich at lanl.gov  Thu May 19 17:36:23 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 09:36:23 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <20050519150749.GA15618@openbios.org>
References: <Pine.LNX.4.58.0505171709140.18949@enigma.lanl.gov>
	<9c7fbf5b7c01b1bad7af4cf7b1636b77@chromatix.demon.co.uk>
	<Pine.LNX.4.58.0505172052030.20321@enigma.lanl.gov>
	<428BE8AE.7000703@onelabs.com> <20050519114821.GA9539@openbios.org>
	<Pine.LNX.4.58.0505190856030.24293@enigma.lanl.gov>
	<20050519150749.GA15618@openbios.org>
Message-ID: <Pine.LNX.4.58.0505190936140.24293@enigma.lanl.gov>

ok, just added snapshots, any others?

ron




From rminnich at lanl.gov  Thu May 19 17:41:43 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 09:41:43 -0600 (MDT)
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <428CADCA.5000302@irobot.com>
References: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>
	<Pine.LNX.4.58.0505190852360.24293@enigma.lanl.gov>
	<428CADCA.5000302@irobot.com>
Message-ID: <Pine.LNX.4.58.0505190941190.24293@enigma.lanl.gov>



On Thu, 19 May 2005, Tyson Sawyer wrote:

> ...but at least at the time you weren't interested in the patches. ;-)

yeah, I remember, I was still hanging on to the 'use linux' idea. 

I'd like to see it sometime ..

ron



From bari at onelabs.com  Thu May 19 18:05:15 2005
From: bari at onelabs.com (Bari Ari)
Date: Thu, 19 May 2005 11:05:15 -0500
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <428CADCA.5000302@irobot.com>
References: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>	<Pine.LNX.4.58.0505190852360.24293@enigma.lanl.gov>
	<428CADCA.5000302@irobot.com>
Message-ID: <428CB93B.9000807@onelabs.com>

Tyson Sawyer wrote:
> Ronald G. Minnich wrote:
> 
>>
>> I'd really like to get a kernel in there and start resolving these 
>> issues. 
> 
> 
> I put a command line interface on Linuxbios v1 a LOOOONG time ago and we 
> are still using it.
> 
> ...but at least at the time you weren't interested in the patches. ;-)
> 
> We use it to select a kernel image in the ROM, the kernel command line 
> options and optionally select a initrd image from ROM.   ...we have lots 
> of ROM. ;-)

Just FYI for all the LPC Flash users, SST is just releasing a 16 Mbit 
LPC Firmware Flash 
http://www.sst.com/products.xhtml/serial_flash/49/SST49LF016C
Plenty of room for kernels in ROM now.

-Bari



From rminnich at lanl.gov  Thu May 19 18:22:02 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 10:22:02 -0600 (MDT)
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <428CB93B.9000807@onelabs.com>
References: <3174569B9743D511922F00A0C943142309F80FE2@TYANWEB>
	<Pine.LNX.4.58.0505190852360.24293@enigma.lanl.gov>
	<428CADCA.5000302@irobot.com> <428CB93B.9000807@onelabs.com>
Message-ID: <Pine.LNX.4.58.0505191021550.24293@enigma.lanl.gov>



On Thu, 19 May 2005, Bari Ari wrote:

> Just FYI for all the LPC Flash users, SST is just releasing a 16 Mbit LPC
> Firmware Flash http://www.sst.com/products.xhtml/serial_flash/49/SST49LF016C
> Plenty of room for kernels in ROM now.

ah, heaven.

ron



From a.mimms at f5.com  Thu May 19 18:58:12 2005
From: a.mimms at f5.com (Alan Mimms)
Date: Thu, 19 May 2005 09:58:12 -0700
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
Message-ID: <7D7AEA925A7F724194B1521C75E622DCC69AC2@exchfive.olympus.f5net.com>

Hey, what about stucking the command line and utility aspects of u-boot
(u-boot.sf.net) onto LinuxBIOS?  I have been toying with the idea of
doing that for months now.  Does anyone want this?

Alan Mimms, Senior Architect
F5 Networks, Inc.  Spokane Development Center
1322 North Whitman Lane
Liberty Lake, Washington   99019
v: 509-343-3524   f: 509-343-3501
 

-----Original Message-----
From: linuxbios-bounces at openbios.org
[mailto:linuxbios-bounces at openbios.org] On Behalf Of Tyson Sawyer
Sent: Thursday, May 19, 2005 8:16 AM
To: Ronald G. Minnich
Cc: linuxbios at openbios.org
Subject: Re: [LinuxBIOS] Re: Next step with LinuxBIOS
Importance: Low

Ronald G. Minnich wrote:
> YES, please send me your kernel config and I'd like to try this. The 
> single biggest complaint we get on linubios is
> - no command interface
> - can't load a system from cdrom
> - can't boot from arbitrary disk
> - no command interface
> - no command interface
> - no command interface
> - no command interface
> - no command interface
> - no command interface
> - "we hate etherboot"
> - "FILO does not do enough"
> - "we want Open Firmware"
> 
> Oh, wait, that's more than one, but you get my drift. Please send
config 
> file!
> 
> I'd really like to get a kernel in there and start resolving these
issues. 

I put a command line interface on Linuxbios v1 a LOOOONG time ago and we

are still using it.

...but at least at the time you weren't interested in the patches. ;-)

We use it to select a kernel image in the ROM, the kernel command line 
options and optionally select a initrd image from ROM.   ...we have lots

of ROM. ;-)

Cheers!
Ty

-- 
Tyson D Sawyer                     iRobot Corporation
Lead Systems Engineer              Government & Industrial Robotics
tsawyer at irobot.com                 Robots for the Real World
781-345-0200 ext 3329              http://www.irobot.com

_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios



From rminnich at lanl.gov  Thu May 19 19:07:12 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 11:07:12 -0600 (MDT)
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <7D7AEA925A7F724194B1521C75E622DCC69AC2@exchfive.olympus.f5net.com>
References: <7D7AEA925A7F724194B1521C75E622DCC69AC2@exchfive.olympus.f5net.com>
Message-ID: <Pine.LNX.4.58.0505191106460.24293@enigma.lanl.gov>



On Thu, 19 May 2005, Alan Mimms wrote:

> Hey, what about stucking the command line and utility aspects of u-boot
> (u-boot.sf.net) onto LinuxBIOS?  I have been toying with the idea of
> doing that for months now.  Does anyone want this?

sure, why not try that too. I keep thinking we ought to see what we can 
use from u-boot, since it's nice work.

ron



From rminnich at lanl.gov  Thu May 19 19:11:15 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 11:11:15 -0600 (MDT)
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <Pine.LNX.4.58.0505191106460.24293@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DCC69AC2@exchfive.olympus.f5net.com>
	<Pine.LNX.4.58.0505191106460.24293@enigma.lanl.gov>
Message-ID: <Pine.LNX.4.58.0505191110520.24293@enigma.lanl.gov>

although, that said, in my heart of hearts I really want to run a linux 
kernel in there, to avoid all the driver problems that come with other 
approaches. 

ron




From gwatson at lanl.gov  Thu May 19 20:02:11 2005
From: gwatson at lanl.gov (Greg Watson)
Date: Thu, 19 May 2005 12:02:11 -0600
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <Pine.LNX.4.58.0505191106460.24293@enigma.lanl.gov>
References: <7D7AEA925A7F724194B1521C75E622DCC69AC2@exchfive.olympus.f5net.com>
	<Pine.LNX.4.58.0505191106460.24293@enigma.lanl.gov>
Message-ID: <DF16CD65-A578-4F6D-B073-D754B39E487A@lanl.gov>


On May 19, 2005, at 11:07 AM, Ronald G. Minnich wrote:

>
>
> On Thu, 19 May 2005, Alan Mimms wrote:
>
>
>> Hey, what about stucking the command line and utility aspects of u- 
>> boot
>> (u-boot.sf.net) onto LinuxBIOS?  I have been toying with the idea of
>> doing that for months now.  Does anyone want this?
>>
>
> sure, why not try that too. I keep thinking we ought to see what we  
> can
> use from u-boot, since it's nice work.
>
> ron
>

This is provided with the FILO code I added to the linuxbios tree.  
Someone could try and get that going (it was working for PPC but not  
x86). You enable it by setting the CONFIG_FS_STREAM option.

Greg



From YhLu at tyan.com  Thu May 19 20:43:56 2005
From: YhLu at tyan.com (YhLu)
Date: Thu, 19 May 2005 11:43:56 -0700
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
Message-ID: <3174569B9743D511922F00A0C943142309F8111C@TYANWEB>

My question:
1. use initrd to put that small program?
2. what kind of features needed by that small program?

YH 

> -----Original Message-----
> From: Ronald G. Minnich [mailto:rminnich at lanl.gov] 
> Sent: Thursday, May 19, 2005 10:11 AM
> To: Alan Mimms
> Cc: linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] Re: Next step with LinuxBIOS
> 
> although, that said, in my heart of hearts I really want to 
> run a linux kernel in there, to avoid all the driver problems 
> that come with other approaches. 
> 
> ron
> 
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From lists at endian.se  Thu May 19 20:56:59 2005
From: lists at endian.se (Kjell Svensson)
Date: Thu, 19 May 2005 20:56:59 +0200
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <Pine.LNX.4.58.0505190844570.24293@enigma.lanl.gov>
References: <56ce23fbc454b4afca705f058d43d46c@endian.se>
	<Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
	<Pine.LNX.4.58.0505171605570.18949@enigma.lanl.gov>
	<3cc9bb94ebb91f3693e5986cfdc31b2e@endian.se>
	<Pine.LNX.4.58.0505190844570.24293@enigma.lanl.gov>
Message-ID: <12863346846117bbd114fb77f98624c6@endian.se>

Thanks a million Ron!
I'll try this image as soon as i get back into the lab tomorrow. I 
haven't had time to try your memtest suggestion yet either but I'll try 
that as well then. I know where to get memtest86, and I've used it 
before - no problem.
Ultimately, my goal is to generate a 256kB image that I can use to 
"upgrade" the 256kB BIOS:es supplied by DigitalLogic, but at this point 
your 512kB image should be just fine since I've got that size of 
flashes in stock in the lab.

Since my last tries, I have only been able to come up with the 
following ideas:
- Im using gcc 3.3.2, could this be a too new toolset? Any point in 
trying 2.95.x?
- I noticed in the example config files that the etherboot image was 
suffixed .ebi, is this in anyway a different elf format than the one 
coming out of the linker after a normal build?? I have tried both 
building FILO and Etherboot myself, and also downloaded an etherboot 
from their rom-o-matic website which builds on-line, and to me the 
resulting elf files seems equivalent...

Cheers
/Kjell




On 19 maj 2005, at 16:45, Ronald G. Minnich wrote:

>
>
> no guarantees, but this might be it.
>
> it's a 512KB image. What size rom do you have?
>
> ron<smartcore.rom>




From rminnich at lanl.gov  Thu May 19 21:31:04 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 13:31:04 -0600 (MDT)
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <3174569B9743D511922F00A0C943142309F8111C@TYANWEB>
References: <3174569B9743D511922F00A0C943142309F8111C@TYANWEB>
Message-ID: <Pine.LNX.4.58.0505191330250.24293@enigma.lanl.gov>



On Thu, 19 May 2005, YhLu wrote:

> 1. use initrd to put that small program?

yeah. Kind of what we do with our clusters now. Kernel + initrd in flash 
-- or ide-flash if flash is too small.


> 2. what kind of features needed by that small program?

how about user-mode open-firmware, i.e. openbios.

ron



From yinghailu at gmail.com  Thu May 19 21:35:05 2005
From: yinghailu at gmail.com (yhlu)
Date: Thu, 19 May 2005 12:35:05 -0700
Subject: [LinuxBIOS] Re: Next step with LinuxBIOS
In-Reply-To: <Pine.LNX.4.58.0505191330250.24293@enigma.lanl.gov>
References: <3174569B9743D511922F00A0C943142309F8111C@TYANWEB>
	<Pine.LNX.4.58.0505191330250.24293@enigma.lanl.gov>
Message-ID: <2ea3fae1050519123538f3ff13@mail.gmail.com>

1. initrd could be 200k in flash...
2. will try kexec at first.....

YH

On 5/19/05, Ronald G. Minnich <rminnich at lanl.gov> wrote:
> 
> 
> On Thu, 19 May 2005, YhLu wrote:
> 
> > 1. use initrd to put that small program?
> 
> yeah. Kind of what we do with our clusters now. Kernel + initrd in flash
> -- or ide-flash if flash is too small.
> 
> 
> > 2. what kind of features needed by that small program?
> 
> how about user-mode open-firmware, i.e. openbios.
> 
> ron
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From lists at endian.se  Thu May 19 22:25:24 2005
From: lists at endian.se (Kjell Svensson)
Date: Thu, 19 May 2005 22:25:24 +0200
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <Pine.LNX.4.58.0505190844570.24293@enigma.lanl.gov>
References: <56ce23fbc454b4afca705f058d43d46c@endian.se>
	<Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
	<Pine.LNX.4.58.0505171605570.18949@enigma.lanl.gov>
	<3cc9bb94ebb91f3693e5986cfdc31b2e@endian.se>
	<Pine.LNX.4.58.0505190844570.24293@enigma.lanl.gov>
Message-ID: <80cc9fc5e732f48d24652098a560c279@endian.se>

Hmm, interesting image you sent!...
I was curious about the image, so I had a look at it in my hex editor 
back home while waiting to get back into work tomorrow to actually test 
it. I was surprised to find the image to be repeating after 256kB, i.e 
comparing the first 256k with the second 256k showed they were 
identical!
Is this what a LinuxBIOS romimage is supposed to be? If so, the images 
my builds have generated are certainly bogus, because I never got that.
If not, could you have made an error when copying the image, so that 
your cluster nodes actually use this image in 256kB flashes?

Except for this, I couldn't see anything unusual.

Cheers,
/Kjell



On 19 maj 2005, at 16:45, Ronald G. Minnich wrote:

>
>
> no guarantees, but this might be it.
>
> it's a 512KB image. What size rom do you have?
>
> ron<smartcore.rom>




From rminnich at lanl.gov  Thu May 19 22:28:27 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Thu, 19 May 2005 14:28:27 -0600 (MDT)
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <80cc9fc5e732f48d24652098a560c279@endian.se>
References: <56ce23fbc454b4afca705f058d43d46c@endian.se>
	<Pine.LNX.4.58.0505171601090.18949@enigma.lanl.gov>
	<Pine.LNX.4.58.0505171605570.18949@enigma.lanl.gov>
	<3cc9bb94ebb91f3693e5986cfdc31b2e@endian.se>
	<Pine.LNX.4.58.0505190844570.24293@enigma.lanl.gov>
	<80cc9fc5e732f48d24652098a560c279@endian.se>
Message-ID: <Pine.LNX.4.58.0505191427170.24293@enigma.lanl.gov>



On Thu, 19 May 2005, Kjell Svensson wrote:

> Hmm, interesting image you sent!...
> I was curious about the image, so I had a look at it in my hex editor back
> home while waiting to get back into work tomorrow to actually test it. I was
> surprised to find the image to be repeating after 256kB, i.e comparing the
> first 256k with the second 256k showed they were identical!

it's ancient. I had a build for 256KB, and only had a 512KB lying around, 
so I guess I did this:
cat img img > img2


> Is this what a LinuxBIOS romimage is supposed to be? 

no

give it a shot. 

You can also put an elfimage at the start of flash and leave the linuxbios 
at the end unchanged, i.e. use dd to cat off the last 64BK as the startup 
code, and then put different payloads at the front. 

just an idea.

ron



From peter.fox at aeroflex.com  Fri May 20 10:32:45 2005
From: peter.fox at aeroflex.com (Peter Fox)
Date: Fri, 20 May 2005 09:32:45 +0100
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0505190925230.24293@enigma.lanl.gov>
Message-ID: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>

It would be convenient for those who have developed something
using v1 to have linuxbios v1 available via the linuxbios site
- so if you update the download page to serve the last snapshot,
with instructions how to extract from that, it would be fine by me.

-- 
Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
Principal Design Engineer                            Stevenage
Any opinions expressed above are      http://www.aeroflex.com/
not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200

-----Original Message-----
From: linuxbios-bounces at openbios.org
[mailto:linuxbios-bounces at openbios.org]On Behalf Of Ronald G. Minnich
Sent: 19 May 2005 16:26
To: Bari Ari
Cc: linuxbios at openbios.org
Subject: Re: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org




On Thu, 19 May 2005, Bari Ari wrote:

> Will http://cvs.sourceforge.net/cvstarballs/freebios-cvsroot.tar.bz2 be
> taken down for good as well?

I sure hope so, or is that still needed.

ron

_______________________________________________
LinuxBIOS mailing list
LinuxBIOS at openbios.org
http://www.openbios.org/mailman/listinfo/linuxbios



From kjell at endian.se  Fri May 20 10:44:38 2005
From: kjell at endian.se (Kjell Svensson)
Date: Fri, 20 May 2005 10:44:38 +0200
Subject: Fwd: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <c3b83d7418b0a80790af11178e7c3a78@endian.se>
References: <c3b83d7418b0a80790af11178e7c3a78@endian.se>
Message-ID: <1116578678.428da376953f5@endian.se>

Hi again,

I just tried the romimage - It didn't work!
Well, the LinuxBIOS booted and everything looked OK up until the same point as I
have seen before from my builds; elfboot is started, but the payload seems
completely dead... :-(
Since I saw the payload in the romimage was etherboot, I also hooked up the
ethernet and started sniffing it with ethereal, but no packets were ever sent on
the ethernet. I have also checked that nothing comes out on the VGA console.
My conclusion is that the Etherboot payload either never is
reached, or crashes at an early stage.

Well, I guess this anyway gives me lots of hints by ruling out all the doubts I
had about my config and build process; now I guess there must be something
different between our Smartcore-P5 based hardwares...

Could I please ask you to check what cardtype/revision you're using?
My HW config looks as follows:
DigitalLogic MSM-P5SEN, V3.9, Rev A. It's also marked 03.04 which I guess is the
manufacturing date(?)
This card has a SmartCore-P5 module clocked at 166MHz. There is only one
Revision label on this module, but it has no revision mark on it...
The MSM-P5SEN variant comes without VGA cirquitry, but I have also tried
LinuxBIOS on the VGA-equipped variant we have around here with the same result.
The onboard Flash is a Winbond 29C020CP (i.e 256kB), but LinuxBIOS boots equally
well also from 128kB and 512kB flashes I've tried in the socket.
The card has one SDRAM slot, which we have equipped with a 128MB large module.

Looking for simple answers; could you possibly be using a different size
(larger) RAM, and could the elfboot for this platform have some code fragments
not checking the detected RAM size so that it relocates the payload out inito
the void?

-- 
Cheers. /Kjell 
 


Quoting Kjell Svensson <lists at endian.se>:

> 
> 
> 
> Begin forwarded message:
> 
> > From: "Ronald G. Minnich" <rminnich at lanl.gov>
> > Date: 19 maj 2005 16:45:16 MET
> > To: Kjell Svensson <lists at endian.se>
> > Subject: Re: [LinuxBIOS] still no luck on smartcore-p5
> >
> >
> >
> > no guarantees, but this might be it.
> >
> > it's a 512KB image. What size rom do you have?
> >
> > ron



From stepan at openbios.org  Fri May 20 15:18:03 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Fri, 20 May 2005 15:18:03 +0200
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
References: <Pine.LNX.4.58.0505190925230.24293@enigma.lanl.gov>
	<NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
Message-ID: <20050520131803.GA15047@openbios.org>

* Peter Fox <peter.fox at aeroflex.com> [050520 10:32]:
> It would be convenient for those who have developed something
> using v1 to have linuxbios v1 available via the linuxbios site

Check http://snapshots.linuxbios.org/ - the latest v1 version is there,
and so will be any v1 versions that might appear in the future.

> - so if you update the download page to serve the last snapshot,
> with instructions how to extract from that, it would be fine by me.
 
I cleaned up the download page a little bit. Hope it's more
understandable now. 

Stefan





From stepan at openbios.org  Fri May 20 15:26:06 2005
From: stepan at openbios.org (Stefan Reinauer)
Date: Fri, 20 May 2005 15:26:06 +0200
Subject: [LinuxBIOS] LSI1030?
In-Reply-To: <20050520131803.GA15047@openbios.org>
References: <Pine.LNX.4.58.0505190925230.24293@enigma.lanl.gov>
	<NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
	<20050520131803.GA15047@openbios.org>
Message-ID: <20050520132606.GA16195@openbios.org>

Hi

some boards in the current tree fail with:
===> ERROR: Could not open file
"/tmp/LBABUILD-fL6924/freebios/src/drivers/lsi/53c1030/Config.lb"

Can anyone check this file in? YhLu?

Stefan






From steve at digidescorp.com  Fri May 20 16:37:56 2005
From: steve at digidescorp.com (Steven J. Magnani)
Date: Fri, 20 May 2005 09:37:56 -0500
Subject: [LinuxBIOS] Posted memory write enable...incorrect?
Message-ID: <002201c55d49$86741f00$6ffea8c0@banana>

Hi,

In looking over the Intel 82801ER (ICH-5) southbridge code, I noticed
some statements that modify LPC PCI config register 0x46 to enable PCI
posted memory writes (src/southbridge/intel/i82801er/i82801er_lpc.c):

    static void lpc_init(struct device *dev)
    {
        ...
 
       /* posted memory write enable */
       byte = pci_read_config8(dev, 0x46);
       pci_write_config8(dev, 0x46, byte | (1<<0)); 

       ...
    }

The ICH-5 datasheet does not mention such a configuration register.
Neither do the datasheets for the ICH-4 (82801DBM) or the AMD 8111,
which have similar code.

Is it possible that these were inherited (incorrectly) from code for the
AMD 766 southbridge? That *does* support this functionality.

Steve Magnani
Digital Design Corporation
www.digidescorp.com






From rminnich at lanl.gov  Fri May 20 17:29:34 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 20 May 2005 09:29:34 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
References: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
Message-ID: <Pine.LNX.4.58.0505200929260.28152@enigma.lanl.gov>



On Fri, 20 May 2005, Peter Fox wrote:

> It would be convenient for those who have developed something
> using v1 to have linuxbios v1 available via the linuxbios site
> - so if you update the download page to serve the last snapshot,
> with instructions how to extract from that, it would be fine by me.


> 
> -- 
> Peter Fox <peter.fox at aeroflex.com>     Aeroflex Test Solutions
> Principal Design Engineer                            Stevenage
> Any opinions expressed above are      http://www.aeroflex.com/
> not necessarily those of Aeroflex.   Tel: + 44 (0) 1438 742200
> 
> -----Original Message-----
> From: linuxbios-bounces at openbios.org
> [mailto:linuxbios-bounces at openbios.org]On Behalf Of Ronald G. Minnich
> Sent: 19 May 2005 16:26
> To: Bari Ari
> Cc: linuxbios at openbios.org
> Subject: Re: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
> 
> 
> 
> 
> On Thu, 19 May 2005, Bari Ari wrote:
> 
> > Will http://cvs.sourceforge.net/cvstarballs/freebios-cvsroot.tar.bz2 be
> > taken down for good as well?
> 
> I sure hope so, or is that still needed.
> 
> ron
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From rminnich at lanl.gov  Fri May 20 17:32:58 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 20 May 2005 09:32:58 -0600 (MDT)
Subject: Fwd: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <1116578678.428da376953f5@endian.se>
References: <c3b83d7418b0a80790af11178e7c3a78@endian.se>
	<1116578678.428da376953f5@endian.se>
Message-ID: <Pine.LNX.4.58.0505200930020.28152@enigma.lanl.gov>



On Fri, 20 May 2005, Kjell Svensson wrote:

> Well, the LinuxBIOS booted and everything looked OK up until the same point as I
> have seen before from my builds; elfboot is started, but the payload seems
> completely dead... :-(

most likely this is a memory programming issue then. We've had lots of 
trouble with the tiny DIMMS used on these cards -- the fuctory bios 
programs them very conservatively, or linuxbios gets something wrong, or 
some combination of the two, and result is what you are seeing. 

Recommend you get memtest86. 

Also, the memory that has worked well for us is Apacer. What I have on my 
SC520 is the Apacer 128MB UBN PC133 CL3 memory.

ron



From rminnich at lanl.gov  Fri May 20 17:45:13 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 20 May 2005 09:45:13 -0600 (MDT)
Subject: Fwd: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <20050520153801.GA26197@openbios.org>
References: <c3b83d7418b0a80790af11178e7c3a78@endian.se>
	<1116578678.428da376953f5@endian.se>
	<Pine.LNX.4.58.0505200930020.28152@enigma.lanl.gov>
	<20050520153801.GA26197@openbios.org>
Message-ID: <Pine.LNX.4.58.0505200944530.28152@enigma.lanl.gov>


On Fri, 20 May 2005, Stefan Reinauer wrote:

> * Ronald G. Minnich <rminnich at lanl.gov> [050520 17:32]:
> > Also, the memory that has worked well for us is Apacer. What I have on my 
> > SC520 is the Apacer 128MB UBN PC133 CL3 memory.
    ^^^^^ Smartcore P5.
typo! 


ron



From lists at endian.se  Fri May 20 18:09:57 2005
From: lists at endian.se (Kjell Svensson)
Date: Fri, 20 May 2005 18:09:57 +0200
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <Pine.LNX.4.58.0505200930020.28152@enigma.lanl.gov>
References: <c3b83d7418b0a80790af11178e7c3a78@endian.se>
	<1116578678.428da376953f5@endian.se>
	<Pine.LNX.4.58.0505200930020.28152@enigma.lanl.gov>
Message-ID: <d45678364ba8c6bf2200159700b403c1@endian.se>

Hi again,
I've left the lab for the week now, so I can't check what DIMM type 
we're using until Monday.
But I do now for sure they work well using the factory BIOS settings, 
we have several hundred units shipped running Linux well on them 
without customer complaints.

I'm not sure I understand what I could use memtest86 for at this point? 
Since I'm not able to start any payloads from LinuxBIOS, I wouldn't be 
able to run memtest from that?
Or do you mean I should run memtest86 started from the route factory 
BIOS -> GRUB -> memtest86? If so, what is it I should look for??

Are there any special linuxbios memory settings you believe I could try 
with more conservative settings?
But if it's a DRAM issue, wouldn't then the LinuxBIOS itself crash 
then? Isn't LinuxBIOS relocating itself into the DRAM during startup?

Cheers,
/Kjell



On 20 maj 2005, at 17:32, Ronald G. Minnich wrote:

>
>
> On Fri, 20 May 2005, Kjell Svensson wrote:
>
>> Well, the LinuxBIOS booted and everything looked OK up until the same 
>> point as I
>> have seen before from my builds; elfboot is started, but the payload 
>> seems
>> completely dead... :-(
>
> most likely this is a memory programming issue then. We've had lots of
> trouble with the tiny DIMMS used on these cards -- the fuctory bios
> programs them very conservatively, or linuxbios gets something wrong, 
> or
> some combination of the two, and result is what you are seeing.
>
> Recommend you get memtest86.
>
> Also, the memory that has worked well for us is Apacer. What I have on 
> my
> SC520 is the Apacer 128MB UBN PC133 CL3 memory.
>
> ron
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios




From steve at digidescorp.com  Fri May 20 18:16:39 2005
From: steve at digidescorp.com (Steven J. Magnani)
Date: Fri, 20 May 2005 11:16:39 -0500
Subject: [LinuxBIOS] Intel 82801 southbridge NMI configuration
Message-ID: <002301c55d57$4dfcacb0$6ffea8c0@banana>

It's me again.

Further down in the 82801{er | dbm} LPC initialization code, there is a
block that configures NMI handling:

    static void lpc_init(struct device *dev)
    {
        ...

        /* Set up NMI on errors */
        byte = pci_read_config8(dev, 0x61);
        byte |= (1 << 3); /* IOCHK# NMI Enable */
        byte |= (1 << 6); /* PCI SERR# Enable */
        pci_write_config8(dev, 0x61, byte);
        byte = pci_read_config8(dev, 0x70);
        nmi_option = NMI_OFF;
        get_option(&nmi_option, "nmi");
        if (nmi_option) {			
            byte |= (1 << 7); /* set NMI */
            pci_write_config8(dev, 0x70, byte);
        }
    
        ...
    }

>From the ICH-5 ('ER) documentation, it looks to me like this is meant to
be accessing NMI_SC and NMI_EN, the NMI Status and Control and NMI
Enable registers, which are at 0x61 and 0x70 in processor I/O space, not
PCI configuration space. So inb()/outb() should be used instead of
pci_read_config8()/pci_write_config8().

If these are the correct registers, SERR# enable is controlled by bit 2,
not bit 6.

Also it looks like the code does the opposite of what was intended,
enabling NMIs when it should be disabling them, and vice versa. This is
because Intel defines the NMI bits used above with reverse
polarity...set to 1 to DISable, 0 to ENable.

So the code should read instead as:

    #include <arch/io.h>

    static void lpc_init(struct device *dev)
    {
        ...

        /* Set up NMI on errors */
        byte = inb(0x61);
        byte &= ~(1 << 3); /* IOCHK# NMI Enable */
        byte &= ~(1 << 2); /* PCI SERR# Enable */
        outb(0x61, byte);
        byte = inb(0x70);
        nmi_option = NMI_OFF;
        get_option(&nmi_option, "nmi");
        if (nmi_option) {			
            byte &= ~(1 << 7); /* set NMI */
            outb(0x70, byte);
        }
    
        ...
    }

It this looks right, I'm willing to attempt folding this change into the
source (never used arch before...), but I have no way to test that it
does anything other than compile.

Regards,
Steve Magnani
Digital Design Corporation
www.digidescorp.com






From bari at onelabs.com  Fri May 20 18:25:45 2005
From: bari at onelabs.com (Bari Ari)
Date: Fri, 20 May 2005 11:25:45 -0500
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0505200929260.28152@enigma.lanl.gov>
References: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
	<Pine.LNX.4.58.0505200929260.28152@enigma.lanl.gov>
Message-ID: <428E0F89.5050409@onelabs.com>

Ronald G. Minnich wrote:

>>On Thu, 19 May 2005, Bari Ari wrote:
>>
>>
>>>Will http://cvs.sourceforge.net/cvstarballs/freebios-cvsroot.tar.bz2 be
>>>taken down for good as well?
>>
>>I sure hope so, or is that still needed.

My concern was only with keeping links from external websites to the 
snapshots current and unbroken.

I think the snapshots are convenient way for new visitors to Linuxbios 
to have a quick look at the code and structure.

-Bari



From steve at digidescorp.com  Fri May 20 18:39:30 2005
From: steve at digidescorp.com (Steven J. Magnani)
Date: Fri, 20 May 2005 11:39:30 -0500
Subject: [LinuxBIOS] RE: Intel 82801 southbridge NMI configuration
Message-ID: <002401c55d5a$7ec8dd20$6ffea8c0@banana>

A correction to the corrected code, for the record...the outb()
parameters were reversed...

    #include <arch/io.h>

    static void lpc_init(struct device *dev)
    {
        ...

        /* Set up NMI on errors */
        byte = inb(0x61);
        byte &= ~(1 << 3); /* IOCHK# NMI Enable */
        byte &= ~(1 << 2); /* PCI SERR# Enable */
        outb(byte, 0x61);
        byte = inb(0x70);
        nmi_option = NMI_OFF;
        get_option(&nmi_option, "nmi");
        if (nmi_option) {			
            byte &= ~(1 << 7); /* set NMI */
            outb(byte, 0x70);
        }
    
        ...
    }

--Steve






From rminnich at lanl.gov  Fri May 20 18:43:08 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 20 May 2005 10:43:08 -0600 (MDT)
Subject: [LinuxBIOS] still no luck on smartcore-p5
In-Reply-To: <d45678364ba8c6bf2200159700b403c1@endian.se>
References: <c3b83d7418b0a80790af11178e7c3a78@endian.se>
	<1116578678.428da376953f5@endian.se>
	<Pine.LNX.4.58.0505200930020.28152@enigma.lanl.gov>
	<d45678364ba8c6bf2200159700b403c1@endian.se>
Message-ID: <Pine.LNX.4.58.0505201042370.28152@enigma.lanl.gov>

I've been able to run memtest at times when I could not run a real 
payload. 

I am pretty sure this is memory timing, I just don't see why or how. 

I'll try to think on this over the weekend.

ron




From rminnich at lanl.gov  Fri May 20 18:44:24 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 20 May 2005 10:44:24 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <428E0F89.5050409@onelabs.com>
References: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
	<Pine.LNX.4.58.0505200929260.28152@enigma.lanl.gov>
	<428E0F89.5050409@onelabs.com>
Message-ID: <Pine.LNX.4.58.0505201044160.28152@enigma.lanl.gov>

just tell me what CNAMEs you need and I will set them up.

ron




From yinghailu at gmail.com  Fri May 20 19:02:10 2005
From: yinghailu at gmail.com (yhlu)
Date: Fri, 20 May 2005 10:02:10 -0700
Subject: [LinuxBIOS] LSI1030?
In-Reply-To: <20050520132606.GA16195@openbios.org>
References: <Pine.LNX.4.58.0505190925230.24293@enigma.lanl.gov>
	<NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
	<20050520131803.GA15047@openbios.org>
	<20050520132606.GA16195@openbios.org>
Message-ID: <2ea3fae105052010026e2973ad@mail.gmail.com>

I can not check lsi scsi support code. They didn't isssue
authentication letter for that.

I have removes including lines in MB Config.lb (s2880, s4880, s4882).

YH

On 5/20/05, Stefan Reinauer <stepan at openbios.org> wrote:
> Hi
> 
> some boards in the current tree fail with:
> ===> ERROR: Could not open file
> "/tmp/LBABUILD-fL6924/freebios/src/drivers/lsi/53c1030/Config.lb"
> 
> Can anyone check this file in? YhLu?
> 
> Stefan
> 
> 
> 
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From bari at onelabs.com  Fri May 20 20:09:03 2005
From: bari at onelabs.com (Bari Ari)
Date: Fri, 20 May 2005 13:09:03 -0500
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0505201044160.28152@enigma.lanl.gov>
References: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
	<Pine.LNX.4.58.0505200929260.28152@enigma.lanl.gov>
	<428E0F89.5050409@onelabs.com>
	<Pine.LNX.4.58.0505201044160.28152@enigma.lanl.gov>
Message-ID: <428E27BF.6070500@onelabs.com>

Ronald G. Minnich wrote:
> just tell me what CNAMEs you need and I will set them up.
> 

Stefan Reinauer wrote:
 > * Peter Fox <peter.fox at aeroflex.com> [050520 10:32]:
 >
 >>It would be convenient for those who have developed something
 >>using v1 to have linuxbios v1 available via the linuxbios site
 >
 >
 > Check http://snapshots.linuxbios.org/ - the latest v1 version is there,
 > and so will be any v1 versions that might appear in the future.


Having  http://snapshots.linuxbios.org/  is fine for me.

-Bari



From rminnich at lanl.gov  Fri May 20 21:21:20 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 20 May 2005 13:21:20 -0600 (MDT)
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <428E27BF.6070500@onelabs.com>
References: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
	<Pine.LNX.4.58.0505200929260.28152@enigma.lanl.gov>
	<428E0F89.5050409@onelabs.com>
	<Pine.LNX.4.58.0505201044160.28152@enigma.lanl.gov>
	<428E27BF.6070500@onelabs.com>
Message-ID: <Pine.LNX.4.58.0505201320490.28152@enigma.lanl.gov>



On Fri, 20 May 2005, Bari Ari wrote:

> Having  http://snapshots.linuxbios.org/  is fine for me.

ok, I just tested that and it is there, let me know if there is any 
problem with it. 

Bari, is there documentation available yet for the via 8606 (twister)?

ron



From steve at digidescorp.com  Fri May 20 23:12:56 2005
From: steve at digidescorp.com (Steven J. Magnani)
Date: Fri, 20 May 2005 16:12:56 -0500
Subject: [LinuxBIOS] Bug in pnp_set_drq()?
Message-ID: <002701c55d80$b527ab00$6ffea8c0@banana>

I ran across the following code in src/devices/pnp_device.c:

    void pnp_set_drq(device_t dev, unsigned drq, unsigned index)
    {
        /* Index == 0x74 */
        pnp_write_config(dev, index, drq & 0xff);
    }

    static void pnp_set_resource(device_t dev, struct resource
*resource)
    {
        ...

        /* Now store the resource */
        if (resource->flags & IORESOURCE_IO) {
            pnp_set_iobase(dev, resource->index, resource->base);
        }
        else if (resource->flags & IORESOURCE_DRQ) {
            pnp_set_drq(dev, resource->index, resource->base);
        }

        ...
    }

The declaration of pnp_set_drq() looks backwards to me. Shouldn't it be

    void pnp_set_drq(device_t dev, unsigned index, unsigned drq)

to match the way it's being called?

Steve Magnani
Digital Design Corporation
www.digidescorp.com






From rminnich at lanl.gov  Fri May 20 23:25:28 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 20 May 2005 15:25:28 -0600 (MDT)
Subject: [LinuxBIOS] Bug in pnp_set_drq()?
In-Reply-To: <002701c55d80$b527ab00$6ffea8c0@banana>
References: <002701c55d80$b527ab00$6ffea8c0@banana>
Message-ID: <Pine.LNX.4.58.0505201525050.28152@enigma.lanl.gov>

Steven, it's good to have you finding these nits. We'll try to figure it 
out but don't give up if you don't get an answer right away!

thanks!

ron




From bari at onelabs.com  Fri May 20 23:29:28 2005
From: bari at onelabs.com (Bari Ari)
Date: Fri, 20 May 2005 16:29:28 -0500
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0505201320490.28152@enigma.lanl.gov>
References: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
	<Pine.LNX.4.58.0505200929260.28152@enigma.lanl.gov>
	<428E0F89.5050409@onelabs.com>
	<Pine.LNX.4.58.0505201044160.28152@enigma.lanl.gov>
	<428E27BF.6070500@onelabs.com>
	<Pine.LNX.4.58.0505201320490.28152@enigma.lanl.gov>
Message-ID: <428E56B8.200@onelabs.com>

Ronald G. Minnich wrote:
> 
> On Fri, 20 May 2005, Bari Ari wrote:
> 
> 
>>Having  http://snapshots.linuxbios.org/  is fine for me.
> 
> 
> ok, I just tested that and it is there, let me know if there is any 
> problem with it. 
> 
> Bari, is there documentation available yet for the via 8606 (twister)?

The VIA Twister VT8606 northbridge has been out for quite a while and is 
targeted at many embedded applications. I've seen it used in lots of 
industrial sbc's and thin clients. Data sheets should be easier to get 
than the desktop parts.

VIA has been releasing lots of the source for drivers of many chipsets 
including 2d/3d, mpeg, tv for unichrome graphics accelerators.

Much of the source and info may be found here:

http://www.viaarena.com/

http://www.viavpsd.com/

http://www.viaembedded.com/

http://unichrome.sourceforge.net/

http://www.via.com.tw/

-Bari



From bari at onelabs.com  Sat May 21 03:48:36 2005
From: bari at onelabs.com (Bari Ari)
Date: Fri, 20 May 2005 20:48:36 -0500
Subject: [LinuxBIOS] I"ve updated the dns for www.linuxbios.org
In-Reply-To: <Pine.LNX.4.58.0505201320490.28152@enigma.lanl.gov>
References: <NEBBJLECKKOPJEEKNGJOMEGJENAA.peter.fox@aeroflex.com>
	<Pine.LNX.4.58.0505200929260.28152@enigma.lanl.gov>
	<428E0F89.5050409@onelabs.com>
	<Pine.LNX.4.58.0505201044160.28152@enigma.lanl.gov>
	<428E27BF.6070500@onelabs.com>
	<Pine.LNX.4.58.0505201320490.28152@enigma.lanl.gov>
Message-ID: <428E9374.3000200@onelabs.com>

Ronald G. Minnich wrote:
> Bari, is there documentation available yet for the via 8606 (twister)?

The VIA ProSavage PN133T is the vt8606 and called the Twister-T.

http://www.viaarena.com/default.aspx?PageID=40&STypeID=4

The link seems to be broken to the marketing docs:
http://www.via.com.tw/en/ProSavage%20Chipsets/pn133t.jsp

It may have EOLed recently since the CLE266 and CN400 support the same 
cpu's but offer far better performance and features.

-Bari




From ralph at inputplus.co.uk  Sat May 21 11:43:42 2005
From: ralph at inputplus.co.uk (Ralph Corderoy)
Date: Sat, 21 May 2005 10:43:42 +0100
Subject: [LinuxBIOS] Adding Support for ATA Freeze Command.
Message-ID: <200505210943.j4L9hhZ04279@blake.inputplus.co.uk>


Hi,

Are people generally aware of the ATA security commands?  They allow a
password to be set on a hard drive.  It's the hard drive that's doing
the password storing, not the motherboard, so the drive's still locked
if it's moved to another machine.  On boot-up the BIOS recognises the
drive's locked and prompts the user for the password.  It's also the
normal UI for setting it in the first place.

Anyway, my point is passwords are typically not set.  This means
something malicous can set it and the next time the machine boots the
user's locked out of his own drive.  The c't magazine had an article on
it recently.

    http://www.heise.de/ct/english/05/08/172/

Once a drive's locked with an unknown user password then it's a dead
drive unless the manufacturer can be persuade to give you the higher
level password that allows a security format of the device to be done.
This normally requires a paper-chase to prove you're the rightful owner.

Options are for users to set the password on their drives so it can't be
set malicously to something unknown to them but that's a pain because it
needs supplying on boot-up.  Or, for the ATA Freeze command to be used
soon after boot-up.  This puts the drive in a state where it won't
accept any password setting until after the next boot.

(The ATA-3 spec. is http://www.t13.org/project/d2008r7b-ATA-3.pdf -- see
pages 33 and 75 by the number written on the page.)

Ideally, the Freeze needs to be done as soon as possible in the BIOS ->
bootloader -> OS chain to make it harder to set the password before the
freeze is done.  That's why I'm here.  :-)  

It LinuxBIOS were to add support for Freeze drives it would be another
advantage over other BIOSes.  Am I right in thinking that LinuxBIOS
itself knows nothing about ATA and that's left to FILO?  Is that the
only payload that deals with ATA?

(I'm also going to lobby the Grub people for those of us that don't have
BIOS support for ATA Freeze.)

Cheers,


Ralph.




From stuge-linuxbios at cdy.org  Sat May 21 15:07:28 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Sat, 21 May 2005 15:07:28 +0200
Subject: [LinuxBIOS] Adding Support for ATA Freeze Command.
In-Reply-To: <200505210943.j4L9hhZ04279@blake.inputplus.co.uk>
References: <200505210943.j4L9hhZ04279@blake.inputplus.co.uk>
Message-ID: <20050521130728.GA20704@foo.birdnet.se>

On Sat, May 21, 2005 at 10:43:42AM +0100, Ralph Corderoy wrote:
> Are people generally aware of the ATA security commands?

No, probably not. Certainly not if people means everyone with a
ATA drive.


> Once a drive's locked with an unknown user password then it's a
> dead drive unless the manufacturer can be persuade to give you the
> higher level password that allows a security format of the device
> to be done. This normally requires a paper-chase to prove you're
> the rightful owner.

I can see at least two other ways to recover the drive;

1. Find that higher level password from someone other than the
manufacturer.

2. Build custom hardware or just a custom BIOS to do a brute force
search for the password in the drive.


> It LinuxBIOS were to add support for Freeze drives it would be
> another advantage over other BIOSes.  Am I right in thinking that
> LinuxBIOS itself knows nothing about ATA and that's left to FILO?

LinuxBIOS initializes the chipset and the payload may use the chipset
to speak to a disk.


> Is that the only payload that deals with ATA?

No, I know of a few other; Etherboot, Linux, ADLO and the FreeBSD
kernel if we got that booted, I don't remember.

I'm not sure this functionality really belongs in the init part of
LinuxBIOS, but perhaps you could have it added to Linux if it isn't
already available there through ioctl() calls.

There's a problem with the interaction required, LinuxBIOS has always
been designed to not require any configuration or options to be
handled interactively, which I think is good. Others will of course
disagree. :)


//Peter



From ralph at inputplus.co.uk  Sat May 21 17:26:01 2005
From: ralph at inputplus.co.uk (Ralph Corderoy)
Date: Sat, 21 May 2005 16:26:01 +0100
Subject: [LinuxBIOS] Adding Support for ATA Freeze Command. 
In-Reply-To: <20050521130728.GA20704@foo.birdnet.se> 
Message-ID: <200505211526.j4LFQ2w10967@blake.inputplus.co.uk>


Hi Peter,

> On Sat, May 21, 2005 at 10:43:42AM +0100, Ralph Corderoy wrote:
> > Are people generally aware of the ATA security commands?
> 
> No, probably not. Certainly not if people means everyone with a ATA
> drive.

No, sorry, I meant people on the list.

> > Once a drive's locked with an unknown user password then it's a dead
> > drive unless the manufacturer can be persuade to give you the higher
> > level password that allows a security format of the device to be
> > done. This normally requires a paper-chase to prove you're the
> > rightful owner.
> 
> I can see at least two other ways to recover the drive;
> 
> 1. Find that higher level password from someone other than the
> manufacturer.

The manufacturer tends to set it to something unique and keeps a record
of it against the unit's serial number.

> 2. Build custom hardware or just a custom BIOS to do a brute force
> search for the password in the drive.

After five failed attempts the drive refuses to do anything more until a
hardware reset or power cycle.  Custom hardware could do the reset but I
don't know if it's within the ability of a BIOS?

I am aware that someone in the UK has built hardware that can
brute-force it in under 12 hours.

> > It LinuxBIOS were to add support for Freeze drives it would be
> > another advantage over other BIOSes.  Am I right in thinking that
> > LinuxBIOS itself knows nothing about ATA and that's left to FILO?
> 
> LinuxBIOS initializes the chipset and the payload may use the chipset
> to speak to a disk.

Right.  So it's not LinuxBIOS itself that would be involved.

> > Is that the only payload that deals with ATA?
> 
> No, I know of a few other; Etherboot, Linux, ADLO and the FreeBSD
> kernel if we got that booted, I don't remember.
> 
> I'm not sure this functionality really belongs in the init part of
> LinuxBIOS,

No, I don't think it does unless there's already ATA commands in there
that talk to a drive.

> but perhaps you could have it added to Linux if it isn't already
> available there through ioctl() calls.

It's possible in Linux already at the system call level, and recently
hdparm added support through its -F option -- the c't article's author
sent a patch IIRC, but by the time Linux is running is a bit late.  A
malicious program running under Linux where Freeze has already been done
by hdparm could write to the MBR causing the password to be set on the
next boot.  That's unless the BIOS has done a Freeze before the MBR gets
run.

> There's a problem with the interaction required, LinuxBIOS has always
> been designed to not require any configuration or options to be
> handled interactively, which I think is good. Others will of course
> disagree. :)

It does need an element of configuration else the drive would always be
frozen and the password could never be set.  It sounds like FILO could
be the place.  Is that the standard `boot from a hard drive' payload
with LinuxBIOS?

Cheers,


Ralph.




From kfuchs at winternet.com  Sat May 21 21:41:15 2005
From: kfuchs at winternet.com (Ken Fuchs)
Date: Sat, 21 May 2005 14:41:15 -0500
Subject: [LinuxBIOS] http://wiki.linuxbios.org/ not found.
Message-ID: <200505211941.j4LJfF925030@ecstasy1.winternet.com>

When I try to access

http://wiki.linuxbios.org/

I get wiki.linuxbios.org is not found.

http://www.linuxbios.org/ works fine.

It would be nice if any access within the linuxbios.org domain responds
with something more useful than <host>.linuxbios.org is not found.

Sincerely,

Ken Fuchs <kfuchs at winternet.com>



From stuge-linuxbios at cdy.org  Sun May 22 05:06:37 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Sun, 22 May 2005 05:06:37 +0200
Subject: [LinuxBIOS] Adding Support for ATA Freeze Command.
In-Reply-To: <200505211526.j4LFQ2w10967@blake.inputplus.co.uk>
References: <20050521130728.GA20704@foo.birdnet.se>
	<200505211526.j4LFQ2w10967@blake.inputplus.co.uk>
Message-ID: <20050522030637.GA11366@foo.birdnet.se>

Hey,

On Sat, May 21, 2005 at 04:26:01PM +0100, Ralph Corderoy wrote:
> > On Sat, May 21, 2005 at 10:43:42AM +0100, Ralph Corderoy wrote:
> > > Are people generally aware of the ATA security commands?
> > 
> > No, probably not. Certainly not if people means everyone with a ATA
> > drive.
> 
> No, sorry, I meant people on the list.

Oh, ok. Well, by now everyone should be aware. :)


> > 1. Find that higher level password from someone other than the
> > manufacturer.
> 
> The manufacturer tends to set it to something unique and keeps a
> record of it against the unit's serial number.

Oh, ok, then that wont work.


> > 2. Build custom hardware or just a custom BIOS to do a brute
> > force search for the password in the drive.
> 
> After five failed attempts the drive refuses to do anything more
> until a hardware reset or power cycle.

Right. Some drives I've had even had a limit of three attempts.


> Custom hardware could do the reset but I don't know if it's within
> the ability of a BIOS?

It's certainly possible to add a simple reset circuitry using common
components (one resistor+one transistor) on e.g. a parallell port and
control it from the BIOS. Just twisting wires together with component
pins would be enough, and doable in any environment.


> I am aware that someone in the UK has built hardware that can
> brute-force it in under 12 hours.

Ok. I haven't made any tests even though I've thought about this
matter earlier, but 12 hours feels a bit short. I guess it isn't
particularly CPU intensive though, no encryption, just add one and
send, with the occasional reset..


> > LinuxBIOS initializes the chipset and the payload may use the chipset
> > to speak to a disk.
> 
> Right.  So it's not LinuxBIOS itself that would be involved.

Well.. See discussion below.


> > I'm not sure this functionality really belongs in the init part of
> > LinuxBIOS,
> 
> No, I don't think it does unless there's already ATA commands in
> there that talk to a drive.

Right. There aren't. But..


> > but perhaps you could have it added to Linux if it isn't already
> > available there through ioctl() calls.
> 
> It's possible in Linux already at the system call level, and
> recently hdparm added support through its -F option -- the c't
> article's author sent a patch IIRC, but by the time Linux is
> running is a bit late.  A malicious program running under Linux
> where Freeze has already been done by hdparm could write to the MBR
> causing the password to be set on the next boot.  That's unless the
> BIOS has done a Freeze before the MBR gets run.

My humble opinion is that you have much bigger problems if a
malicious program has root priviledges in your system.

Sure, if a security "hole" is easy to plug, why not plug it, but
there are many other security measures that can and should be used
on production systems with important data that are effective for
recovering from an attack of this kind as well as several others.
(Redundant hardware and storage, with external backups.)


> > There's a problem with the interaction required, LinuxBIOS has
> > always been designed to not require any configuration or options
> > to be handled interactively, which I think is good. Others will
> > of course disagree. :)
> 
> It does need an element of configuration else the drive would
> always be frozen and the password could never be set.  It sounds
> like FILO could be the place.  Is that the standard `boot from a
> hard drive' payload with LinuxBIOS?

(See here about the things above.)

..yes.. At the moment, standalone FILO or the FILO included in
Etherboot is the standard boot-from-storage payload for most OSes.

The intention, however, has always been to use Linux as the boot-
from-anything payload and we're getting closer to that becoming
reality each day. The showstopper is flash ROM size, but that is
increasing on new mainboards, and LPC (where any size ROM can be
used) is getting much more popular as well.

Then, suddenly, the Linux kernel isn't so late in the boot process.
Remember, LinuxBIOS doesn't care about legacy junk such as the MBR,
it starts the payload immediately, as per compile-time configuration.

But, if the malicious program can write to MBR, it can also write a
new BIOS to flash. Rather than trying to stop root from destroying
hardware I'd prefer to make sure the system doesn't run as root or
make sure that the hardware can't be destroyed, or that it doesn't
matter if it IS destroyed. (Security commands unsupported or VMware
or frequent backups or ..)


//Peter



From ralph at inputplus.co.uk  Mon May 23 19:13:32 2005
From: ralph at inputplus.co.uk (Ralph Corderoy)
Date: Mon, 23 May 2005 18:13:32 +0100
Subject: [LinuxBIOS] Adding Support for ATA Freeze Command. 
In-Reply-To: <20050522030637.GA11366@foo.birdnet.se> 
Message-ID: <200505231713.j4NHDWO02433@blake.inputplus.co.uk>


Hi Peter,

> > Custom hardware could do the reset but I don't know if it's within
> > the ability of a BIOS?
> 
> It's certainly possible to add a simple reset circuitry using common
> components (one resistor+one transistor) on e.g. a parallell port and
> control it from the BIOS. Just twisting wires together with component
> pins would be enough, and doable in any environment.

OK, well if I come back in another life where I have some free time I'll
have a play.

> > I am aware that someone in the UK has built hardware that can
> > brute-force it in under 12 hours.
> 
> Ok. I haven't made any tests even though I've thought about this
> matter earlier, but 12 hours feels a bit short. I guess it isn't
> particularly CPU intensive though, no encryption, just add one and
> send, with the occasional reset..

I too thought it was a bit short but he works for a hard disc company
and I wouldn't be surprised if either he has some means of detecting
whether he's getting warmer or not, or perhaps he just tries likely
passwords first and he was talking about the typical time taken.

> > It's possible in Linux already at the system call level, and
> > recently hdparm added support through its -F option -- the c't
> > article's author sent a patch IIRC, but by the time Linux is running
> > is a bit late.  A malicious program running under Linux where Freeze
> > has already been done by hdparm could write to the MBR causing the
> > password to be set on the next boot.  That's unless the BIOS has
> > done a Freeze before the MBR gets run.
> 
> My humble opinion is that you have much bigger problems if a malicious
> program has root priviledges in your system.
> 
> Sure, if a security "hole" is easy to plug, why not plug it, but there
> are many other security measures that can and should be used on
> production systems with important data that are effective for
> recovering from an attack of this kind as well as several others.
> (Redundant hardware and storage, with external backups.)

A scenario:  I have daily backups, I carry out a post-mortem after
detecting an intrusion, I'm happy to re-install from scratch and restore
a known-safe backup, and fix the entry point of the cracker before
exposing the machine to the network.  But the hard drive is now for the
bin because it's been locked.

I'm happy to take all those other precautions, but I'm trying to cut out
one of the few things a malicious, remote, cracker could do that costs
me hardware.

> The intention, however, has always been to use Linux as the boot-
> from-anything payload and we're getting closer to that becoming
> reality each day. The showstopper is flash ROM size, but that is
> increasing on new mainboards, and LPC (where any size ROM can be used)
> is getting much more popular as well.
> 
> Then, suddenly, the Linux kernel isn't so late in the boot process.
> Remember, LinuxBIOS doesn't care about legacy junk such as the MBR, it
> starts the payload immediately, as per compile-time configuration.

I agree if the Linux kernel is very early on, i.e. the BIOS stage, then
it's good enough for the kernel to do it.  I was talking about the OS
once started by the bootloader.  But wouldn't that require a run-time
option again because you'd want to avoid the freeze happening some
times, and without flashing a new BIOS.

> But, if the malicious program can write to MBR, it can also write a
> new BIOS to flash. Rather than trying to stop root from destroying
> hardware I'd prefer to make sure the system doesn't run as root or
> make sure that the hardware can't be destroyed, or that it doesn't
> matter if it IS destroyed. (Security commands unsupported or VMware or
> frequent backups or ..)

It's far easier and more portable to write the MBR than it is the BIOS.
Given root access will sometimes be obtained I'd like to stop them being
able to make my hard drive defunct;  its data I've got backed up,
offline.  It's all a trade-off but it would seem that adding an ATA
Freeze most of the time on start-up is a worthwhile one.

Cheers,


Ralph.




From stuge-linuxbios at cdy.org  Mon May 23 20:41:48 2005
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Mon, 23 May 2005 20:41:48 +0200
Subject: [LinuxBIOS] Adding Support for ATA Freeze Command.
In-Reply-To: <200505231713.j4NHDWO02433@blake.inputplus.co.uk>
References: <20050522030637.GA11366@foo.birdnet.se>
	<200505231713.j4NHDWO02433@blake.inputplus.co.uk>
Message-ID: <20050523184148.GB30028@foo.birdnet.se>

Hi again Ralph,

On Mon, May 23, 2005 at 06:13:32PM +0100, Ralph Corderoy wrote:
> > My humble opinion is that you have much bigger problems if a malicious
> > program has root priviledges in your system.
> > 
> > Sure, if a security "hole" is easy to plug, why not plug it, but there
> > are many other security measures that can and should be used on
> > production systems with important data that are effective for
> > recovering from an attack of this kind as well as several others.
> > (Redundant hardware and storage, with external backups.)
> 
> A scenario:  I have daily backups, I carry out a post-mortem after
> detecting an intrusion, I'm happy to re-install from scratch and restore
> a known-safe backup, and fix the entry point of the cracker before
> exposing the machine to the network.  But the hard drive is now for the
> bin because it's been locked.
> 
> I'm happy to take all those other precautions, but I'm trying to cut out
> one of the few things a malicious, remote, cracker could do that costs
> me hardware.

Right, no redundant storage, which probably wouldn't be susceptible
to the problem anyway since the security commands only work with ATA
and S-ATA drives.

I know I wouldn't care much about the ATA drive if I was prepared to
deal with downtime and labor required for forensics and recovery in
the above scenario.


> > Then, suddenly, the Linux kernel isn't so late in the boot process.
> > Remember, LinuxBIOS doesn't care about legacy junk such as the MBR, it
> > starts the payload immediately, as per compile-time configuration.
> 
> I agree if the Linux kernel is very early on, i.e. the BIOS stage,
> then it's good enough for the kernel to do it.  I was talking about
> the OS once started by the bootloader.

With Linux as the payload, the OS is the bootloader. :)


> But wouldn't that require a run-time option again because you'd
> want to avoid the freeze happening some times, and without flashing
> a new BIOS.

Right. And the option can't be accessible by root.


> It's far easier and more portable to write the MBR than it is the
> BIOS. Given root access will sometimes be obtained I'd like to stop
> them being able to make my hard drive defunct;  its data I've got
> backed up, offline.  It's all a trade-off but it would seem that
> adding an ATA Freeze most of the time on start-up is a worthwhile
> one.

"more difficult and less portable" is not "secure" - I would argue
quite the opposite; it's security by obscurity, and that's always a
bad idea.

But sure, if you want to protect the BIOS from software run as root,
use real ROM (not flash). And if you want to protect the ATA drive
from being locked by root, have the software in ROM send a freeze
command.

Question is, should LinuxBIOS really go about changing configuration
and settings of the hardware beyond what is absolutely neccessary for
the payload to function?

I'm not sure it should, I think it's better to put the freeze command
in FILO or Linux or 9load or ADLO or whatever payload.

>From a security point of view it doesn't matter since the LinuxBIOS
init code and payload are stored in the same place and if the payload
can be changed the init code can be changed too.


//Peter



From josiah at lanl.gov  Tue May 24 00:14:57 2005
From: josiah at lanl.gov (Josiah England)
Date: Mon, 23 May 2005 16:14:57 -0600
Subject: [LinuxBIOS] VIA VT8231 documentation
Message-ID: <1116886498.7018.21.camel@plipper.ccstar>

Does anyone have good links to recent documentation?  Latest I have is
from 2/1/2001.




From bari at onelabs.com  Tue May 24 01:39:11 2005
From: bari at onelabs.com (Bari Ari)
Date: Mon, 23 May 2005 18:39:11 -0500
Subject: [LinuxBIOS] VIA VT8231 documentation
In-Reply-To: <1116886498.7018.21.camel@plipper.ccstar>
References: <1116886498.7018.21.camel@plipper.ccstar>
Message-ID: <4292699F.4090603@onelabs.com>

Josiah England wrote:
> Does anyone have good links to recent documentation?  Latest I have is
> from 2/1/2001.

http://www.via.com.tw/en/resources/download-center/chipsets/




From YhLu at tyan.com  Tue May 24 05:02:48 2005
From: YhLu at tyan.com (YhLu)
Date: Mon, 23 May 2005 20:02:48 -0700
Subject: [LinuxBIOS] About Nvidia chipset support
Message-ID: <3174569B9743D511922F00A0C943142309F8143F@TYANWEB>

Onboard SATA works now.

YH 

> -----Original Message-----
> From: YhLu 
> Sent: Friday, May 13, 2005 1:54 PM
> To: 'Ronald G. Minnich'; 'ebiederman at lnxi.com'; 'Stefan 
> Reinauer'; 'Li-Ta Lo'
> Cc: 'linuxbios at openbios.org'
> Subject: RE: [LinuxBIOS] About Nvidia chipset support
> 
> Just commit some lines to  ondie Lan work now.
> 
> YH
> 
> > -----Original Message-----
> > From: YhLu
> > Sent: Wednesday, May 11, 2005 1:36 PM
> > To: YhLu; Ronald G. Minnich; ebiederman at lnxi.com; Stefan Reinauer; 
> > Li-Ta Lo
> > Cc: linuxbios at openbios.org
> > Subject: RE: [LinuxBIOS] About Nvidia chipset support
> > 
> > commited. 
> > 
> > > -----Original Message-----
> > > From: YhLu
> > > Sent: Wednesday, May 11, 2005 11:21 AM
> > > To: Ronald G. Minnich; ebiederman at lnxi.com; Stefan
> > Reinauer; Li-Ta Lo
> > > Cc: linuxbios at openbios.org
> > > Subject: [LinuxBIOS] About Nvidia chipset support
> > > 
> > > All,
> > > 
> > > Finally I get the approval for releasing Nvidia chipset 
> support for 
> > > Ck804. I hope end user to press nvidia to release more 
> info to make 
> > > sata and on die lan work.
> > > 
> > > The problem my code is messed up dual core support etc. I 
> need some 
> > > time to split them up.
> > > 
> > > I will commit soon about
> > > Nvidia CK804 support
> > > smbus bus number support (to handle multi sumbus and mux)
> > superio smsc
> > > 47 support Tyan S2895/S2891/S2892 support flash_rom Ck804 support
> > > 
> > > maybe two months later after AMD issue auth letter or put
> > dual core on
> > > public
> > > 
> > > AMD D0/E0 Opteron new mem mapping support AMD E Opteron dual core 
> > > support AMD E Opteron mem hole support AMD K8 Four Ranks
> > DIMM support
> > > 
> > > Regards
> > > 
> > > YH
> > > 
> > > _______________________________________________
> > > LinuxBIOS mailing list
> > > LinuxBIOS at openbios.org
> > > http://www.openbios.org/mailman/listinfo/linuxbios
> > > 
> > 
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From YhLu at tyan.com  Tue May 24 18:56:34 2005
From: YhLu at tyan.com (YhLu)
Date: Tue, 24 May 2005 09:56:34 -0700
Subject: [LinuxBIOS] RE: boot from SATA
Message-ID: <3174569B9743D511922F00A0C943142309F81459@TYANWEB>

Please use 5.2.6 and gcc 3.2.2, so you need to use RH9. for that.
 
You may try 5.4 too (use CVS to get latest one), it can be compiled in late
compiler.
 
The problem it doesn't support memtest till now....
 
YH


  _____  

From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
Sent: Tuesday, May 24, 2005 9:31 AM
To: YhLu
Subject: boot from SATA



YH,

 

I want to boot from a SATA drive with etherboot.

I made the Config file change from
http://www.linuxbios.org/index.php/Etherboot
<http://www.linuxbios.org/index.php/Etherboot> .

But I get these errors:

 

ld -r bin/tg3.o bin/filo.rt.o -o bin/tg3--filo.rt.o

objcopy -R .text16 bin/elfprefix.o bin/elfprefix.entry.o

objcopy -R .prefix bin/elfprefix.o bin/elfprefix.exit.o

ld  -N -T arch/i386/core/etherboot.lds -o bin/tg3--filo.elf.rt
bin/elfprefix.exit.o  bin/tg3--filo.rt.o

bin/tg3--filo.rt.o(.text+0x4507): In function `install_pxe_stack':

: undefined reference to `allot_base_memory'

bin/tg3--filo.rt.o(.text+0x457e): In function `install_pxe_stack':

: undefined reference to `e820mangler_size'

bin/tg3--filo.rt.o(.text+0x4763): In function `install_pxe_stack':

: undefined reference to `install_rm_callback_interface'

bin/tg3--filo.rt.o(.text+0x4769): In function `install_pxe_stack':

: undefined reference to `install_e820mangler'

bin/tg3--filo.rt.o(.text+0x4787): In function `use_undi_ds_for_rm_stack':

: undefined reference to `forget_real_mode_stack'

bin/tg3--filo.rt.o(.text+0x47b7): In function `hook_pxe_stack':

: undefined reference to `hide_etherboot'

bin/tg3--filo.rt.o(.text+0x4852): In function `unhook_pxe_stack':

: undefined reference to `unhide_etherboot'

bin/tg3--filo.rt.o(.text+0x4889): In function `remove_pxe_stack':

: undefined reference to `forget_base_memory'

bin/tg3--filo.rt.o(.text+0x4a51): In function `filo_pci_probe':

: undefined reference to `filo'

bin/tg3--filo.rt.o(.text+0x98b9): In function `pxenv_restart_tftp':

: undefined reference to `get_free_base_memory'

make: *** [bin/tg3--filo.elf.rt] Error 1

rm bin/elfprefix.exit.o bin/tg3--filo.rt.o bin/filo.rt.o
bin/elfprefix.entry.o bin/filo.o

 

What am I missing?  Thanks.

 

Steve

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From Stephen.Kimball at bench.com  Wed May 25 14:13:05 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed, 25 May 2005 08:13:05 -0400
Subject: [LinuxBIOS] etherboot with LinuxBIOS
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C4F@nh-ex01.bench.com>


Does anyone know how to build etherboot with a current version of gcc?
I am using gcc version 3.4.3 and binutils 2.15.
I've tried several etherboot versions up to 5.4.0.
I know etherboot 5.2.6 with gcc 3.2.2 works, but that's an old version of gcc.  Thanks.

Steve 



From kfuchs at winternet.com  Wed May 25 15:14:23 2005
From: kfuchs at winternet.com (Ken Fuchs)
Date: Wed, 25 May 2005 08:14:23 -0500
Subject: [LinuxBIOS] Using tla (gnuarch) through a proxy server/firewall
Message-ID: <200505251314.j4PDEN714318@ecstasy1.winternet.com>

I'm trying to setup tla access to the LinuxBIOS (openbios.org) archive
through a proxy server that also functions as a firewall.

The proxy server is denying access when I try to do:

$ tla register-archive \
      ftp://openbios.org/pub/arch/linuxbios at linuxbios.org--devel

Can http be used instead of ftp in the above URL?

I'm using the following environment variable, defined with

$ ftp_proxy = http://<username>:<password>@<proxy-server>:<proxy-port>
$ export ftp_proxy

where <username>, <password>, <proxy-server>, <proxy-port> are all
replaced by literal values acceptable to the proxy server.

I've tried to use google to shed light on this issue, but haven't found
anything useful.

------

I've got yum working through this proxy server using http_proxy:

$ http_proxy = http://<username>:<password>@<proxy-server>:<proxy-port>
$ export http_proxy

So, I know that at least http passes through the proxy server just fine.

------

Any suggestions or comments?

Sincerely,

Ken Fuchs <kfuchs at winternet.com>



From rminnich at lanl.gov  Wed May 25 17:13:09 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Wed, 25 May 2005 09:13:09 -0600 (MDT)
Subject: [LinuxBIOS] How is 'arch' working for you?
Message-ID: <Pine.LNX.4.58.0505250912220.12496@enigma.lanl.gov>


Are folks getting along with 'arch' ok? Are you able to download as 
needed? How does it compare to CVS? Is there a different SCM you would 
like to see used?

thanks

ron



From gwatson at lanl.gov  Wed May 25 17:33:32 2005
From: gwatson at lanl.gov (Greg Watson)
Date: Wed, 25 May 2005 09:33:32 -0600
Subject: [LinuxBIOS] How is 'arch' working for you?
In-Reply-To: <Pine.LNX.4.58.0505250912220.12496@enigma.lanl.gov>
References: <Pine.LNX.4.58.0505250912220.12496@enigma.lanl.gov>
Message-ID: <99AC1C67-1D60-464C-BF47-7ABEF397B333@lanl.gov>

It scares the crap out of me. I'm now using 3 different systems (CVS,  
svn, arch) which is painful. Not only do I need to remember three  
sets of commands, but I have to maintain the three installations.

Just my $0.02 worth.

Greg


On May 25, 2005, at 9:13 AM, Ronald G. Minnich wrote:

>
> Are folks getting along with 'arch' ok? Are you able to download as
> needed? How does it compare to CVS? Is there a different SCM you would
> like to see used?
>
> thanks
>
> ron
>
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>




From smithbone at gmail.com  Wed May 25 18:04:26 2005
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 25 May 2005 11:04:26 -0500
Subject: [LinuxBIOS] How is 'arch' working for you?
In-Reply-To: <99AC1C67-1D60-464C-BF47-7ABEF397B333@lanl.gov>
References: <Pine.LNX.4.58.0505250912220.12496@enigma.lanl.gov>
	<99AC1C67-1D60-464C-BF47-7ABEF397B333@lanl.gov>
Message-ID: <8a0c367805052509046d1ceb00@mail.gmail.com>

> > Are folks getting along with 'arch' ok? Are you able to download as
> > needed? How does it compare to CVS? Is there a different SCM you would
> > like to see used?

This seems like a lead in... *grin*  Are you getting along with arch? 
 I've yet to actually commit anything to linuxbios since I just
reciently fixed up my key.

Reciently though on some projects here at Bitworks we have had a few
CVS gotcha's cause some pain.  So I've been looking for a replacement
and playing with various scm a bit. I've messed with
arch,svn,bazzar-ng, and darcs.  With web page reads of the myriad of
other scms that are popping up.

IMHO arch is just too unwieldly.  I can't imagine trying to explain it
to the other developers here at Bitworks.  baz might make this easier
but that's not one I've looked at that.  Perhpas I'll mess with baz
for trying a commit of the 440bx stuff.

I'm not advocating (yet) but darcs is currently leading the pack on
replacing CVS here at Bitworks.  A nifty additional benefit is that
darcs can now (mostly) work with kernel git trees.

-- 
Richard A. Smith



From ollie at lanl.gov  Wed May 25 21:12:19 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Wed, 25 May 2005 13:12:19 -0600
Subject: [LinuxBIOS] How is 'arch' working for you?
In-Reply-To: <99AC1C67-1D60-464C-BF47-7ABEF397B333@lanl.gov>
References: <Pine.LNX.4.58.0505250912220.12496@enigma.lanl.gov>
	<99AC1C67-1D60-464C-BF47-7ABEF397B333@lanl.gov>
Message-ID: <1117048339.4346.8.camel@exponential.lanl.gov>

On Wed, 2005-05-25 at 09:33 -0600, Greg Watson wrote:
> It scares the crap out of me. I'm now using 3 different systems (CVS,  
> svn, arch) which is painful. Not only do I need to remember three  
> sets of commands, but I have to maintain the three installations.
> 
> Just my $0.02 worth.
> 

Does your PDT try to cope with this? An integrate enviroment for those
revision control systems?

-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From ollie at lanl.gov  Wed May 25 21:13:57 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Wed, 25 May 2005 13:13:57 -0600
Subject: [LinuxBIOS] How is 'arch' working for you?
In-Reply-To: <8a0c367805052509046d1ceb00@mail.gmail.com>
References: <Pine.LNX.4.58.0505250912220.12496@enigma.lanl.gov>
	<99AC1C67-1D60-464C-BF47-7ABEF397B333@lanl.gov>
	<8a0c367805052509046d1ceb00@mail.gmail.com>
Message-ID: <1117048437.4346.10.camel@exponential.lanl.gov>

On Wed, 2005-05-25 at 11:04 -0500, Richard Smith wrote:
> I'm not advocating (yet) but darcs is currently leading the pack on
> replacing CVS here at Bitworks.  A nifty additional benefit is that
> darcs can now (mostly) work with kernel git trees.
> 

Is it the Haskell one ?

-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From smithbone at gmail.com  Wed May 25 21:16:26 2005
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 25 May 2005 14:16:26 -0500
Subject: [LinuxBIOS] How is 'arch' working for you?
In-Reply-To: <1117048437.4346.10.camel@exponential.lanl.gov>
References: <Pine.LNX.4.58.0505250912220.12496@enigma.lanl.gov>
	<99AC1C67-1D60-464C-BF47-7ABEF397B333@lanl.gov>
	<8a0c367805052509046d1ceb00@mail.gmail.com>
	<1117048437.4346.10.camel@exponential.lanl.gov>
Message-ID: <8a0c367805052512165903b610@mail.gmail.com>

> > replacing CVS here at Bitworks.  A nifty additional benefit is that
> > darcs can now (mostly) work with kernel git trees.
> > 
> Is it the Haskell one ?

Yeah.

-- 
Richard A. Smith



From gwatson at lanl.gov  Wed May 25 22:22:38 2005
From: gwatson at lanl.gov (Greg Watson)
Date: Wed, 25 May 2005 14:22:38 -0600
Subject: [LinuxBIOS] How is 'arch' working for you?
In-Reply-To: <1117048339.4346.8.camel@exponential.lanl.gov>
References: <Pine.LNX.4.58.0505250912220.12496@enigma.lanl.gov>
	<99AC1C67-1D60-464C-BF47-7ABEF397B333@lanl.gov>
	<1117048339.4346.8.camel@exponential.lanl.gov>
Message-ID: <6A544D6B-0664-4054-897F-2EDC2403DAB3@lanl.gov>


On May 25, 2005, at 1:12 PM, Li-Ta Lo wrote:

> On Wed, 2005-05-25 at 09:33 -0600, Greg Watson wrote:
>
>> It scares the crap out of me. I'm now using 3 different systems (CVS,
>> svn, arch) which is painful. Not only do I need to remember three
>> sets of commands, but I have to maintain the three installations.
>>
>> Just my $0.02 worth.
>>
>>
>
> Does your PDT try to cope with this? An integrate enviroment for those
> revision control systems?
>

As far as I know there's only CVS and subversion support for Eclipse.

Greg




From Stephen.Kimball at bench.com  Wed May 25 22:29:13 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed, 25 May 2005 16:29:13 -0400
Subject: [LinuxBIOS] does the CK804 code work?
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C53@nh-ex01.bench.com>


YH,

After running the new CK804 code, I'm having trouble getting the CK804 devices to work.  Most references to ck804_enable are commented out.
I'm wondering how devices get enabled.

Steve 



From YhLu at tyan.com  Wed May 25 22:56:59 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 25 May 2005 13:56:59 -0700
Subject: [LinuxBIOS] RE: does the CK804 code work?
Message-ID: <3174569B9743D511922F00A0C943142309F815F7@TYANWEB>

through enable_dev.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 25, 2005 1:29 PM
> To: YhLu
> Cc: linuxbios at openbios.org
> Subject: does the CK804 code work?
> 
> 
> YH,
> 
> After running the new CK804 code, I'm having trouble getting 
> the CK804 devices to work.  Most references to ck804_enable 
> are commented out.
> I'm wondering how devices get enabled.
> 
> Steve 
> 



From Stephen.Kimball at bench.com  Wed May 25 23:14:17 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Wed, 25 May 2005 17:14:17 -0400
Subject: [LinuxBIOS] RE: does the CK804 code work?
Message-ID: <9B124F08B3EFDA4F8813B05102DC719502905B1B@nh-ex01.bench.com>

You're right, but why comment it out everywhere except enable_dev?

grep ck804_enable *
ck804_ac97.c:// .enable           = ck804_enable,
ck804_ac97.c:// .enable           = ck804_enable,
ck804.c:void ck804_enable(device_t dev)
ck804.c:        .enable_dev = ck804_enable,
ck804_enable_rom.c:static void ck804_enable_rom(void)
ck804.h:void ck804_enable(device_t dev);
ck804_ide.c://  .enable           = ck804_enable,
ck804_lpc.c://  .enable           = ck804_enable,
ck804_lpc.c://        .enable           = ck804_enable,
ck804_nic.c://  .enable           = ck804_enable,
ck804_pci.c://  .enable           = ck804_enable,
ck804_pcie.c:// .enable           = ck804_enable,
ck804_sata.c:// .enable           = ck804_enable,
ck804_smbus.c://        .enable           = ck804_enable,
ck804_usb2.c:// .enable           = ck804_enable,
ck804_usb.c://  .enable           = ck804_enable,

Steve 

-----Original Message-----
From: YhLu [mailto:YhLu at tyan.com] 
Sent: Wednesday, May 25, 2005 4:57 PM
To: Kimball, Stephen
Cc: linuxbios at openbios.org
Subject: RE: does the CK804 code work?

through enable_dev.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 25, 2005 1:29 PM
> To: YhLu
> Cc: linuxbios at openbios.org
> Subject: does the CK804 code work?
> 
> 
> YH,
> 
> After running the new CK804 code, I'm having trouble getting 
> the CK804 devices to work.  Most references to ck804_enable 
> are commented out.
> I'm wondering how devices get enabled.
> 
> Steve 
> 



From YhLu at tyan.com  Thu May 26 03:12:46 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 25 May 2005 18:12:46 -0700
Subject: [LinuxBIOS] Is any notebook with Nvidia NForce4 or Ck804?
Message-ID: <3174569B9743D511922F00A0C943142309F81667@TYANWEB>

Is any notebook with Nvidia NForce4 or CK804?

It seems there is some with NForce3.....

YH



From YhLu at tyan.com  Thu May 26 03:15:05 2005
From: YhLu at tyan.com (YhLu)
Date: Wed, 25 May 2005 18:15:05 -0700
Subject: [LinuxBIOS] RE: does the CK804 code work?
Message-ID: <3174569B9743D511922F00A0C943142309F81669@TYANWEB>

You could talk to Nvidia to see if I can release support code for their
CRB....

It seems that you have spend lot of time on it.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 25, 2005 1:29 PM
> To: YhLu
> Cc: linuxbios at openbios.org
> Subject: does the CK804 code work?
> 
> 
> YH,
> 
> After running the new CK804 code, I'm having trouble getting 
> the CK804 devices to work.  Most references to ck804_enable 
> are commented out.
> I'm wondering how devices get enabled.
> 
> Steve 
> 



From Stephen.Kimball at bench.com  Thu May 26 14:35:10 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Thu, 26 May 2005 08:35:10 -0400
Subject: [LinuxBIOS] RE: does the CK804 code work?
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C55@nh-ex01.bench.com>

We have the CRB working. We'd like to work with you and nVidia to
improve what you have released.

Steve

-----Original Message-----
From: YhLu [mailto:YhLu at tyan.com] 
Sent: Wednesday, May 25, 2005 9:15 PM
To: Kimball, Stephen
Cc: linuxbios at openbios.org
Subject: RE: does the CK804 code work?

You could talk to Nvidia to see if I can release support code for their
CRB....

It seems that you have spend lot of time on it.

YH 

> -----Original Message-----
> From: Stephen.Kimball at bench.com [mailto:Stephen.Kimball at bench.com] 
> Sent: Wednesday, May 25, 2005 1:29 PM
> To: YhLu
> Cc: linuxbios at openbios.org
> Subject: does the CK804 code work?
> 
> 
> YH,
> 
> After running the new CK804 code, I'm having trouble getting 
> the CK804 devices to work.  Most references to ck804_enable 
> are commented out.
> I'm wondering how devices get enabled.
> 
> Steve 
> 



From Stephen.Kimball at bench.com  Thu May 26 18:37:59 2005
From: Stephen.Kimball at bench.com (Stephen.Kimball at bench.com)
Date: Thu, 26 May 2005 12:37:59 -0400
Subject: [LinuxBIOS] CK804 hard_reset
Message-ID: <9B124F08B3EFDA4F8813B05102DC719503A40C59@nh-ex01.bench.com>


One of the hard_reset() functions are wrong.  The two files don't agree:
  src/mainboard/tyan/s2895/auto.c
  src/southbridge/nvidia/ck804/ck804_reset.c

I think auto.c is correct, but I'd suggest changing it to:

static void hard_reset(void)
{
        set_bios_reset();

        pci_write_config32(PCI_DEV(1, CK804_DEVN_BASE + 0x1, 0), 0xe8, 0x0);

        /* hard reset */
        outb(0x0a, 0x0cf9); 
        outb(0x0e, 0x0cf9);

L1:     goto L1;            /* loop till reset */
}



From YhLu at tyan.com  Thu May 26 20:07:39 2005
From: YhLu at tyan.com (YhLu)
Date: Thu, 26 May 2005 11:07:39 -0700
Subject: [LinuxBIOS] Is any notebook with Nvidia NForce4 or Ck804?
Message-ID: <3174569B9743D511922F00A0C943142309F816F8@TYANWEB>

 ATI Xpress 200M in HP ZV6000 support pci-e. 

I wonder why there is no Nvidia CK804M for NB.  Too hot?

First NB support LinuxBIOS?

YH

> -----Original Message-----
> From: YhLu 
> Sent: Wednesday, May 25, 2005 6:13 PM
> To: linuxbios at openbios.org
> Subject: [LinuxBIOS] Is any notebook with Nvidia NForce4 or Ck804?
> 
> Is any notebook with Nvidia NForce4 or CK804?
> 
> It seems there is some with NForce3.....
> 
> YH
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From steve at digidescorp.com  Fri May 27 05:20:05 2005
From: steve at digidescorp.com (Steve Magnani)
Date: Thu, 26 May 2005 22:20:05 -0500
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
Message-ID: <WorldClient-F200505262220.AA20050010@digidescorp.com>

Hi,

Does anyone (Steven James? yhlu?) know what registers 0x14, 0xD8, and 0xF4
in the E7501's D0:F0 PCI configuration space are for? I know that 0x80 and
0x88 are undocumented, but I didn't see anything in the code
(northbridge/intel/e7501/raminit.c) that said these others were
undocumented. Unfortunately, they seem to be; at least, I can't find any
mention of them in any of the Intel documentation I have.

Also, if I am reading the code correctly, the last entry in
register_values[] will update D2:F0:0x50. That register is also undocumented.

Any help would be much appreciated...

Thanks,
Steve Magnani
www.digidescorp.com





From YhLu at tyan.com  Fri May 27 19:03:07 2005
From: YhLu at tyan.com (YhLu)
Date: Fri, 27 May 2005 10:03:07 -0700
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
Message-ID: <3174569B9743D511922F00A0C943142309F81805@TYANWEB>

why still waste time on Intel platform? They will not support  LinuxBIOS,
because they have EFI....

YH

> -----Original Message-----
> From: Steve Magnani [mailto:steve at digidescorp.com] 
> Sent: Thursday, May 26, 2005 8:20 PM
> To: linuxbios at openbios.org
> Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
> 
> Hi,
> 
> Does anyone (Steven James? yhlu?) know what registers 0x14, 
> 0xD8, and 0xF4 in the E7501's D0:F0 PCI configuration space 
> are for? I know that 0x80 and
> 0x88 are undocumented, but I didn't see anything in the code
> (northbridge/intel/e7501/raminit.c) that said these others 
> were undocumented. Unfortunately, they seem to be; at least, 
> I can't find any mention of them in any of the Intel 
> documentation I have.
> 
> Also, if I am reading the code correctly, the last entry in 
> register_values[] will update D2:F0:0x50. That register is 
> also undocumented.
> 
> Any help would be much appreciated...
> 
> Thanks,
> Steve Magnani
> www.digidescorp.com
> 
> 
> 
> _______________________________________________
> LinuxBIOS mailing list
> LinuxBIOS at openbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 



From steve at digidescorp.com  Fri May 27 19:14:06 2005
From: steve at digidescorp.com (Steven J. Magnani)
Date: Fri, 27 May 2005 12:14:06 -0500
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
In-Reply-To: <3174569B9743D511922F00A0C943142309F81805@TYANWEB>
Message-ID: <006901c562df$80220770$6ffea8c0@banana>

> From: YhLu [mailto:YhLu at tyan.com] 
> why still waste time on Intel platform? They will not support
LinuxBIOS, because they have EFI....

So, you'd recommend using EFI over LinuxBIOS?

Steve






From YhLu at tyan.com  Fri May 27 19:19:14 2005
From: YhLu at tyan.com (YhLu)
Date: Fri, 27 May 2005 10:19:14 -0700
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
Message-ID: <3174569B9743D511922F00A0C943142309F8180E@TYANWEB>

No.

Acctually you should select that according to your applicance....

Maybe change to use AMD or other platform, or even PowerPC.

YH 

> -----Original Message-----
> From: Steven J. Magnani [mailto:steve at digidescorp.com] 
> Sent: Friday, May 27, 2005 10:14 AM
> To: YhLu; linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] Intel E7501 Northbridge head-scratching
> 
> > From: YhLu [mailto:YhLu at tyan.com]
> > why still waste time on Intel platform? They will not support
> LinuxBIOS, because they have EFI....
> 
> So, you'd recommend using EFI over LinuxBIOS?
> 
> Steve
> 
> 
> 



From rminnich at lanl.gov  Fri May 27 19:22:39 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 27 May 2005 11:22:39 -0600 (MDT)
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
In-Reply-To: <006901c562df$80220770$6ffea8c0@banana>
References: <3174569B9743D511922F00A0C943142309F81805@TYANWEB>
	<006901c562df$80220770$6ffea8c0@banana>
Message-ID: <50434.128.165.0.81.1117214559.squirrel@webmail.lanl.gov>

>> From: YhLu [mailto:YhLu at tyan.com]
>> why still waste time on Intel platform? They will not support
> LinuxBIOS, because they have EFI....
>
> So, you'd recommend using EFI over LinuxBIOS?

I believe he is recommending not using intel because intel will not
support linuxbios.

I can not endorse any given vendor due to DOE rules; I can, however, say
that LANL is only buying linuxbios-based cluster nodes these days.

ron



From steve at digidescorp.com  Fri May 27 19:22:15 2005
From: steve at digidescorp.com (Steven J. Magnani)
Date: Fri, 27 May 2005 12:22:15 -0500
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
In-Reply-To: <3174569B9743D511922F00A0C943142309F8180E@TYANWEB>
Message-ID: <006a01c562e0$a3d9e650$6ffea8c0@banana>

> Maybe change to use AMD or other platform, or even PowerPC.

The architecture is fixed. I either have to find a way to make LinuxBIOS
work with it, or switch to something else. Which comes back to my
original question...is there any more information available on the
undocumented things the LinuxBIOS E7501 code does? Does the LinuxBIOS
community support this code, or recommend against using it?

Steve






From YhLu at tyan.com  Fri May 27 19:28:56 2005
From: YhLu at tyan.com (YhLu)
Date: Fri, 27 May 2005 10:28:56 -0700
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
Message-ID: <3174569B9743D511922F00A0C943142309F81813@TYANWEB>

What i did about Intel LinuxBIOS support
1. change ICH5 to ICH5R in v1.
2. move E7501 and ICH5R from V1 and V2.

For SB, documentation should be enough.
For NB, I guess there is some undocumented info, and you may talk to intel
directly or hack it out.

YH

> -----Original Message-----
> From: Steven J. Magnani [mailto:steve at digidescorp.com] 
> Sent: Friday, May 27, 2005 10:22 AM
> To: YhLu; linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] Intel E7501 Northbridge head-scratching
> 
> > Maybe change to use AMD or other platform, or even PowerPC.
> 
> The architecture is fixed. I either have to find a way to 
> make LinuxBIOS work with it, or switch to something else. 
> Which comes back to my original question...is there any more 
> information available on the undocumented things the 
> LinuxBIOS E7501 code does? Does the LinuxBIOS community 
> support this code, or recommend against using it?
> 
> Steve
> 
> 
> 



From rminnich at lanl.gov  Sat May 28 05:39:10 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 27 May 2005 21:39:10 -0600 (MDT)
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
In-Reply-To: <006a01c562e0$a3d9e650$6ffea8c0@banana>
References: <006a01c562e0$a3d9e650$6ffea8c0@banana>
Message-ID: <Pine.LNX.4.58.0505272137350.19494@enigma.lanl.gov>



On Fri, 27 May 2005, Steven J. Magnani wrote:
> The architecture is fixed. I either have to find a way to make LinuxBIOS

we are also working here on V2 and 7501 for other reasons. 

I think the code can be made to work. 

On another note, we just found and killed an extremely nasty bug in the
EPIA port, early in ram init. Once we can get 'arch' working for josiah he
can commit the latest epia patches. I think that we can say 'epia is good'
very soon.

Next will be epia-m.

ron



From rminnich at lanl.gov  Sat May 28 05:39:56 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Fri, 27 May 2005 21:39:56 -0600 (MDT)
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
In-Reply-To: <3174569B9743D511922F00A0C943142309F81813@TYANWEB>
References: <3174569B9743D511922F00A0C943142309F81813@TYANWEB>
Message-ID: <Pine.LNX.4.58.0505272139330.19494@enigma.lanl.gov>



On Fri, 27 May 2005, YhLu wrote:

> For NB, I guess there is some undocumented info, and you may talk to intel
> directly or hack it out.

and we can be pretty sure, based on Intel's comments w.r.t LinuxBIOS, that 
they will decline to help. 

ron



From talbotx at comcast.net  Tue May 31 03:26:09 2005
From: talbotx at comcast.net (Adam Talbot)
Date: Mon, 30 May 2005 18:26:09 -0700
Subject: [LinuxBIOS] EPIA-M status
References: <3174569B9743D511922F00A0C943142309F81813@TYANWEB>
	<Pine.LNX.4.58.0505272139330.19494@enigma.lanl.gov>
Message-ID: <001d01c5657f$bc7ce1c0$c501a8c0@newflame>

Any one had any time to look at the EPIA-M code?  Or is it still broken?
-Adam




From rminnich at lanl.gov  Tue May 31 05:43:29 2005
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon, 30 May 2005 21:43:29 -0600 (MDT)
Subject: [LinuxBIOS] Re: EPIA-M status
In-Reply-To: <001d01c5657f$bc7ce1c0$c501a8c0@newflame>
References: <3174569B9743D511922F00A0C943142309F81813@TYANWEB>
	<Pine.LNX.4.58.0505272139330.19494@enigma.lanl.gov>
	<001d01c5657f$bc7ce1c0$c501a8c0@newflame>
Message-ID: <Pine.LNX.4.58.0505302143210.27215@enigma.lanl.gov>



On Mon, 30 May 2005, Adam Talbot wrote:

> Any one had any time to look at the EPIA-M code?  Or is it still broken?

give us time, we're wrapping up epia now.

ron



From ollie at lanl.gov  Tue May 31 19:39:45 2005
From: ollie at lanl.gov (Li-Ta Lo)
Date: Tue, 31 May 2005 11:39:45 -0600
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
In-Reply-To: <3174569B9743D511922F00A0C943142309F81805@TYANWEB>
References: <3174569B9743D511922F00A0C943142309F81805@TYANWEB>
Message-ID: <1117561185.3602.1.camel@logarithm.lanl.gov>

On Fri, 2005-05-27 at 10:03 -0700, YhLu wrote:
> why still waste time on Intel platform? They will not support  LinuxBIOS,
> because they have EFI....
> 

BTW, is tyan s2735 code in the current tla tree working? We tried to
use it as a base for a supermicro board but failed.

-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab




From YhLu at tyan.com  Tue May 31 19:42:58 2005
From: YhLu at tyan.com (YhLu)
Date: Tue, 31 May 2005 10:42:58 -0700
Subject: [LinuxBIOS] Intel E7501 Northbridge head-scratching
Message-ID: <3174569B9743D511922F00A0C94314230A403724@TYANWEB>

It should be working. But I wonder some AMD check in about MTRR or CPU
initialization would break it.

YH 

> -----Original Message-----
> From: Li-Ta Lo [mailto:ollie at lanl.gov] 
> Sent: Tuesday, May 31, 2005 10:40 AM
> To: YhLu
> Cc: Steve Magnani; linuxbios at openbios.org
> Subject: RE: [LinuxBIOS] Intel E7501 Northbridge head-scratching
> 
> On Fri, 2005-05-27 at 10:03 -0700, YhLu wrote:
> > why still waste time on Intel platform? They will not support  
> > LinuxBIOS, because they have EFI....
> > 
> 
> BTW, is tyan s2735 code in the current tla tree working? We 
> tried to use it as a base for a supermicro board but failed.
> 
> --
> Li-Ta Lo <ollie at lanl.gov>
> Los Alamos National Lab
>